forked from TencentOS/TencentOS-kernel
[ Upstream commit df8e34ac27e8a0d8dce364628226c5619693c3fd ] [why] When combining two or more pipes in DSC mode, there will always be more than 1 slice per line. In this case, as per DSC rules, the sink device is expecting that the ICH is reset at the end of each slice line (i.e. ICH_RESET_AT_END_OF_LINE must be configured based on the number of slices at the output of ODM). It is recommended that software set ICH_RESET_AT_END_OF_LINE = 0xF for each DSC in the ODM combine. However the current code only set ICH_RESET_AT_END_OF_LINE = 0xF when number of slice per DSC engine is greater than 1 instead of number of slice per output after ODM combine. [how] Add is_odm in dsc config. Set ICH_RESET_AT_END_OF_LINE = 0xF if either is_odm or number of slice per DSC engine is greater than 1. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org> |
||
|---|---|---|
| .. | ||
| hw | ||
| bw_fixed.h | ||
| clock_source.h | ||
| compressor.h | ||
| core_status.h | ||
| core_types.h | ||
| custom_float.h | ||
| dc_link_ddc.h | ||
| dc_link_dp.h | ||
| dce_calcs.h | ||
| dcn_calc_math.h | ||
| dcn_calcs.h | ||
| hw_sequencer.h | ||
| link_hwss.h | ||
| reg_helper.h | ||
| resource.h | ||
| vm_helper.h | ||