forked from TencentOS/TencentOS-kernel
7bcb8ed9d5
commit 11a163f2c7d6a9f27ce144cd7e367a81c851621a upstream.
The previous code assumed that a higher hardware value always resulted
in a bigger divider, which is correct for the regular clocks, but is
an invalid assumption when a divider table is provided for the clock.
Perfect example of this is the PLL0_HALF clock, which applies a /2
divider with the hardware value 0, and a /1 divider otherwise.
Fixes: a9fa2893fcc6 ("clk: ingenic: Add support for divider tables")
Cc: <stable@vger.kernel.org> # 5.2
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| .. | ||
| Kconfig | ||
| Makefile | ||
| cgu.c | ||
| cgu.h | ||
| jz4725b-cgu.c | ||
| jz4740-cgu.c | ||
| jz4770-cgu.c | ||
| jz4780-cgu.c | ||
| pm.c | ||
| pm.h | ||
| tcu.c | ||