Merge pull request #235 from peaceforeverCN/master

kernel: config pci reset quirk by cmdline

drivers/pci/quirks.c

@@ -3817,6 +3817,150 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
 	return 0;
 }
 
+
+#define DEFAULT_PCI_RESET_WAIT_TIMEOUT 0
+#define MIN_PCI_RESET_WAIT_TIMEOUT DEFAULT_PCI_RESET_WAIT_TIMEOUT
+#define MAX_PCI_RESET_WAIT_TIMEOUT 4
+
+struct pci_reset_quirk_config {
+	unsigned short	vendor;
+	unsigned short	device;
+	union {   /* 4 bytes in size. */
+	    unsigned int timeout;
+	    unsigned int reserve;
+	};
+	int (*reset)(struct pci_dev *dev, struct pci_reset_quirk_config *cfg, int probe);
+};
+
+#define MAX_PCI_RESET_CONFIG_NUM 20
+static int pci_reset_quirk_config_num = 0;
+static struct pci_reset_quirk_config pci_reset_quirk_config[MAX_PCI_RESET_CONFIG_NUM] = {
+	{ 0 }
+};
+
+static int pci_reset_quirk_no_reset(struct pci_dev *dev, 
+		struct pci_reset_quirk_config *cfg, int probe)
+{
+	pci_info(dev, "do no reset the device\n");
+	return 0;
+}
+
+static void pci_no_reset_quirk_get_opt(char *str)
+{
+	unsigned short vid, did;
+	struct pci_reset_quirk_config *cfg;
+
+	while (str) {
+		char *k = strchr(str, ',');
+		if (k)
+			*k++ = 0;
+
+		if (str) {
+			vid = (unsigned short)simple_strtoul(str, &str, 16);
+			did = (unsigned short)simple_strtoul(str + 1, &str, 16);
+
+			cfg = &pci_reset_quirk_config[pci_reset_quirk_config_num++ % MAX_PCI_RESET_CONFIG_NUM];
+			cfg->vendor = vid;
+			cfg->device = did;
+			cfg->reserve = 0;
+			cfg->reset = pci_reset_quirk_no_reset;
+			pr_info("add no reset quirk success: %x:%x\n", vid, did);
+		}
+		str = k;
+	}
+}
+
+static int pci_reset_quirk_ssleep_after_sbr(struct pci_dev *dev, 
+		struct pci_reset_quirk_config *cfg, int probe)
+{
+	struct pci_dev *slot = dev->bus->self;
+	u16 reg, timeout = cfg->timeout;
+
+	if (probe)
+		return -ENOTTY;
+
+	if (!timeout)
+		return -ENOTTY;
+
+	pcie_capability_read_word(slot, PCI_EXP_SLTCTL, &reg);
+	reg &= (~PCI_EXP_SLTCTL_DLLSCE);
+	pcie_capability_write_word(slot, PCI_EXP_SLTCTL, reg);
+
+	pci_reset_secondary_bus(slot);
+
+	ssleep(timeout);
+
+	pcie_capability_write_word(slot, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_DLLSC);
+	pcie_capability_read_word(slot, PCI_EXP_SLTCTL, &reg);
+	reg |= PCI_EXP_SLTCTL_DLLSCE;
+	pcie_capability_write_word(slot, PCI_EXP_SLTCTL, reg);
+
+	pci_info(dev, "do sleep %ds after device reset\n", timeout);
+	return 0;
+}
+
+static void pci_reset_timeout_quirk_get_opt(char *str)
+{
+	unsigned short vid, did;
+	unsigned int t;
+	struct pci_reset_quirk_config *cfg;
+		
+	while (str) {
+		char *k = strchr(str, ',');
+		if (k)
+			*k++ = 0;
+
+		if (str) {
+			vid = (unsigned short)simple_strtoul(str, &str, 16);
+			did = (unsigned short)simple_strtoul(str + 1, &str, 16);
+			t = (unsigned int)simple_strtoul(str + 1, &str, 10);
+
+			if (t > MAX_PCI_RESET_WAIT_TIMEOUT	
+					|| t < MIN_PCI_RESET_WAIT_TIMEOUT)
+					t = MIN_PCI_RESET_WAIT_TIMEOUT;
+
+			cfg = &pci_reset_quirk_config[pci_reset_quirk_config_num++ % MAX_PCI_RESET_CONFIG_NUM];
+			cfg->vendor = vid;
+			cfg->device = did;
+			cfg->timeout = t;
+			cfg->reset = pci_reset_quirk_ssleep_after_sbr;
+			pr_info("add reset timeout quirk success: %x:%x timeout:%x\n", vid, did, t);
+		}
+		str = k;
+	}
+}
+
+/* 
+ * cmdline e.g.: pcireset_quirk=timeout,1ea0:2a16=4,1ea0:2a17=3 pcireset_quirk=noreset,1ea0:2a16,1ea0:2a17
+*/
+static int __init pci_reset_quirk_setup(char *str)
+{
+	if (!strncmp(str, "timeout,", 8)) {
+		pci_reset_timeout_quirk_get_opt(str + 8);
+	} else if (!strncmp(str, "noreset,", 8)) {
+		pci_no_reset_quirk_get_opt(str + 8);
+	} else {
+		pr_err("PCI: Unknown option in pcireset_quirk. '%s'\n", str);
+	}
+	return 0;
+}
+__setup("pcireset_quirk=", pci_reset_quirk_setup);
+
+static int pci_reset_quirk_cmdline(struct pci_dev *dev, int probe)
+{
+	int i;
+	struct pci_reset_quirk_config *cfg;
+
+	for (i = 0; i < pci_reset_quirk_config_num && i < MAX_PCI_RESET_CONFIG_NUM; i++){
+		cfg = &pci_reset_quirk_config[i];
+		if (cfg->vendor == dev->vendor &&
+			cfg->device == dev->device &&
+			cfg->reset)
+			return cfg->reset(dev, cfg, probe);
+	}
+	return -ENOTTY;
+}
+
 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF   0x10ed
 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA      0x0156
 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA     0x0166
@@ -3830,6 +3974,7 @@ static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
 		reset_ivb_igd },
 	{ PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
 		reset_chelsio_generic_dev },
+	{ PCI_ANY_ID, PCI_ANY_ID, pci_reset_quirk_cmdline },
 	{ 0 }
 };
 

kernel/sched/fair.c

@@ -5449,28 +5449,43 @@ static int wake_wide(struct task_struct *p)
  * soonest. For the purpose of speed we only consider the waking and previous
  * CPU.
  *
- * wake_affine_idle() - only considers 'now', it check if the waking CPU is (or
- *			will be) idle.
+ * wake_affine_idle() - only considers 'now', it check if the waking CPU is
+ * 			cache-affine and is (or will be) idle.
  *
  * wake_affine_weight() - considers the weight to reflect the average
  *			  scheduling latency of the CPUs. This seems to work
  *			  for the overloaded case.
  */
 
-static bool
+static int
 wake_affine_idle(struct sched_domain *sd, struct task_struct *p,
 		 int this_cpu, int prev_cpu, int sync)
 {
-	if (idle_cpu(this_cpu))
-		return true;
+	/*
+	 * If this_cpu is idle, it implies the wakeup is from interrupt
+	 * context. Only allow the move if cache is shared. Otherwise an
+	 * interrupt intensive workload could force all tasks onto one
+	 * node depending on the IO topology or IRQ affinity settings.
+	 *
+	 * If the prev_cpu is idle and cache affine then avoid a migration.
+	 * There is no guarantee that the cache hot data from an interrupt
+	 * is more important than cache hot data on the prev_cpu and from
+	 * a cpufreq perspective, it's better to have higher utilisation
+	 * on one CPU.
+	 */
+	if (idle_cpu(this_cpu) && cpus_share_cache(this_cpu, prev_cpu))
+		return idle_cpu(prev_cpu) ? prev_cpu : this_cpu;
 
 	if (sync && cpu_rq(this_cpu)->nr_running == 1)
-		return true;
+		return this_cpu;
 
-	return false;
+	if (idle_cpu(prev_cpu))
+		return prev_cpu;
+
+	return nr_cpumask_bits;
 }
 
-static bool
+static int
 wake_affine_weight(struct sched_domain *sd, struct task_struct *p,
 		   int this_cpu, int prev_cpu, int sync)
 {
@@ -5484,7 +5499,7 @@ wake_affine_weight(struct sched_domain *sd, struct task_struct *p,
 		unsigned long current_load = task_h_load(current);
 
 		if (current_load > this_eff_load)
-			return true;
+			return this_cpu;
 
 		this_eff_load -= current_load;
 	}
@@ -5501,7 +5516,16 @@ wake_affine_weight(struct sched_domain *sd, struct task_struct *p,
 		prev_eff_load *= 100 + (sd->imbalance_pct - 100) / 2;
 	prev_eff_load *= capacity_of(this_cpu);
 
-	return this_eff_load <= prev_eff_load;
+	/*
+	 * If sync, adjust the weight of prev_eff_load such that if
+	 * prev_eff == this_eff that select_idle_sibling() will consider
+	 * stacking the wakee on top of the waker if no other CPU is
+	 * idle.
+	 */
+	if (sync)
+		prev_eff_load += 1;
+
+	return this_eff_load < prev_eff_load ? this_cpu : nr_cpumask_bits;
 }
 
 static int wake_affine(struct sched_domain *sd, struct task_struct *p,
@@ -5509,14 +5533,17 @@ static int wake_affine(struct sched_domain *sd, struct task_struct *p,
 {
 	int this_cpu = smp_processor_id();
 	bool affine = false;
+	int target = nr_cpumask_bits;
 
-	if (sched_feat(WA_IDLE) && !affine)
-		affine = wake_affine_idle(sd, p, this_cpu, prev_cpu, sync);
+	if (sched_feat(WA_IDLE))
+		target = wake_affine_idle(sd, p, this_cpu, prev_cpu, sync);
 
-	if (sched_feat(WA_WEIGHT) && !affine)
-		affine = wake_affine_weight(sd, p, this_cpu, prev_cpu, sync);
+	if (sched_feat(WA_WEIGHT) && target == nr_cpumask_bits)
+		target = wake_affine_weight(sd, p, this_cpu, prev_cpu, sync);
 
 	schedstat_inc(p->se.statistics.nr_wakeups_affine_attempts);
+	if (target == this_cpu)
+		affine = true;
 	if (affine) {
 		schedstat_inc(sd->ttwu_move_affine);
 		schedstat_inc(p->se.statistics.nr_wakeups_affine);