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Author SHA1 Message Date
frankjpliu 6bd26b3101
Merge pull request #235 from peaceforeverCN/master
kernel: config pci reset quirk by cmdline
2022-08-08 15:07:26 +08:00
leolingli a88d1328fa kernel: config pci reset quirk by cmdline
[desc]:
can use cmdline in grub to:
  1). custom set sleep time after device reset.
      e.g. pcireset_quirk=timeout,vid1:did1=t1,vid2:did2=t2
      this will set t1 second sleep after vid1:did1 device reset and so do vid2:did2
      use to solve zixiao gpu reset problem.
  2). return 0 directly when device reset.
      e.g. pcireset_quirk=noreset,vid1:did1,vid2:did2
      this will return 0 when vid1:did1 device reset and so do vid2:did2
      use to solve 2080Ti & 3070 GPU reset cause ff problem.

Signed-off-by: leolingli <leolingli@tencent.com>
Signed-off-by: snailzhao <snailzhao@tencent.com>
2022-07-04 11:53:29 +08:00
yongduan 33347536c7 backport wake affine upstream optimization
[upstream]
7332dec0 sched/fair: Only immediately migrate tasks due to interrupts
         if prev and target CPUs share cache
806486c3 sched/fair: Do not migrate if the prev_cpu is idle
082f764a sched/fair: Do not migrate on wake_affine_weight() if weights
         are equal
d8fcb81f sched/fair: Check for idle core in wake_affine

Signed-off-by: yongduan <yongduan@tencent.com>
2021-03-17 08:58:32 +00:00
8 changed files with 561 additions and 1957 deletions

View File

@ -3817,6 +3817,150 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
return 0;
}
#define DEFAULT_PCI_RESET_WAIT_TIMEOUT 0
#define MIN_PCI_RESET_WAIT_TIMEOUT DEFAULT_PCI_RESET_WAIT_TIMEOUT
#define MAX_PCI_RESET_WAIT_TIMEOUT 4
struct pci_reset_quirk_config {
unsigned short vendor;
unsigned short device;
union { /* 4 bytes in size. */
unsigned int timeout;
unsigned int reserve;
};
int (*reset)(struct pci_dev *dev, struct pci_reset_quirk_config *cfg, int probe);
};
#define MAX_PCI_RESET_CONFIG_NUM 20
static int pci_reset_quirk_config_num = 0;
static struct pci_reset_quirk_config pci_reset_quirk_config[MAX_PCI_RESET_CONFIG_NUM] = {
{ 0 }
};
static int pci_reset_quirk_no_reset(struct pci_dev *dev,
struct pci_reset_quirk_config *cfg, int probe)
{
pci_info(dev, "do no reset the device\n");
return 0;
}
static void pci_no_reset_quirk_get_opt(char *str)
{
unsigned short vid, did;
struct pci_reset_quirk_config *cfg;
while (str) {
char *k = strchr(str, ',');
if (k)
*k++ = 0;
if (str) {
vid = (unsigned short)simple_strtoul(str, &str, 16);
did = (unsigned short)simple_strtoul(str + 1, &str, 16);
cfg = &pci_reset_quirk_config[pci_reset_quirk_config_num++ % MAX_PCI_RESET_CONFIG_NUM];
cfg->vendor = vid;
cfg->device = did;
cfg->reserve = 0;
cfg->reset = pci_reset_quirk_no_reset;
pr_info("add no reset quirk success: %x:%x\n", vid, did);
}
str = k;
}
}
static int pci_reset_quirk_ssleep_after_sbr(struct pci_dev *dev,
struct pci_reset_quirk_config *cfg, int probe)
{
struct pci_dev *slot = dev->bus->self;
u16 reg, timeout = cfg->timeout;
if (probe)
return -ENOTTY;
if (!timeout)
return -ENOTTY;
pcie_capability_read_word(slot, PCI_EXP_SLTCTL, &reg);
reg &= (~PCI_EXP_SLTCTL_DLLSCE);
pcie_capability_write_word(slot, PCI_EXP_SLTCTL, reg);
pci_reset_secondary_bus(slot);
ssleep(timeout);
pcie_capability_write_word(slot, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_DLLSC);
pcie_capability_read_word(slot, PCI_EXP_SLTCTL, &reg);
reg |= PCI_EXP_SLTCTL_DLLSCE;
pcie_capability_write_word(slot, PCI_EXP_SLTCTL, reg);
pci_info(dev, "do sleep %ds after device reset\n", timeout);
return 0;
}
static void pci_reset_timeout_quirk_get_opt(char *str)
{
unsigned short vid, did;
unsigned int t;
struct pci_reset_quirk_config *cfg;
while (str) {
char *k = strchr(str, ',');
if (k)
*k++ = 0;
if (str) {
vid = (unsigned short)simple_strtoul(str, &str, 16);
did = (unsigned short)simple_strtoul(str + 1, &str, 16);
t = (unsigned int)simple_strtoul(str + 1, &str, 10);
if (t > MAX_PCI_RESET_WAIT_TIMEOUT
|| t < MIN_PCI_RESET_WAIT_TIMEOUT)
t = MIN_PCI_RESET_WAIT_TIMEOUT;
cfg = &pci_reset_quirk_config[pci_reset_quirk_config_num++ % MAX_PCI_RESET_CONFIG_NUM];
cfg->vendor = vid;
cfg->device = did;
cfg->timeout = t;
cfg->reset = pci_reset_quirk_ssleep_after_sbr;
pr_info("add reset timeout quirk success: %x:%x timeout:%x\n", vid, did, t);
}
str = k;
}
}
/*
* cmdline e.g.: pcireset_quirk=timeout,1ea0:2a16=4,1ea0:2a17=3 pcireset_quirk=noreset,1ea0:2a16,1ea0:2a17
*/
static int __init pci_reset_quirk_setup(char *str)
{
if (!strncmp(str, "timeout,", 8)) {
pci_reset_timeout_quirk_get_opt(str + 8);
} else if (!strncmp(str, "noreset,", 8)) {
pci_no_reset_quirk_get_opt(str + 8);
} else {
pr_err("PCI: Unknown option in pcireset_quirk. '%s'\n", str);
}
return 0;
}
__setup("pcireset_quirk=", pci_reset_quirk_setup);
static int pci_reset_quirk_cmdline(struct pci_dev *dev, int probe)
{
int i;
struct pci_reset_quirk_config *cfg;
for (i = 0; i < pci_reset_quirk_config_num && i < MAX_PCI_RESET_CONFIG_NUM; i++){
cfg = &pci_reset_quirk_config[i];
if (cfg->vendor == dev->vendor &&
cfg->device == dev->device &&
cfg->reset)
return cfg->reset(dev, cfg, probe);
}
return -ENOTTY;
}
#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
@ -3830,6 +3974,7 @@ static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
reset_ivb_igd },
{ PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
reset_chelsio_generic_dev },
{ PCI_ANY_ID, PCI_ANY_ID, pci_reset_quirk_cmdline },
{ 0 }
};

View File

@ -21,9 +21,6 @@
#if !defined(_SMARTPQI_H)
#define _SMARTPQI_H
#include <scsi/scsi_host.h>
#include <linux/bsg-lib.h>
#pragma pack(1)
#define PQI_DEVICE_SIGNATURE "PQI DREG"
@ -100,12 +97,6 @@ struct pqi_ctrl_registers {
struct pqi_device_registers pqi_registers; /* 4000h */
};
#if ((HZ) < 1000)
#define PQI_HZ 1000
#else
#define PQI_HZ (HZ)
#endif
#define PQI_DEVICE_REGISTERS_OFFSET 0x4000
enum pqi_io_path {
@ -356,10 +347,6 @@ struct pqi_event_config {
#define PQI_MAX_EVENT_DESCRIPTORS 255
#define PQI_EVENT_OFA_MEMORY_ALLOCATION 0x0
#define PQI_EVENT_OFA_QUIESCE 0x1
#define PQI_EVENT_OFA_CANCELLED 0x2
struct pqi_event_response {
struct pqi_iu_header header;
u8 event_type;
@ -367,17 +354,7 @@ struct pqi_event_response {
u8 request_acknowlege : 1;
__le16 event_id;
__le32 additional_event_id;
union {
struct {
__le32 bytes_requested;
u8 reserved[12];
} ofa_memory_allocation;
struct {
__le16 reason; /* reason for cancellation */
u8 reserved[14];
} ofa_cancelled;
} data;
u8 data[16];
};
struct pqi_event_acknowledge_request {
@ -412,54 +389,6 @@ struct pqi_task_management_response {
u8 response_code;
};
struct pqi_vendor_general_request {
struct pqi_iu_header header;
__le16 request_id;
__le16 function_code;
union {
struct {
__le16 first_section;
__le16 last_section;
u8 reserved[48];
} config_table_update;
struct {
__le64 buffer_address;
__le32 buffer_length;
u8 reserved[40];
} ofa_memory_allocation;
} data;
};
struct pqi_vendor_general_response {
struct pqi_iu_header header;
__le16 request_id;
__le16 function_code;
__le16 status;
u8 reserved[2];
};
#define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0
#define PQI_VENDOR_GENERAL_HOST_MEMORY_UPDATE 1
#define PQI_OFA_VERSION 1
#define PQI_OFA_SIGNATURE "OFA_QRM"
#define PQI_OFA_MAX_SG_DESCRIPTORS 64
#define PQI_OFA_MEMORY_DESCRIPTOR_LENGTH \
(offsetof(struct pqi_ofa_memory, sg_descriptor) + \
(PQI_OFA_MAX_SG_DESCRIPTORS * sizeof(struct pqi_sg_descriptor)))
struct pqi_ofa_memory {
__le64 signature; /* "OFA_QRM" */
__le16 version; /* version of this struct(1 = 1st version) */
u8 reserved[62];
__le32 bytes_allocated; /* total allocated memory in bytes */
__le16 num_memory_descriptors;
u8 reserved1[2];
struct pqi_sg_descriptor sg_descriptor[1];
};
struct pqi_aio_error_info {
u8 status;
u8 service_response;
@ -490,7 +419,6 @@ struct pqi_raid_error_info {
#define PQI_REQUEST_IU_GENERAL_ADMIN 0x60
#define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72
#define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73
#define PQI_REQUEST_IU_VENDOR_GENERAL 0x75
#define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6
#define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81
@ -502,7 +430,6 @@ struct pqi_raid_error_info {
#define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3
#define PQI_RESPONSE_IU_AIO_PATH_DISABLED 0xf4
#define PQI_RESPONSE_IU_VENDOR_EVENT 0xf5
#define PQI_RESPONSE_IU_VENDOR_GENERAL 0xf7
#define PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY 0x0
#define PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ 0x10
@ -556,8 +483,6 @@ struct pqi_raid_error_info {
#define CISS_CMD_STATUS_TMF 0xd
#define CISS_CMD_STATUS_AIO_DISABLED 0xe
#define PQI_CMD_STATUS_ABORTED CISS_CMD_STATUS_ABORTED
#define PQI_NUM_EVENT_QUEUE_ELEMENTS 32
#define PQI_EVENT_OQ_ELEMENT_LENGTH sizeof(struct pqi_event_response)
@ -565,7 +490,6 @@ struct pqi_raid_error_info {
#define PQI_EVENT_TYPE_HARDWARE 0x2
#define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4
#define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5
#define PQI_EVENT_TYPE_OFA 0xfb
#define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd
#define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe
@ -630,7 +554,6 @@ typedef u32 pqi_index_t;
#define SOP_TASK_ATTRIBUTE_ACA 4
#define SOP_TMF_COMPLETE 0x0
#define SOP_TMF_REJECTED 0x4
#define SOP_TMF_FUNCTION_SUCCEEDED 0x8
/* additional CDB bytes usage field codes */
@ -658,8 +581,8 @@ struct pqi_admin_queues_aligned {
struct pqi_admin_queues {
void *iq_element_array;
void *oq_element_array;
pqi_index_t *iq_ci;
pqi_index_t __iomem *oq_pi;
volatile pqi_index_t *iq_ci;
volatile pqi_index_t *oq_pi;
dma_addr_t iq_element_array_bus_addr;
dma_addr_t oq_element_array_bus_addr;
dma_addr_t iq_ci_bus_addr;
@ -683,8 +606,8 @@ struct pqi_queue_group {
dma_addr_t oq_element_array_bus_addr;
__le32 __iomem *iq_pi[2];
pqi_index_t iq_pi_copy[2];
pqi_index_t __iomem *iq_ci[2];
pqi_index_t __iomem *oq_pi;
volatile pqi_index_t *iq_ci[2];
volatile pqi_index_t *oq_pi;
dma_addr_t iq_ci_bus_addr[2];
dma_addr_t oq_pi_bus_addr;
__le32 __iomem *oq_ci;
@ -697,7 +620,7 @@ struct pqi_event_queue {
u16 oq_id;
u16 int_msg_num;
void *oq_element_array;
pqi_index_t __iomem *oq_pi;
volatile pqi_index_t *oq_pi;
dma_addr_t oq_element_array_bus_addr;
dma_addr_t oq_pi_bus_addr;
__le32 __iomem *oq_ci;
@ -719,13 +642,11 @@ struct pqi_encryption_info {
#define PQI_CONFIG_TABLE_MAX_LENGTH ((u16)~0)
/* configuration table section IDs */
#define PQI_CONFIG_TABLE_ALL_SECTIONS (-1)
#define PQI_CONFIG_TABLE_SECTION_GENERAL_INFO 0
#define PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES 1
#define PQI_CONFIG_TABLE_SECTION_FIRMWARE_ERRATA 2
#define PQI_CONFIG_TABLE_SECTION_DEBUG 3
#define PQI_CONFIG_TABLE_SECTION_HEARTBEAT 4
#define PQI_CONFIG_TABLE_SECTION_SOFT_RESET 5
struct pqi_config_table {
u8 signature[8]; /* "CFGTABLE" */
@ -757,18 +678,6 @@ struct pqi_config_table_general_info {
/* command */
};
struct pqi_config_table_firmware_features {
struct pqi_config_table_section_header header;
__le16 num_elements;
u8 features_supported[];
/* u8 features_requested_by_host[]; */
/* u8 features_enabled[]; */
};
#define PQI_FIRMWARE_FEATURE_OFA 0
#define PQI_FIRMWARE_FEATURE_SMP 1
#define PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE 11
struct pqi_config_table_debug {
struct pqi_config_table_section_header header;
__le32 scratchpad;
@ -779,22 +688,6 @@ struct pqi_config_table_heartbeat {
__le32 heartbeat_counter;
};
struct pqi_config_table_soft_reset {
struct pqi_config_table_section_header header;
u8 soft_reset_status;
};
#define PQI_SOFT_RESET_INITIATE 0x1
#define PQI_SOFT_RESET_ABORT 0x2
enum pqi_soft_reset_status {
RESET_INITIATE_FIRMWARE,
RESET_INITIATE_DRIVER,
RESET_ABORT,
RESET_NORESPONSE,
RESET_TIMEDOUT
};
union pqi_reset_register {
struct {
u32 reset_type : 3;
@ -913,10 +806,8 @@ struct pqi_scsi_dev {
u8 scsi3addr[8];
__be64 wwid;
u8 volume_id[16];
u8 unique_id[16];
u8 is_physical_device : 1;
u8 is_external_raid_device : 1;
u8 is_expander_smp_device : 1;
u8 target_lun_valid : 1;
u8 device_gone : 1;
u8 new_device : 1;
@ -924,7 +815,6 @@ struct pqi_scsi_dev {
u8 volume_offline : 1;
bool aio_enabled; /* only valid for physical disks */
bool in_reset;
bool in_remove;
bool device_offline;
u8 vendor[8]; /* bytes 8-15 of inquiry data */
u8 model[16]; /* bytes 16-31 of inquiry data */
@ -962,8 +852,6 @@ struct pqi_scsi_dev {
#define CISS_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */
#define CISS_VPD_LV_BYPASS_STATUS 0xc2 /* vendor-specific page */
#define CISS_VPD_LV_STATUS 0xc3 /* vendor-specific page */
#define SCSI_VPD_HEADER_SZ 4
#define SCSI_VPD_DEVICE_ID_IDX 8 /* Index of page id in page */
#define VPD_PAGE (1 << 8)
@ -1026,7 +914,6 @@ struct pqi_sas_node {
struct pqi_sas_port {
struct list_head port_list_entry;
u64 sas_address;
struct pqi_scsi_dev *device;
struct sas_port *port;
int next_phy_index;
struct list_head phy_list_head;
@ -1058,15 +945,13 @@ struct pqi_io_request {
struct list_head request_list_entry;
};
#define PQI_NUM_SUPPORTED_EVENTS 7
#define PQI_NUM_SUPPORTED_EVENTS 6
struct pqi_event {
bool pending;
u8 event_type;
__le16 event_id;
__le32 additional_event_id;
__le32 ofa_bytes_requested;
__le16 ofa_cancel_reason;
};
#define PQI_RESERVED_IO_SLOTS_LUN_RESET 1
@ -1127,16 +1012,12 @@ struct pqi_ctrl_info {
struct mutex scan_mutex;
struct mutex lun_reset_mutex;
struct mutex ofa_mutex; /* serialize ofa */
bool controller_online;
bool block_requests;
bool in_shutdown;
bool in_ofa;
u8 inbound_spanning_supported : 1;
u8 outbound_spanning_supported : 1;
u8 pqi_mode_enabled : 1;
u8 pqi_reset_quiesce_supported : 1;
u8 soft_reset_handshake_supported : 1;
struct list_head scsi_device_list;
spinlock_t scsi_device_list_lock;
@ -1157,7 +1038,6 @@ struct pqi_ctrl_info {
int previous_num_interrupts;
u32 previous_heartbeat_count;
__le32 __iomem *heartbeat_counter;
u8 __iomem *soft_reset_status;
struct timer_list heartbeat_timer;
struct work_struct ctrl_offline_work;
@ -1169,10 +1049,6 @@ struct pqi_ctrl_info {
struct list_head raid_bypass_retry_list;
spinlock_t raid_bypass_retry_list_lock;
struct work_struct raid_bypass_retry_work;
struct pqi_ofa_memory *pqi_ofa_mem_virt_addr;
dma_addr_t pqi_ofa_mem_dma_handle;
void **pqi_ofa_chunk_virt_addr;
};
enum pqi_ctrl_mode {
@ -1202,13 +1078,8 @@ enum pqi_ctrl_mode {
#define BMIC_WRITE 0x27
#define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64
#define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66
#define BMIC_CSMI_PASSTHRU 0x68
#define BMIC_WRITE_HOST_WELLNESS 0xa5
#define BMIC_FLUSH_CACHE 0xc2
#define BMIC_SET_DIAG_OPTIONS 0xf4
#define BMIC_SENSE_DIAG_OPTIONS 0xf5
#define CSMI_CC_SAS_SMP_PASSTHRU 0X17
#define SA_FLUSH_CACHE 0x1
@ -1236,10 +1107,6 @@ struct bmic_identify_controller {
u8 reserved3[32];
};
#define SA_EXPANDER_SMP_DEVICE 0x05
/*SCSI Invalid Device Type for SAS devices*/
#define PQI_SAS_SCSI_INVALID_DEVTYPE 0xff
struct bmic_identify_physical_device {
u8 scsi_bus; /* SCSI Bus number on controller */
u8 scsi_id; /* SCSI ID on this bus */
@ -1320,50 +1187,6 @@ struct bmic_identify_physical_device {
u8 padding_to_multiple_of_512[9];
};
struct bmic_smp_request {
u8 frame_type;
u8 function;
u8 allocated_response_length;
u8 request_length;
u8 additional_request_bytes[1016];
};
struct bmic_smp_response {
u8 frame_type;
u8 function;
u8 function_result;
u8 response_length;
u8 additional_response_bytes[1016];
};
struct bmic_csmi_ioctl_header {
__le32 header_length;
u8 signature[8];
__le32 timeout;
__le32 control_code;
__le32 return_code;
__le32 length;
};
struct bmic_csmi_smp_passthru {
u8 phy_identifier;
u8 port_identifier;
u8 connection_rate;
u8 reserved;
__be64 destination_sas_address;
__le32 request_length;
struct bmic_smp_request request;
u8 connection_status;
u8 reserved1[3];
__le32 response_length;
struct bmic_smp_response response;
};
struct bmic_csmi_smp_passthru_buffer {
struct bmic_csmi_ioctl_header ioctl_header;
struct bmic_csmi_smp_passthru parameters;
};
struct bmic_flush_cache {
u8 disable_flag;
u8 system_power_action;
@ -1381,42 +1204,8 @@ enum bmic_flush_cache_shutdown_event {
RESTART = 4
};
struct bmic_diag_options {
__le32 options;
};
#pragma pack()
static inline struct pqi_ctrl_info *shost_to_hba(struct Scsi_Host *shost)
{
void *hostdata = shost_priv(shost);
return *((struct pqi_ctrl_info **)hostdata);
}
static inline bool pqi_ctrl_offline(struct pqi_ctrl_info *ctrl_info)
{
return !ctrl_info->controller_online;
}
static inline void pqi_ctrl_busy(struct pqi_ctrl_info *ctrl_info)
{
atomic_inc(&ctrl_info->num_busy_threads);
}
static inline void pqi_ctrl_unbusy(struct pqi_ctrl_info *ctrl_info)
{
atomic_dec(&ctrl_info->num_busy_threads);
}
static inline bool pqi_ctrl_blocked(struct pqi_ctrl_info *ctrl_info)
{
return ctrl_info->block_requests;
}
void pqi_sas_smp_handler(struct bsg_job *job, struct Scsi_Host *shost,
struct sas_rphy *rphy);
int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info);
void pqi_delete_sas_host(struct pqi_ctrl_info *ctrl_info);
int pqi_add_sas_device(struct pqi_sas_node *pqi_sas_node,
@ -1425,9 +1214,6 @@ void pqi_remove_sas_device(struct pqi_scsi_dev *device);
struct pqi_scsi_dev *pqi_find_device_by_sas_rphy(
struct pqi_ctrl_info *ctrl_info, struct sas_rphy *rphy);
void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd);
int pqi_csmi_smp_passthru(struct pqi_ctrl_info *ctrl_info,
struct bmic_csmi_smp_passthru_buffer *buffer, size_t buffer_length,
struct pqi_raid_error_info *error_info);
extern struct sas_function_template pqi_sas_transport_functions;

File diff suppressed because it is too large Load Diff

View File

@ -17,11 +17,9 @@
*/
#include <linux/kernel.h>
#include <linux/bsg-lib.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_transport_sas.h>
#include <asm/unaligned.h>
#include "smartpqi.h"
static struct pqi_sas_phy *pqi_alloc_sas_phy(struct pqi_sas_port *pqi_sas_port)
@ -99,32 +97,14 @@ static int pqi_sas_port_add_rphy(struct pqi_sas_port *pqi_sas_port,
identify = &rphy->identify;
identify->sas_address = pqi_sas_port->sas_address;
if (pqi_sas_port->device &&
pqi_sas_port->device->is_expander_smp_device) {
identify->initiator_port_protocols = SAS_PROTOCOL_SMP;
identify->target_port_protocols = SAS_PROTOCOL_SMP;
} else {
identify->initiator_port_protocols = SAS_PROTOCOL_STP;
identify->target_port_protocols = SAS_PROTOCOL_STP;
}
identify->initiator_port_protocols = SAS_PROTOCOL_STP;
identify->target_port_protocols = SAS_PROTOCOL_STP;
return sas_rphy_add(rphy);
}
static struct sas_rphy *pqi_sas_rphy_alloc(struct pqi_sas_port *pqi_sas_port)
{
if (pqi_sas_port->device &&
pqi_sas_port->device->is_expander_smp_device)
return sas_expander_alloc(pqi_sas_port->port,
SAS_FANOUT_EXPANDER_DEVICE);
return sas_end_device_alloc(pqi_sas_port->port);
}
static struct pqi_sas_port *pqi_alloc_sas_port(
struct pqi_sas_node *pqi_sas_node, u64 sas_address,
struct pqi_scsi_dev *device)
struct pqi_sas_node *pqi_sas_node, u64 sas_address)
{
int rc;
struct pqi_sas_port *pqi_sas_port;
@ -147,7 +127,6 @@ static struct pqi_sas_port *pqi_alloc_sas_port(
pqi_sas_port->port = port;
pqi_sas_port->sas_address = sas_address;
pqi_sas_port->device = device;
list_add_tail(&pqi_sas_port->port_list_entry,
&pqi_sas_node->port_list_head);
@ -167,7 +146,7 @@ static void pqi_free_sas_port(struct pqi_sas_port *pqi_sas_port)
struct pqi_sas_phy *next;
list_for_each_entry_safe(pqi_sas_phy, next,
&pqi_sas_port->phy_list_head, phy_list_entry)
&pqi_sas_port->phy_list_head, phy_list_entry)
pqi_free_sas_phy(pqi_sas_phy);
sas_port_delete(pqi_sas_port->port);
@ -197,7 +176,7 @@ static void pqi_free_sas_node(struct pqi_sas_node *pqi_sas_node)
return;
list_for_each_entry_safe(pqi_sas_port, next,
&pqi_sas_node->port_list_head, port_list_entry)
&pqi_sas_node->port_list_head, port_list_entry)
pqi_free_sas_port(pqi_sas_port);
kfree(pqi_sas_node);
@ -227,14 +206,13 @@ int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info)
struct pqi_sas_port *pqi_sas_port;
struct pqi_sas_phy *pqi_sas_phy;
parent_dev = &shost->shost_dev;
parent_dev = &shost->shost_gendev;
pqi_sas_node = pqi_alloc_sas_node(parent_dev);
if (!pqi_sas_node)
return -ENOMEM;
pqi_sas_port = pqi_alloc_sas_port(pqi_sas_node,
ctrl_info->sas_address, NULL);
pqi_sas_port = pqi_alloc_sas_port(pqi_sas_node, ctrl_info->sas_address);
if (!pqi_sas_port) {
rc = -ENODEV;
goto free_sas_node;
@ -276,12 +254,11 @@ int pqi_add_sas_device(struct pqi_sas_node *pqi_sas_node,
struct pqi_sas_port *pqi_sas_port;
struct sas_rphy *rphy;
pqi_sas_port = pqi_alloc_sas_port(pqi_sas_node,
device->sas_address, device);
pqi_sas_port = pqi_alloc_sas_port(pqi_sas_node, device->sas_address);
if (!pqi_sas_port)
return -ENOMEM;
rphy = pqi_sas_rphy_alloc(pqi_sas_port);
rphy = sas_end_device_alloc(pqi_sas_port->port);
if (!rphy) {
rc = -ENODEV;
goto free_sas_port;
@ -352,128 +329,6 @@ static int pqi_sas_phy_speed(struct sas_phy *phy,
return -EINVAL;
}
#define CSMI_IOCTL_TIMEOUT 60
#define SMP_CRC_FIELD_LENGTH 4
static struct bmic_csmi_smp_passthru_buffer *
pqi_build_csmi_smp_passthru_buffer(struct sas_rphy *rphy,
struct bsg_job *job)
{
struct bmic_csmi_smp_passthru_buffer *smp_buf;
struct bmic_csmi_ioctl_header *ioctl_header;
struct bmic_csmi_smp_passthru *parameters;
u32 req_size;
u32 resp_size;
smp_buf = kzalloc(sizeof(*smp_buf), GFP_KERNEL);
if (!smp_buf)
return NULL;
req_size = job->request_payload.payload_len;
resp_size = job->reply_payload.payload_len;
ioctl_header = &smp_buf->ioctl_header;
put_unaligned_le32(sizeof(smp_buf->ioctl_header),
&ioctl_header->header_length);
put_unaligned_le32(CSMI_IOCTL_TIMEOUT, &ioctl_header->timeout);
put_unaligned_le32(CSMI_CC_SAS_SMP_PASSTHRU,
&ioctl_header->control_code);
put_unaligned_le32(sizeof(smp_buf->parameters), &ioctl_header->length);
parameters = &smp_buf->parameters;
parameters->phy_identifier = rphy->identify.phy_identifier;
parameters->port_identifier = 0;
parameters->connection_rate = 0;
put_unaligned_be64(rphy->identify.sas_address,
&parameters->destination_sas_address);
if (req_size > SMP_CRC_FIELD_LENGTH)
req_size -= SMP_CRC_FIELD_LENGTH;
put_unaligned_le32(req_size, &parameters->request_length);
put_unaligned_le32(resp_size, &parameters->response_length);
sg_copy_to_buffer(job->request_payload.sg_list,
job->reply_payload.sg_cnt, &parameters->request,
req_size);
return smp_buf;
}
static unsigned int pqi_build_sas_smp_handler_reply(
struct bmic_csmi_smp_passthru_buffer *smp_buf, struct bsg_job *job,
struct pqi_raid_error_info *error_info)
{
sg_copy_from_buffer(job->reply_payload.sg_list,
job->reply_payload.sg_cnt, &smp_buf->parameters.response,
le32_to_cpu(smp_buf->parameters.response_length));
job->reply_len = le16_to_cpu(error_info->sense_data_length);
memcpy(job->reply, error_info->data,
le16_to_cpu(error_info->sense_data_length));
return job->reply_payload.payload_len -
get_unaligned_le32(&error_info->data_in_transferred);
}
void pqi_sas_smp_handler(struct bsg_job *job, struct Scsi_Host *shost,
struct sas_rphy *rphy)
{
int rc;
struct pqi_ctrl_info *ctrl_info = shost_to_hba(shost);
struct bmic_csmi_smp_passthru_buffer *smp_buf;
struct pqi_raid_error_info error_info;
unsigned int reslen = 0;
pqi_ctrl_busy(ctrl_info);
if (job->reply_payload.payload_len == 0) {
rc = -ENOMEM;
goto out;
}
if (!rphy) {
rc = -EINVAL;
goto out;
}
if (rphy->identify.device_type != SAS_FANOUT_EXPANDER_DEVICE) {
rc = -EINVAL;
goto out;
}
if (job->request_payload.sg_cnt > 1 || job->reply_payload.sg_cnt > 1) {
rc = -EINVAL;
goto out;
}
if (pqi_ctrl_offline(ctrl_info)) {
rc = -ENXIO;
goto out;
}
if (pqi_ctrl_blocked(ctrl_info)) {
rc = -EBUSY;
goto out;
}
smp_buf = pqi_build_csmi_smp_passthru_buffer(rphy, job);
if (!smp_buf) {
rc = -ENOMEM;
goto out;
}
rc = pqi_csmi_smp_passthru(ctrl_info, smp_buf, sizeof(*smp_buf),
&error_info);
if (rc)
goto out;
reslen = pqi_build_sas_smp_handler_reply(smp_buf, job, &error_info);
out:
bsg_job_done(job, rc, reslen);
pqi_ctrl_unbusy(ctrl_info);
}
struct sas_function_template pqi_sas_transport_functions = {
.get_linkerrors = pqi_sas_get_linkerrors,
.get_enclosure_identifier = pqi_sas_get_enclosure_identifier,
@ -483,5 +338,4 @@ struct sas_function_template pqi_sas_transport_functions = {
.phy_setup = pqi_sas_phy_setup,
.phy_release = pqi_sas_phy_release,
.set_phy_speed = pqi_sas_phy_speed,
.smp_handler = pqi_sas_smp_handler,
};

View File

@ -34,7 +34,6 @@
#define SIS_REENABLE_SIS_MODE 0x1
#define SIS_ENABLE_MSIX 0x40
#define SIS_ENABLE_INTX 0x80
#define SIS_SOFT_RESET 0x100
#define SIS_CMD_READY 0x200
#define SIS_TRIGGER_SHUTDOWN 0x800000
#define SIS_PQI_RESET_QUIESCE 0x1000000
@ -91,7 +90,7 @@ static int sis_wait_for_ctrl_ready_with_timeout(struct pqi_ctrl_info *ctrl_info,
unsigned long timeout;
u32 status;
timeout = (timeout_secs * PQI_HZ) + jiffies;
timeout = (timeout_secs * HZ) + jiffies;
while (1) {
status = readl(&ctrl_info->registers->sis_firmware_status);
@ -203,7 +202,7 @@ static int sis_send_sync_cmd(struct pqi_ctrl_info *ctrl_info,
* the top of the loop in order to give the controller time to start
* processing the command before we start polling.
*/
timeout = (SIS_CMD_COMPLETE_TIMEOUT_SECS * PQI_HZ) + jiffies;
timeout = (SIS_CMD_COMPLETE_TIMEOUT_SECS * HZ) + jiffies;
while (1) {
msleep(SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS);
doorbell = readl(&registers->sis_ctrl_to_host_doorbell);
@ -317,9 +316,9 @@ int sis_init_base_struct_addr(struct pqi_ctrl_info *ctrl_info)
put_unaligned_le32(ctrl_info->max_io_slots,
&base_struct->error_buffer_num_elements);
bus_address = dma_map_single(&ctrl_info->pci_dev->dev, base_struct,
sizeof(*base_struct), DMA_TO_DEVICE);
if (dma_mapping_error(&ctrl_info->pci_dev->dev, bus_address)) {
bus_address = pci_map_single(ctrl_info->pci_dev, base_struct,
sizeof(*base_struct), PCI_DMA_TODEVICE);
if (pci_dma_mapping_error(ctrl_info->pci_dev, bus_address)) {
rc = -ENOMEM;
goto out;
}
@ -332,8 +331,9 @@ int sis_init_base_struct_addr(struct pqi_ctrl_info *ctrl_info)
rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_INIT_BASE_STRUCT_ADDRESS,
&params);
dma_unmap_single(&ctrl_info->pci_dev->dev, bus_address,
sizeof(*base_struct), DMA_TO_DEVICE);
pci_unmap_single(ctrl_info->pci_dev, bus_address, sizeof(*base_struct),
PCI_DMA_TODEVICE);
out:
kfree(base_struct_unaligned);
@ -349,7 +349,7 @@ static int sis_wait_for_doorbell_bit_to_clear(
u32 doorbell_register;
unsigned long timeout;
timeout = (SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS * PQI_HZ) + jiffies;
timeout = (SIS_DOORBELL_BIT_CLEAR_TIMEOUT_SECS * HZ) + jiffies;
while (1) {
doorbell_register =
@ -421,12 +421,6 @@ u32 sis_read_driver_scratch(struct pqi_ctrl_info *ctrl_info)
return readl(&ctrl_info->registers->sis_driver_scratch);
}
void sis_soft_reset(struct pqi_ctrl_info *ctrl_info)
{
writel(SIS_SOFT_RESET,
&ctrl_info->registers->sis_host_to_ctrl_doorbell);
}
static void __attribute__((unused)) verify_structures(void)
{
BUILD_BUG_ON(offsetof(struct sis_base_struct,

View File

@ -33,6 +33,5 @@ int sis_pqi_reset_quiesce(struct pqi_ctrl_info *ctrl_info);
int sis_reenable_sis_mode(struct pqi_ctrl_info *ctrl_info);
void sis_write_driver_scratch(struct pqi_ctrl_info *ctrl_info, u32 value);
u32 sis_read_driver_scratch(struct pqi_ctrl_info *ctrl_info);
void sis_soft_reset(struct pqi_ctrl_info *ctrl_info);
#endif /* _SMARTPQI_SIS_H */

View File

@ -5449,28 +5449,43 @@ static int wake_wide(struct task_struct *p)
* soonest. For the purpose of speed we only consider the waking and previous
* CPU.
*
* wake_affine_idle() - only considers 'now', it check if the waking CPU is (or
* will be) idle.
* wake_affine_idle() - only considers 'now', it check if the waking CPU is
* cache-affine and is (or will be) idle.
*
* wake_affine_weight() - considers the weight to reflect the average
* scheduling latency of the CPUs. This seems to work
* for the overloaded case.
*/
static bool
static int
wake_affine_idle(struct sched_domain *sd, struct task_struct *p,
int this_cpu, int prev_cpu, int sync)
{
if (idle_cpu(this_cpu))
return true;
/*
* If this_cpu is idle, it implies the wakeup is from interrupt
* context. Only allow the move if cache is shared. Otherwise an
* interrupt intensive workload could force all tasks onto one
* node depending on the IO topology or IRQ affinity settings.
*
* If the prev_cpu is idle and cache affine then avoid a migration.
* There is no guarantee that the cache hot data from an interrupt
* is more important than cache hot data on the prev_cpu and from
* a cpufreq perspective, it's better to have higher utilisation
* on one CPU.
*/
if (idle_cpu(this_cpu) && cpus_share_cache(this_cpu, prev_cpu))
return idle_cpu(prev_cpu) ? prev_cpu : this_cpu;
if (sync && cpu_rq(this_cpu)->nr_running == 1)
return true;
return this_cpu;
return false;
if (idle_cpu(prev_cpu))
return prev_cpu;
return nr_cpumask_bits;
}
static bool
static int
wake_affine_weight(struct sched_domain *sd, struct task_struct *p,
int this_cpu, int prev_cpu, int sync)
{
@ -5484,7 +5499,7 @@ wake_affine_weight(struct sched_domain *sd, struct task_struct *p,
unsigned long current_load = task_h_load(current);
if (current_load > this_eff_load)
return true;
return this_cpu;
this_eff_load -= current_load;
}
@ -5501,7 +5516,16 @@ wake_affine_weight(struct sched_domain *sd, struct task_struct *p,
prev_eff_load *= 100 + (sd->imbalance_pct - 100) / 2;
prev_eff_load *= capacity_of(this_cpu);
return this_eff_load <= prev_eff_load;
/*
* If sync, adjust the weight of prev_eff_load such that if
* prev_eff == this_eff that select_idle_sibling() will consider
* stacking the wakee on top of the waker if no other CPU is
* idle.
*/
if (sync)
prev_eff_load += 1;
return this_eff_load < prev_eff_load ? this_cpu : nr_cpumask_bits;
}
static int wake_affine(struct sched_domain *sd, struct task_struct *p,
@ -5509,14 +5533,17 @@ static int wake_affine(struct sched_domain *sd, struct task_struct *p,
{
int this_cpu = smp_processor_id();
bool affine = false;
int target = nr_cpumask_bits;
if (sched_feat(WA_IDLE) && !affine)
affine = wake_affine_idle(sd, p, this_cpu, prev_cpu, sync);
if (sched_feat(WA_IDLE))
target = wake_affine_idle(sd, p, this_cpu, prev_cpu, sync);
if (sched_feat(WA_WEIGHT) && !affine)
affine = wake_affine_weight(sd, p, this_cpu, prev_cpu, sync);
if (sched_feat(WA_WEIGHT) && target == nr_cpumask_bits)
target = wake_affine_weight(sd, p, this_cpu, prev_cpu, sync);
schedstat_inc(p->se.statistics.nr_wakeups_affine_attempts);
if (target == this_cpu)
affine = true;
if (affine) {
schedstat_inc(sd->ttwu_move_affine);
schedstat_inc(p->se.statistics.nr_wakeups_affine);

View File

@ -1715,7 +1715,7 @@ CONFIG_SCSI_ARCMSR=y
CONFIG_SCSI_MPT3SAS=y
CONFIG_SCSI_MPT2SAS_MAX_SGE=128
CONFIG_SCSI_MPT3SAS_MAX_SGE=128
CONFIG_SCSI_SMARTPQI=y
# CONFIG_SCSI_SMARTPQI is not set
CONFIG_SCSI_UFSHCD=y
CONFIG_SCSI_UFSHCD_PCI=y
# CONFIG_SCSI_UFS_DWC_TC_PCI is not set