forked from OSchip/UnityChipVerification
103 lines
4.7 KiB
Systemverilog
103 lines
4.7 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module DelayN_2( // @[utility/src/main/scala/utility/Hold.scala:86:7]
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input clock, // @[utility/src/main/scala/utility/Hold.scala:86:7]
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input [35:0] io_in, // @[utility/src/main/scala/utility/Hold.scala:87:14]
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output [35:0] io_out // @[utility/src/main/scala/utility/Hold.scala:87:14]
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);
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reg [35:0] REG; // @[utility/src/main/scala/utility/Hold.scala:93:18]
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reg [35:0] REG_1; // @[utility/src/main/scala/utility/Hold.scala:93:18]
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reg [35:0] REG_2; // @[utility/src/main/scala/utility/Hold.scala:93:18]
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reg [35:0] REG_3; // @[utility/src/main/scala/utility/Hold.scala:93:18]
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reg [35:0] REG_4; // @[utility/src/main/scala/utility/Hold.scala:93:18]
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always @(posedge clock) begin // @[utility/src/main/scala/utility/Hold.scala:86:7]
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REG <= io_in; // @[utility/src/main/scala/utility/Hold.scala:93:18]
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REG_1 <= REG; // @[utility/src/main/scala/utility/Hold.scala:93:18]
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REG_2 <= REG_1; // @[utility/src/main/scala/utility/Hold.scala:93:18]
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REG_3 <= REG_2; // @[utility/src/main/scala/utility/Hold.scala:93:18]
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REG_4 <= REG_3; // @[utility/src/main/scala/utility/Hold.scala:93:18]
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end // always @(posedge)
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`ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/Hold.scala:86:7]
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`ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/Hold.scala:86:7]
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`FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/Hold.scala:86:7]
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`endif // FIRRTL_BEFORE_INITIAL
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logic [31:0] _RANDOM[0:5]; // @[utility/src/main/scala/utility/Hold.scala:86:7]
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initial begin // @[utility/src/main/scala/utility/Hold.scala:86:7]
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`ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/Hold.scala:86:7]
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`INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/Hold.scala:86:7]
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`endif // INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/Hold.scala:86:7]
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for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin
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_RANDOM[i] = `RANDOM; // @[utility/src/main/scala/utility/Hold.scala:86:7]
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end // @[utility/src/main/scala/utility/Hold.scala:86:7]
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REG = {_RANDOM[3'h0], _RANDOM[3'h1][3:0]}; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18]
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REG_1 = {_RANDOM[3'h1][31:4], _RANDOM[3'h2][7:0]}; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18]
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REG_2 = {_RANDOM[3'h2][31:8], _RANDOM[3'h3][11:0]}; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18]
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REG_3 = {_RANDOM[3'h3][31:12], _RANDOM[3'h4][15:0]}; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18]
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REG_4 = {_RANDOM[3'h4][31:16], _RANDOM[3'h5][19:0]}; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18]
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`endif // RANDOMIZE_REG_INIT
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/Hold.scala:86:7]
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`FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/Hold.scala:86:7]
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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assign io_out = REG_4; // @[utility/src/main/scala/utility/Hold.scala:86:7, :93:18]
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endmodule
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