forked from OSchip/UnityChipVerification
249 lines
10 KiB
Systemverilog
249 lines
10 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module SCTable_2(
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input clock,
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input reset,
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input io_req_valid,
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input [40:0] io_req_bits_pc,
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input [7:0] io_req_bits_folded_hist_hist_11_folded_hist,
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output [5:0] io_resp_ctrs_0_0,
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output [5:0] io_resp_ctrs_0_1,
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output [5:0] io_resp_ctrs_1_0,
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output [5:0] io_resp_ctrs_1_1,
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input [40:0] io_update_pc,
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input [7:0] io_update_folded_hist_hist_11_folded_hist,
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input io_update_mask_0,
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input io_update_mask_1,
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input [5:0] io_update_oldCtrs_0,
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input [5:0] io_update_oldCtrs_1,
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input io_update_tagePreds_0,
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input io_update_tagePreds_1,
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input io_update_takens_0,
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input io_update_takens_1
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);
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wire _wrbypasses_1_io_hit;
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wire _wrbypasses_1_io_hit_data_0_valid;
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wire [5:0] _wrbypasses_1_io_hit_data_0_bits;
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wire _wrbypasses_1_io_hit_data_1_valid;
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wire [5:0] _wrbypasses_1_io_hit_data_1_bits;
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wire _wrbypasses_0_io_hit;
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wire _wrbypasses_0_io_hit_data_0_valid;
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wire [5:0] _wrbypasses_0_io_hit_data_0_bits;
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wire _wrbypasses_0_io_hit_data_1_valid;
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wire [5:0] _wrbypasses_0_io_hit_data_1_bits;
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wire [5:0] _table_io_r_resp_data_0;
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wire [5:0] _table_io_r_resp_data_1;
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wire [5:0] _table_io_r_resp_data_2;
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wire [5:0] _table_io_r_resp_data_3;
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reg [40:0] s1_pc;
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wire updateWayMask_0 =
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io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
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& io_update_pc[1] & ~io_update_tagePreds_1;
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wire updateWayMask_1 =
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io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
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& io_update_pc[1] & io_update_tagePreds_1;
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wire updateWayMask_2 =
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io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
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& ~(io_update_pc[1]) & ~io_update_tagePreds_1;
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wire updateWayMask_3 =
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io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
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& ~(io_update_pc[1]) & io_update_tagePreds_1;
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wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_11_folded_hist;
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wire ctrPos =
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~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1;
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wire [5:0] oldCtr =
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(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
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& (ctrPos
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? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
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& _wrbypasses_1_io_hit_data_1_valid
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: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
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& _wrbypasses_1_io_hit_data_0_valid)
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? (ctrPos
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? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
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| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
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: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
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| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
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: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
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| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0);
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wire taken =
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~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1;
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wire [5:0] update_wdata_0 =
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oldCtr == 6'h1F & taken
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? 6'h1F
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: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1);
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wire ctrPos_1 =
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io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1;
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wire [5:0] oldCtr_1 =
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(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
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& (ctrPos_1
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? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
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& _wrbypasses_1_io_hit_data_1_valid
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: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
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& _wrbypasses_1_io_hit_data_0_valid)
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? (ctrPos_1
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? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
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| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
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: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
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| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
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: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
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| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1);
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wire taken_1 =
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io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1;
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wire [5:0] update_wdata_1 =
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oldCtr_1 == 6'h1F & taken_1
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? 6'h1F
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: oldCtr_1 == 6'h20 & ~taken_1
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? 6'h20
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: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1);
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wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0;
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wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0;
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wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0;
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wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1;
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always @(posedge clock) begin
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if (io_req_valid)
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s1_pc <= io_req_bits_pc;
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end // always @(posedge)
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`ifdef ENABLE_INITIAL_REG_
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`ifdef FIRRTL_BEFORE_INITIAL
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`FIRRTL_BEFORE_INITIAL
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`endif // FIRRTL_BEFORE_INITIAL
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logic [31:0] _RANDOM[0:1];
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initial begin
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`ifdef INIT_RANDOM_PROLOG_
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`INIT_RANDOM_PROLOG_
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`endif // INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE_REG_INIT
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for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
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_RANDOM[i[0]] = `RANDOM;
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end
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s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]};
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`endif // RANDOMIZE_REG_INIT
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL
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`FIRRTL_AFTER_INITIAL
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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SRAMTemplate_35 table_0 (
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.clock (clock),
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.reset (reset),
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.io_r_req_valid (io_req_valid),
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.io_r_req_bits_setIdx
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(io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_11_folded_hist),
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.io_r_resp_data_0 (_table_io_r_resp_data_0),
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.io_r_resp_data_1 (_table_io_r_resp_data_1),
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.io_r_resp_data_2 (_table_io_r_resp_data_2),
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.io_r_resp_data_3 (_table_io_r_resp_data_3),
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.io_w_req_valid (io_update_mask_0 | io_update_mask_1),
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.io_w_req_bits_setIdx (update_idx),
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.io_w_req_bits_data_0 (update_wdata_0),
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.io_w_req_bits_data_1 (update_wdata_0),
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.io_w_req_bits_data_2 (update_wdata_1),
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.io_w_req_bits_data_3 (update_wdata_1),
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.io_w_req_bits_waymask
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({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0})
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);
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WrBypass_33 wrbypasses_0 (
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.clock (clock),
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.reset (reset),
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.io_wen (io_update_mask_0),
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.io_write_idx (update_idx),
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.io_write_data_0 (_GEN | _GEN_0),
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.io_write_data_1 (_GEN | _GEN_0),
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.io_write_way_mask_0
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(~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2),
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.io_write_way_mask_1
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(~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3),
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.io_hit (_wrbypasses_0_io_hit),
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.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
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.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
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.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
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.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
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);
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WrBypass_33 wrbypasses_1 (
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.clock (clock),
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.reset (reset),
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.io_wen (io_update_mask_1),
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.io_write_idx (update_idx),
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.io_write_data_0 (_GEN_1 | _GEN_2),
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.io_write_data_1 (_GEN_1 | _GEN_2),
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.io_write_way_mask_0
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(io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2),
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.io_write_way_mask_1
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(io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3),
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.io_hit (_wrbypasses_1_io_hit),
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.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
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.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
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.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
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.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
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);
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assign io_resp_ctrs_0_0 =
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(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
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| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0);
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assign io_resp_ctrs_0_1 =
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(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
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| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0);
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assign io_resp_ctrs_1_0 =
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(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
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| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2);
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assign io_resp_ctrs_1_1 =
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(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
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| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3);
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endmodule
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