forked from OSchip/UnityChipVerification
227 lines
9.0 KiB
Systemverilog
227 lines
9.0 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
|
|
// Standard header to adapt well known macros for register randomization.
|
|
`ifndef RANDOMIZE
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif // RANDOMIZE_MEM_INIT
|
|
`endif // not def RANDOMIZE
|
|
`ifndef RANDOMIZE
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif // RANDOMIZE_REG_INIT
|
|
`endif // not def RANDOMIZE
|
|
|
|
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif // not def RANDOM
|
|
|
|
// Users can define INIT_RANDOM as general code that gets injected into the
|
|
// initializer block for modules with registers.
|
|
`ifndef INIT_RANDOM
|
|
`define INIT_RANDOM
|
|
`endif // not def INIT_RANDOM
|
|
|
|
// If using random initialization, you can also define RANDOMIZE_DELAY to
|
|
// customize the delay used, otherwise 0.002 is used.
|
|
`ifndef RANDOMIZE_DELAY
|
|
`define RANDOMIZE_DELAY 0.002
|
|
`endif // not def RANDOMIZE_DELAY
|
|
|
|
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
|
|
`ifndef INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE
|
|
`ifdef VERILATOR
|
|
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
|
|
`else // VERILATOR
|
|
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
|
|
`endif // VERILATOR
|
|
`else // RANDOMIZE
|
|
`define INIT_RANDOM_PROLOG_
|
|
`endif // RANDOMIZE
|
|
`endif // not def INIT_RANDOM_PROLOG_
|
|
|
|
// Include register initializers in init blocks unless synthesis is set
|
|
`ifndef SYNTHESIS
|
|
`ifndef ENABLE_INITIAL_REG_
|
|
`define ENABLE_INITIAL_REG_
|
|
`endif // not def ENABLE_INITIAL_REG_
|
|
`endif // not def SYNTHESIS
|
|
|
|
// Include rmemory initializers in init blocks unless synthesis is set
|
|
`ifndef SYNTHESIS
|
|
`ifndef ENABLE_INITIAL_MEM_
|
|
`define ENABLE_INITIAL_MEM_
|
|
`endif // not def ENABLE_INITIAL_MEM_
|
|
`endif // not def SYNTHESIS
|
|
|
|
module ITTageTable(
|
|
input clock,
|
|
input reset,
|
|
input io_req_valid,
|
|
input [40:0] io_req_bits_pc,
|
|
input [3:0] io_req_bits_folded_hist_hist_12_folded_hist,
|
|
output io_resp_valid,
|
|
output [1:0] io_resp_bits_ctr,
|
|
output [1:0] io_resp_bits_u,
|
|
output [40:0] io_resp_bits_target,
|
|
input [40:0] io_update_pc,
|
|
input [3:0] io_update_folded_hist_hist_12_folded_hist,
|
|
input io_update_valid,
|
|
input io_update_correct,
|
|
input io_update_alloc,
|
|
input [1:0] io_update_oldCtr,
|
|
input io_update_uValid,
|
|
input io_update_u,
|
|
input io_update_reset_u,
|
|
input [40:0] io_update_target,
|
|
input [40:0] io_update_old_target
|
|
);
|
|
|
|
wire _resp_invalid_by_write_T_2;
|
|
wire _wrbypass_io_hit;
|
|
wire [1:0] _wrbypass_io_hit_data_0_bits;
|
|
wire _table_banks_1_io_r_resp_data_0_valid;
|
|
wire [8:0] _table_banks_1_io_r_resp_data_0_tag;
|
|
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr;
|
|
wire [40:0] _table_banks_1_io_r_resp_data_0_target;
|
|
wire _table_banks_0_io_r_resp_data_0_valid;
|
|
wire [8:0] _table_banks_0_io_r_resp_data_0_tag;
|
|
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr;
|
|
wire [40:0] _table_banks_0_io_r_resp_data_0_target;
|
|
wire _us_io_rdata_0;
|
|
wire [3:0] _GEN = io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist;
|
|
reg [8:0] s1_tag;
|
|
reg s1_bank_req_1h_0;
|
|
reg s1_bank_req_1h_1;
|
|
wire [6:0] _table_banks_1_io_r_req_bits_setIdx_T = {io_req_bits_pc[8:5], _GEN[3:1]};
|
|
reg s1_bank_has_write_on_this_req_0;
|
|
reg s1_bank_has_write_on_this_req_1;
|
|
wire [3:0] _GEN_0 = io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist;
|
|
wire [7:0] update_idx = {io_update_pc[8:5], _GEN_0};
|
|
wire [8:0] update_tag =
|
|
{io_update_pc[17:14],
|
|
{io_update_pc[13], io_update_pc[12:9] ^ io_update_folded_hist_hist_12_folded_hist}
|
|
^ {io_update_folded_hist_hist_12_folded_hist, 1'h0}};
|
|
wire [6:0] update_idx_in_bank = {io_update_pc[8:5], _GEN_0[3:1]};
|
|
assign _resp_invalid_by_write_T_2 =
|
|
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
|
|
& s1_bank_has_write_on_this_req_1;
|
|
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(_GEN_0[0]);
|
|
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & _GEN_0[0];
|
|
wire [1:0] old_ctr =
|
|
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;
|
|
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;
|
|
wire [1:0] update_wdata_ctr =
|
|
io_update_alloc
|
|
? 2'h2
|
|
: (&old_ctr) & io_update_correct
|
|
? 2'h3
|
|
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
|
|
? 2'h0
|
|
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);
|
|
wire [40:0] update_wdata_target =
|
|
io_update_alloc | update_wdata_ctr_oldSatNotTaken
|
|
? io_update_target
|
|
: io_update_old_target;
|
|
always @(posedge clock) begin
|
|
if (io_req_valid) begin
|
|
s1_tag <=
|
|
{io_req_bits_pc[17:14],
|
|
{io_req_bits_pc[13],
|
|
io_req_bits_pc[12:9] ^ io_req_bits_folded_hist_hist_12_folded_hist}
|
|
^ {io_req_bits_folded_hist_hist_12_folded_hist, 1'h0}};
|
|
s1_bank_req_1h_0 <= ~(_GEN[0]);
|
|
s1_bank_req_1h_1 <= _GEN[0];
|
|
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
|
|
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
|
|
end
|
|
end // always @(posedge)
|
|
`ifdef ENABLE_INITIAL_REG_
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif // FIRRTL_BEFORE_INITIAL
|
|
logic [31:0] _RANDOM[0:0];
|
|
initial begin
|
|
`ifdef INIT_RANDOM_PROLOG_
|
|
`INIT_RANDOM_PROLOG_
|
|
`endif // INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
|
|
s1_tag = _RANDOM[/*Zero width*/ 1'b0][16:8];
|
|
s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][17];
|
|
s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][18];
|
|
s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][19];
|
|
s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][20];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif // FIRRTL_AFTER_INITIAL
|
|
`endif // ENABLE_INITIAL_REG_
|
|
Folded1WDataModuleTemplate us (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_ren_0 (io_req_valid),
|
|
.io_raddr_0 ({io_req_bits_pc[8:5], _GEN}),
|
|
.io_rdata_0 (_us_io_rdata_0),
|
|
.io_wen (io_update_uValid),
|
|
.io_waddr (update_idx),
|
|
.io_wdata (io_update_u),
|
|
.io_resetEn (io_update_reset_u)
|
|
);
|
|
FoldedSRAMTemplate_21 table_banks_0 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_r_req_valid (io_req_valid & ~(_GEN[0])),
|
|
.io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T),
|
|
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
|
|
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
|
|
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
|
|
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
|
|
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
|
|
.io_w_req_bits_setIdx (update_idx_in_bank),
|
|
.io_w_req_bits_data_0_tag (update_tag),
|
|
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
|
|
.io_w_req_bits_data_0_target (update_wdata_target)
|
|
);
|
|
FoldedSRAMTemplate_21 table_banks_1 (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_r_req_valid (io_req_valid & _GEN[0]),
|
|
.io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T),
|
|
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
|
|
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
|
|
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
|
|
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
|
|
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
|
|
.io_w_req_bits_setIdx (update_idx_in_bank),
|
|
.io_w_req_bits_data_0_tag (update_tag),
|
|
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
|
|
.io_w_req_bits_data_0_target (update_wdata_target)
|
|
);
|
|
WrBypass_41 wrbypass (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_wen (io_update_valid),
|
|
.io_write_idx (update_idx),
|
|
.io_write_data_0 (update_wdata_ctr),
|
|
.io_hit (_wrbypass_io_hit),
|
|
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
|
|
);
|
|
assign io_resp_valid =
|
|
(s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1
|
|
& _table_banks_1_io_r_resp_data_0_valid)
|
|
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
|
|
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
|
|
& ~_resp_invalid_by_write_T_2;
|
|
assign io_resp_bits_ctr =
|
|
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
|
|
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);
|
|
assign io_resp_bits_u = {1'h0, _us_io_rdata_0};
|
|
assign io_resp_bits_target =
|
|
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)
|
|
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);
|
|
endmodule
|
|
|