forked from OSchip/UnityChipVerification
1645 lines
86 KiB
Systemverilog
1645 lines
86 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module FTB(
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input clock,
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input reset,
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input [35:0] io_reset_vector,
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input [40:0] io_in_bits_s0_pc_0,
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input [40:0] io_in_bits_s0_pc_1,
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input [40:0] io_in_bits_s0_pc_2,
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input [40:0] io_in_bits_s0_pc_3,
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input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0,
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input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1,
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input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0,
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input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1,
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input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0,
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input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1,
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input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0,
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input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1,
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input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0,
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input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1,
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input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0,
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input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1,
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input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0,
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input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1,
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input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0,
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input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1,
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output io_out_s2_full_pred_0_br_taken_mask_0,
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output io_out_s2_full_pred_0_br_taken_mask_1,
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output io_out_s2_full_pred_0_slot_valids_0,
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output io_out_s2_full_pred_0_slot_valids_1,
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output [40:0] io_out_s2_full_pred_0_targets_0,
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output [40:0] io_out_s2_full_pred_0_targets_1,
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output [40:0] io_out_s2_full_pred_0_jalr_target,
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output [3:0] io_out_s2_full_pred_0_offsets_0,
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output [3:0] io_out_s2_full_pred_0_offsets_1,
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output [40:0] io_out_s2_full_pred_0_fallThroughAddr,
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output io_out_s2_full_pred_0_is_br_sharing,
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output io_out_s2_full_pred_0_hit,
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output io_out_s2_full_pred_1_br_taken_mask_0,
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output io_out_s2_full_pred_1_br_taken_mask_1,
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output io_out_s2_full_pred_1_slot_valids_0,
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output io_out_s2_full_pred_1_slot_valids_1,
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output [40:0] io_out_s2_full_pred_1_targets_0,
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output [40:0] io_out_s2_full_pred_1_targets_1,
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output [40:0] io_out_s2_full_pred_1_jalr_target,
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output [3:0] io_out_s2_full_pred_1_offsets_0,
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output [3:0] io_out_s2_full_pred_1_offsets_1,
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output [40:0] io_out_s2_full_pred_1_fallThroughAddr,
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output io_out_s2_full_pred_1_is_br_sharing,
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output io_out_s2_full_pred_1_hit,
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output io_out_s2_full_pred_2_br_taken_mask_0,
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output io_out_s2_full_pred_2_br_taken_mask_1,
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output io_out_s2_full_pred_2_slot_valids_0,
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output io_out_s2_full_pred_2_slot_valids_1,
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output [40:0] io_out_s2_full_pred_2_targets_0,
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output [40:0] io_out_s2_full_pred_2_targets_1,
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output [40:0] io_out_s2_full_pred_2_jalr_target,
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output [3:0] io_out_s2_full_pred_2_offsets_0,
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output [3:0] io_out_s2_full_pred_2_offsets_1,
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output [40:0] io_out_s2_full_pred_2_fallThroughAddr,
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output io_out_s2_full_pred_2_is_jalr,
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output io_out_s2_full_pred_2_is_call,
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output io_out_s2_full_pred_2_is_ret,
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output io_out_s2_full_pred_2_last_may_be_rvi_call,
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output io_out_s2_full_pred_2_is_br_sharing,
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output io_out_s2_full_pred_2_hit,
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output io_out_s2_full_pred_3_br_taken_mask_0,
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output io_out_s2_full_pred_3_br_taken_mask_1,
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output io_out_s2_full_pred_3_slot_valids_0,
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output io_out_s2_full_pred_3_slot_valids_1,
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output [40:0] io_out_s2_full_pred_3_targets_0,
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output [40:0] io_out_s2_full_pred_3_targets_1,
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output [40:0] io_out_s2_full_pred_3_jalr_target,
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output [3:0] io_out_s2_full_pred_3_offsets_0,
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output [3:0] io_out_s2_full_pred_3_offsets_1,
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output [40:0] io_out_s2_full_pred_3_fallThroughAddr,
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output io_out_s2_full_pred_3_fallThroughErr,
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output io_out_s2_full_pred_3_is_br_sharing,
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output io_out_s2_full_pred_3_hit,
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output io_out_s3_full_pred_0_br_taken_mask_0,
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output io_out_s3_full_pred_0_br_taken_mask_1,
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output io_out_s3_full_pred_0_slot_valids_0,
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output io_out_s3_full_pred_0_slot_valids_1,
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output [40:0] io_out_s3_full_pred_0_targets_0,
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output [40:0] io_out_s3_full_pred_0_targets_1,
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output [40:0] io_out_s3_full_pred_0_jalr_target,
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output [40:0] io_out_s3_full_pred_0_fallThroughAddr,
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output io_out_s3_full_pred_0_fallThroughErr,
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output io_out_s3_full_pred_0_is_br_sharing,
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output io_out_s3_full_pred_0_hit,
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output io_out_s3_full_pred_1_br_taken_mask_0,
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output io_out_s3_full_pred_1_br_taken_mask_1,
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output io_out_s3_full_pred_1_slot_valids_0,
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output io_out_s3_full_pred_1_slot_valids_1,
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output [40:0] io_out_s3_full_pred_1_targets_0,
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output [40:0] io_out_s3_full_pred_1_targets_1,
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output [40:0] io_out_s3_full_pred_1_jalr_target,
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output [40:0] io_out_s3_full_pred_1_fallThroughAddr,
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output io_out_s3_full_pred_1_fallThroughErr,
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output io_out_s3_full_pred_1_is_br_sharing,
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output io_out_s3_full_pred_1_hit,
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output io_out_s3_full_pred_2_br_taken_mask_0,
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output io_out_s3_full_pred_2_br_taken_mask_1,
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output io_out_s3_full_pred_2_slot_valids_0,
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output io_out_s3_full_pred_2_slot_valids_1,
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output [40:0] io_out_s3_full_pred_2_targets_0,
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output [40:0] io_out_s3_full_pred_2_targets_1,
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output [40:0] io_out_s3_full_pred_2_jalr_target,
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output [40:0] io_out_s3_full_pred_2_fallThroughAddr,
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output io_out_s3_full_pred_2_fallThroughErr,
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output io_out_s3_full_pred_2_is_jalr,
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output io_out_s3_full_pred_2_is_call,
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output io_out_s3_full_pred_2_is_ret,
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output io_out_s3_full_pred_2_is_br_sharing,
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output io_out_s3_full_pred_2_hit,
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output io_out_s3_full_pred_3_br_taken_mask_0,
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output io_out_s3_full_pred_3_br_taken_mask_1,
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output io_out_s3_full_pred_3_slot_valids_0,
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output io_out_s3_full_pred_3_slot_valids_1,
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output [40:0] io_out_s3_full_pred_3_targets_0,
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output [40:0] io_out_s3_full_pred_3_targets_1,
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output [40:0] io_out_s3_full_pred_3_jalr_target,
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output [3:0] io_out_s3_full_pred_3_offsets_0,
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output [3:0] io_out_s3_full_pred_3_offsets_1,
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output [40:0] io_out_s3_full_pred_3_fallThroughAddr,
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output io_out_s3_full_pred_3_fallThroughErr,
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output io_out_s3_full_pred_3_is_br_sharing,
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output io_out_s3_full_pred_3_hit,
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output [222:0] io_out_last_stage_meta,
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output io_out_last_stage_ftb_entry_valid,
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output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset,
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output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower,
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output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat,
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output io_out_last_stage_ftb_entry_brSlots_0_sharing,
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output io_out_last_stage_ftb_entry_brSlots_0_valid,
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output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset,
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output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower,
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output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat,
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output io_out_last_stage_ftb_entry_tailSlot_sharing,
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output io_out_last_stage_ftb_entry_tailSlot_valid,
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output [3:0] io_out_last_stage_ftb_entry_pftAddr,
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output io_out_last_stage_ftb_entry_carry,
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output io_out_last_stage_ftb_entry_isCall,
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output io_out_last_stage_ftb_entry_isRet,
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output io_out_last_stage_ftb_entry_isJalr,
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output io_out_last_stage_ftb_entry_last_may_be_rvi_call,
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output io_out_last_stage_ftb_entry_always_taken_0,
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output io_out_last_stage_ftb_entry_always_taken_1,
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input io_ctrl_btb_enable,
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input io_s0_fire_0,
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input io_s0_fire_1,
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input io_s0_fire_2,
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input io_s0_fire_3,
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input io_s1_fire_0,
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input io_s1_fire_1,
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input io_s1_fire_2,
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input io_s1_fire_3,
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input io_s2_fire_0,
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input io_s2_fire_1,
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input io_s2_fire_2,
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input io_s2_fire_3,
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output io_s1_ready,
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input io_update_valid,
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input [40:0] io_update_bits_pc,
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input io_update_bits_ftb_entry_valid,
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input [3:0] io_update_bits_ftb_entry_brSlots_0_offset,
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input [11:0] io_update_bits_ftb_entry_brSlots_0_lower,
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input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat,
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input io_update_bits_ftb_entry_brSlots_0_sharing,
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input io_update_bits_ftb_entry_brSlots_0_valid,
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input [3:0] io_update_bits_ftb_entry_tailSlot_offset,
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input [19:0] io_update_bits_ftb_entry_tailSlot_lower,
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input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat,
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input io_update_bits_ftb_entry_tailSlot_sharing,
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input io_update_bits_ftb_entry_tailSlot_valid,
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input [3:0] io_update_bits_ftb_entry_pftAddr,
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input io_update_bits_ftb_entry_carry,
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input io_update_bits_ftb_entry_isCall,
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input io_update_bits_ftb_entry_isRet,
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input io_update_bits_ftb_entry_isJalr,
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input io_update_bits_ftb_entry_last_may_be_rvi_call,
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input io_update_bits_ftb_entry_always_taken_0,
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input io_update_bits_ftb_entry_always_taken_1,
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input io_update_bits_old_entry,
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input [222:0] io_update_bits_meta,
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output [5:0] io_perf_0_value,
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output [5:0] io_perf_1_value
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);
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wire _write_valid_delay_io_out;
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wire _delay2_entry_pipMod_io_out_bits_valid;
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wire [3:0] _delay2_entry_pipMod_io_out_bits_brSlots_0_offset;
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wire [11:0] _delay2_entry_pipMod_io_out_bits_brSlots_0_lower;
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wire [1:0] _delay2_entry_pipMod_io_out_bits_brSlots_0_tarStat;
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wire _delay2_entry_pipMod_io_out_bits_brSlots_0_sharing;
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wire _delay2_entry_pipMod_io_out_bits_brSlots_0_valid;
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wire [3:0] _delay2_entry_pipMod_io_out_bits_tailSlot_offset;
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wire [19:0] _delay2_entry_pipMod_io_out_bits_tailSlot_lower;
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wire [1:0] _delay2_entry_pipMod_io_out_bits_tailSlot_tarStat;
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wire _delay2_entry_pipMod_io_out_bits_tailSlot_sharing;
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wire _delay2_entry_pipMod_io_out_bits_tailSlot_valid;
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wire [3:0] _delay2_entry_pipMod_io_out_bits_pftAddr;
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wire _delay2_entry_pipMod_io_out_bits_carry;
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wire _delay2_entry_pipMod_io_out_bits_isCall;
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wire _delay2_entry_pipMod_io_out_bits_isRet;
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wire _delay2_entry_pipMod_io_out_bits_isJalr;
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wire _delay2_entry_pipMod_io_out_bits_last_may_be_rvi_call;
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wire _delay2_entry_pipMod_io_out_bits_always_taken_0;
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wire _delay2_entry_pipMod_io_out_bits_always_taken_1;
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wire [40:0] _delay2_pc_pipMod_io_out_bits;
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wire _ftbBank_io_req_pc_ready;
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wire _ftbBank_io_read_resp_valid;
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wire [3:0] _ftbBank_io_read_resp_brSlots_0_offset;
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wire [11:0] _ftbBank_io_read_resp_brSlots_0_lower;
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wire [1:0] _ftbBank_io_read_resp_brSlots_0_tarStat;
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wire _ftbBank_io_read_resp_brSlots_0_sharing;
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wire _ftbBank_io_read_resp_brSlots_0_valid;
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wire [3:0] _ftbBank_io_read_resp_tailSlot_offset;
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wire [19:0] _ftbBank_io_read_resp_tailSlot_lower;
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wire [1:0] _ftbBank_io_read_resp_tailSlot_tarStat;
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wire _ftbBank_io_read_resp_tailSlot_sharing;
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wire _ftbBank_io_read_resp_tailSlot_valid;
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wire [3:0] _ftbBank_io_read_resp_pftAddr;
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wire _ftbBank_io_read_resp_carry;
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wire _ftbBank_io_read_resp_isCall;
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wire _ftbBank_io_read_resp_isRet;
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wire _ftbBank_io_read_resp_isJalr;
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wire _ftbBank_io_read_resp_last_may_be_rvi_call;
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wire _ftbBank_io_read_resp_always_taken_0;
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wire _ftbBank_io_read_resp_always_taken_1;
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wire _ftbBank_io_read_hits_valid;
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wire [1:0] _ftbBank_io_read_hits_bits;
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wire _ftbBank_io_update_hits_valid;
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wire [1:0] _ftbBank_io_update_hits_bits;
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wire [35:0] _reset_vector_delay_io_out;
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reg [40:0] s1_pc_dup_0;
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reg [40:0] s1_pc_dup_1;
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reg [40:0] s1_pc_dup_2;
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reg [40:0] s1_pc_dup_3;
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reg [40:0] s2_pc_dup_0;
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reg [40:0] s2_pc_dup_1;
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reg [40:0] s2_pc_dup_2;
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reg [40:0] s2_pc_dup_3;
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reg [40:0] s3_pc_dup_0;
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reg [40:0] s3_pc_dup_1;
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reg [40:0] s3_pc_dup_2;
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reg [40:0] s3_pc_dup_3;
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reg REG;
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reg REG_1;
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reg s2_ftb_entry_dup_0_valid;
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reg [3:0] s2_ftb_entry_dup_0_brSlots_0_offset;
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reg [11:0] s2_ftb_entry_dup_0_brSlots_0_lower;
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reg [1:0] s2_ftb_entry_dup_0_brSlots_0_tarStat;
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reg s2_ftb_entry_dup_0_brSlots_0_sharing;
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reg s2_ftb_entry_dup_0_brSlots_0_valid;
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reg [3:0] s2_ftb_entry_dup_0_tailSlot_offset;
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reg [19:0] s2_ftb_entry_dup_0_tailSlot_lower;
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reg [1:0] s2_ftb_entry_dup_0_tailSlot_tarStat;
|
|
reg s2_ftb_entry_dup_0_tailSlot_sharing;
|
|
reg s2_ftb_entry_dup_0_tailSlot_valid;
|
|
reg [3:0] s2_ftb_entry_dup_0_pftAddr;
|
|
reg s2_ftb_entry_dup_0_carry;
|
|
reg s2_ftb_entry_dup_0_isCall;
|
|
reg s2_ftb_entry_dup_0_isRet;
|
|
reg s2_ftb_entry_dup_0_isJalr;
|
|
reg s2_ftb_entry_dup_0_last_may_be_rvi_call;
|
|
reg s2_ftb_entry_dup_0_always_taken_0;
|
|
reg s2_ftb_entry_dup_0_always_taken_1;
|
|
reg [3:0] s2_ftb_entry_dup_1_brSlots_0_offset;
|
|
reg [11:0] s2_ftb_entry_dup_1_brSlots_0_lower;
|
|
reg [1:0] s2_ftb_entry_dup_1_brSlots_0_tarStat;
|
|
reg s2_ftb_entry_dup_1_brSlots_0_valid;
|
|
reg [3:0] s2_ftb_entry_dup_1_tailSlot_offset;
|
|
reg [19:0] s2_ftb_entry_dup_1_tailSlot_lower;
|
|
reg [1:0] s2_ftb_entry_dup_1_tailSlot_tarStat;
|
|
reg s2_ftb_entry_dup_1_tailSlot_sharing;
|
|
reg s2_ftb_entry_dup_1_tailSlot_valid;
|
|
reg [3:0] s2_ftb_entry_dup_1_pftAddr;
|
|
reg s2_ftb_entry_dup_1_carry;
|
|
reg s2_ftb_entry_dup_1_always_taken_0;
|
|
reg s2_ftb_entry_dup_1_always_taken_1;
|
|
reg [3:0] s2_ftb_entry_dup_2_brSlots_0_offset;
|
|
reg [11:0] s2_ftb_entry_dup_2_brSlots_0_lower;
|
|
reg [1:0] s2_ftb_entry_dup_2_brSlots_0_tarStat;
|
|
reg s2_ftb_entry_dup_2_brSlots_0_valid;
|
|
reg [3:0] s2_ftb_entry_dup_2_tailSlot_offset;
|
|
reg [19:0] s2_ftb_entry_dup_2_tailSlot_lower;
|
|
reg [1:0] s2_ftb_entry_dup_2_tailSlot_tarStat;
|
|
reg s2_ftb_entry_dup_2_tailSlot_sharing;
|
|
reg s2_ftb_entry_dup_2_tailSlot_valid;
|
|
reg [3:0] s2_ftb_entry_dup_2_pftAddr;
|
|
reg s2_ftb_entry_dup_2_carry;
|
|
reg s2_ftb_entry_dup_2_isCall;
|
|
reg s2_ftb_entry_dup_2_isRet;
|
|
reg s2_ftb_entry_dup_2_isJalr;
|
|
reg s2_ftb_entry_dup_2_last_may_be_rvi_call;
|
|
reg s2_ftb_entry_dup_2_always_taken_0;
|
|
reg s2_ftb_entry_dup_2_always_taken_1;
|
|
reg [3:0] s2_ftb_entry_dup_3_brSlots_0_offset;
|
|
reg [11:0] s2_ftb_entry_dup_3_brSlots_0_lower;
|
|
reg [1:0] s2_ftb_entry_dup_3_brSlots_0_tarStat;
|
|
reg s2_ftb_entry_dup_3_brSlots_0_valid;
|
|
reg [3:0] s2_ftb_entry_dup_3_tailSlot_offset;
|
|
reg [19:0] s2_ftb_entry_dup_3_tailSlot_lower;
|
|
reg [1:0] s2_ftb_entry_dup_3_tailSlot_tarStat;
|
|
reg s2_ftb_entry_dup_3_tailSlot_sharing;
|
|
reg s2_ftb_entry_dup_3_tailSlot_valid;
|
|
reg [3:0] s2_ftb_entry_dup_3_pftAddr;
|
|
reg s2_ftb_entry_dup_3_carry;
|
|
reg s2_ftb_entry_dup_3_always_taken_0;
|
|
reg s2_ftb_entry_dup_3_always_taken_1;
|
|
reg s3_ftb_entry_dup_0_valid;
|
|
reg [3:0] s3_ftb_entry_dup_0_brSlots_0_offset;
|
|
reg [11:0] s3_ftb_entry_dup_0_brSlots_0_lower;
|
|
reg [1:0] s3_ftb_entry_dup_0_brSlots_0_tarStat;
|
|
reg s3_ftb_entry_dup_0_brSlots_0_sharing;
|
|
reg s3_ftb_entry_dup_0_brSlots_0_valid;
|
|
reg [3:0] s3_ftb_entry_dup_0_tailSlot_offset;
|
|
reg [19:0] s3_ftb_entry_dup_0_tailSlot_lower;
|
|
reg [1:0] s3_ftb_entry_dup_0_tailSlot_tarStat;
|
|
reg s3_ftb_entry_dup_0_tailSlot_sharing;
|
|
reg s3_ftb_entry_dup_0_tailSlot_valid;
|
|
reg [3:0] s3_ftb_entry_dup_0_pftAddr;
|
|
reg s3_ftb_entry_dup_0_carry;
|
|
reg s3_ftb_entry_dup_0_isCall;
|
|
reg s3_ftb_entry_dup_0_isRet;
|
|
reg s3_ftb_entry_dup_0_isJalr;
|
|
reg s3_ftb_entry_dup_0_last_may_be_rvi_call;
|
|
reg s3_ftb_entry_dup_0_always_taken_0;
|
|
reg s3_ftb_entry_dup_0_always_taken_1;
|
|
reg [11:0] s3_ftb_entry_dup_1_brSlots_0_lower;
|
|
reg [1:0] s3_ftb_entry_dup_1_brSlots_0_tarStat;
|
|
reg s3_ftb_entry_dup_1_brSlots_0_valid;
|
|
reg [19:0] s3_ftb_entry_dup_1_tailSlot_lower;
|
|
reg [1:0] s3_ftb_entry_dup_1_tailSlot_tarStat;
|
|
reg s3_ftb_entry_dup_1_tailSlot_sharing;
|
|
reg s3_ftb_entry_dup_1_tailSlot_valid;
|
|
reg [3:0] s3_ftb_entry_dup_1_pftAddr;
|
|
reg s3_ftb_entry_dup_1_carry;
|
|
reg s3_ftb_entry_dup_1_always_taken_0;
|
|
reg s3_ftb_entry_dup_1_always_taken_1;
|
|
reg [11:0] s3_ftb_entry_dup_2_brSlots_0_lower;
|
|
reg [1:0] s3_ftb_entry_dup_2_brSlots_0_tarStat;
|
|
reg s3_ftb_entry_dup_2_brSlots_0_valid;
|
|
reg [19:0] s3_ftb_entry_dup_2_tailSlot_lower;
|
|
reg [1:0] s3_ftb_entry_dup_2_tailSlot_tarStat;
|
|
reg s3_ftb_entry_dup_2_tailSlot_sharing;
|
|
reg s3_ftb_entry_dup_2_tailSlot_valid;
|
|
reg [3:0] s3_ftb_entry_dup_2_pftAddr;
|
|
reg s3_ftb_entry_dup_2_carry;
|
|
reg s3_ftb_entry_dup_2_isCall;
|
|
reg s3_ftb_entry_dup_2_isRet;
|
|
reg s3_ftb_entry_dup_2_isJalr;
|
|
reg s3_ftb_entry_dup_2_always_taken_0;
|
|
reg s3_ftb_entry_dup_2_always_taken_1;
|
|
reg [3:0] s3_ftb_entry_dup_3_brSlots_0_offset;
|
|
reg [11:0] s3_ftb_entry_dup_3_brSlots_0_lower;
|
|
reg [1:0] s3_ftb_entry_dup_3_brSlots_0_tarStat;
|
|
reg s3_ftb_entry_dup_3_brSlots_0_valid;
|
|
reg [3:0] s3_ftb_entry_dup_3_tailSlot_offset;
|
|
reg [19:0] s3_ftb_entry_dup_3_tailSlot_lower;
|
|
reg [1:0] s3_ftb_entry_dup_3_tailSlot_tarStat;
|
|
reg s3_ftb_entry_dup_3_tailSlot_sharing;
|
|
reg s3_ftb_entry_dup_3_tailSlot_valid;
|
|
reg [3:0] s3_ftb_entry_dup_3_pftAddr;
|
|
reg s3_ftb_entry_dup_3_carry;
|
|
reg s3_ftb_entry_dup_3_always_taken_0;
|
|
reg s3_ftb_entry_dup_3_always_taken_1;
|
|
wire s1_hit = _ftbBank_io_read_hits_valid & io_ctrl_btb_enable;
|
|
reg s2_hit_dup_0;
|
|
reg s2_hit_dup_1;
|
|
reg s2_hit_dup_2;
|
|
reg s2_hit_dup_3;
|
|
reg s3_hit_dup_0;
|
|
reg s3_hit_dup_1;
|
|
reg s3_hit_dup_2;
|
|
reg s3_hit_dup_3;
|
|
reg [27:0] higher_r;
|
|
reg [27:0] higher_plus_one_r;
|
|
reg [27:0] higher_minus_one_r;
|
|
reg [27:0] higher_r_1;
|
|
reg [27:0] higher_plus_one_r_1;
|
|
reg [27:0] higher_minus_one_r_1;
|
|
wire _target_T_18 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h1;
|
|
wire _target_T_19 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h2;
|
|
wire _target_T_20 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h0;
|
|
reg [19:0] higher_r_2;
|
|
reg [19:0] higher_plus_one_r_2;
|
|
reg [19:0] higher_minus_one_r_2;
|
|
wire [40:0] io_out_s2_full_pred_0_targets_1_0 =
|
|
{s2_ftb_entry_dup_0_tailSlot_sharing
|
|
? {(_target_T_18 ? higher_plus_one_r_1 : 28'h0)
|
|
| (_target_T_19 ? higher_minus_one_r_1 : 28'h0)
|
|
| (_target_T_20 ? higher_r_1 : 28'h0),
|
|
s2_ftb_entry_dup_0_tailSlot_lower[11:0]}
|
|
: {(_target_T_18 ? higher_plus_one_r_2 : 20'h0)
|
|
| (_target_T_19 ? higher_minus_one_r_2 : 20'h0)
|
|
| (_target_T_20 ? higher_r_2 : 20'h0),
|
|
s2_ftb_entry_dup_0_tailSlot_lower},
|
|
1'h0};
|
|
reg io_out_s2_full_pred_0_fallThroughAddr_stashed_carry;
|
|
reg [27:0] higher_r_3;
|
|
reg [27:0] higher_plus_one_r_3;
|
|
reg [27:0] higher_minus_one_r_3;
|
|
reg [27:0] higher_r_4;
|
|
reg [27:0] higher_plus_one_r_4;
|
|
reg [27:0] higher_minus_one_r_4;
|
|
wire _target_T_45 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h1;
|
|
wire _target_T_46 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h2;
|
|
wire _target_T_47 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h0;
|
|
reg [19:0] higher_r_5;
|
|
reg [19:0] higher_plus_one_r_5;
|
|
reg [19:0] higher_minus_one_r_5;
|
|
wire [40:0] io_out_s2_full_pred_1_targets_1_0 =
|
|
{s2_ftb_entry_dup_1_tailSlot_sharing
|
|
? {(_target_T_45 ? higher_plus_one_r_4 : 28'h0)
|
|
| (_target_T_46 ? higher_minus_one_r_4 : 28'h0)
|
|
| (_target_T_47 ? higher_r_4 : 28'h0),
|
|
s2_ftb_entry_dup_1_tailSlot_lower[11:0]}
|
|
: {(_target_T_45 ? higher_plus_one_r_5 : 20'h0)
|
|
| (_target_T_46 ? higher_minus_one_r_5 : 20'h0)
|
|
| (_target_T_47 ? higher_r_5 : 20'h0),
|
|
s2_ftb_entry_dup_1_tailSlot_lower},
|
|
1'h0};
|
|
reg io_out_s2_full_pred_1_fallThroughAddr_stashed_carry;
|
|
reg [27:0] higher_r_6;
|
|
reg [27:0] higher_plus_one_r_6;
|
|
reg [27:0] higher_minus_one_r_6;
|
|
reg [27:0] higher_r_7;
|
|
reg [27:0] higher_plus_one_r_7;
|
|
reg [27:0] higher_minus_one_r_7;
|
|
wire _target_T_72 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h1;
|
|
wire _target_T_73 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h2;
|
|
wire _target_T_74 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h0;
|
|
reg [19:0] higher_r_8;
|
|
reg [19:0] higher_plus_one_r_8;
|
|
reg [19:0] higher_minus_one_r_8;
|
|
wire [40:0] io_out_s2_full_pred_2_targets_1_0 =
|
|
{s2_ftb_entry_dup_2_tailSlot_sharing
|
|
? {(_target_T_72 ? higher_plus_one_r_7 : 28'h0)
|
|
| (_target_T_73 ? higher_minus_one_r_7 : 28'h0)
|
|
| (_target_T_74 ? higher_r_7 : 28'h0),
|
|
s2_ftb_entry_dup_2_tailSlot_lower[11:0]}
|
|
: {(_target_T_72 ? higher_plus_one_r_8 : 20'h0)
|
|
| (_target_T_73 ? higher_minus_one_r_8 : 20'h0)
|
|
| (_target_T_74 ? higher_r_8 : 20'h0),
|
|
s2_ftb_entry_dup_2_tailSlot_lower},
|
|
1'h0};
|
|
reg io_out_s2_full_pred_2_fallThroughAddr_stashed_carry;
|
|
reg [27:0] higher_r_9;
|
|
reg [27:0] higher_plus_one_r_9;
|
|
reg [27:0] higher_minus_one_r_9;
|
|
reg [27:0] higher_r_10;
|
|
reg [27:0] higher_plus_one_r_10;
|
|
reg [27:0] higher_minus_one_r_10;
|
|
wire _target_T_99 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h1;
|
|
wire _target_T_100 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h2;
|
|
wire _target_T_101 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h0;
|
|
reg [19:0] higher_r_11;
|
|
reg [19:0] higher_plus_one_r_11;
|
|
reg [19:0] higher_minus_one_r_11;
|
|
wire [40:0] io_out_s2_full_pred_3_targets_1_0 =
|
|
{s2_ftb_entry_dup_3_tailSlot_sharing
|
|
? {(_target_T_99 ? higher_plus_one_r_10 : 28'h0)
|
|
| (_target_T_100 ? higher_minus_one_r_10 : 28'h0)
|
|
| (_target_T_101 ? higher_r_10 : 28'h0),
|
|
s2_ftb_entry_dup_3_tailSlot_lower[11:0]}
|
|
: {(_target_T_99 ? higher_plus_one_r_11 : 20'h0)
|
|
| (_target_T_100 ? higher_minus_one_r_11 : 20'h0)
|
|
| (_target_T_101 ? higher_r_11 : 20'h0),
|
|
s2_ftb_entry_dup_3_tailSlot_lower},
|
|
1'h0};
|
|
wire io_out_s2_full_pred_3_fallThroughErr_0 =
|
|
{1'h0, s2_pc_dup_3[4:1]} >= {s2_ftb_entry_dup_3_carry, s2_ftb_entry_dup_3_pftAddr};
|
|
reg io_out_s2_full_pred_3_fallThroughAddr_stashed_carry;
|
|
reg [27:0] higher_r_12;
|
|
reg [27:0] higher_plus_one_r_12;
|
|
reg [27:0] higher_minus_one_r_12;
|
|
reg [27:0] higher_r_13;
|
|
reg [27:0] higher_plus_one_r_13;
|
|
reg [27:0] higher_minus_one_r_13;
|
|
wire _target_T_126 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h1;
|
|
wire _target_T_127 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h2;
|
|
wire _target_T_128 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h0;
|
|
reg [19:0] higher_r_14;
|
|
reg [19:0] higher_plus_one_r_14;
|
|
reg [19:0] higher_minus_one_r_14;
|
|
wire [40:0] io_out_s3_full_pred_0_targets_1_0 =
|
|
{s3_ftb_entry_dup_0_tailSlot_sharing
|
|
? {(_target_T_126 ? higher_plus_one_r_13 : 28'h0)
|
|
| (_target_T_127 ? higher_minus_one_r_13 : 28'h0)
|
|
| (_target_T_128 ? higher_r_13 : 28'h0),
|
|
s3_ftb_entry_dup_0_tailSlot_lower[11:0]}
|
|
: {(_target_T_126 ? higher_plus_one_r_14 : 20'h0)
|
|
| (_target_T_127 ? higher_minus_one_r_14 : 20'h0)
|
|
| (_target_T_128 ? higher_r_14 : 20'h0),
|
|
s3_ftb_entry_dup_0_tailSlot_lower},
|
|
1'h0};
|
|
wire io_out_s3_full_pred_0_fallThroughErr_0 =
|
|
{1'h0, s3_pc_dup_0[4:1]} >= {s3_ftb_entry_dup_0_carry, s3_ftb_entry_dup_0_pftAddr};
|
|
reg [27:0] higher_r_15;
|
|
reg [27:0] higher_plus_one_r_15;
|
|
reg [27:0] higher_minus_one_r_15;
|
|
reg [27:0] higher_r_16;
|
|
reg [27:0] higher_plus_one_r_16;
|
|
reg [27:0] higher_minus_one_r_16;
|
|
wire _target_T_153 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h1;
|
|
wire _target_T_154 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h2;
|
|
wire _target_T_155 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h0;
|
|
reg [19:0] higher_r_17;
|
|
reg [19:0] higher_plus_one_r_17;
|
|
reg [19:0] higher_minus_one_r_17;
|
|
wire [40:0] io_out_s3_full_pred_1_targets_1_0 =
|
|
{s3_ftb_entry_dup_1_tailSlot_sharing
|
|
? {(_target_T_153 ? higher_plus_one_r_16 : 28'h0)
|
|
| (_target_T_154 ? higher_minus_one_r_16 : 28'h0)
|
|
| (_target_T_155 ? higher_r_16 : 28'h0),
|
|
s3_ftb_entry_dup_1_tailSlot_lower[11:0]}
|
|
: {(_target_T_153 ? higher_plus_one_r_17 : 20'h0)
|
|
| (_target_T_154 ? higher_minus_one_r_17 : 20'h0)
|
|
| (_target_T_155 ? higher_r_17 : 20'h0),
|
|
s3_ftb_entry_dup_1_tailSlot_lower},
|
|
1'h0};
|
|
wire io_out_s3_full_pred_1_fallThroughErr_0 =
|
|
{1'h0, s3_pc_dup_1[4:1]} >= {s3_ftb_entry_dup_1_carry, s3_ftb_entry_dup_1_pftAddr};
|
|
reg [27:0] higher_r_18;
|
|
reg [27:0] higher_plus_one_r_18;
|
|
reg [27:0] higher_minus_one_r_18;
|
|
reg [27:0] higher_r_19;
|
|
reg [27:0] higher_plus_one_r_19;
|
|
reg [27:0] higher_minus_one_r_19;
|
|
wire _target_T_180 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h1;
|
|
wire _target_T_181 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h2;
|
|
wire _target_T_182 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h0;
|
|
reg [19:0] higher_r_20;
|
|
reg [19:0] higher_plus_one_r_20;
|
|
reg [19:0] higher_minus_one_r_20;
|
|
wire [40:0] io_out_s3_full_pred_2_targets_1_0 =
|
|
{s3_ftb_entry_dup_2_tailSlot_sharing
|
|
? {(_target_T_180 ? higher_plus_one_r_19 : 28'h0)
|
|
| (_target_T_181 ? higher_minus_one_r_19 : 28'h0)
|
|
| (_target_T_182 ? higher_r_19 : 28'h0),
|
|
s3_ftb_entry_dup_2_tailSlot_lower[11:0]}
|
|
: {(_target_T_180 ? higher_plus_one_r_20 : 20'h0)
|
|
| (_target_T_181 ? higher_minus_one_r_20 : 20'h0)
|
|
| (_target_T_182 ? higher_r_20 : 20'h0),
|
|
s3_ftb_entry_dup_2_tailSlot_lower},
|
|
1'h0};
|
|
wire io_out_s3_full_pred_2_fallThroughErr_0 =
|
|
{1'h0, s3_pc_dup_2[4:1]} >= {s3_ftb_entry_dup_2_carry, s3_ftb_entry_dup_2_pftAddr};
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|
reg [27:0] higher_r_21;
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reg [27:0] higher_plus_one_r_21;
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reg [27:0] higher_minus_one_r_21;
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|
reg [27:0] higher_r_22;
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reg [27:0] higher_plus_one_r_22;
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reg [27:0] higher_minus_one_r_22;
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wire _target_T_207 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h1;
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|
wire _target_T_208 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h2;
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wire _target_T_209 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h0;
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reg [19:0] higher_r_23;
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reg [19:0] higher_plus_one_r_23;
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reg [19:0] higher_minus_one_r_23;
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wire [40:0] io_out_s3_full_pred_3_targets_1_0 =
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{s3_ftb_entry_dup_3_tailSlot_sharing
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? {(_target_T_207 ? higher_plus_one_r_22 : 28'h0)
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| (_target_T_208 ? higher_minus_one_r_22 : 28'h0)
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| (_target_T_209 ? higher_r_22 : 28'h0),
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s3_ftb_entry_dup_3_tailSlot_lower[11:0]}
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: {(_target_T_207 ? higher_plus_one_r_23 : 20'h0)
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| (_target_T_208 ? higher_minus_one_r_23 : 20'h0)
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| (_target_T_209 ? higher_r_23 : 20'h0),
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s3_ftb_entry_dup_3_tailSlot_lower},
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1'h0};
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wire io_out_s3_full_pred_3_fallThroughErr_0 =
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{1'h0, s3_pc_dup_3[4:1]} >= {s3_ftb_entry_dup_3_carry, s3_ftb_entry_dup_3_pftAddr};
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reg [2:0] io_out_last_stage_meta_r;
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reg [2:0] io_out_last_stage_meta_r_1;
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wire u_valid = io_update_valid & ~io_update_bits_old_entry;
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wire update_now = u_valid & io_update_bits_meta[0];
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wire update_need_read = u_valid & ~(io_update_bits_meta[0]);
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reg io_s1_ready_REG;
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wire [40:0] _ftbBank_io_update_pc_T =
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update_now ? io_update_bits_pc : _delay2_pc_pipMod_io_out_bits;
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reg [1:0] ftbBank_io_update_write_way_REG;
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reg ftbBank_io_update_write_alloc_REG;
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reg io_perf_0_value_REG;
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reg io_perf_0_value_REG_1;
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reg io_perf_1_value_REG;
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reg io_perf_1_value_REG_1;
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wire [40:0] _GEN = {5'h0, _reset_vector_delay_io_out};
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always @(posedge clock) begin
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|
if (REG_1) begin
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|
s1_pc_dup_0 <= _GEN;
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s1_pc_dup_1 <= _GEN;
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s1_pc_dup_2 <= _GEN;
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s1_pc_dup_3 <= _GEN;
|
|
end
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|
else begin
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|
if (io_s0_fire_0)
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|
s1_pc_dup_0 <= io_in_bits_s0_pc_0;
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if (io_s0_fire_1)
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|
s1_pc_dup_1 <= io_in_bits_s0_pc_1;
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if (io_s0_fire_2)
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s1_pc_dup_2 <= io_in_bits_s0_pc_2;
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if (io_s0_fire_3)
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s1_pc_dup_3 <= io_in_bits_s0_pc_3;
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|
end
|
|
if (io_s1_fire_0) begin
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|
s2_pc_dup_0 <= s1_pc_dup_0;
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s2_ftb_entry_dup_0_valid <= _ftbBank_io_read_resp_valid;
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s2_ftb_entry_dup_0_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset;
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|
s2_ftb_entry_dup_0_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower;
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|
s2_ftb_entry_dup_0_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat;
|
|
s2_ftb_entry_dup_0_brSlots_0_sharing <= _ftbBank_io_read_resp_brSlots_0_sharing;
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|
s2_ftb_entry_dup_0_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid;
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|
s2_ftb_entry_dup_0_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset;
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|
s2_ftb_entry_dup_0_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower;
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|
s2_ftb_entry_dup_0_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat;
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|
s2_ftb_entry_dup_0_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing;
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|
s2_ftb_entry_dup_0_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid;
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|
s2_ftb_entry_dup_0_pftAddr <= _ftbBank_io_read_resp_pftAddr;
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|
s2_ftb_entry_dup_0_carry <= _ftbBank_io_read_resp_carry;
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|
s2_ftb_entry_dup_0_isCall <= _ftbBank_io_read_resp_isCall;
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|
s2_ftb_entry_dup_0_isRet <= _ftbBank_io_read_resp_isRet;
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|
s2_ftb_entry_dup_0_isJalr <= _ftbBank_io_read_resp_isJalr;
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|
s2_ftb_entry_dup_0_last_may_be_rvi_call <=
|
|
_ftbBank_io_read_resp_last_may_be_rvi_call;
|
|
s2_ftb_entry_dup_0_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0;
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|
s2_ftb_entry_dup_0_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1;
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|
higher_r <= s1_pc_dup_0[40:13];
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|
higher_plus_one_r <= 28'(s1_pc_dup_0[40:13] + 28'h1);
|
|
higher_minus_one_r <= 28'(s1_pc_dup_0[40:13] - 28'h1);
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|
higher_r_1 <= s1_pc_dup_0[40:13];
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|
higher_plus_one_r_1 <= 28'(s1_pc_dup_0[40:13] + 28'h1);
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|
higher_minus_one_r_1 <= 28'(s1_pc_dup_0[40:13] - 28'h1);
|
|
higher_r_2 <= s1_pc_dup_0[40:21];
|
|
higher_plus_one_r_2 <= 20'(s1_pc_dup_0[40:21] + 20'h1);
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|
higher_minus_one_r_2 <= 20'(s1_pc_dup_0[40:21] - 20'h1);
|
|
io_out_s2_full_pred_0_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry;
|
|
io_out_last_stage_meta_r <= {_ftbBank_io_read_hits_bits, s1_hit};
|
|
end
|
|
if (io_s1_fire_1) begin
|
|
s2_pc_dup_1 <= s1_pc_dup_1;
|
|
s2_ftb_entry_dup_1_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset;
|
|
s2_ftb_entry_dup_1_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower;
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|
s2_ftb_entry_dup_1_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat;
|
|
s2_ftb_entry_dup_1_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid;
|
|
s2_ftb_entry_dup_1_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset;
|
|
s2_ftb_entry_dup_1_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower;
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|
s2_ftb_entry_dup_1_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat;
|
|
s2_ftb_entry_dup_1_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing;
|
|
s2_ftb_entry_dup_1_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid;
|
|
s2_ftb_entry_dup_1_pftAddr <= _ftbBank_io_read_resp_pftAddr;
|
|
s2_ftb_entry_dup_1_carry <= _ftbBank_io_read_resp_carry;
|
|
s2_ftb_entry_dup_1_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0;
|
|
s2_ftb_entry_dup_1_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1;
|
|
higher_r_3 <= s1_pc_dup_1[40:13];
|
|
higher_plus_one_r_3 <= 28'(s1_pc_dup_1[40:13] + 28'h1);
|
|
higher_minus_one_r_3 <= 28'(s1_pc_dup_1[40:13] - 28'h1);
|
|
higher_r_4 <= s1_pc_dup_1[40:13];
|
|
higher_plus_one_r_4 <= 28'(s1_pc_dup_1[40:13] + 28'h1);
|
|
higher_minus_one_r_4 <= 28'(s1_pc_dup_1[40:13] - 28'h1);
|
|
higher_r_5 <= s1_pc_dup_1[40:21];
|
|
higher_plus_one_r_5 <= 20'(s1_pc_dup_1[40:21] + 20'h1);
|
|
higher_minus_one_r_5 <= 20'(s1_pc_dup_1[40:21] - 20'h1);
|
|
io_out_s2_full_pred_1_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry;
|
|
end
|
|
if (io_s1_fire_2) begin
|
|
s2_pc_dup_2 <= s1_pc_dup_2;
|
|
s2_ftb_entry_dup_2_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset;
|
|
s2_ftb_entry_dup_2_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower;
|
|
s2_ftb_entry_dup_2_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat;
|
|
s2_ftb_entry_dup_2_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid;
|
|
s2_ftb_entry_dup_2_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset;
|
|
s2_ftb_entry_dup_2_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower;
|
|
s2_ftb_entry_dup_2_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat;
|
|
s2_ftb_entry_dup_2_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing;
|
|
s2_ftb_entry_dup_2_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid;
|
|
s2_ftb_entry_dup_2_pftAddr <= _ftbBank_io_read_resp_pftAddr;
|
|
s2_ftb_entry_dup_2_carry <= _ftbBank_io_read_resp_carry;
|
|
s2_ftb_entry_dup_2_isCall <= _ftbBank_io_read_resp_isCall;
|
|
s2_ftb_entry_dup_2_isRet <= _ftbBank_io_read_resp_isRet;
|
|
s2_ftb_entry_dup_2_isJalr <= _ftbBank_io_read_resp_isJalr;
|
|
s2_ftb_entry_dup_2_last_may_be_rvi_call <=
|
|
_ftbBank_io_read_resp_last_may_be_rvi_call;
|
|
s2_ftb_entry_dup_2_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0;
|
|
s2_ftb_entry_dup_2_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1;
|
|
higher_r_6 <= s1_pc_dup_2[40:13];
|
|
higher_plus_one_r_6 <= 28'(s1_pc_dup_2[40:13] + 28'h1);
|
|
higher_minus_one_r_6 <= 28'(s1_pc_dup_2[40:13] - 28'h1);
|
|
higher_r_7 <= s1_pc_dup_2[40:13];
|
|
higher_plus_one_r_7 <= 28'(s1_pc_dup_2[40:13] + 28'h1);
|
|
higher_minus_one_r_7 <= 28'(s1_pc_dup_2[40:13] - 28'h1);
|
|
higher_r_8 <= s1_pc_dup_2[40:21];
|
|
higher_plus_one_r_8 <= 20'(s1_pc_dup_2[40:21] + 20'h1);
|
|
higher_minus_one_r_8 <= 20'(s1_pc_dup_2[40:21] - 20'h1);
|
|
io_out_s2_full_pred_2_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry;
|
|
end
|
|
if (io_s1_fire_3) begin
|
|
s2_pc_dup_3 <= s1_pc_dup_3;
|
|
s2_ftb_entry_dup_3_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset;
|
|
s2_ftb_entry_dup_3_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower;
|
|
s2_ftb_entry_dup_3_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat;
|
|
s2_ftb_entry_dup_3_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid;
|
|
s2_ftb_entry_dup_3_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset;
|
|
s2_ftb_entry_dup_3_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower;
|
|
s2_ftb_entry_dup_3_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat;
|
|
s2_ftb_entry_dup_3_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing;
|
|
s2_ftb_entry_dup_3_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid;
|
|
s2_ftb_entry_dup_3_pftAddr <= _ftbBank_io_read_resp_pftAddr;
|
|
s2_ftb_entry_dup_3_carry <= _ftbBank_io_read_resp_carry;
|
|
s2_ftb_entry_dup_3_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0;
|
|
s2_ftb_entry_dup_3_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1;
|
|
higher_r_9 <= s1_pc_dup_3[40:13];
|
|
higher_plus_one_r_9 <= 28'(s1_pc_dup_3[40:13] + 28'h1);
|
|
higher_minus_one_r_9 <= 28'(s1_pc_dup_3[40:13] - 28'h1);
|
|
higher_r_10 <= s1_pc_dup_3[40:13];
|
|
higher_plus_one_r_10 <= 28'(s1_pc_dup_3[40:13] + 28'h1);
|
|
higher_minus_one_r_10 <= 28'(s1_pc_dup_3[40:13] - 28'h1);
|
|
higher_r_11 <= s1_pc_dup_3[40:21];
|
|
higher_plus_one_r_11 <= 20'(s1_pc_dup_3[40:21] + 20'h1);
|
|
higher_minus_one_r_11 <= 20'(s1_pc_dup_3[40:21] - 20'h1);
|
|
io_out_s2_full_pred_3_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry;
|
|
end
|
|
if (io_s2_fire_0) begin
|
|
s3_pc_dup_0 <= s2_pc_dup_0;
|
|
s3_ftb_entry_dup_0_valid <= s2_ftb_entry_dup_0_valid;
|
|
s3_ftb_entry_dup_0_brSlots_0_offset <= s2_ftb_entry_dup_0_brSlots_0_offset;
|
|
s3_ftb_entry_dup_0_brSlots_0_lower <= s2_ftb_entry_dup_0_brSlots_0_lower;
|
|
s3_ftb_entry_dup_0_brSlots_0_tarStat <= s2_ftb_entry_dup_0_brSlots_0_tarStat;
|
|
s3_ftb_entry_dup_0_brSlots_0_sharing <= s2_ftb_entry_dup_0_brSlots_0_sharing;
|
|
s3_ftb_entry_dup_0_brSlots_0_valid <= s2_ftb_entry_dup_0_brSlots_0_valid;
|
|
s3_ftb_entry_dup_0_tailSlot_offset <= s2_ftb_entry_dup_0_tailSlot_offset;
|
|
s3_ftb_entry_dup_0_tailSlot_lower <= s2_ftb_entry_dup_0_tailSlot_lower;
|
|
s3_ftb_entry_dup_0_tailSlot_tarStat <= s2_ftb_entry_dup_0_tailSlot_tarStat;
|
|
s3_ftb_entry_dup_0_tailSlot_sharing <= s2_ftb_entry_dup_0_tailSlot_sharing;
|
|
s3_ftb_entry_dup_0_tailSlot_valid <= s2_ftb_entry_dup_0_tailSlot_valid;
|
|
s3_ftb_entry_dup_0_pftAddr <= s2_ftb_entry_dup_0_pftAddr;
|
|
s3_ftb_entry_dup_0_carry <= s2_ftb_entry_dup_0_carry;
|
|
s3_ftb_entry_dup_0_isCall <= s2_ftb_entry_dup_0_isCall;
|
|
s3_ftb_entry_dup_0_isRet <= s2_ftb_entry_dup_0_isRet;
|
|
s3_ftb_entry_dup_0_isJalr <= s2_ftb_entry_dup_0_isJalr;
|
|
s3_ftb_entry_dup_0_last_may_be_rvi_call <= s2_ftb_entry_dup_0_last_may_be_rvi_call;
|
|
s3_ftb_entry_dup_0_always_taken_0 <= s2_ftb_entry_dup_0_always_taken_0;
|
|
s3_ftb_entry_dup_0_always_taken_1 <= s2_ftb_entry_dup_0_always_taken_1;
|
|
higher_r_12 <= s2_pc_dup_0[40:13];
|
|
higher_plus_one_r_12 <= 28'(s2_pc_dup_0[40:13] + 28'h1);
|
|
higher_minus_one_r_12 <= 28'(s2_pc_dup_0[40:13] - 28'h1);
|
|
higher_r_13 <= s2_pc_dup_0[40:13];
|
|
higher_plus_one_r_13 <= 28'(s2_pc_dup_0[40:13] + 28'h1);
|
|
higher_minus_one_r_13 <= 28'(s2_pc_dup_0[40:13] - 28'h1);
|
|
higher_r_14 <= s2_pc_dup_0[40:21];
|
|
higher_plus_one_r_14 <= 20'(s2_pc_dup_0[40:21] + 20'h1);
|
|
higher_minus_one_r_14 <= 20'(s2_pc_dup_0[40:21] - 20'h1);
|
|
io_out_last_stage_meta_r_1 <= io_out_last_stage_meta_r;
|
|
end
|
|
if (io_s2_fire_1) begin
|
|
s3_pc_dup_1 <= s2_pc_dup_1;
|
|
s3_ftb_entry_dup_1_brSlots_0_lower <= s2_ftb_entry_dup_1_brSlots_0_lower;
|
|
s3_ftb_entry_dup_1_brSlots_0_tarStat <= s2_ftb_entry_dup_1_brSlots_0_tarStat;
|
|
s3_ftb_entry_dup_1_brSlots_0_valid <= s2_ftb_entry_dup_1_brSlots_0_valid;
|
|
s3_ftb_entry_dup_1_tailSlot_lower <= s2_ftb_entry_dup_1_tailSlot_lower;
|
|
s3_ftb_entry_dup_1_tailSlot_tarStat <= s2_ftb_entry_dup_1_tailSlot_tarStat;
|
|
s3_ftb_entry_dup_1_tailSlot_sharing <= s2_ftb_entry_dup_1_tailSlot_sharing;
|
|
s3_ftb_entry_dup_1_tailSlot_valid <= s2_ftb_entry_dup_1_tailSlot_valid;
|
|
s3_ftb_entry_dup_1_pftAddr <= s2_ftb_entry_dup_1_pftAddr;
|
|
s3_ftb_entry_dup_1_carry <= s2_ftb_entry_dup_1_carry;
|
|
s3_ftb_entry_dup_1_always_taken_0 <= s2_ftb_entry_dup_1_always_taken_0;
|
|
s3_ftb_entry_dup_1_always_taken_1 <= s2_ftb_entry_dup_1_always_taken_1;
|
|
higher_r_15 <= s2_pc_dup_1[40:13];
|
|
higher_plus_one_r_15 <= 28'(s2_pc_dup_1[40:13] + 28'h1);
|
|
higher_minus_one_r_15 <= 28'(s2_pc_dup_1[40:13] - 28'h1);
|
|
higher_r_16 <= s2_pc_dup_1[40:13];
|
|
higher_plus_one_r_16 <= 28'(s2_pc_dup_1[40:13] + 28'h1);
|
|
higher_minus_one_r_16 <= 28'(s2_pc_dup_1[40:13] - 28'h1);
|
|
higher_r_17 <= s2_pc_dup_1[40:21];
|
|
higher_plus_one_r_17 <= 20'(s2_pc_dup_1[40:21] + 20'h1);
|
|
higher_minus_one_r_17 <= 20'(s2_pc_dup_1[40:21] - 20'h1);
|
|
end
|
|
if (io_s2_fire_2) begin
|
|
s3_pc_dup_2 <= s2_pc_dup_2;
|
|
s3_ftb_entry_dup_2_brSlots_0_lower <= s2_ftb_entry_dup_2_brSlots_0_lower;
|
|
s3_ftb_entry_dup_2_brSlots_0_tarStat <= s2_ftb_entry_dup_2_brSlots_0_tarStat;
|
|
s3_ftb_entry_dup_2_brSlots_0_valid <= s2_ftb_entry_dup_2_brSlots_0_valid;
|
|
s3_ftb_entry_dup_2_tailSlot_lower <= s2_ftb_entry_dup_2_tailSlot_lower;
|
|
s3_ftb_entry_dup_2_tailSlot_tarStat <= s2_ftb_entry_dup_2_tailSlot_tarStat;
|
|
s3_ftb_entry_dup_2_tailSlot_sharing <= s2_ftb_entry_dup_2_tailSlot_sharing;
|
|
s3_ftb_entry_dup_2_tailSlot_valid <= s2_ftb_entry_dup_2_tailSlot_valid;
|
|
s3_ftb_entry_dup_2_pftAddr <= s2_ftb_entry_dup_2_pftAddr;
|
|
s3_ftb_entry_dup_2_carry <= s2_ftb_entry_dup_2_carry;
|
|
s3_ftb_entry_dup_2_isCall <= s2_ftb_entry_dup_2_isCall;
|
|
s3_ftb_entry_dup_2_isRet <= s2_ftb_entry_dup_2_isRet;
|
|
s3_ftb_entry_dup_2_isJalr <= s2_ftb_entry_dup_2_isJalr;
|
|
s3_ftb_entry_dup_2_always_taken_0 <= s2_ftb_entry_dup_2_always_taken_0;
|
|
s3_ftb_entry_dup_2_always_taken_1 <= s2_ftb_entry_dup_2_always_taken_1;
|
|
higher_r_18 <= s2_pc_dup_2[40:13];
|
|
higher_plus_one_r_18 <= 28'(s2_pc_dup_2[40:13] + 28'h1);
|
|
higher_minus_one_r_18 <= 28'(s2_pc_dup_2[40:13] - 28'h1);
|
|
higher_r_19 <= s2_pc_dup_2[40:13];
|
|
higher_plus_one_r_19 <= 28'(s2_pc_dup_2[40:13] + 28'h1);
|
|
higher_minus_one_r_19 <= 28'(s2_pc_dup_2[40:13] - 28'h1);
|
|
higher_r_20 <= s2_pc_dup_2[40:21];
|
|
higher_plus_one_r_20 <= 20'(s2_pc_dup_2[40:21] + 20'h1);
|
|
higher_minus_one_r_20 <= 20'(s2_pc_dup_2[40:21] - 20'h1);
|
|
end
|
|
if (io_s2_fire_3) begin
|
|
s3_pc_dup_3 <= s2_pc_dup_3;
|
|
s3_ftb_entry_dup_3_brSlots_0_offset <= s2_ftb_entry_dup_3_brSlots_0_offset;
|
|
s3_ftb_entry_dup_3_brSlots_0_lower <= s2_ftb_entry_dup_3_brSlots_0_lower;
|
|
s3_ftb_entry_dup_3_brSlots_0_tarStat <= s2_ftb_entry_dup_3_brSlots_0_tarStat;
|
|
s3_ftb_entry_dup_3_brSlots_0_valid <= s2_ftb_entry_dup_3_brSlots_0_valid;
|
|
s3_ftb_entry_dup_3_tailSlot_offset <= s2_ftb_entry_dup_3_tailSlot_offset;
|
|
s3_ftb_entry_dup_3_tailSlot_lower <= s2_ftb_entry_dup_3_tailSlot_lower;
|
|
s3_ftb_entry_dup_3_tailSlot_tarStat <= s2_ftb_entry_dup_3_tailSlot_tarStat;
|
|
s3_ftb_entry_dup_3_tailSlot_sharing <= s2_ftb_entry_dup_3_tailSlot_sharing;
|
|
s3_ftb_entry_dup_3_tailSlot_valid <= s2_ftb_entry_dup_3_tailSlot_valid;
|
|
s3_ftb_entry_dup_3_pftAddr <= s2_ftb_entry_dup_3_pftAddr;
|
|
s3_ftb_entry_dup_3_carry <= s2_ftb_entry_dup_3_carry;
|
|
s3_ftb_entry_dup_3_always_taken_0 <= s2_ftb_entry_dup_3_always_taken_0;
|
|
s3_ftb_entry_dup_3_always_taken_1 <= s2_ftb_entry_dup_3_always_taken_1;
|
|
higher_r_21 <= s2_pc_dup_3[40:13];
|
|
higher_plus_one_r_21 <= 28'(s2_pc_dup_3[40:13] + 28'h1);
|
|
higher_minus_one_r_21 <= 28'(s2_pc_dup_3[40:13] - 28'h1);
|
|
higher_r_22 <= s2_pc_dup_3[40:13];
|
|
higher_plus_one_r_22 <= 28'(s2_pc_dup_3[40:13] + 28'h1);
|
|
higher_minus_one_r_22 <= 28'(s2_pc_dup_3[40:13] - 28'h1);
|
|
higher_r_23 <= s2_pc_dup_3[40:21];
|
|
higher_plus_one_r_23 <= 20'(s2_pc_dup_3[40:21] + 20'h1);
|
|
higher_minus_one_r_23 <= 20'(s2_pc_dup_3[40:21] - 20'h1);
|
|
end
|
|
REG <= reset;
|
|
REG_1 <= REG & ~reset;
|
|
io_s1_ready_REG <= update_need_read;
|
|
ftbBank_io_update_write_way_REG <= _ftbBank_io_update_hits_bits;
|
|
ftbBank_io_update_write_alloc_REG <= ~_ftbBank_io_update_hits_valid;
|
|
io_perf_0_value_REG <= io_update_valid & io_update_bits_meta[0];
|
|
io_perf_0_value_REG_1 <= io_perf_0_value_REG;
|
|
io_perf_1_value_REG <= io_update_valid & ~(io_update_bits_meta[0]);
|
|
io_perf_1_value_REG_1 <= io_perf_1_value_REG;
|
|
end // always @(posedge)
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
s2_hit_dup_0 <= 1'h0;
|
|
s2_hit_dup_1 <= 1'h0;
|
|
s2_hit_dup_2 <= 1'h0;
|
|
s2_hit_dup_3 <= 1'h0;
|
|
s3_hit_dup_0 <= 1'h0;
|
|
s3_hit_dup_1 <= 1'h0;
|
|
s3_hit_dup_2 <= 1'h0;
|
|
s3_hit_dup_3 <= 1'h0;
|
|
end
|
|
else begin
|
|
if (io_s1_fire_0)
|
|
s2_hit_dup_0 <= s1_hit;
|
|
if (io_s1_fire_1)
|
|
s2_hit_dup_1 <= s1_hit;
|
|
if (io_s1_fire_2)
|
|
s2_hit_dup_2 <= s1_hit;
|
|
if (io_s1_fire_3)
|
|
s2_hit_dup_3 <= s1_hit;
|
|
if (io_s2_fire_0)
|
|
s3_hit_dup_0 <= s2_hit_dup_0;
|
|
if (io_s2_fire_1)
|
|
s3_hit_dup_1 <= s2_hit_dup_1;
|
|
if (io_s2_fire_2)
|
|
s3_hit_dup_2 <= s2_hit_dup_2;
|
|
if (io_s2_fire_3)
|
|
s3_hit_dup_3 <= s2_hit_dup_3;
|
|
end
|
|
end // always @(posedge, posedge)
|
|
`ifdef ENABLE_INITIAL_REG_
|
|
`ifdef FIRRTL_BEFORE_INITIAL
|
|
`FIRRTL_BEFORE_INITIAL
|
|
`endif // FIRRTL_BEFORE_INITIAL
|
|
logic [31:0] _RANDOM[0:90];
|
|
initial begin
|
|
`ifdef INIT_RANDOM_PROLOG_
|
|
`INIT_RANDOM_PROLOG_
|
|
`endif // INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
for (logic [6:0] i = 7'h0; i < 7'h5B; i += 7'h1) begin
|
|
_RANDOM[i] = `RANDOM;
|
|
end
|
|
s1_pc_dup_0 = {_RANDOM[7'h0], _RANDOM[7'h1][8:0]};
|
|
s1_pc_dup_1 = {_RANDOM[7'h1][31:9], _RANDOM[7'h2][17:0]};
|
|
s1_pc_dup_2 = {_RANDOM[7'h2][31:18], _RANDOM[7'h3][26:0]};
|
|
s1_pc_dup_3 = {_RANDOM[7'h3][31:27], _RANDOM[7'h4], _RANDOM[7'h5][3:0]};
|
|
s2_pc_dup_0 = {_RANDOM[7'h5][31:4], _RANDOM[7'h6][12:0]};
|
|
s2_pc_dup_1 = {_RANDOM[7'h6][31:13], _RANDOM[7'h7][21:0]};
|
|
s2_pc_dup_2 = {_RANDOM[7'h7][31:22], _RANDOM[7'h8][30:0]};
|
|
s2_pc_dup_3 = {_RANDOM[7'h8][31], _RANDOM[7'h9], _RANDOM[7'hA][7:0]};
|
|
s3_pc_dup_0 = {_RANDOM[7'hA][31:8], _RANDOM[7'hB][16:0]};
|
|
s3_pc_dup_1 = {_RANDOM[7'hB][31:17], _RANDOM[7'hC][25:0]};
|
|
s3_pc_dup_2 = {_RANDOM[7'hC][31:26], _RANDOM[7'hD], _RANDOM[7'hE][2:0]};
|
|
s3_pc_dup_3 = {_RANDOM[7'hE][31:3], _RANDOM[7'hF][11:0]};
|
|
REG = _RANDOM[7'hF][12];
|
|
REG_1 = _RANDOM[7'hF][13];
|
|
s2_ftb_entry_dup_0_valid = _RANDOM[7'hF][15];
|
|
s2_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'hF][19:16];
|
|
s2_ftb_entry_dup_0_brSlots_0_lower = _RANDOM[7'hF][31:20];
|
|
s2_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'h10][1:0];
|
|
s2_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'h10][2];
|
|
s2_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'h10][3];
|
|
s2_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'h10][7:4];
|
|
s2_ftb_entry_dup_0_tailSlot_lower = _RANDOM[7'h10][27:8];
|
|
s2_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h10][29:28];
|
|
s2_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h10][30];
|
|
s2_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h10][31];
|
|
s2_ftb_entry_dup_0_pftAddr = _RANDOM[7'h11][3:0];
|
|
s2_ftb_entry_dup_0_carry = _RANDOM[7'h11][4];
|
|
s2_ftb_entry_dup_0_isCall = _RANDOM[7'h11][5];
|
|
s2_ftb_entry_dup_0_isRet = _RANDOM[7'h11][6];
|
|
s2_ftb_entry_dup_0_isJalr = _RANDOM[7'h11][7];
|
|
s2_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h11][8];
|
|
s2_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h11][9];
|
|
s2_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h11][10];
|
|
s2_ftb_entry_dup_1_brSlots_0_offset = _RANDOM[7'h11][15:12];
|
|
s2_ftb_entry_dup_1_brSlots_0_lower = _RANDOM[7'h11][27:16];
|
|
s2_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h11][29:28];
|
|
s2_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h11][31];
|
|
s2_ftb_entry_dup_1_tailSlot_offset = _RANDOM[7'h12][3:0];
|
|
s2_ftb_entry_dup_1_tailSlot_lower = _RANDOM[7'h12][23:4];
|
|
s2_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h12][25:24];
|
|
s2_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h12][26];
|
|
s2_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h12][27];
|
|
s2_ftb_entry_dup_1_pftAddr = _RANDOM[7'h12][31:28];
|
|
s2_ftb_entry_dup_1_carry = _RANDOM[7'h13][0];
|
|
s2_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h13][5];
|
|
s2_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h13][6];
|
|
s2_ftb_entry_dup_2_brSlots_0_offset = _RANDOM[7'h13][11:8];
|
|
s2_ftb_entry_dup_2_brSlots_0_lower = _RANDOM[7'h13][23:12];
|
|
s2_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h13][25:24];
|
|
s2_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h13][27];
|
|
s2_ftb_entry_dup_2_tailSlot_offset = _RANDOM[7'h13][31:28];
|
|
s2_ftb_entry_dup_2_tailSlot_lower = _RANDOM[7'h14][19:0];
|
|
s2_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h14][21:20];
|
|
s2_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h14][22];
|
|
s2_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h14][23];
|
|
s2_ftb_entry_dup_2_pftAddr = _RANDOM[7'h14][27:24];
|
|
s2_ftb_entry_dup_2_carry = _RANDOM[7'h14][28];
|
|
s2_ftb_entry_dup_2_isCall = _RANDOM[7'h14][29];
|
|
s2_ftb_entry_dup_2_isRet = _RANDOM[7'h14][30];
|
|
s2_ftb_entry_dup_2_isJalr = _RANDOM[7'h14][31];
|
|
s2_ftb_entry_dup_2_last_may_be_rvi_call = _RANDOM[7'h15][0];
|
|
s2_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h15][1];
|
|
s2_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h15][2];
|
|
s2_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h15][7:4];
|
|
s2_ftb_entry_dup_3_brSlots_0_lower = _RANDOM[7'h15][19:8];
|
|
s2_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h15][21:20];
|
|
s2_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h15][23];
|
|
s2_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h15][27:24];
|
|
s2_ftb_entry_dup_3_tailSlot_lower = {_RANDOM[7'h15][31:28], _RANDOM[7'h16][15:0]};
|
|
s2_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h16][17:16];
|
|
s2_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h16][18];
|
|
s2_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h16][19];
|
|
s2_ftb_entry_dup_3_pftAddr = _RANDOM[7'h16][23:20];
|
|
s2_ftb_entry_dup_3_carry = _RANDOM[7'h16][24];
|
|
s2_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h16][29];
|
|
s2_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h16][30];
|
|
s3_ftb_entry_dup_0_valid = _RANDOM[7'h16][31];
|
|
s3_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'h17][3:0];
|
|
s3_ftb_entry_dup_0_brSlots_0_lower = _RANDOM[7'h17][15:4];
|
|
s3_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'h17][17:16];
|
|
s3_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'h17][18];
|
|
s3_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'h17][19];
|
|
s3_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'h17][23:20];
|
|
s3_ftb_entry_dup_0_tailSlot_lower = {_RANDOM[7'h17][31:24], _RANDOM[7'h18][11:0]};
|
|
s3_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h18][13:12];
|
|
s3_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h18][14];
|
|
s3_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h18][15];
|
|
s3_ftb_entry_dup_0_pftAddr = _RANDOM[7'h18][19:16];
|
|
s3_ftb_entry_dup_0_carry = _RANDOM[7'h18][20];
|
|
s3_ftb_entry_dup_0_isCall = _RANDOM[7'h18][21];
|
|
s3_ftb_entry_dup_0_isRet = _RANDOM[7'h18][22];
|
|
s3_ftb_entry_dup_0_isJalr = _RANDOM[7'h18][23];
|
|
s3_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h18][24];
|
|
s3_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h18][25];
|
|
s3_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h18][26];
|
|
s3_ftb_entry_dup_1_brSlots_0_lower = _RANDOM[7'h19][11:0];
|
|
s3_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h19][13:12];
|
|
s3_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h19][15];
|
|
s3_ftb_entry_dup_1_tailSlot_lower = {_RANDOM[7'h19][31:20], _RANDOM[7'h1A][7:0]};
|
|
s3_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h1A][9:8];
|
|
s3_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h1A][10];
|
|
s3_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h1A][11];
|
|
s3_ftb_entry_dup_1_pftAddr = _RANDOM[7'h1A][15:12];
|
|
s3_ftb_entry_dup_1_carry = _RANDOM[7'h1A][16];
|
|
s3_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h1A][21];
|
|
s3_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h1A][22];
|
|
s3_ftb_entry_dup_2_brSlots_0_lower = {_RANDOM[7'h1A][31:28], _RANDOM[7'h1B][7:0]};
|
|
s3_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h1B][9:8];
|
|
s3_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h1B][11];
|
|
s3_ftb_entry_dup_2_tailSlot_lower = {_RANDOM[7'h1B][31:16], _RANDOM[7'h1C][3:0]};
|
|
s3_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h1C][5:4];
|
|
s3_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h1C][6];
|
|
s3_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h1C][7];
|
|
s3_ftb_entry_dup_2_pftAddr = _RANDOM[7'h1C][11:8];
|
|
s3_ftb_entry_dup_2_carry = _RANDOM[7'h1C][12];
|
|
s3_ftb_entry_dup_2_isCall = _RANDOM[7'h1C][13];
|
|
s3_ftb_entry_dup_2_isRet = _RANDOM[7'h1C][14];
|
|
s3_ftb_entry_dup_2_isJalr = _RANDOM[7'h1C][15];
|
|
s3_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h1C][17];
|
|
s3_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h1C][18];
|
|
s3_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h1C][23:20];
|
|
s3_ftb_entry_dup_3_brSlots_0_lower = {_RANDOM[7'h1C][31:24], _RANDOM[7'h1D][3:0]};
|
|
s3_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h1D][5:4];
|
|
s3_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h1D][7];
|
|
s3_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h1D][11:8];
|
|
s3_ftb_entry_dup_3_tailSlot_lower = _RANDOM[7'h1D][31:12];
|
|
s3_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h1E][1:0];
|
|
s3_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h1E][2];
|
|
s3_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h1E][3];
|
|
s3_ftb_entry_dup_3_pftAddr = _RANDOM[7'h1E][7:4];
|
|
s3_ftb_entry_dup_3_carry = _RANDOM[7'h1E][8];
|
|
s3_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h1E][13];
|
|
s3_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h1E][14];
|
|
s2_hit_dup_0 = _RANDOM[7'h1E][15];
|
|
s2_hit_dup_1 = _RANDOM[7'h1E][16];
|
|
s2_hit_dup_2 = _RANDOM[7'h1E][17];
|
|
s2_hit_dup_3 = _RANDOM[7'h1E][18];
|
|
s3_hit_dup_0 = _RANDOM[7'h1E][19];
|
|
s3_hit_dup_1 = _RANDOM[7'h1E][20];
|
|
s3_hit_dup_2 = _RANDOM[7'h1E][21];
|
|
s3_hit_dup_3 = _RANDOM[7'h1E][22];
|
|
higher_r = {_RANDOM[7'h1E][31:23], _RANDOM[7'h1F][18:0]};
|
|
higher_plus_one_r = {_RANDOM[7'h1F][31:19], _RANDOM[7'h20][14:0]};
|
|
higher_minus_one_r = {_RANDOM[7'h20][31:15], _RANDOM[7'h21][10:0]};
|
|
higher_r_1 = {_RANDOM[7'h21][31:11], _RANDOM[7'h22][6:0]};
|
|
higher_plus_one_r_1 = {_RANDOM[7'h22][31:7], _RANDOM[7'h23][2:0]};
|
|
higher_minus_one_r_1 = _RANDOM[7'h23][30:3];
|
|
higher_r_2 = {_RANDOM[7'h23][31], _RANDOM[7'h24][18:0]};
|
|
higher_plus_one_r_2 = {_RANDOM[7'h24][31:19], _RANDOM[7'h25][6:0]};
|
|
higher_minus_one_r_2 = _RANDOM[7'h25][26:7];
|
|
io_out_s2_full_pred_0_fallThroughAddr_stashed_carry = _RANDOM[7'h25][27];
|
|
higher_r_3 = {_RANDOM[7'h25][31:28], _RANDOM[7'h26][23:0]};
|
|
higher_plus_one_r_3 = {_RANDOM[7'h26][31:24], _RANDOM[7'h27][19:0]};
|
|
higher_minus_one_r_3 = {_RANDOM[7'h27][31:20], _RANDOM[7'h28][15:0]};
|
|
higher_r_4 = {_RANDOM[7'h28][31:16], _RANDOM[7'h29][11:0]};
|
|
higher_plus_one_r_4 = {_RANDOM[7'h29][31:12], _RANDOM[7'h2A][7:0]};
|
|
higher_minus_one_r_4 = {_RANDOM[7'h2A][31:8], _RANDOM[7'h2B][3:0]};
|
|
higher_r_5 = _RANDOM[7'h2B][23:4];
|
|
higher_plus_one_r_5 = {_RANDOM[7'h2B][31:24], _RANDOM[7'h2C][11:0]};
|
|
higher_minus_one_r_5 = _RANDOM[7'h2C][31:12];
|
|
io_out_s2_full_pred_1_fallThroughAddr_stashed_carry = _RANDOM[7'h2D][0];
|
|
higher_r_6 = _RANDOM[7'h2D][28:1];
|
|
higher_plus_one_r_6 = {_RANDOM[7'h2D][31:29], _RANDOM[7'h2E][24:0]};
|
|
higher_minus_one_r_6 = {_RANDOM[7'h2E][31:25], _RANDOM[7'h2F][20:0]};
|
|
higher_r_7 = {_RANDOM[7'h2F][31:21], _RANDOM[7'h30][16:0]};
|
|
higher_plus_one_r_7 = {_RANDOM[7'h30][31:17], _RANDOM[7'h31][12:0]};
|
|
higher_minus_one_r_7 = {_RANDOM[7'h31][31:13], _RANDOM[7'h32][8:0]};
|
|
higher_r_8 = _RANDOM[7'h32][28:9];
|
|
higher_plus_one_r_8 = {_RANDOM[7'h32][31:29], _RANDOM[7'h33][16:0]};
|
|
higher_minus_one_r_8 = {_RANDOM[7'h33][31:17], _RANDOM[7'h34][4:0]};
|
|
io_out_s2_full_pred_2_fallThroughAddr_stashed_carry = _RANDOM[7'h34][5];
|
|
higher_r_9 = {_RANDOM[7'h34][31:6], _RANDOM[7'h35][1:0]};
|
|
higher_plus_one_r_9 = _RANDOM[7'h35][29:2];
|
|
higher_minus_one_r_9 = {_RANDOM[7'h35][31:30], _RANDOM[7'h36][25:0]};
|
|
higher_r_10 = {_RANDOM[7'h36][31:26], _RANDOM[7'h37][21:0]};
|
|
higher_plus_one_r_10 = {_RANDOM[7'h37][31:22], _RANDOM[7'h38][17:0]};
|
|
higher_minus_one_r_10 = {_RANDOM[7'h38][31:18], _RANDOM[7'h39][13:0]};
|
|
higher_r_11 = {_RANDOM[7'h39][31:14], _RANDOM[7'h3A][1:0]};
|
|
higher_plus_one_r_11 = _RANDOM[7'h3A][21:2];
|
|
higher_minus_one_r_11 = {_RANDOM[7'h3A][31:22], _RANDOM[7'h3B][9:0]};
|
|
io_out_s2_full_pred_3_fallThroughAddr_stashed_carry = _RANDOM[7'h3B][10];
|
|
higher_r_12 = {_RANDOM[7'h3B][31:11], _RANDOM[7'h3C][6:0]};
|
|
higher_plus_one_r_12 = {_RANDOM[7'h3C][31:7], _RANDOM[7'h3D][2:0]};
|
|
higher_minus_one_r_12 = _RANDOM[7'h3D][30:3];
|
|
higher_r_13 = {_RANDOM[7'h3D][31], _RANDOM[7'h3E][26:0]};
|
|
higher_plus_one_r_13 = {_RANDOM[7'h3E][31:27], _RANDOM[7'h3F][22:0]};
|
|
higher_minus_one_r_13 = {_RANDOM[7'h3F][31:23], _RANDOM[7'h40][18:0]};
|
|
higher_r_14 = {_RANDOM[7'h40][31:19], _RANDOM[7'h41][6:0]};
|
|
higher_plus_one_r_14 = _RANDOM[7'h41][26:7];
|
|
higher_minus_one_r_14 = {_RANDOM[7'h41][31:27], _RANDOM[7'h42][14:0]};
|
|
higher_r_15 = {_RANDOM[7'h42][31:15], _RANDOM[7'h43][10:0]};
|
|
higher_plus_one_r_15 = {_RANDOM[7'h43][31:11], _RANDOM[7'h44][6:0]};
|
|
higher_minus_one_r_15 = {_RANDOM[7'h44][31:7], _RANDOM[7'h45][2:0]};
|
|
higher_r_16 = _RANDOM[7'h45][30:3];
|
|
higher_plus_one_r_16 = {_RANDOM[7'h45][31], _RANDOM[7'h46][26:0]};
|
|
higher_minus_one_r_16 = {_RANDOM[7'h46][31:27], _RANDOM[7'h47][22:0]};
|
|
higher_r_17 = {_RANDOM[7'h47][31:23], _RANDOM[7'h48][10:0]};
|
|
higher_plus_one_r_17 = _RANDOM[7'h48][30:11];
|
|
higher_minus_one_r_17 = {_RANDOM[7'h48][31], _RANDOM[7'h49][18:0]};
|
|
higher_r_18 = {_RANDOM[7'h49][31:19], _RANDOM[7'h4A][14:0]};
|
|
higher_plus_one_r_18 = {_RANDOM[7'h4A][31:15], _RANDOM[7'h4B][10:0]};
|
|
higher_minus_one_r_18 = {_RANDOM[7'h4B][31:11], _RANDOM[7'h4C][6:0]};
|
|
higher_r_19 = {_RANDOM[7'h4C][31:7], _RANDOM[7'h4D][2:0]};
|
|
higher_plus_one_r_19 = _RANDOM[7'h4D][30:3];
|
|
higher_minus_one_r_19 = {_RANDOM[7'h4D][31], _RANDOM[7'h4E][26:0]};
|
|
higher_r_20 = {_RANDOM[7'h4E][31:27], _RANDOM[7'h4F][14:0]};
|
|
higher_plus_one_r_20 = {_RANDOM[7'h4F][31:15], _RANDOM[7'h50][2:0]};
|
|
higher_minus_one_r_20 = _RANDOM[7'h50][22:3];
|
|
higher_r_21 = {_RANDOM[7'h50][31:23], _RANDOM[7'h51][18:0]};
|
|
higher_plus_one_r_21 = {_RANDOM[7'h51][31:19], _RANDOM[7'h52][14:0]};
|
|
higher_minus_one_r_21 = {_RANDOM[7'h52][31:15], _RANDOM[7'h53][10:0]};
|
|
higher_r_22 = {_RANDOM[7'h53][31:11], _RANDOM[7'h54][6:0]};
|
|
higher_plus_one_r_22 = {_RANDOM[7'h54][31:7], _RANDOM[7'h55][2:0]};
|
|
higher_minus_one_r_22 = _RANDOM[7'h55][30:3];
|
|
higher_r_23 = {_RANDOM[7'h55][31], _RANDOM[7'h56][18:0]};
|
|
higher_plus_one_r_23 = {_RANDOM[7'h56][31:19], _RANDOM[7'h57][6:0]};
|
|
higher_minus_one_r_23 = _RANDOM[7'h57][26:7];
|
|
io_out_last_stage_meta_r = _RANDOM[7'h59][29:27];
|
|
io_out_last_stage_meta_r_1 = {_RANDOM[7'h59][31:30], _RANDOM[7'h5A][0]};
|
|
io_s1_ready_REG = _RANDOM[7'h5A][1];
|
|
ftbBank_io_update_write_way_REG = _RANDOM[7'h5A][3:2];
|
|
ftbBank_io_update_write_alloc_REG = _RANDOM[7'h5A][4];
|
|
io_perf_0_value_REG = _RANDOM[7'h5A][7];
|
|
io_perf_0_value_REG_1 = _RANDOM[7'h5A][8];
|
|
io_perf_1_value_REG = _RANDOM[7'h5A][9];
|
|
io_perf_1_value_REG_1 = _RANDOM[7'h5A][10];
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin
|
|
s2_hit_dup_0 = 1'h0;
|
|
s2_hit_dup_1 = 1'h0;
|
|
s2_hit_dup_2 = 1'h0;
|
|
s2_hit_dup_3 = 1'h0;
|
|
s3_hit_dup_0 = 1'h0;
|
|
s3_hit_dup_1 = 1'h0;
|
|
s3_hit_dup_2 = 1'h0;
|
|
s3_hit_dup_3 = 1'h0;
|
|
end
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL
|
|
`FIRRTL_AFTER_INITIAL
|
|
`endif // FIRRTL_AFTER_INITIAL
|
|
`endif // ENABLE_INITIAL_REG_
|
|
DelayN_2 reset_vector_delay (
|
|
.clock (clock),
|
|
.io_in (io_reset_vector),
|
|
.io_out (_reset_vector_delay_io_out)
|
|
);
|
|
FTBBank ftbBank (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_s1_fire (io_s1_fire_0),
|
|
.io_req_pc_ready (_ftbBank_io_req_pc_ready),
|
|
.io_req_pc_valid (io_s0_fire_0),
|
|
.io_req_pc_bits (io_in_bits_s0_pc_0),
|
|
.io_read_resp_valid (_ftbBank_io_read_resp_valid),
|
|
.io_read_resp_brSlots_0_offset
|
|
(_ftbBank_io_read_resp_brSlots_0_offset),
|
|
.io_read_resp_brSlots_0_lower
|
|
(_ftbBank_io_read_resp_brSlots_0_lower),
|
|
.io_read_resp_brSlots_0_tarStat
|
|
(_ftbBank_io_read_resp_brSlots_0_tarStat),
|
|
.io_read_resp_brSlots_0_sharing
|
|
(_ftbBank_io_read_resp_brSlots_0_sharing),
|
|
.io_read_resp_brSlots_0_valid
|
|
(_ftbBank_io_read_resp_brSlots_0_valid),
|
|
.io_read_resp_tailSlot_offset
|
|
(_ftbBank_io_read_resp_tailSlot_offset),
|
|
.io_read_resp_tailSlot_lower
|
|
(_ftbBank_io_read_resp_tailSlot_lower),
|
|
.io_read_resp_tailSlot_tarStat
|
|
(_ftbBank_io_read_resp_tailSlot_tarStat),
|
|
.io_read_resp_tailSlot_sharing
|
|
(_ftbBank_io_read_resp_tailSlot_sharing),
|
|
.io_read_resp_tailSlot_valid
|
|
(_ftbBank_io_read_resp_tailSlot_valid),
|
|
.io_read_resp_pftAddr (_ftbBank_io_read_resp_pftAddr),
|
|
.io_read_resp_carry (_ftbBank_io_read_resp_carry),
|
|
.io_read_resp_isCall (_ftbBank_io_read_resp_isCall),
|
|
.io_read_resp_isRet (_ftbBank_io_read_resp_isRet),
|
|
.io_read_resp_isJalr (_ftbBank_io_read_resp_isJalr),
|
|
.io_read_resp_last_may_be_rvi_call
|
|
(_ftbBank_io_read_resp_last_may_be_rvi_call),
|
|
.io_read_resp_always_taken_0
|
|
(_ftbBank_io_read_resp_always_taken_0),
|
|
.io_read_resp_always_taken_1
|
|
(_ftbBank_io_read_resp_always_taken_1),
|
|
.io_read_hits_valid (_ftbBank_io_read_hits_valid),
|
|
.io_read_hits_bits (_ftbBank_io_read_hits_bits),
|
|
.io_u_req_pc_valid (update_need_read),
|
|
.io_u_req_pc_bits (io_update_bits_pc),
|
|
.io_update_hits_valid (_ftbBank_io_update_hits_valid),
|
|
.io_update_hits_bits (_ftbBank_io_update_hits_bits),
|
|
.io_update_access
|
|
(u_valid & ~(io_update_bits_meta[0])),
|
|
.io_update_pc (_ftbBank_io_update_pc_T),
|
|
.io_update_write_data_valid
|
|
(update_now | _write_valid_delay_io_out),
|
|
.io_update_write_data_bits_entry_valid
|
|
(update_now
|
|
? io_update_bits_ftb_entry_valid
|
|
: _delay2_entry_pipMod_io_out_bits_valid),
|
|
.io_update_write_data_bits_entry_brSlots_0_offset
|
|
(update_now
|
|
? io_update_bits_ftb_entry_brSlots_0_offset
|
|
: _delay2_entry_pipMod_io_out_bits_brSlots_0_offset),
|
|
.io_update_write_data_bits_entry_brSlots_0_lower
|
|
(update_now
|
|
? io_update_bits_ftb_entry_brSlots_0_lower
|
|
: _delay2_entry_pipMod_io_out_bits_brSlots_0_lower),
|
|
.io_update_write_data_bits_entry_brSlots_0_tarStat
|
|
(update_now
|
|
? io_update_bits_ftb_entry_brSlots_0_tarStat
|
|
: _delay2_entry_pipMod_io_out_bits_brSlots_0_tarStat),
|
|
.io_update_write_data_bits_entry_brSlots_0_sharing
|
|
(update_now
|
|
? io_update_bits_ftb_entry_brSlots_0_sharing
|
|
: _delay2_entry_pipMod_io_out_bits_brSlots_0_sharing),
|
|
.io_update_write_data_bits_entry_brSlots_0_valid
|
|
(update_now
|
|
? io_update_bits_ftb_entry_brSlots_0_valid
|
|
: _delay2_entry_pipMod_io_out_bits_brSlots_0_valid),
|
|
.io_update_write_data_bits_entry_tailSlot_offset
|
|
(update_now
|
|
? io_update_bits_ftb_entry_tailSlot_offset
|
|
: _delay2_entry_pipMod_io_out_bits_tailSlot_offset),
|
|
.io_update_write_data_bits_entry_tailSlot_lower
|
|
(update_now
|
|
? io_update_bits_ftb_entry_tailSlot_lower
|
|
: _delay2_entry_pipMod_io_out_bits_tailSlot_lower),
|
|
.io_update_write_data_bits_entry_tailSlot_tarStat
|
|
(update_now
|
|
? io_update_bits_ftb_entry_tailSlot_tarStat
|
|
: _delay2_entry_pipMod_io_out_bits_tailSlot_tarStat),
|
|
.io_update_write_data_bits_entry_tailSlot_sharing
|
|
(update_now
|
|
? io_update_bits_ftb_entry_tailSlot_sharing
|
|
: _delay2_entry_pipMod_io_out_bits_tailSlot_sharing),
|
|
.io_update_write_data_bits_entry_tailSlot_valid
|
|
(update_now
|
|
? io_update_bits_ftb_entry_tailSlot_valid
|
|
: _delay2_entry_pipMod_io_out_bits_tailSlot_valid),
|
|
.io_update_write_data_bits_entry_pftAddr
|
|
(update_now
|
|
? io_update_bits_ftb_entry_pftAddr
|
|
: _delay2_entry_pipMod_io_out_bits_pftAddr),
|
|
.io_update_write_data_bits_entry_carry
|
|
(update_now
|
|
? io_update_bits_ftb_entry_carry
|
|
: _delay2_entry_pipMod_io_out_bits_carry),
|
|
.io_update_write_data_bits_entry_isCall
|
|
(update_now
|
|
? io_update_bits_ftb_entry_isCall
|
|
: _delay2_entry_pipMod_io_out_bits_isCall),
|
|
.io_update_write_data_bits_entry_isRet
|
|
(update_now
|
|
? io_update_bits_ftb_entry_isRet
|
|
: _delay2_entry_pipMod_io_out_bits_isRet),
|
|
.io_update_write_data_bits_entry_isJalr
|
|
(update_now
|
|
? io_update_bits_ftb_entry_isJalr
|
|
: _delay2_entry_pipMod_io_out_bits_isJalr),
|
|
.io_update_write_data_bits_entry_last_may_be_rvi_call
|
|
(update_now
|
|
? io_update_bits_ftb_entry_last_may_be_rvi_call
|
|
: _delay2_entry_pipMod_io_out_bits_last_may_be_rvi_call),
|
|
.io_update_write_data_bits_entry_always_taken_0
|
|
(update_now
|
|
? io_update_bits_ftb_entry_always_taken_0
|
|
: _delay2_entry_pipMod_io_out_bits_always_taken_0),
|
|
.io_update_write_data_bits_entry_always_taken_1
|
|
(update_now
|
|
? io_update_bits_ftb_entry_always_taken_1
|
|
: _delay2_entry_pipMod_io_out_bits_always_taken_1),
|
|
.io_update_write_data_bits_tag
|
|
(_ftbBank_io_update_pc_T[29:10]),
|
|
.io_update_write_way
|
|
(update_now ? io_update_bits_meta[2:1] : ftbBank_io_update_write_way_REG),
|
|
.io_update_write_alloc
|
|
(~update_now & ftbBank_io_update_write_alloc_REG)
|
|
);
|
|
DelayNWithValid delay2_pc_pipMod (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_in_bits (io_update_bits_pc),
|
|
.io_in_valid (u_valid),
|
|
.io_out_bits (_delay2_pc_pipMod_io_out_bits)
|
|
);
|
|
DelayNWithValid_1 delay2_entry_pipMod (
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_in_bits_valid (io_update_bits_ftb_entry_valid),
|
|
.io_in_bits_brSlots_0_offset (io_update_bits_ftb_entry_brSlots_0_offset),
|
|
.io_in_bits_brSlots_0_lower (io_update_bits_ftb_entry_brSlots_0_lower),
|
|
.io_in_bits_brSlots_0_tarStat (io_update_bits_ftb_entry_brSlots_0_tarStat),
|
|
.io_in_bits_brSlots_0_sharing (io_update_bits_ftb_entry_brSlots_0_sharing),
|
|
.io_in_bits_brSlots_0_valid (io_update_bits_ftb_entry_brSlots_0_valid),
|
|
.io_in_bits_tailSlot_offset (io_update_bits_ftb_entry_tailSlot_offset),
|
|
.io_in_bits_tailSlot_lower (io_update_bits_ftb_entry_tailSlot_lower),
|
|
.io_in_bits_tailSlot_tarStat (io_update_bits_ftb_entry_tailSlot_tarStat),
|
|
.io_in_bits_tailSlot_sharing (io_update_bits_ftb_entry_tailSlot_sharing),
|
|
.io_in_bits_tailSlot_valid (io_update_bits_ftb_entry_tailSlot_valid),
|
|
.io_in_bits_pftAddr (io_update_bits_ftb_entry_pftAddr),
|
|
.io_in_bits_carry (io_update_bits_ftb_entry_carry),
|
|
.io_in_bits_isCall (io_update_bits_ftb_entry_isCall),
|
|
.io_in_bits_isRet (io_update_bits_ftb_entry_isRet),
|
|
.io_in_bits_isJalr (io_update_bits_ftb_entry_isJalr),
|
|
.io_in_bits_last_may_be_rvi_call (io_update_bits_ftb_entry_last_may_be_rvi_call),
|
|
.io_in_bits_always_taken_0 (io_update_bits_ftb_entry_always_taken_0),
|
|
.io_in_bits_always_taken_1 (io_update_bits_ftb_entry_always_taken_1),
|
|
.io_in_valid (u_valid),
|
|
.io_out_bits_valid (_delay2_entry_pipMod_io_out_bits_valid),
|
|
.io_out_bits_brSlots_0_offset (_delay2_entry_pipMod_io_out_bits_brSlots_0_offset),
|
|
.io_out_bits_brSlots_0_lower (_delay2_entry_pipMod_io_out_bits_brSlots_0_lower),
|
|
.io_out_bits_brSlots_0_tarStat
|
|
(_delay2_entry_pipMod_io_out_bits_brSlots_0_tarStat),
|
|
.io_out_bits_brSlots_0_sharing
|
|
(_delay2_entry_pipMod_io_out_bits_brSlots_0_sharing),
|
|
.io_out_bits_brSlots_0_valid (_delay2_entry_pipMod_io_out_bits_brSlots_0_valid),
|
|
.io_out_bits_tailSlot_offset (_delay2_entry_pipMod_io_out_bits_tailSlot_offset),
|
|
.io_out_bits_tailSlot_lower (_delay2_entry_pipMod_io_out_bits_tailSlot_lower),
|
|
.io_out_bits_tailSlot_tarStat (_delay2_entry_pipMod_io_out_bits_tailSlot_tarStat),
|
|
.io_out_bits_tailSlot_sharing (_delay2_entry_pipMod_io_out_bits_tailSlot_sharing),
|
|
.io_out_bits_tailSlot_valid (_delay2_entry_pipMod_io_out_bits_tailSlot_valid),
|
|
.io_out_bits_pftAddr (_delay2_entry_pipMod_io_out_bits_pftAddr),
|
|
.io_out_bits_carry (_delay2_entry_pipMod_io_out_bits_carry),
|
|
.io_out_bits_isCall (_delay2_entry_pipMod_io_out_bits_isCall),
|
|
.io_out_bits_isRet (_delay2_entry_pipMod_io_out_bits_isRet),
|
|
.io_out_bits_isJalr (_delay2_entry_pipMod_io_out_bits_isJalr),
|
|
.io_out_bits_last_may_be_rvi_call
|
|
(_delay2_entry_pipMod_io_out_bits_last_may_be_rvi_call),
|
|
.io_out_bits_always_taken_0 (_delay2_entry_pipMod_io_out_bits_always_taken_0),
|
|
.io_out_bits_always_taken_1 (_delay2_entry_pipMod_io_out_bits_always_taken_1)
|
|
);
|
|
DelayN_4 write_valid_delay (
|
|
.clock (clock),
|
|
.io_in (u_valid & ~(io_update_bits_meta[0])),
|
|
.io_out (_write_valid_delay_io_out)
|
|
);
|
|
assign io_out_s2_full_pred_0_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 | s2_hit_dup_0
|
|
& s2_ftb_entry_dup_0_always_taken_0;
|
|
assign io_out_s2_full_pred_0_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 | s2_hit_dup_0
|
|
& s2_ftb_entry_dup_0_always_taken_1;
|
|
assign io_out_s2_full_pred_0_slot_valids_0 = s2_ftb_entry_dup_0_brSlots_0_valid;
|
|
assign io_out_s2_full_pred_0_slot_valids_1 = s2_ftb_entry_dup_0_tailSlot_valid;
|
|
assign io_out_s2_full_pred_0_targets_0 =
|
|
{(s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r : 28'h0)
|
|
| (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r : 28'h0)
|
|
| (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r : 28'h0),
|
|
s2_ftb_entry_dup_0_brSlots_0_lower,
|
|
1'h0};
|
|
assign io_out_s2_full_pred_0_targets_1 = io_out_s2_full_pred_0_targets_1_0;
|
|
assign io_out_s2_full_pred_0_jalr_target = io_out_s2_full_pred_0_targets_1_0;
|
|
assign io_out_s2_full_pred_0_offsets_0 = s2_ftb_entry_dup_0_brSlots_0_offset;
|
|
assign io_out_s2_full_pred_0_offsets_1 = s2_ftb_entry_dup_0_tailSlot_offset;
|
|
assign io_out_s2_full_pred_0_fallThroughAddr =
|
|
{1'h0, s2_pc_dup_0[4:1]} >= {s2_ftb_entry_dup_0_carry, s2_ftb_entry_dup_0_pftAddr}
|
|
? 41'(s2_pc_dup_0 + 41'h20)
|
|
: {io_out_s2_full_pred_0_fallThroughAddr_stashed_carry
|
|
? 36'(s2_pc_dup_0[40:5] + 36'h1)
|
|
: s2_pc_dup_0[40:5],
|
|
s2_ftb_entry_dup_0_pftAddr,
|
|
1'h0};
|
|
assign io_out_s2_full_pred_0_is_br_sharing =
|
|
s2_ftb_entry_dup_0_tailSlot_valid & s2_ftb_entry_dup_0_tailSlot_sharing;
|
|
assign io_out_s2_full_pred_0_hit = s2_hit_dup_0;
|
|
assign io_out_s2_full_pred_1_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 | s2_hit_dup_1
|
|
& s2_ftb_entry_dup_1_always_taken_0;
|
|
assign io_out_s2_full_pred_1_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 | s2_hit_dup_1
|
|
& s2_ftb_entry_dup_1_always_taken_1;
|
|
assign io_out_s2_full_pred_1_slot_valids_0 = s2_ftb_entry_dup_1_brSlots_0_valid;
|
|
assign io_out_s2_full_pred_1_slot_valids_1 = s2_ftb_entry_dup_1_tailSlot_valid;
|
|
assign io_out_s2_full_pred_1_targets_0 =
|
|
{(s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_3 : 28'h0)
|
|
| (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_3 : 28'h0)
|
|
| (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_3 : 28'h0),
|
|
s2_ftb_entry_dup_1_brSlots_0_lower,
|
|
1'h0};
|
|
assign io_out_s2_full_pred_1_targets_1 = io_out_s2_full_pred_1_targets_1_0;
|
|
assign io_out_s2_full_pred_1_jalr_target = io_out_s2_full_pred_1_targets_1_0;
|
|
assign io_out_s2_full_pred_1_offsets_0 = s2_ftb_entry_dup_1_brSlots_0_offset;
|
|
assign io_out_s2_full_pred_1_offsets_1 = s2_ftb_entry_dup_1_tailSlot_offset;
|
|
assign io_out_s2_full_pred_1_fallThroughAddr =
|
|
{1'h0, s2_pc_dup_1[4:1]} >= {s2_ftb_entry_dup_1_carry, s2_ftb_entry_dup_1_pftAddr}
|
|
? 41'(s2_pc_dup_1 + 41'h20)
|
|
: {io_out_s2_full_pred_1_fallThroughAddr_stashed_carry
|
|
? 36'(s2_pc_dup_1[40:5] + 36'h1)
|
|
: s2_pc_dup_1[40:5],
|
|
s2_ftb_entry_dup_1_pftAddr,
|
|
1'h0};
|
|
assign io_out_s2_full_pred_1_is_br_sharing =
|
|
s2_ftb_entry_dup_1_tailSlot_valid & s2_ftb_entry_dup_1_tailSlot_sharing;
|
|
assign io_out_s2_full_pred_1_hit = s2_hit_dup_1;
|
|
assign io_out_s2_full_pred_2_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 | s2_hit_dup_2
|
|
& s2_ftb_entry_dup_2_always_taken_0;
|
|
assign io_out_s2_full_pred_2_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 | s2_hit_dup_2
|
|
& s2_ftb_entry_dup_2_always_taken_1;
|
|
assign io_out_s2_full_pred_2_slot_valids_0 = s2_ftb_entry_dup_2_brSlots_0_valid;
|
|
assign io_out_s2_full_pred_2_slot_valids_1 = s2_ftb_entry_dup_2_tailSlot_valid;
|
|
assign io_out_s2_full_pred_2_targets_0 =
|
|
{(s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_6 : 28'h0)
|
|
| (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_6 : 28'h0)
|
|
| (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_6 : 28'h0),
|
|
s2_ftb_entry_dup_2_brSlots_0_lower,
|
|
1'h0};
|
|
assign io_out_s2_full_pred_2_targets_1 = io_out_s2_full_pred_2_targets_1_0;
|
|
assign io_out_s2_full_pred_2_jalr_target = io_out_s2_full_pred_2_targets_1_0;
|
|
assign io_out_s2_full_pred_2_offsets_0 = s2_ftb_entry_dup_2_brSlots_0_offset;
|
|
assign io_out_s2_full_pred_2_offsets_1 = s2_ftb_entry_dup_2_tailSlot_offset;
|
|
assign io_out_s2_full_pred_2_fallThroughAddr =
|
|
{1'h0, s2_pc_dup_2[4:1]} >= {s2_ftb_entry_dup_2_carry, s2_ftb_entry_dup_2_pftAddr}
|
|
? 41'(s2_pc_dup_2 + 41'h20)
|
|
: {io_out_s2_full_pred_2_fallThroughAddr_stashed_carry
|
|
? 36'(s2_pc_dup_2[40:5] + 36'h1)
|
|
: s2_pc_dup_2[40:5],
|
|
s2_ftb_entry_dup_2_pftAddr,
|
|
1'h0};
|
|
assign io_out_s2_full_pred_2_is_jalr =
|
|
s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isJalr;
|
|
assign io_out_s2_full_pred_2_is_call =
|
|
s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isCall;
|
|
assign io_out_s2_full_pred_2_is_ret =
|
|
s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isRet;
|
|
assign io_out_s2_full_pred_2_last_may_be_rvi_call =
|
|
s2_ftb_entry_dup_2_last_may_be_rvi_call;
|
|
assign io_out_s2_full_pred_2_is_br_sharing =
|
|
s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_tailSlot_sharing;
|
|
assign io_out_s2_full_pred_2_hit = s2_hit_dup_2;
|
|
assign io_out_s2_full_pred_3_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 | s2_hit_dup_3
|
|
& s2_ftb_entry_dup_3_always_taken_0;
|
|
assign io_out_s2_full_pred_3_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 | s2_hit_dup_3
|
|
& s2_ftb_entry_dup_3_always_taken_1;
|
|
assign io_out_s2_full_pred_3_slot_valids_0 = s2_ftb_entry_dup_3_brSlots_0_valid;
|
|
assign io_out_s2_full_pred_3_slot_valids_1 = s2_ftb_entry_dup_3_tailSlot_valid;
|
|
assign io_out_s2_full_pred_3_targets_0 =
|
|
{(s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_9 : 28'h0)
|
|
| (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_9 : 28'h0)
|
|
| (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_9 : 28'h0),
|
|
s2_ftb_entry_dup_3_brSlots_0_lower,
|
|
1'h0};
|
|
assign io_out_s2_full_pred_3_targets_1 = io_out_s2_full_pred_3_targets_1_0;
|
|
assign io_out_s2_full_pred_3_jalr_target = io_out_s2_full_pred_3_targets_1_0;
|
|
assign io_out_s2_full_pred_3_offsets_0 = s2_ftb_entry_dup_3_brSlots_0_offset;
|
|
assign io_out_s2_full_pred_3_offsets_1 = s2_ftb_entry_dup_3_tailSlot_offset;
|
|
assign io_out_s2_full_pred_3_fallThroughAddr =
|
|
io_out_s2_full_pred_3_fallThroughErr_0
|
|
? 41'(s2_pc_dup_3 + 41'h20)
|
|
: {io_out_s2_full_pred_3_fallThroughAddr_stashed_carry
|
|
? 36'(s2_pc_dup_3[40:5] + 36'h1)
|
|
: s2_pc_dup_3[40:5],
|
|
s2_ftb_entry_dup_3_pftAddr,
|
|
1'h0};
|
|
assign io_out_s2_full_pred_3_fallThroughErr = io_out_s2_full_pred_3_fallThroughErr_0;
|
|
assign io_out_s2_full_pred_3_is_br_sharing =
|
|
s2_ftb_entry_dup_3_tailSlot_valid & s2_ftb_entry_dup_3_tailSlot_sharing;
|
|
assign io_out_s2_full_pred_3_hit = s2_hit_dup_3;
|
|
assign io_out_s3_full_pred_0_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 | s3_hit_dup_0
|
|
& s3_ftb_entry_dup_0_always_taken_0;
|
|
assign io_out_s3_full_pred_0_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 | s3_hit_dup_0
|
|
& s3_ftb_entry_dup_0_always_taken_1;
|
|
assign io_out_s3_full_pred_0_slot_valids_0 = s3_ftb_entry_dup_0_brSlots_0_valid;
|
|
assign io_out_s3_full_pred_0_slot_valids_1 = s3_ftb_entry_dup_0_tailSlot_valid;
|
|
assign io_out_s3_full_pred_0_targets_0 =
|
|
{(s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_12 : 28'h0)
|
|
| (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_12 : 28'h0)
|
|
| (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r_12 : 28'h0),
|
|
s3_ftb_entry_dup_0_brSlots_0_lower,
|
|
1'h0};
|
|
assign io_out_s3_full_pred_0_targets_1 = io_out_s3_full_pred_0_targets_1_0;
|
|
assign io_out_s3_full_pred_0_jalr_target = io_out_s3_full_pred_0_targets_1_0;
|
|
assign io_out_s3_full_pred_0_fallThroughAddr =
|
|
io_out_s3_full_pred_0_fallThroughErr_0
|
|
? 41'(s3_pc_dup_0 + 41'h20)
|
|
: {s3_ftb_entry_dup_0_carry ? 36'(s3_pc_dup_0[40:5] + 36'h1) : s3_pc_dup_0[40:5],
|
|
s3_ftb_entry_dup_0_pftAddr,
|
|
1'h0};
|
|
assign io_out_s3_full_pred_0_fallThroughErr = io_out_s3_full_pred_0_fallThroughErr_0;
|
|
assign io_out_s3_full_pred_0_is_br_sharing =
|
|
s3_ftb_entry_dup_0_tailSlot_valid & s3_ftb_entry_dup_0_tailSlot_sharing;
|
|
assign io_out_s3_full_pred_0_hit = s3_hit_dup_0;
|
|
assign io_out_s3_full_pred_1_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 | s3_hit_dup_1
|
|
& s3_ftb_entry_dup_1_always_taken_0;
|
|
assign io_out_s3_full_pred_1_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 | s3_hit_dup_1
|
|
& s3_ftb_entry_dup_1_always_taken_1;
|
|
assign io_out_s3_full_pred_1_slot_valids_0 = s3_ftb_entry_dup_1_brSlots_0_valid;
|
|
assign io_out_s3_full_pred_1_slot_valids_1 = s3_ftb_entry_dup_1_tailSlot_valid;
|
|
assign io_out_s3_full_pred_1_targets_0 =
|
|
{(s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_15 : 28'h0)
|
|
| (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_15 : 28'h0)
|
|
| (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_15 : 28'h0),
|
|
s3_ftb_entry_dup_1_brSlots_0_lower,
|
|
1'h0};
|
|
assign io_out_s3_full_pred_1_targets_1 = io_out_s3_full_pred_1_targets_1_0;
|
|
assign io_out_s3_full_pred_1_jalr_target = io_out_s3_full_pred_1_targets_1_0;
|
|
assign io_out_s3_full_pred_1_fallThroughAddr =
|
|
io_out_s3_full_pred_1_fallThroughErr_0
|
|
? 41'(s3_pc_dup_1 + 41'h20)
|
|
: {s3_ftb_entry_dup_1_carry ? 36'(s3_pc_dup_1[40:5] + 36'h1) : s3_pc_dup_1[40:5],
|
|
s3_ftb_entry_dup_1_pftAddr,
|
|
1'h0};
|
|
assign io_out_s3_full_pred_1_fallThroughErr = io_out_s3_full_pred_1_fallThroughErr_0;
|
|
assign io_out_s3_full_pred_1_is_br_sharing =
|
|
s3_ftb_entry_dup_1_tailSlot_valid & s3_ftb_entry_dup_1_tailSlot_sharing;
|
|
assign io_out_s3_full_pred_1_hit = s3_hit_dup_1;
|
|
assign io_out_s3_full_pred_2_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 | s3_hit_dup_2
|
|
& s3_ftb_entry_dup_2_always_taken_0;
|
|
assign io_out_s3_full_pred_2_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 | s3_hit_dup_2
|
|
& s3_ftb_entry_dup_2_always_taken_1;
|
|
assign io_out_s3_full_pred_2_slot_valids_0 = s3_ftb_entry_dup_2_brSlots_0_valid;
|
|
assign io_out_s3_full_pred_2_slot_valids_1 = s3_ftb_entry_dup_2_tailSlot_valid;
|
|
assign io_out_s3_full_pred_2_targets_0 =
|
|
{(s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_18 : 28'h0)
|
|
| (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_18 : 28'h0)
|
|
| (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_18 : 28'h0),
|
|
s3_ftb_entry_dup_2_brSlots_0_lower,
|
|
1'h0};
|
|
assign io_out_s3_full_pred_2_targets_1 = io_out_s3_full_pred_2_targets_1_0;
|
|
assign io_out_s3_full_pred_2_jalr_target = io_out_s3_full_pred_2_targets_1_0;
|
|
assign io_out_s3_full_pred_2_fallThroughAddr =
|
|
io_out_s3_full_pred_2_fallThroughErr_0
|
|
? 41'(s3_pc_dup_2 + 41'h20)
|
|
: {s3_ftb_entry_dup_2_carry ? 36'(s3_pc_dup_2[40:5] + 36'h1) : s3_pc_dup_2[40:5],
|
|
s3_ftb_entry_dup_2_pftAddr,
|
|
1'h0};
|
|
assign io_out_s3_full_pred_2_fallThroughErr = io_out_s3_full_pred_2_fallThroughErr_0;
|
|
assign io_out_s3_full_pred_2_is_jalr =
|
|
s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isJalr;
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assign io_out_s3_full_pred_2_is_call =
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s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isCall;
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assign io_out_s3_full_pred_2_is_ret =
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s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isRet;
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assign io_out_s3_full_pred_2_is_br_sharing =
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s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_tailSlot_sharing;
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assign io_out_s3_full_pred_2_hit = s3_hit_dup_2;
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assign io_out_s3_full_pred_3_br_taken_mask_0 =
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io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 | s3_hit_dup_3
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& s3_ftb_entry_dup_3_always_taken_0;
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assign io_out_s3_full_pred_3_br_taken_mask_1 =
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io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 | s3_hit_dup_3
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& s3_ftb_entry_dup_3_always_taken_1;
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assign io_out_s3_full_pred_3_slot_valids_0 = s3_ftb_entry_dup_3_brSlots_0_valid;
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assign io_out_s3_full_pred_3_slot_valids_1 = s3_ftb_entry_dup_3_tailSlot_valid;
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assign io_out_s3_full_pred_3_targets_0 =
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{(s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_21 : 28'h0)
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| (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_21 : 28'h0)
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| (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_21 : 28'h0),
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s3_ftb_entry_dup_3_brSlots_0_lower,
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1'h0};
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assign io_out_s3_full_pred_3_targets_1 = io_out_s3_full_pred_3_targets_1_0;
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assign io_out_s3_full_pred_3_jalr_target = io_out_s3_full_pred_3_targets_1_0;
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assign io_out_s3_full_pred_3_offsets_0 = s3_ftb_entry_dup_3_brSlots_0_offset;
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assign io_out_s3_full_pred_3_offsets_1 = s3_ftb_entry_dup_3_tailSlot_offset;
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assign io_out_s3_full_pred_3_fallThroughAddr =
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io_out_s3_full_pred_3_fallThroughErr_0
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? 41'(s3_pc_dup_3 + 41'h20)
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: {s3_ftb_entry_dup_3_carry ? 36'(s3_pc_dup_3[40:5] + 36'h1) : s3_pc_dup_3[40:5],
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s3_ftb_entry_dup_3_pftAddr,
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1'h0};
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assign io_out_s3_full_pred_3_fallThroughErr = io_out_s3_full_pred_3_fallThroughErr_0;
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assign io_out_s3_full_pred_3_is_br_sharing =
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s3_ftb_entry_dup_3_tailSlot_valid & s3_ftb_entry_dup_3_tailSlot_sharing;
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assign io_out_s3_full_pred_3_hit = s3_hit_dup_3;
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assign io_out_last_stage_meta = {220'h0, io_out_last_stage_meta_r_1};
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assign io_out_last_stage_ftb_entry_valid = s3_ftb_entry_dup_0_valid;
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assign io_out_last_stage_ftb_entry_brSlots_0_offset =
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s3_ftb_entry_dup_0_brSlots_0_offset;
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assign io_out_last_stage_ftb_entry_brSlots_0_lower = s3_ftb_entry_dup_0_brSlots_0_lower;
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assign io_out_last_stage_ftb_entry_brSlots_0_tarStat =
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s3_ftb_entry_dup_0_brSlots_0_tarStat;
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assign io_out_last_stage_ftb_entry_brSlots_0_sharing =
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s3_ftb_entry_dup_0_brSlots_0_sharing;
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assign io_out_last_stage_ftb_entry_brSlots_0_valid = s3_ftb_entry_dup_0_brSlots_0_valid;
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assign io_out_last_stage_ftb_entry_tailSlot_offset = s3_ftb_entry_dup_0_tailSlot_offset;
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assign io_out_last_stage_ftb_entry_tailSlot_lower = s3_ftb_entry_dup_0_tailSlot_lower;
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assign io_out_last_stage_ftb_entry_tailSlot_tarStat =
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s3_ftb_entry_dup_0_tailSlot_tarStat;
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assign io_out_last_stage_ftb_entry_tailSlot_sharing =
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s3_ftb_entry_dup_0_tailSlot_sharing;
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assign io_out_last_stage_ftb_entry_tailSlot_valid = s3_ftb_entry_dup_0_tailSlot_valid;
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assign io_out_last_stage_ftb_entry_pftAddr = s3_ftb_entry_dup_0_pftAddr;
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assign io_out_last_stage_ftb_entry_carry = s3_ftb_entry_dup_0_carry;
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assign io_out_last_stage_ftb_entry_isCall = s3_ftb_entry_dup_0_isCall;
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assign io_out_last_stage_ftb_entry_isRet = s3_ftb_entry_dup_0_isRet;
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assign io_out_last_stage_ftb_entry_isJalr = s3_ftb_entry_dup_0_isJalr;
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assign io_out_last_stage_ftb_entry_last_may_be_rvi_call =
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s3_ftb_entry_dup_0_last_may_be_rvi_call;
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assign io_out_last_stage_ftb_entry_always_taken_0 = s3_ftb_entry_dup_0_always_taken_0;
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assign io_out_last_stage_ftb_entry_always_taken_1 = s3_ftb_entry_dup_0_always_taken_1;
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assign io_s1_ready = _ftbBank_io_req_pc_ready & ~update_need_read & ~io_s1_ready_REG;
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assign io_perf_0_value = {5'h0, io_perf_0_value_REG_1};
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assign io_perf_1_value = {5'h0, io_perf_1_value_REG_1};
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endmodule
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