diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..b036c27 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +out +split_verilogs diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..c72e6b5 --- /dev/null +++ b/Makefile @@ -0,0 +1,25 @@ +export LANG ?= python +export WAVE ?= true +export VERBOSE ?= false +export EXAMPLE ?= false +export TARGET + + + +default: + echo "TODO" + + +tage_sc: + make -f ./mk/Tage.mk tage_sc + +uftb: + make -f ./mk/uFTB.mk uftb + +ftb: + make -f ./mk/FTB.mk ftb + +filter: + cat log|grep Cannot |awk '{print $8}'| sort| uniq|tr -d "'" + +all: tage_sc uftb ftb diff --git a/mk/FTB.mk b/mk/FTB.mk new file mode 100644 index 0000000..309fa57 --- /dev/null +++ b/mk/FTB.mk @@ -0,0 +1,47 @@ +TOP_ENTRY := ./src/FTB/FTB.sv +TOP_FILES := ./src/FTB.txt +LANG ?= cpp + +ifneq ($(TARGET),) + TARGET := $(TARGET) +else + TARGET := out/picker_out_FTB +endif + +# if EXAMPLE is set, then _EXAMPLE is set to -e +ifneq ($(EXAMPLE), false) + _EXAMPLE := -e +endif +_EXAMPLE ?= +# if VERBOSE is set, then _VERBOSE is set to -v +ifneq ($(VERBOSE), false) + _VERBOSE := -v +endif +_VERBOSE ?= +# if WAVE is set, then _WAVEFORM is set to -w +ifneq ($(WAVE), false) + ifneq ($(WAVE), true) + _WAVEFORM := -w $(WAVE) + else + _WAVEFORM := -w FTB.fst + endif +endif +_WAVEFORM ?= + +ftb: + @echo "Building tage module with parameters: " + @echo "LANG=${LANG}" + @echo "TOP_ENTRY=${TOP_ENTRY}" + @echo "TOP_FILES=${TOP_FILES}" + @echo "TARGET=${TARGET}" + @echo "WAVEFORM=${_WAVEFORM}" + @echo "VERBOSE=${_VERBOSE}" + @echo "EXAMPLE=${_EXAMPLE}" + + @mkdir -p out + rm -rf ${TARGET} + picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${LANG} \ + -t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE} + + cd ${TARGET} && make + diff --git a/mk/Tage.mk b/mk/Tage.mk new file mode 100644 index 0000000..27c45ca --- /dev/null +++ b/mk/Tage.mk @@ -0,0 +1,47 @@ +TOP_ENTRY := ./src/TageSC/Tage_SC.sv +TOP_FILES := ./src/Tage_SC.txt +LANG ?= cpp + +ifneq ($(TARGET),) + TARGET := $(TARGET) +else + TARGET := out/picker_out_TageSC +endif + +# if EXAMPLE is set, then _EXAMPLE is set to -e +ifneq ($(EXAMPLE), false) + _EXAMPLE := -e +endif +_EXAMPLE ?= +# if VERBOSE is set, then _VERBOSE is set to -v +ifneq ($(VERBOSE), false) + _VERBOSE := -v +endif +_VERBOSE ?= +# if WAVE is set, then _WAVEFORM is set to -w +ifneq ($(WAVE), false) + ifneq ($(WAVE), true) + _WAVEFORM := -w $(WAVE) + else + _WAVEFORM := -w TageSC.fst + endif +endif +_WAVEFORM ?= + +tage_sc: + @echo "Building tage module with parameters: " + @echo "LANG=${LANG}" + @echo "TOP_ENTRY=${TOP_ENTRY}" + @echo "TOP_FILES=${TOP_FILES}" + @echo "TARGET=${TARGET}" + @echo "WAVEFORM=${_WAVEFORM}" + @echo "VERBOSE=${_VERBOSE}" + @echo "EXAMPLE=${_EXAMPLE}" + + @mkdir -p out + rm -rf ${TARGET} + picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${LANG} \ + -t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE} + + cd ${TARGET} && make + diff --git a/mk/uFTB.mk b/mk/uFTB.mk new file mode 100644 index 0000000..5fe02a7 --- /dev/null +++ b/mk/uFTB.mk @@ -0,0 +1,47 @@ +TOP_ENTRY := ./src/uFTB/FauFTB.sv +TOP_FILES := ./src/uFTB.txt +LANG ?= cpp + +ifneq ($(TARGET),) + TARGET := $(TARGET) +else + TARGET := out/picker_out_uFTB +endif + +# if EXAMPLE is set, then _EXAMPLE is set to -e +ifneq ($(EXAMPLE), false) + _EXAMPLE := -e +endif +_EXAMPLE ?= +# if VERBOSE is set, then _VERBOSE is set to -v +ifneq ($(VERBOSE), false) + _VERBOSE := -v +endif +_VERBOSE ?= +# if WAVE is set, then _WAVEFORM is set to -w +ifneq ($(WAVE), false) + ifneq ($(WAVE), true) + _WAVEFORM := -w $(WAVE) + else + _WAVEFORM := -w uFTB.fst + endif +endif +_WAVEFORM ?= + +uftb: + @echo "Building tage module with parameters: " + @echo "LANG=${LANG}" + @echo "TOP_ENTRY=${TOP_ENTRY}" + @echo "TOP_FILES=${TOP_FILES}" + @echo "TARGET=${TARGET}" + @echo "WAVEFORM=${_WAVEFORM}" + @echo "VERBOSE=${_VERBOSE}" + @echo "EXAMPLE=${_EXAMPLE}" + + @mkdir -p out + rm -rf ${TARGET} + picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${LANG} \ + -t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE} + + cd ${TARGET} && make + diff --git a/src/FTB.txt b/src/FTB.txt new file mode 100644 index 0000000..8573759 --- /dev/null +++ b/src/FTB.txt @@ -0,0 +1,9 @@ +./src/FTB/FTBBank.sv +./src/FTB/FTBEntryGen.sv +./src/FTB/SRAMTemplate_9.sv +./src/FTB/array_3.sv +./src/common/ext_sram.v +./src/common/DelayN_2.sv +./src/common/DelayN_4.sv +./src/common/DelayN_5.sv +./src/common/DelayN_6.sv \ No newline at end of file diff --git a/src/FTB/FTB.sv b/src/FTB/FTB.sv new file mode 100644 index 0000000..b984820 --- /dev/null +++ b/src/FTB/FTB.sv @@ -0,0 +1,1617 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FTB( // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + input clock, + input reset, + input [35:0] io_reset_vector, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_ctrl_btb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_s1_ready, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [11:0] io_update_bits_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [19:0] io_update_bits_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_old_entry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [218:0] io_update_bits_meta // src/main/scala/xiangshan/frontend/BPU.scala:171:14 +); + + wire _write_valid_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _delay2_entry_delay_io_out_valid; // utility/src/main/scala/utility/Hold.scala:97:23 + wire [3:0] _delay2_entry_delay_io_out_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:97:23 + wire [11:0] _delay2_entry_delay_io_out_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:97:23 + wire [1:0] _delay2_entry_delay_io_out_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _delay2_entry_delay_io_out_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _delay2_entry_delay_io_out_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:97:23 + wire [3:0] _delay2_entry_delay_io_out_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:97:23 + wire [19:0] _delay2_entry_delay_io_out_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:97:23 + wire [1:0] _delay2_entry_delay_io_out_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _delay2_entry_delay_io_out_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _delay2_entry_delay_io_out_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:97:23 + wire [3:0] _delay2_entry_delay_io_out_pftAddr; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _delay2_entry_delay_io_out_carry; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _delay2_entry_delay_io_out_isCall; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _delay2_entry_delay_io_out_isRet; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _delay2_entry_delay_io_out_isJalr; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _delay2_entry_delay_io_out_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _delay2_entry_delay_io_out_always_taken_0; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _delay2_entry_delay_io_out_always_taken_1; // utility/src/main/scala/utility/Hold.scala:97:23 + wire [38:0] _delay2_pc_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _ftbBank_io_req_pc_ready; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_read_resp_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire [3:0] _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire [11:0] _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire [1:0] _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_read_resp_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire [3:0] _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire [19:0] _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire [1:0] _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire [3:0] _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_read_resp_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_read_resp_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_read_resp_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_read_resp_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_read_hits_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire [1:0] _ftbBank_io_read_hits_bits; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire _ftbBank_io_update_hits_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire [1:0] _ftbBank_io_update_hits_bits; // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + wire [35:0] _reset_vector_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 + reg [38:0] s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + reg [38:0] s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + reg [38:0] s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + reg [38:0] s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + reg [38:0] s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 + reg [38:0] s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 + reg [38:0] s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 + reg [38:0] s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 + reg [38:0] s3_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 + reg [38:0] s3_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 + reg [38:0] s3_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 + reg [38:0] s3_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 + reg REG; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 + reg REG_1; // src/main/scala/xiangshan/frontend/BPU.scala:190:16 + reg s2_ftb_entry_dup_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [3:0] s2_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [11:0] s2_ftb_entry_dup_0_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [1:0] s2_ftb_entry_dup_0_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_0_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [3:0] s2_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [19:0] s2_ftb_entry_dup_0_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [1:0] s2_ftb_entry_dup_0_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [3:0] s2_ftb_entry_dup_0_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_0_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_0_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_0_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_0_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_0_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [3:0] s2_ftb_entry_dup_1_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [11:0] s2_ftb_entry_dup_1_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [1:0] s2_ftb_entry_dup_1_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [3:0] s2_ftb_entry_dup_1_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [19:0] s2_ftb_entry_dup_1_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [1:0] s2_ftb_entry_dup_1_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [3:0] s2_ftb_entry_dup_1_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_1_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [3:0] s2_ftb_entry_dup_2_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [11:0] s2_ftb_entry_dup_2_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [1:0] s2_ftb_entry_dup_2_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [3:0] s2_ftb_entry_dup_2_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [19:0] s2_ftb_entry_dup_2_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [1:0] s2_ftb_entry_dup_2_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [3:0] s2_ftb_entry_dup_2_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_2_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_2_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [3:0] s2_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [11:0] s2_ftb_entry_dup_3_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [1:0] s2_ftb_entry_dup_3_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [3:0] s2_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [19:0] s2_ftb_entry_dup_3_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [1:0] s2_ftb_entry_dup_3_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg [3:0] s2_ftb_entry_dup_3_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_3_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s2_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55 + reg s3_ftb_entry_dup_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [3:0] s3_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [11:0] s3_ftb_entry_dup_0_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [1:0] s3_ftb_entry_dup_0_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_0_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [3:0] s3_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [19:0] s3_ftb_entry_dup_0_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [1:0] s3_ftb_entry_dup_0_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [3:0] s3_ftb_entry_dup_0_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_0_carry; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_0_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_0_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_0_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_0_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [11:0] s3_ftb_entry_dup_1_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [1:0] s3_ftb_entry_dup_1_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [19:0] s3_ftb_entry_dup_1_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [1:0] s3_ftb_entry_dup_1_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [3:0] s3_ftb_entry_dup_1_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_1_carry; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [11:0] s3_ftb_entry_dup_2_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [1:0] s3_ftb_entry_dup_2_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [19:0] s3_ftb_entry_dup_2_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [1:0] s3_ftb_entry_dup_2_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [3:0] s3_ftb_entry_dup_2_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_2_carry; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [3:0] s3_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [11:0] s3_ftb_entry_dup_3_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [1:0] s3_ftb_entry_dup_3_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [3:0] s3_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [19:0] s3_ftb_entry_dup_3_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [1:0] s3_ftb_entry_dup_3_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg [3:0] s3_ftb_entry_dup_3_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_3_carry; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + reg s3_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:429:88 + wire io_out_last_stage_meta_e_hit = + _ftbBank_io_read_hits_valid & io_ctrl_btb_enable; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :431:43 + reg s2_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:432:49 + reg s2_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:432:49 + reg s2_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:432:49 + reg s2_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:432:49 + reg s3_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:433:76 + reg s3_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:433:76 + reg s3_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:433:76 + reg s3_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:433:76 + reg [25:0] higher_r; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + reg [25:0] higher_r_1; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_1; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_1; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire _target_T_18 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55 + wire _target_T_19 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55 + wire _target_T_20 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55 + reg [17:0] higher_r_2; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [17:0] higher_plus_one_r_2; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [17:0] higher_minus_one_r_2; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire [38:0] _io_out_s2_full_pred_0_targets_1_output = + {s2_ftb_entry_dup_0_tailSlot_sharing + ? {(_target_T_18 ? higher_plus_one_r_1 : 26'h0) + | (_target_T_19 ? higher_minus_one_r_1 : 26'h0) + | (_target_T_20 ? higher_r_1 : 26'h0), + s2_ftb_entry_dup_0_tailSlot_lower[11:0]} + : {(_target_T_18 ? higher_plus_one_r_2 : 18'h0) + | (_target_T_19 ? higher_minus_one_r_2 : 18'h0) + | (_target_T_20 ? higher_r_2 : 18'h0), + s2_ftb_entry_dup_0_tailSlot_lower}, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55 + reg io_out_s2_full_pred_0_fallThroughAddr_stashed_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36 + reg [25:0] higher_r_3; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_3; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_3; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + reg [25:0] higher_r_4; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_4; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_4; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire _target_T_45 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55 + wire _target_T_46 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55 + wire _target_T_47 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55 + reg [17:0] higher_r_5; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [17:0] higher_plus_one_r_5; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [17:0] higher_minus_one_r_5; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire [38:0] _io_out_s2_full_pred_1_targets_1_output = + {s2_ftb_entry_dup_1_tailSlot_sharing + ? {(_target_T_45 ? higher_plus_one_r_4 : 26'h0) + | (_target_T_46 ? higher_minus_one_r_4 : 26'h0) + | (_target_T_47 ? higher_r_4 : 26'h0), + s2_ftb_entry_dup_1_tailSlot_lower[11:0]} + : {(_target_T_45 ? higher_plus_one_r_5 : 18'h0) + | (_target_T_46 ? higher_minus_one_r_5 : 18'h0) + | (_target_T_47 ? higher_r_5 : 18'h0), + s2_ftb_entry_dup_1_tailSlot_lower}, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55 + reg io_out_s2_full_pred_1_fallThroughAddr_stashed_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36 + reg [25:0] higher_r_6; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_6; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_6; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + reg [25:0] higher_r_7; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_7; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_7; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire _target_T_72 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55 + wire _target_T_73 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55 + wire _target_T_74 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55 + reg [17:0] higher_r_8; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [17:0] higher_plus_one_r_8; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [17:0] higher_minus_one_r_8; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire [38:0] _io_out_s2_full_pred_2_targets_1_output = + {s2_ftb_entry_dup_2_tailSlot_sharing + ? {(_target_T_72 ? higher_plus_one_r_7 : 26'h0) + | (_target_T_73 ? higher_minus_one_r_7 : 26'h0) + | (_target_T_74 ? higher_r_7 : 26'h0), + s2_ftb_entry_dup_2_tailSlot_lower[11:0]} + : {(_target_T_72 ? higher_plus_one_r_8 : 18'h0) + | (_target_T_73 ? higher_minus_one_r_8 : 18'h0) + | (_target_T_74 ? higher_r_8 : 18'h0), + s2_ftb_entry_dup_2_tailSlot_lower}, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55 + reg io_out_s2_full_pred_2_fallThroughAddr_stashed_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36 + reg [25:0] higher_r_9; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_9; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_9; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + reg [25:0] higher_r_10; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_10; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_10; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire _target_T_99 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55 + wire _target_T_100 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55 + wire _target_T_101 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55 + reg [17:0] higher_r_11; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [17:0] higher_plus_one_r_11; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [17:0] higher_minus_one_r_11; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire [38:0] _io_out_s2_full_pred_3_targets_1_output = + {s2_ftb_entry_dup_3_tailSlot_sharing + ? {(_target_T_99 ? higher_plus_one_r_10 : 26'h0) + | (_target_T_100 ? higher_minus_one_r_10 : 26'h0) + | (_target_T_101 ? higher_r_10 : 26'h0), + s2_ftb_entry_dup_3_tailSlot_lower[11:0]} + : {(_target_T_99 ? higher_plus_one_r_11 : 18'h0) + | (_target_T_100 ? higher_minus_one_r_11 : 18'h0) + | (_target_T_101 ? higher_r_11 : 18'h0), + s2_ftb_entry_dup_3_tailSlot_lower}, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55 + wire _io_out_s2_full_pred_3_fallThroughErr_output = + {1'h0, s2_pc_dup_3[4:1]} >= {s2_ftb_entry_dup_3_carry, s2_ftb_entry_dup_3_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + reg io_out_s2_full_pred_3_fallThroughAddr_stashed_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36 + reg [25:0] higher_r_12; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_12; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_12; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + reg [25:0] higher_r_13; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_13; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_13; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire _target_T_126 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88 + wire _target_T_127 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88 + wire _target_T_128 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88 + reg [17:0] higher_r_14; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [17:0] higher_plus_one_r_14; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [17:0] higher_minus_one_r_14; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire [38:0] _io_out_s3_full_pred_0_targets_1_output = + {s3_ftb_entry_dup_0_tailSlot_sharing + ? {(_target_T_126 ? higher_plus_one_r_13 : 26'h0) + | (_target_T_127 ? higher_minus_one_r_13 : 26'h0) + | (_target_T_128 ? higher_r_13 : 26'h0), + s3_ftb_entry_dup_0_tailSlot_lower[11:0]} + : {(_target_T_126 ? higher_plus_one_r_14 : 18'h0) + | (_target_T_127 ? higher_minus_one_r_14 : 18'h0) + | (_target_T_128 ? higher_r_14 : 18'h0), + s3_ftb_entry_dup_0_tailSlot_lower}, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88 + wire _io_out_s3_full_pred_0_fallThroughErr_output = + {1'h0, s3_pc_dup_0[4:1]} >= {s3_ftb_entry_dup_0_carry, s3_ftb_entry_dup_0_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + reg [25:0] higher_r_15; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_15; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_15; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + reg [25:0] higher_r_16; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_16; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_16; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire _target_T_153 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88 + wire _target_T_154 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88 + wire _target_T_155 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88 + reg [17:0] higher_r_17; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [17:0] higher_plus_one_r_17; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [17:0] higher_minus_one_r_17; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire [38:0] _io_out_s3_full_pred_1_targets_1_output = + {s3_ftb_entry_dup_1_tailSlot_sharing + ? {(_target_T_153 ? higher_plus_one_r_16 : 26'h0) + | (_target_T_154 ? higher_minus_one_r_16 : 26'h0) + | (_target_T_155 ? higher_r_16 : 26'h0), + s3_ftb_entry_dup_1_tailSlot_lower[11:0]} + : {(_target_T_153 ? higher_plus_one_r_17 : 18'h0) + | (_target_T_154 ? higher_minus_one_r_17 : 18'h0) + | (_target_T_155 ? higher_r_17 : 18'h0), + s3_ftb_entry_dup_1_tailSlot_lower}, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88 + wire _io_out_s3_full_pred_1_fallThroughErr_output = + {1'h0, s3_pc_dup_1[4:1]} >= {s3_ftb_entry_dup_1_carry, s3_ftb_entry_dup_1_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + reg [25:0] higher_r_18; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_18; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_18; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + reg [25:0] higher_r_19; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_19; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_19; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire _target_T_180 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88 + wire _target_T_181 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88 + wire _target_T_182 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88 + reg [17:0] higher_r_20; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [17:0] higher_plus_one_r_20; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [17:0] higher_minus_one_r_20; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire [38:0] _io_out_s3_full_pred_2_targets_1_output = + {s3_ftb_entry_dup_2_tailSlot_sharing + ? {(_target_T_180 ? higher_plus_one_r_19 : 26'h0) + | (_target_T_181 ? higher_minus_one_r_19 : 26'h0) + | (_target_T_182 ? higher_r_19 : 26'h0), + s3_ftb_entry_dup_2_tailSlot_lower[11:0]} + : {(_target_T_180 ? higher_plus_one_r_20 : 18'h0) + | (_target_T_181 ? higher_minus_one_r_20 : 18'h0) + | (_target_T_182 ? higher_r_20 : 18'h0), + s3_ftb_entry_dup_2_tailSlot_lower}, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88 + wire _io_out_s3_full_pred_2_fallThroughErr_output = + {1'h0, s3_pc_dup_2[4:1]} >= {s3_ftb_entry_dup_2_carry, s3_ftb_entry_dup_2_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + reg [25:0] higher_r_21; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_21; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_21; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + reg [25:0] higher_r_22; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [25:0] higher_plus_one_r_22; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [25:0] higher_minus_one_r_22; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire _target_T_207 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88 + wire _target_T_208 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88 + wire _target_T_209 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88 + reg [17:0] higher_r_23; // src/main/scala/xiangshan/frontend/FTB.scala:87:28 + reg [17:0] higher_plus_one_r_23; // src/main/scala/xiangshan/frontend/FTB.scala:88:37 + reg [17:0] higher_minus_one_r_23; // src/main/scala/xiangshan/frontend/FTB.scala:89:38 + wire [38:0] _io_out_s3_full_pred_3_targets_1_output = + {s3_ftb_entry_dup_3_tailSlot_sharing + ? {(_target_T_207 ? higher_plus_one_r_22 : 26'h0) + | (_target_T_208 ? higher_minus_one_r_22 : 26'h0) + | (_target_T_209 ? higher_r_22 : 26'h0), + s3_ftb_entry_dup_3_tailSlot_lower[11:0]} + : {(_target_T_207 ? higher_plus_one_r_23 : 18'h0) + | (_target_T_208 ? higher_minus_one_r_23 : 18'h0) + | (_target_T_209 ? higher_r_23 : 18'h0), + s3_ftb_entry_dup_3_tailSlot_lower}, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88 + wire _io_out_s3_full_pred_3_fallThroughErr_output = + {1'h0, s3_pc_dup_3[4:1]} >= {s3_ftb_entry_dup_3_carry, s3_ftb_entry_dup_3_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + reg [2:0] io_out_last_stage_meta_r; // src/main/scala/xiangshan/frontend/FTB.scala:458:48 + reg [2:0] io_out_last_stage_meta_r_1; // src/main/scala/xiangshan/frontend/FTB.scala:458:38 + wire u_valid = io_update_valid & ~io_update_bits_old_entry; // src/main/scala/xiangshan/frontend/FTB.scala:474:{33,36} + wire update_now = u_valid & io_update_bits_meta[0]; // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :480:28 + wire update_need_read = u_valid & ~(io_update_bits_meta[0]); // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :481:{34,37} + reg io_s1_ready_REG; // src/main/scala/xiangshan/frontend/FTB.scala:483:76 + wire [38:0] _ftb_write_tag_WIRE_2 = + update_now ? io_update_bits_pc : _delay2_pc_delay_io_out; // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :492:40, utility/src/main/scala/utility/Hold.scala:97:23 + reg [1:0] ftbBank_io_update_write_way_REG; // src/main/scala/xiangshan/frontend/FTB.scala:499:76 + reg ftbBank_io_update_write_alloc_REG; // src/main/scala/xiangshan/frontend/FTB.scala:500:76 + wire [38:0] _GEN = {3'h0, _reset_vector_delay_io_out}; // src/main/scala/xiangshan/frontend/BPU.scala:191:39, utility/src/main/scala/utility/Hold.scala:97:23 + always @(posedge clock) begin + if (REG_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16 + s1_pc_dup_0 <= _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + s1_pc_dup_1 <= _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + s1_pc_dup_2 <= _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + s1_pc_dup_3 <= _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + end + else begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16 + if (io_s0_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s1_pc_dup_0 <= io_in_bits_s0_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + if (io_s0_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s1_pc_dup_1 <= io_in_bits_s0_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + if (io_s0_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s1_pc_dup_2 <= io_in_bits_s0_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + if (io_s0_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s1_pc_dup_3 <= io_in_bits_s0_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + end + if (io_s1_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_pc_dup_0 <= s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 + s2_ftb_entry_dup_0_valid <= _ftbBank_io_read_resp_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_brSlots_0_sharing <= _ftbBank_io_read_resp_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_pftAddr <= _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_isCall <= _ftbBank_io_read_resp_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_isRet <= _ftbBank_io_read_resp_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_isJalr <= _ftbBank_io_read_resp_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_last_may_be_rvi_call <= + _ftbBank_io_read_resp_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_0_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + higher_r <= s1_pc_dup_0[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 + higher_plus_one_r <= 26'(s1_pc_dup_0[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} + higher_minus_one_r <= 26'(s1_pc_dup_0[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} + higher_r_1 <= s1_pc_dup_0[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 + higher_plus_one_r_1 <= 26'(s1_pc_dup_0[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} + higher_minus_one_r_1 <= 26'(s1_pc_dup_0[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} + higher_r_2 <= s1_pc_dup_0[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 + higher_plus_one_r_2 <= 18'(s1_pc_dup_0[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} + higher_minus_one_r_2 <= 18'(s1_pc_dup_0[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} + io_out_s2_full_pred_0_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23 + io_out_last_stage_meta_r <= + {_ftbBank_io_read_hits_bits, io_out_last_stage_meta_e_hit}; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :431:43, :458:{48,92} + end + if (io_s1_fire_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_pc_dup_1 <= s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 + s2_ftb_entry_dup_1_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_1_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_1_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_1_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_1_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_1_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_1_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_1_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_1_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_1_pftAddr <= _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_1_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_1_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_1_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + higher_r_3 <= s1_pc_dup_1[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 + higher_plus_one_r_3 <= 26'(s1_pc_dup_1[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} + higher_minus_one_r_3 <= 26'(s1_pc_dup_1[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} + higher_r_4 <= s1_pc_dup_1[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 + higher_plus_one_r_4 <= 26'(s1_pc_dup_1[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} + higher_minus_one_r_4 <= 26'(s1_pc_dup_1[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} + higher_r_5 <= s1_pc_dup_1[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 + higher_plus_one_r_5 <= 18'(s1_pc_dup_1[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} + higher_minus_one_r_5 <= 18'(s1_pc_dup_1[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} + io_out_s2_full_pred_1_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23 + end + if (io_s1_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_pc_dup_2 <= s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 + s2_ftb_entry_dup_2_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_pftAddr <= _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_isCall <= _ftbBank_io_read_resp_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_isRet <= _ftbBank_io_read_resp_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_isJalr <= _ftbBank_io_read_resp_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_last_may_be_rvi_call <= + _ftbBank_io_read_resp_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_2_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + higher_r_6 <= s1_pc_dup_2[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 + higher_plus_one_r_6 <= 26'(s1_pc_dup_2[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} + higher_minus_one_r_6 <= 26'(s1_pc_dup_2[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} + higher_r_7 <= s1_pc_dup_2[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 + higher_plus_one_r_7 <= 26'(s1_pc_dup_2[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} + higher_minus_one_r_7 <= 26'(s1_pc_dup_2[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} + higher_r_8 <= s1_pc_dup_2[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 + higher_plus_one_r_8 <= 18'(s1_pc_dup_2[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} + higher_minus_one_r_8 <= 18'(s1_pc_dup_2[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} + io_out_s2_full_pred_2_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23 + end + if (io_s1_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_pc_dup_3 <= s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 + s2_ftb_entry_dup_3_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_3_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_3_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_3_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_3_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_3_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_3_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_3_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_3_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_3_pftAddr <= _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_3_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_3_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + s2_ftb_entry_dup_3_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55 + higher_r_9 <= s1_pc_dup_3[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 + higher_plus_one_r_9 <= 26'(s1_pc_dup_3[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} + higher_minus_one_r_9 <= 26'(s1_pc_dup_3[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} + higher_r_10 <= s1_pc_dup_3[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 + higher_plus_one_r_10 <= 26'(s1_pc_dup_3[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} + higher_minus_one_r_10 <= 26'(s1_pc_dup_3[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} + higher_r_11 <= s1_pc_dup_3[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28 + higher_plus_one_r_11 <= 18'(s1_pc_dup_3[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53} + higher_minus_one_r_11 <= 18'(s1_pc_dup_3[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54} + io_out_s2_full_pred_3_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23 + end + if (io_s2_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_pc_dup_0 <= s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 + s3_ftb_entry_dup_0_valid <= s2_ftb_entry_dup_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_brSlots_0_offset <= s2_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_brSlots_0_lower <= s2_ftb_entry_dup_0_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_brSlots_0_tarStat <= s2_ftb_entry_dup_0_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_brSlots_0_sharing <= s2_ftb_entry_dup_0_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_brSlots_0_valid <= s2_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_tailSlot_offset <= s2_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_tailSlot_lower <= s2_ftb_entry_dup_0_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_tailSlot_tarStat <= s2_ftb_entry_dup_0_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_tailSlot_sharing <= s2_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_tailSlot_valid <= s2_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_pftAddr <= s2_ftb_entry_dup_0_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_carry <= s2_ftb_entry_dup_0_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_isCall <= s2_ftb_entry_dup_0_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_isRet <= s2_ftb_entry_dup_0_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_isJalr <= s2_ftb_entry_dup_0_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_last_may_be_rvi_call <= s2_ftb_entry_dup_0_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_always_taken_0 <= s2_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_0_always_taken_1 <= s2_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + higher_r_12 <= s2_pc_dup_0[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 + higher_plus_one_r_12 <= 26'(s2_pc_dup_0[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} + higher_minus_one_r_12 <= 26'(s2_pc_dup_0[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + higher_r_13 <= s2_pc_dup_0[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 + higher_plus_one_r_13 <= 26'(s2_pc_dup_0[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} + higher_minus_one_r_13 <= 26'(s2_pc_dup_0[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + higher_r_14 <= s2_pc_dup_0[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 + higher_plus_one_r_14 <= 18'(s2_pc_dup_0[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} + higher_minus_one_r_14 <= 18'(s2_pc_dup_0[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + io_out_last_stage_meta_r_1 <= io_out_last_stage_meta_r; // src/main/scala/xiangshan/frontend/FTB.scala:458:{38,48} + end + if (io_s2_fire_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_pc_dup_1 <= s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 + s3_ftb_entry_dup_1_brSlots_0_lower <= s2_ftb_entry_dup_1_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_1_brSlots_0_tarStat <= s2_ftb_entry_dup_1_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_1_brSlots_0_valid <= s2_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_1_tailSlot_lower <= s2_ftb_entry_dup_1_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_1_tailSlot_tarStat <= s2_ftb_entry_dup_1_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_1_tailSlot_sharing <= s2_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_1_tailSlot_valid <= s2_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_1_pftAddr <= s2_ftb_entry_dup_1_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_1_carry <= s2_ftb_entry_dup_1_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_1_always_taken_0 <= s2_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_1_always_taken_1 <= s2_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + higher_r_15 <= s2_pc_dup_1[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 + higher_plus_one_r_15 <= 26'(s2_pc_dup_1[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} + higher_minus_one_r_15 <= 26'(s2_pc_dup_1[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + higher_r_16 <= s2_pc_dup_1[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 + higher_plus_one_r_16 <= 26'(s2_pc_dup_1[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} + higher_minus_one_r_16 <= 26'(s2_pc_dup_1[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + higher_r_17 <= s2_pc_dup_1[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 + higher_plus_one_r_17 <= 18'(s2_pc_dup_1[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} + higher_minus_one_r_17 <= 18'(s2_pc_dup_1[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + end + if (io_s2_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_pc_dup_2 <= s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 + s3_ftb_entry_dup_2_brSlots_0_lower <= s2_ftb_entry_dup_2_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_2_brSlots_0_tarStat <= s2_ftb_entry_dup_2_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_2_brSlots_0_valid <= s2_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_2_tailSlot_lower <= s2_ftb_entry_dup_2_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_2_tailSlot_tarStat <= s2_ftb_entry_dup_2_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_2_tailSlot_sharing <= s2_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_2_tailSlot_valid <= s2_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_2_pftAddr <= s2_ftb_entry_dup_2_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_2_carry <= s2_ftb_entry_dup_2_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_2_isCall <= s2_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_2_isRet <= s2_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_2_isJalr <= s2_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_2_always_taken_0 <= s2_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_2_always_taken_1 <= s2_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + higher_r_18 <= s2_pc_dup_2[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 + higher_plus_one_r_18 <= 26'(s2_pc_dup_2[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} + higher_minus_one_r_18 <= 26'(s2_pc_dup_2[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + higher_r_19 <= s2_pc_dup_2[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 + higher_plus_one_r_19 <= 26'(s2_pc_dup_2[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} + higher_minus_one_r_19 <= 26'(s2_pc_dup_2[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + higher_r_20 <= s2_pc_dup_2[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 + higher_plus_one_r_20 <= 18'(s2_pc_dup_2[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} + higher_minus_one_r_20 <= 18'(s2_pc_dup_2[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + end + if (io_s2_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_pc_dup_3 <= s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 + s3_ftb_entry_dup_3_brSlots_0_offset <= s2_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_3_brSlots_0_lower <= s2_ftb_entry_dup_3_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_3_brSlots_0_tarStat <= s2_ftb_entry_dup_3_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_3_brSlots_0_valid <= s2_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_3_tailSlot_offset <= s2_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_3_tailSlot_lower <= s2_ftb_entry_dup_3_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_3_tailSlot_tarStat <= s2_ftb_entry_dup_3_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_3_tailSlot_sharing <= s2_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_3_tailSlot_valid <= s2_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_3_pftAddr <= s2_ftb_entry_dup_3_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_3_carry <= s2_ftb_entry_dup_3_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_3_always_taken_0 <= s2_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + s3_ftb_entry_dup_3_always_taken_1 <= s2_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88 + higher_r_21 <= s2_pc_dup_3[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 + higher_plus_one_r_21 <= 26'(s2_pc_dup_3[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} + higher_minus_one_r_21 <= 26'(s2_pc_dup_3[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + higher_r_22 <= s2_pc_dup_3[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 + higher_plus_one_r_22 <= 26'(s2_pc_dup_3[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} + higher_minus_one_r_22 <= 26'(s2_pc_dup_3[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + higher_r_23 <= s2_pc_dup_3[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28 + higher_plus_one_r_23 <= 18'(s2_pc_dup_3[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53} + higher_minus_one_r_23 <= 18'(s2_pc_dup_3[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54} + end + REG <= reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 + REG_1 <= REG & ~reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24,39,42} + io_s1_ready_REG <= update_need_read; // src/main/scala/xiangshan/frontend/FTB.scala:481:34, :483:76 + ftbBank_io_update_write_way_REG <= _ftbBank_io_update_hits_bits; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :499:76 + ftbBank_io_update_write_alloc_REG <= ~_ftbBank_io_update_hits_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :500:{76,77} + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) begin + s2_hit_dup_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 + s2_hit_dup_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 + s2_hit_dup_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 + s2_hit_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 + s3_hit_dup_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 + s3_hit_dup_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 + s3_hit_dup_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 + s3_hit_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 + end + else begin + if (io_s1_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_hit_dup_0 <= io_out_last_stage_meta_e_hit; // src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49 + if (io_s1_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_hit_dup_1 <= io_out_last_stage_meta_e_hit; // src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49 + if (io_s1_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_hit_dup_2 <= io_out_last_stage_meta_e_hit; // src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49 + if (io_s1_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_hit_dup_3 <= io_out_last_stage_meta_e_hit; // src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49 + if (io_s2_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_hit_dup_0 <= s2_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76 + if (io_s2_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_hit_dup_1 <= s2_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76 + if (io_s2_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_hit_dup_2 <= s2_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76 + if (io_s2_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_hit_dup_3 <= s2_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76 + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:84]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + initial begin // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + for (logic [6:0] i = 7'h0; i < 7'h55; i += 7'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + end // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s1_pc_dup_0 = {_RANDOM[7'h0], _RANDOM[7'h1][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s1_pc_dup_1 = {_RANDOM[7'h1][31:7], _RANDOM[7'h2][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s1_pc_dup_2 = {_RANDOM[7'h2][31:14], _RANDOM[7'h3][20:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s1_pc_dup_3 = {_RANDOM[7'h3][31:21], _RANDOM[7'h4][27:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s2_pc_dup_0 = {_RANDOM[7'h4][31:28], _RANDOM[7'h5], _RANDOM[7'h6][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s2_pc_dup_1 = {_RANDOM[7'h6][31:3], _RANDOM[7'h7][9:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s2_pc_dup_2 = {_RANDOM[7'h7][31:10], _RANDOM[7'h8][16:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s2_pc_dup_3 = {_RANDOM[7'h8][31:17], _RANDOM[7'h9][23:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s3_pc_dup_0 = {_RANDOM[7'h9][31:24], _RANDOM[7'hA][30:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s3_pc_dup_1 = {_RANDOM[7'hA][31], _RANDOM[7'hB], _RANDOM[7'hC][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s3_pc_dup_2 = {_RANDOM[7'hC][31:6], _RANDOM[7'hD][12:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s3_pc_dup_3 = {_RANDOM[7'hD][31:13], _RANDOM[7'hE][19:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + REG = _RANDOM[7'hE][20]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, :190:24, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + REG_1 = _RANDOM[7'hE][21]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, :190:16, src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s2_ftb_entry_dup_0_valid = _RANDOM[7'hE][23]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'hE][27:24]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_brSlots_0_lower = {_RANDOM[7'hE][31:28], _RANDOM[7'hF][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'hF][9:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'hF][10]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'hF][11]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'hF][15:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_tailSlot_lower = {_RANDOM[7'hF][31:16], _RANDOM[7'h10][3:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h10][5:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h10][6]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h10][7]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_pftAddr = _RANDOM[7'h10][11:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_carry = _RANDOM[7'h10][12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_isCall = _RANDOM[7'h10][13]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_isRet = _RANDOM[7'h10][14]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_isJalr = _RANDOM[7'h10][15]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h10][16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h10][17]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h10][18]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_1_brSlots_0_offset = _RANDOM[7'h10][23:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_1_brSlots_0_lower = {_RANDOM[7'h10][31:24], _RANDOM[7'h11][3:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h11][5:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h11][7]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_1_tailSlot_offset = _RANDOM[7'h11][11:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_1_tailSlot_lower = _RANDOM[7'h11][31:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h12][1:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h12][2]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h12][3]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_1_pftAddr = _RANDOM[7'h12][7:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_1_carry = _RANDOM[7'h12][8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h12][13]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h12][14]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_brSlots_0_offset = _RANDOM[7'h12][19:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_brSlots_0_lower = _RANDOM[7'h12][31:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h13][1:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h13][3]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_tailSlot_offset = _RANDOM[7'h13][7:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_tailSlot_lower = _RANDOM[7'h13][27:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h13][29:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h13][30]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h13][31]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_pftAddr = _RANDOM[7'h14][3:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_carry = _RANDOM[7'h14][4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_isCall = _RANDOM[7'h14][5]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_isRet = _RANDOM[7'h14][6]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_isJalr = _RANDOM[7'h14][7]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_last_may_be_rvi_call = _RANDOM[7'h14][8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h14][9]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h14][10]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h14][15:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_3_brSlots_0_lower = _RANDOM[7'h14][27:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h14][29:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h14][31]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h15][3:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_3_tailSlot_lower = _RANDOM[7'h15][23:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h15][25:24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h15][26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h15][27]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_3_pftAddr = _RANDOM[7'h15][31:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_3_carry = _RANDOM[7'h16][0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h16][5]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s2_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h16][6]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + s3_ftb_entry_dup_0_valid = _RANDOM[7'h16][7]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 + s3_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'h16][11:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 + s3_ftb_entry_dup_0_brSlots_0_lower = _RANDOM[7'h16][23:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 + s3_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'h16][25:24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 + s3_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'h16][26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 + s3_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'h16][27]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 + s3_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'h16][31:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88 + s3_ftb_entry_dup_0_tailSlot_lower = _RANDOM[7'h17][19:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h17][21:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h17][22]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h17][23]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_pftAddr = _RANDOM[7'h17][27:24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_carry = _RANDOM[7'h17][28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_isCall = _RANDOM[7'h17][29]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_isRet = _RANDOM[7'h17][30]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_isJalr = _RANDOM[7'h17][31]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h18][0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h18][1]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h18][2]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_1_brSlots_0_lower = _RANDOM[7'h18][19:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h18][21:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h18][23]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_1_tailSlot_lower = {_RANDOM[7'h18][31:28], _RANDOM[7'h19][15:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h19][17:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h19][18]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h19][19]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_1_pftAddr = _RANDOM[7'h19][23:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_1_carry = _RANDOM[7'h19][24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h19][29]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h19][30]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_brSlots_0_lower = _RANDOM[7'h1A][15:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h1A][17:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h1A][19]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_tailSlot_lower = {_RANDOM[7'h1A][31:24], _RANDOM[7'h1B][11:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h1B][13:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h1B][14]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h1B][15]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_pftAddr = _RANDOM[7'h1B][19:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_carry = _RANDOM[7'h1B][20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_isCall = _RANDOM[7'h1B][21]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_isRet = _RANDOM[7'h1B][22]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_isJalr = _RANDOM[7'h1B][23]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h1B][25]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h1B][26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h1B][31:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_brSlots_0_lower = _RANDOM[7'h1C][11:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h1C][13:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h1C][15]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h1C][19:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_tailSlot_lower = {_RANDOM[7'h1C][31:20], _RANDOM[7'h1D][7:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h1D][9:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h1D][10]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h1D][11]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_pftAddr = _RANDOM[7'h1D][15:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_carry = _RANDOM[7'h1D][16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h1D][21]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s3_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h1D][22]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + s2_hit_dup_0 = _RANDOM[7'h1D][23]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49 + s2_hit_dup_1 = _RANDOM[7'h1D][24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49 + s2_hit_dup_2 = _RANDOM[7'h1D][25]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49 + s2_hit_dup_3 = _RANDOM[7'h1D][26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49 + s3_hit_dup_0 = _RANDOM[7'h1D][27]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76 + s3_hit_dup_1 = _RANDOM[7'h1D][28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76 + s3_hit_dup_2 = _RANDOM[7'h1D][29]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76 + s3_hit_dup_3 = _RANDOM[7'h1D][30]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76 + higher_r = {_RANDOM[7'h1D][31], _RANDOM[7'h1E][24:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :284:7, :429:88 + higher_plus_one_r = {_RANDOM[7'h1E][31:25], _RANDOM[7'h1F][18:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r = {_RANDOM[7'h1F][31:19], _RANDOM[7'h20][12:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_1 = {_RANDOM[7'h20][31:13], _RANDOM[7'h21][6:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_1 = {_RANDOM[7'h21][31:7], _RANDOM[7'h22][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_1 = _RANDOM[7'h22][26:1]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_2 = {_RANDOM[7'h22][31:27], _RANDOM[7'h23][12:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_plus_one_r_2 = _RANDOM[7'h23][30:13]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_2 = {_RANDOM[7'h23][31], _RANDOM[7'h24][16:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + io_out_s2_full_pred_0_fallThroughAddr_stashed_carry = _RANDOM[7'h24][17]; // src/main/scala/xiangshan/frontend/FTB.scala:89:38, :177:36, :284:7 + higher_r_3 = {_RANDOM[7'h24][31:18], _RANDOM[7'h25][11:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_3 = {_RANDOM[7'h25][31:12], _RANDOM[7'h26][5:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_3 = _RANDOM[7'h26][31:6]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_4 = _RANDOM[7'h27][25:0]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :284:7 + higher_plus_one_r_4 = {_RANDOM[7'h27][31:26], _RANDOM[7'h28][19:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_4 = {_RANDOM[7'h28][31:20], _RANDOM[7'h29][13:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_5 = _RANDOM[7'h29][31:14]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_5 = _RANDOM[7'h2A][17:0]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :284:7 + higher_minus_one_r_5 = {_RANDOM[7'h2A][31:18], _RANDOM[7'h2B][3:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + io_out_s2_full_pred_1_fallThroughAddr_stashed_carry = _RANDOM[7'h2B][4]; // src/main/scala/xiangshan/frontend/FTB.scala:89:38, :177:36, :284:7 + higher_r_6 = _RANDOM[7'h2B][30:5]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_6 = {_RANDOM[7'h2B][31], _RANDOM[7'h2C][24:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_minus_one_r_6 = {_RANDOM[7'h2C][31:25], _RANDOM[7'h2D][18:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_7 = {_RANDOM[7'h2D][31:19], _RANDOM[7'h2E][12:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_7 = {_RANDOM[7'h2E][31:13], _RANDOM[7'h2F][6:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_7 = {_RANDOM[7'h2F][31:7], _RANDOM[7'h30][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_8 = _RANDOM[7'h30][18:1]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_8 = {_RANDOM[7'h30][31:19], _RANDOM[7'h31][4:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_minus_one_r_8 = _RANDOM[7'h31][22:5]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + io_out_s2_full_pred_2_fallThroughAddr_stashed_carry = _RANDOM[7'h31][23]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :177:36, :284:7 + higher_r_9 = {_RANDOM[7'h31][31:24], _RANDOM[7'h32][17:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_plus_one_r_9 = {_RANDOM[7'h32][31:18], _RANDOM[7'h33][11:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_9 = {_RANDOM[7'h33][31:12], _RANDOM[7'h34][5:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_10 = _RANDOM[7'h34][31:6]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_10 = _RANDOM[7'h35][25:0]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :284:7 + higher_minus_one_r_10 = {_RANDOM[7'h35][31:26], _RANDOM[7'h36][19:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_11 = {_RANDOM[7'h36][31:20], _RANDOM[7'h37][5:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_11 = _RANDOM[7'h37][23:6]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_11 = {_RANDOM[7'h37][31:24], _RANDOM[7'h38][9:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + io_out_s2_full_pred_3_fallThroughAddr_stashed_carry = _RANDOM[7'h38][10]; // src/main/scala/xiangshan/frontend/FTB.scala:89:38, :177:36, :284:7 + higher_r_12 = {_RANDOM[7'h38][31:11], _RANDOM[7'h39][4:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_12 = _RANDOM[7'h39][30:5]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_12 = {_RANDOM[7'h39][31], _RANDOM[7'h3A][24:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_r_13 = {_RANDOM[7'h3A][31:25], _RANDOM[7'h3B][18:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_13 = {_RANDOM[7'h3B][31:19], _RANDOM[7'h3C][12:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_13 = {_RANDOM[7'h3C][31:13], _RANDOM[7'h3D][6:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_14 = _RANDOM[7'h3D][24:7]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_14 = {_RANDOM[7'h3D][31:25], _RANDOM[7'h3E][10:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_minus_one_r_14 = _RANDOM[7'h3E][28:11]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_15 = {_RANDOM[7'h3E][31:29], _RANDOM[7'h3F][22:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_plus_one_r_15 = {_RANDOM[7'h3F][31:23], _RANDOM[7'h40][16:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_15 = {_RANDOM[7'h40][31:17], _RANDOM[7'h41][10:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_16 = {_RANDOM[7'h41][31:11], _RANDOM[7'h42][4:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_16 = _RANDOM[7'h42][30:5]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_16 = {_RANDOM[7'h42][31], _RANDOM[7'h43][24:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_r_17 = {_RANDOM[7'h43][31:25], _RANDOM[7'h44][10:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_17 = _RANDOM[7'h44][28:11]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_17 = {_RANDOM[7'h44][31:29], _RANDOM[7'h45][14:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_r_18 = {_RANDOM[7'h45][31:15], _RANDOM[7'h46][8:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_18 = {_RANDOM[7'h46][31:9], _RANDOM[7'h47][2:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_18 = _RANDOM[7'h47][28:3]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_19 = {_RANDOM[7'h47][31:29], _RANDOM[7'h48][22:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_plus_one_r_19 = {_RANDOM[7'h48][31:23], _RANDOM[7'h49][16:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_19 = {_RANDOM[7'h49][31:17], _RANDOM[7'h4A][10:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_20 = _RANDOM[7'h4A][28:11]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_20 = {_RANDOM[7'h4A][31:29], _RANDOM[7'h4B][14:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_minus_one_r_20 = {_RANDOM[7'h4B][31:15], _RANDOM[7'h4C][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_21 = _RANDOM[7'h4C][26:1]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_21 = {_RANDOM[7'h4C][31:27], _RANDOM[7'h4D][20:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_minus_one_r_21 = {_RANDOM[7'h4D][31:21], _RANDOM[7'h4E][14:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_22 = {_RANDOM[7'h4E][31:15], _RANDOM[7'h4F][8:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7 + higher_plus_one_r_22 = {_RANDOM[7'h4F][31:9], _RANDOM[7'h50][2:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_22 = _RANDOM[7'h50][28:3]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + higher_r_23 = {_RANDOM[7'h50][31:29], _RANDOM[7'h51][14:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_plus_one_r_23 = {_RANDOM[7'h51][31:15], _RANDOM[7'h52][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7 + higher_minus_one_r_23 = _RANDOM[7'h52][18:1]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7 + io_out_last_stage_meta_r = _RANDOM[7'h54][21:19]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:48 + io_out_last_stage_meta_r_1 = _RANDOM[7'h54][24:22]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:{38,48} + io_s1_ready_REG = _RANDOM[7'h54][25]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:48, :483:76 + ftbBank_io_update_write_way_REG = _RANDOM[7'h54][27:26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:48, :499:76 + ftbBank_io_update_write_alloc_REG = _RANDOM[7'h54][28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:48, :500:76 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + s2_hit_dup_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 + s2_hit_dup_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 + s2_hit_dup_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 + s2_hit_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49 + s3_hit_dup_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 + s3_hit_dup_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 + s3_hit_dup_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 + s3_hit_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:284:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + DelayN_2 reset_vector_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + .clock (clock), + .io_in (io_reset_vector), + .io_out (_reset_vector_delay_io_out) + ); + FTBBank ftbBank ( // src/main/scala/xiangshan/frontend/FTB.scala:422:23 + .clock (clock), + .reset (reset), + .io_s1_fire (io_s1_fire_0), + .io_req_pc_ready (_ftbBank_io_req_pc_ready), + .io_req_pc_valid (io_s0_fire_0), + .io_req_pc_bits (io_in_bits_s0_pc_0), + .io_read_resp_valid (_ftbBank_io_read_resp_valid), + .io_read_resp_brSlots_0_offset + (_ftbBank_io_read_resp_brSlots_0_offset), + .io_read_resp_brSlots_0_lower + (_ftbBank_io_read_resp_brSlots_0_lower), + .io_read_resp_brSlots_0_tarStat + (_ftbBank_io_read_resp_brSlots_0_tarStat), + .io_read_resp_brSlots_0_sharing + (_ftbBank_io_read_resp_brSlots_0_sharing), + .io_read_resp_brSlots_0_valid + (_ftbBank_io_read_resp_brSlots_0_valid), + .io_read_resp_tailSlot_offset + (_ftbBank_io_read_resp_tailSlot_offset), + .io_read_resp_tailSlot_lower + (_ftbBank_io_read_resp_tailSlot_lower), + .io_read_resp_tailSlot_tarStat + (_ftbBank_io_read_resp_tailSlot_tarStat), + .io_read_resp_tailSlot_sharing + (_ftbBank_io_read_resp_tailSlot_sharing), + .io_read_resp_tailSlot_valid + (_ftbBank_io_read_resp_tailSlot_valid), + .io_read_resp_pftAddr (_ftbBank_io_read_resp_pftAddr), + .io_read_resp_carry (_ftbBank_io_read_resp_carry), + .io_read_resp_isCall (_ftbBank_io_read_resp_isCall), + .io_read_resp_isRet (_ftbBank_io_read_resp_isRet), + .io_read_resp_isJalr (_ftbBank_io_read_resp_isJalr), + .io_read_resp_last_may_be_rvi_call + (_ftbBank_io_read_resp_last_may_be_rvi_call), + .io_read_resp_always_taken_0 + (_ftbBank_io_read_resp_always_taken_0), + .io_read_resp_always_taken_1 + (_ftbBank_io_read_resp_always_taken_1), + .io_read_hits_valid (_ftbBank_io_read_hits_valid), + .io_read_hits_bits (_ftbBank_io_read_hits_bits), + .io_u_req_pc_valid (update_need_read), // src/main/scala/xiangshan/frontend/FTB.scala:481:34 + .io_u_req_pc_bits (io_update_bits_pc), + .io_update_hits_valid (_ftbBank_io_update_hits_valid), + .io_update_hits_bits (_ftbBank_io_update_hits_bits), + .io_update_access + (u_valid & ~(io_update_bits_meta[0])), // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :481:37, :501:39 + .io_update_pc (_ftb_write_tag_WIRE_2), // src/main/scala/xiangshan/frontend/FTB.scala:492:40 + .io_update_write_data_valid + (update_now | _write_valid_delay_io_out), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :494:32, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_valid + (update_now ? io_update_bits_ftb_entry_valid : _delay2_entry_delay_io_out_valid), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_brSlots_0_offset + (update_now + ? io_update_bits_ftb_entry_brSlots_0_offset + : _delay2_entry_delay_io_out_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_brSlots_0_lower + (update_now + ? io_update_bits_ftb_entry_brSlots_0_lower + : _delay2_entry_delay_io_out_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_brSlots_0_tarStat + (update_now + ? io_update_bits_ftb_entry_brSlots_0_tarStat + : _delay2_entry_delay_io_out_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_brSlots_0_sharing + (update_now + ? io_update_bits_ftb_entry_brSlots_0_sharing + : _delay2_entry_delay_io_out_brSlots_0_sharing), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_brSlots_0_valid + (update_now + ? io_update_bits_ftb_entry_brSlots_0_valid + : _delay2_entry_delay_io_out_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_tailSlot_offset + (update_now + ? io_update_bits_ftb_entry_tailSlot_offset + : _delay2_entry_delay_io_out_tailSlot_offset), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_tailSlot_lower + (update_now + ? io_update_bits_ftb_entry_tailSlot_lower + : _delay2_entry_delay_io_out_tailSlot_lower), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_tailSlot_tarStat + (update_now + ? io_update_bits_ftb_entry_tailSlot_tarStat + : _delay2_entry_delay_io_out_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_tailSlot_sharing + (update_now + ? io_update_bits_ftb_entry_tailSlot_sharing + : _delay2_entry_delay_io_out_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_tailSlot_valid + (update_now + ? io_update_bits_ftb_entry_tailSlot_valid + : _delay2_entry_delay_io_out_tailSlot_valid), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_pftAddr + (update_now + ? io_update_bits_ftb_entry_pftAddr + : _delay2_entry_delay_io_out_pftAddr), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_carry + (update_now ? io_update_bits_ftb_entry_carry : _delay2_entry_delay_io_out_carry), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_isCall + (update_now ? io_update_bits_ftb_entry_isCall : _delay2_entry_delay_io_out_isCall), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_isRet + (update_now ? io_update_bits_ftb_entry_isRet : _delay2_entry_delay_io_out_isRet), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_isJalr + (update_now ? io_update_bits_ftb_entry_isJalr : _delay2_entry_delay_io_out_isJalr), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_last_may_be_rvi_call + (update_now + ? io_update_bits_ftb_entry_last_may_be_rvi_call + : _delay2_entry_delay_io_out_last_may_be_rvi_call), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_always_taken_0 + (update_now + ? io_update_bits_ftb_entry_always_taken_0 + : _delay2_entry_delay_io_out_always_taken_0), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_entry_always_taken_1 + (update_now + ? io_update_bits_ftb_entry_always_taken_1 + : _delay2_entry_delay_io_out_always_taken_1), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23 + .io_update_write_data_bits_tag (_ftb_write_tag_WIRE_2[29:10]), // src/main/scala/xiangshan/frontend/FTB.scala:492:{40,75} + .io_update_write_way + (update_now ? io_update_bits_meta[2:1] : ftbBank_io_update_write_way_REG), // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :480:28, :499:{39,76} + .io_update_write_alloc + (~update_now & ftbBank_io_update_write_alloc_REG) // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :500:{39,76} + ); + DelayN_4 delay2_pc_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + .clock (clock), + .io_in (io_update_bits_pc), + .io_out (_delay2_pc_delay_io_out) + ); + DelayN_5 delay2_entry_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + .clock (clock), + .io_in_valid (io_update_bits_ftb_entry_valid), + .io_in_brSlots_0_offset (io_update_bits_ftb_entry_brSlots_0_offset), + .io_in_brSlots_0_lower (io_update_bits_ftb_entry_brSlots_0_lower), + .io_in_brSlots_0_tarStat (io_update_bits_ftb_entry_brSlots_0_tarStat), + .io_in_brSlots_0_sharing (io_update_bits_ftb_entry_brSlots_0_sharing), + .io_in_brSlots_0_valid (io_update_bits_ftb_entry_brSlots_0_valid), + .io_in_tailSlot_offset (io_update_bits_ftb_entry_tailSlot_offset), + .io_in_tailSlot_lower (io_update_bits_ftb_entry_tailSlot_lower), + .io_in_tailSlot_tarStat (io_update_bits_ftb_entry_tailSlot_tarStat), + .io_in_tailSlot_sharing (io_update_bits_ftb_entry_tailSlot_sharing), + .io_in_tailSlot_valid (io_update_bits_ftb_entry_tailSlot_valid), + .io_in_pftAddr (io_update_bits_ftb_entry_pftAddr), + .io_in_carry (io_update_bits_ftb_entry_carry), + .io_in_isCall (io_update_bits_ftb_entry_isCall), + .io_in_isRet (io_update_bits_ftb_entry_isRet), + .io_in_isJalr (io_update_bits_ftb_entry_isJalr), + .io_in_last_may_be_rvi_call (io_update_bits_ftb_entry_last_may_be_rvi_call), + .io_in_always_taken_0 (io_update_bits_ftb_entry_always_taken_0), + .io_in_always_taken_1 (io_update_bits_ftb_entry_always_taken_1), + .io_out_valid (_delay2_entry_delay_io_out_valid), + .io_out_brSlots_0_offset (_delay2_entry_delay_io_out_brSlots_0_offset), + .io_out_brSlots_0_lower (_delay2_entry_delay_io_out_brSlots_0_lower), + .io_out_brSlots_0_tarStat (_delay2_entry_delay_io_out_brSlots_0_tarStat), + .io_out_brSlots_0_sharing (_delay2_entry_delay_io_out_brSlots_0_sharing), + .io_out_brSlots_0_valid (_delay2_entry_delay_io_out_brSlots_0_valid), + .io_out_tailSlot_offset (_delay2_entry_delay_io_out_tailSlot_offset), + .io_out_tailSlot_lower (_delay2_entry_delay_io_out_tailSlot_lower), + .io_out_tailSlot_tarStat (_delay2_entry_delay_io_out_tailSlot_tarStat), + .io_out_tailSlot_sharing (_delay2_entry_delay_io_out_tailSlot_sharing), + .io_out_tailSlot_valid (_delay2_entry_delay_io_out_tailSlot_valid), + .io_out_pftAddr (_delay2_entry_delay_io_out_pftAddr), + .io_out_carry (_delay2_entry_delay_io_out_carry), + .io_out_isCall (_delay2_entry_delay_io_out_isCall), + .io_out_isRet (_delay2_entry_delay_io_out_isRet), + .io_out_isJalr (_delay2_entry_delay_io_out_isJalr), + .io_out_last_may_be_rvi_call (_delay2_entry_delay_io_out_last_may_be_rvi_call), + .io_out_always_taken_0 (_delay2_entry_delay_io_out_always_taken_0), + .io_out_always_taken_1 (_delay2_entry_delay_io_out_always_taken_1) + ); + DelayN_6 write_valid_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + .clock (clock), + .io_in (u_valid & ~(io_update_bits_meta[0])), // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :481:37, :494:50 + .io_out (_write_valid_delay_io_out) + ); + assign io_out_s2_full_pred_0_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 | s2_hit_dup_0 + & s2_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} + assign io_out_s2_full_pred_0_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 | s2_hit_dup_0 + & s2_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} + assign io_out_s2_full_pred_0_slot_valids_0 = s2_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_0_slot_valids_1 = s2_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_0_targets_0 = + {(s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r : 26'h0) + | (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r : 26'h0) + | (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r : 26'h0), + s2_ftb_entry_dup_0_brSlots_0_lower, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55 + assign io_out_s2_full_pred_0_targets_1 = _io_out_s2_full_pred_0_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s2_full_pred_0_jalr_target = _io_out_s2_full_pred_0_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s2_full_pred_0_offsets_0 = s2_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_0_offsets_1 = s2_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_0_fallThroughAddr = + {1'h0, s2_pc_dup_0[4:1]} >= {s2_ftb_entry_dup_0_carry, s2_ftb_entry_dup_0_pftAddr} + ? 39'(s2_pc_dup_0 + 39'h20) + : {io_out_s2_full_pred_0_fallThroughAddr_stashed_carry + ? 34'(s2_pc_dup_0[38:5] + 34'h1) + : s2_pc_dup_0[38:5], + s2_ftb_entry_dup_0_pftAddr, + 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34, :550:{27,47} + assign io_out_s2_full_pred_0_is_br_sharing = + s2_ftb_entry_dup_0_tailSlot_valid & s2_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 + assign io_out_s2_full_pred_0_hit = s2_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49 + assign io_out_s2_full_pred_1_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 | s2_hit_dup_1 + & s2_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} + assign io_out_s2_full_pred_1_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 | s2_hit_dup_1 + & s2_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} + assign io_out_s2_full_pred_1_slot_valids_0 = s2_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_1_slot_valids_1 = s2_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_1_targets_0 = + {(s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_3 : 26'h0) + | (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_3 : 26'h0) + | (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_3 : 26'h0), + s2_ftb_entry_dup_1_brSlots_0_lower, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55 + assign io_out_s2_full_pred_1_targets_1 = _io_out_s2_full_pred_1_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s2_full_pred_1_jalr_target = _io_out_s2_full_pred_1_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s2_full_pred_1_offsets_0 = s2_ftb_entry_dup_1_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_1_offsets_1 = s2_ftb_entry_dup_1_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_1_fallThroughAddr = + {1'h0, s2_pc_dup_1[4:1]} >= {s2_ftb_entry_dup_1_carry, s2_ftb_entry_dup_1_pftAddr} + ? 39'(s2_pc_dup_1 + 39'h20) + : {io_out_s2_full_pred_1_fallThroughAddr_stashed_carry + ? 34'(s2_pc_dup_1[38:5] + 34'h1) + : s2_pc_dup_1[38:5], + s2_ftb_entry_dup_1_pftAddr, + 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34, :550:{27,47} + assign io_out_s2_full_pred_1_is_br_sharing = + s2_ftb_entry_dup_1_tailSlot_valid & s2_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 + assign io_out_s2_full_pred_1_hit = s2_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49 + assign io_out_s2_full_pred_2_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 | s2_hit_dup_2 + & s2_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} + assign io_out_s2_full_pred_2_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 | s2_hit_dup_2 + & s2_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} + assign io_out_s2_full_pred_2_slot_valids_0 = s2_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_2_slot_valids_1 = s2_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_2_targets_0 = + {(s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_6 : 26'h0) + | (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_6 : 26'h0) + | (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_6 : 26'h0), + s2_ftb_entry_dup_2_brSlots_0_lower, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55 + assign io_out_s2_full_pred_2_targets_1 = _io_out_s2_full_pred_2_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s2_full_pred_2_jalr_target = _io_out_s2_full_pred_2_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s2_full_pred_2_offsets_0 = s2_ftb_entry_dup_2_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_2_offsets_1 = s2_ftb_entry_dup_2_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_2_fallThroughAddr = + {1'h0, s2_pc_dup_2[4:1]} >= {s2_ftb_entry_dup_2_carry, s2_ftb_entry_dup_2_pftAddr} + ? 39'(s2_pc_dup_2 + 39'h20) + : {io_out_s2_full_pred_2_fallThroughAddr_stashed_carry + ? 34'(s2_pc_dup_2[38:5] + 34'h1) + : s2_pc_dup_2[38:5], + s2_ftb_entry_dup_2_pftAddr, + 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34, :550:{27,47} + assign io_out_s2_full_pred_2_is_jalr = + s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:540:37 + assign io_out_s2_full_pred_2_is_call = + s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:541:37 + assign io_out_s2_full_pred_2_is_ret = + s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:542:36 + assign io_out_s2_full_pred_2_last_may_be_rvi_call = + s2_ftb_entry_dup_2_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_2_is_br_sharing = + s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 + assign io_out_s2_full_pred_2_hit = s2_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49 + assign io_out_s2_full_pred_3_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 | s2_hit_dup_3 + & s2_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} + assign io_out_s2_full_pred_3_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 | s2_hit_dup_3 + & s2_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67} + assign io_out_s2_full_pred_3_slot_valids_0 = s2_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_3_slot_valids_1 = s2_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_3_targets_0 = + {(s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_9 : 26'h0) + | (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_9 : 26'h0) + | (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_9 : 26'h0), + s2_ftb_entry_dup_3_brSlots_0_lower, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55 + assign io_out_s2_full_pred_3_targets_1 = _io_out_s2_full_pred_3_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s2_full_pred_3_jalr_target = _io_out_s2_full_pred_3_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s2_full_pred_3_offsets_0 = s2_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_3_offsets_1 = s2_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55 + assign io_out_s2_full_pred_3_fallThroughAddr = + _io_out_s2_full_pred_3_fallThroughErr_output + ? 39'(s2_pc_dup_3 + 39'h20) + : {io_out_s2_full_pred_3_fallThroughAddr_stashed_carry + ? 34'(s2_pc_dup_3[38:5] + 34'h1) + : s2_pc_dup_3[38:5], + s2_ftb_entry_dup_3_pftAddr, + 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47} + assign io_out_s2_full_pred_3_fallThroughErr = + _io_out_s2_full_pred_3_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34 + assign io_out_s2_full_pred_3_is_br_sharing = + s2_ftb_entry_dup_3_tailSlot_valid & s2_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 + assign io_out_s2_full_pred_3_hit = s2_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49 + assign io_out_s3_full_pred_0_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 | s3_hit_dup_0 + & s3_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} + assign io_out_s3_full_pred_0_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 | s3_hit_dup_0 + & s3_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} + assign io_out_s3_full_pred_0_slot_valids_0 = s3_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_s3_full_pred_0_slot_valids_1 = s3_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_s3_full_pred_0_targets_0 = + {(s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_12 : 26'h0) + | (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_12 : 26'h0) + | (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r_12 : 26'h0), + s3_ftb_entry_dup_0_brSlots_0_lower, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88 + assign io_out_s3_full_pred_0_targets_1 = _io_out_s3_full_pred_0_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s3_full_pred_0_jalr_target = _io_out_s3_full_pred_0_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s3_full_pred_0_fallThroughAddr = + _io_out_s3_full_pred_0_fallThroughErr_output + ? 39'(s3_pc_dup_0 + 39'h20) + : {s3_ftb_entry_dup_0_carry ? 34'(s3_pc_dup_0[38:5] + 34'h1) : s3_pc_dup_0[38:5], + s3_ftb_entry_dup_0_pftAddr, + 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47} + assign io_out_s3_full_pred_0_fallThroughErr = + _io_out_s3_full_pred_0_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34 + assign io_out_s3_full_pred_0_is_br_sharing = + s3_ftb_entry_dup_0_tailSlot_valid & s3_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 + assign io_out_s3_full_pred_0_hit = s3_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76 + assign io_out_s3_full_pred_1_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 | s3_hit_dup_1 + & s3_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} + assign io_out_s3_full_pred_1_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 | s3_hit_dup_1 + & s3_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} + assign io_out_s3_full_pred_1_slot_valids_0 = s3_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_s3_full_pred_1_slot_valids_1 = s3_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_s3_full_pred_1_targets_0 = + {(s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_15 : 26'h0) + | (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_15 : 26'h0) + | (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_15 : 26'h0), + s3_ftb_entry_dup_1_brSlots_0_lower, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88 + assign io_out_s3_full_pred_1_targets_1 = _io_out_s3_full_pred_1_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s3_full_pred_1_jalr_target = _io_out_s3_full_pred_1_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s3_full_pred_1_fallThroughAddr = + _io_out_s3_full_pred_1_fallThroughErr_output + ? 39'(s3_pc_dup_1 + 39'h20) + : {s3_ftb_entry_dup_1_carry ? 34'(s3_pc_dup_1[38:5] + 34'h1) : s3_pc_dup_1[38:5], + s3_ftb_entry_dup_1_pftAddr, + 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47} + assign io_out_s3_full_pred_1_fallThroughErr = + _io_out_s3_full_pred_1_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34 + assign io_out_s3_full_pred_1_is_br_sharing = + s3_ftb_entry_dup_1_tailSlot_valid & s3_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 + assign io_out_s3_full_pred_1_hit = s3_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76 + assign io_out_s3_full_pred_2_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 | s3_hit_dup_2 + & s3_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} + assign io_out_s3_full_pred_2_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 | s3_hit_dup_2 + & s3_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} + assign io_out_s3_full_pred_2_slot_valids_0 = s3_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_s3_full_pred_2_slot_valids_1 = s3_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_s3_full_pred_2_targets_0 = + {(s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_18 : 26'h0) + | (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_18 : 26'h0) + | (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_18 : 26'h0), + s3_ftb_entry_dup_2_brSlots_0_lower, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88 + assign io_out_s3_full_pred_2_targets_1 = _io_out_s3_full_pred_2_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s3_full_pred_2_jalr_target = _io_out_s3_full_pred_2_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s3_full_pred_2_fallThroughAddr = + _io_out_s3_full_pred_2_fallThroughErr_output + ? 39'(s3_pc_dup_2 + 39'h20) + : {s3_ftb_entry_dup_2_carry ? 34'(s3_pc_dup_2[38:5] + 34'h1) : s3_pc_dup_2[38:5], + s3_ftb_entry_dup_2_pftAddr, + 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47} + assign io_out_s3_full_pred_2_fallThroughErr = + _io_out_s3_full_pred_2_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34 + assign io_out_s3_full_pred_2_is_jalr = + s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:540:37 + assign io_out_s3_full_pred_2_is_call = + s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:541:37 + assign io_out_s3_full_pred_2_is_ret = + s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:542:36 + assign io_out_s3_full_pred_2_is_br_sharing = + s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 + assign io_out_s3_full_pred_2_hit = s3_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76 + assign io_out_s3_full_pred_3_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 | s3_hit_dup_3 + & s3_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} + assign io_out_s3_full_pred_3_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 | s3_hit_dup_3 + & s3_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67} + assign io_out_s3_full_pred_3_slot_valids_0 = s3_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_s3_full_pred_3_slot_valids_1 = s3_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_s3_full_pred_3_targets_0 = + {(s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_21 : 26'h0) + | (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_21 : 26'h0) + | (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_21 : 26'h0), + s3_ftb_entry_dup_3_brSlots_0_lower, + 1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88 + assign io_out_s3_full_pred_3_targets_1 = _io_out_s3_full_pred_3_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s3_full_pred_3_jalr_target = _io_out_s3_full_pred_3_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7 + assign io_out_s3_full_pred_3_offsets_0 = s3_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_s3_full_pred_3_offsets_1 = s3_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_s3_full_pred_3_fallThroughAddr = + _io_out_s3_full_pred_3_fallThroughErr_output + ? 39'(s3_pc_dup_3 + 39'h20) + : {s3_ftb_entry_dup_3_carry ? 34'(s3_pc_dup_3[38:5] + 34'h1) : s3_pc_dup_3[38:5], + s3_ftb_entry_dup_3_pftAddr, + 1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47} + assign io_out_s3_full_pred_3_fallThroughErr = + _io_out_s3_full_pred_3_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34 + assign io_out_s3_full_pred_3_is_br_sharing = + s3_ftb_entry_dup_3_tailSlot_valid & s3_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43 + assign io_out_s3_full_pred_3_hit = s3_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76 + assign io_out_last_stage_meta = {216'h0, io_out_last_stage_meta_r_1}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:{26,38} + assign io_out_last_stage_ftb_entry_valid = s3_ftb_entry_dup_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_brSlots_0_offset = + s3_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_brSlots_0_lower = s3_ftb_entry_dup_0_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_brSlots_0_tarStat = + s3_ftb_entry_dup_0_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_brSlots_0_sharing = + s3_ftb_entry_dup_0_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_brSlots_0_valid = s3_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_tailSlot_offset = s3_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_tailSlot_lower = s3_ftb_entry_dup_0_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_tailSlot_tarStat = + s3_ftb_entry_dup_0_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_tailSlot_sharing = + s3_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_tailSlot_valid = s3_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_pftAddr = s3_ftb_entry_dup_0_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_carry = s3_ftb_entry_dup_0_carry; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_isCall = s3_ftb_entry_dup_0_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_isRet = s3_ftb_entry_dup_0_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_isJalr = s3_ftb_entry_dup_0_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_last_may_be_rvi_call = + s3_ftb_entry_dup_0_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_always_taken_0 = s3_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_out_last_stage_ftb_entry_always_taken_1 = s3_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88 + assign io_s1_ready = _ftbBank_io_req_pc_ready & ~update_need_read & ~io_s1_ready_REG; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :422:23, :481:34, :483:{45,65,68,76} +endmodule + diff --git a/src/FTB/FTBBank.sv b/src/FTB/FTBBank.sv new file mode 100644 index 0000000..277e35b --- /dev/null +++ b/src/FTB/FTBBank.sv @@ -0,0 +1,8418 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FTBBank( // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + input clock, + input reset, + input io_s1_fire, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_req_pc_ready, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_req_pc_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input [38:0] io_req_pc_bits, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_read_resp_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output [3:0] io_read_resp_brSlots_0_offset, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output [11:0] io_read_resp_brSlots_0_lower, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output [1:0] io_read_resp_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_read_resp_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_read_resp_brSlots_0_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output [3:0] io_read_resp_tailSlot_offset, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output [19:0] io_read_resp_tailSlot_lower, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output [1:0] io_read_resp_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_read_resp_tailSlot_sharing, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_read_resp_tailSlot_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output [3:0] io_read_resp_pftAddr, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_read_resp_carry, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_read_resp_isCall, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_read_resp_isRet, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_read_resp_isJalr, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_read_resp_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_read_resp_always_taken_0, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_read_resp_always_taken_1, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_read_hits_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output [1:0] io_read_hits_bits, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_u_req_pc_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input [38:0] io_u_req_pc_bits, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output io_update_hits_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + output [1:0] io_update_hits_bits, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_access, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_data_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_data_bits_entry_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input [3:0] io_update_write_data_bits_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input [11:0] io_update_write_data_bits_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input [1:0] io_update_write_data_bits_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_data_bits_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_data_bits_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input [3:0] io_update_write_data_bits_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input [19:0] io_update_write_data_bits_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input [1:0] io_update_write_data_bits_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_data_bits_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_data_bits_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input [3:0] io_update_write_data_bits_entry_pftAddr, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_data_bits_entry_carry, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_data_bits_entry_isCall, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_data_bits_entry_isRet, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_data_bits_entry_isJalr, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_data_bits_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_data_bits_entry_always_taken_0, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_data_bits_entry_always_taken_1, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input [19:0] io_update_write_data_bits_tag, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input [1:0] io_update_write_way, // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + input io_update_write_alloc // src/main/scala/xiangshan/frontend/FTB.scala:291:16 +); + + wire _ftb_io_r_resp_data_0_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [3:0] _ftb_io_r_resp_data_0_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [11:0] _ftb_io_r_resp_data_0_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [1:0] _ftb_io_r_resp_data_0_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_0_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_0_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [3:0] _ftb_io_r_resp_data_0_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [19:0] _ftb_io_r_resp_data_0_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [1:0] _ftb_io_r_resp_data_0_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_0_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_0_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [3:0] _ftb_io_r_resp_data_0_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_0_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_0_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_0_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_0_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_0_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_0_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_0_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [19:0] _ftb_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_1_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [3:0] _ftb_io_r_resp_data_1_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [11:0] _ftb_io_r_resp_data_1_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [1:0] _ftb_io_r_resp_data_1_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_1_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_1_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [3:0] _ftb_io_r_resp_data_1_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [19:0] _ftb_io_r_resp_data_1_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [1:0] _ftb_io_r_resp_data_1_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_1_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_1_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [3:0] _ftb_io_r_resp_data_1_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_1_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_1_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_1_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_1_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_1_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_1_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_1_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [19:0] _ftb_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_2_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [3:0] _ftb_io_r_resp_data_2_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [11:0] _ftb_io_r_resp_data_2_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [1:0] _ftb_io_r_resp_data_2_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_2_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_2_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [3:0] _ftb_io_r_resp_data_2_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [19:0] _ftb_io_r_resp_data_2_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [1:0] _ftb_io_r_resp_data_2_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_2_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_2_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [3:0] _ftb_io_r_resp_data_2_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_2_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_2_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_2_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_2_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_2_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_2_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_2_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [19:0] _ftb_io_r_resp_data_2_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_3_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [3:0] _ftb_io_r_resp_data_3_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [11:0] _ftb_io_r_resp_data_3_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [1:0] _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_3_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_3_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [3:0] _ftb_io_r_resp_data_3_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [19:0] _ftb_io_r_resp_data_3_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [1:0] _ftb_io_r_resp_data_3_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_3_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_3_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [3:0] _ftb_io_r_resp_data_3_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_3_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_3_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_3_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_3_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_3_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire _ftb_io_r_resp_data_3_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + wire [19:0] _ftb_io_r_resp_data_3_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + reg pred_rdata_REG; // src/main/scala/xiangshan/frontend/FTB.scala:315:62 + reg pred_rdata_hold_data_0_entry_valid; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [3:0] pred_rdata_hold_data_0_entry_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [11:0] pred_rdata_hold_data_0_entry_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] pred_rdata_hold_data_0_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_0_entry_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_0_entry_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [3:0] pred_rdata_hold_data_0_entry_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [19:0] pred_rdata_hold_data_0_entry_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] pred_rdata_hold_data_0_entry_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_0_entry_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_0_entry_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [3:0] pred_rdata_hold_data_0_entry_pftAddr; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_0_entry_carry; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_0_entry_isCall; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_0_entry_isRet; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_0_entry_isJalr; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_0_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_0_entry_always_taken_0; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_0_entry_always_taken_1; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [19:0] pred_rdata_hold_data_0_tag; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_1_entry_valid; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [3:0] pred_rdata_hold_data_1_entry_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [11:0] pred_rdata_hold_data_1_entry_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] pred_rdata_hold_data_1_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_1_entry_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_1_entry_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [3:0] pred_rdata_hold_data_1_entry_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [19:0] pred_rdata_hold_data_1_entry_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] pred_rdata_hold_data_1_entry_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_1_entry_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_1_entry_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [3:0] pred_rdata_hold_data_1_entry_pftAddr; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_1_entry_carry; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_1_entry_isCall; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_1_entry_isRet; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_1_entry_isJalr; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_1_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_1_entry_always_taken_0; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_1_entry_always_taken_1; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [19:0] pred_rdata_hold_data_1_tag; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_2_entry_valid; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [3:0] pred_rdata_hold_data_2_entry_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [11:0] pred_rdata_hold_data_2_entry_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] pred_rdata_hold_data_2_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_2_entry_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_2_entry_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [3:0] pred_rdata_hold_data_2_entry_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [19:0] pred_rdata_hold_data_2_entry_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] pred_rdata_hold_data_2_entry_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_2_entry_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_2_entry_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [3:0] pred_rdata_hold_data_2_entry_pftAddr; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_2_entry_carry; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_2_entry_isCall; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_2_entry_isRet; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_2_entry_isJalr; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_2_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_2_entry_always_taken_0; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_2_entry_always_taken_1; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [19:0] pred_rdata_hold_data_2_tag; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_3_entry_valid; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [3:0] pred_rdata_hold_data_3_entry_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [11:0] pred_rdata_hold_data_3_entry_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] pred_rdata_hold_data_3_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_3_entry_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_3_entry_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [3:0] pred_rdata_hold_data_3_entry_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [19:0] pred_rdata_hold_data_3_entry_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] pred_rdata_hold_data_3_entry_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_3_entry_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_3_entry_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [3:0] pred_rdata_hold_data_3_entry_pftAddr; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_3_entry_carry; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_3_entry_isCall; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_3_entry_isRet; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_3_entry_isJalr; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_3_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_3_entry_always_taken_0; // utility/src/main/scala/utility/Hold.scala:24:82 + reg pred_rdata_hold_data_3_entry_always_taken_1; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [19:0] pred_rdata_hold_data_3_tag; // utility/src/main/scala/utility/Hold.scala:24:82 + wire pred_rdata_0_entry_valid = + pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_valid + : pred_rdata_hold_data_0_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + wire pred_rdata_1_entry_valid = + pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_valid + : pred_rdata_hold_data_1_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + wire pred_rdata_2_entry_valid = + pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_valid + : pred_rdata_hold_data_2_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + wire pred_rdata_3_entry_valid = + pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_valid + : pred_rdata_hold_data_3_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + reg [19:0] req_tag; // src/main/scala/xiangshan/frontend/FTB.scala:324:28 + reg [8:0] req_idx; // src/main/scala/xiangshan/frontend/FTB.scala:325:28 + reg [19:0] u_req_tag; // src/main/scala/xiangshan/frontend/FTB.scala:327:30 + wire total_hits_0 = + (pred_rdata_REG ? _ftb_io_r_resp_data_0_tag : pred_rdata_hold_data_0_tag) == req_tag + & pred_rdata_0_entry_valid & io_s1_fire; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, :324:28, :332:{70,107}, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + wire total_hits_1 = + (pred_rdata_REG ? _ftb_io_r_resp_data_1_tag : pred_rdata_hold_data_1_tag) == req_tag + & pred_rdata_1_entry_valid & io_s1_fire; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, :324:28, :332:{70,107}, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + wire total_hits_2 = + (pred_rdata_REG ? _ftb_io_r_resp_data_2_tag : pred_rdata_hold_data_2_tag) == req_tag + & pred_rdata_2_entry_valid & io_s1_fire; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, :324:28, :332:{70,107}, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + wire total_hits_3 = + (pred_rdata_REG ? _ftb_io_r_resp_data_3_tag : pred_rdata_hold_data_3_tag) == req_tag + & pred_rdata_3_entry_valid & io_s1_fire; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :315:62, :324:28, :332:{70,107}, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + wire read_way_valid = + total_hits_0 | total_hits_1 | total_hits_2 | total_hits_3; // src/main/scala/xiangshan/frontend/FTB.scala:332:107, :333:34 + wire [1:0] read_way_bits = + {|{total_hits_3, total_hits_2}, total_hits_3 | total_hits_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/FTB.scala:332:107 + reg u_total_hits_REG; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 + reg u_total_hits_REG_1; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 + wire u_total_hits_1 = + _ftb_io_r_resp_data_1_tag == u_req_tag & _ftb_io_r_resp_data_1_entry_valid + & u_total_hits_REG_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :327:30, :338:{35,86,96} + reg u_total_hits_REG_2; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 + wire u_total_hits_2 = + _ftb_io_r_resp_data_2_tag == u_req_tag & _ftb_io_r_resp_data_2_entry_valid + & u_total_hits_REG_2; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :327:30, :338:{35,86,96} + reg u_total_hits_REG_3; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 + wire u_total_hits_3 = + _ftb_io_r_resp_data_3_tag == u_req_tag & _ftb_io_r_resp_data_3_entry_valid + & u_total_hits_REG_3; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :327:30, :338:{35,86,96} + reg [2:0] state_vec_0; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_1; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_2; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_3; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_4; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_5; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_6; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_7; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_8; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_9; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_10; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_11; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_12; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_13; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_14; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_15; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_16; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_17; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_18; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_19; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_20; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_21; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_22; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_23; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_24; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_25; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_26; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_27; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_28; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_29; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_30; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_31; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_32; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_33; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_34; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_35; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_36; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_37; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_38; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_39; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_40; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_41; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_42; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_43; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_44; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_45; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_46; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_47; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_48; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_49; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_50; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_51; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_52; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_53; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_54; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_55; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_56; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_57; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_58; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_59; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_60; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_61; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_62; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_63; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_64; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_65; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_66; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_67; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_68; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_69; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_70; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_71; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_72; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_73; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_74; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_75; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_76; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_77; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_78; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_79; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_80; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_81; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_82; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_83; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_84; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_85; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_86; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_87; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_88; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_89; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_90; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_91; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_92; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_93; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_94; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_95; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_96; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_97; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_98; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_99; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_100; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_101; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_102; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_103; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_104; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_105; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_106; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_107; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_108; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_109; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_110; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_111; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_112; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_113; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_114; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_115; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_116; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_117; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_118; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_119; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_120; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_121; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_122; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_123; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_124; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_125; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_126; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_127; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_128; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_129; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_130; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_131; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_132; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_133; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_134; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_135; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_136; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_137; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_138; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_139; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_140; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_141; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_142; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_143; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_144; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_145; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_146; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_147; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_148; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_149; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_150; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_151; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_152; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_153; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_154; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_155; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_156; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_157; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_158; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_159; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_160; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_161; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_162; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_163; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_164; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_165; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_166; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_167; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_168; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_169; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_170; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_171; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_172; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_173; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_174; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_175; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_176; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_177; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_178; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_179; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_180; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_181; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_182; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_183; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_184; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_185; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_186; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_187; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_188; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_189; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_190; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_191; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_192; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_193; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_194; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_195; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_196; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_197; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_198; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_199; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_200; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_201; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_202; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_203; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_204; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_205; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_206; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_207; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_208; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_209; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_210; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_211; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_212; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_213; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_214; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_215; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_216; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_217; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_218; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_219; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_220; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_221; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_222; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_223; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_224; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_225; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_226; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_227; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_228; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_229; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_230; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_231; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_232; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_233; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_234; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_235; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_236; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_237; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_238; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_239; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_240; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_241; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_242; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_243; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_244; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_245; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_246; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_247; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_248; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_249; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_250; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_251; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_252; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_253; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_254; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_255; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_256; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_257; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_258; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_259; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_260; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_261; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_262; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_263; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_264; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_265; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_266; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_267; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_268; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_269; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_270; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_271; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_272; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_273; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_274; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_275; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_276; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_277; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_278; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_279; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_280; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_281; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_282; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_283; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_284; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_285; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_286; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_287; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_288; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_289; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_290; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_291; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_292; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_293; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_294; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_295; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_296; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_297; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_298; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_299; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_300; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_301; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_302; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_303; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_304; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_305; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_306; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_307; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_308; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_309; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_310; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_311; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_312; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_313; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_314; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_315; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_316; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_317; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_318; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_319; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_320; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_321; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_322; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_323; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_324; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_325; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_326; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_327; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_328; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_329; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_330; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_331; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_332; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_333; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_334; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_335; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_336; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_337; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_338; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_339; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_340; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_341; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_342; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_343; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_344; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_345; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_346; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_347; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_348; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_349; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_350; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_351; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_352; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_353; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_354; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_355; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_356; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_357; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_358; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_359; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_360; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_361; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_362; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_363; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_364; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_365; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_366; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_367; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_368; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_369; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_370; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_371; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_372; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_373; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_374; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_375; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_376; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_377; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_378; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_379; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_380; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_381; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_382; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_383; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_384; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_385; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_386; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_387; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_388; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_389; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_390; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_391; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_392; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_393; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_394; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_395; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_396; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_397; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_398; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_399; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_400; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_401; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_402; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_403; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_404; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_405; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_406; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_407; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_408; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_409; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_410; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_411; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_412; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_413; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_414; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_415; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_416; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_417; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_418; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_419; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_420; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_421; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_422; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_423; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_424; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_425; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_426; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_427; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_428; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_429; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_430; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_431; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_432; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_433; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_434; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_435; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_436; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_437; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_438; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_439; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_440; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_441; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_442; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_443; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_444; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_445; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_446; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_447; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_448; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_449; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_450; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_451; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_452; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_453; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_454; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_455; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_456; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_457; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_458; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_459; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_460; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_461; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_462; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_463; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_464; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_465; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_466; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_467; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_468; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_469; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_470; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_471; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_472; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_473; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_474; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_475; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_476; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_477; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_478; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_479; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_480; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_481; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_482; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_483; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_484; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_485; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_486; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_487; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_488; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_489; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_490; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_491; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_492; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_493; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_494; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_495; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_496; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_497; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_498; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_499; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_500; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_501; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_502; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_503; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_504; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_505; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_506; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_507; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_508; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_509; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_510; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [2:0] state_vec_511; // rocket-chip/src/main/scala/util/Replacement.scala:374:17 + reg [8:0] touch_set_0_REG; // src/main/scala/xiangshan/frontend/FTB.scala:368:60 + reg touch_way_0_valid_REG; // src/main/scala/xiangshan/frontend/FTB.scala:369:53 + reg [1:0] touch_way_0_bits_REG; // src/main/scala/xiangshan/frontend/FTB.scala:370:70 + reg allocWriteWay_REG_0; // src/main/scala/xiangshan/frontend/FTB.scala:401:41 + reg allocWriteWay_REG_1; // src/main/scala/xiangshan/frontend/FTB.scala:401:41 + reg allocWriteWay_REG_2; // src/main/scala/xiangshan/frontend/FTB.scala:401:41 + reg allocWriteWay_REG_3; // src/main/scala/xiangshan/frontend/FTB.scala:401:41 + wire [511:0][2:0] _GEN = + {{state_vec_511}, + {state_vec_510}, + {state_vec_509}, + {state_vec_508}, + {state_vec_507}, + {state_vec_506}, + {state_vec_505}, + {state_vec_504}, + {state_vec_503}, + {state_vec_502}, + {state_vec_501}, + {state_vec_500}, + {state_vec_499}, + {state_vec_498}, + {state_vec_497}, + {state_vec_496}, + {state_vec_495}, + {state_vec_494}, + {state_vec_493}, + {state_vec_492}, + {state_vec_491}, + {state_vec_490}, + {state_vec_489}, + {state_vec_488}, + {state_vec_487}, + {state_vec_486}, + {state_vec_485}, + {state_vec_484}, + {state_vec_483}, + {state_vec_482}, + {state_vec_481}, + {state_vec_480}, + {state_vec_479}, + {state_vec_478}, + {state_vec_477}, + {state_vec_476}, + {state_vec_475}, + {state_vec_474}, + {state_vec_473}, + {state_vec_472}, + {state_vec_471}, + {state_vec_470}, + {state_vec_469}, + {state_vec_468}, + {state_vec_467}, + {state_vec_466}, + {state_vec_465}, + {state_vec_464}, + {state_vec_463}, + {state_vec_462}, + {state_vec_461}, + {state_vec_460}, + {state_vec_459}, + {state_vec_458}, + {state_vec_457}, + {state_vec_456}, + {state_vec_455}, + {state_vec_454}, + {state_vec_453}, + {state_vec_452}, + {state_vec_451}, + {state_vec_450}, + {state_vec_449}, + {state_vec_448}, + {state_vec_447}, + {state_vec_446}, + {state_vec_445}, + {state_vec_444}, + {state_vec_443}, + {state_vec_442}, + {state_vec_441}, + {state_vec_440}, + {state_vec_439}, + {state_vec_438}, + {state_vec_437}, + {state_vec_436}, + {state_vec_435}, + {state_vec_434}, + {state_vec_433}, + {state_vec_432}, + {state_vec_431}, + {state_vec_430}, + {state_vec_429}, + {state_vec_428}, + {state_vec_427}, + {state_vec_426}, + {state_vec_425}, + {state_vec_424}, + {state_vec_423}, + {state_vec_422}, + {state_vec_421}, + {state_vec_420}, + {state_vec_419}, + {state_vec_418}, + {state_vec_417}, + {state_vec_416}, + {state_vec_415}, + {state_vec_414}, + {state_vec_413}, + {state_vec_412}, + {state_vec_411}, + {state_vec_410}, + {state_vec_409}, + {state_vec_408}, + {state_vec_407}, + {state_vec_406}, + {state_vec_405}, + {state_vec_404}, + {state_vec_403}, + {state_vec_402}, + {state_vec_401}, + {state_vec_400}, + {state_vec_399}, + {state_vec_398}, + {state_vec_397}, + {state_vec_396}, + {state_vec_395}, + {state_vec_394}, + {state_vec_393}, + {state_vec_392}, + {state_vec_391}, + {state_vec_390}, + {state_vec_389}, + {state_vec_388}, + {state_vec_387}, + {state_vec_386}, + {state_vec_385}, + {state_vec_384}, + {state_vec_383}, + {state_vec_382}, + {state_vec_381}, + {state_vec_380}, + {state_vec_379}, + {state_vec_378}, + {state_vec_377}, + {state_vec_376}, + {state_vec_375}, + {state_vec_374}, + {state_vec_373}, + {state_vec_372}, + {state_vec_371}, + {state_vec_370}, + {state_vec_369}, + {state_vec_368}, + {state_vec_367}, + {state_vec_366}, + {state_vec_365}, + {state_vec_364}, + {state_vec_363}, + {state_vec_362}, + {state_vec_361}, + {state_vec_360}, + {state_vec_359}, + {state_vec_358}, + {state_vec_357}, + {state_vec_356}, + {state_vec_355}, + {state_vec_354}, + {state_vec_353}, + {state_vec_352}, + {state_vec_351}, + {state_vec_350}, + {state_vec_349}, + {state_vec_348}, + {state_vec_347}, + {state_vec_346}, + {state_vec_345}, + {state_vec_344}, + {state_vec_343}, + {state_vec_342}, + {state_vec_341}, + {state_vec_340}, + {state_vec_339}, + {state_vec_338}, + {state_vec_337}, + {state_vec_336}, + {state_vec_335}, + {state_vec_334}, + {state_vec_333}, + {state_vec_332}, + {state_vec_331}, + {state_vec_330}, + {state_vec_329}, + {state_vec_328}, + {state_vec_327}, + {state_vec_326}, + {state_vec_325}, + {state_vec_324}, + {state_vec_323}, + {state_vec_322}, + {state_vec_321}, + {state_vec_320}, + {state_vec_319}, + {state_vec_318}, + {state_vec_317}, + {state_vec_316}, + {state_vec_315}, + {state_vec_314}, + {state_vec_313}, + {state_vec_312}, + {state_vec_311}, + {state_vec_310}, + {state_vec_309}, + {state_vec_308}, + {state_vec_307}, + {state_vec_306}, + {state_vec_305}, + {state_vec_304}, + {state_vec_303}, + {state_vec_302}, + {state_vec_301}, + {state_vec_300}, + {state_vec_299}, + {state_vec_298}, + {state_vec_297}, + {state_vec_296}, + {state_vec_295}, + {state_vec_294}, + {state_vec_293}, + {state_vec_292}, + {state_vec_291}, + {state_vec_290}, + {state_vec_289}, + {state_vec_288}, + {state_vec_287}, + {state_vec_286}, + {state_vec_285}, + {state_vec_284}, + {state_vec_283}, + {state_vec_282}, + {state_vec_281}, + {state_vec_280}, + {state_vec_279}, + {state_vec_278}, + {state_vec_277}, + {state_vec_276}, + {state_vec_275}, + {state_vec_274}, + {state_vec_273}, + {state_vec_272}, + {state_vec_271}, + {state_vec_270}, + {state_vec_269}, + {state_vec_268}, + {state_vec_267}, + {state_vec_266}, + {state_vec_265}, + {state_vec_264}, + {state_vec_263}, + {state_vec_262}, + {state_vec_261}, + {state_vec_260}, + {state_vec_259}, + {state_vec_258}, + {state_vec_257}, + {state_vec_256}, + {state_vec_255}, + {state_vec_254}, + {state_vec_253}, + {state_vec_252}, + {state_vec_251}, + {state_vec_250}, + {state_vec_249}, + {state_vec_248}, + {state_vec_247}, + {state_vec_246}, + {state_vec_245}, + {state_vec_244}, + {state_vec_243}, + {state_vec_242}, + {state_vec_241}, + {state_vec_240}, + {state_vec_239}, + {state_vec_238}, + {state_vec_237}, + {state_vec_236}, + {state_vec_235}, + {state_vec_234}, + {state_vec_233}, + {state_vec_232}, + {state_vec_231}, + {state_vec_230}, + {state_vec_229}, + {state_vec_228}, + {state_vec_227}, + {state_vec_226}, + {state_vec_225}, + {state_vec_224}, + {state_vec_223}, + {state_vec_222}, + {state_vec_221}, + {state_vec_220}, + {state_vec_219}, + {state_vec_218}, + {state_vec_217}, + {state_vec_216}, + {state_vec_215}, + {state_vec_214}, + {state_vec_213}, + {state_vec_212}, + {state_vec_211}, + {state_vec_210}, + {state_vec_209}, + {state_vec_208}, + {state_vec_207}, + {state_vec_206}, + {state_vec_205}, + {state_vec_204}, + {state_vec_203}, + {state_vec_202}, + {state_vec_201}, + {state_vec_200}, + {state_vec_199}, + {state_vec_198}, + {state_vec_197}, + {state_vec_196}, + {state_vec_195}, + {state_vec_194}, + {state_vec_193}, + {state_vec_192}, + {state_vec_191}, + {state_vec_190}, + {state_vec_189}, + {state_vec_188}, + {state_vec_187}, + {state_vec_186}, + {state_vec_185}, + {state_vec_184}, + {state_vec_183}, + {state_vec_182}, + {state_vec_181}, + {state_vec_180}, + {state_vec_179}, + {state_vec_178}, + {state_vec_177}, + {state_vec_176}, + {state_vec_175}, + {state_vec_174}, + {state_vec_173}, + {state_vec_172}, + {state_vec_171}, + {state_vec_170}, + {state_vec_169}, + {state_vec_168}, + {state_vec_167}, + {state_vec_166}, + {state_vec_165}, + {state_vec_164}, + {state_vec_163}, + {state_vec_162}, + {state_vec_161}, + {state_vec_160}, + {state_vec_159}, + {state_vec_158}, + {state_vec_157}, + {state_vec_156}, + {state_vec_155}, + {state_vec_154}, + {state_vec_153}, + {state_vec_152}, + {state_vec_151}, + {state_vec_150}, + {state_vec_149}, + {state_vec_148}, + {state_vec_147}, + {state_vec_146}, + {state_vec_145}, + {state_vec_144}, + {state_vec_143}, + {state_vec_142}, + {state_vec_141}, + {state_vec_140}, + {state_vec_139}, + {state_vec_138}, + {state_vec_137}, + {state_vec_136}, + {state_vec_135}, + {state_vec_134}, + {state_vec_133}, + {state_vec_132}, + {state_vec_131}, + {state_vec_130}, + {state_vec_129}, + {state_vec_128}, + {state_vec_127}, + {state_vec_126}, + {state_vec_125}, + {state_vec_124}, + {state_vec_123}, + {state_vec_122}, + {state_vec_121}, + {state_vec_120}, + {state_vec_119}, + {state_vec_118}, + {state_vec_117}, + {state_vec_116}, + {state_vec_115}, + {state_vec_114}, + {state_vec_113}, + {state_vec_112}, + {state_vec_111}, + {state_vec_110}, + {state_vec_109}, + {state_vec_108}, + {state_vec_107}, + {state_vec_106}, + {state_vec_105}, + {state_vec_104}, + {state_vec_103}, + {state_vec_102}, + {state_vec_101}, + {state_vec_100}, + {state_vec_99}, + {state_vec_98}, + {state_vec_97}, + {state_vec_96}, + {state_vec_95}, + {state_vec_94}, + {state_vec_93}, + {state_vec_92}, + {state_vec_91}, + {state_vec_90}, + {state_vec_89}, + {state_vec_88}, + {state_vec_87}, + {state_vec_86}, + {state_vec_85}, + {state_vec_84}, + {state_vec_83}, + {state_vec_82}, + {state_vec_81}, + {state_vec_80}, + {state_vec_79}, + {state_vec_78}, + {state_vec_77}, + {state_vec_76}, + {state_vec_75}, + {state_vec_74}, + {state_vec_73}, + {state_vec_72}, + {state_vec_71}, + {state_vec_70}, + {state_vec_69}, + {state_vec_68}, + {state_vec_67}, + {state_vec_66}, + {state_vec_65}, + {state_vec_64}, + {state_vec_63}, + {state_vec_62}, + {state_vec_61}, + {state_vec_60}, + {state_vec_59}, + {state_vec_58}, + {state_vec_57}, + {state_vec_56}, + {state_vec_55}, + {state_vec_54}, + {state_vec_53}, + {state_vec_52}, + {state_vec_51}, + {state_vec_50}, + {state_vec_49}, + {state_vec_48}, + {state_vec_47}, + {state_vec_46}, + {state_vec_45}, + {state_vec_44}, + {state_vec_43}, + {state_vec_42}, + {state_vec_41}, + {state_vec_40}, + {state_vec_39}, + {state_vec_38}, + {state_vec_37}, + {state_vec_36}, + {state_vec_35}, + {state_vec_34}, + {state_vec_33}, + {state_vec_32}, + {state_vec_31}, + {state_vec_30}, + {state_vec_29}, + {state_vec_28}, + {state_vec_27}, + {state_vec_26}, + {state_vec_25}, + {state_vec_24}, + {state_vec_23}, + {state_vec_22}, + {state_vec_21}, + {state_vec_20}, + {state_vec_19}, + {state_vec_18}, + {state_vec_17}, + {state_vec_16}, + {state_vec_15}, + {state_vec_14}, + {state_vec_13}, + {state_vec_12}, + {state_vec_11}, + {state_vec_10}, + {state_vec_9}, + {state_vec_8}, + {state_vec_7}, + {state_vec_6}, + {state_vec_5}, + {state_vec_4}, + {state_vec_3}, + {state_vec_2}, + {state_vec_1}, + {state_vec_0}}; // rocket-chip/src/main/scala/util/Replacement.scala:243:38, :374:17 + wire [2:0] _GEN_0 = _GEN[io_update_pc[9:1]]; // rocket-chip/src/main/scala/util/Replacement.scala:243:38, src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 + wire [2:0] _allocWriteWay_w_T_4 = + ~{allocWriteWay_REG_2, allocWriteWay_REG_1, allocWriteWay_REG_0}; // src/main/scala/xiangshan/frontend/FTB.scala:382:60, :401:{41,79} + wire [1:0] write_way_bits = + io_update_write_alloc + ? ((&{allocWriteWay_REG_3, + allocWriteWay_REG_2, + allocWriteWay_REG_1, + allocWriteWay_REG_0}) + ? {_GEN_0[2], _GEN_0[2] ? _GEN_0[1] : _GEN_0[0]} + : _allocWriteWay_w_T_4[0] + ? 2'h0 + : _allocWriteWay_w_T_4[1] ? 2'h1 : {1'h1, ~(_allocWriteWay_w_T_4[2])}) + : io_update_write_way; // rocket-chip/src/main/scala/util/Replacement.scala:243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/chisel3/util/Mux.scala:30:73, :50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/FTB.scala:346:71, :381:37, :382:{17,60}, :401:{41,79}, :402:20 + always @(posedge clock) begin + pred_rdata_REG <= io_req_pc_valid & ~io_update_access; // src/main/scala/xiangshan/frontend/FTB.scala:315:{62,79,82} + if (pred_rdata_REG) begin // src/main/scala/xiangshan/frontend/FTB.scala:315:62 + pred_rdata_hold_data_0_entry_valid <= _ftb_io_r_resp_data_0_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_brSlots_0_offset <= + _ftb_io_r_resp_data_0_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_brSlots_0_lower <= + _ftb_io_r_resp_data_0_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_brSlots_0_tarStat <= + _ftb_io_r_resp_data_0_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_brSlots_0_sharing <= + _ftb_io_r_resp_data_0_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_brSlots_0_valid <= + _ftb_io_r_resp_data_0_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_tailSlot_offset <= + _ftb_io_r_resp_data_0_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_tailSlot_lower <= + _ftb_io_r_resp_data_0_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_tailSlot_tarStat <= + _ftb_io_r_resp_data_0_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_tailSlot_sharing <= + _ftb_io_r_resp_data_0_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_tailSlot_valid <= + _ftb_io_r_resp_data_0_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_pftAddr <= _ftb_io_r_resp_data_0_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_carry <= _ftb_io_r_resp_data_0_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_isCall <= _ftb_io_r_resp_data_0_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_isRet <= _ftb_io_r_resp_data_0_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_isJalr <= _ftb_io_r_resp_data_0_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_last_may_be_rvi_call <= + _ftb_io_r_resp_data_0_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_always_taken_0 <= + _ftb_io_r_resp_data_0_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_always_taken_1 <= + _ftb_io_r_resp_data_0_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_tag <= _ftb_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_valid <= _ftb_io_r_resp_data_1_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_brSlots_0_offset <= + _ftb_io_r_resp_data_1_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_brSlots_0_lower <= + _ftb_io_r_resp_data_1_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_brSlots_0_tarStat <= + _ftb_io_r_resp_data_1_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_brSlots_0_sharing <= + _ftb_io_r_resp_data_1_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_brSlots_0_valid <= + _ftb_io_r_resp_data_1_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_tailSlot_offset <= + _ftb_io_r_resp_data_1_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_tailSlot_lower <= + _ftb_io_r_resp_data_1_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_tailSlot_tarStat <= + _ftb_io_r_resp_data_1_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_tailSlot_sharing <= + _ftb_io_r_resp_data_1_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_tailSlot_valid <= + _ftb_io_r_resp_data_1_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_pftAddr <= _ftb_io_r_resp_data_1_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_carry <= _ftb_io_r_resp_data_1_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_isCall <= _ftb_io_r_resp_data_1_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_isRet <= _ftb_io_r_resp_data_1_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_isJalr <= _ftb_io_r_resp_data_1_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_last_may_be_rvi_call <= + _ftb_io_r_resp_data_1_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_always_taken_0 <= + _ftb_io_r_resp_data_1_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_always_taken_1 <= + _ftb_io_r_resp_data_1_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_tag <= _ftb_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_valid <= _ftb_io_r_resp_data_2_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_brSlots_0_offset <= + _ftb_io_r_resp_data_2_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_brSlots_0_lower <= + _ftb_io_r_resp_data_2_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_brSlots_0_tarStat <= + _ftb_io_r_resp_data_2_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_brSlots_0_sharing <= + _ftb_io_r_resp_data_2_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_brSlots_0_valid <= + _ftb_io_r_resp_data_2_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_tailSlot_offset <= + _ftb_io_r_resp_data_2_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_tailSlot_lower <= + _ftb_io_r_resp_data_2_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_tailSlot_tarStat <= + _ftb_io_r_resp_data_2_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_tailSlot_sharing <= + _ftb_io_r_resp_data_2_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_tailSlot_valid <= + _ftb_io_r_resp_data_2_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_pftAddr <= _ftb_io_r_resp_data_2_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_carry <= _ftb_io_r_resp_data_2_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_isCall <= _ftb_io_r_resp_data_2_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_isRet <= _ftb_io_r_resp_data_2_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_isJalr <= _ftb_io_r_resp_data_2_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_last_may_be_rvi_call <= + _ftb_io_r_resp_data_2_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_always_taken_0 <= + _ftb_io_r_resp_data_2_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_always_taken_1 <= + _ftb_io_r_resp_data_2_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_tag <= _ftb_io_r_resp_data_2_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_valid <= _ftb_io_r_resp_data_3_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_brSlots_0_offset <= + _ftb_io_r_resp_data_3_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_brSlots_0_lower <= + _ftb_io_r_resp_data_3_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_brSlots_0_tarStat <= + _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_brSlots_0_sharing <= + _ftb_io_r_resp_data_3_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_brSlots_0_valid <= + _ftb_io_r_resp_data_3_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_tailSlot_offset <= + _ftb_io_r_resp_data_3_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_tailSlot_lower <= + _ftb_io_r_resp_data_3_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_tailSlot_tarStat <= + _ftb_io_r_resp_data_3_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_tailSlot_sharing <= + _ftb_io_r_resp_data_3_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_tailSlot_valid <= + _ftb_io_r_resp_data_3_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_pftAddr <= _ftb_io_r_resp_data_3_entry_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_carry <= _ftb_io_r_resp_data_3_entry_carry; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_isCall <= _ftb_io_r_resp_data_3_entry_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_isRet <= _ftb_io_r_resp_data_3_entry_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_isJalr <= _ftb_io_r_resp_data_3_entry_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_last_may_be_rvi_call <= + _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_always_taken_0 <= + _ftb_io_r_resp_data_3_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_always_taken_1 <= + _ftb_io_r_resp_data_3_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_tag <= _ftb_io_r_resp_data_3_tag; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, utility/src/main/scala/utility/Hold.scala:24:82 + end + if (io_req_pc_valid) begin // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + req_tag <= io_req_pc_bits[29:10]; // src/main/scala/xiangshan/frontend/FTB.scala:324:{28,59} + req_idx <= io_req_pc_bits[9:1]; // src/main/scala/xiangshan/frontend/FTB.scala:325:28, src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 + end + if (io_u_req_pc_valid) // src/main/scala/xiangshan/frontend/FTB.scala:291:16 + u_req_tag <= io_u_req_pc_bits[29:10]; // src/main/scala/xiangshan/frontend/FTB.scala:327:{30,63} + u_total_hits_REG <= io_update_access; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 + u_total_hits_REG_1 <= io_update_access; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 + u_total_hits_REG_2 <= io_update_access; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 + u_total_hits_REG_3 <= io_update_access; // src/main/scala/xiangshan/frontend/FTB.scala:338:96 + touch_set_0_REG <= req_idx; // src/main/scala/xiangshan/frontend/FTB.scala:325:28, :368:60 + touch_way_0_valid_REG <= read_way_valid; // src/main/scala/xiangshan/frontend/FTB.scala:333:34, :369:53 + touch_way_0_bits_REG <= read_way_bits; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/FTB.scala:370:70 + allocWriteWay_REG_0 <= _ftb_io_r_resp_data_0_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :401:41 + allocWriteWay_REG_1 <= _ftb_io_r_resp_data_1_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :401:41 + allocWriteWay_REG_2 <= _ftb_io_r_resp_data_2_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :401:41 + allocWriteWay_REG_3 <= _ftb_io_r_resp_data_3_entry_valid; // src/main/scala/xiangshan/frontend/FTB.scala:312:21, :401:41 + end // always @(posedge) + wire [8:0] touch_set_0 = + io_update_write_data_valid ? io_update_pc[9:1] : touch_set_0_REG; // src/main/scala/xiangshan/frontend/FTB.scala:368:{24,60}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 + wire touch_way_0_valid = + io_update_write_data_valid | touch_way_0_valid_REG; // src/main/scala/xiangshan/frontend/FTB.scala:369:{43,53} + wire [1:0] set_touch_ways_0_511_bits = + io_update_write_data_valid ? write_way_bits : touch_way_0_bits_REG; // src/main/scala/xiangshan/frontend/FTB.scala:370:{29,70}, :402:20 + always @(posedge clock or posedge reset) begin + if (reset) begin + state_vec_0 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_1 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_2 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_3 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_4 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_5 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_6 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_7 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_8 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_9 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_10 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_11 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_12 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_13 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_14 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_15 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_16 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_17 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_18 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_19 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_20 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_21 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_22 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_23 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_24 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_25 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_26 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_27 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_28 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_29 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_30 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_31 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_32 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_33 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_34 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_35 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_36 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_37 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_38 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_39 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_40 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_41 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_42 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_43 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_44 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_45 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_46 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_47 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_48 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_49 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_50 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_51 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_52 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_53 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_54 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_55 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_56 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_57 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_58 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_59 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_60 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_61 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_62 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_63 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_64 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_65 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_66 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_67 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_68 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_69 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_70 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_71 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_72 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_73 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_74 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_75 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_76 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_77 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_78 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_79 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_80 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_81 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_82 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_83 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_84 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_85 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_86 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_87 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_88 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_89 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_90 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_91 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_92 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_93 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_94 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_95 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_96 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_97 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_98 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_99 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_100 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_101 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_102 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_103 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_104 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_105 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_106 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_107 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_108 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_109 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_110 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_111 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_112 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_113 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_114 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_115 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_116 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_117 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_118 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_119 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_120 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_121 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_122 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_123 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_124 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_125 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_126 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_127 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_128 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_129 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_130 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_131 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_132 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_133 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_134 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_135 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_136 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_137 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_138 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_139 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_140 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_141 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_142 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_143 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_144 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_145 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_146 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_147 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_148 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_149 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_150 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_151 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_152 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_153 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_154 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_155 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_156 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_157 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_158 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_159 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_160 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_161 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_162 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_163 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_164 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_165 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_166 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_167 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_168 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_169 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_170 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_171 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_172 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_173 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_174 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_175 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_176 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_177 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_178 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_179 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_180 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_181 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_182 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_183 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_184 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_185 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_186 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_187 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_188 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_189 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_190 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_191 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_192 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_193 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_194 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_195 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_196 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_197 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_198 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_199 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_200 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_201 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_202 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_203 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_204 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_205 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_206 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_207 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_208 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_209 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_210 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_211 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_212 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_213 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_214 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_215 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_216 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_217 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_218 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_219 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_220 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_221 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_222 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_223 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_224 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_225 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_226 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_227 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_228 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_229 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_230 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_231 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_232 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_233 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_234 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_235 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_236 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_237 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_238 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_239 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_240 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_241 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_242 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_243 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_244 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_245 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_246 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_247 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_248 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_249 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_250 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_251 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_252 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_253 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_254 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_255 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_256 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_257 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_258 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_259 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_260 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_261 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_262 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_263 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_264 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_265 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_266 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_267 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_268 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_269 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_270 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_271 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_272 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_273 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_274 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_275 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_276 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_277 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_278 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_279 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_280 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_281 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_282 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_283 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_284 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_285 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_286 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_287 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_288 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_289 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_290 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_291 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_292 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_293 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_294 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_295 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_296 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_297 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_298 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_299 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_300 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_301 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_302 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_303 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_304 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_305 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_306 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_307 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_308 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_309 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_310 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_311 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_312 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_313 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_314 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_315 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_316 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_317 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_318 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_319 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_320 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_321 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_322 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_323 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_324 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_325 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_326 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_327 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_328 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_329 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_330 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_331 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_332 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_333 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_334 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_335 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_336 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_337 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_338 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_339 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_340 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_341 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_342 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_343 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_344 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_345 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_346 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_347 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_348 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_349 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_350 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_351 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_352 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_353 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_354 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_355 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_356 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_357 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_358 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_359 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_360 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_361 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_362 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_363 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_364 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_365 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_366 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_367 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_368 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_369 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_370 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_371 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_372 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_373 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_374 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_375 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_376 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_377 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_378 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_379 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_380 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_381 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_382 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_383 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_384 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_385 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_386 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_387 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_388 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_389 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_390 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_391 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_392 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_393 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_394 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_395 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_396 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_397 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_398 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_399 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_400 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_401 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_402 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_403 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_404 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_405 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_406 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_407 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_408 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_409 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_410 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_411 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_412 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_413 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_414 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_415 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_416 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_417 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_418 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_419 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_420 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_421 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_422 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_423 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_424 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_425 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_426 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_427 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_428 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_429 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_430 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_431 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_432 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_433 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_434 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_435 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_436 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_437 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_438 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_439 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_440 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_441 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_442 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_443 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_444 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_445 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_446 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_447 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_448 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_449 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_450 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_451 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_452 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_453 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_454 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_455 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_456 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_457 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_458 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_459 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_460 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_461 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_462 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_463 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_464 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_465 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_466 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_467 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_468 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_469 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_470 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_471 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_472 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_473 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_474 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_475 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_476 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_477 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_478 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_479 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_480 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_481 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_482 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_483 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_484 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_485 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_486 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_487 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_488 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_489 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_490 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_491 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_492 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_493 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_494 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_495 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_496 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_497 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_498 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_499 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_500 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_501 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_502 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_503 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_504 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_505 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_506 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_507 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_508 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_509 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_510 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_511 <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + end + else begin + if (touch_way_0_valid & touch_set_0 == 9'h0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_0 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_0[1], + set_touch_ways_0_511_bits[1] + ? state_vec_0[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_1 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_1[1], + set_touch_ways_0_511_bits[1] + ? state_vec_1[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_2 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_2[1], + set_touch_ways_0_511_bits[1] + ? state_vec_2[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_3 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_3[1], + set_touch_ways_0_511_bits[1] + ? state_vec_3[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_4 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_4[1], + set_touch_ways_0_511_bits[1] + ? state_vec_4[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_5 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_5[1], + set_touch_ways_0_511_bits[1] + ? state_vec_5[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_6 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_6[1], + set_touch_ways_0_511_bits[1] + ? state_vec_6[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_7 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_7[1], + set_touch_ways_0_511_bits[1] + ? state_vec_7[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_8 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_8[1], + set_touch_ways_0_511_bits[1] + ? state_vec_8[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_9 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_9[1], + set_touch_ways_0_511_bits[1] + ? state_vec_9[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_10 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_10[1], + set_touch_ways_0_511_bits[1] + ? state_vec_10[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_11 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_11[1], + set_touch_ways_0_511_bits[1] + ? state_vec_11[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_12 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_12[1], + set_touch_ways_0_511_bits[1] + ? state_vec_12[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_13 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_13[1], + set_touch_ways_0_511_bits[1] + ? state_vec_13[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_14 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_14[1], + set_touch_ways_0_511_bits[1] + ? state_vec_14[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_15 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_15[1], + set_touch_ways_0_511_bits[1] + ? state_vec_15[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h10) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_16 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_16[1], + set_touch_ways_0_511_bits[1] + ? state_vec_16[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h11) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_17 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_17[1], + set_touch_ways_0_511_bits[1] + ? state_vec_17[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h12) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_18 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_18[1], + set_touch_ways_0_511_bits[1] + ? state_vec_18[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h13) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_19 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_19[1], + set_touch_ways_0_511_bits[1] + ? state_vec_19[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h14) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_20 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_20[1], + set_touch_ways_0_511_bits[1] + ? state_vec_20[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h15) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_21 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_21[1], + set_touch_ways_0_511_bits[1] + ? state_vec_21[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h16) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_22 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_22[1], + set_touch_ways_0_511_bits[1] + ? state_vec_22[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h17) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_23 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_23[1], + set_touch_ways_0_511_bits[1] + ? state_vec_23[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h18) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_24 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_24[1], + set_touch_ways_0_511_bits[1] + ? state_vec_24[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h19) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_25 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_25[1], + set_touch_ways_0_511_bits[1] + ? state_vec_25[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_26 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_26[1], + set_touch_ways_0_511_bits[1] + ? state_vec_26[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_27 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_27[1], + set_touch_ways_0_511_bits[1] + ? state_vec_27[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_28 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_28[1], + set_touch_ways_0_511_bits[1] + ? state_vec_28[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_29 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_29[1], + set_touch_ways_0_511_bits[1] + ? state_vec_29[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_30 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_30[1], + set_touch_ways_0_511_bits[1] + ? state_vec_30[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_31 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_31[1], + set_touch_ways_0_511_bits[1] + ? state_vec_31[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h20) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_32 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_32[1], + set_touch_ways_0_511_bits[1] + ? state_vec_32[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h21) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_33 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_33[1], + set_touch_ways_0_511_bits[1] + ? state_vec_33[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h22) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_34 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_34[1], + set_touch_ways_0_511_bits[1] + ? state_vec_34[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h23) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_35 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_35[1], + set_touch_ways_0_511_bits[1] + ? state_vec_35[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h24) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_36 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_36[1], + set_touch_ways_0_511_bits[1] + ? state_vec_36[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h25) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_37 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_37[1], + set_touch_ways_0_511_bits[1] + ? state_vec_37[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h26) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_38 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_38[1], + set_touch_ways_0_511_bits[1] + ? state_vec_38[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h27) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_39 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_39[1], + set_touch_ways_0_511_bits[1] + ? state_vec_39[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h28) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_40 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_40[1], + set_touch_ways_0_511_bits[1] + ? state_vec_40[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h29) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_41 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_41[1], + set_touch_ways_0_511_bits[1] + ? state_vec_41[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h2A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_42 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_42[1], + set_touch_ways_0_511_bits[1] + ? state_vec_42[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h2B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_43 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_43[1], + set_touch_ways_0_511_bits[1] + ? state_vec_43[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h2C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_44 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_44[1], + set_touch_ways_0_511_bits[1] + ? state_vec_44[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h2D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_45 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_45[1], + set_touch_ways_0_511_bits[1] + ? state_vec_45[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h2E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_46 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_46[1], + set_touch_ways_0_511_bits[1] + ? state_vec_46[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h2F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_47 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_47[1], + set_touch_ways_0_511_bits[1] + ? state_vec_47[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h30) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_48 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_48[1], + set_touch_ways_0_511_bits[1] + ? state_vec_48[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h31) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_49 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_49[1], + set_touch_ways_0_511_bits[1] + ? state_vec_49[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h32) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_50 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_50[1], + set_touch_ways_0_511_bits[1] + ? state_vec_50[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h33) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_51 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_51[1], + set_touch_ways_0_511_bits[1] + ? state_vec_51[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h34) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_52 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_52[1], + set_touch_ways_0_511_bits[1] + ? state_vec_52[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h35) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_53 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_53[1], + set_touch_ways_0_511_bits[1] + ? state_vec_53[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h36) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_54 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_54[1], + set_touch_ways_0_511_bits[1] + ? state_vec_54[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h37) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_55 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_55[1], + set_touch_ways_0_511_bits[1] + ? state_vec_55[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h38) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_56 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_56[1], + set_touch_ways_0_511_bits[1] + ? state_vec_56[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h39) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_57 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_57[1], + set_touch_ways_0_511_bits[1] + ? state_vec_57[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h3A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_58 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_58[1], + set_touch_ways_0_511_bits[1] + ? state_vec_58[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h3B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_59 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_59[1], + set_touch_ways_0_511_bits[1] + ? state_vec_59[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h3C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_60 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_60[1], + set_touch_ways_0_511_bits[1] + ? state_vec_60[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h3D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_61 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_61[1], + set_touch_ways_0_511_bits[1] + ? state_vec_61[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h3E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_62 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_62[1], + set_touch_ways_0_511_bits[1] + ? state_vec_62[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h3F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_63 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_63[1], + set_touch_ways_0_511_bits[1] + ? state_vec_63[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h40) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_64 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_64[1], + set_touch_ways_0_511_bits[1] + ? state_vec_64[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h41) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_65 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_65[1], + set_touch_ways_0_511_bits[1] + ? state_vec_65[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h42) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_66 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_66[1], + set_touch_ways_0_511_bits[1] + ? state_vec_66[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h43) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_67 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_67[1], + set_touch_ways_0_511_bits[1] + ? state_vec_67[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h44) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_68 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_68[1], + set_touch_ways_0_511_bits[1] + ? state_vec_68[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h45) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_69 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_69[1], + set_touch_ways_0_511_bits[1] + ? state_vec_69[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h46) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_70 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_70[1], + set_touch_ways_0_511_bits[1] + ? state_vec_70[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h47) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_71 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_71[1], + set_touch_ways_0_511_bits[1] + ? state_vec_71[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h48) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_72 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_72[1], + set_touch_ways_0_511_bits[1] + ? state_vec_72[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h49) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_73 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_73[1], + set_touch_ways_0_511_bits[1] + ? state_vec_73[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h4A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_74 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_74[1], + set_touch_ways_0_511_bits[1] + ? state_vec_74[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h4B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_75 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_75[1], + set_touch_ways_0_511_bits[1] + ? state_vec_75[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h4C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_76 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_76[1], + set_touch_ways_0_511_bits[1] + ? state_vec_76[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h4D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_77 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_77[1], + set_touch_ways_0_511_bits[1] + ? state_vec_77[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h4E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_78 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_78[1], + set_touch_ways_0_511_bits[1] + ? state_vec_78[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h4F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_79 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_79[1], + set_touch_ways_0_511_bits[1] + ? state_vec_79[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h50) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_80 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_80[1], + set_touch_ways_0_511_bits[1] + ? state_vec_80[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h51) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_81 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_81[1], + set_touch_ways_0_511_bits[1] + ? state_vec_81[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h52) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_82 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_82[1], + set_touch_ways_0_511_bits[1] + ? state_vec_82[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h53) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_83 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_83[1], + set_touch_ways_0_511_bits[1] + ? state_vec_83[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h54) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_84 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_84[1], + set_touch_ways_0_511_bits[1] + ? state_vec_84[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h55) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_85 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_85[1], + set_touch_ways_0_511_bits[1] + ? state_vec_85[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h56) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_86 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_86[1], + set_touch_ways_0_511_bits[1] + ? state_vec_86[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h57) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_87 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_87[1], + set_touch_ways_0_511_bits[1] + ? state_vec_87[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h58) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_88 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_88[1], + set_touch_ways_0_511_bits[1] + ? state_vec_88[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h59) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_89 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_89[1], + set_touch_ways_0_511_bits[1] + ? state_vec_89[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h5A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_90 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_90[1], + set_touch_ways_0_511_bits[1] + ? state_vec_90[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h5B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_91 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_91[1], + set_touch_ways_0_511_bits[1] + ? state_vec_91[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h5C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_92 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_92[1], + set_touch_ways_0_511_bits[1] + ? state_vec_92[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h5D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_93 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_93[1], + set_touch_ways_0_511_bits[1] + ? state_vec_93[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h5E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_94 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_94[1], + set_touch_ways_0_511_bits[1] + ? state_vec_94[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h5F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_95 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_95[1], + set_touch_ways_0_511_bits[1] + ? state_vec_95[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h60) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_96 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_96[1], + set_touch_ways_0_511_bits[1] + ? state_vec_96[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h61) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_97 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_97[1], + set_touch_ways_0_511_bits[1] + ? state_vec_97[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h62) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_98 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_98[1], + set_touch_ways_0_511_bits[1] + ? state_vec_98[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h63) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_99 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_99[1], + set_touch_ways_0_511_bits[1] + ? state_vec_99[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h64) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_100 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_100[1], + set_touch_ways_0_511_bits[1] + ? state_vec_100[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h65) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_101 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_101[1], + set_touch_ways_0_511_bits[1] + ? state_vec_101[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h66) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_102 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_102[1], + set_touch_ways_0_511_bits[1] + ? state_vec_102[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h67) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_103 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_103[1], + set_touch_ways_0_511_bits[1] + ? state_vec_103[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h68) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_104 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_104[1], + set_touch_ways_0_511_bits[1] + ? state_vec_104[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h69) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_105 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_105[1], + set_touch_ways_0_511_bits[1] + ? state_vec_105[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h6A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_106 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_106[1], + set_touch_ways_0_511_bits[1] + ? state_vec_106[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h6B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_107 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_107[1], + set_touch_ways_0_511_bits[1] + ? state_vec_107[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h6C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_108 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_108[1], + set_touch_ways_0_511_bits[1] + ? state_vec_108[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h6D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_109 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_109[1], + set_touch_ways_0_511_bits[1] + ? state_vec_109[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h6E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_110 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_110[1], + set_touch_ways_0_511_bits[1] + ? state_vec_110[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h6F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_111 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_111[1], + set_touch_ways_0_511_bits[1] + ? state_vec_111[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h70) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_112 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_112[1], + set_touch_ways_0_511_bits[1] + ? state_vec_112[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h71) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_113 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_113[1], + set_touch_ways_0_511_bits[1] + ? state_vec_113[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h72) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_114 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_114[1], + set_touch_ways_0_511_bits[1] + ? state_vec_114[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h73) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_115 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_115[1], + set_touch_ways_0_511_bits[1] + ? state_vec_115[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h74) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_116 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_116[1], + set_touch_ways_0_511_bits[1] + ? state_vec_116[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h75) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_117 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_117[1], + set_touch_ways_0_511_bits[1] + ? state_vec_117[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h76) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_118 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_118[1], + set_touch_ways_0_511_bits[1] + ? state_vec_118[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h77) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_119 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_119[1], + set_touch_ways_0_511_bits[1] + ? state_vec_119[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h78) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_120 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_120[1], + set_touch_ways_0_511_bits[1] + ? state_vec_120[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h79) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_121 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_121[1], + set_touch_ways_0_511_bits[1] + ? state_vec_121[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h7A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_122 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_122[1], + set_touch_ways_0_511_bits[1] + ? state_vec_122[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h7B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_123 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_123[1], + set_touch_ways_0_511_bits[1] + ? state_vec_123[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h7C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_124 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_124[1], + set_touch_ways_0_511_bits[1] + ? state_vec_124[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h7D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_125 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_125[1], + set_touch_ways_0_511_bits[1] + ? state_vec_125[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h7E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_126 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_126[1], + set_touch_ways_0_511_bits[1] + ? state_vec_126[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h7F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_127 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_127[1], + set_touch_ways_0_511_bits[1] + ? state_vec_127[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h80) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_128 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_128[1], + set_touch_ways_0_511_bits[1] + ? state_vec_128[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h81) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_129 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_129[1], + set_touch_ways_0_511_bits[1] + ? state_vec_129[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h82) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_130 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_130[1], + set_touch_ways_0_511_bits[1] + ? state_vec_130[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h83) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_131 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_131[1], + set_touch_ways_0_511_bits[1] + ? state_vec_131[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h84) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_132 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_132[1], + set_touch_ways_0_511_bits[1] + ? state_vec_132[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h85) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_133 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_133[1], + set_touch_ways_0_511_bits[1] + ? state_vec_133[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h86) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_134 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_134[1], + set_touch_ways_0_511_bits[1] + ? state_vec_134[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h87) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_135 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_135[1], + set_touch_ways_0_511_bits[1] + ? state_vec_135[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h88) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_136 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_136[1], + set_touch_ways_0_511_bits[1] + ? state_vec_136[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h89) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_137 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_137[1], + set_touch_ways_0_511_bits[1] + ? state_vec_137[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h8A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_138 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_138[1], + set_touch_ways_0_511_bits[1] + ? state_vec_138[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h8B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_139 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_139[1], + set_touch_ways_0_511_bits[1] + ? state_vec_139[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h8C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_140 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_140[1], + set_touch_ways_0_511_bits[1] + ? state_vec_140[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h8D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_141 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_141[1], + set_touch_ways_0_511_bits[1] + ? state_vec_141[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h8E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_142 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_142[1], + set_touch_ways_0_511_bits[1] + ? state_vec_142[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h8F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_143 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_143[1], + set_touch_ways_0_511_bits[1] + ? state_vec_143[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h90) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_144 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_144[1], + set_touch_ways_0_511_bits[1] + ? state_vec_144[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h91) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_145 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_145[1], + set_touch_ways_0_511_bits[1] + ? state_vec_145[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h92) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_146 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_146[1], + set_touch_ways_0_511_bits[1] + ? state_vec_146[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h93) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_147 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_147[1], + set_touch_ways_0_511_bits[1] + ? state_vec_147[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h94) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_148 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_148[1], + set_touch_ways_0_511_bits[1] + ? state_vec_148[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h95) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_149 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_149[1], + set_touch_ways_0_511_bits[1] + ? state_vec_149[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h96) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_150 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_150[1], + set_touch_ways_0_511_bits[1] + ? state_vec_150[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h97) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_151 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_151[1], + set_touch_ways_0_511_bits[1] + ? state_vec_151[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h98) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_152 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_152[1], + set_touch_ways_0_511_bits[1] + ? state_vec_152[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h99) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_153 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_153[1], + set_touch_ways_0_511_bits[1] + ? state_vec_153[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h9A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_154 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_154[1], + set_touch_ways_0_511_bits[1] + ? state_vec_154[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h9B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_155 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_155[1], + set_touch_ways_0_511_bits[1] + ? state_vec_155[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h9C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_156 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_156[1], + set_touch_ways_0_511_bits[1] + ? state_vec_156[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h9D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_157 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_157[1], + set_touch_ways_0_511_bits[1] + ? state_vec_157[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h9E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_158 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_158[1], + set_touch_ways_0_511_bits[1] + ? state_vec_158[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h9F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_159 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_159[1], + set_touch_ways_0_511_bits[1] + ? state_vec_159[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hA0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_160 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_160[1], + set_touch_ways_0_511_bits[1] + ? state_vec_160[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hA1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_161 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_161[1], + set_touch_ways_0_511_bits[1] + ? state_vec_161[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hA2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_162 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_162[1], + set_touch_ways_0_511_bits[1] + ? state_vec_162[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hA3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_163 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_163[1], + set_touch_ways_0_511_bits[1] + ? state_vec_163[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hA4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_164 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_164[1], + set_touch_ways_0_511_bits[1] + ? state_vec_164[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hA5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_165 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_165[1], + set_touch_ways_0_511_bits[1] + ? state_vec_165[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hA6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_166 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_166[1], + set_touch_ways_0_511_bits[1] + ? state_vec_166[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hA7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_167 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_167[1], + set_touch_ways_0_511_bits[1] + ? state_vec_167[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hA8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_168 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_168[1], + set_touch_ways_0_511_bits[1] + ? state_vec_168[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hA9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_169 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_169[1], + set_touch_ways_0_511_bits[1] + ? state_vec_169[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hAA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_170 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_170[1], + set_touch_ways_0_511_bits[1] + ? state_vec_170[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hAB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_171 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_171[1], + set_touch_ways_0_511_bits[1] + ? state_vec_171[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hAC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_172 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_172[1], + set_touch_ways_0_511_bits[1] + ? state_vec_172[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hAD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_173 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_173[1], + set_touch_ways_0_511_bits[1] + ? state_vec_173[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hAE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_174 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_174[1], + set_touch_ways_0_511_bits[1] + ? state_vec_174[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hAF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_175 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_175[1], + set_touch_ways_0_511_bits[1] + ? state_vec_175[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hB0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_176 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_176[1], + set_touch_ways_0_511_bits[1] + ? state_vec_176[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hB1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_177 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_177[1], + set_touch_ways_0_511_bits[1] + ? state_vec_177[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hB2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_178 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_178[1], + set_touch_ways_0_511_bits[1] + ? state_vec_178[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hB3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_179 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_179[1], + set_touch_ways_0_511_bits[1] + ? state_vec_179[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hB4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_180 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_180[1], + set_touch_ways_0_511_bits[1] + ? state_vec_180[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hB5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_181 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_181[1], + set_touch_ways_0_511_bits[1] + ? state_vec_181[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hB6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_182 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_182[1], + set_touch_ways_0_511_bits[1] + ? state_vec_182[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hB7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_183 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_183[1], + set_touch_ways_0_511_bits[1] + ? state_vec_183[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hB8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_184 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_184[1], + set_touch_ways_0_511_bits[1] + ? state_vec_184[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hB9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_185 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_185[1], + set_touch_ways_0_511_bits[1] + ? state_vec_185[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hBA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_186 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_186[1], + set_touch_ways_0_511_bits[1] + ? state_vec_186[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hBB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_187 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_187[1], + set_touch_ways_0_511_bits[1] + ? state_vec_187[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hBC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_188 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_188[1], + set_touch_ways_0_511_bits[1] + ? state_vec_188[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hBD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_189 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_189[1], + set_touch_ways_0_511_bits[1] + ? state_vec_189[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hBE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_190 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_190[1], + set_touch_ways_0_511_bits[1] + ? state_vec_190[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hBF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_191 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_191[1], + set_touch_ways_0_511_bits[1] + ? state_vec_191[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hC0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_192 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_192[1], + set_touch_ways_0_511_bits[1] + ? state_vec_192[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hC1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_193 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_193[1], + set_touch_ways_0_511_bits[1] + ? state_vec_193[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hC2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_194 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_194[1], + set_touch_ways_0_511_bits[1] + ? state_vec_194[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hC3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_195 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_195[1], + set_touch_ways_0_511_bits[1] + ? state_vec_195[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hC4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_196 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_196[1], + set_touch_ways_0_511_bits[1] + ? state_vec_196[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hC5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_197 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_197[1], + set_touch_ways_0_511_bits[1] + ? state_vec_197[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hC6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_198 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_198[1], + set_touch_ways_0_511_bits[1] + ? state_vec_198[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hC7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_199 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_199[1], + set_touch_ways_0_511_bits[1] + ? state_vec_199[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hC8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_200 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_200[1], + set_touch_ways_0_511_bits[1] + ? state_vec_200[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hC9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_201 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_201[1], + set_touch_ways_0_511_bits[1] + ? state_vec_201[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hCA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_202 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_202[1], + set_touch_ways_0_511_bits[1] + ? state_vec_202[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hCB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_203 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_203[1], + set_touch_ways_0_511_bits[1] + ? state_vec_203[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hCC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_204 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_204[1], + set_touch_ways_0_511_bits[1] + ? state_vec_204[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hCD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_205 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_205[1], + set_touch_ways_0_511_bits[1] + ? state_vec_205[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hCE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_206 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_206[1], + set_touch_ways_0_511_bits[1] + ? state_vec_206[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hCF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_207 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_207[1], + set_touch_ways_0_511_bits[1] + ? state_vec_207[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hD0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_208 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_208[1], + set_touch_ways_0_511_bits[1] + ? state_vec_208[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hD1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_209 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_209[1], + set_touch_ways_0_511_bits[1] + ? state_vec_209[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hD2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_210 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_210[1], + set_touch_ways_0_511_bits[1] + ? state_vec_210[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hD3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_211 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_211[1], + set_touch_ways_0_511_bits[1] + ? state_vec_211[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hD4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_212 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_212[1], + set_touch_ways_0_511_bits[1] + ? state_vec_212[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hD5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_213 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_213[1], + set_touch_ways_0_511_bits[1] + ? state_vec_213[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hD6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_214 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_214[1], + set_touch_ways_0_511_bits[1] + ? state_vec_214[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hD7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_215 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_215[1], + set_touch_ways_0_511_bits[1] + ? state_vec_215[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hD8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_216 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_216[1], + set_touch_ways_0_511_bits[1] + ? state_vec_216[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hD9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_217 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_217[1], + set_touch_ways_0_511_bits[1] + ? state_vec_217[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hDA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_218 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_218[1], + set_touch_ways_0_511_bits[1] + ? state_vec_218[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hDB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_219 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_219[1], + set_touch_ways_0_511_bits[1] + ? state_vec_219[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hDC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_220 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_220[1], + set_touch_ways_0_511_bits[1] + ? state_vec_220[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hDD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_221 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_221[1], + set_touch_ways_0_511_bits[1] + ? state_vec_221[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hDE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_222 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_222[1], + set_touch_ways_0_511_bits[1] + ? state_vec_222[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hDF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_223 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_223[1], + set_touch_ways_0_511_bits[1] + ? state_vec_223[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hE0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_224 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_224[1], + set_touch_ways_0_511_bits[1] + ? state_vec_224[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hE1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_225 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_225[1], + set_touch_ways_0_511_bits[1] + ? state_vec_225[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hE2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_226 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_226[1], + set_touch_ways_0_511_bits[1] + ? state_vec_226[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hE3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_227 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_227[1], + set_touch_ways_0_511_bits[1] + ? state_vec_227[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hE4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_228 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_228[1], + set_touch_ways_0_511_bits[1] + ? state_vec_228[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hE5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_229 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_229[1], + set_touch_ways_0_511_bits[1] + ? state_vec_229[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hE6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_230 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_230[1], + set_touch_ways_0_511_bits[1] + ? state_vec_230[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hE7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_231 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_231[1], + set_touch_ways_0_511_bits[1] + ? state_vec_231[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hE8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_232 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_232[1], + set_touch_ways_0_511_bits[1] + ? state_vec_232[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hE9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_233 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_233[1], + set_touch_ways_0_511_bits[1] + ? state_vec_233[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hEA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_234 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_234[1], + set_touch_ways_0_511_bits[1] + ? state_vec_234[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hEB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_235 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_235[1], + set_touch_ways_0_511_bits[1] + ? state_vec_235[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hEC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_236 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_236[1], + set_touch_ways_0_511_bits[1] + ? state_vec_236[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hED) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_237 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_237[1], + set_touch_ways_0_511_bits[1] + ? state_vec_237[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hEE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_238 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_238[1], + set_touch_ways_0_511_bits[1] + ? state_vec_238[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hEF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_239 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_239[1], + set_touch_ways_0_511_bits[1] + ? state_vec_239[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hF0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_240 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_240[1], + set_touch_ways_0_511_bits[1] + ? state_vec_240[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hF1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_241 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_241[1], + set_touch_ways_0_511_bits[1] + ? state_vec_241[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hF2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_242 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_242[1], + set_touch_ways_0_511_bits[1] + ? state_vec_242[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hF3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_243 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_243[1], + set_touch_ways_0_511_bits[1] + ? state_vec_243[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hF4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_244 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_244[1], + set_touch_ways_0_511_bits[1] + ? state_vec_244[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hF5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_245 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_245[1], + set_touch_ways_0_511_bits[1] + ? state_vec_245[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hF6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_246 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_246[1], + set_touch_ways_0_511_bits[1] + ? state_vec_246[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hF7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_247 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_247[1], + set_touch_ways_0_511_bits[1] + ? state_vec_247[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hF8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_248 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_248[1], + set_touch_ways_0_511_bits[1] + ? state_vec_248[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hF9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_249 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_249[1], + set_touch_ways_0_511_bits[1] + ? state_vec_249[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hFA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_250 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_250[1], + set_touch_ways_0_511_bits[1] + ? state_vec_250[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hFB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_251 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_251[1], + set_touch_ways_0_511_bits[1] + ? state_vec_251[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hFC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_252 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_252[1], + set_touch_ways_0_511_bits[1] + ? state_vec_252[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hFD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_253 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_253[1], + set_touch_ways_0_511_bits[1] + ? state_vec_253[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hFE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_254 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_254[1], + set_touch_ways_0_511_bits[1] + ? state_vec_254[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'hFF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_255 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_255[1], + set_touch_ways_0_511_bits[1] + ? state_vec_255[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h100) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_256 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_256[1], + set_touch_ways_0_511_bits[1] + ? state_vec_256[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h101) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_257 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_257[1], + set_touch_ways_0_511_bits[1] + ? state_vec_257[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h102) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_258 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_258[1], + set_touch_ways_0_511_bits[1] + ? state_vec_258[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h103) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_259 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_259[1], + set_touch_ways_0_511_bits[1] + ? state_vec_259[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h104) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_260 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_260[1], + set_touch_ways_0_511_bits[1] + ? state_vec_260[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h105) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_261 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_261[1], + set_touch_ways_0_511_bits[1] + ? state_vec_261[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h106) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_262 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_262[1], + set_touch_ways_0_511_bits[1] + ? state_vec_262[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h107) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_263 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_263[1], + set_touch_ways_0_511_bits[1] + ? state_vec_263[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h108) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_264 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_264[1], + set_touch_ways_0_511_bits[1] + ? state_vec_264[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h109) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_265 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_265[1], + set_touch_ways_0_511_bits[1] + ? state_vec_265[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h10A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_266 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_266[1], + set_touch_ways_0_511_bits[1] + ? state_vec_266[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h10B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_267 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_267[1], + set_touch_ways_0_511_bits[1] + ? state_vec_267[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h10C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_268 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_268[1], + set_touch_ways_0_511_bits[1] + ? state_vec_268[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h10D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_269 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_269[1], + set_touch_ways_0_511_bits[1] + ? state_vec_269[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h10E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_270 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_270[1], + set_touch_ways_0_511_bits[1] + ? state_vec_270[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h10F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_271 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_271[1], + set_touch_ways_0_511_bits[1] + ? state_vec_271[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h110) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_272 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_272[1], + set_touch_ways_0_511_bits[1] + ? state_vec_272[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h111) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_273 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_273[1], + set_touch_ways_0_511_bits[1] + ? state_vec_273[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h112) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_274 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_274[1], + set_touch_ways_0_511_bits[1] + ? state_vec_274[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h113) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_275 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_275[1], + set_touch_ways_0_511_bits[1] + ? state_vec_275[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h114) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_276 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_276[1], + set_touch_ways_0_511_bits[1] + ? state_vec_276[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h115) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_277 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_277[1], + set_touch_ways_0_511_bits[1] + ? state_vec_277[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h116) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_278 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_278[1], + set_touch_ways_0_511_bits[1] + ? state_vec_278[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h117) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_279 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_279[1], + set_touch_ways_0_511_bits[1] + ? state_vec_279[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h118) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_280 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_280[1], + set_touch_ways_0_511_bits[1] + ? state_vec_280[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h119) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_281 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_281[1], + set_touch_ways_0_511_bits[1] + ? state_vec_281[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h11A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_282 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_282[1], + set_touch_ways_0_511_bits[1] + ? state_vec_282[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h11B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_283 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_283[1], + set_touch_ways_0_511_bits[1] + ? state_vec_283[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h11C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_284 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_284[1], + set_touch_ways_0_511_bits[1] + ? state_vec_284[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h11D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_285 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_285[1], + set_touch_ways_0_511_bits[1] + ? state_vec_285[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h11E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_286 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_286[1], + set_touch_ways_0_511_bits[1] + ? state_vec_286[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h11F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_287 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_287[1], + set_touch_ways_0_511_bits[1] + ? state_vec_287[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h120) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_288 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_288[1], + set_touch_ways_0_511_bits[1] + ? state_vec_288[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h121) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_289 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_289[1], + set_touch_ways_0_511_bits[1] + ? state_vec_289[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h122) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_290 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_290[1], + set_touch_ways_0_511_bits[1] + ? state_vec_290[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h123) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_291 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_291[1], + set_touch_ways_0_511_bits[1] + ? state_vec_291[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h124) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_292 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_292[1], + set_touch_ways_0_511_bits[1] + ? state_vec_292[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h125) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_293 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_293[1], + set_touch_ways_0_511_bits[1] + ? state_vec_293[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h126) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_294 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_294[1], + set_touch_ways_0_511_bits[1] + ? state_vec_294[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h127) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_295 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_295[1], + set_touch_ways_0_511_bits[1] + ? state_vec_295[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h128) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_296 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_296[1], + set_touch_ways_0_511_bits[1] + ? state_vec_296[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h129) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_297 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_297[1], + set_touch_ways_0_511_bits[1] + ? state_vec_297[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h12A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_298 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_298[1], + set_touch_ways_0_511_bits[1] + ? state_vec_298[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h12B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_299 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_299[1], + set_touch_ways_0_511_bits[1] + ? state_vec_299[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h12C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_300 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_300[1], + set_touch_ways_0_511_bits[1] + ? state_vec_300[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h12D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_301 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_301[1], + set_touch_ways_0_511_bits[1] + ? state_vec_301[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h12E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_302 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_302[1], + set_touch_ways_0_511_bits[1] + ? state_vec_302[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h12F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_303 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_303[1], + set_touch_ways_0_511_bits[1] + ? state_vec_303[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h130) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_304 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_304[1], + set_touch_ways_0_511_bits[1] + ? state_vec_304[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h131) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_305 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_305[1], + set_touch_ways_0_511_bits[1] + ? state_vec_305[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h132) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_306 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_306[1], + set_touch_ways_0_511_bits[1] + ? state_vec_306[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h133) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_307 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_307[1], + set_touch_ways_0_511_bits[1] + ? state_vec_307[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h134) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_308 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_308[1], + set_touch_ways_0_511_bits[1] + ? state_vec_308[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h135) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_309 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_309[1], + set_touch_ways_0_511_bits[1] + ? state_vec_309[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h136) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_310 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_310[1], + set_touch_ways_0_511_bits[1] + ? state_vec_310[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h137) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_311 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_311[1], + set_touch_ways_0_511_bits[1] + ? state_vec_311[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h138) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_312 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_312[1], + set_touch_ways_0_511_bits[1] + ? state_vec_312[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h139) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_313 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_313[1], + set_touch_ways_0_511_bits[1] + ? state_vec_313[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h13A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_314 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_314[1], + set_touch_ways_0_511_bits[1] + ? state_vec_314[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h13B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_315 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_315[1], + set_touch_ways_0_511_bits[1] + ? state_vec_315[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h13C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_316 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_316[1], + set_touch_ways_0_511_bits[1] + ? state_vec_316[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h13D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_317 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_317[1], + set_touch_ways_0_511_bits[1] + ? state_vec_317[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h13E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_318 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_318[1], + set_touch_ways_0_511_bits[1] + ? state_vec_318[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h13F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_319 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_319[1], + set_touch_ways_0_511_bits[1] + ? state_vec_319[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h140) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_320 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_320[1], + set_touch_ways_0_511_bits[1] + ? state_vec_320[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h141) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_321 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_321[1], + set_touch_ways_0_511_bits[1] + ? state_vec_321[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h142) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_322 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_322[1], + set_touch_ways_0_511_bits[1] + ? state_vec_322[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h143) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_323 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_323[1], + set_touch_ways_0_511_bits[1] + ? state_vec_323[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h144) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_324 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_324[1], + set_touch_ways_0_511_bits[1] + ? state_vec_324[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h145) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_325 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_325[1], + set_touch_ways_0_511_bits[1] + ? state_vec_325[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h146) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_326 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_326[1], + set_touch_ways_0_511_bits[1] + ? state_vec_326[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h147) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_327 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_327[1], + set_touch_ways_0_511_bits[1] + ? state_vec_327[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h148) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_328 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_328[1], + set_touch_ways_0_511_bits[1] + ? state_vec_328[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h149) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_329 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_329[1], + set_touch_ways_0_511_bits[1] + ? state_vec_329[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h14A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_330 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_330[1], + set_touch_ways_0_511_bits[1] + ? state_vec_330[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h14B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_331 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_331[1], + set_touch_ways_0_511_bits[1] + ? state_vec_331[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h14C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_332 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_332[1], + set_touch_ways_0_511_bits[1] + ? state_vec_332[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h14D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_333 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_333[1], + set_touch_ways_0_511_bits[1] + ? state_vec_333[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h14E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_334 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_334[1], + set_touch_ways_0_511_bits[1] + ? state_vec_334[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h14F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_335 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_335[1], + set_touch_ways_0_511_bits[1] + ? state_vec_335[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h150) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_336 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_336[1], + set_touch_ways_0_511_bits[1] + ? state_vec_336[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h151) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_337 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_337[1], + set_touch_ways_0_511_bits[1] + ? state_vec_337[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h152) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_338 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_338[1], + set_touch_ways_0_511_bits[1] + ? state_vec_338[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h153) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_339 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_339[1], + set_touch_ways_0_511_bits[1] + ? state_vec_339[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h154) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_340 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_340[1], + set_touch_ways_0_511_bits[1] + ? state_vec_340[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h155) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_341 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_341[1], + set_touch_ways_0_511_bits[1] + ? state_vec_341[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h156) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_342 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_342[1], + set_touch_ways_0_511_bits[1] + ? state_vec_342[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h157) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_343 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_343[1], + set_touch_ways_0_511_bits[1] + ? state_vec_343[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h158) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_344 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_344[1], + set_touch_ways_0_511_bits[1] + ? state_vec_344[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h159) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_345 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_345[1], + set_touch_ways_0_511_bits[1] + ? state_vec_345[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h15A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_346 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_346[1], + set_touch_ways_0_511_bits[1] + ? state_vec_346[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h15B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_347 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_347[1], + set_touch_ways_0_511_bits[1] + ? state_vec_347[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h15C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_348 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_348[1], + set_touch_ways_0_511_bits[1] + ? state_vec_348[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h15D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_349 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_349[1], + set_touch_ways_0_511_bits[1] + ? state_vec_349[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h15E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_350 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_350[1], + set_touch_ways_0_511_bits[1] + ? state_vec_350[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h15F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_351 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_351[1], + set_touch_ways_0_511_bits[1] + ? state_vec_351[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h160) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_352 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_352[1], + set_touch_ways_0_511_bits[1] + ? state_vec_352[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h161) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_353 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_353[1], + set_touch_ways_0_511_bits[1] + ? state_vec_353[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h162) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_354 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_354[1], + set_touch_ways_0_511_bits[1] + ? state_vec_354[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h163) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_355 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_355[1], + set_touch_ways_0_511_bits[1] + ? state_vec_355[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h164) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_356 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_356[1], + set_touch_ways_0_511_bits[1] + ? state_vec_356[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h165) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_357 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_357[1], + set_touch_ways_0_511_bits[1] + ? state_vec_357[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h166) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_358 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_358[1], + set_touch_ways_0_511_bits[1] + ? state_vec_358[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h167) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_359 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_359[1], + set_touch_ways_0_511_bits[1] + ? state_vec_359[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h168) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_360 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_360[1], + set_touch_ways_0_511_bits[1] + ? state_vec_360[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h169) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_361 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_361[1], + set_touch_ways_0_511_bits[1] + ? state_vec_361[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h16A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_362 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_362[1], + set_touch_ways_0_511_bits[1] + ? state_vec_362[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h16B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_363 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_363[1], + set_touch_ways_0_511_bits[1] + ? state_vec_363[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h16C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_364 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_364[1], + set_touch_ways_0_511_bits[1] + ? state_vec_364[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h16D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_365 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_365[1], + set_touch_ways_0_511_bits[1] + ? state_vec_365[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h16E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_366 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_366[1], + set_touch_ways_0_511_bits[1] + ? state_vec_366[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h16F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_367 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_367[1], + set_touch_ways_0_511_bits[1] + ? state_vec_367[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h170) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_368 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_368[1], + set_touch_ways_0_511_bits[1] + ? state_vec_368[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h171) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_369 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_369[1], + set_touch_ways_0_511_bits[1] + ? state_vec_369[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h172) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_370 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_370[1], + set_touch_ways_0_511_bits[1] + ? state_vec_370[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h173) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_371 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_371[1], + set_touch_ways_0_511_bits[1] + ? state_vec_371[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h174) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_372 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_372[1], + set_touch_ways_0_511_bits[1] + ? state_vec_372[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h175) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_373 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_373[1], + set_touch_ways_0_511_bits[1] + ? state_vec_373[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h176) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_374 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_374[1], + set_touch_ways_0_511_bits[1] + ? state_vec_374[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h177) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_375 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_375[1], + set_touch_ways_0_511_bits[1] + ? state_vec_375[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h178) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_376 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_376[1], + set_touch_ways_0_511_bits[1] + ? state_vec_376[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h179) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_377 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_377[1], + set_touch_ways_0_511_bits[1] + ? state_vec_377[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h17A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_378 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_378[1], + set_touch_ways_0_511_bits[1] + ? state_vec_378[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h17B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_379 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_379[1], + set_touch_ways_0_511_bits[1] + ? state_vec_379[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h17C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_380 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_380[1], + set_touch_ways_0_511_bits[1] + ? state_vec_380[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h17D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_381 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_381[1], + set_touch_ways_0_511_bits[1] + ? state_vec_381[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h17E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_382 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_382[1], + set_touch_ways_0_511_bits[1] + ? state_vec_382[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h17F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_383 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_383[1], + set_touch_ways_0_511_bits[1] + ? state_vec_383[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h180) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_384 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_384[1], + set_touch_ways_0_511_bits[1] + ? state_vec_384[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h181) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_385 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_385[1], + set_touch_ways_0_511_bits[1] + ? state_vec_385[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h182) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_386 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_386[1], + set_touch_ways_0_511_bits[1] + ? state_vec_386[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h183) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_387 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_387[1], + set_touch_ways_0_511_bits[1] + ? state_vec_387[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h184) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_388 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_388[1], + set_touch_ways_0_511_bits[1] + ? state_vec_388[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h185) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_389 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_389[1], + set_touch_ways_0_511_bits[1] + ? state_vec_389[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h186) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_390 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_390[1], + set_touch_ways_0_511_bits[1] + ? state_vec_390[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h187) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_391 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_391[1], + set_touch_ways_0_511_bits[1] + ? state_vec_391[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h188) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_392 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_392[1], + set_touch_ways_0_511_bits[1] + ? state_vec_392[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h189) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_393 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_393[1], + set_touch_ways_0_511_bits[1] + ? state_vec_393[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h18A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_394 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_394[1], + set_touch_ways_0_511_bits[1] + ? state_vec_394[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h18B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_395 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_395[1], + set_touch_ways_0_511_bits[1] + ? state_vec_395[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h18C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_396 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_396[1], + set_touch_ways_0_511_bits[1] + ? state_vec_396[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h18D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_397 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_397[1], + set_touch_ways_0_511_bits[1] + ? state_vec_397[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h18E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_398 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_398[1], + set_touch_ways_0_511_bits[1] + ? state_vec_398[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h18F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_399 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_399[1], + set_touch_ways_0_511_bits[1] + ? state_vec_399[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h190) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_400 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_400[1], + set_touch_ways_0_511_bits[1] + ? state_vec_400[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h191) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_401 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_401[1], + set_touch_ways_0_511_bits[1] + ? state_vec_401[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h192) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_402 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_402[1], + set_touch_ways_0_511_bits[1] + ? state_vec_402[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h193) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_403 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_403[1], + set_touch_ways_0_511_bits[1] + ? state_vec_403[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h194) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_404 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_404[1], + set_touch_ways_0_511_bits[1] + ? state_vec_404[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h195) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_405 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_405[1], + set_touch_ways_0_511_bits[1] + ? state_vec_405[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h196) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_406 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_406[1], + set_touch_ways_0_511_bits[1] + ? state_vec_406[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h197) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_407 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_407[1], + set_touch_ways_0_511_bits[1] + ? state_vec_407[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h198) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_408 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_408[1], + set_touch_ways_0_511_bits[1] + ? state_vec_408[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h199) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_409 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_409[1], + set_touch_ways_0_511_bits[1] + ? state_vec_409[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h19A) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_410 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_410[1], + set_touch_ways_0_511_bits[1] + ? state_vec_410[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h19B) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_411 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_411[1], + set_touch_ways_0_511_bits[1] + ? state_vec_411[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h19C) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_412 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_412[1], + set_touch_ways_0_511_bits[1] + ? state_vec_412[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h19D) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_413 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_413[1], + set_touch_ways_0_511_bits[1] + ? state_vec_413[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h19E) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_414 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_414[1], + set_touch_ways_0_511_bits[1] + ? state_vec_414[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h19F) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_415 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_415[1], + set_touch_ways_0_511_bits[1] + ? state_vec_415[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1A0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_416 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_416[1], + set_touch_ways_0_511_bits[1] + ? state_vec_416[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1A1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_417 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_417[1], + set_touch_ways_0_511_bits[1] + ? state_vec_417[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1A2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_418 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_418[1], + set_touch_ways_0_511_bits[1] + ? state_vec_418[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1A3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_419 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_419[1], + set_touch_ways_0_511_bits[1] + ? state_vec_419[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1A4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_420 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_420[1], + set_touch_ways_0_511_bits[1] + ? state_vec_420[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1A5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_421 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_421[1], + set_touch_ways_0_511_bits[1] + ? state_vec_421[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1A6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_422 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_422[1], + set_touch_ways_0_511_bits[1] + ? state_vec_422[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1A7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_423 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_423[1], + set_touch_ways_0_511_bits[1] + ? state_vec_423[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1A8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_424 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_424[1], + set_touch_ways_0_511_bits[1] + ? state_vec_424[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1A9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_425 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_425[1], + set_touch_ways_0_511_bits[1] + ? state_vec_425[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1AA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_426 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_426[1], + set_touch_ways_0_511_bits[1] + ? state_vec_426[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1AB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_427 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_427[1], + set_touch_ways_0_511_bits[1] + ? state_vec_427[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1AC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_428 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_428[1], + set_touch_ways_0_511_bits[1] + ? state_vec_428[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1AD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_429 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_429[1], + set_touch_ways_0_511_bits[1] + ? state_vec_429[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1AE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_430 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_430[1], + set_touch_ways_0_511_bits[1] + ? state_vec_430[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1AF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_431 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_431[1], + set_touch_ways_0_511_bits[1] + ? state_vec_431[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1B0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_432 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_432[1], + set_touch_ways_0_511_bits[1] + ? state_vec_432[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1B1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_433 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_433[1], + set_touch_ways_0_511_bits[1] + ? state_vec_433[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1B2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_434 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_434[1], + set_touch_ways_0_511_bits[1] + ? state_vec_434[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1B3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_435 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_435[1], + set_touch_ways_0_511_bits[1] + ? state_vec_435[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1B4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_436 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_436[1], + set_touch_ways_0_511_bits[1] + ? state_vec_436[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1B5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_437 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_437[1], + set_touch_ways_0_511_bits[1] + ? state_vec_437[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1B6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_438 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_438[1], + set_touch_ways_0_511_bits[1] + ? state_vec_438[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1B7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_439 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_439[1], + set_touch_ways_0_511_bits[1] + ? state_vec_439[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1B8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_440 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_440[1], + set_touch_ways_0_511_bits[1] + ? state_vec_440[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1B9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_441 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_441[1], + set_touch_ways_0_511_bits[1] + ? state_vec_441[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1BA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_442 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_442[1], + set_touch_ways_0_511_bits[1] + ? state_vec_442[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1BB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_443 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_443[1], + set_touch_ways_0_511_bits[1] + ? state_vec_443[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1BC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_444 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_444[1], + set_touch_ways_0_511_bits[1] + ? state_vec_444[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1BD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_445 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_445[1], + set_touch_ways_0_511_bits[1] + ? state_vec_445[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1BE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_446 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_446[1], + set_touch_ways_0_511_bits[1] + ? state_vec_446[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1BF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_447 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_447[1], + set_touch_ways_0_511_bits[1] + ? state_vec_447[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1C0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_448 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_448[1], + set_touch_ways_0_511_bits[1] + ? state_vec_448[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1C1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_449 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_449[1], + set_touch_ways_0_511_bits[1] + ? state_vec_449[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1C2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_450 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_450[1], + set_touch_ways_0_511_bits[1] + ? state_vec_450[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1C3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_451 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_451[1], + set_touch_ways_0_511_bits[1] + ? state_vec_451[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1C4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_452 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_452[1], + set_touch_ways_0_511_bits[1] + ? state_vec_452[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1C5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_453 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_453[1], + set_touch_ways_0_511_bits[1] + ? state_vec_453[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1C6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_454 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_454[1], + set_touch_ways_0_511_bits[1] + ? state_vec_454[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1C7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_455 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_455[1], + set_touch_ways_0_511_bits[1] + ? state_vec_455[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1C8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_456 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_456[1], + set_touch_ways_0_511_bits[1] + ? state_vec_456[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1C9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_457 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_457[1], + set_touch_ways_0_511_bits[1] + ? state_vec_457[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1CA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_458 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_458[1], + set_touch_ways_0_511_bits[1] + ? state_vec_458[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1CB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_459 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_459[1], + set_touch_ways_0_511_bits[1] + ? state_vec_459[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1CC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_460 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_460[1], + set_touch_ways_0_511_bits[1] + ? state_vec_460[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1CD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_461 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_461[1], + set_touch_ways_0_511_bits[1] + ? state_vec_461[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1CE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_462 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_462[1], + set_touch_ways_0_511_bits[1] + ? state_vec_462[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1CF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_463 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_463[1], + set_touch_ways_0_511_bits[1] + ? state_vec_463[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1D0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_464 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_464[1], + set_touch_ways_0_511_bits[1] + ? state_vec_464[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1D1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_465 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_465[1], + set_touch_ways_0_511_bits[1] + ? state_vec_465[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1D2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_466 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_466[1], + set_touch_ways_0_511_bits[1] + ? state_vec_466[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1D3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_467 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_467[1], + set_touch_ways_0_511_bits[1] + ? state_vec_467[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1D4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_468 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_468[1], + set_touch_ways_0_511_bits[1] + ? state_vec_468[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1D5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_469 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_469[1], + set_touch_ways_0_511_bits[1] + ? state_vec_469[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1D6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_470 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_470[1], + set_touch_ways_0_511_bits[1] + ? state_vec_470[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1D7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_471 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_471[1], + set_touch_ways_0_511_bits[1] + ? state_vec_471[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1D8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_472 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_472[1], + set_touch_ways_0_511_bits[1] + ? state_vec_472[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1D9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_473 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_473[1], + set_touch_ways_0_511_bits[1] + ? state_vec_473[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1DA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_474 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_474[1], + set_touch_ways_0_511_bits[1] + ? state_vec_474[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1DB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_475 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_475[1], + set_touch_ways_0_511_bits[1] + ? state_vec_475[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1DC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_476 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_476[1], + set_touch_ways_0_511_bits[1] + ? state_vec_476[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1DD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_477 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_477[1], + set_touch_ways_0_511_bits[1] + ? state_vec_477[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1DE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_478 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_478[1], + set_touch_ways_0_511_bits[1] + ? state_vec_478[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1DF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_479 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_479[1], + set_touch_ways_0_511_bits[1] + ? state_vec_479[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1E0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_480 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_480[1], + set_touch_ways_0_511_bits[1] + ? state_vec_480[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1E1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_481 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_481[1], + set_touch_ways_0_511_bits[1] + ? state_vec_481[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1E2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_482 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_482[1], + set_touch_ways_0_511_bits[1] + ? state_vec_482[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1E3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_483 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_483[1], + set_touch_ways_0_511_bits[1] + ? state_vec_483[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1E4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_484 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_484[1], + set_touch_ways_0_511_bits[1] + ? state_vec_484[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1E5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_485 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_485[1], + set_touch_ways_0_511_bits[1] + ? state_vec_485[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1E6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_486 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_486[1], + set_touch_ways_0_511_bits[1] + ? state_vec_486[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1E7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_487 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_487[1], + set_touch_ways_0_511_bits[1] + ? state_vec_487[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1E8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_488 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_488[1], + set_touch_ways_0_511_bits[1] + ? state_vec_488[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1E9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_489 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_489[1], + set_touch_ways_0_511_bits[1] + ? state_vec_489[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1EA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_490 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_490[1], + set_touch_ways_0_511_bits[1] + ? state_vec_490[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1EB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_491 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_491[1], + set_touch_ways_0_511_bits[1] + ? state_vec_491[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1EC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_492 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_492[1], + set_touch_ways_0_511_bits[1] + ? state_vec_492[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1ED) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_493 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_493[1], + set_touch_ways_0_511_bits[1] + ? state_vec_493[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1EE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_494 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_494[1], + set_touch_ways_0_511_bits[1] + ? state_vec_494[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1EF) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_495 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_495[1], + set_touch_ways_0_511_bits[1] + ? state_vec_495[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1F0) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_496 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_496[1], + set_touch_ways_0_511_bits[1] + ? state_vec_496[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1F1) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_497 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_497[1], + set_touch_ways_0_511_bits[1] + ? state_vec_497[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1F2) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_498 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_498[1], + set_touch_ways_0_511_bits[1] + ? state_vec_498[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1F3) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_499 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_499[1], + set_touch_ways_0_511_bits[1] + ? state_vec_499[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1F4) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_500 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_500[1], + set_touch_ways_0_511_bits[1] + ? state_vec_500[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1F5) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_501 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_501[1], + set_touch_ways_0_511_bits[1] + ? state_vec_501[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1F6) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_502 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_502[1], + set_touch_ways_0_511_bits[1] + ? state_vec_502[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1F7) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_503 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_503[1], + set_touch_ways_0_511_bits[1] + ? state_vec_503[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1F8) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_504 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_504[1], + set_touch_ways_0_511_bits[1] + ? state_vec_504[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1F9) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_505 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_505[1], + set_touch_ways_0_511_bits[1] + ? state_vec_505[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1FA) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_506 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_506[1], + set_touch_ways_0_511_bits[1] + ? state_vec_506[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1FB) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_507 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_507[1], + set_touch_ways_0_511_bits[1] + ? state_vec_507[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1FC) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_508 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_508[1], + set_touch_ways_0_511_bits[1] + ? state_vec_508[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1FD) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_509 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_509[1], + set_touch_ways_0_511_bits[1] + ? state_vec_509[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & touch_set_0 == 9'h1FE) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_510 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_510[1], + set_touch_ways_0_511_bits[1] + ? state_vec_510[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + if (touch_way_0_valid & (&touch_set_0)) // rocket-chip/src/main/scala/util/Replacement.scala:384:{30,44}, src/main/scala/xiangshan/frontend/FTB.scala:368:24, :369:43 + state_vec_511 <= + {~(set_touch_ways_0_511_bits[1]), + set_touch_ways_0_511_bits[1] + ? ~(set_touch_ways_0_511_bits[0]) + : state_vec_511[1], + set_touch_ways_0_511_bits[1] + ? state_vec_511[0] + : ~(set_touch_ways_0_511_bits[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :374:17, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FTB.scala:370:29 + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:60]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + initial begin // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + for (logic [5:0] i = 6'h0; i < 6'h3D; i += 6'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + end // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + pred_rdata_REG = _RANDOM[6'h0][0]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62 + pred_rdata_hold_data_0_entry_valid = _RANDOM[6'h0][1]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_brSlots_0_offset = _RANDOM[6'h0][5:2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_brSlots_0_lower = _RANDOM[6'h0][17:6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_brSlots_0_tarStat = _RANDOM[6'h0][19:18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_brSlots_0_sharing = _RANDOM[6'h0][20]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_brSlots_0_valid = _RANDOM[6'h0][21]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_tailSlot_offset = _RANDOM[6'h0][25:22]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_tailSlot_lower = + {_RANDOM[6'h0][31:26], _RANDOM[6'h1][13:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :315:62, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_tailSlot_tarStat = _RANDOM[6'h1][15:14]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_tailSlot_sharing = _RANDOM[6'h1][16]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_tailSlot_valid = _RANDOM[6'h1][17]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_pftAddr = _RANDOM[6'h1][21:18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_carry = _RANDOM[6'h1][22]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_isCall = _RANDOM[6'h1][23]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_isRet = _RANDOM[6'h1][24]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_isJalr = _RANDOM[6'h1][25]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_last_may_be_rvi_call = _RANDOM[6'h1][26]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_always_taken_0 = _RANDOM[6'h1][27]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_entry_always_taken_1 = _RANDOM[6'h1][28]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_0_tag = {_RANDOM[6'h1][31:29], _RANDOM[6'h2][16:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_valid = _RANDOM[6'h2][17]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_brSlots_0_offset = _RANDOM[6'h2][21:18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_brSlots_0_lower = + {_RANDOM[6'h2][31:22], _RANDOM[6'h3][1:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_brSlots_0_tarStat = _RANDOM[6'h3][3:2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_brSlots_0_sharing = _RANDOM[6'h3][4]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_brSlots_0_valid = _RANDOM[6'h3][5]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_tailSlot_offset = _RANDOM[6'h3][9:6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_tailSlot_lower = _RANDOM[6'h3][29:10]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_tailSlot_tarStat = _RANDOM[6'h3][31:30]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_tailSlot_sharing = _RANDOM[6'h4][0]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_tailSlot_valid = _RANDOM[6'h4][1]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_pftAddr = _RANDOM[6'h4][5:2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_carry = _RANDOM[6'h4][6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_isCall = _RANDOM[6'h4][7]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_isRet = _RANDOM[6'h4][8]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_isJalr = _RANDOM[6'h4][9]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_last_may_be_rvi_call = _RANDOM[6'h4][10]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_always_taken_0 = _RANDOM[6'h4][11]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_entry_always_taken_1 = _RANDOM[6'h4][12]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_1_tag = {_RANDOM[6'h4][31:13], _RANDOM[6'h5][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_valid = _RANDOM[6'h5][1]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_brSlots_0_offset = _RANDOM[6'h5][5:2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_brSlots_0_lower = _RANDOM[6'h5][17:6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_brSlots_0_tarStat = _RANDOM[6'h5][19:18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_brSlots_0_sharing = _RANDOM[6'h5][20]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_brSlots_0_valid = _RANDOM[6'h5][21]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_tailSlot_offset = _RANDOM[6'h5][25:22]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_tailSlot_lower = + {_RANDOM[6'h5][31:26], _RANDOM[6'h6][13:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_tailSlot_tarStat = _RANDOM[6'h6][15:14]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_tailSlot_sharing = _RANDOM[6'h6][16]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_tailSlot_valid = _RANDOM[6'h6][17]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_pftAddr = _RANDOM[6'h6][21:18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_carry = _RANDOM[6'h6][22]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_isCall = _RANDOM[6'h6][23]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_isRet = _RANDOM[6'h6][24]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_isJalr = _RANDOM[6'h6][25]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_last_may_be_rvi_call = _RANDOM[6'h6][26]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_always_taken_0 = _RANDOM[6'h6][27]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_entry_always_taken_1 = _RANDOM[6'h6][28]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_2_tag = {_RANDOM[6'h6][31:29], _RANDOM[6'h7][16:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_valid = _RANDOM[6'h7][17]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_brSlots_0_offset = _RANDOM[6'h7][21:18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_brSlots_0_lower = + {_RANDOM[6'h7][31:22], _RANDOM[6'h8][1:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_brSlots_0_tarStat = _RANDOM[6'h8][3:2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_brSlots_0_sharing = _RANDOM[6'h8][4]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_brSlots_0_valid = _RANDOM[6'h8][5]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_tailSlot_offset = _RANDOM[6'h8][9:6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_tailSlot_lower = _RANDOM[6'h8][29:10]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_tailSlot_tarStat = _RANDOM[6'h8][31:30]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_tailSlot_sharing = _RANDOM[6'h9][0]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_tailSlot_valid = _RANDOM[6'h9][1]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_pftAddr = _RANDOM[6'h9][5:2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_carry = _RANDOM[6'h9][6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_isCall = _RANDOM[6'h9][7]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_isRet = _RANDOM[6'h9][8]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_isJalr = _RANDOM[6'h9][9]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_last_may_be_rvi_call = _RANDOM[6'h9][10]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_always_taken_0 = _RANDOM[6'h9][11]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_entry_always_taken_1 = _RANDOM[6'h9][12]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + pred_rdata_hold_data_3_tag = {_RANDOM[6'h9][31:13], _RANDOM[6'hA][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, utility/src/main/scala/utility/Hold.scala:24:82 + req_tag = _RANDOM[6'hA][20:1]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :324:28, utility/src/main/scala/utility/Hold.scala:24:82 + req_idx = _RANDOM[6'hA][29:21]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :325:28, utility/src/main/scala/utility/Hold.scala:24:82 + u_req_tag = {_RANDOM[6'hA][31:30], _RANDOM[6'hB][17:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, utility/src/main/scala/utility/Hold.scala:24:82 + u_total_hits_REG = _RANDOM[6'hB][18]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, :338:96 + u_total_hits_REG_1 = _RANDOM[6'hB][19]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, :338:96 + u_total_hits_REG_2 = _RANDOM[6'hB][20]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, :338:96 + u_total_hits_REG_3 = _RANDOM[6'hB][21]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30, :338:96 + state_vec_0 = _RANDOM[6'hB][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30 + state_vec_1 = _RANDOM[6'hB][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30 + state_vec_2 = {_RANDOM[6'hB][31], _RANDOM[6'hC][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :327:30 + state_vec_3 = _RANDOM[6'hC][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_4 = _RANDOM[6'hC][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_5 = _RANDOM[6'hC][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_6 = _RANDOM[6'hC][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_7 = _RANDOM[6'hC][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_8 = _RANDOM[6'hC][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_9 = _RANDOM[6'hC][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_10 = _RANDOM[6'hC][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_11 = _RANDOM[6'hC][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_12 = _RANDOM[6'hC][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_13 = _RANDOM[6'hD][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_14 = _RANDOM[6'hD][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_15 = _RANDOM[6'hD][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_16 = _RANDOM[6'hD][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_17 = _RANDOM[6'hD][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_18 = _RANDOM[6'hD][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_19 = _RANDOM[6'hD][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_20 = _RANDOM[6'hD][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_21 = _RANDOM[6'hD][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_22 = _RANDOM[6'hD][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_23 = {_RANDOM[6'hD][31:30], _RANDOM[6'hE][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_24 = _RANDOM[6'hE][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_25 = _RANDOM[6'hE][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_26 = _RANDOM[6'hE][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_27 = _RANDOM[6'hE][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_28 = _RANDOM[6'hE][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_29 = _RANDOM[6'hE][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_30 = _RANDOM[6'hE][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_31 = _RANDOM[6'hE][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_32 = _RANDOM[6'hE][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_33 = _RANDOM[6'hE][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_34 = {_RANDOM[6'hE][31], _RANDOM[6'hF][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_35 = _RANDOM[6'hF][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_36 = _RANDOM[6'hF][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_37 = _RANDOM[6'hF][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_38 = _RANDOM[6'hF][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_39 = _RANDOM[6'hF][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_40 = _RANDOM[6'hF][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_41 = _RANDOM[6'hF][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_42 = _RANDOM[6'hF][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_43 = _RANDOM[6'hF][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_44 = _RANDOM[6'hF][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_45 = _RANDOM[6'h10][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_46 = _RANDOM[6'h10][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_47 = _RANDOM[6'h10][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_48 = _RANDOM[6'h10][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_49 = _RANDOM[6'h10][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_50 = _RANDOM[6'h10][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_51 = _RANDOM[6'h10][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_52 = _RANDOM[6'h10][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_53 = _RANDOM[6'h10][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_54 = _RANDOM[6'h10][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_55 = {_RANDOM[6'h10][31:30], _RANDOM[6'h11][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_56 = _RANDOM[6'h11][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_57 = _RANDOM[6'h11][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_58 = _RANDOM[6'h11][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_59 = _RANDOM[6'h11][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_60 = _RANDOM[6'h11][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_61 = _RANDOM[6'h11][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_62 = _RANDOM[6'h11][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_63 = _RANDOM[6'h11][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_64 = _RANDOM[6'h11][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_65 = _RANDOM[6'h11][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_66 = {_RANDOM[6'h11][31], _RANDOM[6'h12][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_67 = _RANDOM[6'h12][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_68 = _RANDOM[6'h12][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_69 = _RANDOM[6'h12][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_70 = _RANDOM[6'h12][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_71 = _RANDOM[6'h12][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_72 = _RANDOM[6'h12][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_73 = _RANDOM[6'h12][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_74 = _RANDOM[6'h12][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_75 = _RANDOM[6'h12][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_76 = _RANDOM[6'h12][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_77 = _RANDOM[6'h13][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_78 = _RANDOM[6'h13][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_79 = _RANDOM[6'h13][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_80 = _RANDOM[6'h13][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_81 = _RANDOM[6'h13][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_82 = _RANDOM[6'h13][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_83 = _RANDOM[6'h13][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_84 = _RANDOM[6'h13][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_85 = _RANDOM[6'h13][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_86 = _RANDOM[6'h13][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_87 = {_RANDOM[6'h13][31:30], _RANDOM[6'h14][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_88 = _RANDOM[6'h14][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_89 = _RANDOM[6'h14][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_90 = _RANDOM[6'h14][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_91 = _RANDOM[6'h14][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_92 = _RANDOM[6'h14][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_93 = _RANDOM[6'h14][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_94 = _RANDOM[6'h14][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_95 = _RANDOM[6'h14][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_96 = _RANDOM[6'h14][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_97 = _RANDOM[6'h14][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_98 = {_RANDOM[6'h14][31], _RANDOM[6'h15][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_99 = _RANDOM[6'h15][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_100 = _RANDOM[6'h15][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_101 = _RANDOM[6'h15][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_102 = _RANDOM[6'h15][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_103 = _RANDOM[6'h15][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_104 = _RANDOM[6'h15][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_105 = _RANDOM[6'h15][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_106 = _RANDOM[6'h15][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_107 = _RANDOM[6'h15][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_108 = _RANDOM[6'h15][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_109 = _RANDOM[6'h16][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_110 = _RANDOM[6'h16][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_111 = _RANDOM[6'h16][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_112 = _RANDOM[6'h16][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_113 = _RANDOM[6'h16][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_114 = _RANDOM[6'h16][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_115 = _RANDOM[6'h16][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_116 = _RANDOM[6'h16][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_117 = _RANDOM[6'h16][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_118 = _RANDOM[6'h16][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_119 = {_RANDOM[6'h16][31:30], _RANDOM[6'h17][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_120 = _RANDOM[6'h17][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_121 = _RANDOM[6'h17][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_122 = _RANDOM[6'h17][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_123 = _RANDOM[6'h17][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_124 = _RANDOM[6'h17][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_125 = _RANDOM[6'h17][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_126 = _RANDOM[6'h17][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_127 = _RANDOM[6'h17][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_128 = _RANDOM[6'h17][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_129 = _RANDOM[6'h17][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_130 = {_RANDOM[6'h17][31], _RANDOM[6'h18][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_131 = _RANDOM[6'h18][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_132 = _RANDOM[6'h18][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_133 = _RANDOM[6'h18][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_134 = _RANDOM[6'h18][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_135 = _RANDOM[6'h18][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_136 = _RANDOM[6'h18][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_137 = _RANDOM[6'h18][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_138 = _RANDOM[6'h18][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_139 = _RANDOM[6'h18][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_140 = _RANDOM[6'h18][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_141 = _RANDOM[6'h19][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_142 = _RANDOM[6'h19][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_143 = _RANDOM[6'h19][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_144 = _RANDOM[6'h19][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_145 = _RANDOM[6'h19][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_146 = _RANDOM[6'h19][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_147 = _RANDOM[6'h19][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_148 = _RANDOM[6'h19][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_149 = _RANDOM[6'h19][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_150 = _RANDOM[6'h19][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_151 = {_RANDOM[6'h19][31:30], _RANDOM[6'h1A][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_152 = _RANDOM[6'h1A][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_153 = _RANDOM[6'h1A][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_154 = _RANDOM[6'h1A][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_155 = _RANDOM[6'h1A][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_156 = _RANDOM[6'h1A][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_157 = _RANDOM[6'h1A][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_158 = _RANDOM[6'h1A][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_159 = _RANDOM[6'h1A][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_160 = _RANDOM[6'h1A][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_161 = _RANDOM[6'h1A][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_162 = {_RANDOM[6'h1A][31], _RANDOM[6'h1B][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_163 = _RANDOM[6'h1B][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_164 = _RANDOM[6'h1B][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_165 = _RANDOM[6'h1B][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_166 = _RANDOM[6'h1B][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_167 = _RANDOM[6'h1B][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_168 = _RANDOM[6'h1B][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_169 = _RANDOM[6'h1B][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_170 = _RANDOM[6'h1B][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_171 = _RANDOM[6'h1B][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_172 = _RANDOM[6'h1B][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_173 = _RANDOM[6'h1C][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_174 = _RANDOM[6'h1C][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_175 = _RANDOM[6'h1C][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_176 = _RANDOM[6'h1C][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_177 = _RANDOM[6'h1C][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_178 = _RANDOM[6'h1C][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_179 = _RANDOM[6'h1C][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_180 = _RANDOM[6'h1C][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_181 = _RANDOM[6'h1C][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_182 = _RANDOM[6'h1C][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_183 = {_RANDOM[6'h1C][31:30], _RANDOM[6'h1D][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_184 = _RANDOM[6'h1D][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_185 = _RANDOM[6'h1D][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_186 = _RANDOM[6'h1D][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_187 = _RANDOM[6'h1D][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_188 = _RANDOM[6'h1D][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_189 = _RANDOM[6'h1D][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_190 = _RANDOM[6'h1D][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_191 = _RANDOM[6'h1D][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_192 = _RANDOM[6'h1D][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_193 = _RANDOM[6'h1D][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_194 = {_RANDOM[6'h1D][31], _RANDOM[6'h1E][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_195 = _RANDOM[6'h1E][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_196 = _RANDOM[6'h1E][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_197 = _RANDOM[6'h1E][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_198 = _RANDOM[6'h1E][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_199 = _RANDOM[6'h1E][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_200 = _RANDOM[6'h1E][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_201 = _RANDOM[6'h1E][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_202 = _RANDOM[6'h1E][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_203 = _RANDOM[6'h1E][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_204 = _RANDOM[6'h1E][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_205 = _RANDOM[6'h1F][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_206 = _RANDOM[6'h1F][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_207 = _RANDOM[6'h1F][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_208 = _RANDOM[6'h1F][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_209 = _RANDOM[6'h1F][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_210 = _RANDOM[6'h1F][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_211 = _RANDOM[6'h1F][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_212 = _RANDOM[6'h1F][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_213 = _RANDOM[6'h1F][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_214 = _RANDOM[6'h1F][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_215 = {_RANDOM[6'h1F][31:30], _RANDOM[6'h20][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_216 = _RANDOM[6'h20][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_217 = _RANDOM[6'h20][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_218 = _RANDOM[6'h20][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_219 = _RANDOM[6'h20][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_220 = _RANDOM[6'h20][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_221 = _RANDOM[6'h20][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_222 = _RANDOM[6'h20][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_223 = _RANDOM[6'h20][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_224 = _RANDOM[6'h20][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_225 = _RANDOM[6'h20][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_226 = {_RANDOM[6'h20][31], _RANDOM[6'h21][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_227 = _RANDOM[6'h21][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_228 = _RANDOM[6'h21][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_229 = _RANDOM[6'h21][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_230 = _RANDOM[6'h21][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_231 = _RANDOM[6'h21][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_232 = _RANDOM[6'h21][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_233 = _RANDOM[6'h21][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_234 = _RANDOM[6'h21][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_235 = _RANDOM[6'h21][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_236 = _RANDOM[6'h21][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_237 = _RANDOM[6'h22][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_238 = _RANDOM[6'h22][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_239 = _RANDOM[6'h22][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_240 = _RANDOM[6'h22][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_241 = _RANDOM[6'h22][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_242 = _RANDOM[6'h22][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_243 = _RANDOM[6'h22][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_244 = _RANDOM[6'h22][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_245 = _RANDOM[6'h22][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_246 = _RANDOM[6'h22][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_247 = {_RANDOM[6'h22][31:30], _RANDOM[6'h23][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_248 = _RANDOM[6'h23][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_249 = _RANDOM[6'h23][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_250 = _RANDOM[6'h23][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_251 = _RANDOM[6'h23][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_252 = _RANDOM[6'h23][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_253 = _RANDOM[6'h23][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_254 = _RANDOM[6'h23][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_255 = _RANDOM[6'h23][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_256 = _RANDOM[6'h23][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_257 = _RANDOM[6'h23][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_258 = {_RANDOM[6'h23][31], _RANDOM[6'h24][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_259 = _RANDOM[6'h24][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_260 = _RANDOM[6'h24][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_261 = _RANDOM[6'h24][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_262 = _RANDOM[6'h24][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_263 = _RANDOM[6'h24][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_264 = _RANDOM[6'h24][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_265 = _RANDOM[6'h24][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_266 = _RANDOM[6'h24][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_267 = _RANDOM[6'h24][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_268 = _RANDOM[6'h24][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_269 = _RANDOM[6'h25][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_270 = _RANDOM[6'h25][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_271 = _RANDOM[6'h25][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_272 = _RANDOM[6'h25][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_273 = _RANDOM[6'h25][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_274 = _RANDOM[6'h25][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_275 = _RANDOM[6'h25][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_276 = _RANDOM[6'h25][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_277 = _RANDOM[6'h25][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_278 = _RANDOM[6'h25][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_279 = {_RANDOM[6'h25][31:30], _RANDOM[6'h26][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_280 = _RANDOM[6'h26][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_281 = _RANDOM[6'h26][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_282 = _RANDOM[6'h26][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_283 = _RANDOM[6'h26][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_284 = _RANDOM[6'h26][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_285 = _RANDOM[6'h26][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_286 = _RANDOM[6'h26][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_287 = _RANDOM[6'h26][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_288 = _RANDOM[6'h26][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_289 = _RANDOM[6'h26][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_290 = {_RANDOM[6'h26][31], _RANDOM[6'h27][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_291 = _RANDOM[6'h27][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_292 = _RANDOM[6'h27][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_293 = _RANDOM[6'h27][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_294 = _RANDOM[6'h27][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_295 = _RANDOM[6'h27][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_296 = _RANDOM[6'h27][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_297 = _RANDOM[6'h27][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_298 = _RANDOM[6'h27][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_299 = _RANDOM[6'h27][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_300 = _RANDOM[6'h27][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_301 = _RANDOM[6'h28][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_302 = _RANDOM[6'h28][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_303 = _RANDOM[6'h28][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_304 = _RANDOM[6'h28][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_305 = _RANDOM[6'h28][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_306 = _RANDOM[6'h28][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_307 = _RANDOM[6'h28][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_308 = _RANDOM[6'h28][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_309 = _RANDOM[6'h28][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_310 = _RANDOM[6'h28][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_311 = {_RANDOM[6'h28][31:30], _RANDOM[6'h29][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_312 = _RANDOM[6'h29][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_313 = _RANDOM[6'h29][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_314 = _RANDOM[6'h29][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_315 = _RANDOM[6'h29][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_316 = _RANDOM[6'h29][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_317 = _RANDOM[6'h29][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_318 = _RANDOM[6'h29][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_319 = _RANDOM[6'h29][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_320 = _RANDOM[6'h29][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_321 = _RANDOM[6'h29][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_322 = {_RANDOM[6'h29][31], _RANDOM[6'h2A][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_323 = _RANDOM[6'h2A][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_324 = _RANDOM[6'h2A][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_325 = _RANDOM[6'h2A][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_326 = _RANDOM[6'h2A][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_327 = _RANDOM[6'h2A][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_328 = _RANDOM[6'h2A][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_329 = _RANDOM[6'h2A][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_330 = _RANDOM[6'h2A][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_331 = _RANDOM[6'h2A][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_332 = _RANDOM[6'h2A][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_333 = _RANDOM[6'h2B][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_334 = _RANDOM[6'h2B][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_335 = _RANDOM[6'h2B][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_336 = _RANDOM[6'h2B][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_337 = _RANDOM[6'h2B][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_338 = _RANDOM[6'h2B][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_339 = _RANDOM[6'h2B][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_340 = _RANDOM[6'h2B][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_341 = _RANDOM[6'h2B][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_342 = _RANDOM[6'h2B][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_343 = {_RANDOM[6'h2B][31:30], _RANDOM[6'h2C][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_344 = _RANDOM[6'h2C][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_345 = _RANDOM[6'h2C][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_346 = _RANDOM[6'h2C][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_347 = _RANDOM[6'h2C][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_348 = _RANDOM[6'h2C][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_349 = _RANDOM[6'h2C][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_350 = _RANDOM[6'h2C][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_351 = _RANDOM[6'h2C][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_352 = _RANDOM[6'h2C][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_353 = _RANDOM[6'h2C][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_354 = {_RANDOM[6'h2C][31], _RANDOM[6'h2D][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_355 = _RANDOM[6'h2D][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_356 = _RANDOM[6'h2D][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_357 = _RANDOM[6'h2D][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_358 = _RANDOM[6'h2D][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_359 = _RANDOM[6'h2D][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_360 = _RANDOM[6'h2D][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_361 = _RANDOM[6'h2D][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_362 = _RANDOM[6'h2D][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_363 = _RANDOM[6'h2D][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_364 = _RANDOM[6'h2D][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_365 = _RANDOM[6'h2E][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_366 = _RANDOM[6'h2E][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_367 = _RANDOM[6'h2E][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_368 = _RANDOM[6'h2E][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_369 = _RANDOM[6'h2E][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_370 = _RANDOM[6'h2E][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_371 = _RANDOM[6'h2E][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_372 = _RANDOM[6'h2E][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_373 = _RANDOM[6'h2E][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_374 = _RANDOM[6'h2E][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_375 = {_RANDOM[6'h2E][31:30], _RANDOM[6'h2F][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_376 = _RANDOM[6'h2F][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_377 = _RANDOM[6'h2F][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_378 = _RANDOM[6'h2F][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_379 = _RANDOM[6'h2F][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_380 = _RANDOM[6'h2F][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_381 = _RANDOM[6'h2F][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_382 = _RANDOM[6'h2F][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_383 = _RANDOM[6'h2F][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_384 = _RANDOM[6'h2F][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_385 = _RANDOM[6'h2F][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_386 = {_RANDOM[6'h2F][31], _RANDOM[6'h30][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_387 = _RANDOM[6'h30][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_388 = _RANDOM[6'h30][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_389 = _RANDOM[6'h30][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_390 = _RANDOM[6'h30][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_391 = _RANDOM[6'h30][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_392 = _RANDOM[6'h30][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_393 = _RANDOM[6'h30][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_394 = _RANDOM[6'h30][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_395 = _RANDOM[6'h30][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_396 = _RANDOM[6'h30][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_397 = _RANDOM[6'h31][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_398 = _RANDOM[6'h31][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_399 = _RANDOM[6'h31][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_400 = _RANDOM[6'h31][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_401 = _RANDOM[6'h31][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_402 = _RANDOM[6'h31][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_403 = _RANDOM[6'h31][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_404 = _RANDOM[6'h31][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_405 = _RANDOM[6'h31][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_406 = _RANDOM[6'h31][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_407 = {_RANDOM[6'h31][31:30], _RANDOM[6'h32][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_408 = _RANDOM[6'h32][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_409 = _RANDOM[6'h32][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_410 = _RANDOM[6'h32][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_411 = _RANDOM[6'h32][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_412 = _RANDOM[6'h32][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_413 = _RANDOM[6'h32][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_414 = _RANDOM[6'h32][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_415 = _RANDOM[6'h32][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_416 = _RANDOM[6'h32][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_417 = _RANDOM[6'h32][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_418 = {_RANDOM[6'h32][31], _RANDOM[6'h33][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_419 = _RANDOM[6'h33][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_420 = _RANDOM[6'h33][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_421 = _RANDOM[6'h33][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_422 = _RANDOM[6'h33][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_423 = _RANDOM[6'h33][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_424 = _RANDOM[6'h33][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_425 = _RANDOM[6'h33][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_426 = _RANDOM[6'h33][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_427 = _RANDOM[6'h33][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_428 = _RANDOM[6'h33][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_429 = _RANDOM[6'h34][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_430 = _RANDOM[6'h34][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_431 = _RANDOM[6'h34][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_432 = _RANDOM[6'h34][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_433 = _RANDOM[6'h34][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_434 = _RANDOM[6'h34][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_435 = _RANDOM[6'h34][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_436 = _RANDOM[6'h34][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_437 = _RANDOM[6'h34][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_438 = _RANDOM[6'h34][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_439 = {_RANDOM[6'h34][31:30], _RANDOM[6'h35][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_440 = _RANDOM[6'h35][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_441 = _RANDOM[6'h35][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_442 = _RANDOM[6'h35][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_443 = _RANDOM[6'h35][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_444 = _RANDOM[6'h35][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_445 = _RANDOM[6'h35][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_446 = _RANDOM[6'h35][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_447 = _RANDOM[6'h35][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_448 = _RANDOM[6'h35][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_449 = _RANDOM[6'h35][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_450 = {_RANDOM[6'h35][31], _RANDOM[6'h36][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_451 = _RANDOM[6'h36][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_452 = _RANDOM[6'h36][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_453 = _RANDOM[6'h36][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_454 = _RANDOM[6'h36][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_455 = _RANDOM[6'h36][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_456 = _RANDOM[6'h36][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_457 = _RANDOM[6'h36][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_458 = _RANDOM[6'h36][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_459 = _RANDOM[6'h36][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_460 = _RANDOM[6'h36][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_461 = _RANDOM[6'h37][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_462 = _RANDOM[6'h37][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_463 = _RANDOM[6'h37][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_464 = _RANDOM[6'h37][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_465 = _RANDOM[6'h37][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_466 = _RANDOM[6'h37][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_467 = _RANDOM[6'h37][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_468 = _RANDOM[6'h37][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_469 = _RANDOM[6'h37][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_470 = _RANDOM[6'h37][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_471 = {_RANDOM[6'h37][31:30], _RANDOM[6'h38][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_472 = _RANDOM[6'h38][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_473 = _RANDOM[6'h38][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_474 = _RANDOM[6'h38][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_475 = _RANDOM[6'h38][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_476 = _RANDOM[6'h38][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_477 = _RANDOM[6'h38][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_478 = _RANDOM[6'h38][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_479 = _RANDOM[6'h38][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_480 = _RANDOM[6'h38][27:25]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_481 = _RANDOM[6'h38][30:28]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_482 = {_RANDOM[6'h38][31], _RANDOM[6'h39][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_483 = _RANDOM[6'h39][4:2]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_484 = _RANDOM[6'h39][7:5]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_485 = _RANDOM[6'h39][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_486 = _RANDOM[6'h39][13:11]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_487 = _RANDOM[6'h39][16:14]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_488 = _RANDOM[6'h39][19:17]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_489 = _RANDOM[6'h39][22:20]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_490 = _RANDOM[6'h39][25:23]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_491 = _RANDOM[6'h39][28:26]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_492 = _RANDOM[6'h39][31:29]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_493 = _RANDOM[6'h3A][2:0]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_494 = _RANDOM[6'h3A][5:3]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_495 = _RANDOM[6'h3A][8:6]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_496 = _RANDOM[6'h3A][11:9]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_497 = _RANDOM[6'h3A][14:12]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_498 = _RANDOM[6'h3A][17:15]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_499 = _RANDOM[6'h3A][20:18]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_500 = _RANDOM[6'h3A][23:21]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_501 = _RANDOM[6'h3A][26:24]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_502 = _RANDOM[6'h3A][29:27]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_503 = {_RANDOM[6'h3A][31:30], _RANDOM[6'h3B][0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_504 = _RANDOM[6'h3B][3:1]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_505 = _RANDOM[6'h3B][6:4]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_506 = _RANDOM[6'h3B][9:7]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_507 = _RANDOM[6'h3B][12:10]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_508 = _RANDOM[6'h3B][15:13]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_509 = _RANDOM[6'h3B][18:16]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_510 = _RANDOM[6'h3B][21:19]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_511 = _RANDOM[6'h3B][24:22]; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + touch_set_0_REG = {_RANDOM[6'h3B][31:25], _RANDOM[6'h3C][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:374:17, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60 + touch_way_0_valid_REG = _RANDOM[6'h3C][2]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :369:53 + touch_way_0_bits_REG = _RANDOM[6'h3C][4:3]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :370:70 + allocWriteWay_REG_0 = _RANDOM[6'h3C][5]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :401:41 + allocWriteWay_REG_1 = _RANDOM[6'h3C][6]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :401:41 + allocWriteWay_REG_2 = _RANDOM[6'h3C][7]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :401:41 + allocWriteWay_REG_3 = _RANDOM[6'h3C][8]; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :368:60, :401:41 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + state_vec_0 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_1 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_2 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_3 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_4 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_5 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_6 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_7 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_8 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_9 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_10 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_11 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_12 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_13 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_14 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_15 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_16 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_17 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_18 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_19 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_20 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_21 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_22 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_23 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_24 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_25 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_26 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_27 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_28 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_29 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_30 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_31 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_32 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_33 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_34 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_35 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_36 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_37 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_38 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_39 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_40 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_41 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_42 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_43 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_44 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_45 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_46 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_47 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_48 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_49 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_50 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_51 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_52 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_53 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_54 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_55 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_56 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_57 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_58 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_59 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_60 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_61 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_62 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_63 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_64 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_65 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_66 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_67 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_68 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_69 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_70 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_71 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_72 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_73 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_74 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_75 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_76 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_77 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_78 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_79 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_80 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_81 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_82 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_83 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_84 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_85 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_86 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_87 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_88 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_89 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_90 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_91 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_92 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_93 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_94 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_95 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_96 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_97 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_98 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_99 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_100 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_101 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_102 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_103 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_104 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_105 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_106 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_107 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_108 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_109 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_110 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_111 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_112 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_113 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_114 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_115 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_116 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_117 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_118 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_119 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_120 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_121 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_122 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_123 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_124 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_125 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_126 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_127 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_128 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_129 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_130 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_131 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_132 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_133 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_134 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_135 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_136 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_137 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_138 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_139 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_140 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_141 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_142 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_143 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_144 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_145 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_146 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_147 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_148 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_149 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_150 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_151 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_152 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_153 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_154 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_155 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_156 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_157 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_158 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_159 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_160 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_161 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_162 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_163 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_164 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_165 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_166 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_167 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_168 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_169 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_170 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_171 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_172 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_173 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_174 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_175 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_176 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_177 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_178 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_179 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_180 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_181 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_182 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_183 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_184 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_185 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_186 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_187 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_188 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_189 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_190 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_191 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_192 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_193 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_194 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_195 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_196 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_197 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_198 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_199 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_200 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_201 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_202 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_203 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_204 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_205 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_206 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_207 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_208 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_209 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_210 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_211 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_212 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_213 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_214 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_215 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_216 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_217 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_218 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_219 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_220 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_221 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_222 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_223 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_224 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_225 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_226 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_227 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_228 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_229 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_230 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_231 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_232 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_233 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_234 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_235 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_236 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_237 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_238 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_239 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_240 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_241 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_242 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_243 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_244 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_245 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_246 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_247 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_248 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_249 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_250 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_251 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_252 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_253 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_254 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_255 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_256 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_257 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_258 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_259 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_260 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_261 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_262 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_263 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_264 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_265 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_266 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_267 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_268 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_269 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_270 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_271 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_272 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_273 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_274 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_275 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_276 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_277 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_278 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_279 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_280 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_281 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_282 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_283 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_284 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_285 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_286 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_287 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_288 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_289 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_290 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_291 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_292 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_293 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_294 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_295 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_296 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_297 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_298 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_299 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_300 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_301 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_302 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_303 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_304 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_305 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_306 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_307 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_308 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_309 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_310 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_311 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_312 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_313 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_314 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_315 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_316 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_317 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_318 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_319 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_320 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_321 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_322 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_323 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_324 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_325 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_326 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_327 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_328 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_329 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_330 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_331 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_332 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_333 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_334 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_335 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_336 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_337 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_338 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_339 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_340 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_341 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_342 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_343 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_344 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_345 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_346 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_347 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_348 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_349 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_350 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_351 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_352 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_353 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_354 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_355 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_356 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_357 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_358 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_359 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_360 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_361 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_362 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_363 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_364 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_365 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_366 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_367 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_368 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_369 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_370 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_371 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_372 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_373 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_374 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_375 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_376 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_377 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_378 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_379 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_380 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_381 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_382 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_383 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_384 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_385 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_386 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_387 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_388 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_389 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_390 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_391 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_392 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_393 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_394 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_395 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_396 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_397 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_398 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_399 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_400 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_401 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_402 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_403 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_404 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_405 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_406 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_407 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_408 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_409 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_410 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_411 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_412 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_413 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_414 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_415 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_416 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_417 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_418 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_419 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_420 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_421 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_422 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_423 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_424 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_425 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_426 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_427 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_428 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_429 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_430 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_431 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_432 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_433 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_434 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_435 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_436 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_437 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_438 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_439 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_440 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_441 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_442 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_443 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_444 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_445 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_446 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_447 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_448 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_449 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_450 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_451 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_452 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_453 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_454 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_455 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_456 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_457 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_458 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_459 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_460 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_461 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_462 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_463 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_464 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_465 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_466 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_467 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_468 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_469 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_470 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_471 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_472 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_473 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_474 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_475 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_476 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_477 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_478 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_479 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_480 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_481 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_482 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_483 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_484 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_485 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_486 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_487 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_488 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_489 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_490 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_491 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_492 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_493 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_494 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_495 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_496 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_497 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_498 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_499 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_500 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_501 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_502 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_503 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_504 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_505 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_506 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_507 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_508 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_509 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_510 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + state_vec_511 = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :374:17 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:290:9 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_9 ftb ( // src/main/scala/xiangshan/frontend/FTB.scala:312:21 + .clock (clock), + .reset (reset), + .io_r_req_ready (io_req_pc_ready), + .io_r_req_valid + (io_req_pc_valid | io_u_req_pc_valid), // src/main/scala/xiangshan/frontend/FTB.scala:316:43 + .io_r_req_bits_setIdx + (io_u_req_pc_valid ? io_u_req_pc_bits[9:1] : io_req_pc_bits[9:1]), // src/main/scala/xiangshan/frontend/FTB.scala:317:36, src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 + .io_r_resp_data_0_entry_valid (_ftb_io_r_resp_data_0_entry_valid), + .io_r_resp_data_0_entry_brSlots_0_offset + (_ftb_io_r_resp_data_0_entry_brSlots_0_offset), + .io_r_resp_data_0_entry_brSlots_0_lower + (_ftb_io_r_resp_data_0_entry_brSlots_0_lower), + .io_r_resp_data_0_entry_brSlots_0_tarStat + (_ftb_io_r_resp_data_0_entry_brSlots_0_tarStat), + .io_r_resp_data_0_entry_brSlots_0_sharing + (_ftb_io_r_resp_data_0_entry_brSlots_0_sharing), + .io_r_resp_data_0_entry_brSlots_0_valid + (_ftb_io_r_resp_data_0_entry_brSlots_0_valid), + .io_r_resp_data_0_entry_tailSlot_offset + (_ftb_io_r_resp_data_0_entry_tailSlot_offset), + .io_r_resp_data_0_entry_tailSlot_lower + (_ftb_io_r_resp_data_0_entry_tailSlot_lower), + .io_r_resp_data_0_entry_tailSlot_tarStat + (_ftb_io_r_resp_data_0_entry_tailSlot_tarStat), + .io_r_resp_data_0_entry_tailSlot_sharing + (_ftb_io_r_resp_data_0_entry_tailSlot_sharing), + .io_r_resp_data_0_entry_tailSlot_valid + (_ftb_io_r_resp_data_0_entry_tailSlot_valid), + .io_r_resp_data_0_entry_pftAddr + (_ftb_io_r_resp_data_0_entry_pftAddr), + .io_r_resp_data_0_entry_carry (_ftb_io_r_resp_data_0_entry_carry), + .io_r_resp_data_0_entry_isCall (_ftb_io_r_resp_data_0_entry_isCall), + .io_r_resp_data_0_entry_isRet (_ftb_io_r_resp_data_0_entry_isRet), + .io_r_resp_data_0_entry_isJalr (_ftb_io_r_resp_data_0_entry_isJalr), + .io_r_resp_data_0_entry_last_may_be_rvi_call + (_ftb_io_r_resp_data_0_entry_last_may_be_rvi_call), + .io_r_resp_data_0_entry_always_taken_0 + (_ftb_io_r_resp_data_0_entry_always_taken_0), + .io_r_resp_data_0_entry_always_taken_1 + (_ftb_io_r_resp_data_0_entry_always_taken_1), + .io_r_resp_data_0_tag (_ftb_io_r_resp_data_0_tag), + .io_r_resp_data_1_entry_valid (_ftb_io_r_resp_data_1_entry_valid), + .io_r_resp_data_1_entry_brSlots_0_offset + (_ftb_io_r_resp_data_1_entry_brSlots_0_offset), + .io_r_resp_data_1_entry_brSlots_0_lower + (_ftb_io_r_resp_data_1_entry_brSlots_0_lower), + .io_r_resp_data_1_entry_brSlots_0_tarStat + (_ftb_io_r_resp_data_1_entry_brSlots_0_tarStat), + .io_r_resp_data_1_entry_brSlots_0_sharing + (_ftb_io_r_resp_data_1_entry_brSlots_0_sharing), + .io_r_resp_data_1_entry_brSlots_0_valid + (_ftb_io_r_resp_data_1_entry_brSlots_0_valid), + .io_r_resp_data_1_entry_tailSlot_offset + (_ftb_io_r_resp_data_1_entry_tailSlot_offset), + .io_r_resp_data_1_entry_tailSlot_lower + (_ftb_io_r_resp_data_1_entry_tailSlot_lower), + .io_r_resp_data_1_entry_tailSlot_tarStat + (_ftb_io_r_resp_data_1_entry_tailSlot_tarStat), + .io_r_resp_data_1_entry_tailSlot_sharing + (_ftb_io_r_resp_data_1_entry_tailSlot_sharing), + .io_r_resp_data_1_entry_tailSlot_valid + (_ftb_io_r_resp_data_1_entry_tailSlot_valid), + .io_r_resp_data_1_entry_pftAddr + (_ftb_io_r_resp_data_1_entry_pftAddr), + .io_r_resp_data_1_entry_carry (_ftb_io_r_resp_data_1_entry_carry), + .io_r_resp_data_1_entry_isCall (_ftb_io_r_resp_data_1_entry_isCall), + .io_r_resp_data_1_entry_isRet (_ftb_io_r_resp_data_1_entry_isRet), + .io_r_resp_data_1_entry_isJalr (_ftb_io_r_resp_data_1_entry_isJalr), + .io_r_resp_data_1_entry_last_may_be_rvi_call + (_ftb_io_r_resp_data_1_entry_last_may_be_rvi_call), + .io_r_resp_data_1_entry_always_taken_0 + (_ftb_io_r_resp_data_1_entry_always_taken_0), + .io_r_resp_data_1_entry_always_taken_1 + (_ftb_io_r_resp_data_1_entry_always_taken_1), + .io_r_resp_data_1_tag (_ftb_io_r_resp_data_1_tag), + .io_r_resp_data_2_entry_valid (_ftb_io_r_resp_data_2_entry_valid), + .io_r_resp_data_2_entry_brSlots_0_offset + (_ftb_io_r_resp_data_2_entry_brSlots_0_offset), + .io_r_resp_data_2_entry_brSlots_0_lower + (_ftb_io_r_resp_data_2_entry_brSlots_0_lower), + .io_r_resp_data_2_entry_brSlots_0_tarStat + (_ftb_io_r_resp_data_2_entry_brSlots_0_tarStat), + .io_r_resp_data_2_entry_brSlots_0_sharing + (_ftb_io_r_resp_data_2_entry_brSlots_0_sharing), + .io_r_resp_data_2_entry_brSlots_0_valid + (_ftb_io_r_resp_data_2_entry_brSlots_0_valid), + .io_r_resp_data_2_entry_tailSlot_offset + (_ftb_io_r_resp_data_2_entry_tailSlot_offset), + .io_r_resp_data_2_entry_tailSlot_lower + (_ftb_io_r_resp_data_2_entry_tailSlot_lower), + .io_r_resp_data_2_entry_tailSlot_tarStat + (_ftb_io_r_resp_data_2_entry_tailSlot_tarStat), + .io_r_resp_data_2_entry_tailSlot_sharing + (_ftb_io_r_resp_data_2_entry_tailSlot_sharing), + .io_r_resp_data_2_entry_tailSlot_valid + (_ftb_io_r_resp_data_2_entry_tailSlot_valid), + .io_r_resp_data_2_entry_pftAddr + (_ftb_io_r_resp_data_2_entry_pftAddr), + .io_r_resp_data_2_entry_carry (_ftb_io_r_resp_data_2_entry_carry), + .io_r_resp_data_2_entry_isCall (_ftb_io_r_resp_data_2_entry_isCall), + .io_r_resp_data_2_entry_isRet (_ftb_io_r_resp_data_2_entry_isRet), + .io_r_resp_data_2_entry_isJalr (_ftb_io_r_resp_data_2_entry_isJalr), + .io_r_resp_data_2_entry_last_may_be_rvi_call + (_ftb_io_r_resp_data_2_entry_last_may_be_rvi_call), + .io_r_resp_data_2_entry_always_taken_0 + (_ftb_io_r_resp_data_2_entry_always_taken_0), + .io_r_resp_data_2_entry_always_taken_1 + (_ftb_io_r_resp_data_2_entry_always_taken_1), + .io_r_resp_data_2_tag (_ftb_io_r_resp_data_2_tag), + .io_r_resp_data_3_entry_valid (_ftb_io_r_resp_data_3_entry_valid), + .io_r_resp_data_3_entry_brSlots_0_offset + (_ftb_io_r_resp_data_3_entry_brSlots_0_offset), + .io_r_resp_data_3_entry_brSlots_0_lower + (_ftb_io_r_resp_data_3_entry_brSlots_0_lower), + .io_r_resp_data_3_entry_brSlots_0_tarStat + (_ftb_io_r_resp_data_3_entry_brSlots_0_tarStat), + .io_r_resp_data_3_entry_brSlots_0_sharing + (_ftb_io_r_resp_data_3_entry_brSlots_0_sharing), + .io_r_resp_data_3_entry_brSlots_0_valid + (_ftb_io_r_resp_data_3_entry_brSlots_0_valid), + .io_r_resp_data_3_entry_tailSlot_offset + (_ftb_io_r_resp_data_3_entry_tailSlot_offset), + .io_r_resp_data_3_entry_tailSlot_lower + (_ftb_io_r_resp_data_3_entry_tailSlot_lower), + .io_r_resp_data_3_entry_tailSlot_tarStat + (_ftb_io_r_resp_data_3_entry_tailSlot_tarStat), + .io_r_resp_data_3_entry_tailSlot_sharing + (_ftb_io_r_resp_data_3_entry_tailSlot_sharing), + .io_r_resp_data_3_entry_tailSlot_valid + (_ftb_io_r_resp_data_3_entry_tailSlot_valid), + .io_r_resp_data_3_entry_pftAddr + (_ftb_io_r_resp_data_3_entry_pftAddr), + .io_r_resp_data_3_entry_carry (_ftb_io_r_resp_data_3_entry_carry), + .io_r_resp_data_3_entry_isCall (_ftb_io_r_resp_data_3_entry_isCall), + .io_r_resp_data_3_entry_isRet (_ftb_io_r_resp_data_3_entry_isRet), + .io_r_resp_data_3_entry_isJalr (_ftb_io_r_resp_data_3_entry_isJalr), + .io_r_resp_data_3_entry_last_may_be_rvi_call + (_ftb_io_r_resp_data_3_entry_last_may_be_rvi_call), + .io_r_resp_data_3_entry_always_taken_0 + (_ftb_io_r_resp_data_3_entry_always_taken_0), + .io_r_resp_data_3_entry_always_taken_1 + (_ftb_io_r_resp_data_3_entry_always_taken_1), + .io_r_resp_data_3_tag (_ftb_io_r_resp_data_3_tag), + .io_w_req_valid (io_update_write_data_valid), + .io_w_req_bits_setIdx (io_update_pc[9:1]), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 + .io_w_req_bits_data_0_entry_valid + (io_update_write_data_bits_entry_valid), + .io_w_req_bits_data_0_entry_brSlots_0_offset + (io_update_write_data_bits_entry_brSlots_0_offset), + .io_w_req_bits_data_0_entry_brSlots_0_lower + (io_update_write_data_bits_entry_brSlots_0_lower), + .io_w_req_bits_data_0_entry_brSlots_0_tarStat + (io_update_write_data_bits_entry_brSlots_0_tarStat), + .io_w_req_bits_data_0_entry_brSlots_0_sharing + (io_update_write_data_bits_entry_brSlots_0_sharing), + .io_w_req_bits_data_0_entry_brSlots_0_valid + (io_update_write_data_bits_entry_brSlots_0_valid), + .io_w_req_bits_data_0_entry_tailSlot_offset + (io_update_write_data_bits_entry_tailSlot_offset), + .io_w_req_bits_data_0_entry_tailSlot_lower + (io_update_write_data_bits_entry_tailSlot_lower), + .io_w_req_bits_data_0_entry_tailSlot_tarStat + (io_update_write_data_bits_entry_tailSlot_tarStat), + .io_w_req_bits_data_0_entry_tailSlot_sharing + (io_update_write_data_bits_entry_tailSlot_sharing), + .io_w_req_bits_data_0_entry_tailSlot_valid + (io_update_write_data_bits_entry_tailSlot_valid), + .io_w_req_bits_data_0_entry_pftAddr + (io_update_write_data_bits_entry_pftAddr), + .io_w_req_bits_data_0_entry_carry + (io_update_write_data_bits_entry_carry), + .io_w_req_bits_data_0_entry_isCall + (io_update_write_data_bits_entry_isCall), + .io_w_req_bits_data_0_entry_isRet + (io_update_write_data_bits_entry_isRet), + .io_w_req_bits_data_0_entry_isJalr + (io_update_write_data_bits_entry_isJalr), + .io_w_req_bits_data_0_entry_last_may_be_rvi_call + (io_update_write_data_bits_entry_last_may_be_rvi_call), + .io_w_req_bits_data_0_entry_always_taken_0 + (io_update_write_data_bits_entry_always_taken_0), + .io_w_req_bits_data_0_entry_always_taken_1 + (io_update_write_data_bits_entry_always_taken_1), + .io_w_req_bits_data_0_tag (io_update_write_data_bits_tag), + .io_w_req_bits_data_1_entry_valid + (io_update_write_data_bits_entry_valid), + .io_w_req_bits_data_1_entry_brSlots_0_offset + (io_update_write_data_bits_entry_brSlots_0_offset), + .io_w_req_bits_data_1_entry_brSlots_0_lower + (io_update_write_data_bits_entry_brSlots_0_lower), + .io_w_req_bits_data_1_entry_brSlots_0_tarStat + (io_update_write_data_bits_entry_brSlots_0_tarStat), + .io_w_req_bits_data_1_entry_brSlots_0_sharing + (io_update_write_data_bits_entry_brSlots_0_sharing), + .io_w_req_bits_data_1_entry_brSlots_0_valid + (io_update_write_data_bits_entry_brSlots_0_valid), + .io_w_req_bits_data_1_entry_tailSlot_offset + (io_update_write_data_bits_entry_tailSlot_offset), + .io_w_req_bits_data_1_entry_tailSlot_lower + (io_update_write_data_bits_entry_tailSlot_lower), + .io_w_req_bits_data_1_entry_tailSlot_tarStat + (io_update_write_data_bits_entry_tailSlot_tarStat), + .io_w_req_bits_data_1_entry_tailSlot_sharing + (io_update_write_data_bits_entry_tailSlot_sharing), + .io_w_req_bits_data_1_entry_tailSlot_valid + (io_update_write_data_bits_entry_tailSlot_valid), + .io_w_req_bits_data_1_entry_pftAddr + (io_update_write_data_bits_entry_pftAddr), + .io_w_req_bits_data_1_entry_carry + (io_update_write_data_bits_entry_carry), + .io_w_req_bits_data_1_entry_isCall + (io_update_write_data_bits_entry_isCall), + .io_w_req_bits_data_1_entry_isRet + (io_update_write_data_bits_entry_isRet), + .io_w_req_bits_data_1_entry_isJalr + (io_update_write_data_bits_entry_isJalr), + .io_w_req_bits_data_1_entry_last_may_be_rvi_call + (io_update_write_data_bits_entry_last_may_be_rvi_call), + .io_w_req_bits_data_1_entry_always_taken_0 + (io_update_write_data_bits_entry_always_taken_0), + .io_w_req_bits_data_1_entry_always_taken_1 + (io_update_write_data_bits_entry_always_taken_1), + .io_w_req_bits_data_1_tag (io_update_write_data_bits_tag), + .io_w_req_bits_data_2_entry_valid + (io_update_write_data_bits_entry_valid), + .io_w_req_bits_data_2_entry_brSlots_0_offset + (io_update_write_data_bits_entry_brSlots_0_offset), + .io_w_req_bits_data_2_entry_brSlots_0_lower + (io_update_write_data_bits_entry_brSlots_0_lower), + .io_w_req_bits_data_2_entry_brSlots_0_tarStat + (io_update_write_data_bits_entry_brSlots_0_tarStat), + .io_w_req_bits_data_2_entry_brSlots_0_sharing + (io_update_write_data_bits_entry_brSlots_0_sharing), + .io_w_req_bits_data_2_entry_brSlots_0_valid + (io_update_write_data_bits_entry_brSlots_0_valid), + .io_w_req_bits_data_2_entry_tailSlot_offset + (io_update_write_data_bits_entry_tailSlot_offset), + .io_w_req_bits_data_2_entry_tailSlot_lower + (io_update_write_data_bits_entry_tailSlot_lower), + .io_w_req_bits_data_2_entry_tailSlot_tarStat + (io_update_write_data_bits_entry_tailSlot_tarStat), + .io_w_req_bits_data_2_entry_tailSlot_sharing + (io_update_write_data_bits_entry_tailSlot_sharing), + .io_w_req_bits_data_2_entry_tailSlot_valid + (io_update_write_data_bits_entry_tailSlot_valid), + .io_w_req_bits_data_2_entry_pftAddr + (io_update_write_data_bits_entry_pftAddr), + .io_w_req_bits_data_2_entry_carry + (io_update_write_data_bits_entry_carry), + .io_w_req_bits_data_2_entry_isCall + (io_update_write_data_bits_entry_isCall), + .io_w_req_bits_data_2_entry_isRet + (io_update_write_data_bits_entry_isRet), + .io_w_req_bits_data_2_entry_isJalr + (io_update_write_data_bits_entry_isJalr), + .io_w_req_bits_data_2_entry_last_may_be_rvi_call + (io_update_write_data_bits_entry_last_may_be_rvi_call), + .io_w_req_bits_data_2_entry_always_taken_0 + (io_update_write_data_bits_entry_always_taken_0), + .io_w_req_bits_data_2_entry_always_taken_1 + (io_update_write_data_bits_entry_always_taken_1), + .io_w_req_bits_data_2_tag (io_update_write_data_bits_tag), + .io_w_req_bits_data_3_entry_valid + (io_update_write_data_bits_entry_valid), + .io_w_req_bits_data_3_entry_brSlots_0_offset + (io_update_write_data_bits_entry_brSlots_0_offset), + .io_w_req_bits_data_3_entry_brSlots_0_lower + (io_update_write_data_bits_entry_brSlots_0_lower), + .io_w_req_bits_data_3_entry_brSlots_0_tarStat + (io_update_write_data_bits_entry_brSlots_0_tarStat), + .io_w_req_bits_data_3_entry_brSlots_0_sharing + (io_update_write_data_bits_entry_brSlots_0_sharing), + .io_w_req_bits_data_3_entry_brSlots_0_valid + (io_update_write_data_bits_entry_brSlots_0_valid), + .io_w_req_bits_data_3_entry_tailSlot_offset + (io_update_write_data_bits_entry_tailSlot_offset), + .io_w_req_bits_data_3_entry_tailSlot_lower + (io_update_write_data_bits_entry_tailSlot_lower), + .io_w_req_bits_data_3_entry_tailSlot_tarStat + (io_update_write_data_bits_entry_tailSlot_tarStat), + .io_w_req_bits_data_3_entry_tailSlot_sharing + (io_update_write_data_bits_entry_tailSlot_sharing), + .io_w_req_bits_data_3_entry_tailSlot_valid + (io_update_write_data_bits_entry_tailSlot_valid), + .io_w_req_bits_data_3_entry_pftAddr + (io_update_write_data_bits_entry_pftAddr), + .io_w_req_bits_data_3_entry_carry + (io_update_write_data_bits_entry_carry), + .io_w_req_bits_data_3_entry_isCall + (io_update_write_data_bits_entry_isCall), + .io_w_req_bits_data_3_entry_isRet + (io_update_write_data_bits_entry_isRet), + .io_w_req_bits_data_3_entry_isJalr + (io_update_write_data_bits_entry_isJalr), + .io_w_req_bits_data_3_entry_last_may_be_rvi_call + (io_update_write_data_bits_entry_last_may_be_rvi_call), + .io_w_req_bits_data_3_entry_always_taken_0 + (io_update_write_data_bits_entry_always_taken_0), + .io_w_req_bits_data_3_entry_always_taken_1 + (io_update_write_data_bits_entry_always_taken_1), + .io_w_req_bits_data_3_tag (io_update_write_data_bits_tag), + .io_w_req_bits_waymask (4'h1 << write_way_bits) // src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/FTB.scala:402:20 + ); + assign io_read_resp_valid = + total_hits_0 & pred_rdata_0_entry_valid | total_hits_1 & pred_rdata_1_entry_valid + | total_hits_2 & pred_rdata_2_entry_valid | total_hits_3 & pred_rdata_3_entry_valid; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :332:107, utility/src/main/scala/utility/Hold.scala:25:8 + assign io_read_resp_brSlots_0_offset = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_brSlots_0_offset + : pred_rdata_hold_data_0_entry_brSlots_0_offset) + : 4'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_brSlots_0_offset + : pred_rdata_hold_data_1_entry_brSlots_0_offset) + : 4'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_brSlots_0_offset + : pred_rdata_hold_data_2_entry_brSlots_0_offset) + : 4'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_brSlots_0_offset + : pred_rdata_hold_data_3_entry_brSlots_0_offset) + : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_brSlots_0_lower = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_brSlots_0_lower + : pred_rdata_hold_data_0_entry_brSlots_0_lower) + : 12'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_brSlots_0_lower + : pred_rdata_hold_data_1_entry_brSlots_0_lower) + : 12'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_brSlots_0_lower + : pred_rdata_hold_data_2_entry_brSlots_0_lower) + : 12'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_brSlots_0_lower + : pred_rdata_hold_data_3_entry_brSlots_0_lower) + : 12'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_brSlots_0_tarStat = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_brSlots_0_tarStat + : pred_rdata_hold_data_0_entry_brSlots_0_tarStat) + : 2'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_brSlots_0_tarStat + : pred_rdata_hold_data_1_entry_brSlots_0_tarStat) + : 2'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_brSlots_0_tarStat + : pred_rdata_hold_data_2_entry_brSlots_0_tarStat) + : 2'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat + : pred_rdata_hold_data_3_entry_brSlots_0_tarStat) + : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_brSlots_0_sharing = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_brSlots_0_sharing + : pred_rdata_hold_data_0_entry_brSlots_0_sharing) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_brSlots_0_sharing + : pred_rdata_hold_data_1_entry_brSlots_0_sharing) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_brSlots_0_sharing + : pred_rdata_hold_data_2_entry_brSlots_0_sharing) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_brSlots_0_sharing + : pred_rdata_hold_data_3_entry_brSlots_0_sharing); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_brSlots_0_valid = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_brSlots_0_valid + : pred_rdata_hold_data_0_entry_brSlots_0_valid) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_brSlots_0_valid + : pred_rdata_hold_data_1_entry_brSlots_0_valid) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_brSlots_0_valid + : pred_rdata_hold_data_2_entry_brSlots_0_valid) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_brSlots_0_valid + : pred_rdata_hold_data_3_entry_brSlots_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_tailSlot_offset = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_tailSlot_offset + : pred_rdata_hold_data_0_entry_tailSlot_offset) + : 4'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_tailSlot_offset + : pred_rdata_hold_data_1_entry_tailSlot_offset) + : 4'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_tailSlot_offset + : pred_rdata_hold_data_2_entry_tailSlot_offset) + : 4'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_tailSlot_offset + : pred_rdata_hold_data_3_entry_tailSlot_offset) + : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_tailSlot_lower = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_tailSlot_lower + : pred_rdata_hold_data_0_entry_tailSlot_lower) + : 20'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_tailSlot_lower + : pred_rdata_hold_data_1_entry_tailSlot_lower) + : 20'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_tailSlot_lower + : pred_rdata_hold_data_2_entry_tailSlot_lower) + : 20'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_tailSlot_lower + : pred_rdata_hold_data_3_entry_tailSlot_lower) + : 20'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_tailSlot_tarStat = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_tailSlot_tarStat + : pred_rdata_hold_data_0_entry_tailSlot_tarStat) + : 2'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_tailSlot_tarStat + : pred_rdata_hold_data_1_entry_tailSlot_tarStat) + : 2'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_tailSlot_tarStat + : pred_rdata_hold_data_2_entry_tailSlot_tarStat) + : 2'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_tailSlot_tarStat + : pred_rdata_hold_data_3_entry_tailSlot_tarStat) + : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_tailSlot_sharing = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_tailSlot_sharing + : pred_rdata_hold_data_0_entry_tailSlot_sharing) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_tailSlot_sharing + : pred_rdata_hold_data_1_entry_tailSlot_sharing) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_tailSlot_sharing + : pred_rdata_hold_data_2_entry_tailSlot_sharing) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_tailSlot_sharing + : pred_rdata_hold_data_3_entry_tailSlot_sharing); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_tailSlot_valid = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_tailSlot_valid + : pred_rdata_hold_data_0_entry_tailSlot_valid) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_tailSlot_valid + : pred_rdata_hold_data_1_entry_tailSlot_valid) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_tailSlot_valid + : pred_rdata_hold_data_2_entry_tailSlot_valid) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_tailSlot_valid + : pred_rdata_hold_data_3_entry_tailSlot_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_pftAddr = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_pftAddr + : pred_rdata_hold_data_0_entry_pftAddr) + : 4'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_pftAddr + : pred_rdata_hold_data_1_entry_pftAddr) + : 4'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_pftAddr + : pred_rdata_hold_data_2_entry_pftAddr) + : 4'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_pftAddr + : pred_rdata_hold_data_3_entry_pftAddr) + : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_carry = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_carry + : pred_rdata_hold_data_0_entry_carry) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_carry + : pred_rdata_hold_data_1_entry_carry) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_carry + : pred_rdata_hold_data_2_entry_carry) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_carry + : pred_rdata_hold_data_3_entry_carry); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_isCall = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_isCall + : pred_rdata_hold_data_0_entry_isCall) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_isCall + : pred_rdata_hold_data_1_entry_isCall) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_isCall + : pred_rdata_hold_data_2_entry_isCall) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_isCall + : pred_rdata_hold_data_3_entry_isCall); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_isRet = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_isRet + : pred_rdata_hold_data_0_entry_isRet) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_isRet + : pred_rdata_hold_data_1_entry_isRet) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_isRet + : pred_rdata_hold_data_2_entry_isRet) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_isRet + : pred_rdata_hold_data_3_entry_isRet); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_isJalr = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_isJalr + : pred_rdata_hold_data_0_entry_isJalr) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_isJalr + : pred_rdata_hold_data_1_entry_isJalr) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_isJalr + : pred_rdata_hold_data_2_entry_isJalr) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_isJalr + : pred_rdata_hold_data_3_entry_isJalr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_last_may_be_rvi_call = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_last_may_be_rvi_call + : pred_rdata_hold_data_0_entry_last_may_be_rvi_call) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_last_may_be_rvi_call + : pred_rdata_hold_data_1_entry_last_may_be_rvi_call) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_last_may_be_rvi_call + : pred_rdata_hold_data_2_entry_last_may_be_rvi_call) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call + : pred_rdata_hold_data_3_entry_last_may_be_rvi_call); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_always_taken_0 = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_always_taken_0 + : pred_rdata_hold_data_0_entry_always_taken_0) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_always_taken_0 + : pred_rdata_hold_data_1_entry_always_taken_0) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_always_taken_0 + : pred_rdata_hold_data_2_entry_always_taken_0) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_always_taken_0 + : pred_rdata_hold_data_3_entry_always_taken_0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_resp_always_taken_1 = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_always_taken_1 + : pred_rdata_hold_data_0_entry_always_taken_1) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_always_taken_1 + : pred_rdata_hold_data_1_entry_always_taken_1) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_always_taken_1 + : pred_rdata_hold_data_2_entry_always_taken_1) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_always_taken_1 + : pred_rdata_hold_data_3_entry_always_taken_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :315:62, :332:107, utility/src/main/scala/utility/Hold.scala:24:82, :25:8 + assign io_read_hits_valid = read_way_valid; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :333:34 + assign io_read_hits_bits = read_way_bits; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/FTB.scala:290:9 + assign io_update_hits_valid = + _ftb_io_r_resp_data_0_tag == u_req_tag & _ftb_io_r_resp_data_0_entry_valid + & u_total_hits_REG | u_total_hits_1 | u_total_hits_2 | u_total_hits_3; // src/main/scala/xiangshan/frontend/FTB.scala:290:9, :312:21, :327:30, :338:{35,86,96}, :339:38 + assign io_update_hits_bits = + {|{u_total_hits_3, u_total_hits_2}, u_total_hits_3 | u_total_hits_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/FTB.scala:290:9, :338:86 +endmodule + diff --git a/src/FTB/FTBEntryGen.sv b/src/FTB/FTBEntryGen.sv new file mode 100644 index 0000000..616bf32 --- /dev/null +++ b/src/FTB/FTBEntryGen.sv @@ -0,0 +1,413 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FTBEntryGen( // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7 + input [38:0] io_start_addr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_old_entry_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input [3:0] io_old_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input [11:0] io_old_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input [1:0] io_old_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_old_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_old_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input [3:0] io_old_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input [19:0] io_old_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input [1:0] io_old_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_old_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_old_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input [3:0] io_old_entry_pftAddr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_old_entry_carry, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_old_entry_isCall, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_old_entry_isRet, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_old_entry_isJalr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_old_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_old_entry_always_taken_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_old_entry_always_taken_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_3, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_4, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_5, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_6, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_7, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_8, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_9, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_10, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_11, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_12, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_13, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_14, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_brMask_15, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_jmpInfo_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_jmpInfo_bits_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_jmpInfo_bits_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_jmpInfo_bits_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input [3:0] io_pd_jmpOffset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input [38:0] io_pd_jalTarget, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_3, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_4, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_5, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_6, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_7, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_8, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_9, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_10, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_11, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_12, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_13, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_14, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_pd_rvcMask_15, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_cfiIndex_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input [3:0] io_cfiIndex_bits, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input [38:0] io_target, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_hit, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_3, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_4, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_5, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_6, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_7, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_8, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_9, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_10, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_11, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_12, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_13, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_14, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + input io_mispredict_vec_15, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_new_entry_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output [3:0] io_new_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output [11:0] io_new_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output [1:0] io_new_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_new_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_new_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output [3:0] io_new_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output [19:0] io_new_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output [1:0] io_new_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_new_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_new_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output [3:0] io_new_entry_pftAddr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_new_entry_carry, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_new_entry_isCall, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_new_entry_isRet, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_new_entry_isJalr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_new_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_new_entry_always_taken_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_new_entry_always_taken_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_taken_mask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_taken_mask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_jmp_taken, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_mispred_mask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_mispred_mask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_mispred_mask_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 + output io_is_old_entry // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14 +); + + wire [15:0] _GEN = + {{io_pd_brMask_15}, + {io_pd_brMask_14}, + {io_pd_brMask_13}, + {io_pd_brMask_12}, + {io_pd_brMask_11}, + {io_pd_brMask_10}, + {io_pd_brMask_9}, + {io_pd_brMask_8}, + {io_pd_brMask_7}, + {io_pd_brMask_6}, + {io_pd_brMask_5}, + {io_pd_brMask_4}, + {io_pd_brMask_3}, + {io_pd_brMask_2}, + {io_pd_brMask_1}, + {io_pd_brMask_0}}; // src/main/scala/xiangshan/frontend/NewFtq.scala:253:47 + wire init_entry_always_taken_0 = _GEN[io_cfiIndex_bits] & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:253:47 + wire init_entry_isJalr = + io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_0 & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:256:62 + wire last_jmp_rvi = io_pd_jmpInfo_valid & (&io_pd_jmpOffset) & ~io_pd_rvcMask_15; // src/main/scala/xiangshan/frontend/NewFtq.scala:259:{52,75,78} + wire cfi_is_jalr = io_cfiIndex_bits == io_pd_jmpOffset & init_entry_isJalr; // src/main/scala/xiangshan/frontend/NewFtq.scala:256:62, :262:37, :263:55 + wire [37:0] _GEN_0 = cfi_is_jalr ? io_target[38:1] : io_pd_jalTarget[38:1]; // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14, :263:55, :284:64 + wire [4:0] _GEN_1 = {1'h0, io_start_addr[4:1]}; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :266:30, :287:40 + wire [15:0] _GEN_2 = + {{io_pd_rvcMask_15}, + {io_pd_rvcMask_14}, + {io_pd_rvcMask_13}, + {io_pd_rvcMask_12}, + {io_pd_rvcMask_11}, + {io_pd_rvcMask_10}, + {io_pd_rvcMask_9}, + {io_pd_rvcMask_8}, + {io_pd_rvcMask_7}, + {io_pd_rvcMask_6}, + {io_pd_rvcMask_5}, + {io_pd_rvcMask_4}, + {io_pd_rvcMask_3}, + {io_pd_rvcMask_2}, + {io_pd_rvcMask_1}, + {io_pd_rvcMask_0}}; // src/main/scala/xiangshan/frontend/NewFtq.scala:287:62 + wire [4:0] jmpPft = + 5'(_GEN_1 + + 5'({1'h0, io_pd_jmpOffset} + {3'h0, _GEN_2[io_pd_jmpOffset] ? 2'h1 : 2'h2})); // src/main/scala/xiangshan/frontend/FTB.scala:60:10, :61:12, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :287:{40,56,62} + wire is_new_br = + init_entry_always_taken_0 + & {io_old_entry_tailSlot_valid & io_old_entry_tailSlot_offset == io_cfiIndex_bits + & io_old_entry_tailSlot_sharing, + io_old_entry_brSlots_0_valid + & io_old_entry_brSlots_0_offset == io_cfiIndex_bits} == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:194:{32,44}, :195:{42,53}, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :253:47, :299:{37,44}, :300:29 + wire new_br_insert_onehot_0 = + ~io_old_entry_brSlots_0_valid | io_cfiIndex_bits < io_old_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:307:{9,33,50} + wire _new_br_insert_onehot_T_3 = + io_cfiIndex_bits > io_old_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:309:53 + wire new_br_insert_onehot_1 = + io_old_entry_brSlots_0_valid & _new_br_insert_onehot_T_3 + & (~io_old_entry_tailSlot_valid | io_cfiIndex_bits < io_old_entry_tailSlot_offset); // src/main/scala/xiangshan/frontend/NewFtq.scala:309:{53,83}, :310:{10,36,53} + wire _GEN_3 = io_cfiIndex_bits > io_old_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:322:31 + wire _GEN_4 = _GEN_3 | ~io_old_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:314:36, :322:{31,61}, :329:44 + wire pft_need_to_change = + is_new_br & io_old_entry_brSlots_0_valid & io_old_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :342:38 + wire [3:0] new_pft_offset = + {new_br_insert_onehot_1, new_br_insert_onehot_0} == 2'h0 + ? io_cfiIndex_bits + : io_old_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :307:33, :309:83, :346:{10,33,40} + wire [4:0] _old_entry_modified_carry_T_1 = 5'(_GEN_1 + {1'h0, new_pft_offset}); // src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :287:40, :346:10, :350:59, :351:58 + wire _old_target_target_T_9 = io_old_entry_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:60:10, :98:19 + wire _old_target_target_T_10 = io_old_entry_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:61:12, :99:19 + wire _old_target_target_T_11 = io_old_entry_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41 + wire jalr_target_modified = + cfi_is_jalr + & {io_old_entry_tailSlot_sharing + ? {(_old_target_target_T_9 ? 26'(io_start_addr[38:13] + 26'h1) : 26'h0) + | (_old_target_target_T_10 ? 26'(io_start_addr[38:13] - 26'h1) : 26'h0) + | (_old_target_target_T_11 ? io_start_addr[38:13] : 26'h0), + io_old_entry_tailSlot_lower[11:0]} + : {(_old_target_target_T_9 ? 18'(io_start_addr[38:21] + 18'h1) : 18'h0) + | (_old_target_target_T_10 ? 18'(io_start_addr[38:21] - 18'h1) : 18'h0) + | (_old_target_target_T_11 ? io_start_addr[38:21] : 18'h0), + io_old_entry_tailSlot_lower}, + 1'h0} != io_target & ~io_old_entry_tailSlot_sharing; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :263:55, :360:25, :361:{57,72} + wire old_entry_always_taken_always_taken_0 = + io_old_entry_always_taken_0 & io_cfiIndex_valid & io_old_entry_brSlots_0_valid + & io_cfiIndex_bits == io_old_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:371:{65,85} + wire old_entry_always_taken_always_taken_1 = + io_old_entry_always_taken_1 & io_cfiIndex_valid & io_old_entry_tailSlot_valid + & io_old_entry_tailSlot_sharing & io_cfiIndex_bits == io_old_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:371:{65,85} + wire _GEN_5 = is_new_br & new_br_insert_onehot_0; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :307:33, :379:8 + wire _GEN_6 = is_new_br & pft_need_to_change; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :342:38, :379:8 + wire _GEN_7 = ~is_new_br | ~pft_need_to_change; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :314:36, :342:38, :344:29, :352:45, :379:8 + wire [3:0] _io_new_entry_brSlots_0_offset_output = + io_hit + ? (_GEN_5 ? io_cfiIndex_bits : io_old_entry_brSlots_0_offset) + : init_entry_always_taken_0 ? io_cfiIndex_bits : 4'h0; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:{28,41}, :253:47, :273:20, :275:25, :379:8, :383:22 + wire _io_new_entry_brSlots_0_valid_output = + io_hit ? _GEN_5 | io_old_entry_brSlots_0_valid : init_entry_always_taken_0; // src/main/scala/xiangshan/frontend/NewFtq.scala:253:47, :379:8, :383:22 + wire [3:0] _io_new_entry_tailSlot_offset_output = + io_hit + ? (is_new_br + ? (new_br_insert_onehot_1 + ? io_cfiIndex_bits + : _GEN_4 ? io_old_entry_tailSlot_offset : io_old_entry_brSlots_0_offset) + : io_old_entry_tailSlot_offset) + : io_pd_jmpInfo_valid ? io_pd_jmpOffset : 4'h0; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:{28,41}, :281:24, :282:32, :300:29, :309:83, :314:36, :317:36, :319:19, :322:61, :329:44, :379:8, :383:22 + wire _io_new_entry_tailSlot_sharing_output = + io_hit + & (is_new_br + ? new_br_insert_onehot_1 | ~_GEN_3 & io_old_entry_brSlots_0_valid + | io_old_entry_tailSlot_sharing + : ~jalr_target_modified & io_old_entry_tailSlot_sharing); // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :309:83, :314:36, :317:36, :322:{31,61}, :329:44, :358:47, :361:72, :362:31, :379:8, :380:10, :383:22 + wire _io_new_entry_tailSlot_valid_output = + io_hit + ? (is_new_br + ? new_br_insert_onehot_1 + | (_GEN_4 ? io_old_entry_tailSlot_valid : io_old_entry_brSlots_0_valid) + : io_old_entry_tailSlot_valid) + : io_pd_jmpInfo_valid + & (io_pd_jmpInfo_valid & ~io_pd_jmpInfo_bits_0 & io_cfiIndex_valid + | init_entry_isJalr); // src/main/scala/xiangshan/frontend/NewFtq.scala:250:28, :255:{42,62}, :256:62, :281:24, :283:{31,49}, :300:29, :309:83, :314:36, :317:36, :318:18, :322:61, :329:44, :379:8, :383:22 + wire _io_mispred_mask_1_WIRE_1 = + _io_new_entry_tailSlot_valid_output & _io_new_entry_tailSlot_sharing_output; // src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:383:22 + wire [15:0] _GEN_8 = + {{io_mispredict_vec_15}, + {io_mispredict_vec_14}, + {io_mispredict_vec_13}, + {io_mispredict_vec_12}, + {io_mispredict_vec_11}, + {io_mispredict_vec_10}, + {io_mispredict_vec_9}, + {io_mispredict_vec_8}, + {io_mispredict_vec_7}, + {io_mispredict_vec_6}, + {io_mispredict_vec_5}, + {io_mispredict_vec_4}, + {io_mispredict_vec_3}, + {io_mispredict_vec_2}, + {io_mispredict_vec_1}, + {io_mispredict_vec_0}}; // src/main/scala/xiangshan/frontend/NewFtq.scala:391:52 + assign io_new_entry_valid = ~io_hit | io_old_entry_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:{22,23} + assign io_new_entry_brSlots_0_offset = _io_new_entry_brSlots_0_offset_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22 + assign io_new_entry_brSlots_0_lower = + io_hit + ? (_GEN_5 ? io_target[12:1] : io_old_entry_brSlots_0_lower) + : init_entry_always_taken_0 ? io_target[12:1] : 12'h0; // src/main/scala/xiangshan/frontend/FTB.scala:62:64, :68:16, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :253:47, :273:20, :379:8, :383:22 + assign io_new_entry_brSlots_0_tarStat = + io_hit + ? (_GEN_5 + ? (io_target[38:13] > io_start_addr[38:13] + ? 2'h1 + : {io_target[38:13] < io_start_addr[38:13], 1'h0}) + : io_old_entry_brSlots_0_tarStat) + : init_entry_always_taken_0 + ? (io_target[38:13] > io_start_addr[38:13] + ? 2'h1 + : {io_target[38:13] < io_start_addr[38:13], 1'h0}) + : 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:60:{10,25}, :61:{12,27}, :64:23, :65:31, :69:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :253:47, :273:20, :379:8, :383:22 + assign io_new_entry_brSlots_0_sharing = + io_hit & (~is_new_br | ~new_br_insert_onehot_0) & io_old_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :300:29, :307:33, :314:36, :317:36, :379:8, :383:22 + assign io_new_entry_brSlots_0_valid = _io_new_entry_brSlots_0_valid_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22 + assign io_new_entry_tailSlot_offset = _io_new_entry_tailSlot_offset_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22 + assign io_new_entry_tailSlot_lower = + io_hit + ? (is_new_br + ? (new_br_insert_onehot_1 + ? {8'h0, io_target[12:1]} + : _GEN_4 + ? io_old_entry_tailSlot_lower + : {8'h0, io_old_entry_brSlots_0_lower}) + : jalr_target_modified ? io_target[20:1] : io_old_entry_tailSlot_lower) + : io_pd_jmpInfo_valid ? _GEN_0[19:0] : 20'h0; // src/main/scala/xiangshan/frontend/FTB.scala:62:64, :68:16, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :281:24, :284:64, :300:29, :309:83, :314:36, :317:36, :322:61, :329:44, :361:72, :379:8, :380:10, :383:22, utility/src/main/scala/utility/BitUtils.scala:88:41 + assign io_new_entry_tailSlot_tarStat = + io_hit + ? (is_new_br + ? (new_br_insert_onehot_1 + ? (io_target[38:13] > io_start_addr[38:13] + ? 2'h1 + : {io_target[38:13] < io_start_addr[38:13], 1'h0}) + : _GEN_4 ? io_old_entry_tailSlot_tarStat : io_old_entry_brSlots_0_tarStat) + : jalr_target_modified + ? (io_target[38:21] > io_start_addr[38:21] + ? 2'h1 + : {io_target[38:21] < io_start_addr[38:21], 1'h0}) + : io_old_entry_tailSlot_tarStat) + : io_pd_jmpInfo_valid + ? (_GEN_0[37:20] > io_start_addr[38:21] + ? 2'h1 + : {_GEN_0[37:20] < io_start_addr[38:21], 1'h0}) + : 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:60:{10,25}, :61:{12,27}, :64:23, :65:31, :69:18, :76:32, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :281:24, :284:64, :300:29, :309:83, :314:36, :317:36, :322:61, :329:44, :361:72, :379:8, :380:10, :383:22 + assign io_new_entry_tailSlot_sharing = _io_new_entry_tailSlot_sharing_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22 + assign io_new_entry_tailSlot_valid = _io_new_entry_tailSlot_valid_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22 + assign io_new_entry_pftAddr = + io_hit + ? (_GEN_6 ? 4'(io_start_addr[4:1] + new_pft_offset) : io_old_entry_pftAddr) + : io_pd_jmpInfo_valid & ~last_jmp_rvi ? jmpPft[3:0] : io_start_addr[4:1]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :259:75, :266:30, :287:56, :288:{28,43,46}, :346:10, :350:59, :379:8, :383:22 + assign io_new_entry_carry = + io_hit + ? (_GEN_6 ? _old_entry_modified_carry_T_1[4] : io_old_entry_carry) + : ~(io_pd_jmpInfo_valid & ~last_jmp_rvi) | jmpPft[4]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :259:75, :287:56, :288:46, :289:{28,43,67}, :351:{58,81}, :379:8, :383:22 + assign io_new_entry_isCall = + io_hit + ? _GEN_7 & io_old_entry_isCall + : io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_1 & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :257:62, :379:8, :383:22 + assign io_new_entry_isRet = + io_hit + ? _GEN_7 & io_old_entry_isRet + : io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_2 & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :258:62, :379:8, :383:22 + assign io_new_entry_isJalr = io_hit ? _GEN_7 & io_old_entry_isJalr : init_entry_isJalr; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :256:62, :379:8, :383:22 + assign io_new_entry_last_may_be_rvi_call = + io_hit + ? _GEN_7 & io_old_entry_last_may_be_rvi_call + : (&io_pd_jmpOffset) & ~_GEN_2[io_pd_jmpOffset]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :259:52, :287:62, :294:{74,77}, :379:8, :383:22 + assign io_new_entry_always_taken_0 = + io_hit + ? (is_new_br + ? new_br_insert_onehot_0 | ~_new_br_insert_onehot_T_3 + & io_old_entry_always_taken_0 + : jalr_target_modified + ? ~jalr_target_modified & io_old_entry_always_taken_0 + : old_entry_always_taken_always_taken_0) + : init_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :253:47, :300:29, :307:33, :309:53, :314:36, :317:36, :321:42, :322:61, :323:42, :358:47, :361:72, :362:31, :364:48, :371:65, :379:8, :380:10, :383:22 + assign io_new_entry_always_taken_1 = + io_hit + & (is_new_br + ? new_br_insert_onehot_1 | ~_GEN_3 & io_old_entry_always_taken_1 + : jalr_target_modified + ? ~jalr_target_modified & io_old_entry_always_taken_1 + : old_entry_always_taken_always_taken_1); // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :300:29, :309:83, :314:36, :317:36, :321:42, :322:{31,61}, :323:42, :329:44, :358:47, :361:72, :362:31, :364:48, :371:65, :379:8, :380:10, :383:22 + assign io_taken_mask_0 = + io_cfiIndex_bits == _io_new_entry_brSlots_0_offset_output & io_cfiIndex_valid + & _io_new_entry_brSlots_0_valid_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :387:{39,68} + assign io_taken_mask_1 = + io_cfiIndex_bits == _io_new_entry_tailSlot_offset_output & io_cfiIndex_valid + & _io_mispred_mask_1_WIRE_1; // src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :387:{39,68} + assign io_jmp_taken = + _io_new_entry_tailSlot_valid_output & ~_io_new_entry_tailSlot_sharing_output + & _io_new_entry_tailSlot_offset_output == io_cfiIndex_bits; // src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :389:{41,73} + assign io_mispred_mask_0 = + _io_new_entry_brSlots_0_valid_output & _GEN_8[_io_new_entry_brSlots_0_offset_output]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :391:52 + assign io_mispred_mask_1 = + _io_mispred_mask_1_WIRE_1 & _GEN_8[_io_new_entry_tailSlot_offset_output]; // src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :391:52 + assign io_mispred_mask_2 = + _io_new_entry_tailSlot_valid_output & ~_io_new_entry_tailSlot_sharing_output + & _GEN_8[io_pd_jmpOffset]; // src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :391:52, :393:49 + assign io_is_old_entry = + io_hit & ~is_new_br & ~jalr_target_modified + & ~(io_old_entry_always_taken_0 & ~old_entry_always_taken_always_taken_0 + | io_old_entry_always_taken_1 & ~old_entry_always_taken_always_taken_1); // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :300:29, :361:72, :371:65, :372:{56,59}, :374:65, :397:{29,43,65,68} +endmodule + diff --git a/src/FTB/SRAMTemplate_9.sv b/src/FTB/SRAMTemplate_9.sv new file mode 100644 index 0000000..9cc03e1 --- /dev/null +++ b/src/FTB/SRAMTemplate_9.sv @@ -0,0 +1,659 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_9( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + input clock, + input reset, + output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [8:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [3:0] io_r_resp_data_0_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [11:0] io_r_resp_data_0_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_0_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [3:0] io_r_resp_data_0_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [19:0] io_r_resp_data_0_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_0_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [3:0] io_r_resp_data_0_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [19:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [3:0] io_r_resp_data_1_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [11:0] io_r_resp_data_1_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_1_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [3:0] io_r_resp_data_1_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [19:0] io_r_resp_data_1_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_1_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [3:0] io_r_resp_data_1_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [19:0] io_r_resp_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_2_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [3:0] io_r_resp_data_2_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [11:0] io_r_resp_data_2_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_2_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_2_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_2_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [3:0] io_r_resp_data_2_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [19:0] io_r_resp_data_2_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_2_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_2_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_2_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [3:0] io_r_resp_data_2_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_2_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_2_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_2_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_2_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_2_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_2_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_2_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [19:0] io_r_resp_data_2_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_3_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [3:0] io_r_resp_data_3_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [11:0] io_r_resp_data_3_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_3_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_3_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_3_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [3:0] io_r_resp_data_3_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [19:0] io_r_resp_data_3_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_3_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_3_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_3_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [3:0] io_r_resp_data_3_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_3_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_3_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_3_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_3_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_3_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_3_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_3_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [19:0] io_r_resp_data_3_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [8:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_0_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_data_0_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [11:0] io_w_req_bits_data_0_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_0_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_0_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_0_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_data_0_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [19:0] io_w_req_bits_data_0_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_0_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_0_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_0_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_data_0_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_0_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_0_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_0_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_0_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_0_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_0_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_0_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [19:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_1_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_data_1_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [11:0] io_w_req_bits_data_1_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_1_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_1_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_1_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_data_1_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [19:0] io_w_req_bits_data_1_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_1_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_1_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_1_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_data_1_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_1_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_1_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_1_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_1_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_1_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_1_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_1_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [19:0] io_w_req_bits_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_2_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_data_2_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [11:0] io_w_req_bits_data_2_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_2_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_2_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_2_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_data_2_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [19:0] io_w_req_bits_data_2_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_2_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_2_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_2_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_data_2_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_2_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_2_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_2_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_2_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_2_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_2_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_2_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [19:0] io_w_req_bits_data_2_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_3_entry_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_data_3_entry_brSlots_0_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [11:0] io_w_req_bits_data_3_entry_brSlots_0_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_3_entry_brSlots_0_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_3_entry_brSlots_0_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_3_entry_brSlots_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_data_3_entry_tailSlot_offset, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [19:0] io_w_req_bits_data_3_entry_tailSlot_lower, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_3_entry_tailSlot_tarStat, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_3_entry_tailSlot_sharing, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_3_entry_tailSlot_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_data_3_entry_pftAddr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_3_entry_carry, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_3_entry_isCall, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_3_entry_isRet, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_3_entry_isJalr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_3_entry_last_may_be_rvi_call, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_3_entry_always_taken_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_3_entry_always_taken_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [19:0] io_w_req_bits_data_3_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 +); + + wire [19:0] _wdata_T_3_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_3_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_3_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_3_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_3_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_3_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_3_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_3_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [3:0] _wdata_T_3_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_3_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_3_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [1:0] _wdata_T_3_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [19:0] _wdata_T_3_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [3:0] _wdata_T_3_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_3_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_3_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [1:0] _wdata_T_3_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [11:0] _wdata_T_3_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [3:0] _wdata_T_3_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_3_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [19:0] _wdata_T_2_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_2_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_2_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_2_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_2_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_2_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_2_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_2_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [3:0] _wdata_T_2_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_2_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_2_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [1:0] _wdata_T_2_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [19:0] _wdata_T_2_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [3:0] _wdata_T_2_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_2_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_2_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [1:0] _wdata_T_2_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [11:0] _wdata_T_2_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [3:0] _wdata_T_2_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_2_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [19:0] _wdata_T_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_1_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_1_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_1_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_1_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_1_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_1_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_1_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [3:0] _wdata_T_1_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_1_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_1_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [1:0] _wdata_T_1_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [19:0] _wdata_T_1_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [3:0] _wdata_T_1_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_1_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_1_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [1:0] _wdata_T_1_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [11:0] _wdata_T_1_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [3:0] _wdata_T_1_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_1_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [19:0] _wdata_T_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_0_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_0_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_0_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_0_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_0_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_0_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_0_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [3:0] _wdata_T_0_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_0_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_0_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [1:0] _wdata_T_0_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [19:0] _wdata_T_0_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [3:0] _wdata_T_0_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_0_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_0_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [1:0] _wdata_T_0_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [11:0] _wdata_T_0_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [3:0] _wdata_T_0_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_0_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [8:0] array_MPORT_addr; // utility/src/main/scala/utility/SRAMTemplate.scala:125:19 + wire array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38 + wire array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 + wire [319:0] _array_RW0_rdata; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 + reg [8:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40 + assign array_MPORT_en = io_w_req_valid | _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52 + assign array_raw_rdata_en = io_r_req_valid & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52, :123:{38,41} + assign array_MPORT_addr = _resetState ? _resetSet : io_w_req_bits_setIdx; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19 + assign _wdata_T_0_entry_valid = ~_resetState & io_w_req_bits_data_0_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_0_entry_brSlots_0_offset = + _resetState ? 4'h0 : io_w_req_bits_data_0_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_0_entry_brSlots_0_lower = + _resetState ? 12'h0 : io_w_req_bits_data_0_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_0_entry_brSlots_0_tarStat = + _resetState ? 2'h0 : io_w_req_bits_data_0_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_0_entry_brSlots_0_sharing = + ~_resetState & io_w_req_bits_data_0_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_0_entry_brSlots_0_valid = + ~_resetState & io_w_req_bits_data_0_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_0_entry_tailSlot_offset = + _resetState ? 4'h0 : io_w_req_bits_data_0_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_0_entry_tailSlot_lower = + _resetState ? 20'h0 : io_w_req_bits_data_0_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_0_entry_tailSlot_tarStat = + _resetState ? 2'h0 : io_w_req_bits_data_0_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_0_entry_tailSlot_sharing = + ~_resetState & io_w_req_bits_data_0_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_0_entry_tailSlot_valid = + ~_resetState & io_w_req_bits_data_0_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_0_entry_pftAddr = + _resetState ? 4'h0 : io_w_req_bits_data_0_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_0_entry_carry = ~_resetState & io_w_req_bits_data_0_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_0_entry_isCall = ~_resetState & io_w_req_bits_data_0_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_0_entry_isRet = ~_resetState & io_w_req_bits_data_0_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_0_entry_isJalr = ~_resetState & io_w_req_bits_data_0_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_0_entry_last_may_be_rvi_call = + ~_resetState & io_w_req_bits_data_0_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_0_entry_always_taken_0 = + ~_resetState & io_w_req_bits_data_0_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_0_entry_always_taken_1 = + ~_resetState & io_w_req_bits_data_0_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_0_tag = _resetState ? 20'h0 : io_w_req_bits_data_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_1_entry_valid = ~_resetState & io_w_req_bits_data_1_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_1_entry_brSlots_0_offset = + _resetState ? 4'h0 : io_w_req_bits_data_1_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_1_entry_brSlots_0_lower = + _resetState ? 12'h0 : io_w_req_bits_data_1_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_1_entry_brSlots_0_tarStat = + _resetState ? 2'h0 : io_w_req_bits_data_1_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_1_entry_brSlots_0_sharing = + ~_resetState & io_w_req_bits_data_1_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_1_entry_brSlots_0_valid = + ~_resetState & io_w_req_bits_data_1_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_1_entry_tailSlot_offset = + _resetState ? 4'h0 : io_w_req_bits_data_1_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_1_entry_tailSlot_lower = + _resetState ? 20'h0 : io_w_req_bits_data_1_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_1_entry_tailSlot_tarStat = + _resetState ? 2'h0 : io_w_req_bits_data_1_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_1_entry_tailSlot_sharing = + ~_resetState & io_w_req_bits_data_1_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_1_entry_tailSlot_valid = + ~_resetState & io_w_req_bits_data_1_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_1_entry_pftAddr = + _resetState ? 4'h0 : io_w_req_bits_data_1_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_1_entry_carry = ~_resetState & io_w_req_bits_data_1_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_1_entry_isCall = ~_resetState & io_w_req_bits_data_1_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_1_entry_isRet = ~_resetState & io_w_req_bits_data_1_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_1_entry_isJalr = ~_resetState & io_w_req_bits_data_1_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_1_entry_last_may_be_rvi_call = + ~_resetState & io_w_req_bits_data_1_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_1_entry_always_taken_0 = + ~_resetState & io_w_req_bits_data_1_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_1_entry_always_taken_1 = + ~_resetState & io_w_req_bits_data_1_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_1_tag = _resetState ? 20'h0 : io_w_req_bits_data_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_2_entry_valid = ~_resetState & io_w_req_bits_data_2_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_2_entry_brSlots_0_offset = + _resetState ? 4'h0 : io_w_req_bits_data_2_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_2_entry_brSlots_0_lower = + _resetState ? 12'h0 : io_w_req_bits_data_2_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_2_entry_brSlots_0_tarStat = + _resetState ? 2'h0 : io_w_req_bits_data_2_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_2_entry_brSlots_0_sharing = + ~_resetState & io_w_req_bits_data_2_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_2_entry_brSlots_0_valid = + ~_resetState & io_w_req_bits_data_2_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_2_entry_tailSlot_offset = + _resetState ? 4'h0 : io_w_req_bits_data_2_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_2_entry_tailSlot_lower = + _resetState ? 20'h0 : io_w_req_bits_data_2_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_2_entry_tailSlot_tarStat = + _resetState ? 2'h0 : io_w_req_bits_data_2_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_2_entry_tailSlot_sharing = + ~_resetState & io_w_req_bits_data_2_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_2_entry_tailSlot_valid = + ~_resetState & io_w_req_bits_data_2_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_2_entry_pftAddr = + _resetState ? 4'h0 : io_w_req_bits_data_2_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_2_entry_carry = ~_resetState & io_w_req_bits_data_2_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_2_entry_isCall = ~_resetState & io_w_req_bits_data_2_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_2_entry_isRet = ~_resetState & io_w_req_bits_data_2_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_2_entry_isJalr = ~_resetState & io_w_req_bits_data_2_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_2_entry_last_may_be_rvi_call = + ~_resetState & io_w_req_bits_data_2_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_2_entry_always_taken_0 = + ~_resetState & io_w_req_bits_data_2_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_2_entry_always_taken_1 = + ~_resetState & io_w_req_bits_data_2_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_2_tag = _resetState ? 20'h0 : io_w_req_bits_data_2_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_3_entry_valid = ~_resetState & io_w_req_bits_data_3_entry_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_3_entry_brSlots_0_offset = + _resetState ? 4'h0 : io_w_req_bits_data_3_entry_brSlots_0_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_3_entry_brSlots_0_lower = + _resetState ? 12'h0 : io_w_req_bits_data_3_entry_brSlots_0_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_3_entry_brSlots_0_tarStat = + _resetState ? 2'h0 : io_w_req_bits_data_3_entry_brSlots_0_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_3_entry_brSlots_0_sharing = + ~_resetState & io_w_req_bits_data_3_entry_brSlots_0_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_3_entry_brSlots_0_valid = + ~_resetState & io_w_req_bits_data_3_entry_brSlots_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_3_entry_tailSlot_offset = + _resetState ? 4'h0 : io_w_req_bits_data_3_entry_tailSlot_offset; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_3_entry_tailSlot_lower = + _resetState ? 20'h0 : io_w_req_bits_data_3_entry_tailSlot_lower; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_3_entry_tailSlot_tarStat = + _resetState ? 2'h0 : io_w_req_bits_data_3_entry_tailSlot_tarStat; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_3_entry_tailSlot_sharing = + ~_resetState & io_w_req_bits_data_3_entry_tailSlot_sharing; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_3_entry_tailSlot_valid = + ~_resetState & io_w_req_bits_data_3_entry_tailSlot_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_3_entry_pftAddr = + _resetState ? 4'h0 : io_w_req_bits_data_3_entry_pftAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_3_entry_carry = ~_resetState & io_w_req_bits_data_3_entry_carry; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_3_entry_isCall = ~_resetState & io_w_req_bits_data_3_entry_isCall; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_3_entry_isRet = ~_resetState & io_w_req_bits_data_3_entry_isRet; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_3_entry_isJalr = ~_resetState & io_w_req_bits_data_3_entry_isJalr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_3_entry_last_may_be_rvi_call = + ~_resetState & io_w_req_bits_data_3_entry_last_may_be_rvi_call; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_3_entry_always_taken_0 = + ~_resetState & io_w_req_bits_data_3_entry_always_taken_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_3_entry_always_taken_1 = + ~_resetState & io_w_req_bits_data_3_entry_always_taken_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign _wdata_T_3_tag = _resetState ? 20'h0 : io_w_req_bits_data_3_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + always @(posedge clock or posedge reset) begin + if (reset) begin + _resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + _resetSet <= 9'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 + end + else begin + _resetState <= ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38} + if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 + _resetSet <= 9'(_resetSet + 9'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24 + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + _resetState = _RANDOM[/*Zero width*/ 1'b0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + _resetSet = _RANDOM[/*Zero width*/ 1'b0][9:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + _resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + _resetSet = 9'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_3 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + .RW0_addr (array_MPORT_en ? array_MPORT_addr : io_r_req_bits_setIdx), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :125:19 + .RW0_en (array_raw_rdata_en | array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :123:38 + .RW0_clk (clock), + .RW0_wmode (array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 + .RW0_wdata + ({_wdata_T_3_entry_valid, + _wdata_T_3_entry_brSlots_0_offset, + _wdata_T_3_entry_brSlots_0_lower, + _wdata_T_3_entry_brSlots_0_tarStat, + _wdata_T_3_entry_brSlots_0_sharing, + _wdata_T_3_entry_brSlots_0_valid, + _wdata_T_3_entry_tailSlot_offset, + _wdata_T_3_entry_tailSlot_lower, + _wdata_T_3_entry_tailSlot_tarStat, + _wdata_T_3_entry_tailSlot_sharing, + _wdata_T_3_entry_tailSlot_valid, + _wdata_T_3_entry_pftAddr, + _wdata_T_3_entry_carry, + _wdata_T_3_entry_isCall, + _wdata_T_3_entry_isRet, + _wdata_T_3_entry_isJalr, + _wdata_T_3_entry_last_may_be_rvi_call, + _wdata_T_3_entry_always_taken_1, + _wdata_T_3_entry_always_taken_0, + _wdata_T_3_tag, + _wdata_T_2_entry_valid, + _wdata_T_2_entry_brSlots_0_offset, + _wdata_T_2_entry_brSlots_0_lower, + _wdata_T_2_entry_brSlots_0_tarStat, + _wdata_T_2_entry_brSlots_0_sharing, + _wdata_T_2_entry_brSlots_0_valid, + _wdata_T_2_entry_tailSlot_offset, + _wdata_T_2_entry_tailSlot_lower, + _wdata_T_2_entry_tailSlot_tarStat, + _wdata_T_2_entry_tailSlot_sharing, + _wdata_T_2_entry_tailSlot_valid, + _wdata_T_2_entry_pftAddr, + _wdata_T_2_entry_carry, + _wdata_T_2_entry_isCall, + _wdata_T_2_entry_isRet, + _wdata_T_2_entry_isJalr, + _wdata_T_2_entry_last_may_be_rvi_call, + _wdata_T_2_entry_always_taken_1, + _wdata_T_2_entry_always_taken_0, + _wdata_T_2_tag, + _wdata_T_1_entry_valid, + _wdata_T_1_entry_brSlots_0_offset, + _wdata_T_1_entry_brSlots_0_lower, + _wdata_T_1_entry_brSlots_0_tarStat, + _wdata_T_1_entry_brSlots_0_sharing, + _wdata_T_1_entry_brSlots_0_valid, + _wdata_T_1_entry_tailSlot_offset, + _wdata_T_1_entry_tailSlot_lower, + _wdata_T_1_entry_tailSlot_tarStat, + _wdata_T_1_entry_tailSlot_sharing, + _wdata_T_1_entry_tailSlot_valid, + _wdata_T_1_entry_pftAddr, + _wdata_T_1_entry_carry, + _wdata_T_1_entry_isCall, + _wdata_T_1_entry_isRet, + _wdata_T_1_entry_isJalr, + _wdata_T_1_entry_last_may_be_rvi_call, + _wdata_T_1_entry_always_taken_1, + _wdata_T_1_entry_always_taken_0, + _wdata_T_1_tag, + _wdata_T_0_entry_valid, + _wdata_T_0_entry_brSlots_0_offset, + _wdata_T_0_entry_brSlots_0_lower, + _wdata_T_0_entry_brSlots_0_tarStat, + _wdata_T_0_entry_brSlots_0_sharing, + _wdata_T_0_entry_brSlots_0_valid, + _wdata_T_0_entry_tailSlot_offset, + _wdata_T_0_entry_tailSlot_lower, + _wdata_T_0_entry_tailSlot_tarStat, + _wdata_T_0_entry_tailSlot_sharing, + _wdata_T_0_entry_tailSlot_valid, + _wdata_T_0_entry_pftAddr, + _wdata_T_0_entry_carry, + _wdata_T_0_entry_isCall, + _wdata_T_0_entry_isRet, + _wdata_T_0_entry_isJalr, + _wdata_T_0_entry_last_may_be_rvi_call, + _wdata_T_0_entry_always_taken_1, + _wdata_T_0_entry_always_taken_0, + _wdata_T_0_tag}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :126:26 + .RW0_rdata (_array_RW0_rdata), + .RW0_wmask (_resetState ? 4'hF : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37} + ); + assign io_r_req_ready = ~_resetState & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :122:52, :123:41, :157:{21,33} + assign io_r_resp_data_0_entry_valid = _array_RW0_rdata[79]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_brSlots_0_offset = _array_RW0_rdata[78:75]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_brSlots_0_lower = _array_RW0_rdata[74:63]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_brSlots_0_tarStat = _array_RW0_rdata[62:61]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_brSlots_0_sharing = _array_RW0_rdata[60]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_brSlots_0_valid = _array_RW0_rdata[59]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_tailSlot_offset = _array_RW0_rdata[58:55]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_tailSlot_lower = _array_RW0_rdata[54:35]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_tailSlot_tarStat = _array_RW0_rdata[34:33]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_tailSlot_sharing = _array_RW0_rdata[32]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_tailSlot_valid = _array_RW0_rdata[31]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_pftAddr = _array_RW0_rdata[30:27]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_carry = _array_RW0_rdata[26]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_isCall = _array_RW0_rdata[25]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_isRet = _array_RW0_rdata[24]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_isJalr = _array_RW0_rdata[23]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_last_may_be_rvi_call = _array_RW0_rdata[22]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_always_taken_0 = _array_RW0_rdata[20]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_entry_always_taken_1 = _array_RW0_rdata[21]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_0_tag = _array_RW0_rdata[19:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_valid = _array_RW0_rdata[159]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_brSlots_0_offset = _array_RW0_rdata[158:155]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_brSlots_0_lower = _array_RW0_rdata[154:143]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_brSlots_0_tarStat = _array_RW0_rdata[142:141]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_brSlots_0_sharing = _array_RW0_rdata[140]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_brSlots_0_valid = _array_RW0_rdata[139]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_tailSlot_offset = _array_RW0_rdata[138:135]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_tailSlot_lower = _array_RW0_rdata[134:115]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_tailSlot_tarStat = _array_RW0_rdata[114:113]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_tailSlot_sharing = _array_RW0_rdata[112]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_tailSlot_valid = _array_RW0_rdata[111]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_pftAddr = _array_RW0_rdata[110:107]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_carry = _array_RW0_rdata[106]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_isCall = _array_RW0_rdata[105]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_isRet = _array_RW0_rdata[104]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_isJalr = _array_RW0_rdata[103]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_last_may_be_rvi_call = _array_RW0_rdata[102]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_always_taken_0 = _array_RW0_rdata[100]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_entry_always_taken_1 = _array_RW0_rdata[101]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_1_tag = _array_RW0_rdata[99:80]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_valid = _array_RW0_rdata[239]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_brSlots_0_offset = _array_RW0_rdata[238:235]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_brSlots_0_lower = _array_RW0_rdata[234:223]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_brSlots_0_tarStat = _array_RW0_rdata[222:221]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_brSlots_0_sharing = _array_RW0_rdata[220]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_brSlots_0_valid = _array_RW0_rdata[219]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_tailSlot_offset = _array_RW0_rdata[218:215]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_tailSlot_lower = _array_RW0_rdata[214:195]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_tailSlot_tarStat = _array_RW0_rdata[194:193]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_tailSlot_sharing = _array_RW0_rdata[192]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_tailSlot_valid = _array_RW0_rdata[191]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_pftAddr = _array_RW0_rdata[190:187]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_carry = _array_RW0_rdata[186]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_isCall = _array_RW0_rdata[185]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_isRet = _array_RW0_rdata[184]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_isJalr = _array_RW0_rdata[183]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_last_may_be_rvi_call = _array_RW0_rdata[182]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_always_taken_0 = _array_RW0_rdata[180]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_entry_always_taken_1 = _array_RW0_rdata[181]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_2_tag = _array_RW0_rdata[179:160]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_valid = _array_RW0_rdata[319]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_brSlots_0_offset = _array_RW0_rdata[318:315]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_brSlots_0_lower = _array_RW0_rdata[314:303]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_brSlots_0_tarStat = _array_RW0_rdata[302:301]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_brSlots_0_sharing = _array_RW0_rdata[300]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_brSlots_0_valid = _array_RW0_rdata[299]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_tailSlot_offset = _array_RW0_rdata[298:295]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_tailSlot_lower = _array_RW0_rdata[294:275]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_tailSlot_tarStat = _array_RW0_rdata[274:273]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_tailSlot_sharing = _array_RW0_rdata[272]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_tailSlot_valid = _array_RW0_rdata[271]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_pftAddr = _array_RW0_rdata[270:267]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_carry = _array_RW0_rdata[266]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_isCall = _array_RW0_rdata[265]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_isRet = _array_RW0_rdata[264]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_isJalr = _array_RW0_rdata[263]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_last_may_be_rvi_call = _array_RW0_rdata[262]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_always_taken_0 = _array_RW0_rdata[260]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_entry_always_taken_1 = _array_RW0_rdata[261]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 + assign io_r_resp_data_3_tag = _array_RW0_rdata[259:240]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :154:45 +endmodule + diff --git a/src/FTB/array_3.sv b/src/FTB/array_3.sv new file mode 100644 index 0000000..32493ee --- /dev/null +++ b/src/FTB/array_3.sv @@ -0,0 +1,78 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module array_3( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + input [8:0] RW0_addr, + input RW0_en, + input RW0_clk, + input RW0_wmode, + input [319:0] RW0_wdata, + output [319:0] RW0_rdata, + input [3:0] RW0_wmask +); + + array_3_ext array_3_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + .RW0_addr (RW0_addr), + .RW0_en (RW0_en), + .RW0_clk (RW0_clk), + .RW0_wmode (RW0_wmode), + .RW0_wdata (RW0_wdata), + .RW0_rdata (RW0_rdata), + .RW0_wmask (RW0_wmask) + ); +endmodule + diff --git a/src/ITTAGE/ITTage.sv b/src/ITTAGE/ITTage.sv new file mode 100644 index 0000000..5820041 --- /dev/null +++ b/src/ITTAGE/ITTage.sv @@ -0,0 +1,1256 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module ITTage( // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + input clock, + input reset, + input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_3_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [8:0] io_in_bits_folded_hist_3_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [8:0] io_in_bits_folded_hist_3_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [8:0] io_in_bits_folded_hist_3_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_3_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_3_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [11:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [19:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [8:0] io_update_bits_spec_info_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [8:0] io_update_bits_spec_info_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [8:0] io_update_bits_spec_info_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_cfi_idx_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_cfi_idx_bits, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_jmp_taken, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_mispred_mask_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [218:0] io_update_bits_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_update_bits_full_target // src/main/scala/xiangshan/frontend/BPU.scala:171:14 +); + + reg [2:0] resp_meta_allocate_bits_r; // src/main/scala/xiangshan/frontend/ITTAGE.scala:516:40 + reg resp_meta_allocate_valid_r; // src/main/scala/xiangshan/frontend/ITTAGE.scala:515:40 + wire resp_meta_altDiffers; // src/main/scala/xiangshan/frontend/ITTAGE.scala:498:50 + wire _tables_4_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [1:0] _tables_4_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [1:0] _tables_4_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [38:0] _tables_4_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire _tables_3_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [1:0] _tables_3_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [1:0] _tables_3_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [38:0] _tables_3_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire _tables_2_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [1:0] _tables_2_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [1:0] _tables_2_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [38:0] _tables_2_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire _tables_1_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [1:0] _tables_1_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [1:0] _tables_1_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [38:0] _tables_1_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire _tables_0_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [1:0] _tables_0_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [1:0] _tables_0_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + wire [38:0] _tables_0_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + reg [7:0] tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 + reg s2_resps_0_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [1:0] s2_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [1:0] s2_resps_0_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [38:0] s2_resps_0_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg s2_resps_1_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [1:0] s2_resps_1_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [1:0] s2_resps_1_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [38:0] s2_resps_1_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg s2_resps_2_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [1:0] s2_resps_2_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [1:0] s2_resps_2_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [38:0] s2_resps_2_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg s2_resps_3_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [1:0] s2_resps_3_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [1:0] s2_resps_3_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [38:0] s2_resps_3_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg s2_resps_4_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [1:0] s2_resps_4_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [1:0] s2_resps_4_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg [38:0] s2_resps_4_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27 + reg s3_tageTaken_dup_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 + reg s3_tageTaken_dup_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 + reg s3_tageTaken_dup_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 + reg s3_tageTaken_dup_3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 + reg [38:0] s3_tageTarget_dup_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 + reg [38:0] s3_tageTarget_dup_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 + reg [38:0] s3_tageTarget_dup_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 + reg [38:0] s3_tageTarget_dup_3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 + reg [38:0] s3_providerTarget; // src/main/scala/xiangshan/frontend/ITTAGE.scala:396:39 + reg [38:0] s3_altProviderTarget; // src/main/scala/xiangshan/frontend/ITTAGE.scala:397:39 + reg s3_provided; // src/main/scala/xiangshan/frontend/ITTAGE.scala:398:39 + reg [2:0] s3_provider; // src/main/scala/xiangshan/frontend/ITTAGE.scala:399:39 + reg s3_altProvided; // src/main/scala/xiangshan/frontend/ITTAGE.scala:400:39 + reg [2:0] s3_altProvider; // src/main/scala/xiangshan/frontend/ITTAGE.scala:401:39 + reg s3_finalAltPred; // src/main/scala/xiangshan/frontend/ITTAGE.scala:402:39 + reg s3_providerU; // src/main/scala/xiangshan/frontend/ITTAGE.scala:403:39 + reg [1:0] s3_providerCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:404:39 + reg [1:0] s3_altProviderCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:405:39 + wire updateValid = + io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_isJalr + & ~(io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_isRet) + & io_update_valid & ~io_update_bits_ftb_entry_tailSlot_sharing + & io_update_bits_jmp_taken & io_update_bits_cfi_idx_valid + & io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/FrontendBundle.scala:655:41, src/main/scala/xiangshan/frontend/ITTAGE.scala:416:23, :417:{46,69} + assign resp_meta_altDiffers = s3_finalAltPred != s3_tageTaken_dup_3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59, :402:39, :498:50 + reg [63:0] s2_allocLFSR_lfsr; // utility/src/main/scala/utility/LFSR64.scala:27:33 + wire _GEN = + updateValid & io_update_bits_mispred_mask_2 + & ~(io_update_bits_meta[96] & io_update_bits_meta[77:39] == io_update_bits_full_target + & io_update_bits_meta[86:85] == 2'h0); // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :417:46, :421:40, :553:80, :554:47, :555:{38,41,59} + reg tables_0_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 + reg tables_0_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 + reg [38:0] tables_0_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + reg [38:0] tables_0_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + reg tables_0_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 + reg [1:0] tables_0_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 + reg tables_0_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 + reg tables_0_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 + reg tables_0_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 + reg [38:0] tables_0_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + reg [3:0] tables_0_io_update_folded_hist_REG_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + reg tables_1_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 + reg tables_1_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 + reg [38:0] tables_1_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + reg [38:0] tables_1_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + reg tables_1_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 + reg [1:0] tables_1_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 + reg tables_1_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 + reg tables_1_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 + reg tables_1_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 + reg [38:0] tables_1_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + reg [7:0] tables_1_io_update_folded_hist_REG_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + reg tables_2_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 + reg tables_2_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 + reg [38:0] tables_2_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + reg [38:0] tables_2_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + reg tables_2_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 + reg [1:0] tables_2_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 + reg tables_2_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 + reg tables_2_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 + reg tables_2_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 + reg [38:0] tables_2_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + reg [8:0] tables_2_io_update_folded_hist_REG_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + reg [7:0] tables_2_io_update_folded_hist_REG_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + reg tables_3_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 + reg tables_3_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 + reg [38:0] tables_3_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + reg [38:0] tables_3_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + reg tables_3_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 + reg [1:0] tables_3_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 + reg tables_3_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 + reg tables_3_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 + reg tables_3_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 + reg [38:0] tables_3_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + reg [8:0] tables_3_io_update_folded_hist_REG_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + reg [7:0] tables_3_io_update_folded_hist_REG_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + reg tables_4_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 + reg tables_4_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 + reg [38:0] tables_4_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + reg [38:0] tables_4_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + reg tables_4_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 + reg [1:0] tables_4_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 + reg tables_4_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 + reg tables_4_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 + reg tables_4_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 + reg [38:0] tables_4_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + reg [8:0] tables_4_io_update_folded_hist_REG_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + reg [7:0] tables_4_io_update_folded_hist_REG_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + always @(posedge clock or posedge reset) begin + if (reset) begin + tickCtr <= 8'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 + s2_allocLFSR_lfsr <= 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33 + end + else begin + if (&tickCtr) // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17 + tickCtr <= 8'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 + else if (_GEN) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:555:38 + if ((&tickCtr) & ~(io_update_bits_meta[82])) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :421:40, :557:46 + tickCtr <= 8'hFF; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 + else if (tickCtr == 8'h0 & io_update_bits_meta[82]) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:26, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :421:40 + tickCtr <= 8'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 + else if (io_update_bits_meta[82]) // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40 + tickCtr <= 8'(tickCtr - 8'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 + else // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40 + tickCtr <= 8'(tickCtr + 8'h1); // src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 + end + if (s2_allocLFSR_lfsr == 64'h0) // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:24 + s2_allocLFSR_lfsr <= 64'h1; // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:18 + else // utility/src/main/scala/utility/LFSR64.scala:31:24 + s2_allocLFSR_lfsr <= + {s2_allocLFSR_lfsr[0] ^ s2_allocLFSR_lfsr[1] ^ s2_allocLFSR_lfsr[3] + ^ s2_allocLFSR_lfsr[4], + s2_allocLFSR_lfsr[63:1]}; // utility/src/main/scala/utility/LFSR64.scala:27:33, :29:{19,29,39,43,49}, :31:{41,51} + end + end // always @(posedge, posedge) + wire [2:0] selectedInfo_res_1_first_tableIdx = {2'h0, s2_resps_1_valid}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10 + wire [2:0] selectedInfo_res_2_first_tableIdx = + s2_resps_2_valid ? 3'h2 : selectedInfo_res_1_first_tableIdx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, :450:24, utility/src/main/scala/utility/ParallelMux.scala:147:10 + wire selectedInfo_res_hasOne = s2_resps_4_valid | s2_resps_3_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16 + wire selectedInfo_res_hasTwo = s2_resps_4_valid & s2_resps_3_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:146:40 + wire selectedInfo_res_1_hasOne = s2_resps_1_valid | s2_resps_0_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16 + wire [1:0] selectedInfo_res_1_first_ctr = + s2_resps_1_valid ? s2_resps_1_bits_ctr : s2_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10 + wire [38:0] selectedInfo_res_1_first_target = + s2_resps_1_valid ? s2_resps_1_bits_target : s2_resps_0_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10 + wire selectedInfo_res_2_hasOne = s2_resps_2_valid | selectedInfo_res_1_hasOne; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16 + wire [1:0] selectedInfo_res_2_first_ctr = + s2_resps_2_valid ? s2_resps_2_bits_ctr : selectedInfo_res_1_first_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10 + wire [38:0] selectedInfo_res_2_first_target = + s2_resps_2_valid ? s2_resps_2_bits_target : selectedInfo_res_1_first_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10 + wire selectedInfo_hasOne = selectedInfo_res_hasOne | selectedInfo_res_2_hasOne; // utility/src/main/scala/utility/ParallelMux.scala:145:16 + wire selectedInfo_hasTwo = + selectedInfo_res_hasTwo | s2_resps_1_valid & s2_resps_0_valid | s2_resps_2_valid + & selectedInfo_res_1_hasOne | selectedInfo_res_hasOne & selectedInfo_res_2_hasOne; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:{28,40} + wire [1:0] selectedInfo_first_ctr = + selectedInfo_res_hasOne + ? (s2_resps_4_valid ? s2_resps_4_bits_ctr : s2_resps_3_bits_ctr) + : selectedInfo_res_2_first_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10 + wire [38:0] selectedInfo_first_target = + selectedInfo_res_hasOne + ? (s2_resps_4_valid ? s2_resps_4_bits_target : s2_resps_3_bits_target) + : selectedInfo_res_2_first_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10 + wire _selectedInfo_T_91 = selectedInfo_res_hasOne & ~selectedInfo_res_hasTwo; // utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :150:{19,22} + wire [38:0] selectedInfo_second_target = + (selectedInfo_res_hasOne + ? 39'h0 + : (s2_resps_2_valid + ? 39'h0 + : (s2_resps_1_valid ? 39'h0 : s2_resps_0_bits_target) + | (s2_resps_1_valid ? s2_resps_0_bits_target : 39'h0)) + | (s2_resps_2_valid ? selectedInfo_res_1_first_target : 39'h0)) + | (_selectedInfo_T_91 ? selectedInfo_res_2_first_target : 39'h0) + | (selectedInfo_res_hasTwo + ? (s2_resps_4_valid ? 39'h0 : s2_resps_3_bits_target) + | (s2_resps_4_valid ? s2_resps_3_bits_target : 39'h0) + : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19 + wire providerNull = selectedInfo_first_ctr == 2'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :459:39, utility/src/main/scala/utility/ParallelMux.scala:147:10 + wire _s2_tageTarget_T = providerNull & selectedInfo_hasTwo; // src/main/scala/xiangshan/frontend/ITTAGE.scala:459:39, :465:33, utility/src/main/scala/utility/ParallelMux.scala:146:28 + wire _s2_tageTarget_T_3 = selectedInfo_hasTwo & providerNull; // src/main/scala/xiangshan/frontend/ITTAGE.scala:459:39, :466:18, utility/src/main/scala/utility/ParallelMux.scala:146:28 + wire _s2_tageTaken_WIRE = + selectedInfo_hasOne & ~_s2_tageTarget_T | _s2_tageTarget_T_3 | ~selectedInfo_hasOne; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:465:{15,18,33}, :466:18, :467:6, utility/src/main/scala/utility/ParallelMux.scala:145:16 + wire [38:0] _s2_tageTarget_WIRE = + (selectedInfo_hasOne & ~_s2_tageTarget_T ? selectedInfo_first_target : 39'h0) + | (_s2_tageTarget_T_3 ? selectedInfo_second_target : 39'h0) + | (~selectedInfo_hasOne | providerNull & ~selectedInfo_hasTwo + ? io_in_bits_resp_in_0_s2_full_pred_3_jalr_target + : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :459:39, :465:33, :466:18, :467:6, :470:{15,18}, :472:{16,32,35}, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:28, :147:10 + wire _GEN_0 = + io_update_bits_meta[92] & io_update_bits_meta[86:85] == 2'h0 + & io_update_bits_mispred_mask_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :421:40, :525:80, :526:25 + wire _GEN_1 = io_update_bits_meta[95:93] == 3'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :421:40, :539:30 + wire _GEN_2 = updateValid & io_update_bits_meta[96]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:417:46, :421:40, :423:33, :520:22, :521:38, :539:30 + wire _GEN_3 = io_update_bits_meta[95:93] == 3'h1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :539:30 + wire _GEN_4 = io_update_bits_meta[95:93] == 3'h2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :539:30 + wire _GEN_5 = io_update_bits_meta[95:93] == 3'h3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :539:30 + wire _GEN_6 = io_update_bits_meta[95:93] == 3'h4; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :539:30 + wire _updateU_T_2 = + io_update_bits_meta[88] ? ~io_update_bits_mispred_mask_2 : io_update_bits_meta[87]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :542:{31,78} + wire _updateCorrect_T = io_update_bits_meta[77:39] == io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :543:61 + wire _GEN_7 = io_update_bits_meta[81:79] == 3'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :421:40, :560:34 + wire _GEN_8 = _GEN & io_update_bits_meta[82] & _GEN_7; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34 + wire _GEN_9 = io_update_bits_meta[81:79] == 3'h1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :560:34 + wire _GEN_10 = _GEN & io_update_bits_meta[82] & _GEN_9; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34 + wire _GEN_11 = io_update_bits_meta[81:79] == 3'h2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :560:34 + wire _GEN_12 = _GEN & io_update_bits_meta[82] & _GEN_11; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34 + wire _GEN_13 = io_update_bits_meta[81:79] == 3'h3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :560:34 + wire _GEN_14 = _GEN & io_update_bits_meta[82] & _GEN_13; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34 + wire _GEN_15 = io_update_bits_meta[81:79] == 3'h4; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :560:34 + wire _GEN_16 = _GEN & io_update_bits_meta[82] & _GEN_15; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34 + wire _GEN_17 = _GEN & io_update_bits_meta[82]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :563:34 + wire [2:0] selectedInfo_first_tableIdx = + selectedInfo_res_hasOne + ? (s2_resps_4_valid ? 3'h4 : 3'h3) + : selectedInfo_res_2_first_tableIdx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, :450:24, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10 + wire [1:0] selectedInfo_second_ctr = + (selectedInfo_res_hasOne + ? 2'h0 + : (s2_resps_2_valid + ? 2'h0 + : (s2_resps_1_valid ? 2'h0 : s2_resps_0_bits_ctr) + | (s2_resps_1_valid ? s2_resps_0_bits_ctr : 2'h0)) + | (s2_resps_2_valid ? selectedInfo_res_1_first_ctr : 2'h0)) + | (_selectedInfo_T_91 ? selectedInfo_res_2_first_ctr : 2'h0) + | (selectedInfo_res_hasTwo + ? (s2_resps_4_valid ? 2'h0 : s2_resps_3_bits_ctr) + | (s2_resps_4_valid ? s2_resps_3_bits_ctr : 2'h0) + : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19 + wire [7:0] _s2_allocatableSlots_T_17 = 8'h1 << selectedInfo_first_tableIdx; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/ParallelMux.scala:147:10 + wire [4:0] _GEN_18 = _s2_allocatableSlots_T_17[4:0] | _s2_allocatableSlots_T_17[5:1]; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + wire [4:0] _GEN_19 = + ~({_GEN_18[4] | selectedInfo_first_tableIdx == 3'h6 | (&selectedInfo_first_tableIdx), + _GEN_18[3:0] | _s2_allocatableSlots_T_17[5:2] | _s2_allocatableSlots_T_17[6:3] + | _s2_allocatableSlots_T_17[7:4]} & {5{selectedInfo_hasOne}}) + & {~s2_resps_4_valid & s2_resps_4_bits_u == 2'h0, + ~s2_resps_3_valid & s2_resps_3_bits_u == 2'h0, + ~s2_resps_2_valid & s2_resps_2_bits_u == 2'h0, + ~s2_resps_1_valid & s2_resps_1_bits_u == 2'h0, + ~s2_resps_0_valid & s2_resps_0_bits_u == 2'h0}; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, :509:{55,64,67,79,86}, :510:{5,55,61}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53, :145:16, :147:10 + wire [4:0] _GEN_20 = _GEN_19 & s2_allocLFSR_lfsr[4:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:509:86, :511:32, :513:60, utility/src/main/scala/utility/LFSR64.scala:27:33 + wire [2:0] s2_maskedEntry = + _GEN_20[0] + ? 3'h0 + : _GEN_20[1] + ? 3'h1 + : _GEN_20[2] ? 3'h2 : _GEN_20[3] ? 3'h3 : _GEN_20[4] ? 3'h4 : 3'h7; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :450:24, :513:60 + wire [7:0] _s2_allocEntry_T = {3'h0, _GEN_19} >> s2_maskedEntry; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :509:86, :514:47 + always @(posedge clock) begin + if (io_s1_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_resps_0_valid <= _tables_0_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_0_bits_ctr <= _tables_0_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_0_bits_u <= _tables_0_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_0_bits_target <= _tables_0_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_1_valid <= _tables_1_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_1_bits_ctr <= _tables_1_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_1_bits_u <= _tables_1_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_1_bits_target <= _tables_1_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_2_valid <= _tables_2_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_2_bits_ctr <= _tables_2_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_2_bits_u <= _tables_2_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_2_bits_target <= _tables_2_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_3_valid <= _tables_3_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_3_bits_ctr <= _tables_3_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_3_bits_u <= _tables_3_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_3_bits_target <= _tables_3_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_4_valid <= _tables_4_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_4_bits_ctr <= _tables_4_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_4_bits_u <= _tables_4_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + s2_resps_4_bits_target <= _tables_4_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27 + end + if (io_s2_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_tageTaken_dup_0 <= _s2_tageTaken_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 + s3_tageTarget_dup_0 <= _s2_tageTarget_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 + end + if (io_s2_fire_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_tageTaken_dup_1 <= _s2_tageTaken_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 + s3_tageTarget_dup_1 <= _s2_tageTarget_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 + end + if (io_s2_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_tageTaken_dup_2 <= _s2_tageTaken_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 + s3_tageTarget_dup_2 <= _s2_tageTarget_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 + end + if (io_s2_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_tageTaken_dup_3 <= _s2_tageTaken_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59 + s3_tageTarget_dup_3 <= _s2_tageTarget_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59 + s3_providerTarget <= selectedInfo_first_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:396:39, utility/src/main/scala/utility/ParallelMux.scala:147:10 + s3_altProviderTarget <= selectedInfo_second_target; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:397:39 + s3_provided <= selectedInfo_hasOne; // src/main/scala/xiangshan/frontend/ITTAGE.scala:398:39, utility/src/main/scala/utility/ParallelMux.scala:145:16 + s3_provider <= selectedInfo_first_tableIdx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:399:39, utility/src/main/scala/utility/ParallelMux.scala:147:10 + s3_altProvided <= selectedInfo_hasTwo; // src/main/scala/xiangshan/frontend/ITTAGE.scala:400:39, utility/src/main/scala/utility/ParallelMux.scala:146:28 + s3_altProvider <= + (selectedInfo_res_hasOne | ~s2_resps_2_valid + ? 3'h0 + : selectedInfo_res_1_first_tableIdx) + | (_selectedInfo_T_91 ? selectedInfo_res_2_first_tableIdx : 3'h0) + | (selectedInfo_res_hasTwo + ? (s2_resps_4_valid ? 3'h0 : 3'h3) | (s2_resps_4_valid ? 3'h3 : 3'h0) + : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, :401:39, :450:24, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19 + s3_finalAltPred <= ~selectedInfo_hasTwo | selectedInfo_second_ctr[1]; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:402:39, :474:{25,58}, utility/src/main/scala/utility/ParallelMux.scala:146:28 + s3_providerU <= + selectedInfo_res_hasOne + ? (s2_resps_4_valid ? s2_resps_4_bits_u[0] : s2_resps_3_bits_u[0]) + : s2_resps_2_valid + ? s2_resps_2_bits_u[0] + : s2_resps_1_valid ? s2_resps_1_bits_u[0] : s2_resps_0_bits_u[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, :403:39, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10 + s3_providerCtr <= selectedInfo_first_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:404:39, utility/src/main/scala/utility/ParallelMux.scala:147:10 + s3_altProviderCtr <= selectedInfo_second_ctr; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:405:39 + resp_meta_allocate_valid_r <= |_GEN_19; // src/main/scala/xiangshan/frontend/ITTAGE.scala:509:86, :515:{40,61} + resp_meta_allocate_bits_r <= + _s2_allocEntry_T[0] + ? s2_maskedEntry + : _GEN_19[0] + ? 3'h0 + : _GEN_19[1] + ? 3'h1 + : _GEN_19[2] ? 3'h2 : _GEN_19[3] ? 3'h3 : _GEN_19[4] ? 3'h4 : 3'h7; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :450:24, :509:86, :514:{27,47}, :516:40 + end + tables_0_io_update_valid_REG <= + _GEN_8 | _GEN_2 & (_GEN_1 | _GEN_0 & io_update_bits_meta[91:89] == 3'h0); // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :421:40, :423:33, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41 + tables_0_io_update_correct_REG <= _GEN_8 | _GEN_1 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43 + tables_0_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + tables_0_io_update_old_target_REG <= + _GEN_1 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46 + tables_0_io_update_alloc_REG <= _GEN_17 & _GEN_7; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41 + tables_0_io_update_oldCtr_REG <= + _GEN_1 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42 + tables_0_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43 + tables_0_io_update_uValid_REG <= _GEN_8 | _GEN_2 & _GEN_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42 + tables_0_io_update_u_REG <= ~_GEN_8 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37 + tables_0_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + tables_0_io_update_folded_hist_REG_hist_12_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + tables_1_io_update_valid_REG <= + _GEN_10 | _GEN_2 & (_GEN_3 | _GEN_0 & io_update_bits_meta[91:89] == 3'h1); // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :423:33, :450:24, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41 + tables_1_io_update_correct_REG <= _GEN_10 | _GEN_3 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43 + tables_1_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + tables_1_io_update_old_target_REG <= + _GEN_3 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46 + tables_1_io_update_alloc_REG <= _GEN_17 & _GEN_9; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41 + tables_1_io_update_oldCtr_REG <= + _GEN_3 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42 + tables_1_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43 + tables_1_io_update_uValid_REG <= _GEN_10 | _GEN_2 & _GEN_3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42 + tables_1_io_update_u_REG <= ~_GEN_10 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37 + tables_1_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + tables_1_io_update_folded_hist_REG_hist_14_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + tables_2_io_update_valid_REG <= + _GEN_12 | _GEN_2 & (_GEN_4 | _GEN_0 & io_update_bits_meta[91:89] == 3'h2); // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :423:33, :450:24, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41 + tables_2_io_update_correct_REG <= _GEN_12 | _GEN_4 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43 + tables_2_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + tables_2_io_update_old_target_REG <= + _GEN_4 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46 + tables_2_io_update_alloc_REG <= _GEN_17 & _GEN_11; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41 + tables_2_io_update_oldCtr_REG <= + _GEN_4 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42 + tables_2_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43 + tables_2_io_update_uValid_REG <= _GEN_12 | _GEN_2 & _GEN_4; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42 + tables_2_io_update_u_REG <= ~_GEN_12 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37 + tables_2_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + tables_2_io_update_folded_hist_REG_hist_13_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + tables_2_io_update_folded_hist_REG_hist_4_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + tables_3_io_update_valid_REG <= + _GEN_14 | _GEN_2 & (_GEN_5 | _GEN_0 & io_update_bits_meta[91:89] == 3'h3); // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :423:33, :450:24, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41 + tables_3_io_update_correct_REG <= _GEN_14 | _GEN_5 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43 + tables_3_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + tables_3_io_update_old_target_REG <= + _GEN_5 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46 + tables_3_io_update_alloc_REG <= _GEN_17 & _GEN_13; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41 + tables_3_io_update_oldCtr_REG <= + _GEN_5 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42 + tables_3_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43 + tables_3_io_update_uValid_REG <= _GEN_14 | _GEN_2 & _GEN_5; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42 + tables_3_io_update_u_REG <= ~_GEN_14 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37 + tables_3_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + tables_3_io_update_folded_hist_REG_hist_6_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + tables_3_io_update_folded_hist_REG_hist_2_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + tables_4_io_update_valid_REG <= + _GEN_16 | _GEN_2 & (_GEN_6 | _GEN_0 & io_update_bits_meta[91:89] == 3'h4); // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :423:33, :450:24, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41 + tables_4_io_update_correct_REG <= _GEN_16 | _GEN_6 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43 + tables_4_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + tables_4_io_update_old_target_REG <= + _GEN_6 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46 + tables_4_io_update_alloc_REG <= _GEN_17 & _GEN_15; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41 + tables_4_io_update_oldCtr_REG <= + _GEN_6 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42 + tables_4_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43 + tables_4_io_update_uValid_REG <= _GEN_16 | _GEN_2 & _GEN_6; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42 + tables_4_io_update_u_REG <= ~_GEN_16 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37 + tables_4_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + tables_4_io_update_folded_hist_REG_hist_10_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + tables_4_io_update_folded_hist_REG_hist_3_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:77]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + for (logic [6:0] i = 7'h0; i < 7'h4E; i += 7'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + end // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + tickCtr = {_RANDOM[7'hE][31:26], _RANDOM[7'hF][1:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24 + s2_resps_0_valid = _RANDOM[7'hF][2]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24, :375:27 + s2_resps_0_bits_ctr = _RANDOM[7'hF][4:3]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24, :375:27 + s2_resps_0_bits_u = _RANDOM[7'hF][6:5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24, :375:27 + s2_resps_0_bits_target = {_RANDOM[7'hF][31:7], _RANDOM[7'h10][13:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24, :375:27 + s2_resps_1_valid = _RANDOM[7'h10][14]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_1_bits_ctr = _RANDOM[7'h10][16:15]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_1_bits_u = _RANDOM[7'h10][18:17]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_1_bits_target = {_RANDOM[7'h10][31:19], _RANDOM[7'h11][25:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_2_valid = _RANDOM[7'h11][26]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_2_bits_ctr = _RANDOM[7'h11][28:27]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_2_bits_u = _RANDOM[7'h11][30:29]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_2_bits_target = + {_RANDOM[7'h11][31], _RANDOM[7'h12], _RANDOM[7'h13][5:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_3_valid = _RANDOM[7'h13][6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_3_bits_ctr = _RANDOM[7'h13][8:7]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_3_bits_u = _RANDOM[7'h13][10:9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_3_bits_target = {_RANDOM[7'h13][31:11], _RANDOM[7'h14][17:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_4_valid = _RANDOM[7'h14][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_4_bits_ctr = _RANDOM[7'h14][20:19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_4_bits_u = _RANDOM[7'h14][22:21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s2_resps_4_bits_target = {_RANDOM[7'h14][31:23], _RANDOM[7'h15][29:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27 + s3_tageTaken_dup_0 = _RANDOM[7'h19][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59 + s3_tageTaken_dup_1 = _RANDOM[7'h19][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59 + s3_tageTaken_dup_2 = _RANDOM[7'h19][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59 + s3_tageTaken_dup_3 = _RANDOM[7'h19][22]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59 + s3_tageTarget_dup_0 = {_RANDOM[7'h19][31:23], _RANDOM[7'h1A][29:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59 + s3_tageTarget_dup_1 = + {_RANDOM[7'h1A][31:30], _RANDOM[7'h1B], _RANDOM[7'h1C][4:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :395:59 + s3_tageTarget_dup_2 = {_RANDOM[7'h1C][31:5], _RANDOM[7'h1D][11:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :395:59 + s3_tageTarget_dup_3 = {_RANDOM[7'h1D][31:12], _RANDOM[7'h1E][18:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :395:59 + s3_providerTarget = {_RANDOM[7'h1E][31:19], _RANDOM[7'h1F][25:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :395:59, :396:39 + s3_altProviderTarget = {_RANDOM[7'h1F][31:26], _RANDOM[7'h20], _RANDOM[7'h21][0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :396:39, :397:39 + s3_provided = _RANDOM[7'h21][1]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :398:39 + s3_provider = _RANDOM[7'h21][4:2]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :399:39 + s3_altProvided = _RANDOM[7'h21][5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :400:39 + s3_altProvider = _RANDOM[7'h21][8:6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :401:39 + s3_finalAltPred = _RANDOM[7'h21][9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :402:39 + s3_providerU = _RANDOM[7'h21][10]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :403:39 + s3_providerCtr = _RANDOM[7'h21][12:11]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :404:39 + s3_altProviderCtr = _RANDOM[7'h21][14:13]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :405:39 + s2_allocLFSR_lfsr = {_RANDOM[7'h21][31:15], _RANDOM[7'h22], _RANDOM[7'h23][14:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, utility/src/main/scala/utility/LFSR64.scala:27:33 + resp_meta_allocate_valid_r = _RANDOM[7'h23][15]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :515:40, utility/src/main/scala/utility/LFSR64.scala:27:33 + resp_meta_allocate_bits_r = _RANDOM[7'h23][18:16]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :516:40, utility/src/main/scala/utility/LFSR64.scala:27:33 + tables_0_io_update_valid_REG = _RANDOM[7'h23][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, utility/src/main/scala/utility/LFSR64.scala:27:33 + tables_0_io_update_correct_REG = _RANDOM[7'h23][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :580:43, utility/src/main/scala/utility/LFSR64.scala:27:33 + tables_0_io_update_target_REG = {_RANDOM[7'h23][31:21], _RANDOM[7'h24][27:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, utility/src/main/scala/utility/LFSR64.scala:27:33 + tables_0_io_update_old_target_REG = + {_RANDOM[7'h24][31:28], _RANDOM[7'h25], _RANDOM[7'h26][2:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :582:46 + tables_0_io_update_alloc_REG = _RANDOM[7'h26][3]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41 + tables_0_io_update_oldCtr_REG = _RANDOM[7'h26][5:4]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42 + tables_0_io_update_reset_u_REG = _RANDOM[7'h26][6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43 + tables_0_io_update_uValid_REG = _RANDOM[7'h26][7]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42 + tables_0_io_update_u_REG = _RANDOM[7'h26][8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37 + tables_0_io_update_pc_REG = {_RANDOM[7'h26][31:9], _RANDOM[7'h27][15:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38 + tables_0_io_update_folded_hist_REG_hist_12_folded_hist = + {_RANDOM[7'h28][31:30], _RANDOM[7'h29][1:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 + tables_1_io_update_valid_REG = _RANDOM[7'h2C][4]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41 + tables_1_io_update_correct_REG = _RANDOM[7'h2C][5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :580:43 + tables_1_io_update_target_REG = {_RANDOM[7'h2C][31:6], _RANDOM[7'h2D][12:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :581:42 + tables_1_io_update_old_target_REG = {_RANDOM[7'h2D][31:13], _RANDOM[7'h2E][19:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :582:46 + tables_1_io_update_alloc_REG = _RANDOM[7'h2E][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41 + tables_1_io_update_oldCtr_REG = _RANDOM[7'h2E][22:21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42 + tables_1_io_update_reset_u_REG = _RANDOM[7'h2E][23]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43 + tables_1_io_update_uValid_REG = _RANDOM[7'h2E][24]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42 + tables_1_io_update_u_REG = _RANDOM[7'h2E][25]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37 + tables_1_io_update_pc_REG = + {_RANDOM[7'h2E][31:26], _RANDOM[7'h2F], _RANDOM[7'h30][0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38 + tables_1_io_update_folded_hist_REG_hist_14_folded_hist = + {_RANDOM[7'h30][31:30], _RANDOM[7'h31][5:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :589:38, :591:47 + tables_2_io_update_valid_REG = _RANDOM[7'h34][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41 + tables_2_io_update_correct_REG = _RANDOM[7'h34][22]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :580:43 + tables_2_io_update_target_REG = {_RANDOM[7'h34][31:23], _RANDOM[7'h35][29:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :581:42 + tables_2_io_update_old_target_REG = + {_RANDOM[7'h35][31:30], _RANDOM[7'h36], _RANDOM[7'h37][4:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :582:46 + tables_2_io_update_alloc_REG = _RANDOM[7'h37][5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41 + tables_2_io_update_oldCtr_REG = _RANDOM[7'h37][7:6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42 + tables_2_io_update_reset_u_REG = _RANDOM[7'h37][8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43 + tables_2_io_update_uValid_REG = _RANDOM[7'h37][9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42 + tables_2_io_update_u_REG = _RANDOM[7'h37][10]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37 + tables_2_io_update_pc_REG = {_RANDOM[7'h37][31:11], _RANDOM[7'h38][17:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38 + tables_2_io_update_folded_hist_REG_hist_13_folded_hist = _RANDOM[7'h39][31:23]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 + tables_2_io_update_folded_hist_REG_hist_4_folded_hist = + {_RANDOM[7'h3B][31:27], _RANDOM[7'h3C][2:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 + tables_3_io_update_valid_REG = _RANDOM[7'h3D][6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41 + tables_3_io_update_correct_REG = _RANDOM[7'h3D][7]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :580:43 + tables_3_io_update_target_REG = {_RANDOM[7'h3D][31:8], _RANDOM[7'h3E][14:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :581:42 + tables_3_io_update_old_target_REG = {_RANDOM[7'h3E][31:15], _RANDOM[7'h3F][21:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :582:46 + tables_3_io_update_alloc_REG = _RANDOM[7'h3F][22]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41 + tables_3_io_update_oldCtr_REG = _RANDOM[7'h3F][24:23]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42 + tables_3_io_update_reset_u_REG = _RANDOM[7'h3F][25]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43 + tables_3_io_update_uValid_REG = _RANDOM[7'h3F][26]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42 + tables_3_io_update_u_REG = _RANDOM[7'h3F][27]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37 + tables_3_io_update_pc_REG = + {_RANDOM[7'h3F][31:28], _RANDOM[7'h40], _RANDOM[7'h41][2:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38 + tables_3_io_update_folded_hist_REG_hist_6_folded_hist = + {_RANDOM[7'h43][31:28], _RANDOM[7'h44][4:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 + tables_3_io_update_folded_hist_REG_hist_2_folded_hist = + {_RANDOM[7'h44][31:28], _RANDOM[7'h45][3:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 + tables_4_io_update_valid_REG = _RANDOM[7'h45][23]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :591:47 + tables_4_io_update_correct_REG = _RANDOM[7'h45][24]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :580:43, :591:47 + tables_4_io_update_target_REG = {_RANDOM[7'h45][31:25], _RANDOM[7'h46]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :591:47 + tables_4_io_update_old_target_REG = {_RANDOM[7'h47], _RANDOM[7'h48][6:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46 + tables_4_io_update_alloc_REG = _RANDOM[7'h48][7]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41 + tables_4_io_update_oldCtr_REG = _RANDOM[7'h48][9:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42 + tables_4_io_update_reset_u_REG = _RANDOM[7'h48][10]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43 + tables_4_io_update_uValid_REG = _RANDOM[7'h48][11]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42 + tables_4_io_update_u_REG = _RANDOM[7'h48][12]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37 + tables_4_io_update_pc_REG = {_RANDOM[7'h48][31:13], _RANDOM[7'h49][19:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38 + tables_4_io_update_folded_hist_REG_hist_10_folded_hist = _RANDOM[7'h4B][22:14]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 + tables_4_io_update_folded_hist_REG_hist_3_folded_hist = _RANDOM[7'h4D][12:5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + tickCtr = 8'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24 + s2_allocLFSR_lfsr = 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + ITTageTable tables_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_12_folded_hist + (io_in_bits_folded_hist_3_hist_12_folded_hist), + .io_resp_valid (_tables_0_io_resp_valid), + .io_resp_bits_ctr (_tables_0_io_resp_bits_ctr), + .io_resp_bits_u (_tables_0_io_resp_bits_u), + .io_resp_bits_target (_tables_0_io_resp_bits_target), + .io_update_pc (tables_0_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + .io_update_folded_hist_hist_12_folded_hist + (tables_0_io_update_folded_hist_REG_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + .io_update_valid (tables_0_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 + .io_update_correct (tables_0_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 + .io_update_alloc (tables_0_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 + .io_update_oldCtr (tables_0_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 + .io_update_uValid (tables_0_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 + .io_update_u (tables_0_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 + .io_update_reset_u (tables_0_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 + .io_update_target (tables_0_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + .io_update_old_target (tables_0_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + ); + ITTageTable_1 tables_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_14_folded_hist + (io_in_bits_folded_hist_3_hist_14_folded_hist), + .io_resp_valid (_tables_1_io_resp_valid), + .io_resp_bits_ctr (_tables_1_io_resp_bits_ctr), + .io_resp_bits_u (_tables_1_io_resp_bits_u), + .io_resp_bits_target (_tables_1_io_resp_bits_target), + .io_update_pc (tables_1_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + .io_update_folded_hist_hist_14_folded_hist + (tables_1_io_update_folded_hist_REG_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + .io_update_valid (tables_1_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 + .io_update_correct (tables_1_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 + .io_update_alloc (tables_1_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 + .io_update_oldCtr (tables_1_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 + .io_update_uValid (tables_1_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 + .io_update_u (tables_1_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 + .io_update_reset_u (tables_1_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 + .io_update_target (tables_1_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + .io_update_old_target (tables_1_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + ); + ITTageTable_2 tables_2 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_13_folded_hist + (io_in_bits_folded_hist_3_hist_13_folded_hist), + .io_req_bits_folded_hist_hist_4_folded_hist + (io_in_bits_folded_hist_3_hist_4_folded_hist), + .io_resp_valid (_tables_2_io_resp_valid), + .io_resp_bits_ctr (_tables_2_io_resp_bits_ctr), + .io_resp_bits_u (_tables_2_io_resp_bits_u), + .io_resp_bits_target (_tables_2_io_resp_bits_target), + .io_update_pc (tables_2_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + .io_update_folded_hist_hist_13_folded_hist + (tables_2_io_update_folded_hist_REG_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + .io_update_folded_hist_hist_4_folded_hist + (tables_2_io_update_folded_hist_REG_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + .io_update_valid (tables_2_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 + .io_update_correct (tables_2_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 + .io_update_alloc (tables_2_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 + .io_update_oldCtr (tables_2_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 + .io_update_uValid (tables_2_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 + .io_update_u (tables_2_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 + .io_update_reset_u (tables_2_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 + .io_update_target (tables_2_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + .io_update_old_target (tables_2_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + ); + ITTageTable_3 tables_3 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_6_folded_hist + (io_in_bits_folded_hist_3_hist_6_folded_hist), + .io_req_bits_folded_hist_hist_2_folded_hist + (io_in_bits_folded_hist_3_hist_2_folded_hist), + .io_resp_valid (_tables_3_io_resp_valid), + .io_resp_bits_ctr (_tables_3_io_resp_bits_ctr), + .io_resp_bits_u (_tables_3_io_resp_bits_u), + .io_resp_bits_target (_tables_3_io_resp_bits_target), + .io_update_pc (tables_3_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + .io_update_folded_hist_hist_6_folded_hist + (tables_3_io_update_folded_hist_REG_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + .io_update_folded_hist_hist_2_folded_hist + (tables_3_io_update_folded_hist_REG_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + .io_update_valid (tables_3_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 + .io_update_correct (tables_3_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 + .io_update_alloc (tables_3_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 + .io_update_oldCtr (tables_3_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 + .io_update_uValid (tables_3_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 + .io_update_u (tables_3_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 + .io_update_reset_u (tables_3_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 + .io_update_target (tables_3_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + .io_update_old_target (tables_3_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + ); + ITTageTable_4 tables_4 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21 + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_10_folded_hist + (io_in_bits_folded_hist_3_hist_10_folded_hist), + .io_req_bits_folded_hist_hist_3_folded_hist + (io_in_bits_folded_hist_3_hist_3_folded_hist), + .io_resp_valid (_tables_4_io_resp_valid), + .io_resp_bits_ctr (_tables_4_io_resp_bits_ctr), + .io_resp_bits_u (_tables_4_io_resp_bits_u), + .io_resp_bits_target (_tables_4_io_resp_bits_target), + .io_update_pc (tables_4_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38 + .io_update_folded_hist_hist_10_folded_hist + (tables_4_io_update_folded_hist_REG_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + .io_update_folded_hist_hist_3_folded_hist + (tables_4_io_update_folded_hist_REG_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47 + .io_update_valid (tables_4_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41 + .io_update_correct (tables_4_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43 + .io_update_alloc (tables_4_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41 + .io_update_oldCtr (tables_4_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42 + .io_update_uValid (tables_4_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42 + .io_update_u (tables_4_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37 + .io_update_reset_u (tables_4_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43 + .io_update_target (tables_4_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42 + .io_update_old_target (tables_4_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46 + ); + assign io_out_s2_full_pred_0_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_0_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_0_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_0_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_0_targets_1 = io_in_bits_resp_in_0_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_0_jalr_target = + io_in_bits_resp_in_0_s2_full_pred_0_jalr_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_0_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_0_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_1_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_1_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_1_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_1_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_1_targets_1 = io_in_bits_resp_in_0_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_1_jalr_target = + io_in_bits_resp_in_0_s2_full_pred_1_jalr_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_1_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_1_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_targets_1 = io_in_bits_resp_in_0_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_jalr_target = + io_in_bits_resp_in_0_s2_full_pred_2_jalr_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_is_jalr = io_in_bits_resp_in_0_s2_full_pred_2_is_jalr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_is_call = io_in_bits_resp_in_0_s2_full_pred_2_is_call; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_is_ret = io_in_bits_resp_in_0_s2_full_pred_2_is_ret; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_last_may_be_rvi_call = + io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_3_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_3_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_3_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_3_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_3_targets_1 = io_in_bits_resp_in_0_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_3_jalr_target = + io_in_bits_resp_in_0_s2_full_pred_3_jalr_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_3_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_3_fallThroughErr = + io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_3_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_0_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_0_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_0_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_0_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_0_targets_1 = io_in_bits_resp_in_0_s3_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_0_jalr_target = + s3_tageTaken_dup_0 + ? s3_tageTarget_dup_0 + : io_in_bits_resp_in_0_s3_full_pred_0_jalr_target; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59, :490:26, :491:24 + assign io_out_s3_full_pred_0_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_0_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_0_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_1_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_1_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_1_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_1_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_1_targets_1 = io_in_bits_resp_in_0_s3_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_1_jalr_target = + s3_tageTaken_dup_1 + ? s3_tageTarget_dup_1 + : io_in_bits_resp_in_0_s3_full_pred_1_jalr_target; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59, :490:26, :491:24 + assign io_out_s3_full_pred_1_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_1_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_1_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_2_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_2_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_2_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_2_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_2_targets_1 = io_in_bits_resp_in_0_s3_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_2_jalr_target = + s3_tageTaken_dup_2 + ? s3_tageTarget_dup_2 + : io_in_bits_resp_in_0_s3_full_pred_2_jalr_target; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59, :490:26, :491:24 + assign io_out_s3_full_pred_2_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_2_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_2_is_jalr = io_in_bits_resp_in_0_s3_full_pred_2_is_jalr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_2_is_call = io_in_bits_resp_in_0_s3_full_pred_2_is_call; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_2_is_ret = io_in_bits_resp_in_0_s3_full_pred_2_is_ret; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_2_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_3_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_3_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_3_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_3_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_3_targets_1 = io_in_bits_resp_in_0_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_3_jalr_target = + s3_tageTaken_dup_3 + ? s3_tageTarget_dup_3 + : io_in_bits_resp_in_0_s3_full_pred_3_jalr_target; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59, :490:26, :491:24 + assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_3_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_3_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_3_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_meta = + {122'h0, + s3_provided, + s3_provider, + s3_altProvided, + s3_altProvider, + resp_meta_altDiffers, + s3_providerU, + s3_providerCtr, + s3_altProviderCtr, + resp_meta_allocate_valid_r, + resp_meta_allocate_bits_r, + s3_tageTaken_dup_3, + s3_providerTarget, + s3_altProviderTarget}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :396:39, :397:39, :398:39, :399:39, :400:39, :401:39, :403:39, :404:39, :405:39, :410:26, :498:50, :515:40, :516:40 + assign io_out_last_stage_ftb_entry_valid = + io_in_bits_resp_in_0_last_stage_ftb_entry_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_brSlots_0_offset = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_brSlots_0_lower = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_brSlots_0_tarStat = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_brSlots_0_sharing = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_brSlots_0_valid = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_tailSlot_offset = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_tailSlot_lower = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_tailSlot_tarStat = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_tailSlot_sharing = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_tailSlot_valid = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_pftAddr = + io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_carry = + io_in_bits_resp_in_0_last_stage_ftb_entry_carry; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_isCall = + io_in_bits_resp_in_0_last_stage_ftb_entry_isCall; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_isRet = + io_in_bits_resp_in_0_last_stage_ftb_entry_isRet; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_isJalr = + io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_last_may_be_rvi_call = + io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_always_taken_0 = + io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 + assign io_out_last_stage_ftb_entry_always_taken_1 = + io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7 +endmodule + diff --git a/src/ITTAGE/ITTageTable.sv b/src/ITTAGE/ITTageTable.sv new file mode 100644 index 0000000..cc9b2c6 --- /dev/null +++ b/src/ITTAGE/ITTageTable.sv @@ -0,0 +1,502 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module ITTageTable( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + input clock, + input reset, + input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [3:0] io_req_bits_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [3:0] io_update_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 +); + + wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 + wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + reg [255:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + wire [3:0] _GEN = io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 + wire [7:0] s0_idx = {io_req_bits_pc[8:5], _GEN}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:{31,40} + reg [7:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36 + reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68 + reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 + reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 + wire [6:0] _table_banks_1_io_r_req_bits_setIdx_T = {io_req_bits_pc[8:5], _GEN[3:1]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + wire [255:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31 + reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 + reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 + wire [3:0] _GEN_0 = io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 + wire [7:0] update_idx = {io_update_pc[8:5], _GEN_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:{31,40} + wire [8:0] update_wdata_tag = + {io_update_pc[17:14], + {io_update_pc[13], io_update_pc[12:9] ^ io_update_folded_hist_hist_12_folded_hist} + ^ {io_update_folded_hist_hist_12_folded_hist, 1'h0}}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75,82}, :207:43 + wire [6:0] update_idx_in_bank = {io_update_pc[8:5], _GEN_0[3:1]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + assign _resp_invalid_by_write_WIRE = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48 + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(_GEN_0[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33 + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & _GEN_0[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33 + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20 + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20 + wire [1:0] update_wdata_ctr = + io_update_alloc + ? 2'h2 + : (&old_ctr) & io_update_correct + ? 2'h3 + : update_wdata_ctr_oldSatNotTaken & ~io_update_correct + ? 2'h0 + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28 + wire [38:0] update_wdata_target = + io_update_alloc | update_wdata_ctr_oldSatNotTaken + ? io_update_target + : io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46} + wire [255:0] _validArray_T = + {io_update_valid & (&update_idx) | validArray[255], + io_update_valid & update_idx == 8'hFE | validArray[254], + io_update_valid & update_idx == 8'hFD | validArray[253], + io_update_valid & update_idx == 8'hFC | validArray[252], + io_update_valid & update_idx == 8'hFB | validArray[251], + io_update_valid & update_idx == 8'hFA | validArray[250], + io_update_valid & update_idx == 8'hF9 | validArray[249], + io_update_valid & update_idx == 8'hF8 | validArray[248], + io_update_valid & update_idx == 8'hF7 | validArray[247], + io_update_valid & update_idx == 8'hF6 | validArray[246], + io_update_valid & update_idx == 8'hF5 | validArray[245], + io_update_valid & update_idx == 8'hF4 | validArray[244], + io_update_valid & update_idx == 8'hF3 | validArray[243], + io_update_valid & update_idx == 8'hF2 | validArray[242], + io_update_valid & update_idx == 8'hF1 | validArray[241], + io_update_valid & update_idx == 8'hF0 | validArray[240], + io_update_valid & update_idx == 8'hEF | validArray[239], + io_update_valid & update_idx == 8'hEE | validArray[238], + io_update_valid & update_idx == 8'hED | validArray[237], + io_update_valid & update_idx == 8'hEC | validArray[236], + io_update_valid & update_idx == 8'hEB | validArray[235], + io_update_valid & update_idx == 8'hEA | validArray[234], + io_update_valid & update_idx == 8'hE9 | validArray[233], + io_update_valid & update_idx == 8'hE8 | validArray[232], + io_update_valid & update_idx == 8'hE7 | validArray[231], + io_update_valid & update_idx == 8'hE6 | validArray[230], + io_update_valid & update_idx == 8'hE5 | validArray[229], + io_update_valid & update_idx == 8'hE4 | validArray[228], + io_update_valid & update_idx == 8'hE3 | validArray[227], + io_update_valid & update_idx == 8'hE2 | validArray[226], + io_update_valid & update_idx == 8'hE1 | validArray[225], + io_update_valid & update_idx == 8'hE0 | validArray[224], + io_update_valid & update_idx == 8'hDF | validArray[223], + io_update_valid & update_idx == 8'hDE | validArray[222], + io_update_valid & update_idx == 8'hDD | validArray[221], + io_update_valid & update_idx == 8'hDC | validArray[220], + io_update_valid & update_idx == 8'hDB | validArray[219], + io_update_valid & update_idx == 8'hDA | validArray[218], + io_update_valid & update_idx == 8'hD9 | validArray[217], + io_update_valid & update_idx == 8'hD8 | validArray[216], + io_update_valid & update_idx == 8'hD7 | validArray[215], + io_update_valid & update_idx == 8'hD6 | validArray[214], + io_update_valid & update_idx == 8'hD5 | validArray[213], + io_update_valid & update_idx == 8'hD4 | validArray[212], + io_update_valid & update_idx == 8'hD3 | validArray[211], + io_update_valid & update_idx == 8'hD2 | validArray[210], + io_update_valid & update_idx == 8'hD1 | validArray[209], + io_update_valid & update_idx == 8'hD0 | validArray[208], + io_update_valid & update_idx == 8'hCF | validArray[207], + io_update_valid & update_idx == 8'hCE | validArray[206], + io_update_valid & update_idx == 8'hCD | validArray[205], + io_update_valid & update_idx == 8'hCC | validArray[204], + io_update_valid & update_idx == 8'hCB | validArray[203], + io_update_valid & update_idx == 8'hCA | validArray[202], + io_update_valid & update_idx == 8'hC9 | validArray[201], + io_update_valid & update_idx == 8'hC8 | validArray[200], + io_update_valid & update_idx == 8'hC7 | validArray[199], + io_update_valid & update_idx == 8'hC6 | validArray[198], + io_update_valid & update_idx == 8'hC5 | validArray[197], + io_update_valid & update_idx == 8'hC4 | validArray[196], + io_update_valid & update_idx == 8'hC3 | validArray[195], + io_update_valid & update_idx == 8'hC2 | validArray[194], + io_update_valid & update_idx == 8'hC1 | validArray[193], + io_update_valid & update_idx == 8'hC0 | validArray[192], + io_update_valid & update_idx == 8'hBF | validArray[191], + io_update_valid & update_idx == 8'hBE | validArray[190], + io_update_valid & update_idx == 8'hBD | validArray[189], + io_update_valid & update_idx == 8'hBC | validArray[188], + io_update_valid & update_idx == 8'hBB | validArray[187], + io_update_valid & update_idx == 8'hBA | validArray[186], + io_update_valid & update_idx == 8'hB9 | validArray[185], + io_update_valid & update_idx == 8'hB8 | validArray[184], + io_update_valid & update_idx == 8'hB7 | validArray[183], + io_update_valid & update_idx == 8'hB6 | validArray[182], + io_update_valid & update_idx == 8'hB5 | validArray[181], + io_update_valid & update_idx == 8'hB4 | validArray[180], + io_update_valid & update_idx == 8'hB3 | validArray[179], + io_update_valid & update_idx == 8'hB2 | validArray[178], + io_update_valid & update_idx == 8'hB1 | validArray[177], + io_update_valid & update_idx == 8'hB0 | validArray[176], + io_update_valid & update_idx == 8'hAF | validArray[175], + io_update_valid & update_idx == 8'hAE | validArray[174], + io_update_valid & update_idx == 8'hAD | validArray[173], + io_update_valid & update_idx == 8'hAC | validArray[172], + io_update_valid & update_idx == 8'hAB | validArray[171], + io_update_valid & update_idx == 8'hAA | validArray[170], + io_update_valid & update_idx == 8'hA9 | validArray[169], + io_update_valid & update_idx == 8'hA8 | validArray[168], + io_update_valid & update_idx == 8'hA7 | validArray[167], + io_update_valid & update_idx == 8'hA6 | validArray[166], + io_update_valid & update_idx == 8'hA5 | validArray[165], + io_update_valid & update_idx == 8'hA4 | validArray[164], + io_update_valid & update_idx == 8'hA3 | validArray[163], + io_update_valid & update_idx == 8'hA2 | validArray[162], + io_update_valid & update_idx == 8'hA1 | validArray[161], + io_update_valid & update_idx == 8'hA0 | validArray[160], + io_update_valid & update_idx == 8'h9F | validArray[159], + io_update_valid & update_idx == 8'h9E | validArray[158], + io_update_valid & update_idx == 8'h9D | validArray[157], + io_update_valid & update_idx == 8'h9C | validArray[156], + io_update_valid & update_idx == 8'h9B | validArray[155], + io_update_valid & update_idx == 8'h9A | validArray[154], + io_update_valid & update_idx == 8'h99 | validArray[153], + io_update_valid & update_idx == 8'h98 | validArray[152], + io_update_valid & update_idx == 8'h97 | validArray[151], + io_update_valid & update_idx == 8'h96 | validArray[150], + io_update_valid & update_idx == 8'h95 | validArray[149], + io_update_valid & update_idx == 8'h94 | validArray[148], + io_update_valid & update_idx == 8'h93 | validArray[147], + io_update_valid & update_idx == 8'h92 | validArray[146], + io_update_valid & update_idx == 8'h91 | validArray[145], + io_update_valid & update_idx == 8'h90 | validArray[144], + io_update_valid & update_idx == 8'h8F | validArray[143], + io_update_valid & update_idx == 8'h8E | validArray[142], + io_update_valid & update_idx == 8'h8D | validArray[141], + io_update_valid & update_idx == 8'h8C | validArray[140], + io_update_valid & update_idx == 8'h8B | validArray[139], + io_update_valid & update_idx == 8'h8A | validArray[138], + io_update_valid & update_idx == 8'h89 | validArray[137], + io_update_valid & update_idx == 8'h88 | validArray[136], + io_update_valid & update_idx == 8'h87 | validArray[135], + io_update_valid & update_idx == 8'h86 | validArray[134], + io_update_valid & update_idx == 8'h85 | validArray[133], + io_update_valid & update_idx == 8'h84 | validArray[132], + io_update_valid & update_idx == 8'h83 | validArray[131], + io_update_valid & update_idx == 8'h82 | validArray[130], + io_update_valid & update_idx == 8'h81 | validArray[129], + io_update_valid & update_idx == 8'h80 | validArray[128], + io_update_valid & update_idx == 8'h7F | validArray[127], + io_update_valid & update_idx == 8'h7E | validArray[126], + io_update_valid & update_idx == 8'h7D | validArray[125], + io_update_valid & update_idx == 8'h7C | validArray[124], + io_update_valid & update_idx == 8'h7B | validArray[123], + io_update_valid & update_idx == 8'h7A | validArray[122], + io_update_valid & update_idx == 8'h79 | validArray[121], + io_update_valid & update_idx == 8'h78 | validArray[120], + io_update_valid & update_idx == 8'h77 | validArray[119], + io_update_valid & update_idx == 8'h76 | validArray[118], + io_update_valid & update_idx == 8'h75 | validArray[117], + io_update_valid & update_idx == 8'h74 | validArray[116], + io_update_valid & update_idx == 8'h73 | validArray[115], + io_update_valid & update_idx == 8'h72 | validArray[114], + io_update_valid & update_idx == 8'h71 | validArray[113], + io_update_valid & update_idx == 8'h70 | validArray[112], + io_update_valid & update_idx == 8'h6F | validArray[111], + io_update_valid & update_idx == 8'h6E | validArray[110], + io_update_valid & update_idx == 8'h6D | validArray[109], + io_update_valid & update_idx == 8'h6C | validArray[108], + io_update_valid & update_idx == 8'h6B | validArray[107], + io_update_valid & update_idx == 8'h6A | validArray[106], + io_update_valid & update_idx == 8'h69 | validArray[105], + io_update_valid & update_idx == 8'h68 | validArray[104], + io_update_valid & update_idx == 8'h67 | validArray[103], + io_update_valid & update_idx == 8'h66 | validArray[102], + io_update_valid & update_idx == 8'h65 | validArray[101], + io_update_valid & update_idx == 8'h64 | validArray[100], + io_update_valid & update_idx == 8'h63 | validArray[99], + io_update_valid & update_idx == 8'h62 | validArray[98], + io_update_valid & update_idx == 8'h61 | validArray[97], + io_update_valid & update_idx == 8'h60 | validArray[96], + io_update_valid & update_idx == 8'h5F | validArray[95], + io_update_valid & update_idx == 8'h5E | validArray[94], + io_update_valid & update_idx == 8'h5D | validArray[93], + io_update_valid & update_idx == 8'h5C | validArray[92], + io_update_valid & update_idx == 8'h5B | validArray[91], + io_update_valid & update_idx == 8'h5A | validArray[90], + io_update_valid & update_idx == 8'h59 | validArray[89], + io_update_valid & update_idx == 8'h58 | validArray[88], + io_update_valid & update_idx == 8'h57 | validArray[87], + io_update_valid & update_idx == 8'h56 | validArray[86], + io_update_valid & update_idx == 8'h55 | validArray[85], + io_update_valid & update_idx == 8'h54 | validArray[84], + io_update_valid & update_idx == 8'h53 | validArray[83], + io_update_valid & update_idx == 8'h52 | validArray[82], + io_update_valid & update_idx == 8'h51 | validArray[81], + io_update_valid & update_idx == 8'h50 | validArray[80], + io_update_valid & update_idx == 8'h4F | validArray[79], + io_update_valid & update_idx == 8'h4E | validArray[78], + io_update_valid & update_idx == 8'h4D | validArray[77], + io_update_valid & update_idx == 8'h4C | validArray[76], + io_update_valid & update_idx == 8'h4B | validArray[75], + io_update_valid & update_idx == 8'h4A | validArray[74], + io_update_valid & update_idx == 8'h49 | validArray[73], + io_update_valid & update_idx == 8'h48 | validArray[72], + io_update_valid & update_idx == 8'h47 | validArray[71], + io_update_valid & update_idx == 8'h46 | validArray[70], + io_update_valid & update_idx == 8'h45 | validArray[69], + io_update_valid & update_idx == 8'h44 | validArray[68], + io_update_valid & update_idx == 8'h43 | validArray[67], + io_update_valid & update_idx == 8'h42 | validArray[66], + io_update_valid & update_idx == 8'h41 | validArray[65], + io_update_valid & update_idx == 8'h40 | validArray[64], + io_update_valid & update_idx == 8'h3F | validArray[63], + io_update_valid & update_idx == 8'h3E | validArray[62], + io_update_valid & update_idx == 8'h3D | validArray[61], + io_update_valid & update_idx == 8'h3C | validArray[60], + io_update_valid & update_idx == 8'h3B | validArray[59], + io_update_valid & update_idx == 8'h3A | validArray[58], + io_update_valid & update_idx == 8'h39 | validArray[57], + io_update_valid & update_idx == 8'h38 | validArray[56], + io_update_valid & update_idx == 8'h37 | validArray[55], + io_update_valid & update_idx == 8'h36 | validArray[54], + io_update_valid & update_idx == 8'h35 | validArray[53], + io_update_valid & update_idx == 8'h34 | validArray[52], + io_update_valid & update_idx == 8'h33 | validArray[51], + io_update_valid & update_idx == 8'h32 | validArray[50], + io_update_valid & update_idx == 8'h31 | validArray[49], + io_update_valid & update_idx == 8'h30 | validArray[48], + io_update_valid & update_idx == 8'h2F | validArray[47], + io_update_valid & update_idx == 8'h2E | validArray[46], + io_update_valid & update_idx == 8'h2D | validArray[45], + io_update_valid & update_idx == 8'h2C | validArray[44], + io_update_valid & update_idx == 8'h2B | validArray[43], + io_update_valid & update_idx == 8'h2A | validArray[42], + io_update_valid & update_idx == 8'h29 | validArray[41], + io_update_valid & update_idx == 8'h28 | validArray[40], + io_update_valid & update_idx == 8'h27 | validArray[39], + io_update_valid & update_idx == 8'h26 | validArray[38], + io_update_valid & update_idx == 8'h25 | validArray[37], + io_update_valid & update_idx == 8'h24 | validArray[36], + io_update_valid & update_idx == 8'h23 | validArray[35], + io_update_valid & update_idx == 8'h22 | validArray[34], + io_update_valid & update_idx == 8'h21 | validArray[33], + io_update_valid & update_idx == 8'h20 | validArray[32], + io_update_valid & update_idx == 8'h1F | validArray[31], + io_update_valid & update_idx == 8'h1E | validArray[30], + io_update_valid & update_idx == 8'h1D | validArray[29], + io_update_valid & update_idx == 8'h1C | validArray[28], + io_update_valid & update_idx == 8'h1B | validArray[27], + io_update_valid & update_idx == 8'h1A | validArray[26], + io_update_valid & update_idx == 8'h19 | validArray[25], + io_update_valid & update_idx == 8'h18 | validArray[24], + io_update_valid & update_idx == 8'h17 | validArray[23], + io_update_valid & update_idx == 8'h16 | validArray[22], + io_update_valid & update_idx == 8'h15 | validArray[21], + io_update_valid & update_idx == 8'h14 | validArray[20], + io_update_valid & update_idx == 8'h13 | validArray[19], + io_update_valid & update_idx == 8'h12 | validArray[18], + io_update_valid & update_idx == 8'h11 | validArray[17], + io_update_valid & update_idx == 8'h10 | validArray[16], + io_update_valid & update_idx == 8'hF | validArray[15], + io_update_valid & update_idx == 8'hE | validArray[14], + io_update_valid & update_idx == 8'hD | validArray[13], + io_update_valid & update_idx == 8'hC | validArray[12], + io_update_valid & update_idx == 8'hB | validArray[11], + io_update_valid & update_idx == 8'hA | validArray[10], + io_update_valid & update_idx == 8'h9 | validArray[9], + io_update_valid & update_idx == 8'h8 | validArray[8], + io_update_valid & update_idx == 8'h7 | validArray[7], + io_update_valid & update_idx == 8'h6 | validArray[6], + io_update_valid & update_idx == 8'h5 | validArray[5], + io_update_valid & update_idx == 8'h4 | validArray[4], + io_update_valid & update_idx == 8'h3 | validArray[3], + io_update_valid & update_idx == 8'h2 | validArray[2], + io_update_valid & update_idx == 8'h1 | validArray[1], + io_update_valid & update_idx == 8'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40, :200:27, :283:{30,42}, :284:26, :285:31, :286:33 + always @(posedge clock or posedge reset) begin + if (reset) + validArray <= 256'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33 + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40, :213:36 + s1_tag <= + {io_req_bits_pc[17:14], + {io_req_bits_pc[13], + io_req_bits_pc[12:9] ^ io_req_bits_folded_hist_hist_12_folded_hist} + ^ {io_req_bits_folded_hist_hist_12_folded_hist, 1'h0}}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75,82}, :207:43, :213:68 + s1_bank_req_1h_0 <= ~(_GEN[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33 + s1_bank_req_1h_1 <= _GEN[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33 + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + for (logic [3:0] i = 4'h0; i < 4'h9; i += 4'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + validArray = + {_RANDOM[4'h0], + _RANDOM[4'h1], + _RANDOM[4'h2], + _RANDOM[4'h3], + _RANDOM[4'h4], + _RANDOM[4'h5], + _RANDOM[4'h6], + _RANDOM[4'h7]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27 + s1_idx = _RANDOM[4'h8][7:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36 + s1_tag = _RANDOM[4'h8][16:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68} + s1_bank_req_1h_0 = _RANDOM[4'h8][17]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 + s1_bank_req_1h_1 = _RANDOM[4'h8][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 + s1_bank_has_write_on_this_req_0 = _RANDOM[4'h8][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + s1_bank_has_write_on_this_req_1 = _RANDOM[4'h8][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + `endif // RANDOMIZE_REG_INIT + if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + validArray = 256'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Folded1WDataModuleTemplate us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + .clock (clock), + .reset (reset), + .io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40 + .io_rdata_0 (_us_io_rdata_0), + .io_wen (io_update_uValid), + .io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40 + .io_wdata (io_update_u), + .io_resetEn (io_update_reset_u) + ); + FoldedSRAMTemplate_21 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & ~(_GEN[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50 + .io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40 + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 + .io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40 + .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:82 + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + ); + FoldedSRAMTemplate_21 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & _GEN[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50 + .io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40 + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 + .io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:40 + .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:82 + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + ); + WrBypass_41 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + .clock (clock), + .reset (reset), + .io_wen (io_update_valid), + .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:40 + .io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_hit (_wrbypass_io_hit), + .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) + ); + assign io_resp_valid = + _s1_req_rhit_T[0] + & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag + & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53} + assign io_resp_bits_ctr = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18 + assign io_resp_bits_target = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 +endmodule + diff --git a/src/ITTAGE/ITTageTable_1.sv b/src/ITTAGE/ITTageTable_1.sv new file mode 100644 index 0000000..15668b3 --- /dev/null +++ b/src/ITTAGE/ITTageTable_1.sv @@ -0,0 +1,496 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module ITTageTable_1( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + input clock, + input reset, + input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [7:0] io_req_bits_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [7:0] io_update_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 +); + + wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 + wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + reg [255:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + wire [7:0] s0_idx = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 + reg [7:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36 + reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68 + reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 + reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 + wire [255:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31 + reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 + reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 + wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 + wire [8:0] update_wdata_tag = + {io_update_pc[17], io_update_pc[16:9] ^ io_update_folded_hist_hist_14_folded_hist} + ^ {io_update_folded_hist_hist_14_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43 + assign _resp_invalid_by_write_WIRE = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48 + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33 + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33 + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20 + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20 + wire [1:0] update_wdata_ctr = + io_update_alloc + ? 2'h2 + : (&old_ctr) & io_update_correct + ? 2'h3 + : update_wdata_ctr_oldSatNotTaken & ~io_update_correct + ? 2'h0 + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28 + wire [38:0] update_wdata_target = + io_update_alloc | update_wdata_ctr_oldSatNotTaken + ? io_update_target + : io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46} + wire [255:0] _validArray_T = + {io_update_valid & (&update_idx) | validArray[255], + io_update_valid & update_idx == 8'hFE | validArray[254], + io_update_valid & update_idx == 8'hFD | validArray[253], + io_update_valid & update_idx == 8'hFC | validArray[252], + io_update_valid & update_idx == 8'hFB | validArray[251], + io_update_valid & update_idx == 8'hFA | validArray[250], + io_update_valid & update_idx == 8'hF9 | validArray[249], + io_update_valid & update_idx == 8'hF8 | validArray[248], + io_update_valid & update_idx == 8'hF7 | validArray[247], + io_update_valid & update_idx == 8'hF6 | validArray[246], + io_update_valid & update_idx == 8'hF5 | validArray[245], + io_update_valid & update_idx == 8'hF4 | validArray[244], + io_update_valid & update_idx == 8'hF3 | validArray[243], + io_update_valid & update_idx == 8'hF2 | validArray[242], + io_update_valid & update_idx == 8'hF1 | validArray[241], + io_update_valid & update_idx == 8'hF0 | validArray[240], + io_update_valid & update_idx == 8'hEF | validArray[239], + io_update_valid & update_idx == 8'hEE | validArray[238], + io_update_valid & update_idx == 8'hED | validArray[237], + io_update_valid & update_idx == 8'hEC | validArray[236], + io_update_valid & update_idx == 8'hEB | validArray[235], + io_update_valid & update_idx == 8'hEA | validArray[234], + io_update_valid & update_idx == 8'hE9 | validArray[233], + io_update_valid & update_idx == 8'hE8 | validArray[232], + io_update_valid & update_idx == 8'hE7 | validArray[231], + io_update_valid & update_idx == 8'hE6 | validArray[230], + io_update_valid & update_idx == 8'hE5 | validArray[229], + io_update_valid & update_idx == 8'hE4 | validArray[228], + io_update_valid & update_idx == 8'hE3 | validArray[227], + io_update_valid & update_idx == 8'hE2 | validArray[226], + io_update_valid & update_idx == 8'hE1 | validArray[225], + io_update_valid & update_idx == 8'hE0 | validArray[224], + io_update_valid & update_idx == 8'hDF | validArray[223], + io_update_valid & update_idx == 8'hDE | validArray[222], + io_update_valid & update_idx == 8'hDD | validArray[221], + io_update_valid & update_idx == 8'hDC | validArray[220], + io_update_valid & update_idx == 8'hDB | validArray[219], + io_update_valid & update_idx == 8'hDA | validArray[218], + io_update_valid & update_idx == 8'hD9 | validArray[217], + io_update_valid & update_idx == 8'hD8 | validArray[216], + io_update_valid & update_idx == 8'hD7 | validArray[215], + io_update_valid & update_idx == 8'hD6 | validArray[214], + io_update_valid & update_idx == 8'hD5 | validArray[213], + io_update_valid & update_idx == 8'hD4 | validArray[212], + io_update_valid & update_idx == 8'hD3 | validArray[211], + io_update_valid & update_idx == 8'hD2 | validArray[210], + io_update_valid & update_idx == 8'hD1 | validArray[209], + io_update_valid & update_idx == 8'hD0 | validArray[208], + io_update_valid & update_idx == 8'hCF | validArray[207], + io_update_valid & update_idx == 8'hCE | validArray[206], + io_update_valid & update_idx == 8'hCD | validArray[205], + io_update_valid & update_idx == 8'hCC | validArray[204], + io_update_valid & update_idx == 8'hCB | validArray[203], + io_update_valid & update_idx == 8'hCA | validArray[202], + io_update_valid & update_idx == 8'hC9 | validArray[201], + io_update_valid & update_idx == 8'hC8 | validArray[200], + io_update_valid & update_idx == 8'hC7 | validArray[199], + io_update_valid & update_idx == 8'hC6 | validArray[198], + io_update_valid & update_idx == 8'hC5 | validArray[197], + io_update_valid & update_idx == 8'hC4 | validArray[196], + io_update_valid & update_idx == 8'hC3 | validArray[195], + io_update_valid & update_idx == 8'hC2 | validArray[194], + io_update_valid & update_idx == 8'hC1 | validArray[193], + io_update_valid & update_idx == 8'hC0 | validArray[192], + io_update_valid & update_idx == 8'hBF | validArray[191], + io_update_valid & update_idx == 8'hBE | validArray[190], + io_update_valid & update_idx == 8'hBD | validArray[189], + io_update_valid & update_idx == 8'hBC | validArray[188], + io_update_valid & update_idx == 8'hBB | validArray[187], + io_update_valid & update_idx == 8'hBA | validArray[186], + io_update_valid & update_idx == 8'hB9 | validArray[185], + io_update_valid & update_idx == 8'hB8 | validArray[184], + io_update_valid & update_idx == 8'hB7 | validArray[183], + io_update_valid & update_idx == 8'hB6 | validArray[182], + io_update_valid & update_idx == 8'hB5 | validArray[181], + io_update_valid & update_idx == 8'hB4 | validArray[180], + io_update_valid & update_idx == 8'hB3 | validArray[179], + io_update_valid & update_idx == 8'hB2 | validArray[178], + io_update_valid & update_idx == 8'hB1 | validArray[177], + io_update_valid & update_idx == 8'hB0 | validArray[176], + io_update_valid & update_idx == 8'hAF | validArray[175], + io_update_valid & update_idx == 8'hAE | validArray[174], + io_update_valid & update_idx == 8'hAD | validArray[173], + io_update_valid & update_idx == 8'hAC | validArray[172], + io_update_valid & update_idx == 8'hAB | validArray[171], + io_update_valid & update_idx == 8'hAA | validArray[170], + io_update_valid & update_idx == 8'hA9 | validArray[169], + io_update_valid & update_idx == 8'hA8 | validArray[168], + io_update_valid & update_idx == 8'hA7 | validArray[167], + io_update_valid & update_idx == 8'hA6 | validArray[166], + io_update_valid & update_idx == 8'hA5 | validArray[165], + io_update_valid & update_idx == 8'hA4 | validArray[164], + io_update_valid & update_idx == 8'hA3 | validArray[163], + io_update_valid & update_idx == 8'hA2 | validArray[162], + io_update_valid & update_idx == 8'hA1 | validArray[161], + io_update_valid & update_idx == 8'hA0 | validArray[160], + io_update_valid & update_idx == 8'h9F | validArray[159], + io_update_valid & update_idx == 8'h9E | validArray[158], + io_update_valid & update_idx == 8'h9D | validArray[157], + io_update_valid & update_idx == 8'h9C | validArray[156], + io_update_valid & update_idx == 8'h9B | validArray[155], + io_update_valid & update_idx == 8'h9A | validArray[154], + io_update_valid & update_idx == 8'h99 | validArray[153], + io_update_valid & update_idx == 8'h98 | validArray[152], + io_update_valid & update_idx == 8'h97 | validArray[151], + io_update_valid & update_idx == 8'h96 | validArray[150], + io_update_valid & update_idx == 8'h95 | validArray[149], + io_update_valid & update_idx == 8'h94 | validArray[148], + io_update_valid & update_idx == 8'h93 | validArray[147], + io_update_valid & update_idx == 8'h92 | validArray[146], + io_update_valid & update_idx == 8'h91 | validArray[145], + io_update_valid & update_idx == 8'h90 | validArray[144], + io_update_valid & update_idx == 8'h8F | validArray[143], + io_update_valid & update_idx == 8'h8E | validArray[142], + io_update_valid & update_idx == 8'h8D | validArray[141], + io_update_valid & update_idx == 8'h8C | validArray[140], + io_update_valid & update_idx == 8'h8B | validArray[139], + io_update_valid & update_idx == 8'h8A | validArray[138], + io_update_valid & update_idx == 8'h89 | validArray[137], + io_update_valid & update_idx == 8'h88 | validArray[136], + io_update_valid & update_idx == 8'h87 | validArray[135], + io_update_valid & update_idx == 8'h86 | validArray[134], + io_update_valid & update_idx == 8'h85 | validArray[133], + io_update_valid & update_idx == 8'h84 | validArray[132], + io_update_valid & update_idx == 8'h83 | validArray[131], + io_update_valid & update_idx == 8'h82 | validArray[130], + io_update_valid & update_idx == 8'h81 | validArray[129], + io_update_valid & update_idx == 8'h80 | validArray[128], + io_update_valid & update_idx == 8'h7F | validArray[127], + io_update_valid & update_idx == 8'h7E | validArray[126], + io_update_valid & update_idx == 8'h7D | validArray[125], + io_update_valid & update_idx == 8'h7C | validArray[124], + io_update_valid & update_idx == 8'h7B | validArray[123], + io_update_valid & update_idx == 8'h7A | validArray[122], + io_update_valid & update_idx == 8'h79 | validArray[121], + io_update_valid & update_idx == 8'h78 | validArray[120], + io_update_valid & update_idx == 8'h77 | validArray[119], + io_update_valid & update_idx == 8'h76 | validArray[118], + io_update_valid & update_idx == 8'h75 | validArray[117], + io_update_valid & update_idx == 8'h74 | validArray[116], + io_update_valid & update_idx == 8'h73 | validArray[115], + io_update_valid & update_idx == 8'h72 | validArray[114], + io_update_valid & update_idx == 8'h71 | validArray[113], + io_update_valid & update_idx == 8'h70 | validArray[112], + io_update_valid & update_idx == 8'h6F | validArray[111], + io_update_valid & update_idx == 8'h6E | validArray[110], + io_update_valid & update_idx == 8'h6D | validArray[109], + io_update_valid & update_idx == 8'h6C | validArray[108], + io_update_valid & update_idx == 8'h6B | validArray[107], + io_update_valid & update_idx == 8'h6A | validArray[106], + io_update_valid & update_idx == 8'h69 | validArray[105], + io_update_valid & update_idx == 8'h68 | validArray[104], + io_update_valid & update_idx == 8'h67 | validArray[103], + io_update_valid & update_idx == 8'h66 | validArray[102], + io_update_valid & update_idx == 8'h65 | validArray[101], + io_update_valid & update_idx == 8'h64 | validArray[100], + io_update_valid & update_idx == 8'h63 | validArray[99], + io_update_valid & update_idx == 8'h62 | validArray[98], + io_update_valid & update_idx == 8'h61 | validArray[97], + io_update_valid & update_idx == 8'h60 | validArray[96], + io_update_valid & update_idx == 8'h5F | validArray[95], + io_update_valid & update_idx == 8'h5E | validArray[94], + io_update_valid & update_idx == 8'h5D | validArray[93], + io_update_valid & update_idx == 8'h5C | validArray[92], + io_update_valid & update_idx == 8'h5B | validArray[91], + io_update_valid & update_idx == 8'h5A | validArray[90], + io_update_valid & update_idx == 8'h59 | validArray[89], + io_update_valid & update_idx == 8'h58 | validArray[88], + io_update_valid & update_idx == 8'h57 | validArray[87], + io_update_valid & update_idx == 8'h56 | validArray[86], + io_update_valid & update_idx == 8'h55 | validArray[85], + io_update_valid & update_idx == 8'h54 | validArray[84], + io_update_valid & update_idx == 8'h53 | validArray[83], + io_update_valid & update_idx == 8'h52 | validArray[82], + io_update_valid & update_idx == 8'h51 | validArray[81], + io_update_valid & update_idx == 8'h50 | validArray[80], + io_update_valid & update_idx == 8'h4F | validArray[79], + io_update_valid & update_idx == 8'h4E | validArray[78], + io_update_valid & update_idx == 8'h4D | validArray[77], + io_update_valid & update_idx == 8'h4C | validArray[76], + io_update_valid & update_idx == 8'h4B | validArray[75], + io_update_valid & update_idx == 8'h4A | validArray[74], + io_update_valid & update_idx == 8'h49 | validArray[73], + io_update_valid & update_idx == 8'h48 | validArray[72], + io_update_valid & update_idx == 8'h47 | validArray[71], + io_update_valid & update_idx == 8'h46 | validArray[70], + io_update_valid & update_idx == 8'h45 | validArray[69], + io_update_valid & update_idx == 8'h44 | validArray[68], + io_update_valid & update_idx == 8'h43 | validArray[67], + io_update_valid & update_idx == 8'h42 | validArray[66], + io_update_valid & update_idx == 8'h41 | validArray[65], + io_update_valid & update_idx == 8'h40 | validArray[64], + io_update_valid & update_idx == 8'h3F | validArray[63], + io_update_valid & update_idx == 8'h3E | validArray[62], + io_update_valid & update_idx == 8'h3D | validArray[61], + io_update_valid & update_idx == 8'h3C | validArray[60], + io_update_valid & update_idx == 8'h3B | validArray[59], + io_update_valid & update_idx == 8'h3A | validArray[58], + io_update_valid & update_idx == 8'h39 | validArray[57], + io_update_valid & update_idx == 8'h38 | validArray[56], + io_update_valid & update_idx == 8'h37 | validArray[55], + io_update_valid & update_idx == 8'h36 | validArray[54], + io_update_valid & update_idx == 8'h35 | validArray[53], + io_update_valid & update_idx == 8'h34 | validArray[52], + io_update_valid & update_idx == 8'h33 | validArray[51], + io_update_valid & update_idx == 8'h32 | validArray[50], + io_update_valid & update_idx == 8'h31 | validArray[49], + io_update_valid & update_idx == 8'h30 | validArray[48], + io_update_valid & update_idx == 8'h2F | validArray[47], + io_update_valid & update_idx == 8'h2E | validArray[46], + io_update_valid & update_idx == 8'h2D | validArray[45], + io_update_valid & update_idx == 8'h2C | validArray[44], + io_update_valid & update_idx == 8'h2B | validArray[43], + io_update_valid & update_idx == 8'h2A | validArray[42], + io_update_valid & update_idx == 8'h29 | validArray[41], + io_update_valid & update_idx == 8'h28 | validArray[40], + io_update_valid & update_idx == 8'h27 | validArray[39], + io_update_valid & update_idx == 8'h26 | validArray[38], + io_update_valid & update_idx == 8'h25 | validArray[37], + io_update_valid & update_idx == 8'h24 | validArray[36], + io_update_valid & update_idx == 8'h23 | validArray[35], + io_update_valid & update_idx == 8'h22 | validArray[34], + io_update_valid & update_idx == 8'h21 | validArray[33], + io_update_valid & update_idx == 8'h20 | validArray[32], + io_update_valid & update_idx == 8'h1F | validArray[31], + io_update_valid & update_idx == 8'h1E | validArray[30], + io_update_valid & update_idx == 8'h1D | validArray[29], + io_update_valid & update_idx == 8'h1C | validArray[28], + io_update_valid & update_idx == 8'h1B | validArray[27], + io_update_valid & update_idx == 8'h1A | validArray[26], + io_update_valid & update_idx == 8'h19 | validArray[25], + io_update_valid & update_idx == 8'h18 | validArray[24], + io_update_valid & update_idx == 8'h17 | validArray[23], + io_update_valid & update_idx == 8'h16 | validArray[22], + io_update_valid & update_idx == 8'h15 | validArray[21], + io_update_valid & update_idx == 8'h14 | validArray[20], + io_update_valid & update_idx == 8'h13 | validArray[19], + io_update_valid & update_idx == 8'h12 | validArray[18], + io_update_valid & update_idx == 8'h11 | validArray[17], + io_update_valid & update_idx == 8'h10 | validArray[16], + io_update_valid & update_idx == 8'hF | validArray[15], + io_update_valid & update_idx == 8'hE | validArray[14], + io_update_valid & update_idx == 8'hD | validArray[13], + io_update_valid & update_idx == 8'hC | validArray[12], + io_update_valid & update_idx == 8'hB | validArray[11], + io_update_valid & update_idx == 8'hA | validArray[10], + io_update_valid & update_idx == 8'h9 | validArray[9], + io_update_valid & update_idx == 8'h8 | validArray[8], + io_update_valid & update_idx == 8'h7 | validArray[7], + io_update_valid & update_idx == 8'h6 | validArray[6], + io_update_valid & update_idx == 8'h5 | validArray[5], + io_update_valid & update_idx == 8'h4 | validArray[4], + io_update_valid & update_idx == 8'h3 | validArray[3], + io_update_valid & update_idx == 8'h2 | validArray[2], + io_update_valid & update_idx == 8'h1 | validArray[1], + io_update_valid & update_idx == 8'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :200:27, :283:{30,42}, :284:26, :285:31, :286:33 + always @(posedge clock or posedge reset) begin + if (reset) + validArray <= 256'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33 + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :213:36 + s1_tag <= + {io_req_bits_pc[17], + io_req_bits_pc[16:9] ^ io_req_bits_folded_hist_hist_14_folded_hist} + ^ {io_req_bits_folded_hist_hist_14_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43, :213:68 + s1_bank_req_1h_0 <= ~(s0_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33 + s1_bank_req_1h_1 <= s0_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33 + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + for (logic [3:0] i = 4'h0; i < 4'h9; i += 4'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + validArray = + {_RANDOM[4'h0], + _RANDOM[4'h1], + _RANDOM[4'h2], + _RANDOM[4'h3], + _RANDOM[4'h4], + _RANDOM[4'h5], + _RANDOM[4'h6], + _RANDOM[4'h7]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27 + s1_idx = _RANDOM[4'h8][7:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36 + s1_tag = _RANDOM[4'h8][16:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68} + s1_bank_req_1h_0 = _RANDOM[4'h8][17]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 + s1_bank_req_1h_1 = _RANDOM[4'h8][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 + s1_bank_has_write_on_this_req_0 = _RANDOM[4'h8][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + s1_bank_has_write_on_this_req_1 = _RANDOM[4'h8][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + `endif // RANDOMIZE_REG_INIT + if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + validArray = 256'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Folded1WDataModuleTemplate us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + .clock (clock), + .reset (reset), + .io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_rdata_0 (_us_io_rdata_0), + .io_wen (io_update_uValid), + .io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_wdata (io_update_u), + .io_resetEn (io_update_reset_u) + ); + FoldedSRAMTemplate_21 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & ~(s0_idx[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50 + .io_r_req_bits_setIdx (s0_idx[7:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 + .io_w_req_bits_setIdx (update_idx[7:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + ); + FoldedSRAMTemplate_21 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & s0_idx[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50 + .io_r_req_bits_setIdx (s0_idx[7:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 + .io_w_req_bits_setIdx (update_idx[7:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + ); + WrBypass_41 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + .clock (clock), + .reset (reset), + .io_wen (io_update_valid), + .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_hit (_wrbypass_io_hit), + .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) + ); + assign io_resp_valid = + _s1_req_rhit_T[0] + & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag + & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53} + assign io_resp_bits_ctr = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18 + assign io_resp_bits_target = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 +endmodule + diff --git a/src/ITTAGE/ITTageTable_2.sv b/src/ITTAGE/ITTageTable_2.sv new file mode 100644 index 0000000..82959f1 --- /dev/null +++ b/src/ITTAGE/ITTageTable_2.sv @@ -0,0 +1,761 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module ITTageTable_2( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + input clock, + input reset, + input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [8:0] io_req_bits_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [7:0] io_req_bits_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [8:0] io_update_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [7:0] io_update_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 +); + + wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 + wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + reg [511:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 + reg [8:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36 + reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68 + reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 + reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 + wire [511:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31 + reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 + reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 + wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 + wire [8:0] update_wdata_tag = + io_update_pc[18:10] ^ io_update_folded_hist_hist_13_folded_hist + ^ {io_update_folded_hist_hist_4_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43 + assign _resp_invalid_by_write_WIRE = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48 + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33 + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33 + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20 + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20 + wire [1:0] update_wdata_ctr = + io_update_alloc + ? 2'h2 + : (&old_ctr) & io_update_correct + ? 2'h3 + : update_wdata_ctr_oldSatNotTaken & ~io_update_correct + ? 2'h0 + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28 + wire [38:0] update_wdata_target = + io_update_alloc | update_wdata_ctr_oldSatNotTaken + ? io_update_target + : io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46} + wire [511:0] _validArray_T = + {io_update_valid & (&update_idx) | validArray[511], + io_update_valid & update_idx == 9'h1FE | validArray[510], + io_update_valid & update_idx == 9'h1FD | validArray[509], + io_update_valid & update_idx == 9'h1FC | validArray[508], + io_update_valid & update_idx == 9'h1FB | validArray[507], + io_update_valid & update_idx == 9'h1FA | validArray[506], + io_update_valid & update_idx == 9'h1F9 | validArray[505], + io_update_valid & update_idx == 9'h1F8 | validArray[504], + io_update_valid & update_idx == 9'h1F7 | validArray[503], + io_update_valid & update_idx == 9'h1F6 | validArray[502], + io_update_valid & update_idx == 9'h1F5 | validArray[501], + io_update_valid & update_idx == 9'h1F4 | validArray[500], + io_update_valid & update_idx == 9'h1F3 | validArray[499], + io_update_valid & update_idx == 9'h1F2 | validArray[498], + io_update_valid & update_idx == 9'h1F1 | validArray[497], + io_update_valid & update_idx == 9'h1F0 | validArray[496], + io_update_valid & update_idx == 9'h1EF | validArray[495], + io_update_valid & update_idx == 9'h1EE | validArray[494], + io_update_valid & update_idx == 9'h1ED | validArray[493], + io_update_valid & update_idx == 9'h1EC | validArray[492], + io_update_valid & update_idx == 9'h1EB | validArray[491], + io_update_valid & update_idx == 9'h1EA | validArray[490], + io_update_valid & update_idx == 9'h1E9 | validArray[489], + io_update_valid & update_idx == 9'h1E8 | validArray[488], + io_update_valid & update_idx == 9'h1E7 | validArray[487], + io_update_valid & update_idx == 9'h1E6 | validArray[486], + io_update_valid & update_idx == 9'h1E5 | validArray[485], + io_update_valid & update_idx == 9'h1E4 | validArray[484], + io_update_valid & update_idx == 9'h1E3 | validArray[483], + io_update_valid & update_idx == 9'h1E2 | validArray[482], + io_update_valid & update_idx == 9'h1E1 | validArray[481], + io_update_valid & update_idx == 9'h1E0 | validArray[480], + io_update_valid & update_idx == 9'h1DF | validArray[479], + io_update_valid & update_idx == 9'h1DE | validArray[478], + io_update_valid & update_idx == 9'h1DD | validArray[477], + io_update_valid & update_idx == 9'h1DC | validArray[476], + io_update_valid & update_idx == 9'h1DB | validArray[475], + io_update_valid & update_idx == 9'h1DA | validArray[474], + io_update_valid & update_idx == 9'h1D9 | validArray[473], + io_update_valid & update_idx == 9'h1D8 | validArray[472], + io_update_valid & update_idx == 9'h1D7 | validArray[471], + io_update_valid & update_idx == 9'h1D6 | validArray[470], + io_update_valid & update_idx == 9'h1D5 | validArray[469], + io_update_valid & update_idx == 9'h1D4 | validArray[468], + io_update_valid & update_idx == 9'h1D3 | validArray[467], + io_update_valid & update_idx == 9'h1D2 | validArray[466], + io_update_valid & update_idx == 9'h1D1 | validArray[465], + io_update_valid & update_idx == 9'h1D0 | validArray[464], + io_update_valid & update_idx == 9'h1CF | validArray[463], + io_update_valid & update_idx == 9'h1CE | validArray[462], + io_update_valid & update_idx == 9'h1CD | validArray[461], + io_update_valid & update_idx == 9'h1CC | validArray[460], + io_update_valid & update_idx == 9'h1CB | validArray[459], + io_update_valid & update_idx == 9'h1CA | validArray[458], + io_update_valid & update_idx == 9'h1C9 | validArray[457], + io_update_valid & update_idx == 9'h1C8 | validArray[456], + io_update_valid & update_idx == 9'h1C7 | validArray[455], + io_update_valid & update_idx == 9'h1C6 | validArray[454], + io_update_valid & update_idx == 9'h1C5 | validArray[453], + io_update_valid & update_idx == 9'h1C4 | validArray[452], + io_update_valid & update_idx == 9'h1C3 | validArray[451], + io_update_valid & update_idx == 9'h1C2 | validArray[450], + io_update_valid & update_idx == 9'h1C1 | validArray[449], + io_update_valid & update_idx == 9'h1C0 | validArray[448], + io_update_valid & update_idx == 9'h1BF | validArray[447], + io_update_valid & update_idx == 9'h1BE | validArray[446], + io_update_valid & update_idx == 9'h1BD | validArray[445], + io_update_valid & update_idx == 9'h1BC | validArray[444], + io_update_valid & update_idx == 9'h1BB | validArray[443], + io_update_valid & update_idx == 9'h1BA | validArray[442], + io_update_valid & update_idx == 9'h1B9 | validArray[441], + io_update_valid & update_idx == 9'h1B8 | validArray[440], + io_update_valid & update_idx == 9'h1B7 | validArray[439], + io_update_valid & update_idx == 9'h1B6 | validArray[438], + io_update_valid & update_idx == 9'h1B5 | validArray[437], + io_update_valid & update_idx == 9'h1B4 | validArray[436], + io_update_valid & update_idx == 9'h1B3 | validArray[435], + io_update_valid & update_idx == 9'h1B2 | validArray[434], + io_update_valid & update_idx == 9'h1B1 | validArray[433], + io_update_valid & update_idx == 9'h1B0 | validArray[432], + io_update_valid & update_idx == 9'h1AF | validArray[431], + io_update_valid & update_idx == 9'h1AE | validArray[430], + io_update_valid & update_idx == 9'h1AD | validArray[429], + io_update_valid & update_idx == 9'h1AC | validArray[428], + io_update_valid & update_idx == 9'h1AB | validArray[427], + io_update_valid & update_idx == 9'h1AA | validArray[426], + io_update_valid & update_idx == 9'h1A9 | validArray[425], + io_update_valid & update_idx == 9'h1A8 | validArray[424], + io_update_valid & update_idx == 9'h1A7 | validArray[423], + io_update_valid & update_idx == 9'h1A6 | validArray[422], + io_update_valid & update_idx == 9'h1A5 | validArray[421], + io_update_valid & update_idx == 9'h1A4 | validArray[420], + io_update_valid & update_idx == 9'h1A3 | validArray[419], + io_update_valid & update_idx == 9'h1A2 | validArray[418], + io_update_valid & update_idx == 9'h1A1 | validArray[417], + io_update_valid & update_idx == 9'h1A0 | validArray[416], + io_update_valid & update_idx == 9'h19F | validArray[415], + io_update_valid & update_idx == 9'h19E | validArray[414], + io_update_valid & update_idx == 9'h19D | validArray[413], + io_update_valid & update_idx == 9'h19C | validArray[412], + io_update_valid & update_idx == 9'h19B | validArray[411], + io_update_valid & update_idx == 9'h19A | validArray[410], + io_update_valid & update_idx == 9'h199 | validArray[409], + io_update_valid & update_idx == 9'h198 | validArray[408], + io_update_valid & update_idx == 9'h197 | validArray[407], + io_update_valid & update_idx == 9'h196 | validArray[406], + io_update_valid & update_idx == 9'h195 | validArray[405], + io_update_valid & update_idx == 9'h194 | validArray[404], + io_update_valid & update_idx == 9'h193 | validArray[403], + io_update_valid & update_idx == 9'h192 | validArray[402], + io_update_valid & update_idx == 9'h191 | validArray[401], + io_update_valid & update_idx == 9'h190 | validArray[400], + io_update_valid & update_idx == 9'h18F | validArray[399], + io_update_valid & update_idx == 9'h18E | validArray[398], + io_update_valid & update_idx == 9'h18D | validArray[397], + io_update_valid & update_idx == 9'h18C | validArray[396], + io_update_valid & update_idx == 9'h18B | validArray[395], + io_update_valid & update_idx == 9'h18A | validArray[394], + io_update_valid & update_idx == 9'h189 | validArray[393], + io_update_valid & update_idx == 9'h188 | validArray[392], + io_update_valid & update_idx == 9'h187 | validArray[391], + io_update_valid & update_idx == 9'h186 | validArray[390], + io_update_valid & update_idx == 9'h185 | validArray[389], + io_update_valid & update_idx == 9'h184 | validArray[388], + io_update_valid & update_idx == 9'h183 | validArray[387], + io_update_valid & update_idx == 9'h182 | validArray[386], + io_update_valid & update_idx == 9'h181 | validArray[385], + io_update_valid & update_idx == 9'h180 | validArray[384], + io_update_valid & update_idx == 9'h17F | validArray[383], + io_update_valid & update_idx == 9'h17E | validArray[382], + io_update_valid & update_idx == 9'h17D | validArray[381], + io_update_valid & update_idx == 9'h17C | validArray[380], + io_update_valid & update_idx == 9'h17B | validArray[379], + io_update_valid & update_idx == 9'h17A | validArray[378], + io_update_valid & update_idx == 9'h179 | validArray[377], + io_update_valid & update_idx == 9'h178 | validArray[376], + io_update_valid & update_idx == 9'h177 | validArray[375], + io_update_valid & update_idx == 9'h176 | validArray[374], + io_update_valid & update_idx == 9'h175 | validArray[373], + io_update_valid & update_idx == 9'h174 | validArray[372], + io_update_valid & update_idx == 9'h173 | validArray[371], + io_update_valid & update_idx == 9'h172 | validArray[370], + io_update_valid & update_idx == 9'h171 | validArray[369], + io_update_valid & update_idx == 9'h170 | validArray[368], + io_update_valid & update_idx == 9'h16F | validArray[367], + io_update_valid & update_idx == 9'h16E | validArray[366], + io_update_valid & update_idx == 9'h16D | validArray[365], + io_update_valid & update_idx == 9'h16C | validArray[364], + io_update_valid & update_idx == 9'h16B | validArray[363], + io_update_valid & update_idx == 9'h16A | validArray[362], + io_update_valid & update_idx == 9'h169 | validArray[361], + io_update_valid & update_idx == 9'h168 | validArray[360], + io_update_valid & update_idx == 9'h167 | validArray[359], + io_update_valid & update_idx == 9'h166 | validArray[358], + io_update_valid & update_idx == 9'h165 | validArray[357], + io_update_valid & update_idx == 9'h164 | validArray[356], + io_update_valid & update_idx == 9'h163 | validArray[355], + io_update_valid & update_idx == 9'h162 | validArray[354], + io_update_valid & update_idx == 9'h161 | validArray[353], + io_update_valid & update_idx == 9'h160 | validArray[352], + io_update_valid & update_idx == 9'h15F | validArray[351], + io_update_valid & update_idx == 9'h15E | validArray[350], + io_update_valid & update_idx == 9'h15D | validArray[349], + io_update_valid & update_idx == 9'h15C | validArray[348], + io_update_valid & update_idx == 9'h15B | validArray[347], + io_update_valid & update_idx == 9'h15A | validArray[346], + io_update_valid & update_idx == 9'h159 | validArray[345], + io_update_valid & update_idx == 9'h158 | validArray[344], + io_update_valid & update_idx == 9'h157 | validArray[343], + io_update_valid & update_idx == 9'h156 | validArray[342], + io_update_valid & update_idx == 9'h155 | validArray[341], + io_update_valid & update_idx == 9'h154 | validArray[340], + io_update_valid & update_idx == 9'h153 | validArray[339], + io_update_valid & update_idx == 9'h152 | validArray[338], + io_update_valid & update_idx == 9'h151 | validArray[337], + io_update_valid & update_idx == 9'h150 | validArray[336], + io_update_valid & update_idx == 9'h14F | validArray[335], + io_update_valid & update_idx == 9'h14E | validArray[334], + io_update_valid & update_idx == 9'h14D | validArray[333], + io_update_valid & update_idx == 9'h14C | validArray[332], + io_update_valid & update_idx == 9'h14B | validArray[331], + io_update_valid & update_idx == 9'h14A | validArray[330], + io_update_valid & update_idx == 9'h149 | validArray[329], + io_update_valid & update_idx == 9'h148 | validArray[328], + io_update_valid & update_idx == 9'h147 | validArray[327], + io_update_valid & update_idx == 9'h146 | validArray[326], + io_update_valid & update_idx == 9'h145 | validArray[325], + io_update_valid & update_idx == 9'h144 | validArray[324], + io_update_valid & update_idx == 9'h143 | validArray[323], + io_update_valid & update_idx == 9'h142 | validArray[322], + io_update_valid & update_idx == 9'h141 | validArray[321], + io_update_valid & update_idx == 9'h140 | validArray[320], + io_update_valid & update_idx == 9'h13F | validArray[319], + io_update_valid & update_idx == 9'h13E | validArray[318], + io_update_valid & update_idx == 9'h13D | validArray[317], + io_update_valid & update_idx == 9'h13C | validArray[316], + io_update_valid & update_idx == 9'h13B | validArray[315], + io_update_valid & update_idx == 9'h13A | validArray[314], + io_update_valid & update_idx == 9'h139 | validArray[313], + io_update_valid & update_idx == 9'h138 | validArray[312], + io_update_valid & update_idx == 9'h137 | validArray[311], + io_update_valid & update_idx == 9'h136 | validArray[310], + io_update_valid & update_idx == 9'h135 | validArray[309], + io_update_valid & update_idx == 9'h134 | validArray[308], + io_update_valid & update_idx == 9'h133 | validArray[307], + io_update_valid & update_idx == 9'h132 | validArray[306], + io_update_valid & update_idx == 9'h131 | validArray[305], + io_update_valid & update_idx == 9'h130 | validArray[304], + io_update_valid & update_idx == 9'h12F | validArray[303], + io_update_valid & update_idx == 9'h12E | validArray[302], + io_update_valid & update_idx == 9'h12D | validArray[301], + io_update_valid & update_idx == 9'h12C | validArray[300], + io_update_valid & update_idx == 9'h12B | validArray[299], + io_update_valid & update_idx == 9'h12A | validArray[298], + io_update_valid & update_idx == 9'h129 | validArray[297], + io_update_valid & update_idx == 9'h128 | validArray[296], + io_update_valid & update_idx == 9'h127 | validArray[295], + io_update_valid & update_idx == 9'h126 | validArray[294], + io_update_valid & update_idx == 9'h125 | validArray[293], + io_update_valid & update_idx == 9'h124 | validArray[292], + io_update_valid & update_idx == 9'h123 | validArray[291], + io_update_valid & update_idx == 9'h122 | validArray[290], + io_update_valid & update_idx == 9'h121 | validArray[289], + io_update_valid & update_idx == 9'h120 | validArray[288], + io_update_valid & update_idx == 9'h11F | validArray[287], + io_update_valid & update_idx == 9'h11E | validArray[286], + io_update_valid & update_idx == 9'h11D | validArray[285], + io_update_valid & update_idx == 9'h11C | validArray[284], + io_update_valid & update_idx == 9'h11B | validArray[283], + io_update_valid & update_idx == 9'h11A | validArray[282], + io_update_valid & update_idx == 9'h119 | validArray[281], + io_update_valid & update_idx == 9'h118 | validArray[280], + io_update_valid & update_idx == 9'h117 | validArray[279], + io_update_valid & update_idx == 9'h116 | validArray[278], + io_update_valid & update_idx == 9'h115 | validArray[277], + io_update_valid & update_idx == 9'h114 | validArray[276], + io_update_valid & update_idx == 9'h113 | validArray[275], + io_update_valid & update_idx == 9'h112 | validArray[274], + io_update_valid & update_idx == 9'h111 | validArray[273], + io_update_valid & update_idx == 9'h110 | validArray[272], + io_update_valid & update_idx == 9'h10F | validArray[271], + io_update_valid & update_idx == 9'h10E | validArray[270], + io_update_valid & update_idx == 9'h10D | validArray[269], + io_update_valid & update_idx == 9'h10C | validArray[268], + io_update_valid & update_idx == 9'h10B | validArray[267], + io_update_valid & update_idx == 9'h10A | validArray[266], + io_update_valid & update_idx == 9'h109 | validArray[265], + io_update_valid & update_idx == 9'h108 | validArray[264], + io_update_valid & update_idx == 9'h107 | validArray[263], + io_update_valid & update_idx == 9'h106 | validArray[262], + io_update_valid & update_idx == 9'h105 | validArray[261], + io_update_valid & update_idx == 9'h104 | validArray[260], + io_update_valid & update_idx == 9'h103 | validArray[259], + io_update_valid & update_idx == 9'h102 | validArray[258], + io_update_valid & update_idx == 9'h101 | validArray[257], + io_update_valid & update_idx == 9'h100 | validArray[256], + io_update_valid & update_idx == 9'hFF | validArray[255], + io_update_valid & update_idx == 9'hFE | validArray[254], + io_update_valid & update_idx == 9'hFD | validArray[253], + io_update_valid & update_idx == 9'hFC | validArray[252], + io_update_valid & update_idx == 9'hFB | validArray[251], + io_update_valid & update_idx == 9'hFA | validArray[250], + io_update_valid & update_idx == 9'hF9 | validArray[249], + io_update_valid & update_idx == 9'hF8 | validArray[248], + io_update_valid & update_idx == 9'hF7 | validArray[247], + io_update_valid & update_idx == 9'hF6 | validArray[246], + io_update_valid & update_idx == 9'hF5 | validArray[245], + io_update_valid & update_idx == 9'hF4 | validArray[244], + io_update_valid & update_idx == 9'hF3 | validArray[243], + io_update_valid & update_idx == 9'hF2 | validArray[242], + io_update_valid & update_idx == 9'hF1 | validArray[241], + io_update_valid & update_idx == 9'hF0 | validArray[240], + io_update_valid & update_idx == 9'hEF | validArray[239], + io_update_valid & update_idx == 9'hEE | validArray[238], + io_update_valid & update_idx == 9'hED | validArray[237], + io_update_valid & update_idx == 9'hEC | validArray[236], + io_update_valid & update_idx == 9'hEB | validArray[235], + io_update_valid & update_idx == 9'hEA | validArray[234], + io_update_valid & update_idx == 9'hE9 | validArray[233], + io_update_valid & update_idx == 9'hE8 | validArray[232], + io_update_valid & update_idx == 9'hE7 | validArray[231], + io_update_valid & update_idx == 9'hE6 | validArray[230], + io_update_valid & update_idx == 9'hE5 | validArray[229], + io_update_valid & update_idx == 9'hE4 | validArray[228], + io_update_valid & update_idx == 9'hE3 | validArray[227], + io_update_valid & update_idx == 9'hE2 | validArray[226], + io_update_valid & update_idx == 9'hE1 | validArray[225], + io_update_valid & update_idx == 9'hE0 | validArray[224], + io_update_valid & update_idx == 9'hDF | validArray[223], + io_update_valid & update_idx == 9'hDE | validArray[222], + io_update_valid & update_idx == 9'hDD | validArray[221], + io_update_valid & update_idx == 9'hDC | validArray[220], + io_update_valid & update_idx == 9'hDB | validArray[219], + io_update_valid & update_idx == 9'hDA | validArray[218], + io_update_valid & update_idx == 9'hD9 | validArray[217], + io_update_valid & update_idx == 9'hD8 | validArray[216], + io_update_valid & update_idx == 9'hD7 | validArray[215], + io_update_valid & update_idx == 9'hD6 | validArray[214], + io_update_valid & update_idx == 9'hD5 | validArray[213], + io_update_valid & update_idx == 9'hD4 | validArray[212], + io_update_valid & update_idx == 9'hD3 | validArray[211], + io_update_valid & update_idx == 9'hD2 | validArray[210], + io_update_valid & update_idx == 9'hD1 | validArray[209], + io_update_valid & update_idx == 9'hD0 | validArray[208], + io_update_valid & update_idx == 9'hCF | validArray[207], + io_update_valid & update_idx == 9'hCE | validArray[206], + io_update_valid & update_idx == 9'hCD | validArray[205], + io_update_valid & update_idx == 9'hCC | validArray[204], + io_update_valid & update_idx == 9'hCB | validArray[203], + io_update_valid & update_idx == 9'hCA | validArray[202], + io_update_valid & update_idx == 9'hC9 | validArray[201], + io_update_valid & update_idx == 9'hC8 | validArray[200], + io_update_valid & update_idx == 9'hC7 | validArray[199], + io_update_valid & update_idx == 9'hC6 | validArray[198], + io_update_valid & update_idx == 9'hC5 | validArray[197], + io_update_valid & update_idx == 9'hC4 | validArray[196], + io_update_valid & update_idx == 9'hC3 | validArray[195], + io_update_valid & update_idx == 9'hC2 | validArray[194], + io_update_valid & update_idx == 9'hC1 | validArray[193], + io_update_valid & update_idx == 9'hC0 | validArray[192], + io_update_valid & update_idx == 9'hBF | validArray[191], + io_update_valid & update_idx == 9'hBE | validArray[190], + io_update_valid & update_idx == 9'hBD | validArray[189], + io_update_valid & update_idx == 9'hBC | validArray[188], + io_update_valid & update_idx == 9'hBB | validArray[187], + io_update_valid & update_idx == 9'hBA | validArray[186], + io_update_valid & update_idx == 9'hB9 | validArray[185], + io_update_valid & update_idx == 9'hB8 | validArray[184], + io_update_valid & update_idx == 9'hB7 | validArray[183], + io_update_valid & update_idx == 9'hB6 | validArray[182], + io_update_valid & update_idx == 9'hB5 | validArray[181], + io_update_valid & update_idx == 9'hB4 | validArray[180], + io_update_valid & update_idx == 9'hB3 | validArray[179], + io_update_valid & update_idx == 9'hB2 | validArray[178], + io_update_valid & update_idx == 9'hB1 | validArray[177], + io_update_valid & update_idx == 9'hB0 | validArray[176], + io_update_valid & update_idx == 9'hAF | validArray[175], + io_update_valid & update_idx == 9'hAE | validArray[174], + io_update_valid & update_idx == 9'hAD | validArray[173], + io_update_valid & update_idx == 9'hAC | validArray[172], + io_update_valid & update_idx == 9'hAB | validArray[171], + io_update_valid & update_idx == 9'hAA | validArray[170], + io_update_valid & update_idx == 9'hA9 | validArray[169], + io_update_valid & update_idx == 9'hA8 | validArray[168], + io_update_valid & update_idx == 9'hA7 | validArray[167], + io_update_valid & update_idx == 9'hA6 | validArray[166], + io_update_valid & update_idx == 9'hA5 | validArray[165], + io_update_valid & update_idx == 9'hA4 | validArray[164], + io_update_valid & update_idx == 9'hA3 | validArray[163], + io_update_valid & update_idx == 9'hA2 | validArray[162], + io_update_valid & update_idx == 9'hA1 | validArray[161], + io_update_valid & update_idx == 9'hA0 | validArray[160], + io_update_valid & update_idx == 9'h9F | validArray[159], + io_update_valid & update_idx == 9'h9E | validArray[158], + io_update_valid & update_idx == 9'h9D | validArray[157], + io_update_valid & update_idx == 9'h9C | validArray[156], + io_update_valid & update_idx == 9'h9B | validArray[155], + io_update_valid & update_idx == 9'h9A | validArray[154], + io_update_valid & update_idx == 9'h99 | validArray[153], + io_update_valid & update_idx == 9'h98 | validArray[152], + io_update_valid & update_idx == 9'h97 | validArray[151], + io_update_valid & update_idx == 9'h96 | validArray[150], + io_update_valid & update_idx == 9'h95 | validArray[149], + io_update_valid & update_idx == 9'h94 | validArray[148], + io_update_valid & update_idx == 9'h93 | validArray[147], + io_update_valid & update_idx == 9'h92 | validArray[146], + io_update_valid & update_idx == 9'h91 | validArray[145], + io_update_valid & update_idx == 9'h90 | validArray[144], + io_update_valid & update_idx == 9'h8F | validArray[143], + io_update_valid & update_idx == 9'h8E | validArray[142], + io_update_valid & update_idx == 9'h8D | validArray[141], + io_update_valid & update_idx == 9'h8C | validArray[140], + io_update_valid & update_idx == 9'h8B | validArray[139], + io_update_valid & update_idx == 9'h8A | validArray[138], + io_update_valid & update_idx == 9'h89 | validArray[137], + io_update_valid & update_idx == 9'h88 | validArray[136], + io_update_valid & update_idx == 9'h87 | validArray[135], + io_update_valid & update_idx == 9'h86 | validArray[134], + io_update_valid & update_idx == 9'h85 | validArray[133], + io_update_valid & update_idx == 9'h84 | validArray[132], + io_update_valid & update_idx == 9'h83 | validArray[131], + io_update_valid & update_idx == 9'h82 | validArray[130], + io_update_valid & update_idx == 9'h81 | validArray[129], + io_update_valid & update_idx == 9'h80 | validArray[128], + io_update_valid & update_idx == 9'h7F | validArray[127], + io_update_valid & update_idx == 9'h7E | validArray[126], + io_update_valid & update_idx == 9'h7D | validArray[125], + io_update_valid & update_idx == 9'h7C | validArray[124], + io_update_valid & update_idx == 9'h7B | validArray[123], + io_update_valid & update_idx == 9'h7A | validArray[122], + io_update_valid & update_idx == 9'h79 | validArray[121], + io_update_valid & update_idx == 9'h78 | validArray[120], + io_update_valid & update_idx == 9'h77 | validArray[119], + io_update_valid & update_idx == 9'h76 | validArray[118], + io_update_valid & update_idx == 9'h75 | validArray[117], + io_update_valid & update_idx == 9'h74 | validArray[116], + io_update_valid & update_idx == 9'h73 | validArray[115], + io_update_valid & update_idx == 9'h72 | validArray[114], + io_update_valid & update_idx == 9'h71 | validArray[113], + io_update_valid & update_idx == 9'h70 | validArray[112], + io_update_valid & update_idx == 9'h6F | validArray[111], + io_update_valid & update_idx == 9'h6E | validArray[110], + io_update_valid & update_idx == 9'h6D | validArray[109], + io_update_valid & update_idx == 9'h6C | validArray[108], + io_update_valid & update_idx == 9'h6B | validArray[107], + io_update_valid & update_idx == 9'h6A | validArray[106], + io_update_valid & update_idx == 9'h69 | validArray[105], + io_update_valid & update_idx == 9'h68 | validArray[104], + io_update_valid & update_idx == 9'h67 | validArray[103], + io_update_valid & update_idx == 9'h66 | validArray[102], + io_update_valid & update_idx == 9'h65 | validArray[101], + io_update_valid & update_idx == 9'h64 | validArray[100], + io_update_valid & update_idx == 9'h63 | validArray[99], + io_update_valid & update_idx == 9'h62 | validArray[98], + io_update_valid & update_idx == 9'h61 | validArray[97], + io_update_valid & update_idx == 9'h60 | validArray[96], + io_update_valid & update_idx == 9'h5F | validArray[95], + io_update_valid & update_idx == 9'h5E | validArray[94], + io_update_valid & update_idx == 9'h5D | validArray[93], + io_update_valid & update_idx == 9'h5C | validArray[92], + io_update_valid & update_idx == 9'h5B | validArray[91], + io_update_valid & update_idx == 9'h5A | validArray[90], + io_update_valid & update_idx == 9'h59 | validArray[89], + io_update_valid & update_idx == 9'h58 | validArray[88], + io_update_valid & update_idx == 9'h57 | validArray[87], + io_update_valid & update_idx == 9'h56 | validArray[86], + io_update_valid & update_idx == 9'h55 | validArray[85], + io_update_valid & update_idx == 9'h54 | validArray[84], + io_update_valid & update_idx == 9'h53 | validArray[83], + io_update_valid & update_idx == 9'h52 | validArray[82], + io_update_valid & update_idx == 9'h51 | validArray[81], + io_update_valid & update_idx == 9'h50 | validArray[80], + io_update_valid & update_idx == 9'h4F | validArray[79], + io_update_valid & update_idx == 9'h4E | validArray[78], + io_update_valid & update_idx == 9'h4D | validArray[77], + io_update_valid & update_idx == 9'h4C | validArray[76], + io_update_valid & update_idx == 9'h4B | validArray[75], + io_update_valid & update_idx == 9'h4A | validArray[74], + io_update_valid & update_idx == 9'h49 | validArray[73], + io_update_valid & update_idx == 9'h48 | validArray[72], + io_update_valid & update_idx == 9'h47 | validArray[71], + io_update_valid & update_idx == 9'h46 | validArray[70], + io_update_valid & update_idx == 9'h45 | validArray[69], + io_update_valid & update_idx == 9'h44 | validArray[68], + io_update_valid & update_idx == 9'h43 | validArray[67], + io_update_valid & update_idx == 9'h42 | validArray[66], + io_update_valid & update_idx == 9'h41 | validArray[65], + io_update_valid & update_idx == 9'h40 | validArray[64], + io_update_valid & update_idx == 9'h3F | validArray[63], + io_update_valid & update_idx == 9'h3E | validArray[62], + io_update_valid & update_idx == 9'h3D | validArray[61], + io_update_valid & update_idx == 9'h3C | validArray[60], + io_update_valid & update_idx == 9'h3B | validArray[59], + io_update_valid & update_idx == 9'h3A | validArray[58], + io_update_valid & update_idx == 9'h39 | validArray[57], + io_update_valid & update_idx == 9'h38 | validArray[56], + io_update_valid & update_idx == 9'h37 | validArray[55], + io_update_valid & update_idx == 9'h36 | validArray[54], + io_update_valid & update_idx == 9'h35 | validArray[53], + io_update_valid & update_idx == 9'h34 | validArray[52], + io_update_valid & update_idx == 9'h33 | validArray[51], + io_update_valid & update_idx == 9'h32 | validArray[50], + io_update_valid & update_idx == 9'h31 | validArray[49], + io_update_valid & update_idx == 9'h30 | validArray[48], + io_update_valid & update_idx == 9'h2F | validArray[47], + io_update_valid & update_idx == 9'h2E | validArray[46], + io_update_valid & update_idx == 9'h2D | validArray[45], + io_update_valid & update_idx == 9'h2C | validArray[44], + io_update_valid & update_idx == 9'h2B | validArray[43], + io_update_valid & update_idx == 9'h2A | validArray[42], + io_update_valid & update_idx == 9'h29 | validArray[41], + io_update_valid & update_idx == 9'h28 | validArray[40], + io_update_valid & update_idx == 9'h27 | validArray[39], + io_update_valid & update_idx == 9'h26 | validArray[38], + io_update_valid & update_idx == 9'h25 | validArray[37], + io_update_valid & update_idx == 9'h24 | validArray[36], + io_update_valid & update_idx == 9'h23 | validArray[35], + io_update_valid & update_idx == 9'h22 | validArray[34], + io_update_valid & update_idx == 9'h21 | validArray[33], + io_update_valid & update_idx == 9'h20 | validArray[32], + io_update_valid & update_idx == 9'h1F | validArray[31], + io_update_valid & update_idx == 9'h1E | validArray[30], + io_update_valid & update_idx == 9'h1D | validArray[29], + io_update_valid & update_idx == 9'h1C | validArray[28], + io_update_valid & update_idx == 9'h1B | validArray[27], + io_update_valid & update_idx == 9'h1A | validArray[26], + io_update_valid & update_idx == 9'h19 | validArray[25], + io_update_valid & update_idx == 9'h18 | validArray[24], + io_update_valid & update_idx == 9'h17 | validArray[23], + io_update_valid & update_idx == 9'h16 | validArray[22], + io_update_valid & update_idx == 9'h15 | validArray[21], + io_update_valid & update_idx == 9'h14 | validArray[20], + io_update_valid & update_idx == 9'h13 | validArray[19], + io_update_valid & update_idx == 9'h12 | validArray[18], + io_update_valid & update_idx == 9'h11 | validArray[17], + io_update_valid & update_idx == 9'h10 | validArray[16], + io_update_valid & update_idx == 9'hF | validArray[15], + io_update_valid & update_idx == 9'hE | validArray[14], + io_update_valid & update_idx == 9'hD | validArray[13], + io_update_valid & update_idx == 9'hC | validArray[12], + io_update_valid & update_idx == 9'hB | validArray[11], + io_update_valid & update_idx == 9'hA | validArray[10], + io_update_valid & update_idx == 9'h9 | validArray[9], + io_update_valid & update_idx == 9'h8 | validArray[8], + io_update_valid & update_idx == 9'h7 | validArray[7], + io_update_valid & update_idx == 9'h6 | validArray[6], + io_update_valid & update_idx == 9'h5 | validArray[5], + io_update_valid & update_idx == 9'h4 | validArray[4], + io_update_valid & update_idx == 9'h3 | validArray[3], + io_update_valid & update_idx == 9'h2 | validArray[2], + io_update_valid & update_idx == 9'h1 | validArray[1], + io_update_valid & update_idx == 9'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :200:27, :283:{30,42}, :284:26, :285:31, :286:33 + always @(posedge clock or posedge reset) begin + if (reset) + validArray <= 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33 + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :213:36 + s1_tag <= + io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_13_folded_hist + ^ {io_req_bits_folded_hist_hist_4_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43, :213:68 + s1_bank_req_1h_0 <= ~(s0_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33 + s1_bank_req_1h_1 <= s0_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33 + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:16]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + for (logic [4:0] i = 5'h0; i < 5'h11; i += 5'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + validArray = + {_RANDOM[5'h0], + _RANDOM[5'h1], + _RANDOM[5'h2], + _RANDOM[5'h3], + _RANDOM[5'h4], + _RANDOM[5'h5], + _RANDOM[5'h6], + _RANDOM[5'h7], + _RANDOM[5'h8], + _RANDOM[5'h9], + _RANDOM[5'hA], + _RANDOM[5'hB], + _RANDOM[5'hC], + _RANDOM[5'hD], + _RANDOM[5'hE], + _RANDOM[5'hF]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27 + s1_idx = _RANDOM[5'h10][8:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36 + s1_tag = _RANDOM[5'h10][17:9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68} + s1_bank_req_1h_0 = _RANDOM[5'h10][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 + s1_bank_req_1h_1 = _RANDOM[5'h10][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 + s1_bank_has_write_on_this_req_0 = _RANDOM[5'h10][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + s1_bank_has_write_on_this_req_1 = _RANDOM[5'h10][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + `endif // RANDOMIZE_REG_INIT + if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + validArray = 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Folded1WDataModuleTemplate_2 us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + .clock (clock), + .reset (reset), + .io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_rdata_0 (_us_io_rdata_0), + .io_wen (io_update_uValid), + .io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_wdata (io_update_u), + .io_resetEn (io_update_reset_u) + ); + FoldedSRAMTemplate_25 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & ~(s0_idx[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50 + .io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 + .io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + ); + FoldedSRAMTemplate_25 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & s0_idx[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50 + .io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 + .io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + ); + WrBypass_43 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + .clock (clock), + .reset (reset), + .io_wen (io_update_valid), + .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_hit (_wrbypass_io_hit), + .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) + ); + assign io_resp_valid = + _s1_req_rhit_T[0] + & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag + & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53}, :285:31 + assign io_resp_bits_ctr = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18 + assign io_resp_bits_target = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 +endmodule + diff --git a/src/ITTAGE/ITTageTable_3.sv b/src/ITTAGE/ITTageTable_3.sv new file mode 100644 index 0000000..96b5747 --- /dev/null +++ b/src/ITTAGE/ITTageTable_3.sv @@ -0,0 +1,761 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module ITTageTable_3( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + input clock, + input reset, + input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [8:0] io_req_bits_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [7:0] io_req_bits_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [8:0] io_update_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [7:0] io_update_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 +); + + wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 + wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + reg [511:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 + reg [8:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36 + reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68 + reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 + reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 + wire [511:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31 + reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 + reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 + wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 + wire [8:0] update_wdata_tag = + io_update_pc[18:10] ^ io_update_folded_hist_hist_6_folded_hist + ^ {io_update_folded_hist_hist_2_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43 + assign _resp_invalid_by_write_WIRE = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48 + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33 + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33 + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20 + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20 + wire [1:0] update_wdata_ctr = + io_update_alloc + ? 2'h2 + : (&old_ctr) & io_update_correct + ? 2'h3 + : update_wdata_ctr_oldSatNotTaken & ~io_update_correct + ? 2'h0 + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28 + wire [38:0] update_wdata_target = + io_update_alloc | update_wdata_ctr_oldSatNotTaken + ? io_update_target + : io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46} + wire [511:0] _validArray_T = + {io_update_valid & (&update_idx) | validArray[511], + io_update_valid & update_idx == 9'h1FE | validArray[510], + io_update_valid & update_idx == 9'h1FD | validArray[509], + io_update_valid & update_idx == 9'h1FC | validArray[508], + io_update_valid & update_idx == 9'h1FB | validArray[507], + io_update_valid & update_idx == 9'h1FA | validArray[506], + io_update_valid & update_idx == 9'h1F9 | validArray[505], + io_update_valid & update_idx == 9'h1F8 | validArray[504], + io_update_valid & update_idx == 9'h1F7 | validArray[503], + io_update_valid & update_idx == 9'h1F6 | validArray[502], + io_update_valid & update_idx == 9'h1F5 | validArray[501], + io_update_valid & update_idx == 9'h1F4 | validArray[500], + io_update_valid & update_idx == 9'h1F3 | validArray[499], + io_update_valid & update_idx == 9'h1F2 | validArray[498], + io_update_valid & update_idx == 9'h1F1 | validArray[497], + io_update_valid & update_idx == 9'h1F0 | validArray[496], + io_update_valid & update_idx == 9'h1EF | validArray[495], + io_update_valid & update_idx == 9'h1EE | validArray[494], + io_update_valid & update_idx == 9'h1ED | validArray[493], + io_update_valid & update_idx == 9'h1EC | validArray[492], + io_update_valid & update_idx == 9'h1EB | validArray[491], + io_update_valid & update_idx == 9'h1EA | validArray[490], + io_update_valid & update_idx == 9'h1E9 | validArray[489], + io_update_valid & update_idx == 9'h1E8 | validArray[488], + io_update_valid & update_idx == 9'h1E7 | validArray[487], + io_update_valid & update_idx == 9'h1E6 | validArray[486], + io_update_valid & update_idx == 9'h1E5 | validArray[485], + io_update_valid & update_idx == 9'h1E4 | validArray[484], + io_update_valid & update_idx == 9'h1E3 | validArray[483], + io_update_valid & update_idx == 9'h1E2 | validArray[482], + io_update_valid & update_idx == 9'h1E1 | validArray[481], + io_update_valid & update_idx == 9'h1E0 | validArray[480], + io_update_valid & update_idx == 9'h1DF | validArray[479], + io_update_valid & update_idx == 9'h1DE | validArray[478], + io_update_valid & update_idx == 9'h1DD | validArray[477], + io_update_valid & update_idx == 9'h1DC | validArray[476], + io_update_valid & update_idx == 9'h1DB | validArray[475], + io_update_valid & update_idx == 9'h1DA | validArray[474], + io_update_valid & update_idx == 9'h1D9 | validArray[473], + io_update_valid & update_idx == 9'h1D8 | validArray[472], + io_update_valid & update_idx == 9'h1D7 | validArray[471], + io_update_valid & update_idx == 9'h1D6 | validArray[470], + io_update_valid & update_idx == 9'h1D5 | validArray[469], + io_update_valid & update_idx == 9'h1D4 | validArray[468], + io_update_valid & update_idx == 9'h1D3 | validArray[467], + io_update_valid & update_idx == 9'h1D2 | validArray[466], + io_update_valid & update_idx == 9'h1D1 | validArray[465], + io_update_valid & update_idx == 9'h1D0 | validArray[464], + io_update_valid & update_idx == 9'h1CF | validArray[463], + io_update_valid & update_idx == 9'h1CE | validArray[462], + io_update_valid & update_idx == 9'h1CD | validArray[461], + io_update_valid & update_idx == 9'h1CC | validArray[460], + io_update_valid & update_idx == 9'h1CB | validArray[459], + io_update_valid & update_idx == 9'h1CA | validArray[458], + io_update_valid & update_idx == 9'h1C9 | validArray[457], + io_update_valid & update_idx == 9'h1C8 | validArray[456], + io_update_valid & update_idx == 9'h1C7 | validArray[455], + io_update_valid & update_idx == 9'h1C6 | validArray[454], + io_update_valid & update_idx == 9'h1C5 | validArray[453], + io_update_valid & update_idx == 9'h1C4 | validArray[452], + io_update_valid & update_idx == 9'h1C3 | validArray[451], + io_update_valid & update_idx == 9'h1C2 | validArray[450], + io_update_valid & update_idx == 9'h1C1 | validArray[449], + io_update_valid & update_idx == 9'h1C0 | validArray[448], + io_update_valid & update_idx == 9'h1BF | validArray[447], + io_update_valid & update_idx == 9'h1BE | validArray[446], + io_update_valid & update_idx == 9'h1BD | validArray[445], + io_update_valid & update_idx == 9'h1BC | validArray[444], + io_update_valid & update_idx == 9'h1BB | validArray[443], + io_update_valid & update_idx == 9'h1BA | validArray[442], + io_update_valid & update_idx == 9'h1B9 | validArray[441], + io_update_valid & update_idx == 9'h1B8 | validArray[440], + io_update_valid & update_idx == 9'h1B7 | validArray[439], + io_update_valid & update_idx == 9'h1B6 | validArray[438], + io_update_valid & update_idx == 9'h1B5 | validArray[437], + io_update_valid & update_idx == 9'h1B4 | validArray[436], + io_update_valid & update_idx == 9'h1B3 | validArray[435], + io_update_valid & update_idx == 9'h1B2 | validArray[434], + io_update_valid & update_idx == 9'h1B1 | validArray[433], + io_update_valid & update_idx == 9'h1B0 | validArray[432], + io_update_valid & update_idx == 9'h1AF | validArray[431], + io_update_valid & update_idx == 9'h1AE | validArray[430], + io_update_valid & update_idx == 9'h1AD | validArray[429], + io_update_valid & update_idx == 9'h1AC | validArray[428], + io_update_valid & update_idx == 9'h1AB | validArray[427], + io_update_valid & update_idx == 9'h1AA | validArray[426], + io_update_valid & update_idx == 9'h1A9 | validArray[425], + io_update_valid & update_idx == 9'h1A8 | validArray[424], + io_update_valid & update_idx == 9'h1A7 | validArray[423], + io_update_valid & update_idx == 9'h1A6 | validArray[422], + io_update_valid & update_idx == 9'h1A5 | validArray[421], + io_update_valid & update_idx == 9'h1A4 | validArray[420], + io_update_valid & update_idx == 9'h1A3 | validArray[419], + io_update_valid & update_idx == 9'h1A2 | validArray[418], + io_update_valid & update_idx == 9'h1A1 | validArray[417], + io_update_valid & update_idx == 9'h1A0 | validArray[416], + io_update_valid & update_idx == 9'h19F | validArray[415], + io_update_valid & update_idx == 9'h19E | validArray[414], + io_update_valid & update_idx == 9'h19D | validArray[413], + io_update_valid & update_idx == 9'h19C | validArray[412], + io_update_valid & update_idx == 9'h19B | validArray[411], + io_update_valid & update_idx == 9'h19A | validArray[410], + io_update_valid & update_idx == 9'h199 | validArray[409], + io_update_valid & update_idx == 9'h198 | validArray[408], + io_update_valid & update_idx == 9'h197 | validArray[407], + io_update_valid & update_idx == 9'h196 | validArray[406], + io_update_valid & update_idx == 9'h195 | validArray[405], + io_update_valid & update_idx == 9'h194 | validArray[404], + io_update_valid & update_idx == 9'h193 | validArray[403], + io_update_valid & update_idx == 9'h192 | validArray[402], + io_update_valid & update_idx == 9'h191 | validArray[401], + io_update_valid & update_idx == 9'h190 | validArray[400], + io_update_valid & update_idx == 9'h18F | validArray[399], + io_update_valid & update_idx == 9'h18E | validArray[398], + io_update_valid & update_idx == 9'h18D | validArray[397], + io_update_valid & update_idx == 9'h18C | validArray[396], + io_update_valid & update_idx == 9'h18B | validArray[395], + io_update_valid & update_idx == 9'h18A | validArray[394], + io_update_valid & update_idx == 9'h189 | validArray[393], + io_update_valid & update_idx == 9'h188 | validArray[392], + io_update_valid & update_idx == 9'h187 | validArray[391], + io_update_valid & update_idx == 9'h186 | validArray[390], + io_update_valid & update_idx == 9'h185 | validArray[389], + io_update_valid & update_idx == 9'h184 | validArray[388], + io_update_valid & update_idx == 9'h183 | validArray[387], + io_update_valid & update_idx == 9'h182 | validArray[386], + io_update_valid & update_idx == 9'h181 | validArray[385], + io_update_valid & update_idx == 9'h180 | validArray[384], + io_update_valid & update_idx == 9'h17F | validArray[383], + io_update_valid & update_idx == 9'h17E | validArray[382], + io_update_valid & update_idx == 9'h17D | validArray[381], + io_update_valid & update_idx == 9'h17C | validArray[380], + io_update_valid & update_idx == 9'h17B | validArray[379], + io_update_valid & update_idx == 9'h17A | validArray[378], + io_update_valid & update_idx == 9'h179 | validArray[377], + io_update_valid & update_idx == 9'h178 | validArray[376], + io_update_valid & update_idx == 9'h177 | validArray[375], + io_update_valid & update_idx == 9'h176 | validArray[374], + io_update_valid & update_idx == 9'h175 | validArray[373], + io_update_valid & update_idx == 9'h174 | validArray[372], + io_update_valid & update_idx == 9'h173 | validArray[371], + io_update_valid & update_idx == 9'h172 | validArray[370], + io_update_valid & update_idx == 9'h171 | validArray[369], + io_update_valid & update_idx == 9'h170 | validArray[368], + io_update_valid & update_idx == 9'h16F | validArray[367], + io_update_valid & update_idx == 9'h16E | validArray[366], + io_update_valid & update_idx == 9'h16D | validArray[365], + io_update_valid & update_idx == 9'h16C | validArray[364], + io_update_valid & update_idx == 9'h16B | validArray[363], + io_update_valid & update_idx == 9'h16A | validArray[362], + io_update_valid & update_idx == 9'h169 | validArray[361], + io_update_valid & update_idx == 9'h168 | validArray[360], + io_update_valid & update_idx == 9'h167 | validArray[359], + io_update_valid & update_idx == 9'h166 | validArray[358], + io_update_valid & update_idx == 9'h165 | validArray[357], + io_update_valid & update_idx == 9'h164 | validArray[356], + io_update_valid & update_idx == 9'h163 | validArray[355], + io_update_valid & update_idx == 9'h162 | validArray[354], + io_update_valid & update_idx == 9'h161 | validArray[353], + io_update_valid & update_idx == 9'h160 | validArray[352], + io_update_valid & update_idx == 9'h15F | validArray[351], + io_update_valid & update_idx == 9'h15E | validArray[350], + io_update_valid & update_idx == 9'h15D | validArray[349], + io_update_valid & update_idx == 9'h15C | validArray[348], + io_update_valid & update_idx == 9'h15B | validArray[347], + io_update_valid & update_idx == 9'h15A | validArray[346], + io_update_valid & update_idx == 9'h159 | validArray[345], + io_update_valid & update_idx == 9'h158 | validArray[344], + io_update_valid & update_idx == 9'h157 | validArray[343], + io_update_valid & update_idx == 9'h156 | validArray[342], + io_update_valid & update_idx == 9'h155 | validArray[341], + io_update_valid & update_idx == 9'h154 | validArray[340], + io_update_valid & update_idx == 9'h153 | validArray[339], + io_update_valid & update_idx == 9'h152 | validArray[338], + io_update_valid & update_idx == 9'h151 | validArray[337], + io_update_valid & update_idx == 9'h150 | validArray[336], + io_update_valid & update_idx == 9'h14F | validArray[335], + io_update_valid & update_idx == 9'h14E | validArray[334], + io_update_valid & update_idx == 9'h14D | validArray[333], + io_update_valid & update_idx == 9'h14C | validArray[332], + io_update_valid & update_idx == 9'h14B | validArray[331], + io_update_valid & update_idx == 9'h14A | validArray[330], + io_update_valid & update_idx == 9'h149 | validArray[329], + io_update_valid & update_idx == 9'h148 | validArray[328], + io_update_valid & update_idx == 9'h147 | validArray[327], + io_update_valid & update_idx == 9'h146 | validArray[326], + io_update_valid & update_idx == 9'h145 | validArray[325], + io_update_valid & update_idx == 9'h144 | validArray[324], + io_update_valid & update_idx == 9'h143 | validArray[323], + io_update_valid & update_idx == 9'h142 | validArray[322], + io_update_valid & update_idx == 9'h141 | validArray[321], + io_update_valid & update_idx == 9'h140 | validArray[320], + io_update_valid & update_idx == 9'h13F | validArray[319], + io_update_valid & update_idx == 9'h13E | validArray[318], + io_update_valid & update_idx == 9'h13D | validArray[317], + io_update_valid & update_idx == 9'h13C | validArray[316], + io_update_valid & update_idx == 9'h13B | validArray[315], + io_update_valid & update_idx == 9'h13A | validArray[314], + io_update_valid & update_idx == 9'h139 | validArray[313], + io_update_valid & update_idx == 9'h138 | validArray[312], + io_update_valid & update_idx == 9'h137 | validArray[311], + io_update_valid & update_idx == 9'h136 | validArray[310], + io_update_valid & update_idx == 9'h135 | validArray[309], + io_update_valid & update_idx == 9'h134 | validArray[308], + io_update_valid & update_idx == 9'h133 | validArray[307], + io_update_valid & update_idx == 9'h132 | validArray[306], + io_update_valid & update_idx == 9'h131 | validArray[305], + io_update_valid & update_idx == 9'h130 | validArray[304], + io_update_valid & update_idx == 9'h12F | validArray[303], + io_update_valid & update_idx == 9'h12E | validArray[302], + io_update_valid & update_idx == 9'h12D | validArray[301], + io_update_valid & update_idx == 9'h12C | validArray[300], + io_update_valid & update_idx == 9'h12B | validArray[299], + io_update_valid & update_idx == 9'h12A | validArray[298], + io_update_valid & update_idx == 9'h129 | validArray[297], + io_update_valid & update_idx == 9'h128 | validArray[296], + io_update_valid & update_idx == 9'h127 | validArray[295], + io_update_valid & update_idx == 9'h126 | validArray[294], + io_update_valid & update_idx == 9'h125 | validArray[293], + io_update_valid & update_idx == 9'h124 | validArray[292], + io_update_valid & update_idx == 9'h123 | validArray[291], + io_update_valid & update_idx == 9'h122 | validArray[290], + io_update_valid & update_idx == 9'h121 | validArray[289], + io_update_valid & update_idx == 9'h120 | validArray[288], + io_update_valid & update_idx == 9'h11F | validArray[287], + io_update_valid & update_idx == 9'h11E | validArray[286], + io_update_valid & update_idx == 9'h11D | validArray[285], + io_update_valid & update_idx == 9'h11C | validArray[284], + io_update_valid & update_idx == 9'h11B | validArray[283], + io_update_valid & update_idx == 9'h11A | validArray[282], + io_update_valid & update_idx == 9'h119 | validArray[281], + io_update_valid & update_idx == 9'h118 | validArray[280], + io_update_valid & update_idx == 9'h117 | validArray[279], + io_update_valid & update_idx == 9'h116 | validArray[278], + io_update_valid & update_idx == 9'h115 | validArray[277], + io_update_valid & update_idx == 9'h114 | validArray[276], + io_update_valid & update_idx == 9'h113 | validArray[275], + io_update_valid & update_idx == 9'h112 | validArray[274], + io_update_valid & update_idx == 9'h111 | validArray[273], + io_update_valid & update_idx == 9'h110 | validArray[272], + io_update_valid & update_idx == 9'h10F | validArray[271], + io_update_valid & update_idx == 9'h10E | validArray[270], + io_update_valid & update_idx == 9'h10D | validArray[269], + io_update_valid & update_idx == 9'h10C | validArray[268], + io_update_valid & update_idx == 9'h10B | validArray[267], + io_update_valid & update_idx == 9'h10A | validArray[266], + io_update_valid & update_idx == 9'h109 | validArray[265], + io_update_valid & update_idx == 9'h108 | validArray[264], + io_update_valid & update_idx == 9'h107 | validArray[263], + io_update_valid & update_idx == 9'h106 | validArray[262], + io_update_valid & update_idx == 9'h105 | validArray[261], + io_update_valid & update_idx == 9'h104 | validArray[260], + io_update_valid & update_idx == 9'h103 | validArray[259], + io_update_valid & update_idx == 9'h102 | validArray[258], + io_update_valid & update_idx == 9'h101 | validArray[257], + io_update_valid & update_idx == 9'h100 | validArray[256], + io_update_valid & update_idx == 9'hFF | validArray[255], + io_update_valid & update_idx == 9'hFE | validArray[254], + io_update_valid & update_idx == 9'hFD | validArray[253], + io_update_valid & update_idx == 9'hFC | validArray[252], + io_update_valid & update_idx == 9'hFB | validArray[251], + io_update_valid & update_idx == 9'hFA | validArray[250], + io_update_valid & update_idx == 9'hF9 | validArray[249], + io_update_valid & update_idx == 9'hF8 | validArray[248], + io_update_valid & update_idx == 9'hF7 | validArray[247], + io_update_valid & update_idx == 9'hF6 | validArray[246], + io_update_valid & update_idx == 9'hF5 | validArray[245], + io_update_valid & update_idx == 9'hF4 | validArray[244], + io_update_valid & update_idx == 9'hF3 | validArray[243], + io_update_valid & update_idx == 9'hF2 | validArray[242], + io_update_valid & update_idx == 9'hF1 | validArray[241], + io_update_valid & update_idx == 9'hF0 | validArray[240], + io_update_valid & update_idx == 9'hEF | validArray[239], + io_update_valid & update_idx == 9'hEE | validArray[238], + io_update_valid & update_idx == 9'hED | validArray[237], + io_update_valid & update_idx == 9'hEC | validArray[236], + io_update_valid & update_idx == 9'hEB | validArray[235], + io_update_valid & update_idx == 9'hEA | validArray[234], + io_update_valid & update_idx == 9'hE9 | validArray[233], + io_update_valid & update_idx == 9'hE8 | validArray[232], + io_update_valid & update_idx == 9'hE7 | validArray[231], + io_update_valid & update_idx == 9'hE6 | validArray[230], + io_update_valid & update_idx == 9'hE5 | validArray[229], + io_update_valid & update_idx == 9'hE4 | validArray[228], + io_update_valid & update_idx == 9'hE3 | validArray[227], + io_update_valid & update_idx == 9'hE2 | validArray[226], + io_update_valid & update_idx == 9'hE1 | validArray[225], + io_update_valid & update_idx == 9'hE0 | validArray[224], + io_update_valid & update_idx == 9'hDF | validArray[223], + io_update_valid & update_idx == 9'hDE | validArray[222], + io_update_valid & update_idx == 9'hDD | validArray[221], + io_update_valid & update_idx == 9'hDC | validArray[220], + io_update_valid & update_idx == 9'hDB | validArray[219], + io_update_valid & update_idx == 9'hDA | validArray[218], + io_update_valid & update_idx == 9'hD9 | validArray[217], + io_update_valid & update_idx == 9'hD8 | validArray[216], + io_update_valid & update_idx == 9'hD7 | validArray[215], + io_update_valid & update_idx == 9'hD6 | validArray[214], + io_update_valid & update_idx == 9'hD5 | validArray[213], + io_update_valid & update_idx == 9'hD4 | validArray[212], + io_update_valid & update_idx == 9'hD3 | validArray[211], + io_update_valid & update_idx == 9'hD2 | validArray[210], + io_update_valid & update_idx == 9'hD1 | validArray[209], + io_update_valid & update_idx == 9'hD0 | validArray[208], + io_update_valid & update_idx == 9'hCF | validArray[207], + io_update_valid & update_idx == 9'hCE | validArray[206], + io_update_valid & update_idx == 9'hCD | validArray[205], + io_update_valid & update_idx == 9'hCC | validArray[204], + io_update_valid & update_idx == 9'hCB | validArray[203], + io_update_valid & update_idx == 9'hCA | validArray[202], + io_update_valid & update_idx == 9'hC9 | validArray[201], + io_update_valid & update_idx == 9'hC8 | validArray[200], + io_update_valid & update_idx == 9'hC7 | validArray[199], + io_update_valid & update_idx == 9'hC6 | validArray[198], + io_update_valid & update_idx == 9'hC5 | validArray[197], + io_update_valid & update_idx == 9'hC4 | validArray[196], + io_update_valid & update_idx == 9'hC3 | validArray[195], + io_update_valid & update_idx == 9'hC2 | validArray[194], + io_update_valid & update_idx == 9'hC1 | validArray[193], + io_update_valid & update_idx == 9'hC0 | validArray[192], + io_update_valid & update_idx == 9'hBF | validArray[191], + io_update_valid & update_idx == 9'hBE | validArray[190], + io_update_valid & update_idx == 9'hBD | validArray[189], + io_update_valid & update_idx == 9'hBC | validArray[188], + io_update_valid & update_idx == 9'hBB | validArray[187], + io_update_valid & update_idx == 9'hBA | validArray[186], + io_update_valid & update_idx == 9'hB9 | validArray[185], + io_update_valid & update_idx == 9'hB8 | validArray[184], + io_update_valid & update_idx == 9'hB7 | validArray[183], + io_update_valid & update_idx == 9'hB6 | validArray[182], + io_update_valid & update_idx == 9'hB5 | validArray[181], + io_update_valid & update_idx == 9'hB4 | validArray[180], + io_update_valid & update_idx == 9'hB3 | validArray[179], + io_update_valid & update_idx == 9'hB2 | validArray[178], + io_update_valid & update_idx == 9'hB1 | validArray[177], + io_update_valid & update_idx == 9'hB0 | validArray[176], + io_update_valid & update_idx == 9'hAF | validArray[175], + io_update_valid & update_idx == 9'hAE | validArray[174], + io_update_valid & update_idx == 9'hAD | validArray[173], + io_update_valid & update_idx == 9'hAC | validArray[172], + io_update_valid & update_idx == 9'hAB | validArray[171], + io_update_valid & update_idx == 9'hAA | validArray[170], + io_update_valid & update_idx == 9'hA9 | validArray[169], + io_update_valid & update_idx == 9'hA8 | validArray[168], + io_update_valid & update_idx == 9'hA7 | validArray[167], + io_update_valid & update_idx == 9'hA6 | validArray[166], + io_update_valid & update_idx == 9'hA5 | validArray[165], + io_update_valid & update_idx == 9'hA4 | validArray[164], + io_update_valid & update_idx == 9'hA3 | validArray[163], + io_update_valid & update_idx == 9'hA2 | validArray[162], + io_update_valid & update_idx == 9'hA1 | validArray[161], + io_update_valid & update_idx == 9'hA0 | validArray[160], + io_update_valid & update_idx == 9'h9F | validArray[159], + io_update_valid & update_idx == 9'h9E | validArray[158], + io_update_valid & update_idx == 9'h9D | validArray[157], + io_update_valid & update_idx == 9'h9C | validArray[156], + io_update_valid & update_idx == 9'h9B | validArray[155], + io_update_valid & update_idx == 9'h9A | validArray[154], + io_update_valid & update_idx == 9'h99 | validArray[153], + io_update_valid & update_idx == 9'h98 | validArray[152], + io_update_valid & update_idx == 9'h97 | validArray[151], + io_update_valid & update_idx == 9'h96 | validArray[150], + io_update_valid & update_idx == 9'h95 | validArray[149], + io_update_valid & update_idx == 9'h94 | validArray[148], + io_update_valid & update_idx == 9'h93 | validArray[147], + io_update_valid & update_idx == 9'h92 | validArray[146], + io_update_valid & update_idx == 9'h91 | validArray[145], + io_update_valid & update_idx == 9'h90 | validArray[144], + io_update_valid & update_idx == 9'h8F | validArray[143], + io_update_valid & update_idx == 9'h8E | validArray[142], + io_update_valid & update_idx == 9'h8D | validArray[141], + io_update_valid & update_idx == 9'h8C | validArray[140], + io_update_valid & update_idx == 9'h8B | validArray[139], + io_update_valid & update_idx == 9'h8A | validArray[138], + io_update_valid & update_idx == 9'h89 | validArray[137], + io_update_valid & update_idx == 9'h88 | validArray[136], + io_update_valid & update_idx == 9'h87 | validArray[135], + io_update_valid & update_idx == 9'h86 | validArray[134], + io_update_valid & update_idx == 9'h85 | validArray[133], + io_update_valid & update_idx == 9'h84 | validArray[132], + io_update_valid & update_idx == 9'h83 | validArray[131], + io_update_valid & update_idx == 9'h82 | validArray[130], + io_update_valid & update_idx == 9'h81 | validArray[129], + io_update_valid & update_idx == 9'h80 | validArray[128], + io_update_valid & update_idx == 9'h7F | validArray[127], + io_update_valid & update_idx == 9'h7E | validArray[126], + io_update_valid & update_idx == 9'h7D | validArray[125], + io_update_valid & update_idx == 9'h7C | validArray[124], + io_update_valid & update_idx == 9'h7B | validArray[123], + io_update_valid & update_idx == 9'h7A | validArray[122], + io_update_valid & update_idx == 9'h79 | validArray[121], + io_update_valid & update_idx == 9'h78 | validArray[120], + io_update_valid & update_idx == 9'h77 | validArray[119], + io_update_valid & update_idx == 9'h76 | validArray[118], + io_update_valid & update_idx == 9'h75 | validArray[117], + io_update_valid & update_idx == 9'h74 | validArray[116], + io_update_valid & update_idx == 9'h73 | validArray[115], + io_update_valid & update_idx == 9'h72 | validArray[114], + io_update_valid & update_idx == 9'h71 | validArray[113], + io_update_valid & update_idx == 9'h70 | validArray[112], + io_update_valid & update_idx == 9'h6F | validArray[111], + io_update_valid & update_idx == 9'h6E | validArray[110], + io_update_valid & update_idx == 9'h6D | validArray[109], + io_update_valid & update_idx == 9'h6C | validArray[108], + io_update_valid & update_idx == 9'h6B | validArray[107], + io_update_valid & update_idx == 9'h6A | validArray[106], + io_update_valid & update_idx == 9'h69 | validArray[105], + io_update_valid & update_idx == 9'h68 | validArray[104], + io_update_valid & update_idx == 9'h67 | validArray[103], + io_update_valid & update_idx == 9'h66 | validArray[102], + io_update_valid & update_idx == 9'h65 | validArray[101], + io_update_valid & update_idx == 9'h64 | validArray[100], + io_update_valid & update_idx == 9'h63 | validArray[99], + io_update_valid & update_idx == 9'h62 | validArray[98], + io_update_valid & update_idx == 9'h61 | validArray[97], + io_update_valid & update_idx == 9'h60 | validArray[96], + io_update_valid & update_idx == 9'h5F | validArray[95], + io_update_valid & update_idx == 9'h5E | validArray[94], + io_update_valid & update_idx == 9'h5D | validArray[93], + io_update_valid & update_idx == 9'h5C | validArray[92], + io_update_valid & update_idx == 9'h5B | validArray[91], + io_update_valid & update_idx == 9'h5A | validArray[90], + io_update_valid & update_idx == 9'h59 | validArray[89], + io_update_valid & update_idx == 9'h58 | validArray[88], + io_update_valid & update_idx == 9'h57 | validArray[87], + io_update_valid & update_idx == 9'h56 | validArray[86], + io_update_valid & update_idx == 9'h55 | validArray[85], + io_update_valid & update_idx == 9'h54 | validArray[84], + io_update_valid & update_idx == 9'h53 | validArray[83], + io_update_valid & update_idx == 9'h52 | validArray[82], + io_update_valid & update_idx == 9'h51 | validArray[81], + io_update_valid & update_idx == 9'h50 | validArray[80], + io_update_valid & update_idx == 9'h4F | validArray[79], + io_update_valid & update_idx == 9'h4E | validArray[78], + io_update_valid & update_idx == 9'h4D | validArray[77], + io_update_valid & update_idx == 9'h4C | validArray[76], + io_update_valid & update_idx == 9'h4B | validArray[75], + io_update_valid & update_idx == 9'h4A | validArray[74], + io_update_valid & update_idx == 9'h49 | validArray[73], + io_update_valid & update_idx == 9'h48 | validArray[72], + io_update_valid & update_idx == 9'h47 | validArray[71], + io_update_valid & update_idx == 9'h46 | validArray[70], + io_update_valid & update_idx == 9'h45 | validArray[69], + io_update_valid & update_idx == 9'h44 | validArray[68], + io_update_valid & update_idx == 9'h43 | validArray[67], + io_update_valid & update_idx == 9'h42 | validArray[66], + io_update_valid & update_idx == 9'h41 | validArray[65], + io_update_valid & update_idx == 9'h40 | validArray[64], + io_update_valid & update_idx == 9'h3F | validArray[63], + io_update_valid & update_idx == 9'h3E | validArray[62], + io_update_valid & update_idx == 9'h3D | validArray[61], + io_update_valid & update_idx == 9'h3C | validArray[60], + io_update_valid & update_idx == 9'h3B | validArray[59], + io_update_valid & update_idx == 9'h3A | validArray[58], + io_update_valid & update_idx == 9'h39 | validArray[57], + io_update_valid & update_idx == 9'h38 | validArray[56], + io_update_valid & update_idx == 9'h37 | validArray[55], + io_update_valid & update_idx == 9'h36 | validArray[54], + io_update_valid & update_idx == 9'h35 | validArray[53], + io_update_valid & update_idx == 9'h34 | validArray[52], + io_update_valid & update_idx == 9'h33 | validArray[51], + io_update_valid & update_idx == 9'h32 | validArray[50], + io_update_valid & update_idx == 9'h31 | validArray[49], + io_update_valid & update_idx == 9'h30 | validArray[48], + io_update_valid & update_idx == 9'h2F | validArray[47], + io_update_valid & update_idx == 9'h2E | validArray[46], + io_update_valid & update_idx == 9'h2D | validArray[45], + io_update_valid & update_idx == 9'h2C | validArray[44], + io_update_valid & update_idx == 9'h2B | validArray[43], + io_update_valid & update_idx == 9'h2A | validArray[42], + io_update_valid & update_idx == 9'h29 | validArray[41], + io_update_valid & update_idx == 9'h28 | validArray[40], + io_update_valid & update_idx == 9'h27 | validArray[39], + io_update_valid & update_idx == 9'h26 | validArray[38], + io_update_valid & update_idx == 9'h25 | validArray[37], + io_update_valid & update_idx == 9'h24 | validArray[36], + io_update_valid & update_idx == 9'h23 | validArray[35], + io_update_valid & update_idx == 9'h22 | validArray[34], + io_update_valid & update_idx == 9'h21 | validArray[33], + io_update_valid & update_idx == 9'h20 | validArray[32], + io_update_valid & update_idx == 9'h1F | validArray[31], + io_update_valid & update_idx == 9'h1E | validArray[30], + io_update_valid & update_idx == 9'h1D | validArray[29], + io_update_valid & update_idx == 9'h1C | validArray[28], + io_update_valid & update_idx == 9'h1B | validArray[27], + io_update_valid & update_idx == 9'h1A | validArray[26], + io_update_valid & update_idx == 9'h19 | validArray[25], + io_update_valid & update_idx == 9'h18 | validArray[24], + io_update_valid & update_idx == 9'h17 | validArray[23], + io_update_valid & update_idx == 9'h16 | validArray[22], + io_update_valid & update_idx == 9'h15 | validArray[21], + io_update_valid & update_idx == 9'h14 | validArray[20], + io_update_valid & update_idx == 9'h13 | validArray[19], + io_update_valid & update_idx == 9'h12 | validArray[18], + io_update_valid & update_idx == 9'h11 | validArray[17], + io_update_valid & update_idx == 9'h10 | validArray[16], + io_update_valid & update_idx == 9'hF | validArray[15], + io_update_valid & update_idx == 9'hE | validArray[14], + io_update_valid & update_idx == 9'hD | validArray[13], + io_update_valid & update_idx == 9'hC | validArray[12], + io_update_valid & update_idx == 9'hB | validArray[11], + io_update_valid & update_idx == 9'hA | validArray[10], + io_update_valid & update_idx == 9'h9 | validArray[9], + io_update_valid & update_idx == 9'h8 | validArray[8], + io_update_valid & update_idx == 9'h7 | validArray[7], + io_update_valid & update_idx == 9'h6 | validArray[6], + io_update_valid & update_idx == 9'h5 | validArray[5], + io_update_valid & update_idx == 9'h4 | validArray[4], + io_update_valid & update_idx == 9'h3 | validArray[3], + io_update_valid & update_idx == 9'h2 | validArray[2], + io_update_valid & update_idx == 9'h1 | validArray[1], + io_update_valid & update_idx == 9'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :200:27, :283:{30,42}, :284:26, :285:31, :286:33 + always @(posedge clock or posedge reset) begin + if (reset) + validArray <= 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33 + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :213:36 + s1_tag <= + io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_6_folded_hist + ^ {io_req_bits_folded_hist_hist_2_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43, :213:68 + s1_bank_req_1h_0 <= ~(s0_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33 + s1_bank_req_1h_1 <= s0_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33 + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:16]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + for (logic [4:0] i = 5'h0; i < 5'h11; i += 5'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + validArray = + {_RANDOM[5'h0], + _RANDOM[5'h1], + _RANDOM[5'h2], + _RANDOM[5'h3], + _RANDOM[5'h4], + _RANDOM[5'h5], + _RANDOM[5'h6], + _RANDOM[5'h7], + _RANDOM[5'h8], + _RANDOM[5'h9], + _RANDOM[5'hA], + _RANDOM[5'hB], + _RANDOM[5'hC], + _RANDOM[5'hD], + _RANDOM[5'hE], + _RANDOM[5'hF]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27 + s1_idx = _RANDOM[5'h10][8:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36 + s1_tag = _RANDOM[5'h10][17:9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68} + s1_bank_req_1h_0 = _RANDOM[5'h10][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 + s1_bank_req_1h_1 = _RANDOM[5'h10][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 + s1_bank_has_write_on_this_req_0 = _RANDOM[5'h10][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + s1_bank_has_write_on_this_req_1 = _RANDOM[5'h10][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + `endif // RANDOMIZE_REG_INIT + if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + validArray = 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Folded1WDataModuleTemplate_2 us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + .clock (clock), + .reset (reset), + .io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_rdata_0 (_us_io_rdata_0), + .io_wen (io_update_uValid), + .io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_wdata (io_update_u), + .io_resetEn (io_update_reset_u) + ); + FoldedSRAMTemplate_25 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & ~(s0_idx[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50 + .io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 + .io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + ); + FoldedSRAMTemplate_25 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & s0_idx[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50 + .io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 + .io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + ); + WrBypass_43 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + .clock (clock), + .reset (reset), + .io_wen (io_update_valid), + .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_hit (_wrbypass_io_hit), + .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) + ); + assign io_resp_valid = + _s1_req_rhit_T[0] + & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag + & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53}, :285:31 + assign io_resp_bits_ctr = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18 + assign io_resp_bits_target = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 +endmodule + diff --git a/src/ITTAGE/ITTageTable_4.sv b/src/ITTAGE/ITTageTable_4.sv new file mode 100644 index 0000000..a2f43ce --- /dev/null +++ b/src/ITTAGE/ITTageTable_4.sv @@ -0,0 +1,761 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module ITTageTable_4( // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + input clock, + input reset, + input io_req_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [8:0] io_req_bits_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [7:0] io_req_bits_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output io_resp_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [1:0] io_resp_bits_ctr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [1:0] io_resp_bits_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + output [38:0] io_resp_bits_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [8:0] io_update_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [7:0] io_update_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_valid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_correct, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_alloc, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [1:0] io_update_oldCtr, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_uValid, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input io_update_reset_u, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_target, // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + input [38:0] io_update_old_target // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 +); + + wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 + wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [38:0] _table_banks_1_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire [38:0] _table_banks_0_io_r_resp_data_0_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + wire _us_io_rdata_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + reg [511:0] validArray; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 + reg [8:0] s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:36 + reg [8:0] s1_tag; // src/main/scala/xiangshan/frontend/ITTAGE.scala:213:68 + reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 + reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33 + wire [511:0] _s1_req_rhit_T = validArray >> s1_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :213:36, :232:31 + reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 + reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48 + wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :207:43 + wire [8:0] update_wdata_tag = + io_update_pc[18:10] ^ io_update_folded_hist_hist_10_folded_hist + ^ {io_update_folded_hist_hist_3_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43 + assign _resp_invalid_by_write_WIRE = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:215:33, :240:48 + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :255:33 + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :255:33 + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24, :277:20 + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20 + wire [1:0] update_wdata_ctr = + io_update_alloc + ? 2'h2 + : (&old_ctr) & io_update_correct + ? 2'h3 + : update_wdata_ctr_oldSatNotTaken & ~io_update_correct + ? 2'h0 + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/ITTAGE.scala:277:20, :278:28 + wire [38:0] update_wdata_target = + io_update_alloc | update_wdata_ctr_oldSatNotTaken + ? io_update_target + : io_update_old_target; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, src/main/scala/xiangshan/frontend/ITTAGE.scala:281:{29,46} + wire [511:0] _validArray_T = + {io_update_valid & (&update_idx) | validArray[511], + io_update_valid & update_idx == 9'h1FE | validArray[510], + io_update_valid & update_idx == 9'h1FD | validArray[509], + io_update_valid & update_idx == 9'h1FC | validArray[508], + io_update_valid & update_idx == 9'h1FB | validArray[507], + io_update_valid & update_idx == 9'h1FA | validArray[506], + io_update_valid & update_idx == 9'h1F9 | validArray[505], + io_update_valid & update_idx == 9'h1F8 | validArray[504], + io_update_valid & update_idx == 9'h1F7 | validArray[503], + io_update_valid & update_idx == 9'h1F6 | validArray[502], + io_update_valid & update_idx == 9'h1F5 | validArray[501], + io_update_valid & update_idx == 9'h1F4 | validArray[500], + io_update_valid & update_idx == 9'h1F3 | validArray[499], + io_update_valid & update_idx == 9'h1F2 | validArray[498], + io_update_valid & update_idx == 9'h1F1 | validArray[497], + io_update_valid & update_idx == 9'h1F0 | validArray[496], + io_update_valid & update_idx == 9'h1EF | validArray[495], + io_update_valid & update_idx == 9'h1EE | validArray[494], + io_update_valid & update_idx == 9'h1ED | validArray[493], + io_update_valid & update_idx == 9'h1EC | validArray[492], + io_update_valid & update_idx == 9'h1EB | validArray[491], + io_update_valid & update_idx == 9'h1EA | validArray[490], + io_update_valid & update_idx == 9'h1E9 | validArray[489], + io_update_valid & update_idx == 9'h1E8 | validArray[488], + io_update_valid & update_idx == 9'h1E7 | validArray[487], + io_update_valid & update_idx == 9'h1E6 | validArray[486], + io_update_valid & update_idx == 9'h1E5 | validArray[485], + io_update_valid & update_idx == 9'h1E4 | validArray[484], + io_update_valid & update_idx == 9'h1E3 | validArray[483], + io_update_valid & update_idx == 9'h1E2 | validArray[482], + io_update_valid & update_idx == 9'h1E1 | validArray[481], + io_update_valid & update_idx == 9'h1E0 | validArray[480], + io_update_valid & update_idx == 9'h1DF | validArray[479], + io_update_valid & update_idx == 9'h1DE | validArray[478], + io_update_valid & update_idx == 9'h1DD | validArray[477], + io_update_valid & update_idx == 9'h1DC | validArray[476], + io_update_valid & update_idx == 9'h1DB | validArray[475], + io_update_valid & update_idx == 9'h1DA | validArray[474], + io_update_valid & update_idx == 9'h1D9 | validArray[473], + io_update_valid & update_idx == 9'h1D8 | validArray[472], + io_update_valid & update_idx == 9'h1D7 | validArray[471], + io_update_valid & update_idx == 9'h1D6 | validArray[470], + io_update_valid & update_idx == 9'h1D5 | validArray[469], + io_update_valid & update_idx == 9'h1D4 | validArray[468], + io_update_valid & update_idx == 9'h1D3 | validArray[467], + io_update_valid & update_idx == 9'h1D2 | validArray[466], + io_update_valid & update_idx == 9'h1D1 | validArray[465], + io_update_valid & update_idx == 9'h1D0 | validArray[464], + io_update_valid & update_idx == 9'h1CF | validArray[463], + io_update_valid & update_idx == 9'h1CE | validArray[462], + io_update_valid & update_idx == 9'h1CD | validArray[461], + io_update_valid & update_idx == 9'h1CC | validArray[460], + io_update_valid & update_idx == 9'h1CB | validArray[459], + io_update_valid & update_idx == 9'h1CA | validArray[458], + io_update_valid & update_idx == 9'h1C9 | validArray[457], + io_update_valid & update_idx == 9'h1C8 | validArray[456], + io_update_valid & update_idx == 9'h1C7 | validArray[455], + io_update_valid & update_idx == 9'h1C6 | validArray[454], + io_update_valid & update_idx == 9'h1C5 | validArray[453], + io_update_valid & update_idx == 9'h1C4 | validArray[452], + io_update_valid & update_idx == 9'h1C3 | validArray[451], + io_update_valid & update_idx == 9'h1C2 | validArray[450], + io_update_valid & update_idx == 9'h1C1 | validArray[449], + io_update_valid & update_idx == 9'h1C0 | validArray[448], + io_update_valid & update_idx == 9'h1BF | validArray[447], + io_update_valid & update_idx == 9'h1BE | validArray[446], + io_update_valid & update_idx == 9'h1BD | validArray[445], + io_update_valid & update_idx == 9'h1BC | validArray[444], + io_update_valid & update_idx == 9'h1BB | validArray[443], + io_update_valid & update_idx == 9'h1BA | validArray[442], + io_update_valid & update_idx == 9'h1B9 | validArray[441], + io_update_valid & update_idx == 9'h1B8 | validArray[440], + io_update_valid & update_idx == 9'h1B7 | validArray[439], + io_update_valid & update_idx == 9'h1B6 | validArray[438], + io_update_valid & update_idx == 9'h1B5 | validArray[437], + io_update_valid & update_idx == 9'h1B4 | validArray[436], + io_update_valid & update_idx == 9'h1B3 | validArray[435], + io_update_valid & update_idx == 9'h1B2 | validArray[434], + io_update_valid & update_idx == 9'h1B1 | validArray[433], + io_update_valid & update_idx == 9'h1B0 | validArray[432], + io_update_valid & update_idx == 9'h1AF | validArray[431], + io_update_valid & update_idx == 9'h1AE | validArray[430], + io_update_valid & update_idx == 9'h1AD | validArray[429], + io_update_valid & update_idx == 9'h1AC | validArray[428], + io_update_valid & update_idx == 9'h1AB | validArray[427], + io_update_valid & update_idx == 9'h1AA | validArray[426], + io_update_valid & update_idx == 9'h1A9 | validArray[425], + io_update_valid & update_idx == 9'h1A8 | validArray[424], + io_update_valid & update_idx == 9'h1A7 | validArray[423], + io_update_valid & update_idx == 9'h1A6 | validArray[422], + io_update_valid & update_idx == 9'h1A5 | validArray[421], + io_update_valid & update_idx == 9'h1A4 | validArray[420], + io_update_valid & update_idx == 9'h1A3 | validArray[419], + io_update_valid & update_idx == 9'h1A2 | validArray[418], + io_update_valid & update_idx == 9'h1A1 | validArray[417], + io_update_valid & update_idx == 9'h1A0 | validArray[416], + io_update_valid & update_idx == 9'h19F | validArray[415], + io_update_valid & update_idx == 9'h19E | validArray[414], + io_update_valid & update_idx == 9'h19D | validArray[413], + io_update_valid & update_idx == 9'h19C | validArray[412], + io_update_valid & update_idx == 9'h19B | validArray[411], + io_update_valid & update_idx == 9'h19A | validArray[410], + io_update_valid & update_idx == 9'h199 | validArray[409], + io_update_valid & update_idx == 9'h198 | validArray[408], + io_update_valid & update_idx == 9'h197 | validArray[407], + io_update_valid & update_idx == 9'h196 | validArray[406], + io_update_valid & update_idx == 9'h195 | validArray[405], + io_update_valid & update_idx == 9'h194 | validArray[404], + io_update_valid & update_idx == 9'h193 | validArray[403], + io_update_valid & update_idx == 9'h192 | validArray[402], + io_update_valid & update_idx == 9'h191 | validArray[401], + io_update_valid & update_idx == 9'h190 | validArray[400], + io_update_valid & update_idx == 9'h18F | validArray[399], + io_update_valid & update_idx == 9'h18E | validArray[398], + io_update_valid & update_idx == 9'h18D | validArray[397], + io_update_valid & update_idx == 9'h18C | validArray[396], + io_update_valid & update_idx == 9'h18B | validArray[395], + io_update_valid & update_idx == 9'h18A | validArray[394], + io_update_valid & update_idx == 9'h189 | validArray[393], + io_update_valid & update_idx == 9'h188 | validArray[392], + io_update_valid & update_idx == 9'h187 | validArray[391], + io_update_valid & update_idx == 9'h186 | validArray[390], + io_update_valid & update_idx == 9'h185 | validArray[389], + io_update_valid & update_idx == 9'h184 | validArray[388], + io_update_valid & update_idx == 9'h183 | validArray[387], + io_update_valid & update_idx == 9'h182 | validArray[386], + io_update_valid & update_idx == 9'h181 | validArray[385], + io_update_valid & update_idx == 9'h180 | validArray[384], + io_update_valid & update_idx == 9'h17F | validArray[383], + io_update_valid & update_idx == 9'h17E | validArray[382], + io_update_valid & update_idx == 9'h17D | validArray[381], + io_update_valid & update_idx == 9'h17C | validArray[380], + io_update_valid & update_idx == 9'h17B | validArray[379], + io_update_valid & update_idx == 9'h17A | validArray[378], + io_update_valid & update_idx == 9'h179 | validArray[377], + io_update_valid & update_idx == 9'h178 | validArray[376], + io_update_valid & update_idx == 9'h177 | validArray[375], + io_update_valid & update_idx == 9'h176 | validArray[374], + io_update_valid & update_idx == 9'h175 | validArray[373], + io_update_valid & update_idx == 9'h174 | validArray[372], + io_update_valid & update_idx == 9'h173 | validArray[371], + io_update_valid & update_idx == 9'h172 | validArray[370], + io_update_valid & update_idx == 9'h171 | validArray[369], + io_update_valid & update_idx == 9'h170 | validArray[368], + io_update_valid & update_idx == 9'h16F | validArray[367], + io_update_valid & update_idx == 9'h16E | validArray[366], + io_update_valid & update_idx == 9'h16D | validArray[365], + io_update_valid & update_idx == 9'h16C | validArray[364], + io_update_valid & update_idx == 9'h16B | validArray[363], + io_update_valid & update_idx == 9'h16A | validArray[362], + io_update_valid & update_idx == 9'h169 | validArray[361], + io_update_valid & update_idx == 9'h168 | validArray[360], + io_update_valid & update_idx == 9'h167 | validArray[359], + io_update_valid & update_idx == 9'h166 | validArray[358], + io_update_valid & update_idx == 9'h165 | validArray[357], + io_update_valid & update_idx == 9'h164 | validArray[356], + io_update_valid & update_idx == 9'h163 | validArray[355], + io_update_valid & update_idx == 9'h162 | validArray[354], + io_update_valid & update_idx == 9'h161 | validArray[353], + io_update_valid & update_idx == 9'h160 | validArray[352], + io_update_valid & update_idx == 9'h15F | validArray[351], + io_update_valid & update_idx == 9'h15E | validArray[350], + io_update_valid & update_idx == 9'h15D | validArray[349], + io_update_valid & update_idx == 9'h15C | validArray[348], + io_update_valid & update_idx == 9'h15B | validArray[347], + io_update_valid & update_idx == 9'h15A | validArray[346], + io_update_valid & update_idx == 9'h159 | validArray[345], + io_update_valid & update_idx == 9'h158 | validArray[344], + io_update_valid & update_idx == 9'h157 | validArray[343], + io_update_valid & update_idx == 9'h156 | validArray[342], + io_update_valid & update_idx == 9'h155 | validArray[341], + io_update_valid & update_idx == 9'h154 | validArray[340], + io_update_valid & update_idx == 9'h153 | validArray[339], + io_update_valid & update_idx == 9'h152 | validArray[338], + io_update_valid & update_idx == 9'h151 | validArray[337], + io_update_valid & update_idx == 9'h150 | validArray[336], + io_update_valid & update_idx == 9'h14F | validArray[335], + io_update_valid & update_idx == 9'h14E | validArray[334], + io_update_valid & update_idx == 9'h14D | validArray[333], + io_update_valid & update_idx == 9'h14C | validArray[332], + io_update_valid & update_idx == 9'h14B | validArray[331], + io_update_valid & update_idx == 9'h14A | validArray[330], + io_update_valid & update_idx == 9'h149 | validArray[329], + io_update_valid & update_idx == 9'h148 | validArray[328], + io_update_valid & update_idx == 9'h147 | validArray[327], + io_update_valid & update_idx == 9'h146 | validArray[326], + io_update_valid & update_idx == 9'h145 | validArray[325], + io_update_valid & update_idx == 9'h144 | validArray[324], + io_update_valid & update_idx == 9'h143 | validArray[323], + io_update_valid & update_idx == 9'h142 | validArray[322], + io_update_valid & update_idx == 9'h141 | validArray[321], + io_update_valid & update_idx == 9'h140 | validArray[320], + io_update_valid & update_idx == 9'h13F | validArray[319], + io_update_valid & update_idx == 9'h13E | validArray[318], + io_update_valid & update_idx == 9'h13D | validArray[317], + io_update_valid & update_idx == 9'h13C | validArray[316], + io_update_valid & update_idx == 9'h13B | validArray[315], + io_update_valid & update_idx == 9'h13A | validArray[314], + io_update_valid & update_idx == 9'h139 | validArray[313], + io_update_valid & update_idx == 9'h138 | validArray[312], + io_update_valid & update_idx == 9'h137 | validArray[311], + io_update_valid & update_idx == 9'h136 | validArray[310], + io_update_valid & update_idx == 9'h135 | validArray[309], + io_update_valid & update_idx == 9'h134 | validArray[308], + io_update_valid & update_idx == 9'h133 | validArray[307], + io_update_valid & update_idx == 9'h132 | validArray[306], + io_update_valid & update_idx == 9'h131 | validArray[305], + io_update_valid & update_idx == 9'h130 | validArray[304], + io_update_valid & update_idx == 9'h12F | validArray[303], + io_update_valid & update_idx == 9'h12E | validArray[302], + io_update_valid & update_idx == 9'h12D | validArray[301], + io_update_valid & update_idx == 9'h12C | validArray[300], + io_update_valid & update_idx == 9'h12B | validArray[299], + io_update_valid & update_idx == 9'h12A | validArray[298], + io_update_valid & update_idx == 9'h129 | validArray[297], + io_update_valid & update_idx == 9'h128 | validArray[296], + io_update_valid & update_idx == 9'h127 | validArray[295], + io_update_valid & update_idx == 9'h126 | validArray[294], + io_update_valid & update_idx == 9'h125 | validArray[293], + io_update_valid & update_idx == 9'h124 | validArray[292], + io_update_valid & update_idx == 9'h123 | validArray[291], + io_update_valid & update_idx == 9'h122 | validArray[290], + io_update_valid & update_idx == 9'h121 | validArray[289], + io_update_valid & update_idx == 9'h120 | validArray[288], + io_update_valid & update_idx == 9'h11F | validArray[287], + io_update_valid & update_idx == 9'h11E | validArray[286], + io_update_valid & update_idx == 9'h11D | validArray[285], + io_update_valid & update_idx == 9'h11C | validArray[284], + io_update_valid & update_idx == 9'h11B | validArray[283], + io_update_valid & update_idx == 9'h11A | validArray[282], + io_update_valid & update_idx == 9'h119 | validArray[281], + io_update_valid & update_idx == 9'h118 | validArray[280], + io_update_valid & update_idx == 9'h117 | validArray[279], + io_update_valid & update_idx == 9'h116 | validArray[278], + io_update_valid & update_idx == 9'h115 | validArray[277], + io_update_valid & update_idx == 9'h114 | validArray[276], + io_update_valid & update_idx == 9'h113 | validArray[275], + io_update_valid & update_idx == 9'h112 | validArray[274], + io_update_valid & update_idx == 9'h111 | validArray[273], + io_update_valid & update_idx == 9'h110 | validArray[272], + io_update_valid & update_idx == 9'h10F | validArray[271], + io_update_valid & update_idx == 9'h10E | validArray[270], + io_update_valid & update_idx == 9'h10D | validArray[269], + io_update_valid & update_idx == 9'h10C | validArray[268], + io_update_valid & update_idx == 9'h10B | validArray[267], + io_update_valid & update_idx == 9'h10A | validArray[266], + io_update_valid & update_idx == 9'h109 | validArray[265], + io_update_valid & update_idx == 9'h108 | validArray[264], + io_update_valid & update_idx == 9'h107 | validArray[263], + io_update_valid & update_idx == 9'h106 | validArray[262], + io_update_valid & update_idx == 9'h105 | validArray[261], + io_update_valid & update_idx == 9'h104 | validArray[260], + io_update_valid & update_idx == 9'h103 | validArray[259], + io_update_valid & update_idx == 9'h102 | validArray[258], + io_update_valid & update_idx == 9'h101 | validArray[257], + io_update_valid & update_idx == 9'h100 | validArray[256], + io_update_valid & update_idx == 9'hFF | validArray[255], + io_update_valid & update_idx == 9'hFE | validArray[254], + io_update_valid & update_idx == 9'hFD | validArray[253], + io_update_valid & update_idx == 9'hFC | validArray[252], + io_update_valid & update_idx == 9'hFB | validArray[251], + io_update_valid & update_idx == 9'hFA | validArray[250], + io_update_valid & update_idx == 9'hF9 | validArray[249], + io_update_valid & update_idx == 9'hF8 | validArray[248], + io_update_valid & update_idx == 9'hF7 | validArray[247], + io_update_valid & update_idx == 9'hF6 | validArray[246], + io_update_valid & update_idx == 9'hF5 | validArray[245], + io_update_valid & update_idx == 9'hF4 | validArray[244], + io_update_valid & update_idx == 9'hF3 | validArray[243], + io_update_valid & update_idx == 9'hF2 | validArray[242], + io_update_valid & update_idx == 9'hF1 | validArray[241], + io_update_valid & update_idx == 9'hF0 | validArray[240], + io_update_valid & update_idx == 9'hEF | validArray[239], + io_update_valid & update_idx == 9'hEE | validArray[238], + io_update_valid & update_idx == 9'hED | validArray[237], + io_update_valid & update_idx == 9'hEC | validArray[236], + io_update_valid & update_idx == 9'hEB | validArray[235], + io_update_valid & update_idx == 9'hEA | validArray[234], + io_update_valid & update_idx == 9'hE9 | validArray[233], + io_update_valid & update_idx == 9'hE8 | validArray[232], + io_update_valid & update_idx == 9'hE7 | validArray[231], + io_update_valid & update_idx == 9'hE6 | validArray[230], + io_update_valid & update_idx == 9'hE5 | validArray[229], + io_update_valid & update_idx == 9'hE4 | validArray[228], + io_update_valid & update_idx == 9'hE3 | validArray[227], + io_update_valid & update_idx == 9'hE2 | validArray[226], + io_update_valid & update_idx == 9'hE1 | validArray[225], + io_update_valid & update_idx == 9'hE0 | validArray[224], + io_update_valid & update_idx == 9'hDF | validArray[223], + io_update_valid & update_idx == 9'hDE | validArray[222], + io_update_valid & update_idx == 9'hDD | validArray[221], + io_update_valid & update_idx == 9'hDC | validArray[220], + io_update_valid & update_idx == 9'hDB | validArray[219], + io_update_valid & update_idx == 9'hDA | validArray[218], + io_update_valid & update_idx == 9'hD9 | validArray[217], + io_update_valid & update_idx == 9'hD8 | validArray[216], + io_update_valid & update_idx == 9'hD7 | validArray[215], + io_update_valid & update_idx == 9'hD6 | validArray[214], + io_update_valid & update_idx == 9'hD5 | validArray[213], + io_update_valid & update_idx == 9'hD4 | validArray[212], + io_update_valid & update_idx == 9'hD3 | validArray[211], + io_update_valid & update_idx == 9'hD2 | validArray[210], + io_update_valid & update_idx == 9'hD1 | validArray[209], + io_update_valid & update_idx == 9'hD0 | validArray[208], + io_update_valid & update_idx == 9'hCF | validArray[207], + io_update_valid & update_idx == 9'hCE | validArray[206], + io_update_valid & update_idx == 9'hCD | validArray[205], + io_update_valid & update_idx == 9'hCC | validArray[204], + io_update_valid & update_idx == 9'hCB | validArray[203], + io_update_valid & update_idx == 9'hCA | validArray[202], + io_update_valid & update_idx == 9'hC9 | validArray[201], + io_update_valid & update_idx == 9'hC8 | validArray[200], + io_update_valid & update_idx == 9'hC7 | validArray[199], + io_update_valid & update_idx == 9'hC6 | validArray[198], + io_update_valid & update_idx == 9'hC5 | validArray[197], + io_update_valid & update_idx == 9'hC4 | validArray[196], + io_update_valid & update_idx == 9'hC3 | validArray[195], + io_update_valid & update_idx == 9'hC2 | validArray[194], + io_update_valid & update_idx == 9'hC1 | validArray[193], + io_update_valid & update_idx == 9'hC0 | validArray[192], + io_update_valid & update_idx == 9'hBF | validArray[191], + io_update_valid & update_idx == 9'hBE | validArray[190], + io_update_valid & update_idx == 9'hBD | validArray[189], + io_update_valid & update_idx == 9'hBC | validArray[188], + io_update_valid & update_idx == 9'hBB | validArray[187], + io_update_valid & update_idx == 9'hBA | validArray[186], + io_update_valid & update_idx == 9'hB9 | validArray[185], + io_update_valid & update_idx == 9'hB8 | validArray[184], + io_update_valid & update_idx == 9'hB7 | validArray[183], + io_update_valid & update_idx == 9'hB6 | validArray[182], + io_update_valid & update_idx == 9'hB5 | validArray[181], + io_update_valid & update_idx == 9'hB4 | validArray[180], + io_update_valid & update_idx == 9'hB3 | validArray[179], + io_update_valid & update_idx == 9'hB2 | validArray[178], + io_update_valid & update_idx == 9'hB1 | validArray[177], + io_update_valid & update_idx == 9'hB0 | validArray[176], + io_update_valid & update_idx == 9'hAF | validArray[175], + io_update_valid & update_idx == 9'hAE | validArray[174], + io_update_valid & update_idx == 9'hAD | validArray[173], + io_update_valid & update_idx == 9'hAC | validArray[172], + io_update_valid & update_idx == 9'hAB | validArray[171], + io_update_valid & update_idx == 9'hAA | validArray[170], + io_update_valid & update_idx == 9'hA9 | validArray[169], + io_update_valid & update_idx == 9'hA8 | validArray[168], + io_update_valid & update_idx == 9'hA7 | validArray[167], + io_update_valid & update_idx == 9'hA6 | validArray[166], + io_update_valid & update_idx == 9'hA5 | validArray[165], + io_update_valid & update_idx == 9'hA4 | validArray[164], + io_update_valid & update_idx == 9'hA3 | validArray[163], + io_update_valid & update_idx == 9'hA2 | validArray[162], + io_update_valid & update_idx == 9'hA1 | validArray[161], + io_update_valid & update_idx == 9'hA0 | validArray[160], + io_update_valid & update_idx == 9'h9F | validArray[159], + io_update_valid & update_idx == 9'h9E | validArray[158], + io_update_valid & update_idx == 9'h9D | validArray[157], + io_update_valid & update_idx == 9'h9C | validArray[156], + io_update_valid & update_idx == 9'h9B | validArray[155], + io_update_valid & update_idx == 9'h9A | validArray[154], + io_update_valid & update_idx == 9'h99 | validArray[153], + io_update_valid & update_idx == 9'h98 | validArray[152], + io_update_valid & update_idx == 9'h97 | validArray[151], + io_update_valid & update_idx == 9'h96 | validArray[150], + io_update_valid & update_idx == 9'h95 | validArray[149], + io_update_valid & update_idx == 9'h94 | validArray[148], + io_update_valid & update_idx == 9'h93 | validArray[147], + io_update_valid & update_idx == 9'h92 | validArray[146], + io_update_valid & update_idx == 9'h91 | validArray[145], + io_update_valid & update_idx == 9'h90 | validArray[144], + io_update_valid & update_idx == 9'h8F | validArray[143], + io_update_valid & update_idx == 9'h8E | validArray[142], + io_update_valid & update_idx == 9'h8D | validArray[141], + io_update_valid & update_idx == 9'h8C | validArray[140], + io_update_valid & update_idx == 9'h8B | validArray[139], + io_update_valid & update_idx == 9'h8A | validArray[138], + io_update_valid & update_idx == 9'h89 | validArray[137], + io_update_valid & update_idx == 9'h88 | validArray[136], + io_update_valid & update_idx == 9'h87 | validArray[135], + io_update_valid & update_idx == 9'h86 | validArray[134], + io_update_valid & update_idx == 9'h85 | validArray[133], + io_update_valid & update_idx == 9'h84 | validArray[132], + io_update_valid & update_idx == 9'h83 | validArray[131], + io_update_valid & update_idx == 9'h82 | validArray[130], + io_update_valid & update_idx == 9'h81 | validArray[129], + io_update_valid & update_idx == 9'h80 | validArray[128], + io_update_valid & update_idx == 9'h7F | validArray[127], + io_update_valid & update_idx == 9'h7E | validArray[126], + io_update_valid & update_idx == 9'h7D | validArray[125], + io_update_valid & update_idx == 9'h7C | validArray[124], + io_update_valid & update_idx == 9'h7B | validArray[123], + io_update_valid & update_idx == 9'h7A | validArray[122], + io_update_valid & update_idx == 9'h79 | validArray[121], + io_update_valid & update_idx == 9'h78 | validArray[120], + io_update_valid & update_idx == 9'h77 | validArray[119], + io_update_valid & update_idx == 9'h76 | validArray[118], + io_update_valid & update_idx == 9'h75 | validArray[117], + io_update_valid & update_idx == 9'h74 | validArray[116], + io_update_valid & update_idx == 9'h73 | validArray[115], + io_update_valid & update_idx == 9'h72 | validArray[114], + io_update_valid & update_idx == 9'h71 | validArray[113], + io_update_valid & update_idx == 9'h70 | validArray[112], + io_update_valid & update_idx == 9'h6F | validArray[111], + io_update_valid & update_idx == 9'h6E | validArray[110], + io_update_valid & update_idx == 9'h6D | validArray[109], + io_update_valid & update_idx == 9'h6C | validArray[108], + io_update_valid & update_idx == 9'h6B | validArray[107], + io_update_valid & update_idx == 9'h6A | validArray[106], + io_update_valid & update_idx == 9'h69 | validArray[105], + io_update_valid & update_idx == 9'h68 | validArray[104], + io_update_valid & update_idx == 9'h67 | validArray[103], + io_update_valid & update_idx == 9'h66 | validArray[102], + io_update_valid & update_idx == 9'h65 | validArray[101], + io_update_valid & update_idx == 9'h64 | validArray[100], + io_update_valid & update_idx == 9'h63 | validArray[99], + io_update_valid & update_idx == 9'h62 | validArray[98], + io_update_valid & update_idx == 9'h61 | validArray[97], + io_update_valid & update_idx == 9'h60 | validArray[96], + io_update_valid & update_idx == 9'h5F | validArray[95], + io_update_valid & update_idx == 9'h5E | validArray[94], + io_update_valid & update_idx == 9'h5D | validArray[93], + io_update_valid & update_idx == 9'h5C | validArray[92], + io_update_valid & update_idx == 9'h5B | validArray[91], + io_update_valid & update_idx == 9'h5A | validArray[90], + io_update_valid & update_idx == 9'h59 | validArray[89], + io_update_valid & update_idx == 9'h58 | validArray[88], + io_update_valid & update_idx == 9'h57 | validArray[87], + io_update_valid & update_idx == 9'h56 | validArray[86], + io_update_valid & update_idx == 9'h55 | validArray[85], + io_update_valid & update_idx == 9'h54 | validArray[84], + io_update_valid & update_idx == 9'h53 | validArray[83], + io_update_valid & update_idx == 9'h52 | validArray[82], + io_update_valid & update_idx == 9'h51 | validArray[81], + io_update_valid & update_idx == 9'h50 | validArray[80], + io_update_valid & update_idx == 9'h4F | validArray[79], + io_update_valid & update_idx == 9'h4E | validArray[78], + io_update_valid & update_idx == 9'h4D | validArray[77], + io_update_valid & update_idx == 9'h4C | validArray[76], + io_update_valid & update_idx == 9'h4B | validArray[75], + io_update_valid & update_idx == 9'h4A | validArray[74], + io_update_valid & update_idx == 9'h49 | validArray[73], + io_update_valid & update_idx == 9'h48 | validArray[72], + io_update_valid & update_idx == 9'h47 | validArray[71], + io_update_valid & update_idx == 9'h46 | validArray[70], + io_update_valid & update_idx == 9'h45 | validArray[69], + io_update_valid & update_idx == 9'h44 | validArray[68], + io_update_valid & update_idx == 9'h43 | validArray[67], + io_update_valid & update_idx == 9'h42 | validArray[66], + io_update_valid & update_idx == 9'h41 | validArray[65], + io_update_valid & update_idx == 9'h40 | validArray[64], + io_update_valid & update_idx == 9'h3F | validArray[63], + io_update_valid & update_idx == 9'h3E | validArray[62], + io_update_valid & update_idx == 9'h3D | validArray[61], + io_update_valid & update_idx == 9'h3C | validArray[60], + io_update_valid & update_idx == 9'h3B | validArray[59], + io_update_valid & update_idx == 9'h3A | validArray[58], + io_update_valid & update_idx == 9'h39 | validArray[57], + io_update_valid & update_idx == 9'h38 | validArray[56], + io_update_valid & update_idx == 9'h37 | validArray[55], + io_update_valid & update_idx == 9'h36 | validArray[54], + io_update_valid & update_idx == 9'h35 | validArray[53], + io_update_valid & update_idx == 9'h34 | validArray[52], + io_update_valid & update_idx == 9'h33 | validArray[51], + io_update_valid & update_idx == 9'h32 | validArray[50], + io_update_valid & update_idx == 9'h31 | validArray[49], + io_update_valid & update_idx == 9'h30 | validArray[48], + io_update_valid & update_idx == 9'h2F | validArray[47], + io_update_valid & update_idx == 9'h2E | validArray[46], + io_update_valid & update_idx == 9'h2D | validArray[45], + io_update_valid & update_idx == 9'h2C | validArray[44], + io_update_valid & update_idx == 9'h2B | validArray[43], + io_update_valid & update_idx == 9'h2A | validArray[42], + io_update_valid & update_idx == 9'h29 | validArray[41], + io_update_valid & update_idx == 9'h28 | validArray[40], + io_update_valid & update_idx == 9'h27 | validArray[39], + io_update_valid & update_idx == 9'h26 | validArray[38], + io_update_valid & update_idx == 9'h25 | validArray[37], + io_update_valid & update_idx == 9'h24 | validArray[36], + io_update_valid & update_idx == 9'h23 | validArray[35], + io_update_valid & update_idx == 9'h22 | validArray[34], + io_update_valid & update_idx == 9'h21 | validArray[33], + io_update_valid & update_idx == 9'h20 | validArray[32], + io_update_valid & update_idx == 9'h1F | validArray[31], + io_update_valid & update_idx == 9'h1E | validArray[30], + io_update_valid & update_idx == 9'h1D | validArray[29], + io_update_valid & update_idx == 9'h1C | validArray[28], + io_update_valid & update_idx == 9'h1B | validArray[27], + io_update_valid & update_idx == 9'h1A | validArray[26], + io_update_valid & update_idx == 9'h19 | validArray[25], + io_update_valid & update_idx == 9'h18 | validArray[24], + io_update_valid & update_idx == 9'h17 | validArray[23], + io_update_valid & update_idx == 9'h16 | validArray[22], + io_update_valid & update_idx == 9'h15 | validArray[21], + io_update_valid & update_idx == 9'h14 | validArray[20], + io_update_valid & update_idx == 9'h13 | validArray[19], + io_update_valid & update_idx == 9'h12 | validArray[18], + io_update_valid & update_idx == 9'h11 | validArray[17], + io_update_valid & update_idx == 9'h10 | validArray[16], + io_update_valid & update_idx == 9'hF | validArray[15], + io_update_valid & update_idx == 9'hE | validArray[14], + io_update_valid & update_idx == 9'hD | validArray[13], + io_update_valid & update_idx == 9'hC | validArray[12], + io_update_valid & update_idx == 9'hB | validArray[11], + io_update_valid & update_idx == 9'hA | validArray[10], + io_update_valid & update_idx == 9'h9 | validArray[9], + io_update_valid & update_idx == 9'h8 | validArray[8], + io_update_valid & update_idx == 9'h7 | validArray[7], + io_update_valid & update_idx == 9'h6 | validArray[6], + io_update_valid & update_idx == 9'h5 | validArray[5], + io_update_valid & update_idx == 9'h4 | validArray[4], + io_update_valid & update_idx == 9'h3 | validArray[3], + io_update_valid & update_idx == 9'h2 | validArray[2], + io_update_valid & update_idx == 9'h1 | validArray[1], + io_update_valid & update_idx == 9'h0 | validArray[0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :200:27, :283:{30,42}, :284:26, :285:31, :286:33 + always @(posedge clock or posedge reset) begin + if (reset) + validArray <= 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + else if (io_update_valid) // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + validArray <= _validArray_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27, :286:33 + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_req_valid) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:145:14 + s1_idx <= s0_idx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31, :213:36 + s1_tag <= + io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_10_folded_hist + ^ {io_req_bits_folded_hist_hist_3_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:86, :182:{32,52,61,75}, :207:43, :213:68 + s1_bank_req_1h_0 <= ~(s0_idx[0]); // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :215:33 + s1_bank_req_1h_1 <= s0_idx[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :215:33 + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:240:48, :255:33 + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:16]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + for (logic [4:0] i = 5'h0; i < 5'h11; i += 5'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + end // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + validArray = + {_RANDOM[5'h0], + _RANDOM[5'h1], + _RANDOM[5'h2], + _RANDOM[5'h3], + _RANDOM[5'h4], + _RANDOM[5'h5], + _RANDOM[5'h6], + _RANDOM[5'h7], + _RANDOM[5'h8], + _RANDOM[5'h9], + _RANDOM[5'hA], + _RANDOM[5'hB], + _RANDOM[5'hC], + _RANDOM[5'hD], + _RANDOM[5'hE], + _RANDOM[5'hF]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :200:27 + s1_idx = _RANDOM[5'h10][8:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36 + s1_tag = _RANDOM[5'h10][17:9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:{36,68} + s1_bank_req_1h_0 = _RANDOM[5'h10][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 + s1_bank_req_1h_1 = _RANDOM[5'h10][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :215:33 + s1_bank_has_write_on_this_req_0 = _RANDOM[5'h10][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + s1_bank_has_write_on_this_req_1 = _RANDOM[5'h10][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:36, :240:48 + `endif // RANDOMIZE_REG_INIT + if (reset) // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + validArray = 512'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:200:27 + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Folded1WDataModuleTemplate_2 us ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:217:18 + .clock (clock), + .reset (reset), + .io_raddr_0 (s0_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_rdata_0 (_us_io_rdata_0), + .io_wen (io_update_uValid), + .io_waddr (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_wdata (io_update_u), + .io_resetEn (io_update_reset_u) + ); + FoldedSRAMTemplate_25 table_banks_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & ~(s0_idx[0])), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:{66,86}, :181:{31,40}, :223:50 + .io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 + .io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + ); + FoldedSRAMTemplate_25 table_banks_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:220:11 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & s0_idx[0]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:160:66, :181:{31,40}, :223:50 + .io_r_req_bits_setIdx (s0_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/ITTAGE.scala:255:33 + .io_w_req_bits_setIdx (update_idx[8:1]), // src/main/scala/xiangshan/frontend/ITTAGE.scala:161:37, :181:{31,40} + .io_w_req_bits_data_0_tag (update_wdata_tag), // src/main/scala/xiangshan/frontend/ITTAGE.scala:182:61 + .io_w_req_bits_data_0_ctr (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_w_req_bits_data_0_target (update_wdata_target) // src/main/scala/xiangshan/frontend/ITTAGE.scala:281:29 + ); + WrBypass_43 wrbypass ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:271:24 + .clock (clock), + .reset (reset), + .io_wen (io_update_valid), + .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/ITTAGE.scala:181:31 + .io_write_data_0 (update_wdata_ctr), // src/main/scala/xiangshan/frontend/ITTAGE.scala:278:28 + .io_hit (_wrbypass_io_hit), + .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) + ); + assign io_resp_valid = + _s1_req_rhit_T[0] + & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag + & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :213:68, :215:33, :220:11, :232:{31,61}, :235:{50,53}, :285:31 + assign io_resp_bits_ctr = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :160:86, :217:18, :237:18 + assign io_resp_bits_target = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 39'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:140:7, :215:33, :220:11 +endmodule + diff --git a/src/TageSC/CAMTemplate.sv b/src/TageSC/CAMTemplate.sv new file mode 100644 index 0000000..8b2a543 --- /dev/null +++ b/src/TageSC/CAMTemplate.sv @@ -0,0 +1,136 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module CAMTemplate( // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + input clock, + input [8:0] io_r_req_0_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_0, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_1, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_2, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_3, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_4, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_5, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_6, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_7, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + input io_w_valid, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + input [8:0] io_w_bits_data_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + input [2:0] io_w_bits_index // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 +); + + reg [8:0] array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [8:0] array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [8:0] array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [8:0] array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [8:0] array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [8:0] array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [8:0] array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [8:0] array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + always @(posedge clock) begin + if (io_w_valid & io_w_bits_index == 3'h0) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_0 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 3'h1) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_1 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 3'h2) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_2 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 3'h3) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_3 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 3'h4) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_4 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 3'h5) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_5 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 3'h6) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_6 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & (&io_w_bits_index)) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_7 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + initial begin // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + end // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + array_0 = _RANDOM[2'h0][8:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_1 = _RANDOM[2'h0][17:9]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_2 = _RANDOM[2'h0][26:18]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][3:0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_4 = _RANDOM[2'h1][12:4]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_5 = _RANDOM[2'h1][21:13]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_6 = _RANDOM[2'h1][30:22]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_7 = {_RANDOM[2'h1][31], _RANDOM[2'h2][7:0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_4 = io_r_req_0_idx == array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_5 = io_r_req_0_idx == array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_6 = io_r_req_0_idx == array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_7 = io_r_req_0_idx == array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 +endmodule + diff --git a/src/TageSC/CAMTemplate_32.sv b/src/TageSC/CAMTemplate_32.sv new file mode 100644 index 0000000..1cd4bc9 --- /dev/null +++ b/src/TageSC/CAMTemplate_32.sv @@ -0,0 +1,136 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module CAMTemplate_32( // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + input clock, + input [10:0] io_r_req_0_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_0, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_1, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_2, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_3, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_4, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_5, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_6, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_7, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + input io_w_valid, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + input [10:0] io_w_bits_data_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + input [2:0] io_w_bits_index // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 +); + + reg [10:0] array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [10:0] array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [10:0] array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [10:0] array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [10:0] array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [10:0] array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [10:0] array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [10:0] array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + always @(posedge clock) begin + if (io_w_valid & io_w_bits_index == 3'h0) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_0 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 3'h1) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_1 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 3'h2) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_2 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 3'h3) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_3 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 3'h4) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_4 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 3'h5) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_5 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 3'h6) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_6 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & (&io_w_bits_index)) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_7 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + initial begin // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + end // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + array_0 = _RANDOM[2'h0][10:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_1 = _RANDOM[2'h0][21:11]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_2 = {_RANDOM[2'h0][31:22], _RANDOM[2'h1][0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_3 = _RANDOM[2'h1][11:1]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_4 = _RANDOM[2'h1][22:12]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_5 = {_RANDOM[2'h1][31:23], _RANDOM[2'h2][1:0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_6 = _RANDOM[2'h2][12:2]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_7 = _RANDOM[2'h2][23:13]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_4 = io_r_req_0_idx == array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_5 = io_r_req_0_idx == array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_6 = io_r_req_0_idx == array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_7 = io_r_req_0_idx == array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 +endmodule + diff --git a/src/TageSC/CAMTemplate_33.sv b/src/TageSC/CAMTemplate_33.sv new file mode 100644 index 0000000..28a6605 --- /dev/null +++ b/src/TageSC/CAMTemplate_33.sv @@ -0,0 +1,184 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module CAMTemplate_33( // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + input clock, + input [7:0] io_r_req_0_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_0, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_1, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_2, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_3, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_4, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_5, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_6, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_7, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_8, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_9, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_10, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_11, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_12, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_13, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_14, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + output io_r_resp_0_15, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + input io_w_valid, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + input [7:0] io_w_bits_data_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 + input [3:0] io_w_bits_index // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14 +); + + reg [7:0] array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_8; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_9; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_10; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_11; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_12; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_13; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_14; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + reg [7:0] array_15; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + always @(posedge clock) begin + if (io_w_valid & io_w_bits_index == 4'h0) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_0 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'h1) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_1 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'h2) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_2 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'h3) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_3 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'h4) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_4 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'h5) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_5 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'h6) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_6 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'h7) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_7 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'h8) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_8 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'h9) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_9 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'hA) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_10 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'hB) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_11 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'hC) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_12 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'hD) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_13 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & io_w_bits_index == 4'hE) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_14 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + if (io_w_valid & (&io_w_bits_index)) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28 + array_15 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + initial begin // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + end // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + array_0 = _RANDOM[2'h0][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_1 = _RANDOM[2'h0][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_2 = _RANDOM[2'h0][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_3 = _RANDOM[2'h0][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_4 = _RANDOM[2'h1][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_5 = _RANDOM[2'h1][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_6 = _RANDOM[2'h1][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_7 = _RANDOM[2'h1][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_8 = _RANDOM[2'h2][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_9 = _RANDOM[2'h2][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_10 = _RANDOM[2'h2][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_11 = _RANDOM[2'h2][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_12 = _RANDOM[2'h3][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_13 = _RANDOM[2'h3][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_14 = _RANDOM[2'h3][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + array_15 = _RANDOM[2'h3][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_4 = io_r_req_0_idx == array_4; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_5 = io_r_req_0_idx == array_5; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_6 = io_r_req_0_idx == array_6; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_7 = io_r_req_0_idx == array_7; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_8 = io_r_req_0_idx == array_8; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_9 = io_r_req_0_idx == array_9; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_10 = io_r_req_0_idx == array_10; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_11 = io_r_req_0_idx == array_11; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_12 = io_r_req_0_idx == array_12; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_13 = io_r_req_0_idx == array_13; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_14 = io_r_req_0_idx == array_14; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 + assign io_r_resp_0_15 = io_r_req_0_idx == array_15; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39 +endmodule + diff --git a/src/TageSC/FoldedSRAMTemplate.sv b/src/TageSC/FoldedSRAMTemplate.sv new file mode 100644 index 0000000..98cd5b7 --- /dev/null +++ b/src/TageSC/FoldedSRAMTemplate.sv @@ -0,0 +1,209 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FoldedSRAMTemplate( // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + input clock, + input reset, + output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [10:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + output io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + output io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [10:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [1:0] io_w_req_bits_waymask, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input extra_reset // utility/src/main/scala/utility/SRAMTemplate.scala:169:44 +); + + wire _array_io_r_resp_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_4; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_5; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_6; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_7; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_8; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_9; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_10; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_11; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_12; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_13; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_14; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire _array_io_r_resp_data_15; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + reg [2:0] ridx; // utility/src/main/scala/utility/SRAMTemplate.scala:189:21 + reg holdRidx_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 + reg [2:0] holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82 + wire [2:0] holdRidx = holdRidx_REG ? ridx : holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44 + reg holdRidx_REG_1; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 + reg [2:0] holdRidx_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82 + wire [2:0] holdRidx_1 = holdRidx_REG_1 ? ridx : holdRidx_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44 + wire _wmask_T_3 = io_w_req_bits_setIdx[2:0] == 3'h0; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 + wire _wmask_T_9 = io_w_req_bits_setIdx[2:0] == 3'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 + wire _wmask_T_15 = io_w_req_bits_setIdx[2:0] == 3'h2; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 + wire _wmask_T_21 = io_w_req_bits_setIdx[2:0] == 3'h3; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 + wire _wmask_T_27 = io_w_req_bits_setIdx[2:0] == 3'h4; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 + wire _wmask_T_33 = io_w_req_bits_setIdx[2:0] == 3'h5; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 + wire _wmask_T_39 = io_w_req_bits_setIdx[2:0] == 3'h6; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 + always @(posedge clock) begin + ridx <= io_r_req_bits_setIdx[2:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:189:{21,58} + holdRidx_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 + if (holdRidx_REG) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 + holdRidx_hold_data <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21 + holdRidx_REG_1 <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 + if (holdRidx_REG_1) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 + holdRidx_hold_data_1 <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + ridx = _RANDOM[/*Zero width*/ 1'b0][2:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 + holdRidx_REG = _RANDOM[/*Zero width*/ 1'b0][3]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44 + holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][6:4]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 + holdRidx_REG_1 = _RANDOM[/*Zero width*/ 1'b0][7]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44 + holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][10:8]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_10 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + .clock (clock), + .reset (reset), + .io_r_req_ready (io_r_req_ready), + .io_r_req_valid (io_r_req_valid), + .io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:3]), // utility/src/main/scala/utility/SRAMTemplate.scala:188:36 + .io_r_resp_data_0 (_array_io_r_resp_data_0), + .io_r_resp_data_1 (_array_io_r_resp_data_1), + .io_r_resp_data_2 (_array_io_r_resp_data_2), + .io_r_resp_data_3 (_array_io_r_resp_data_3), + .io_r_resp_data_4 (_array_io_r_resp_data_4), + .io_r_resp_data_5 (_array_io_r_resp_data_5), + .io_r_resp_data_6 (_array_io_r_resp_data_6), + .io_r_resp_data_7 (_array_io_r_resp_data_7), + .io_r_resp_data_8 (_array_io_r_resp_data_8), + .io_r_resp_data_9 (_array_io_r_resp_data_9), + .io_r_resp_data_10 (_array_io_r_resp_data_10), + .io_r_resp_data_11 (_array_io_r_resp_data_11), + .io_r_resp_data_12 (_array_io_r_resp_data_12), + .io_r_resp_data_13 (_array_io_r_resp_data_13), + .io_r_resp_data_14 (_array_io_r_resp_data_14), + .io_r_resp_data_15 (_array_io_r_resp_data_15), + .io_w_req_valid (io_w_req_valid), + .io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:3]), // utility/src/main/scala/utility/SRAMTemplate.scala:205:36 + .io_w_req_bits_data_0 (io_w_req_bits_data_0), + .io_w_req_bits_data_1 (io_w_req_bits_data_1), + .io_w_req_bits_data_2 (io_w_req_bits_data_0), + .io_w_req_bits_data_3 (io_w_req_bits_data_1), + .io_w_req_bits_data_4 (io_w_req_bits_data_0), + .io_w_req_bits_data_5 (io_w_req_bits_data_1), + .io_w_req_bits_data_6 (io_w_req_bits_data_0), + .io_w_req_bits_data_7 (io_w_req_bits_data_1), + .io_w_req_bits_data_8 (io_w_req_bits_data_0), + .io_w_req_bits_data_9 (io_w_req_bits_data_1), + .io_w_req_bits_data_10 (io_w_req_bits_data_0), + .io_w_req_bits_data_11 (io_w_req_bits_data_1), + .io_w_req_bits_data_12 (io_w_req_bits_data_0), + .io_w_req_bits_data_13 (io_w_req_bits_data_1), + .io_w_req_bits_data_14 (io_w_req_bits_data_0), + .io_w_req_bits_data_15 (io_w_req_bits_data_1), + .io_w_req_bits_waymask + ({(&(io_w_req_bits_setIdx[2:0])) & io_w_req_bits_waymask[1], + (&(io_w_req_bits_setIdx[2:0])) & io_w_req_bits_waymask[0], + _wmask_T_39 & io_w_req_bits_waymask[1], + _wmask_T_39 & io_w_req_bits_waymask[0], + _wmask_T_33 & io_w_req_bits_waymask[1], + _wmask_T_33 & io_w_req_bits_waymask[0], + _wmask_T_27 & io_w_req_bits_waymask[1], + _wmask_T_27 & io_w_req_bits_waymask[0], + _wmask_T_21 & io_w_req_bits_waymask[1], + _wmask_T_21 & io_w_req_bits_waymask[0], + _wmask_T_15 & io_w_req_bits_waymask[1], + _wmask_T_15 & io_w_req_bits_waymask[0], + _wmask_T_9 & io_w_req_bits_waymask[1], + _wmask_T_9 & io_w_req_bits_waymask[0], + _wmask_T_3 & io_w_req_bits_waymask[1], + _wmask_T_3 & io_w_req_bits_waymask[0]}), // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:{69,82,110,122} + .extra_reset (extra_reset) + ); + assign io_r_resp_data_0 = + holdRidx == 3'h0 & _array_io_r_resp_data_0 | holdRidx == 3'h1 + & _array_io_r_resp_data_2 | holdRidx == 3'h2 & _array_io_r_resp_data_4 + | holdRidx == 3'h3 & _array_io_r_resp_data_6 | holdRidx == 3'h4 + & _array_io_r_resp_data_8 | holdRidx == 3'h5 & _array_io_r_resp_data_10 + | holdRidx == 3'h6 & _array_io_r_resp_data_12 | (&holdRidx) + & _array_io_r_resp_data_14; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21, :210:69 + assign io_r_resp_data_1 = + holdRidx_1 == 3'h0 & _array_io_r_resp_data_1 | holdRidx_1 == 3'h1 + & _array_io_r_resp_data_3 | holdRidx_1 == 3'h2 & _array_io_r_resp_data_5 + | holdRidx_1 == 3'h3 & _array_io_r_resp_data_7 | holdRidx_1 == 3'h4 + & _array_io_r_resp_data_9 | holdRidx_1 == 3'h5 & _array_io_r_resp_data_11 + | holdRidx_1 == 3'h6 & _array_io_r_resp_data_13 | (&holdRidx_1) + & _array_io_r_resp_data_15; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21, :210:69 +endmodule + diff --git a/src/TageSC/FoldedSRAMTemplate_1.sv b/src/TageSC/FoldedSRAMTemplate_1.sv new file mode 100644 index 0000000..fdde6f2 --- /dev/null +++ b/src/TageSC/FoldedSRAMTemplate_1.sv @@ -0,0 +1,100 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FoldedSRAMTemplate_1( // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + input clock, + input reset, + output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [8:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + output io_r_resp_data_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + output [7:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + output [2:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + output io_r_resp_data_1_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + output [7:0] io_r_resp_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + output [2:0] io_r_resp_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [8:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [7:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [2:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [7:0] io_w_req_bits_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [2:0] io_w_req_bits_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [1:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 +); + + SRAMTemplate_11 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + .clock (clock), + .reset (reset), + .io_r_req_ready (io_r_req_ready), + .io_r_req_valid (io_r_req_valid), + .io_r_req_bits_setIdx (io_r_req_bits_setIdx), + .io_r_resp_data_0_valid (io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (io_r_resp_data_1_ctr), + .io_w_req_valid (io_w_req_valid), + .io_w_req_bits_setIdx (io_w_req_bits_setIdx), + .io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag), + .io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr), + .io_w_req_bits_data_1_tag (io_w_req_bits_data_1_tag), + .io_w_req_bits_data_1_ctr (io_w_req_bits_data_1_ctr), + .io_w_req_bits_waymask (io_w_req_bits_waymask) + ); +endmodule + diff --git a/src/TageSC/FoldedSRAMTemplate_20.sv b/src/TageSC/FoldedSRAMTemplate_20.sv new file mode 100644 index 0000000..1fdea3c --- /dev/null +++ b/src/TageSC/FoldedSRAMTemplate_20.sv @@ -0,0 +1,163 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FoldedSRAMTemplate_20( // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + input clock, + input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [10:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + output [1:0] io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + output [1:0] io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [10:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [1:0] io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [1:0] io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 + input [1:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:165:14 +); + + wire [1:0] _array_io_r_resp_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire [1:0] _array_io_r_resp_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire [1:0] _array_io_r_resp_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire [1:0] _array_io_r_resp_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire [1:0] _array_io_r_resp_data_4; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire [1:0] _array_io_r_resp_data_5; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire [1:0] _array_io_r_resp_data_6; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + wire [1:0] _array_io_r_resp_data_7; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + reg [1:0] ridx; // utility/src/main/scala/utility/SRAMTemplate.scala:189:21 + reg holdRidx_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 + reg [1:0] holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82 + wire [1:0] holdRidx = holdRidx_REG ? ridx : holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44 + reg holdRidx_REG_1; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 + reg [1:0] holdRidx_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82 + wire [1:0] holdRidx_1 = holdRidx_REG_1 ? ridx : holdRidx_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44 + wire _wmask_T_3 = io_w_req_bits_setIdx[1:0] == 2'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 + wire _wmask_T_9 = io_w_req_bits_setIdx[1:0] == 2'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 + wire _wmask_T_15 = io_w_req_bits_setIdx[1:0] == 2'h2; // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:69 + always @(posedge clock) begin + ridx <= io_r_req_bits_setIdx[1:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:189:{21,58} + holdRidx_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 + if (holdRidx_REG) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 + holdRidx_hold_data <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21 + holdRidx_REG_1 <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 + if (holdRidx_REG_1) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44 + holdRidx_hold_data_1 <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + ridx = _RANDOM[/*Zero width*/ 1'b0][1:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 + holdRidx_REG = _RANDOM[/*Zero width*/ 1'b0][2]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44 + holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][4:3]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 + holdRidx_REG_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44 + holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][7:6]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_30 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:179:21 + .clock (clock), + .io_r_req_valid (io_r_req_valid), + .io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:2]), // utility/src/main/scala/utility/SRAMTemplate.scala:188:36 + .io_r_resp_data_0 (_array_io_r_resp_data_0), + .io_r_resp_data_1 (_array_io_r_resp_data_1), + .io_r_resp_data_2 (_array_io_r_resp_data_2), + .io_r_resp_data_3 (_array_io_r_resp_data_3), + .io_r_resp_data_4 (_array_io_r_resp_data_4), + .io_r_resp_data_5 (_array_io_r_resp_data_5), + .io_r_resp_data_6 (_array_io_r_resp_data_6), + .io_r_resp_data_7 (_array_io_r_resp_data_7), + .io_w_req_valid (io_w_req_valid), + .io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:2]), // utility/src/main/scala/utility/SRAMTemplate.scala:205:36 + .io_w_req_bits_data_0 (io_w_req_bits_data_0), + .io_w_req_bits_data_1 (io_w_req_bits_data_1), + .io_w_req_bits_data_2 (io_w_req_bits_data_0), + .io_w_req_bits_data_3 (io_w_req_bits_data_1), + .io_w_req_bits_data_4 (io_w_req_bits_data_0), + .io_w_req_bits_data_5 (io_w_req_bits_data_1), + .io_w_req_bits_data_6 (io_w_req_bits_data_0), + .io_w_req_bits_data_7 (io_w_req_bits_data_1), + .io_w_req_bits_waymask + ({(&(io_w_req_bits_setIdx[1:0])) & io_w_req_bits_waymask[1], + (&(io_w_req_bits_setIdx[1:0])) & io_w_req_bits_waymask[0], + _wmask_T_15 & io_w_req_bits_waymask[1], + _wmask_T_15 & io_w_req_bits_waymask[0], + _wmask_T_9 & io_w_req_bits_waymask[1], + _wmask_T_9 & io_w_req_bits_waymask[0], + _wmask_T_3 & io_w_req_bits_waymask[1], + _wmask_T_3 & io_w_req_bits_waymask[0]}) // utility/src/main/scala/utility/SRAMTemplate.scala:206:54, :210:{69,82,110,122} + ); + assign io_r_resp_data_0 = + (holdRidx == 2'h0 ? _array_io_r_resp_data_0 : 2'h0) + | (holdRidx == 2'h1 ? _array_io_r_resp_data_2 : 2'h0) + | (holdRidx == 2'h2 ? _array_io_r_resp_data_4 : 2'h0) + | ((&holdRidx) ? _array_io_r_resp_data_6 : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21, :210:69 + assign io_r_resp_data_1 = + (holdRidx_1 == 2'h0 ? _array_io_r_resp_data_1 : 2'h0) + | (holdRidx_1 == 2'h1 ? _array_io_r_resp_data_3 : 2'h0) + | (holdRidx_1 == 2'h2 ? _array_io_r_resp_data_5 : 2'h0) + | ((&holdRidx_1) ? _array_io_r_resp_data_7 : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21, :210:69 +endmodule + diff --git a/src/TageSC/SCTable.sv b/src/TageSC/SCTable.sv new file mode 100644 index 0000000..9db7c8a --- /dev/null +++ b/src/TageSC/SCTable.sv @@ -0,0 +1,253 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SCTable( // src/main/scala/xiangshan/frontend/SC.scala:66:7 + input clock, + input reset, + input io_req_valid, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_0_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_0_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_1_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_1_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_mask_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_mask_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [5:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [5:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_tagePreds_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_tagePreds_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_takens_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_takens_1 // src/main/scala/xiangshan/frontend/SC.scala:68:14 +); + + wire _wrbypasses_1_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_1_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_0_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_0_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _table_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + wire [5:0] _table_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + wire [5:0] _table_io_r_resp_data_2; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + wire [5:0] _table_io_r_resp_data_3; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + reg [38:0] s1_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 + wire per_br_update_way_mask_0_0 = + io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire per_br_update_way_mask_0_1 = + io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire per_br_update_way_mask_1_0 = + io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + wire per_br_update_way_mask_1_1 = + io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + wire ctrPos = + ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire [5:0] oldCtr = + (~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit) + & (ctrPos + ? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_1_valid + : ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos + ? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0) + : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0)) + : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0) + | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire taken = + ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire [5:0] per_br_update_wdata_packed_0_1 = + oldCtr == 6'h1F & taken + ? 6'h1F + : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 + wire ctrPos_1 = + io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + wire [5:0] oldCtr_1 = + (io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit) + & (ctrPos_1 + ? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_1_valid + : io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos_1 + ? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits) + : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits)) + : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0) + | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + wire taken_1 = + io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + wire [5:0] per_br_update_wdata_packed_1_1 = + oldCtr_1 == 6'h1F & taken_1 + ? 6'h1F + : oldCtr_1 == 6'h20 & ~taken_1 + ? 6'h20 + : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 + wire [5:0] _GEN = + (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_0_1) + | (io_update_pc[1] ? per_br_update_wdata_packed_1_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire [5:0] _GEN_0 = + (io_update_pc[1] ? per_br_update_wdata_packed_0_1 : 6'h0) + | (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_1_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + always @(posedge clock) begin + if (io_req_valid) // src/main/scala/xiangshan/frontend/SC.scala:68:14 + s1_pc <= io_req_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/SC.scala:66:7 + initial begin // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/SC.scala:66:7 + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/SC.scala:66:7 + end // src/main/scala/xiangshan/frontend/SC.scala:66:7 + s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][14:0]}; // src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_31 table_0 ( // src/main/scala/xiangshan/frontend/SC.scala:71:21 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid), + .io_r_req_bits_setIdx (io_req_bits_pc[8:1]), // src/main/scala/xiangshan/frontend/SC.scala:89:{11,29} + .io_r_resp_data_0 (_table_io_r_resp_data_0), + .io_r_resp_data_1 (_table_io_r_resp_data_1), + .io_r_resp_data_2 (_table_io_r_resp_data_2), + .io_r_resp_data_3 (_table_io_r_resp_data_3), + .io_w_req_valid (io_update_mask_0 | io_update_mask_1), // src/main/scala/xiangshan/frontend/SC.scala:130:36 + .io_w_req_bits_setIdx (io_update_pc[8:1]), // src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42 + .io_w_req_bits_data_0 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_data_1 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_data_2 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_data_3 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_waymask + ({per_br_update_way_mask_1_1, + per_br_update_way_mask_1_0, + per_br_update_way_mask_0_1, + per_br_update_way_mask_0_0}) // src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29 + ); + WrBypass_33 wrbypasses_0 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0), + .io_write_idx (io_update_pc[8:1]), // src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42 + .io_write_data_0 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_data_1 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_way_mask_0 + (~(io_update_pc[1]) & per_br_update_way_mask_0_0 | io_update_pc[1] + & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + .io_write_way_mask_1 + (~(io_update_pc[1]) & per_br_update_way_mask_0_1 | io_update_pc[1] + & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + .io_hit (_wrbypasses_0_io_hit), + .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits) + ); + WrBypass_33 wrbypasses_1 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1), + .io_write_idx (io_update_pc[8:1]), // src/main/scala/xiangshan/frontend/SC.scala:89:29, :117:42 + .io_write_data_0 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_data_1 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_way_mask_0 + (io_update_pc[1] & per_br_update_way_mask_0_0 | ~(io_update_pc[1]) + & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + .io_write_way_mask_1 + (io_update_pc[1] & per_br_update_way_mask_0_1 | ~(io_update_pc[1]) + & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + .io_hit (_wrbypasses_1_io_hit), + .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits) + ); + assign io_resp_ctrs_0_0 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0) + | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + assign io_resp_ctrs_0_1 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1) + | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + assign io_resp_ctrs_1_0 = + (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + assign io_resp_ctrs_1_1 = + (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 +endmodule + diff --git a/src/TageSC/SCTable_1.sv b/src/TageSC/SCTable_1.sv new file mode 100644 index 0000000..1442041 --- /dev/null +++ b/src/TageSC/SCTable_1.sv @@ -0,0 +1,259 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SCTable_1( // src/main/scala/xiangshan/frontend/SC.scala:66:7 + input clock, + input reset, + input io_req_valid, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [3:0] io_req_bits_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_0_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_0_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_1_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_1_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [3:0] io_update_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_mask_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_mask_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [5:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [5:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_tagePreds_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_tagePreds_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_takens_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_takens_1 // src/main/scala/xiangshan/frontend/SC.scala:68:14 +); + + wire _wrbypasses_1_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_1_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_0_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_0_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _table_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + wire [5:0] _table_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + wire [5:0] _table_io_r_resp_data_2; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + wire [5:0] _table_io_r_resp_data_3; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + reg [38:0] s1_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 + wire per_br_update_way_mask_0_0 = + io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire per_br_update_way_mask_0_1 = + io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire per_br_update_way_mask_1_0 = + io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + wire per_br_update_way_mask_1_1 = + io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + wire [7:0] update_idx = + {io_update_pc[8:5], io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist}; // src/main/scala/xiangshan/frontend/SC.scala:86:{31,40}, :117:42 + wire ctrPos = + ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire [5:0] oldCtr = + (~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit) + & (ctrPos + ? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_1_valid + : ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos + ? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0) + : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0)) + : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0) + | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire taken = + ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire [5:0] per_br_update_wdata_packed_0_1 = + oldCtr == 6'h1F & taken + ? 6'h1F + : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 + wire ctrPos_1 = + io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + wire [5:0] oldCtr_1 = + (io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit) + & (ctrPos_1 + ? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_1_valid + : io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos_1 + ? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits) + : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits)) + : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0) + | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + wire taken_1 = + io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + wire [5:0] per_br_update_wdata_packed_1_1 = + oldCtr_1 == 6'h1F & taken_1 + ? 6'h1F + : oldCtr_1 == 6'h20 & ~taken_1 + ? 6'h20 + : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 + wire [5:0] _GEN = + (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_0_1) + | (io_update_pc[1] ? per_br_update_wdata_packed_1_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire [5:0] _GEN_0 = + (io_update_pc[1] ? per_br_update_wdata_packed_0_1 : 6'h0) + | (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_1_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + always @(posedge clock) begin + if (io_req_valid) // src/main/scala/xiangshan/frontend/SC.scala:68:14 + s1_pc <= io_req_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/SC.scala:66:7 + initial begin // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/SC.scala:66:7 + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/SC.scala:66:7 + end // src/main/scala/xiangshan/frontend/SC.scala:66:7 + s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][14:0]}; // src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_31 table_0 ( // src/main/scala/xiangshan/frontend/SC.scala:71:21 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid), + .io_r_req_bits_setIdx + ({io_req_bits_pc[8:5], + io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist}), // src/main/scala/xiangshan/frontend/SC.scala:86:{12,31,40} + .io_r_resp_data_0 (_table_io_r_resp_data_0), + .io_r_resp_data_1 (_table_io_r_resp_data_1), + .io_r_resp_data_2 (_table_io_r_resp_data_2), + .io_r_resp_data_3 (_table_io_r_resp_data_3), + .io_w_req_valid (io_update_mask_0 | io_update_mask_1), // src/main/scala/xiangshan/frontend/SC.scala:130:36 + .io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:40 + .io_w_req_bits_data_0 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_data_1 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_data_2 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_data_3 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_waymask + ({per_br_update_way_mask_1_1, + per_br_update_way_mask_1_0, + per_br_update_way_mask_0_1, + per_br_update_way_mask_0_0}) // src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29 + ); + WrBypass_33 wrbypasses_0 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0), + .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:40 + .io_write_data_0 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_data_1 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_way_mask_0 + (~(io_update_pc[1]) & per_br_update_way_mask_0_0 | io_update_pc[1] + & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + .io_write_way_mask_1 + (~(io_update_pc[1]) & per_br_update_way_mask_0_1 | io_update_pc[1] + & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + .io_hit (_wrbypasses_0_io_hit), + .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits) + ); + WrBypass_33 wrbypasses_1 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1), + .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:40 + .io_write_data_0 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_data_1 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_way_mask_0 + (io_update_pc[1] & per_br_update_way_mask_0_0 | ~(io_update_pc[1]) + & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + .io_write_way_mask_1 + (io_update_pc[1] & per_br_update_way_mask_0_1 | ~(io_update_pc[1]) + & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + .io_hit (_wrbypasses_1_io_hit), + .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits) + ); + assign io_resp_ctrs_0_0 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0) + | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + assign io_resp_ctrs_0_1 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1) + | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + assign io_resp_ctrs_1_0 = + (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + assign io_resp_ctrs_1_1 = + (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 +endmodule + diff --git a/src/TageSC/SCTable_2.sv b/src/TageSC/SCTable_2.sv new file mode 100644 index 0000000..61ca86e --- /dev/null +++ b/src/TageSC/SCTable_2.sv @@ -0,0 +1,257 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SCTable_2( // src/main/scala/xiangshan/frontend/SC.scala:66:7 + input clock, + input reset, + input io_req_valid, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [7:0] io_req_bits_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_0_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_0_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_1_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_1_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [7:0] io_update_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_mask_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_mask_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [5:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [5:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_tagePreds_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_tagePreds_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_takens_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_takens_1 // src/main/scala/xiangshan/frontend/SC.scala:68:14 +); + + wire _wrbypasses_1_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_1_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_0_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_0_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _table_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + wire [5:0] _table_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + wire [5:0] _table_io_r_resp_data_2; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + wire [5:0] _table_io_r_resp_data_3; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + reg [38:0] s1_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 + wire per_br_update_way_mask_0_0 = + io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire per_br_update_way_mask_0_1 = + io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire per_br_update_way_mask_1_0 = + io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + wire per_br_update_way_mask_1_1 = + io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:86:31, :117:42 + wire ctrPos = + ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire [5:0] oldCtr = + (~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit) + & (ctrPos + ? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_1_valid + : ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos + ? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0) + : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0)) + : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0) + | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire taken = + ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire [5:0] per_br_update_wdata_packed_0_1 = + oldCtr == 6'h1F & taken + ? 6'h1F + : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 + wire ctrPos_1 = + io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + wire [5:0] oldCtr_1 = + (io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit) + & (ctrPos_1 + ? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_1_valid + : io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos_1 + ? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits) + : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits)) + : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0) + | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + wire taken_1 = + io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + wire [5:0] per_br_update_wdata_packed_1_1 = + oldCtr_1 == 6'h1F & taken_1 + ? 6'h1F + : oldCtr_1 == 6'h20 & ~taken_1 + ? 6'h20 + : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 + wire [5:0] _GEN = + (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_0_1) + | (io_update_pc[1] ? per_br_update_wdata_packed_1_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire [5:0] _GEN_0 = + (io_update_pc[1] ? per_br_update_wdata_packed_0_1 : 6'h0) + | (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_1_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + always @(posedge clock) begin + if (io_req_valid) // src/main/scala/xiangshan/frontend/SC.scala:68:14 + s1_pc <= io_req_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/SC.scala:66:7 + initial begin // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/SC.scala:66:7 + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/SC.scala:66:7 + end // src/main/scala/xiangshan/frontend/SC.scala:66:7 + s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][14:0]}; // src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_31 table_0 ( // src/main/scala/xiangshan/frontend/SC.scala:71:21 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid), + .io_r_req_bits_setIdx + (io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/SC.scala:86:{12,31} + .io_r_resp_data_0 (_table_io_r_resp_data_0), + .io_r_resp_data_1 (_table_io_r_resp_data_1), + .io_r_resp_data_2 (_table_io_r_resp_data_2), + .io_r_resp_data_3 (_table_io_r_resp_data_3), + .io_w_req_valid (io_update_mask_0 | io_update_mask_1), // src/main/scala/xiangshan/frontend/SC.scala:130:36 + .io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31 + .io_w_req_bits_data_0 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_data_1 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_data_2 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_data_3 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_waymask + ({per_br_update_way_mask_1_1, + per_br_update_way_mask_1_0, + per_br_update_way_mask_0_1, + per_br_update_way_mask_0_0}) // src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29 + ); + WrBypass_33 wrbypasses_0 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0), + .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31 + .io_write_data_0 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_data_1 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_way_mask_0 + (~(io_update_pc[1]) & per_br_update_way_mask_0_0 | io_update_pc[1] + & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + .io_write_way_mask_1 + (~(io_update_pc[1]) & per_br_update_way_mask_0_1 | io_update_pc[1] + & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + .io_hit (_wrbypasses_0_io_hit), + .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits) + ); + WrBypass_33 wrbypasses_1 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1), + .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31 + .io_write_data_0 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_data_1 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_way_mask_0 + (io_update_pc[1] & per_br_update_way_mask_0_0 | ~(io_update_pc[1]) + & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + .io_write_way_mask_1 + (io_update_pc[1] & per_br_update_way_mask_0_1 | ~(io_update_pc[1]) + & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + .io_hit (_wrbypasses_1_io_hit), + .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits) + ); + assign io_resp_ctrs_0_0 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0) + | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + assign io_resp_ctrs_0_1 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1) + | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + assign io_resp_ctrs_1_0 = + (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + assign io_resp_ctrs_1_1 = + (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 +endmodule + diff --git a/src/TageSC/SCTable_3.sv b/src/TageSC/SCTable_3.sv new file mode 100644 index 0000000..ed6b86a --- /dev/null +++ b/src/TageSC/SCTable_3.sv @@ -0,0 +1,257 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SCTable_3( // src/main/scala/xiangshan/frontend/SC.scala:66:7 + input clock, + input reset, + input io_req_valid, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [7:0] io_req_bits_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_0_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_0_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_1_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + output [5:0] io_resp_ctrs_1_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [7:0] io_update_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_mask_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_mask_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [5:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input [5:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_tagePreds_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_tagePreds_1, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_takens_0, // src/main/scala/xiangshan/frontend/SC.scala:68:14 + input io_update_takens_1 // src/main/scala/xiangshan/frontend/SC.scala:68:14 +); + + wire _wrbypasses_1_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_1_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_1_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_0_io_hit; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire _wrbypasses_0_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _wrbypasses_0_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/SC.scala:139:42 + wire [5:0] _table_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + wire [5:0] _table_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + wire [5:0] _table_io_r_resp_data_2; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + wire [5:0] _table_io_r_resp_data_3; // src/main/scala/xiangshan/frontend/SC.scala:71:21 + reg [38:0] s1_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 + wire per_br_update_way_mask_0_0 = + io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{69,78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire per_br_update_way_mask_0_1 = + io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:{69,78}, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire per_br_update_way_mask_1_0 = + io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & ~io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :120:{78,81}, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + wire per_br_update_way_mask_1_1 = + io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/xiangshan/frontend/SC.scala:117:42, :123:78, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:86:31, :117:42 + wire ctrPos = + ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire [5:0] oldCtr = + (~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit) + & (ctrPos + ? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_1_valid + : ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos + ? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0) + : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0)) + : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0) + | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire taken = + ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire [5:0] per_br_update_wdata_packed_0_1 = + oldCtr == 6'h1F & taken + ? 6'h1F + : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 + wire ctrPos_1 = + io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + wire [5:0] oldCtr_1 = + (io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit) + & (ctrPos_1 + ? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_1_valid + : io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos_1 + ? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits) + : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits)) + : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0) + | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :139:42, :149:41, :150:21, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + wire taken_1 = + io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92 + wire [5:0] per_br_update_wdata_packed_1_1 = + oldCtr_1 == 6'h1F & taken_1 + ? 6'h1F + : oldCtr_1 == 6'h20 & ~taken_1 + ? 6'h20 + : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:102:27, :103:30, :104:{8,21}, :105:{10,26,29}, :106:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:150:21 + wire [5:0] _GEN = + (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_0_1) + | (io_update_pc[1] ? per_br_update_wdata_packed_1_1 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + wire [5:0] _GEN_0 = + (io_update_pc[1] ? per_br_update_wdata_packed_0_1 : 6'h0) + | (io_update_pc[1] ? 6'h0 : per_br_update_wdata_packed_1_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:104:8, src/main/scala/xiangshan/frontend/SC.scala:117:42, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + always @(posedge clock) begin + if (io_req_valid) // src/main/scala/xiangshan/frontend/SC.scala:68:14 + s1_pc <= io_req_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:99:24 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/SC.scala:66:7 + initial begin // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/SC.scala:66:7 + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/SC.scala:66:7 + end // src/main/scala/xiangshan/frontend/SC.scala:66:7 + s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][14:0]}; // src/main/scala/xiangshan/frontend/SC.scala:66:7, :99:24 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/SC.scala:66:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_31 table_0 ( // src/main/scala/xiangshan/frontend/SC.scala:71:21 + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid), + .io_r_req_bits_setIdx + (io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/SC.scala:86:{12,31} + .io_r_resp_data_0 (_table_io_r_resp_data_0), + .io_r_resp_data_1 (_table_io_r_resp_data_1), + .io_r_resp_data_2 (_table_io_r_resp_data_2), + .io_r_resp_data_3 (_table_io_r_resp_data_3), + .io_w_req_valid (io_update_mask_0 | io_update_mask_1), // src/main/scala/xiangshan/frontend/SC.scala:130:36 + .io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31 + .io_w_req_bits_data_0 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_data_1 (per_br_update_wdata_packed_0_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_data_2 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_data_3 (per_br_update_wdata_packed_1_1), // src/main/scala/xiangshan/frontend/BPU.scala:104:8 + .io_w_req_bits_waymask + ({per_br_update_way_mask_1_1, + per_br_update_way_mask_1_0, + per_br_update_way_mask_0_1, + per_br_update_way_mask_0_0}) // src/main/scala/xiangshan/frontend/SC.scala:121:15, :124:15, :133:29 + ); + WrBypass_33 wrbypasses_0 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0), + .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31 + .io_write_data_0 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_data_1 (_GEN), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_way_mask_0 + (~(io_update_pc[1]) & per_br_update_way_mask_0_0 | io_update_pc[1] + & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + .io_write_way_mask_1 + (~(io_update_pc[1]) & per_br_update_way_mask_0_1 | io_update_pc[1] + & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + .io_hit (_wrbypasses_0_io_hit), + .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits) + ); + WrBypass_33 wrbypasses_1 ( // src/main/scala/xiangshan/frontend/SC.scala:139:42 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1), + .io_write_idx (update_idx), // src/main/scala/xiangshan/frontend/SC.scala:86:31 + .io_write_data_0 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_data_1 (_GEN_0), // src/main/scala/chisel3/util/Mux.scala:30:73 + .io_write_way_mask_0 + (io_update_pc[1] & per_br_update_way_mask_0_0 | ~(io_update_pc[1]) + & per_br_update_way_mask_1_0), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :121:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + .io_write_way_mask_1 + (io_update_pc[1] & per_br_update_way_mask_0_1 | ~(io_update_pc[1]) + & per_br_update_way_mask_1_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:117:42, :124:15, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92 + .io_hit (_wrbypasses_1_io_hit), + .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits) + ); + assign io_resp_ctrs_0_0 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0) + | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + assign io_resp_ctrs_0_1 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1) + | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + assign io_resp_ctrs_1_0 = + (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 + assign io_resp_ctrs_1_1 = + (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/SC.scala:66:7, :71:21, :99:24, :100:31, src/main/scala/xiangshan/frontend/Tage.scala:53:42 +endmodule + diff --git a/src/TageSC/SRAMTemplate_10.sv b/src/TageSC/SRAMTemplate_10.sv new file mode 100644 index 0000000..ced545b --- /dev/null +++ b/src/TageSC/SRAMTemplate_10.sv @@ -0,0 +1,277 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_10( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + input clock, + input reset, + output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [7:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_4, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_5, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_6, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_7, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_8, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_9, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_10, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_11, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_12, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_13, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_14, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_15, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [7:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_4, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_5, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_6, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_7, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_8, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_9, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_10, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_11, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_12, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_13, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_14, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_bits_data_15, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [15:0] io_w_req_bits_waymask, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input extra_reset // utility/src/main/scala/utility/SRAMTemplate.scala:102:44 +); + + wire wdata_15; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_14; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_13; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_12; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_11; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_10; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_9; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_8; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_7; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_6; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_5; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_4; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_3; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_2; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire wdata_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [7:0] array_MPORT_addr; // utility/src/main/scala/utility/SRAMTemplate.scala:125:19 + wire array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38 + wire array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 + wire [15:0] _array_RW0_rdata; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 + reg [7:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40 + assign array_MPORT_en = io_w_req_valid | _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52 + assign array_raw_rdata_en = io_r_req_valid & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52, :123:{38,41} + assign array_MPORT_addr = _resetState ? _resetSet : io_w_req_bits_setIdx; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19 + assign wdata_0 = ~_resetState & io_w_req_bits_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_1 = ~_resetState & io_w_req_bits_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_2 = ~_resetState & io_w_req_bits_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_3 = ~_resetState & io_w_req_bits_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_4 = ~_resetState & io_w_req_bits_data_4; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_5 = ~_resetState & io_w_req_bits_data_5; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_6 = ~_resetState & io_w_req_bits_data_6; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_7 = ~_resetState & io_w_req_bits_data_7; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_8 = ~_resetState & io_w_req_bits_data_8; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_9 = ~_resetState & io_w_req_bits_data_9; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_10 = ~_resetState & io_w_req_bits_data_10; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_11 = ~_resetState & io_w_req_bits_data_11; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_12 = ~_resetState & io_w_req_bits_data_12; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_13 = ~_resetState & io_w_req_bits_data_13; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_14 = ~_resetState & io_w_req_bits_data_14; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + assign wdata_15 = ~_resetState & io_w_req_bits_data_15; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:26 + reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 + reg rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_4; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_5; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_6; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_7; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_8; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_9; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_10; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_11; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_12; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_13; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_14; // utility/src/main/scala/utility/Hold.scala:24:82 + reg rdata_hold_data_15; // utility/src/main/scala/utility/Hold.scala:24:82 + always @(posedge clock or posedge reset) begin + if (reset) begin + _resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + _resetSet <= 8'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 + end + else begin + _resetState <= extra_reset | ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38}, :113:30, :114:21 + if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 + _resetSet <= 8'(_resetSet + 8'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24 + end + end // always @(posedge, posedge) + always @(posedge clock) begin + rdata_REG <= array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38, :153:59 + if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 + rdata_hold_data_0 <= _array_RW0_rdata[0]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_1 <= _array_RW0_rdata[1]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_2 <= _array_RW0_rdata[2]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_3 <= _array_RW0_rdata[3]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_4 <= _array_RW0_rdata[4]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_5 <= _array_RW0_rdata[5]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_6 <= _array_RW0_rdata[6]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_7 <= _array_RW0_rdata[7]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_8 <= _array_RW0_rdata[8]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_9 <= _array_RW0_rdata[9]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_10 <= _array_RW0_rdata[10]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_11 <= _array_RW0_rdata[11]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_12 <= _array_RW0_rdata[12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_13 <= _array_RW0_rdata[13]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_14 <= _array_RW0_rdata[14]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_15 <= _array_RW0_rdata[15]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:33]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + for (logic [5:0] i = 6'h0; i < 6'h22; i += 6'h1) begin + _RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + _resetState = _RANDOM[6'h0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + _resetSet = _RANDOM[6'h0][8:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + rdata_REG = _RANDOM[6'h21][10]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_0 = _RANDOM[6'h21][11]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_1 = _RANDOM[6'h21][12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_2 = _RANDOM[6'h21][13]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_3 = _RANDOM[6'h21][14]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_4 = _RANDOM[6'h21][15]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_5 = _RANDOM[6'h21][16]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_6 = _RANDOM[6'h21][17]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_7 = _RANDOM[6'h21][18]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_8 = _RANDOM[6'h21][19]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_9 = _RANDOM[6'h21][20]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_10 = _RANDOM[6'h21][21]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_11 = _RANDOM[6'h21][22]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_12 = _RANDOM[6'h21][23]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_13 = _RANDOM[6'h21][24]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_14 = _RANDOM[6'h21][25]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_15 = _RANDOM[6'h21][26]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + _resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + _resetSet = 8'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_4 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + .RW0_addr (array_MPORT_en ? array_MPORT_addr : io_r_req_bits_setIdx), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :125:19 + .RW0_en (array_raw_rdata_en | array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :123:38 + .RW0_clk (clock), + .RW0_wmode (array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 + .RW0_wdata + ({wdata_15, + wdata_14, + wdata_13, + wdata_12, + wdata_11, + wdata_10, + wdata_9, + wdata_8, + wdata_7, + wdata_6, + wdata_5, + wdata_4, + wdata_3, + wdata_2, + wdata_1, + wdata_0}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :126:26 + .RW0_rdata (_array_RW0_rdata), + .RW0_wmask (_resetState ? 16'hFFFF : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37} + ); + assign io_r_req_ready = ~_resetState & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :122:52, :123:41, :157:{21,33} + assign io_r_resp_data_0 = rdata_REG ? _array_RW0_rdata[0] : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_1 = rdata_REG ? _array_RW0_rdata[1] : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_2 = rdata_REG ? _array_RW0_rdata[2] : rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_3 = rdata_REG ? _array_RW0_rdata[3] : rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_4 = rdata_REG ? _array_RW0_rdata[4] : rdata_hold_data_4; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_5 = rdata_REG ? _array_RW0_rdata[5] : rdata_hold_data_5; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_6 = rdata_REG ? _array_RW0_rdata[6] : rdata_hold_data_6; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_7 = rdata_REG ? _array_RW0_rdata[7] : rdata_hold_data_7; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_8 = rdata_REG ? _array_RW0_rdata[8] : rdata_hold_data_8; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_9 = rdata_REG ? _array_RW0_rdata[9] : rdata_hold_data_9; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_10 = rdata_REG ? _array_RW0_rdata[10] : rdata_hold_data_10; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_11 = rdata_REG ? _array_RW0_rdata[11] : rdata_hold_data_11; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_12 = rdata_REG ? _array_RW0_rdata[12] : rdata_hold_data_12; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_13 = rdata_REG ? _array_RW0_rdata[13] : rdata_hold_data_13; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_14 = rdata_REG ? _array_RW0_rdata[14] : rdata_hold_data_14; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 + assign io_r_resp_data_15 = rdata_REG ? _array_RW0_rdata[15] : rdata_hold_data_15; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :105:26, :153:59 +endmodule + diff --git a/src/TageSC/SRAMTemplate_11.sv b/src/TageSC/SRAMTemplate_11.sv new file mode 100644 index 0000000..93e82bb --- /dev/null +++ b/src/TageSC/SRAMTemplate_11.sv @@ -0,0 +1,174 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_11( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + input clock, + input reset, + output io_r_req_ready, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [8:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_0_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [7:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [2:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output io_r_resp_data_1_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [7:0] io_r_resp_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [2:0] io_r_resp_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [8:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [7:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [2:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [7:0] io_w_req_bits_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [2:0] io_w_req_bits_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 +); + + wire [2:0] _wdata_T_1_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [7:0] _wdata_T_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_1_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :126:26 + wire [2:0] _wdata_T_0_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [7:0] _wdata_T_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire _wdata_T_0_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :126:26 + wire [8:0] array_MPORT_addr; // utility/src/main/scala/utility/SRAMTemplate.scala:125:19 + wire array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38 + wire array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 + wire [23:0] _array_RW0_rdata; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 + reg [8:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40 + assign array_MPORT_en = io_w_req_valid | _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52 + assign array_raw_rdata_en = io_r_req_valid & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52, :123:{38,41} + assign array_MPORT_addr = _resetState ? _resetSet : io_w_req_bits_setIdx; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19 + assign _wdata_T_0_valid = ~_resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :109:30, :126:26 + assign _wdata_T_0_tag = _resetState ? 8'h0 : io_w_req_bits_data_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_0_ctr = _resetState ? 3'h0 : io_w_req_bits_data_0_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :126:26 + assign _wdata_T_1_valid = ~_resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :109:30, :126:26 + assign _wdata_T_1_tag = _resetState ? 8'h0 : io_w_req_bits_data_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign _wdata_T_1_ctr = _resetState ? 3'h0 : io_w_req_bits_data_1_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :126:26 + reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 + reg [11:0] rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [11:0] rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82 + wire [11:0] _rdata_WIRE = rdata_REG ? _array_RW0_rdata[11:0] : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :153:59 + wire [11:0] _rdata_WIRE_1 = rdata_REG ? _array_RW0_rdata[23:12] : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :153:59 + always @(posedge clock or posedge reset) begin + if (reset) begin + _resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:98:14, :109:30 + _resetSet <= 9'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 + end + else begin + _resetState <= ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38} + if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 + _resetSet <= 9'(_resetSet + 9'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24 + end + end // always @(posedge, posedge) + always @(posedge clock) begin + rdata_REG <= array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38, :153:59 + if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 + rdata_hold_data_0 <= _array_RW0_rdata[11:0]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + rdata_hold_data_1 <= _array_RW0_rdata[23:12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:5]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin + _RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + _resetState = _RANDOM[3'h0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + _resetSet = _RANDOM[3'h0][9:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + rdata_REG = _RANDOM[3'h4][31]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59 + rdata_hold_data_0 = _RANDOM[3'h5][11:0]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + rdata_hold_data_1 = _RANDOM[3'h5][23:12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + _resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:98:14, :109:30 + _resetSet = 9'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_5 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + .RW0_addr (array_MPORT_en ? array_MPORT_addr : io_r_req_bits_setIdx), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :125:19 + .RW0_en (array_raw_rdata_en | array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :123:38 + .RW0_clk (clock), + .RW0_wmode (array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:122:52 + .RW0_wdata + ({_wdata_T_1_valid, + _wdata_T_1_tag, + _wdata_T_1_ctr, + _wdata_T_0_valid, + _wdata_T_0_tag, + _wdata_T_0_ctr}), // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :98:14, :105:26, :126:26 + .RW0_rdata (_array_RW0_rdata), + .RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37} + ); + assign io_r_req_ready = ~_resetState & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :122:52, :123:41, :157:{21,33} + assign io_r_resp_data_0_valid = _rdata_WIRE[11]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 + assign io_r_resp_data_0_tag = _rdata_WIRE[10:3]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 + assign io_r_resp_data_0_ctr = _rdata_WIRE[2:0]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 + assign io_r_resp_data_1_valid = _rdata_WIRE_1[11]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 + assign io_r_resp_data_1_tag = _rdata_WIRE_1[10:3]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 + assign io_r_resp_data_1_ctr = _rdata_WIRE_1[2:0]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45 +endmodule + diff --git a/src/TageSC/SRAMTemplate_30.sv b/src/TageSC/SRAMTemplate_30.sv new file mode 100644 index 0000000..bdbb0de --- /dev/null +++ b/src/TageSC/SRAMTemplate_30.sv @@ -0,0 +1,209 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_30( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + input clock, + input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [8:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_4, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_5, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_6, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [1:0] io_r_resp_data_7, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [8:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_4, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_5, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_6, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [1:0] io_w_req_bits_data_7, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [7:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 +); + + wire [15:0] _array_R0_data; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + reg [1:0] bypass_wdata_REG_0; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + reg [1:0] bypass_wdata_REG_1; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + reg [1:0] bypass_wdata_REG_2; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + reg [1:0] bypass_wdata_REG_3; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + reg [1:0] bypass_wdata_REG_4; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + reg [1:0] bypass_wdata_REG_5; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + reg [1:0] bypass_wdata_REG_6; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + reg [1:0] bypass_wdata_REG_7; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + reg bypass_mask_need_check; // utility/src/main/scala/utility/SRAMTemplate.scala:135:29 + reg [8:0] bypass_mask_waddr_reg; // utility/src/main/scala/utility/SRAMTemplate.scala:136:28 + reg [8:0] bypass_mask_raddr_reg; // utility/src/main/scala/utility/SRAMTemplate.scala:137:28 + reg [7:0] bypass_mask_bypass_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:139:76 + wire [7:0] bypass_mask = + {8{bypass_mask_need_check & bypass_mask_waddr_reg == bypass_mask_raddr_reg}} + & bypass_mask_bypass_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:135:29, :136:28, :137:28, :139:{22,39,52,67,76} + wire [1:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_REG_0 : _array_R0_data[1:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 + wire [1:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_REG_1 : _array_R0_data[3:2]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 + wire [1:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_REG_2 : _array_R0_data[5:4]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 + wire [1:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_REG_3 : _array_R0_data[7:6]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 + wire [1:0] mem_rdata_4 = bypass_mask[4] ? bypass_wdata_REG_4 : _array_R0_data[9:8]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 + wire [1:0] mem_rdata_5 = bypass_mask[5] ? bypass_wdata_REG_5 : _array_R0_data[11:10]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 + wire [1:0] mem_rdata_6 = bypass_mask[6] ? bypass_wdata_REG_6 : _array_R0_data[13:12]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 + wire [1:0] mem_rdata_7 = bypass_mask[7] ? bypass_wdata_REG_7 : _array_R0_data[15:14]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 + reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 + reg [1:0] rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] rdata_hold_data_4; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] rdata_hold_data_5; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] rdata_hold_data_6; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [1:0] rdata_hold_data_7; // utility/src/main/scala/utility/Hold.scala:24:82 + always @(posedge clock) begin + bypass_wdata_REG_0 <= io_w_req_bits_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + bypass_wdata_REG_1 <= io_w_req_bits_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + bypass_wdata_REG_2 <= io_w_req_bits_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + bypass_wdata_REG_3 <= io_w_req_bits_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + bypass_wdata_REG_4 <= io_w_req_bits_data_4; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + bypass_wdata_REG_5 <= io_w_req_bits_data_5; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + bypass_wdata_REG_6 <= io_w_req_bits_data_6; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + bypass_wdata_REG_7 <= io_w_req_bits_data_7; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + bypass_mask_need_check <= io_r_req_valid & io_w_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:135:{29,34} + bypass_mask_waddr_reg <= io_w_req_bits_setIdx; // utility/src/main/scala/utility/SRAMTemplate.scala:136:28 + bypass_mask_raddr_reg <= io_r_req_bits_setIdx; // utility/src/main/scala/utility/SRAMTemplate.scala:137:28 + bypass_mask_bypass_REG <= io_w_req_bits_waymask; // utility/src/main/scala/utility/SRAMTemplate.scala:139:76 + rdata_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 + if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 + rdata_hold_data_0 <= mem_rdata_0; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 + rdata_hold_data_1 <= mem_rdata_1; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 + rdata_hold_data_2 <= mem_rdata_2; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 + rdata_hold_data_3 <= mem_rdata_3; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 + rdata_hold_data_4 <= mem_rdata_4; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 + rdata_hold_data_5 <= mem_rdata_5; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 + rdata_hold_data_6 <= mem_rdata_6; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 + rdata_hold_data_7 <= mem_rdata_7; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + bypass_wdata_REG_0 = _RANDOM[1'h0][1:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 + bypass_wdata_REG_1 = _RANDOM[1'h0][3:2]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 + bypass_wdata_REG_2 = _RANDOM[1'h0][5:4]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 + bypass_wdata_REG_3 = _RANDOM[1'h0][7:6]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 + bypass_wdata_REG_4 = _RANDOM[1'h0][9:8]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 + bypass_wdata_REG_5 = _RANDOM[1'h0][11:10]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 + bypass_wdata_REG_6 = _RANDOM[1'h0][13:12]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 + bypass_wdata_REG_7 = _RANDOM[1'h0][15:14]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 + bypass_mask_need_check = _RANDOM[1'h0][16]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :135:29, :142:54 + bypass_mask_waddr_reg = _RANDOM[1'h0][25:17]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :136:28, :142:54 + bypass_mask_raddr_reg = {_RANDOM[1'h0][31:26], _RANDOM[1'h1][2:0]}; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28, :142:54 + bypass_mask_bypass_REG = _RANDOM[1'h1][10:3]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28, :139:76 + rdata_REG = _RANDOM[1'h1][11]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28, :153:59 + rdata_hold_data_0 = _RANDOM[1'h1][13:12]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 + rdata_hold_data_1 = _RANDOM[1'h1][15:14]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 + rdata_hold_data_2 = _RANDOM[1'h1][17:16]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 + rdata_hold_data_3 = _RANDOM[1'h1][19:18]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 + rdata_hold_data_4 = _RANDOM[1'h1][21:20]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 + rdata_hold_data_5 = _RANDOM[1'h1][23:22]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 + rdata_hold_data_6 = _RANDOM[1'h1][25:24]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 + rdata_hold_data_7 = _RANDOM[1'h1][27:26]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_6 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + .R0_addr (io_r_req_bits_setIdx), + .R0_en (io_r_req_valid), + .R0_clk (clock), + .R0_data (_array_R0_data), + .W0_addr (io_w_req_bits_setIdx), + .W0_en (io_w_req_valid), + .W0_clk (clock), + .W0_data + ({io_w_req_bits_data_7, + io_w_req_bits_data_6, + io_w_req_bits_data_5, + io_w_req_bits_data_4, + io_w_req_bits_data_3, + io_w_req_bits_data_2, + io_w_req_bits_data_1, + io_w_req_bits_data_0}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + .W0_mask (io_w_req_bits_waymask) + ); + assign io_r_resp_data_0 = rdata_REG ? mem_rdata_0 : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 + assign io_r_resp_data_1 = rdata_REG ? mem_rdata_1 : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 + assign io_r_resp_data_2 = rdata_REG ? mem_rdata_2 : rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 + assign io_r_resp_data_3 = rdata_REG ? mem_rdata_3 : rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 + assign io_r_resp_data_4 = rdata_REG ? mem_rdata_4 : rdata_hold_data_4; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 + assign io_r_resp_data_5 = rdata_REG ? mem_rdata_5 : rdata_hold_data_5; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 + assign io_r_resp_data_6 = rdata_REG ? mem_rdata_6 : rdata_hold_data_6; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 + assign io_r_resp_data_7 = rdata_REG ? mem_rdata_7 : rdata_hold_data_7; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 +endmodule + diff --git a/src/TageSC/SRAMTemplate_31.sv b/src/TageSC/SRAMTemplate_31.sv new file mode 100644 index 0000000..f975a8d --- /dev/null +++ b/src/TageSC/SRAMTemplate_31.sv @@ -0,0 +1,189 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_31( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + input clock, + input reset, + input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [7:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [5:0] io_r_resp_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [5:0] io_r_resp_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [5:0] io_r_resp_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + output [5:0] io_r_resp_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [7:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [5:0] io_w_req_bits_data_0, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [5:0] io_w_req_bits_data_1, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [5:0] io_w_req_bits_data_2, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [5:0] io_w_req_bits_data_3, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 + input [3:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14 +); + + wire [5:0] wdata_3; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [5:0] wdata_2; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [5:0] wdata_1; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [5:0] wdata_0; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26 + wire [23:0] _array_R0_data; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 + reg [7:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40 + assign wdata_0 = _resetState ? 6'h0 : io_w_req_bits_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign wdata_1 = _resetState ? 6'h0 : io_w_req_bits_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign wdata_2 = _resetState ? 6'h0 : io_w_req_bits_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + assign wdata_3 = _resetState ? 6'h0 : io_w_req_bits_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51} + reg [5:0] bypass_wdata_REG_0; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + reg [5:0] bypass_wdata_REG_1; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + reg [5:0] bypass_wdata_REG_2; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + reg [5:0] bypass_wdata_REG_3; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + reg bypass_mask_need_check; // utility/src/main/scala/utility/SRAMTemplate.scala:135:29 + reg [7:0] bypass_mask_waddr_reg; // utility/src/main/scala/utility/SRAMTemplate.scala:136:28 + reg [7:0] bypass_mask_raddr_reg; // utility/src/main/scala/utility/SRAMTemplate.scala:137:28 + reg [3:0] bypass_mask_bypass_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:139:76 + wire [3:0] bypass_mask = + {4{bypass_mask_need_check & bypass_mask_waddr_reg == bypass_mask_raddr_reg}} + & bypass_mask_bypass_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:135:29, :136:28, :137:28, :139:{22,39,52,67,76} + wire [5:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_REG_0 : _array_R0_data[5:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 + wire [5:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_REG_1 : _array_R0_data[11:6]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 + wire [5:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_REG_2 : _array_R0_data[17:12]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 + wire [5:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_REG_3 : _array_R0_data[23:18]; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :139:67, :142:54, :147:30, :148:30 + reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 + reg [5:0] rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [5:0] rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [5:0] rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82 + reg [5:0] rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82 + always @(posedge clock or posedge reset) begin + if (reset) begin + _resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + _resetSet <= 8'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 + end + else begin + _resetState <= ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38} + if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30 + _resetSet <= 8'(_resetSet + 8'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24 + end + end // always @(posedge, posedge) + always @(posedge clock) begin + bypass_wdata_REG_0 <= io_w_req_bits_data_0; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + bypass_wdata_REG_1 <= io_w_req_bits_data_1; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + bypass_wdata_REG_2 <= io_w_req_bits_data_2; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + bypass_wdata_REG_3 <= io_w_req_bits_data_3; // utility/src/main/scala/utility/SRAMTemplate.scala:142:54 + bypass_mask_need_check <= io_r_req_valid & io_w_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:135:{29,34} + bypass_mask_waddr_reg <= io_w_req_bits_setIdx; // utility/src/main/scala/utility/SRAMTemplate.scala:136:28 + bypass_mask_raddr_reg <= io_r_req_bits_setIdx; // utility/src/main/scala/utility/SRAMTemplate.scala:137:28 + bypass_mask_bypass_REG <= io_w_req_bits_waymask; // utility/src/main/scala/utility/SRAMTemplate.scala:139:76 + rdata_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 + if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59 + rdata_hold_data_0 <= mem_rdata_0; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 + rdata_hold_data_1 <= mem_rdata_1; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 + rdata_hold_data_2 <= mem_rdata_2; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 + rdata_hold_data_3 <= mem_rdata_3; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:148:30 + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + _resetState = _RANDOM[2'h0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + _resetSet = _RANDOM[2'h0][8:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + bypass_wdata_REG_0 = _RANDOM[2'h0][14:9]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :142:54 + bypass_wdata_REG_1 = _RANDOM[2'h0][20:15]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :142:54 + bypass_wdata_REG_2 = _RANDOM[2'h0][26:21]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :142:54 + bypass_wdata_REG_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][0]}; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30, :142:54 + bypass_mask_need_check = _RANDOM[2'h1][1]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :135:29, :142:54 + bypass_mask_waddr_reg = _RANDOM[2'h1][9:2]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :136:28, :142:54 + bypass_mask_raddr_reg = _RANDOM[2'h1][17:10]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :137:28, :142:54 + bypass_mask_bypass_REG = _RANDOM[2'h1][21:18]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :139:76, :142:54 + rdata_REG = _RANDOM[2'h1][22]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54, :153:59 + rdata_hold_data_0 = _RANDOM[2'h1][28:23]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 + rdata_hold_data_1 = {_RANDOM[2'h1][31:29], _RANDOM[2'h2][2:0]}; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :142:54 + rdata_hold_data_2 = _RANDOM[2'h2][8:3]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + rdata_hold_data_3 = _RANDOM[2'h2][14:9]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + _resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30 + _resetSet = 8'h0; // src/main/scala/chisel3/util/Counter.scala:61:40 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_7 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + .R0_addr (io_r_req_bits_setIdx), + .R0_en (io_r_req_valid), + .R0_clk (clock), + .R0_data (_array_R0_data), + .W0_addr (_resetState ? _resetSet : io_w_req_bits_setIdx), // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19 + .W0_en (io_w_req_valid | _resetState), // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52 + .W0_clk (clock), + .W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :126:26 + .W0_mask (_resetState ? 4'hF : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37} + ); + assign io_r_resp_data_0 = rdata_REG ? mem_rdata_0 : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 + assign io_r_resp_data_1 = rdata_REG ? mem_rdata_1 : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 + assign io_r_resp_data_2 = rdata_REG ? mem_rdata_2 : rdata_hold_data_2; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 + assign io_r_resp_data_3 = rdata_REG ? mem_rdata_3 : rdata_hold_data_3; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :148:30, :153:59 +endmodule + diff --git a/src/TageSC/TageBTable.sv b/src/TageSC/TageBTable.sv new file mode 100644 index 0000000..cfe0cef --- /dev/null +++ b/src/TageSC/TageBTable.sv @@ -0,0 +1,187 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module TageBTable( // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + input clock, + input reset, + output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 + input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 + input [38:0] io_req_bits, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 + output [1:0] io_s1_cnt_0, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 + output [1:0] io_s1_cnt_1, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 + input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 + input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 + input [1:0] io_update_cnt_0, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 + input [1:0] io_update_cnt_1, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 + input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:138:14 + input io_update_takens_1 // src/main/scala/xiangshan/frontend/Tage.scala:138:14 +); + + wire [1:0] newCtrs_1; // src/main/scala/xiangshan/frontend/Tage.scala:213:8 + wire [1:0] newCtrs_0; // src/main/scala/xiangshan/frontend/Tage.scala:213:8 + wire _wrbypass_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:192:24 + wire _wrbypass_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:192:24 + wire [1:0] _wrbypass_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:192:24 + wire _wrbypass_io_hit_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:192:24 + wire [1:0] _wrbypass_io_hit_data_1_bits; // src/main/scala/xiangshan/frontend/Tage.scala:192:24 + wire [1:0] _bt_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:154:18 + wire [1:0] _bt_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:154:18 + reg doing_reset; // src/main/scala/xiangshan/frontend/Tage.scala:166:28 + reg [10:0] resetRow; // src/main/scala/xiangshan/frontend/Tage.scala:167:25 + reg [10:0] s1_idx; // src/main/scala/xiangshan/frontend/Tage.scala:181:25 + wire _wrbypass_io_wen_T = io_update_mask_0 | io_update_mask_1; // src/main/scala/xiangshan/frontend/Tage.scala:193:45 + wire [1:0] oldCtrs_0 = + _wrbypass_io_hit + & (io_update_pc[1] ? _wrbypass_io_hit_data_1_valid : _wrbypass_io_hit_data_0_valid) + ? (io_update_pc[1] ? _wrbypass_io_hit_data_1_bits : _wrbypass_io_hit_data_0_bits) + : io_update_pc[1] ? io_update_cnt_1 : io_update_cnt_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :192:24, :205:{10,27} + wire [1:0] oldCtrs_1 = + _wrbypass_io_hit + & (io_update_pc[1] ? _wrbypass_io_hit_data_0_valid : _wrbypass_io_hit_data_1_valid) + ? (io_update_pc[1] ? _wrbypass_io_hit_data_0_bits : _wrbypass_io_hit_data_1_bits) + : io_update_pc[1] ? io_update_cnt_0 : io_update_cnt_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :192:24, :205:{10,27} + wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :213:21 + assign newCtrs_0 = + (&oldCtrs_0) & _GEN + ? 2'h3 + : oldCtrs_0 == 2'h0 & ~_GEN + ? 2'h0 + : _GEN ? 2'(oldCtrs_0 + 2'h1) : 2'(oldCtrs_0 - 2'h1); // src/main/scala/xiangshan/frontend/Tage.scala:205:10, :211:27, :212:30, :213:{8,21}, :214:{10,26,29}, :215:{12,24,35}, :234:36 + wire _GEN_0 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :213:21 + assign newCtrs_1 = + (&oldCtrs_1) & _GEN_0 + ? 2'h3 + : oldCtrs_1 == 2'h0 & ~_GEN_0 + ? 2'h0 + : _GEN_0 ? 2'(oldCtrs_1 + 2'h1) : 2'(oldCtrs_1 - 2'h1); // src/main/scala/xiangshan/frontend/Tage.scala:205:10, :211:27, :212:30, :213:{8,21}, :214:{10,26,29}, :215:{12,24,35}, :234:36 + always @(posedge clock or posedge reset) begin + if (reset) begin + doing_reset <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28 + resetRow <= 11'h0; // src/main/scala/xiangshan/frontend/Tage.scala:167:25 + end + else begin + doing_reset <= resetRow != 11'h7FF & doing_reset; // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :169:{18,36,50} + resetRow <= 11'(resetRow + {10'h0, doing_reset}); // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :168:24 + end + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_req_valid) // src/main/scala/xiangshan/frontend/Tage.scala:138:14 + s1_idx <= io_req_bits[11:1]; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65, src/main/scala/xiangshan/frontend/Tage.scala:181:25 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + initial begin // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28 + resetRow = _RANDOM[/*Zero width*/ 1'b0][11:1]; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :167:25 + s1_idx = _RANDOM[/*Zero width*/ 1'b0][22:12]; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :181:25 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + doing_reset = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28 + resetRow = 11'h0; // src/main/scala/xiangshan/frontend/Tage.scala:167:25 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:137:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FoldedSRAMTemplate_20 bt ( // src/main/scala/xiangshan/frontend/Tage.scala:154:18 + .clock (clock), + .io_r_req_valid (io_req_valid), + .io_r_req_bits_setIdx (io_req_bits[11:1]), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 + .io_r_resp_data_0 (_bt_io_r_resp_data_0), + .io_r_resp_data_1 (_bt_io_r_resp_data_1), + .io_w_req_valid (_wrbypass_io_wen_T | doing_reset), // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :193:45, :231:41 + .io_w_req_bits_setIdx (doing_reset ? resetRow : io_update_pc[11:1]), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65, src/main/scala/xiangshan/frontend/Tage.scala:166:28, :167:25, :233:17 + .io_w_req_bits_data_0 (doing_reset ? 2'h2 : newCtrs_0), // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :213:8, :232:{15,36} + .io_w_req_bits_data_1 (doing_reset ? 2'h2 : newCtrs_1), // src/main/scala/xiangshan/frontend/Tage.scala:166:28, :213:8, :232:{15,36} + .io_w_req_bits_waymask + (doing_reset + ? 2'h3 + : {io_update_mask_0 & io_update_pc[1] | io_update_mask_1 & ~(io_update_pc[1]), + io_update_mask_0 & ~(io_update_pc[1]) | io_update_mask_1 & io_update_pc[1]}) // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :166:28, :211:27, :226:{26,55}, :227:15, :228:6, :234:18 + ); + WrBypass_32 wrbypass ( // src/main/scala/xiangshan/frontend/Tage.scala:192:24 + .clock (clock), + .reset (reset), + .io_wen (_wrbypass_io_wen_T), // src/main/scala/xiangshan/frontend/Tage.scala:193:45 + .io_write_idx (io_update_pc[11:1]), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:399:65 + .io_write_data_0 (io_update_pc[1] ? newCtrs_1 : newCtrs_0), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :198:32, :213:8 + .io_write_data_1 (io_update_pc[1] ? newCtrs_0 : newCtrs_1), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :198:32, :213:8 + .io_write_way_mask_0 (io_update_mask_0), + .io_write_way_mask_1 (io_update_mask_1), + .io_hit (_wrbypass_io_hit), + .io_hit_data_0_valid (_wrbypass_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypass_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypass_io_hit_data_1_bits) + ); + assign io_req_ready = ~doing_reset; // src/main/scala/xiangshan/frontend/Tage.scala:137:7, :166:28, :172:19 + assign io_s1_cnt_0 = + (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_0) | (s1_idx[0] ? _bt_io_r_resp_data_1 : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :137:7, :154:18, :181:25, :234:36 + assign io_s1_cnt_1 = + (s1_idx[0] ? _bt_io_r_resp_data_0 : 2'h0) | (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :137:7, :154:18, :181:25, :234:36 +endmodule + diff --git a/src/TageSC/TageTable.sv b/src/TageSC/TageTable.sv new file mode 100644 index 0000000..d547c11 --- /dev/null +++ b/src/TageSC/TageTable.sv @@ -0,0 +1,762 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module TageTable( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + input clock, + input reset, + output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [7:0] io_req_bits_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [6:0] io_req_bits_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_0_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output [2:0] io_resps_0_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_0_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_0_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_1_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output [2:0] io_resps_1_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_1_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_1_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [7:0] io_update_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [6:0] io_update_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_takens_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_alloc_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_alloc_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [2:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [2:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_uMask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_uMask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_us_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_us_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_reset_u_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_reset_u_1 // src/main/scala/xiangshan/frontend/Tage.scala:245:14 +); + + wire per_bank_not_silent_update_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + reg powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:399:34 + wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 + wire _bank_wrbypasses_3_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_3_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _table_banks_3_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_3_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_3_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_2_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_2_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_2_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_1_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_1_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_1_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_0_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_0_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_0_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _us_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + wire _us_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + wire _us_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + wire [7:0] _GEN = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 + wire s0_bank_req_1h_0 = _GEN[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire s0_bank_req_1h_1 = _GEN[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire s0_bank_req_1h_2 = _GEN[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19 + wire [8:0] _table_banks_3_io_r_req_bits_setIdx_T = {io_req_bits_pc[11:9], _GEN[7:2]}; // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + reg [37:0] s1_unhashed_idx; // src/main/scala/xiangshan/frontend/Tage.scala:330:34 + reg [7:0] s1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:332:25 + reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_req_1h_3; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + reg s1_bank_has_write_on_this_req_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + reg s1_bank_has_write_on_this_req_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + wire [2:0] _resp_selected_WIRE_1 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 + wire [2:0] _resp_selected_WIRE_5 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 + wire _unconf_selected_WIRE = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 + wire _unconf_selected_WIRE_1 = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 + wire _hit_selected_WIRE = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag + & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag + & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag + & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag + & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} + wire _hit_selected_WIRE_1 = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag + & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag + & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag + & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag + & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} + assign _resp_invalid_by_write_WIRE = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2 + | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48 + wire [7:0] _GEN_0 = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 + wire [7:0] per_bank_update_wdata_3_1_tag = + _GEN_0 ^ {io_update_folded_hist_hist_7_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :290:29, :291:{38,52} + wire update_req_bank_1h_0 = _GEN_0[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire update_req_bank_1h_1 = _GEN_0[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire update_req_bank_1h_2 = _GEN_0[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire [8:0] update_idx_in_bank = {io_update_pc[11:9], _GEN_0[7:2]}; // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + wire [1:0] per_bank_update_way_mask_0 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_0_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_0_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire [1:0] per_bank_update_way_mask_1 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_1_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_1_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire [1:0] per_bank_update_way_mask_2 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_2_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_2_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire [1:0] per_bank_update_way_mask_3 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_3_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_3_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire _s1_bank_has_write_on_this_req_WIRE_0 = + (|per_bank_update_way_mask_0) & update_req_bank_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + wire _s1_bank_has_write_on_this_req_WIRE_1 = + (|per_bank_update_way_mask_1) & update_req_bank_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + wire _s1_bank_has_write_on_this_req_WIRE_2 = + (|per_bank_update_way_mask_2) & update_req_bank_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + wire _s1_bank_has_write_on_this_req_WIRE_3 = + (|per_bank_update_way_mask_3) & (&(_GEN_0[1:0])); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49} + wire [2:0] _wrbypass_io_WIRE_2 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid = + (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire _GEN_1 = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 + wire [2:0] _GEN_2 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 + wire _GEN_3 = (|_GEN_2) | _GEN_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :97:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14 + wire _GEN_4 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + wire [2:0] per_bank_update_wdata_0_0_ctr = + _GEN_4 + ? (_GEN_1 ? 3'h4 : 3'h3) + : wrbypass_data_valid + ? ((&_wrbypass_io_WIRE_2) & _GEN_1 + ? 3'h7 + : _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN_1 + ? 3'h0 + : _GEN_1 + ? 3'(_wrbypass_io_WIRE_2 + 3'h1) + : 3'(_wrbypass_io_WIRE_2 - 3'h1)) + : (&_GEN_2) & _GEN_1 + ? 3'h7 + : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_0_0 = + (wrbypass_data_valid + ? ~((&_wrbypass_io_WIRE_2) & _GEN_1 | _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN_1) + : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_11 = + (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_1 = + (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire _GEN_5 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 + wire [2:0] _GEN_6 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 + wire _GEN_7 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + wire [2:0] per_bank_update_wdata_0_1_ctr = + _GEN_7 + ? (_GEN_5 ? 3'h4 : 3'h3) + : wrbypass_data_valid_1 + ? ((&_wrbypass_io_WIRE_11) & _GEN_5 + ? 3'h7 + : _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 + ? 3'(_wrbypass_io_WIRE_11 + 3'h1) + : 3'(_wrbypass_io_WIRE_11 - 3'h1)) + : (&_GEN_6) & _GEN_5 + ? 3'h7 + : _GEN_6 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_0_1 = + (wrbypass_data_valid_1 + ? ~((&_wrbypass_io_WIRE_11) & _GEN_5 | _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_5) + : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_20 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_2 = + (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_1_0_ctr = + _GEN_4 + ? (_GEN_1 ? 3'h4 : 3'h3) + : wrbypass_data_valid_2 + ? ((&_wrbypass_io_WIRE_20) & _GEN_1 + ? 3'h7 + : _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN_1 + ? 3'h0 + : _GEN_1 + ? 3'(_wrbypass_io_WIRE_20 + 3'h1) + : 3'(_wrbypass_io_WIRE_20 - 3'h1)) + : (&_GEN_2) & _GEN_1 + ? 3'h7 + : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_1_0 = + (wrbypass_data_valid_2 + ? ~((&_wrbypass_io_WIRE_20) & _GEN_1 | _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN_1) + : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_29 = + (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_3 = + (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_1_1_ctr = + _GEN_7 + ? (_GEN_5 ? 3'h4 : 3'h3) + : wrbypass_data_valid_3 + ? ((&_wrbypass_io_WIRE_29) & _GEN_5 + ? 3'h7 + : _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 + ? 3'(_wrbypass_io_WIRE_29 + 3'h1) + : 3'(_wrbypass_io_WIRE_29 - 3'h1)) + : (&_GEN_6) & _GEN_5 + ? 3'h7 + : _GEN_6 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_1_1 = + (wrbypass_data_valid_3 + ? ~((&_wrbypass_io_WIRE_29) & _GEN_5 | _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_5) + : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_38 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_4 = + (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_2_0_ctr = + _GEN_4 + ? (_GEN_1 ? 3'h4 : 3'h3) + : wrbypass_data_valid_4 + ? ((&_wrbypass_io_WIRE_38) & _GEN_1 + ? 3'h7 + : _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN_1 + ? 3'h0 + : _GEN_1 + ? 3'(_wrbypass_io_WIRE_38 + 3'h1) + : 3'(_wrbypass_io_WIRE_38 - 3'h1)) + : (&_GEN_2) & _GEN_1 + ? 3'h7 + : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_2_0 = + (wrbypass_data_valid_4 + ? ~((&_wrbypass_io_WIRE_38) & _GEN_1 | _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN_1) + : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_47 = + (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_5 = + (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_2_1_ctr = + _GEN_7 + ? (_GEN_5 ? 3'h4 : 3'h3) + : wrbypass_data_valid_5 + ? ((&_wrbypass_io_WIRE_47) & _GEN_5 + ? 3'h7 + : _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 + ? 3'(_wrbypass_io_WIRE_47 + 3'h1) + : 3'(_wrbypass_io_WIRE_47 - 3'h1)) + : (&_GEN_6) & _GEN_5 + ? 3'h7 + : _GEN_6 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_2_1 = + (wrbypass_data_valid_5 + ? ~((&_wrbypass_io_WIRE_47) & _GEN_5 | _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_5) + : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_56 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_6 = + (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_3_0_ctr = + _GEN_4 + ? (_GEN_1 ? 3'h4 : 3'h3) + : wrbypass_data_valid_6 + ? ((&_wrbypass_io_WIRE_56) & _GEN_1 + ? 3'h7 + : _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN_1 + ? 3'h0 + : _GEN_1 + ? 3'(_wrbypass_io_WIRE_56 + 3'h1) + : 3'(_wrbypass_io_WIRE_56 - 3'h1)) + : (&_GEN_2) & _GEN_1 + ? 3'h7 + : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_3_0 = + (wrbypass_data_valid_6 + ? ~((&_wrbypass_io_WIRE_56) & _GEN_1 | _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN_1) + : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_65 = + (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_7 = + (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_3_1_ctr = + _GEN_7 + ? (_GEN_5 ? 3'h4 : 3'h3) + : wrbypass_data_valid_7 + ? ((&_wrbypass_io_WIRE_65) & _GEN_5 + ? 3'h7 + : _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 + ? 3'(_wrbypass_io_WIRE_65 + 3'h1) + : 3'(_wrbypass_io_WIRE_65 - 3'h1)) + : (&_GEN_6) & _GEN_5 + ? 3'h7 + : _GEN_6 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_3_1 = + (wrbypass_data_valid_7 + ? ~((&_wrbypass_io_WIRE_65) & _GEN_5 | _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_5) + : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + always @(posedge clock) begin + if (_s1_bank_req_1h_T) begin // src/main/scala/chisel3/util/Decoupled.scala:53:35 + s1_unhashed_idx <= io_req_bits_pc[38:1]; // src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34 + s1_tag <= _GEN ^ {io_req_bits_folded_hist_hist_7_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :290:29, :291:{38,52}, :332:25 + s1_bank_req_1h_0 <= s0_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 + s1_bank_req_1h_1 <= s0_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 + s1_bank_req_1h_2 <= s0_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 + s1_bank_req_1h_3 <= &(_GEN[1:0]); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33 + end + if (io_req_valid) begin // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + end + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) + powerOnResetState <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 + else + powerOnResetState <= + ~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready + & _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready + & _table_banks_3_io_r_req_ready) & powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23 + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + initial begin // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + end // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][5:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34 + s1_tag = _RANDOM[2'h1][24:17]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25 + s1_bank_req_1h_0 = _RANDOM[2'h3][0]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_req_1h_1 = _RANDOM[2'h3][1]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_req_1h_2 = _RANDOM[2'h3][2]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_req_1h_3 = _RANDOM[2'h3][3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][4]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][5]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][6]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][7]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + powerOnResetState = _RANDOM[2'h3][8]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34 + `endif // RANDOMIZE_REG_INIT + if (reset) // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + powerOnResetState = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FoldedSRAMTemplate us ( // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + .clock (clock), + .reset (reset), + .io_r_req_ready (_us_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T), // src/main/scala/chisel3/util/Decoupled.scala:53:35 + .io_r_req_bits_setIdx ({io_req_bits_pc[11:9], _GEN}), // src/main/scala/xiangshan/frontend/Tage.scala:290:{29,38} + .io_r_resp_data_0 (_us_io_r_resp_data_0), + .io_r_resp_data_1 (_us_io_r_resp_data_1), + .io_w_req_valid (io_update_uMask_0 | io_update_uMask_1), // src/main/scala/xiangshan/frontend/Tage.scala:426:41 + .io_w_req_bits_setIdx ({io_update_pc[11:9], _GEN_0}), // src/main/scala/xiangshan/frontend/Tage.scala:290:{29,38} + .io_w_req_bits_data_0 + (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48 + .io_w_req_bits_data_1 + (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43 + .io_w_req_bits_waymask + ({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1, + ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7 + .extra_reset (io_update_reset_u_0 | io_update_reset_u_1) // src/main/scala/xiangshan/frontend/Tage.scala:311:51 + ); + FoldedSRAMTemplate_1 table_banks_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_0_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 + .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_0) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + FoldedSRAMTemplate_1 table_banks_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_1_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 + .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_1) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + FoldedSRAMTemplate_1 table_banks_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_2_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 + .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_2) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + FoldedSRAMTemplate_1 table_banks_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_3_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & (&(_GEN[1:0]))), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52 + .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_3) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + WrBypass bank_wrbypasses_0_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_0_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_0_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_0_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_1_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_1_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_2_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_2_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & (&(_GEN_0[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 + .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_3_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & (&(_GEN_0[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 + .io_write_idx (update_idx_in_bank), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:38 + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_3_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits) + ); + assign io_req_ready = ~powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19 + assign io_resps_0_valid = + ~(s1_unhashed_idx[0]) & _hit_selected_WIRE | s1_unhashed_idx[0] + & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_0_bits_ctr = + (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_1) + | (s1_unhashed_idx[0] ? _resp_selected_WIRE_5 : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_0_bits_u = + ~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0] + & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34 + assign io_resps_0_bits_unconf = + ~(s1_unhashed_idx[0]) & _unconf_selected_WIRE | s1_unhashed_idx[0] + & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_1_valid = + s1_unhashed_idx[0] & _hit_selected_WIRE | ~(s1_unhashed_idx[0]) + & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 + assign io_resps_1_bits_ctr = + (s1_unhashed_idx[0] ? _resp_selected_WIRE_1 : 3'h0) + | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_5); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_1_bits_u = + s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0]) + & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34 + assign io_resps_1_bits_unconf = + s1_unhashed_idx[0] & _unconf_selected_WIRE | ~(s1_unhashed_idx[0]) + & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 +endmodule + diff --git a/src/TageSC/TageTable_1.sv b/src/TageSC/TageTable_1.sv new file mode 100644 index 0000000..335fb19 --- /dev/null +++ b/src/TageSC/TageTable_1.sv @@ -0,0 +1,765 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module TageTable_1( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + input clock, + input reset, + output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [6:0] io_req_bits_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [7:0] io_req_bits_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [10:0] io_req_bits_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_0_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output [2:0] io_resps_0_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_0_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_0_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_1_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output [2:0] io_resps_1_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_1_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_1_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [6:0] io_update_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [7:0] io_update_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [10:0] io_update_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_takens_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_alloc_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_alloc_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [2:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [2:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_uMask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_uMask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_us_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_us_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_reset_u_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_reset_u_1 // src/main/scala/xiangshan/frontend/Tage.scala:245:14 +); + + wire per_bank_not_silent_update_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + reg powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:399:34 + wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 + wire _bank_wrbypasses_3_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_3_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _table_banks_3_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_3_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_3_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_2_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_2_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_2_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_1_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_1_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_1_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_0_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_0_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_0_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _us_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + wire _us_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + wire _us_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 + wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19 + reg [37:0] s1_unhashed_idx; // src/main/scala/xiangshan/frontend/Tage.scala:330:34 + reg [7:0] s1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:332:25 + reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_req_1h_3; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + reg s1_bank_has_write_on_this_req_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + reg s1_bank_has_write_on_this_req_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + wire [2:0] _resp_selected_WIRE_1 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 + wire [2:0] _resp_selected_WIRE_5 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 + wire _unconf_selected_WIRE = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 + wire _unconf_selected_WIRE_1 = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 + wire _hit_selected_WIRE = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag + & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag + & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag + & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag + & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} + wire _hit_selected_WIRE_1 = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag + & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag + & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag + & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag + & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} + assign _resp_invalid_by_write_WIRE = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2 + | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48 + wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 + wire [7:0] per_bank_update_wdata_3_1_tag = + io_update_pc[8:1] ^ io_update_folded_hist_hist_4_folded_hist + ^ {io_update_folded_hist_hist_15_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43 + wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire [1:0] per_bank_update_way_mask_0 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_0_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_0_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire [1:0] per_bank_update_way_mask_1 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_1_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_1_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire [1:0] per_bank_update_way_mask_2 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_2_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_2_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire [1:0] per_bank_update_way_mask_3 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_3_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_3_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire _s1_bank_has_write_on_this_req_WIRE_0 = + (|per_bank_update_way_mask_0) & update_req_bank_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + wire _s1_bank_has_write_on_this_req_WIRE_1 = + (|per_bank_update_way_mask_1) & update_req_bank_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + wire _s1_bank_has_write_on_this_req_WIRE_2 = + (|per_bank_update_way_mask_2) & update_req_bank_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + wire _s1_bank_has_write_on_this_req_WIRE_3 = + (|per_bank_update_way_mask_3) & (&(update_idx[1:0])); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49} + wire [2:0] _wrbypass_io_WIRE_2 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid = + (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 + wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 + wire _GEN_1 = (|_GEN_0) | _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :97:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14 + wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + wire [2:0] per_bank_update_wdata_0_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid + ? ((&_wrbypass_io_WIRE_2) & _GEN + ? 3'h7 + : _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN + ? 3'(_wrbypass_io_WIRE_2 + 3'h1) + : 3'(_wrbypass_io_WIRE_2 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_0_0 = + (wrbypass_data_valid + ? ~((&_wrbypass_io_WIRE_2) & _GEN | _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_11 = + (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_1 = + (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 + wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 + wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + wire [2:0] per_bank_update_wdata_0_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_1 + ? ((&_wrbypass_io_WIRE_11) & _GEN_3 + ? 3'h7 + : _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_WIRE_11 + 3'h1) + : 3'(_wrbypass_io_WIRE_11 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_0_1 = + (wrbypass_data_valid_1 + ? ~((&_wrbypass_io_WIRE_11) & _GEN_3 | _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_20 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_2 = + (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_1_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_2 + ? ((&_wrbypass_io_WIRE_20) & _GEN + ? 3'h7 + : _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN + ? 3'(_wrbypass_io_WIRE_20 + 3'h1) + : 3'(_wrbypass_io_WIRE_20 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_1_0 = + (wrbypass_data_valid_2 + ? ~((&_wrbypass_io_WIRE_20) & _GEN | _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_29 = + (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_3 = + (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_1_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_3 + ? ((&_wrbypass_io_WIRE_29) & _GEN_3 + ? 3'h7 + : _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_WIRE_29 + 3'h1) + : 3'(_wrbypass_io_WIRE_29 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_1_1 = + (wrbypass_data_valid_3 + ? ~((&_wrbypass_io_WIRE_29) & _GEN_3 | _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_38 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_4 = + (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_2_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_4 + ? ((&_wrbypass_io_WIRE_38) & _GEN + ? 3'h7 + : _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN + ? 3'(_wrbypass_io_WIRE_38 + 3'h1) + : 3'(_wrbypass_io_WIRE_38 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_2_0 = + (wrbypass_data_valid_4 + ? ~((&_wrbypass_io_WIRE_38) & _GEN | _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_47 = + (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_5 = + (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_2_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_5 + ? ((&_wrbypass_io_WIRE_47) & _GEN_3 + ? 3'h7 + : _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_WIRE_47 + 3'h1) + : 3'(_wrbypass_io_WIRE_47 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_2_1 = + (wrbypass_data_valid_5 + ? ~((&_wrbypass_io_WIRE_47) & _GEN_3 | _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_56 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_6 = + (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_3_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_6 + ? ((&_wrbypass_io_WIRE_56) & _GEN + ? 3'h7 + : _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN + ? 3'(_wrbypass_io_WIRE_56 + 3'h1) + : 3'(_wrbypass_io_WIRE_56 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_3_0 = + (wrbypass_data_valid_6 + ? ~((&_wrbypass_io_WIRE_56) & _GEN | _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_65 = + (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_7 = + (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_3_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_7 + ? ((&_wrbypass_io_WIRE_65) & _GEN_3 + ? 3'h7 + : _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_WIRE_65 + 3'h1) + : 3'(_wrbypass_io_WIRE_65 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_3_1 = + (wrbypass_data_valid_7 + ? ~((&_wrbypass_io_WIRE_65) & _GEN_3 | _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + always @(posedge clock) begin + if (_s1_bank_req_1h_T) begin // src/main/scala/chisel3/util/Decoupled.scala:53:35 + s1_unhashed_idx <= io_req_bits_pc[38:1]; // src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34 + s1_tag <= + io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_4_folded_hist + ^ {io_req_bits_folded_hist_hist_15_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43, :332:25 + s1_bank_req_1h_0 <= s0_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 + s1_bank_req_1h_1 <= s0_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 + s1_bank_req_1h_2 <= s0_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 + s1_bank_req_1h_3 <= &(s0_idx[1:0]); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33 + end + if (io_req_valid) begin // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + end + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) + powerOnResetState <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 + else + powerOnResetState <= + ~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready + & _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready + & _table_banks_3_io_r_req_ready) & powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23 + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + initial begin // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + end // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][5:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34 + s1_tag = _RANDOM[2'h1][24:17]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25 + s1_bank_req_1h_0 = _RANDOM[2'h3][0]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_req_1h_1 = _RANDOM[2'h3][1]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_req_1h_2 = _RANDOM[2'h3][2]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_req_1h_3 = _RANDOM[2'h3][3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][4]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][5]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][6]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][7]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + powerOnResetState = _RANDOM[2'h3][8]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34 + `endif // RANDOMIZE_REG_INIT + if (reset) // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + powerOnResetState = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FoldedSRAMTemplate us ( // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + .clock (clock), + .reset (reset), + .io_r_req_ready (_us_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T), // src/main/scala/chisel3/util/Decoupled.scala:53:35 + .io_r_req_bits_setIdx (s0_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29 + .io_r_resp_data_0 (_us_io_r_resp_data_0), + .io_r_resp_data_1 (_us_io_r_resp_data_1), + .io_w_req_valid (io_update_uMask_0 | io_update_uMask_1), // src/main/scala/xiangshan/frontend/Tage.scala:426:41 + .io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29 + .io_w_req_bits_data_0 + (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48 + .io_w_req_bits_data_1 + (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43 + .io_w_req_bits_waymask + ({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1, + ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7 + .extra_reset (io_update_reset_u_0 | io_update_reset_u_1) // src/main/scala/xiangshan/frontend/Tage.scala:311:51 + ); + FoldedSRAMTemplate_1 table_banks_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_0_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 + .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_0) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + FoldedSRAMTemplate_1 table_banks_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_1_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 + .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_1) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + FoldedSRAMTemplate_1 table_banks_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_2_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 + .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_2) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + FoldedSRAMTemplate_1 table_banks_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_3_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52 + .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_3) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + WrBypass bank_wrbypasses_0_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_0_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_0_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_0_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_1_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_1_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_2_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_2_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_3_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_3_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits) + ); + assign io_req_ready = ~powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19 + assign io_resps_0_valid = + ~(s1_unhashed_idx[0]) & _hit_selected_WIRE | s1_unhashed_idx[0] + & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_0_bits_ctr = + (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_1) + | (s1_unhashed_idx[0] ? _resp_selected_WIRE_5 : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_0_bits_u = + ~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0] + & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34 + assign io_resps_0_bits_unconf = + ~(s1_unhashed_idx[0]) & _unconf_selected_WIRE | s1_unhashed_idx[0] + & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_1_valid = + s1_unhashed_idx[0] & _hit_selected_WIRE | ~(s1_unhashed_idx[0]) + & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 + assign io_resps_1_bits_ctr = + (s1_unhashed_idx[0] ? _resp_selected_WIRE_1 : 3'h0) + | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_5); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_1_bits_u = + s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0]) + & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34 + assign io_resps_1_bits_unconf = + s1_unhashed_idx[0] & _unconf_selected_WIRE | ~(s1_unhashed_idx[0]) + & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 +endmodule + diff --git a/src/TageSC/TageTable_2.sv b/src/TageSC/TageTable_2.sv new file mode 100644 index 0000000..7e43a07 --- /dev/null +++ b/src/TageSC/TageTable_2.sv @@ -0,0 +1,765 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module TageTable_2( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + input clock, + input reset, + output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [10:0] io_req_bits_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [6:0] io_req_bits_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [7:0] io_req_bits_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_0_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output [2:0] io_resps_0_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_0_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_0_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_1_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output [2:0] io_resps_1_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_1_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_1_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [10:0] io_update_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [6:0] io_update_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [7:0] io_update_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_takens_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_alloc_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_alloc_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [2:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [2:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_uMask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_uMask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_us_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_us_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_reset_u_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_reset_u_1 // src/main/scala/xiangshan/frontend/Tage.scala:245:14 +); + + wire per_bank_not_silent_update_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + reg powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:399:34 + wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 + wire _bank_wrbypasses_3_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_3_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _table_banks_3_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_3_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_3_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_2_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_2_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_2_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_1_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_1_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_1_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_0_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_0_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_0_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _us_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + wire _us_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + wire _us_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 + wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19 + reg [37:0] s1_unhashed_idx; // src/main/scala/xiangshan/frontend/Tage.scala:330:34 + reg [7:0] s1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:332:25 + reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_req_1h_3; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + reg s1_bank_has_write_on_this_req_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + reg s1_bank_has_write_on_this_req_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + wire [2:0] _resp_selected_WIRE_1 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 + wire [2:0] _resp_selected_WIRE_5 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 + wire _unconf_selected_WIRE = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 + wire _unconf_selected_WIRE_1 = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 + wire _hit_selected_WIRE = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag + & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag + & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag + & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag + & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} + wire _hit_selected_WIRE_1 = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag + & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag + & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag + & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag + & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} + assign _resp_invalid_by_write_WIRE = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2 + | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48 + wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 + wire [7:0] per_bank_update_wdata_3_1_tag = + io_update_pc[8:1] ^ io_update_folded_hist_hist_3_folded_hist + ^ {io_update_folded_hist_hist_9_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43 + wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire [1:0] per_bank_update_way_mask_0 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_0_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_0_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire [1:0] per_bank_update_way_mask_1 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_1_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_1_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire [1:0] per_bank_update_way_mask_2 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_2_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_2_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire [1:0] per_bank_update_way_mask_3 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_3_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_3_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire _s1_bank_has_write_on_this_req_WIRE_0 = + (|per_bank_update_way_mask_0) & update_req_bank_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + wire _s1_bank_has_write_on_this_req_WIRE_1 = + (|per_bank_update_way_mask_1) & update_req_bank_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + wire _s1_bank_has_write_on_this_req_WIRE_2 = + (|per_bank_update_way_mask_2) & update_req_bank_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + wire _s1_bank_has_write_on_this_req_WIRE_3 = + (|per_bank_update_way_mask_3) & (&(update_idx[1:0])); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49} + wire [2:0] _wrbypass_io_WIRE_2 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid = + (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 + wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 + wire _GEN_1 = (|_GEN_0) | _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :97:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14 + wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + wire [2:0] per_bank_update_wdata_0_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid + ? ((&_wrbypass_io_WIRE_2) & _GEN + ? 3'h7 + : _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN + ? 3'(_wrbypass_io_WIRE_2 + 3'h1) + : 3'(_wrbypass_io_WIRE_2 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_0_0 = + (wrbypass_data_valid + ? ~((&_wrbypass_io_WIRE_2) & _GEN | _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_11 = + (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_1 = + (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 + wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 + wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + wire [2:0] per_bank_update_wdata_0_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_1 + ? ((&_wrbypass_io_WIRE_11) & _GEN_3 + ? 3'h7 + : _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_WIRE_11 + 3'h1) + : 3'(_wrbypass_io_WIRE_11 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_0_1 = + (wrbypass_data_valid_1 + ? ~((&_wrbypass_io_WIRE_11) & _GEN_3 | _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_20 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_2 = + (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_1_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_2 + ? ((&_wrbypass_io_WIRE_20) & _GEN + ? 3'h7 + : _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN + ? 3'(_wrbypass_io_WIRE_20 + 3'h1) + : 3'(_wrbypass_io_WIRE_20 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_1_0 = + (wrbypass_data_valid_2 + ? ~((&_wrbypass_io_WIRE_20) & _GEN | _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_29 = + (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_3 = + (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_1_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_3 + ? ((&_wrbypass_io_WIRE_29) & _GEN_3 + ? 3'h7 + : _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_WIRE_29 + 3'h1) + : 3'(_wrbypass_io_WIRE_29 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_1_1 = + (wrbypass_data_valid_3 + ? ~((&_wrbypass_io_WIRE_29) & _GEN_3 | _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_38 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_4 = + (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_2_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_4 + ? ((&_wrbypass_io_WIRE_38) & _GEN + ? 3'h7 + : _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN + ? 3'(_wrbypass_io_WIRE_38 + 3'h1) + : 3'(_wrbypass_io_WIRE_38 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_2_0 = + (wrbypass_data_valid_4 + ? ~((&_wrbypass_io_WIRE_38) & _GEN | _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_47 = + (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_5 = + (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_2_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_5 + ? ((&_wrbypass_io_WIRE_47) & _GEN_3 + ? 3'h7 + : _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_WIRE_47 + 3'h1) + : 3'(_wrbypass_io_WIRE_47 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_2_1 = + (wrbypass_data_valid_5 + ? ~((&_wrbypass_io_WIRE_47) & _GEN_3 | _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_56 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_6 = + (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_3_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_6 + ? ((&_wrbypass_io_WIRE_56) & _GEN + ? 3'h7 + : _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN + ? 3'(_wrbypass_io_WIRE_56 + 3'h1) + : 3'(_wrbypass_io_WIRE_56 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_3_0 = + (wrbypass_data_valid_6 + ? ~((&_wrbypass_io_WIRE_56) & _GEN | _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_65 = + (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_7 = + (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_3_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_7 + ? ((&_wrbypass_io_WIRE_65) & _GEN_3 + ? 3'h7 + : _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_WIRE_65 + 3'h1) + : 3'(_wrbypass_io_WIRE_65 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_3_1 = + (wrbypass_data_valid_7 + ? ~((&_wrbypass_io_WIRE_65) & _GEN_3 | _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + always @(posedge clock) begin + if (_s1_bank_req_1h_T) begin // src/main/scala/chisel3/util/Decoupled.scala:53:35 + s1_unhashed_idx <= io_req_bits_pc[38:1]; // src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34 + s1_tag <= + io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_3_folded_hist + ^ {io_req_bits_folded_hist_hist_9_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43, :332:25 + s1_bank_req_1h_0 <= s0_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 + s1_bank_req_1h_1 <= s0_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 + s1_bank_req_1h_2 <= s0_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 + s1_bank_req_1h_3 <= &(s0_idx[1:0]); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33 + end + if (io_req_valid) begin // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + end + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) + powerOnResetState <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 + else + powerOnResetState <= + ~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready + & _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready + & _table_banks_3_io_r_req_ready) & powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23 + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + initial begin // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + end // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][5:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34 + s1_tag = _RANDOM[2'h1][24:17]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25 + s1_bank_req_1h_0 = _RANDOM[2'h3][0]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_req_1h_1 = _RANDOM[2'h3][1]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_req_1h_2 = _RANDOM[2'h3][2]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_req_1h_3 = _RANDOM[2'h3][3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][4]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][5]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][6]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][7]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + powerOnResetState = _RANDOM[2'h3][8]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34 + `endif // RANDOMIZE_REG_INIT + if (reset) // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + powerOnResetState = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FoldedSRAMTemplate us ( // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + .clock (clock), + .reset (reset), + .io_r_req_ready (_us_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T), // src/main/scala/chisel3/util/Decoupled.scala:53:35 + .io_r_req_bits_setIdx (s0_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29 + .io_r_resp_data_0 (_us_io_r_resp_data_0), + .io_r_resp_data_1 (_us_io_r_resp_data_1), + .io_w_req_valid (io_update_uMask_0 | io_update_uMask_1), // src/main/scala/xiangshan/frontend/Tage.scala:426:41 + .io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29 + .io_w_req_bits_data_0 + (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48 + .io_w_req_bits_data_1 + (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43 + .io_w_req_bits_waymask + ({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1, + ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7 + .extra_reset (io_update_reset_u_0 | io_update_reset_u_1) // src/main/scala/xiangshan/frontend/Tage.scala:311:51 + ); + FoldedSRAMTemplate_1 table_banks_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_0_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 + .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_0) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + FoldedSRAMTemplate_1 table_banks_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_1_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 + .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_1) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + FoldedSRAMTemplate_1 table_banks_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_2_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 + .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_2) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + FoldedSRAMTemplate_1 table_banks_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_3_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52 + .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_3) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + WrBypass bank_wrbypasses_0_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_0_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_0_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_0_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_1_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_1_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_2_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_2_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_3_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_3_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits) + ); + assign io_req_ready = ~powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19 + assign io_resps_0_valid = + ~(s1_unhashed_idx[0]) & _hit_selected_WIRE | s1_unhashed_idx[0] + & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_0_bits_ctr = + (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_1) + | (s1_unhashed_idx[0] ? _resp_selected_WIRE_5 : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_0_bits_u = + ~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0] + & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34 + assign io_resps_0_bits_unconf = + ~(s1_unhashed_idx[0]) & _unconf_selected_WIRE | s1_unhashed_idx[0] + & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_1_valid = + s1_unhashed_idx[0] & _hit_selected_WIRE | ~(s1_unhashed_idx[0]) + & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 + assign io_resps_1_bits_ctr = + (s1_unhashed_idx[0] ? _resp_selected_WIRE_1 : 3'h0) + | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_5); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_1_bits_u = + s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0]) + & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34 + assign io_resps_1_bits_unconf = + s1_unhashed_idx[0] & _unconf_selected_WIRE | ~(s1_unhashed_idx[0]) + & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 +endmodule + diff --git a/src/TageSC/TageTable_3.sv b/src/TageSC/TageTable_3.sv new file mode 100644 index 0000000..f4f795f --- /dev/null +++ b/src/TageSC/TageTable_3.sv @@ -0,0 +1,765 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module TageTable_3( // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + input clock, + input reset, + output io_req_ready, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_req_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [38:0] io_req_bits_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [10:0] io_req_bits_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [7:0] io_req_bits_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [6:0] io_req_bits_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_0_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output [2:0] io_resps_0_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_0_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_0_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_1_valid, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output [2:0] io_resps_1_bits_ctr, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_1_bits_u, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + output io_resps_1_bits_unconf, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [38:0] io_update_pc, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [10:0] io_update_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [7:0] io_update_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [6:0] io_update_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_mask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_mask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_takens_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_takens_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_alloc_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_alloc_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [2:0] io_update_oldCtrs_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input [2:0] io_update_oldCtrs_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_uMask_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_uMask_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_us_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_us_1, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_reset_u_0, // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + input io_update_reset_u_1 // src/main/scala/xiangshan/frontend/Tage.scala:245:14 +); + + wire per_bank_not_silent_update_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + wire per_bank_not_silent_update_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:458:81 + reg powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:399:34 + wire _resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73 + wire _bank_wrbypasses_3_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_3_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_3_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_3_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_2_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_1_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_1_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_1_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_0_io_hit; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _bank_wrbypasses_0_0_io_hit_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + wire _table_banks_3_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_3_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_3_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_3_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_3_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_2_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_2_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_2_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_2_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_2_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_1_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_1_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_1_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_1_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_1_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_0_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_0_io_r_resp_data_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_0_io_r_resp_data_0_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _table_banks_0_io_r_resp_data_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [7:0] _table_banks_0_io_r_resp_data_1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + wire _us_io_r_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + wire _us_io_r_resp_data_0; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + wire _us_io_r_resp_data_1; // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 + wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:399:34, :407:19 + reg [37:0] s1_unhashed_idx; // src/main/scala/xiangshan/frontend/Tage.scala:330:34 + reg [7:0] s1_tag; // src/main/scala/xiangshan/frontend/Tage.scala:332:25 + reg s1_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_req_1h_3; // src/main/scala/xiangshan/frontend/Tage.scala:334:33 + reg s1_bank_has_write_on_this_req_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + reg s1_bank_has_write_on_this_req_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + reg s1_bank_has_write_on_this_req_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + reg s1_bank_has_write_on_this_req_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48 + wire [2:0] _resp_selected_WIRE_1 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 + wire [2:0] _resp_selected_WIRE_5 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :315:11, :334:33 + wire _unconf_selected_WIRE = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 + wire _unconf_selected_WIRE_1 = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :240:7, :315:11, :334:33, :449:14 + wire _hit_selected_WIRE = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag + & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag + & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag + & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag + & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} + wire _hit_selected_WIRE_1 = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag + & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag + & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag + & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag + & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:315:11, :332:25, :334:33, :341:{57,82} + assign _resp_invalid_by_write_WIRE = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2 + | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:334:33, :335:48 + wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:290:29, :305:43 + wire [7:0] per_bank_update_wdata_3_1_tag = + io_update_pc[8:1] ^ io_update_folded_hist_hist_8_folded_hist + ^ {io_update_folded_hist_hist_5_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43 + wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :272:{66,86}, :290:{29,38} + wire [1:0] per_bank_update_way_mask_0 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_0_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_0_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire [1:0] per_bank_update_way_mask_1 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_1_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_1_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire [1:0] per_bank_update_way_mask_2 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_2_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_2_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire [1:0] per_bank_update_way_mask_3 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_3_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_3_0}; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :382:{51,60}, :383:{39,44}, :384:11, :458:81 + wire _s1_bank_has_write_on_this_req_WIRE_0 = + (|per_bank_update_way_mask_0) & update_req_bank_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + wire _s1_bank_has_write_on_this_req_WIRE_1 = + (|per_bank_update_way_mask_1) & update_req_bank_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + wire _s1_bank_has_write_on_this_req_WIRE_2 = + (|per_bank_update_way_mask_2) & update_req_bank_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :384:11, :391:{45,49} + wire _s1_bank_has_write_on_this_req_WIRE_3 = + (|per_bank_update_way_mask_3) & (&(update_idx[1:0])); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :384:11, :391:{45,49} + wire [2:0] _wrbypass_io_WIRE_2 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid = + (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 + wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 + wire _GEN_1 = (|_GEN_0) | _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :97:10, src/main/scala/xiangshan/frontend/Tage.scala:449:14 + wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + wire [2:0] per_bank_update_wdata_0_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid + ? ((&_wrbypass_io_WIRE_2) & _GEN + ? 3'h7 + : _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN + ? 3'(_wrbypass_io_WIRE_2 + 3'h1) + : 3'(_wrbypass_io_WIRE_2 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_0_0 = + (wrbypass_data_valid + ? ~((&_wrbypass_io_WIRE_2) & _GEN | _wrbypass_io_WIRE_2 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_11 = + (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_1 = + (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :449:14 + wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43 + wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :448:12 + wire [2:0] per_bank_update_wdata_0_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_1 + ? ((&_wrbypass_io_WIRE_11) & _GEN_3 + ? 3'h7 + : _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_WIRE_11 + 3'h1) + : 3'(_wrbypass_io_WIRE_11 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_0_1 = + (wrbypass_data_valid_1 + ? ~((&_wrbypass_io_WIRE_11) & _GEN_3 | _wrbypass_io_WIRE_11 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_20 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_2 = + (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_1_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_2 + ? ((&_wrbypass_io_WIRE_20) & _GEN + ? 3'h7 + : _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN + ? 3'(_wrbypass_io_WIRE_20 + 3'h1) + : 3'(_wrbypass_io_WIRE_20 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_1_0 = + (wrbypass_data_valid_2 + ? ~((&_wrbypass_io_WIRE_20) & _GEN | _wrbypass_io_WIRE_20 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_29 = + (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_3 = + (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_1_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_3 + ? ((&_wrbypass_io_WIRE_29) & _GEN_3 + ? 3'h7 + : _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_WIRE_29 + 3'h1) + : 3'(_wrbypass_io_WIRE_29 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_1_1 = + (wrbypass_data_valid_3 + ? ~((&_wrbypass_io_WIRE_29) & _GEN_3 | _wrbypass_io_WIRE_29 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_38 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_4 = + (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_2_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_4 + ? ((&_wrbypass_io_WIRE_38) & _GEN + ? 3'h7 + : _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN + ? 3'(_wrbypass_io_WIRE_38 + 3'h1) + : 3'(_wrbypass_io_WIRE_38 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_2_0 = + (wrbypass_data_valid_4 + ? ~((&_wrbypass_io_WIRE_38) & _GEN | _wrbypass_io_WIRE_38 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_47 = + (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_5 = + (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_2_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_5 + ? ((&_wrbypass_io_WIRE_47) & _GEN_3 + ? 3'h7 + : _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_WIRE_47 + 3'h1) + : 3'(_wrbypass_io_WIRE_47 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_2_1 = + (wrbypass_data_valid_5 + ? ~((&_wrbypass_io_WIRE_47) & _GEN_3 | _wrbypass_io_WIRE_47 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_56 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_6 = + (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_3_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_6 + ? ((&_wrbypass_io_WIRE_56) & _GEN + ? 3'h7 + : _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN + ? 3'(_wrbypass_io_WIRE_56 + 3'h1) + : 3'(_wrbypass_io_WIRE_56 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_3_0 = + (wrbypass_data_valid_6 + ? ~((&_wrbypass_io_WIRE_56) & _GEN | _wrbypass_io_WIRE_56 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + wire [2:0] _wrbypass_io_WIRE_65 = + (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :434:11 + wire wrbypass_data_valid_7 = + (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit_data_0_valid); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :56:92, :305:43, :434:11, :446:46 + wire [2:0] per_bank_update_wdata_3_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_7 + ? ((&_wrbypass_io_WIRE_65) & _GEN_3 + ? 3'h7 + : _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_WIRE_65 + 3'h1) + : 3'(_wrbypass_io_WIRE_65 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :95:30, :96:{8,21}, :97:{10,26,29}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :446:46, :448:12, :449:14, :450:14 + assign per_bank_not_silent_update_3_1 = + (wrbypass_data_valid_7 + ? ~((&_wrbypass_io_WIRE_65) & _GEN_3 | _wrbypass_io_WIRE_65 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :97:29, src/main/scala/xiangshan/frontend/Tage.scala:240:7, :430:{9,14,23,31,35}, :446:46, :448:12, :449:14, :456:12, :457:11, :458:{11,81} + always @(posedge clock) begin + if (_s1_bank_req_1h_T) begin // src/main/scala/chisel3/util/Decoupled.scala:53:35 + s1_unhashed_idx <= io_req_bits_pc[38:1]; // src/main/scala/xiangshan/frontend/Tage.scala:305:43, :330:34 + s1_tag <= + io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_8_folded_hist + ^ {io_req_bits_folded_hist_hist_5_folded_hist, 1'h0}; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :291:{29,38,52}, :305:43, :332:25 + s1_bank_req_1h_0 <= s0_bank_req_1h_0; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 + s1_bank_req_1h_1 <= s0_bank_req_1h_1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 + s1_bank_req_1h_2 <= s0_bank_req_1h_2; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :334:33 + s1_bank_req_1h_3 <= &(s0_idx[1:0]); // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :334:33 + end + if (io_req_valid) begin // src/main/scala/xiangshan/frontend/Tage.scala:245:14 + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; // src/main/scala/xiangshan/frontend/Tage.scala:335:48, :391:49 + end + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) + powerOnResetState <= 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 + else + powerOnResetState <= + ~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready + & _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready + & _table_banks_3_io_r_req_ready) & powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:310:18, :315:11, :399:34, :400:{26,79}, :402:23 + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + initial begin // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + end // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][5:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34 + s1_tag = _RANDOM[2'h1][24:17]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :330:34, :332:25 + s1_bank_req_1h_0 = _RANDOM[2'h3][0]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_req_1h_1 = _RANDOM[2'h3][1]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_req_1h_2 = _RANDOM[2'h3][2]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_req_1h_3 = _RANDOM[2'h3][3]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33 + s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][4]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][5]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][6]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][7]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :335:48 + powerOnResetState = _RANDOM[2'h3][8]; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :334:33, :399:34 + `endif // RANDOMIZE_REG_INIT + if (reset) // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + powerOnResetState = 1'h1; // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :399:34 + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:240:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FoldedSRAMTemplate us ( // src/main/scala/xiangshan/frontend/Tage.scala:310:18 + .clock (clock), + .reset (reset), + .io_r_req_ready (_us_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T), // src/main/scala/chisel3/util/Decoupled.scala:53:35 + .io_r_req_bits_setIdx (s0_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29 + .io_r_resp_data_0 (_us_io_r_resp_data_0), + .io_r_resp_data_1 (_us_io_r_resp_data_1), + .io_w_req_valid (io_update_uMask_0 | io_update_uMask_1), // src/main/scala/xiangshan/frontend/Tage.scala:426:41 + .io_w_req_bits_setIdx (update_idx), // src/main/scala/xiangshan/frontend/Tage.scala:290:29 + .io_w_req_bits_data_0 + (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :305:43, :422:48 + .io_w_req_bits_data_1 + (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43 + .io_w_req_bits_waymask + ({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1, + ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), // src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :305:43, :415:{47,56}, :417:15, :418:7 + .extra_reset (io_update_reset_u_0 | io_update_reset_u_1) // src/main/scala/xiangshan/frontend/Tage.scala:311:51 + ); + FoldedSRAMTemplate_1 table_banks_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_0_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 + .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_0) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + FoldedSRAMTemplate_1 table_banks_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_1_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 + .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_1) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + FoldedSRAMTemplate_1 table_banks_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_2_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:86, :322:52 + .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_2) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + FoldedSRAMTemplate_1 table_banks_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:315:11 + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_3_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), // src/main/scala/chisel3/util/Decoupled.scala:53:35, src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :322:52 + .io_r_req_bits_setIdx (s0_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), // src/main/scala/xiangshan/frontend/Tage.scala:391:49 + .io_w_req_bits_setIdx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_w_req_bits_data_0_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_data_1_tag (per_bank_update_wdata_3_1_tag), // src/main/scala/xiangshan/frontend/Tage.scala:291:38 + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), // src/main/scala/xiangshan/frontend/Tage.scala:448:12 + .io_w_req_bits_waymask (per_bank_update_way_mask_3) // src/main/scala/xiangshan/frontend/Tage.scala:384:11 + ); + WrBypass bank_wrbypasses_0_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_0_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_0_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_0), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_0_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_1_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_1), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_1_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_2_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_2), // src/main/scala/xiangshan/frontend/Tage.scala:272:86, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_2_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_3_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:434:11 + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & (&(update_idx[1:0]))), // src/main/scala/xiangshan/frontend/Tage.scala:272:{66,86}, :290:{29,38}, :468:45 + .io_write_idx (update_idx[10:2]), // src/main/scala/xiangshan/frontend/Tage.scala:273:37, :290:{29,38} + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :305:43, :448:12 + .io_hit (_bank_wrbypasses_3_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits) + ); + assign io_req_ready = ~powerOnResetState; // src/main/scala/xiangshan/frontend/Tage.scala:240:7, :399:34, :407:19 + assign io_resps_0_valid = + ~(s1_unhashed_idx[0]) & _hit_selected_WIRE | s1_unhashed_idx[0] + & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_0_bits_ctr = + (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_1) + | (s1_unhashed_idx[0] ? _resp_selected_WIRE_5 : 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_0_bits_u = + ~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0] + & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :310:18, :330:34 + assign io_resps_0_bits_unconf = + ~(s1_unhashed_idx[0]) & _unconf_selected_WIRE | s1_unhashed_idx[0] + & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_1_valid = + s1_unhashed_idx[0] & _hit_selected_WIRE | ~(s1_unhashed_idx[0]) + & _hit_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 + assign io_resps_1_bits_ctr = + (s1_unhashed_idx[0] ? _resp_selected_WIRE_1 : 3'h0) + | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_WIRE_5); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :240:7, :330:34 + assign io_resps_1_bits_u = + s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0]) + & _us_io_r_resp_data_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :310:18, :330:34 + assign io_resps_1_bits_unconf = + s1_unhashed_idx[0] & _unconf_selected_WIRE | ~(s1_unhashed_idx[0]) + & _unconf_selected_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:53:42, :55:92, :240:7, :330:34 +endmodule + diff --git a/src/TageSC/Tage_SC.sv b/src/TageSC/Tage_SC.sv new file mode 100644 index 0000000..a4932a3 --- /dev/null +++ b/src/TageSC/Tage_SC.sv @@ -0,0 +1,5856 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module Tage_SC( // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + input clock, + input reset, + input [35:0] io_reset_vector, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [10:0] io_in_bits_folded_hist_1_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [10:0] io_in_bits_folded_hist_1_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_in_bits_folded_hist_1_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_1_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_in_bits_folded_hist_1_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_1_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_in_bits_folded_hist_1_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_in_bits_folded_hist_1_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_1_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_1_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [10:0] io_in_bits_folded_hist_1_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_3_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_ctrl_tage_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_ctrl_sc_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_s1_ready, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [10:0] io_update_bits_spec_info_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [10:0] io_update_bits_spec_info_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_update_bits_spec_info_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_update_bits_spec_info_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_update_bits_spec_info_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_update_bits_spec_info_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [10:0] io_update_bits_spec_info_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_mispred_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_mispred_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [218:0] io_update_bits_meta // src/main/scala/xiangshan/frontend/BPU.scala:171:14 +); + + reg [5:0] r_1_3; // src/main/scala/xiangshan/frontend/SC.scala:299:40 + reg [5:0] r_1_2; // src/main/scala/xiangshan/frontend/SC.scala:299:40 + reg [5:0] r_1_1; // src/main/scala/xiangshan/frontend/SC.scala:299:40 + reg [5:0] r_1_0; // src/main/scala/xiangshan/frontend/SC.scala:299:40 + reg resp_meta_scMeta_scPreds_1_r; // src/main/scala/xiangshan/frontend/SC.scala:298:40 + reg resp_meta_scMeta_scUsed_1_r; // src/main/scala/xiangshan/frontend/SC.scala:297:40 + reg resp_meta_scMeta_tageTakens_1_r; // src/main/scala/xiangshan/frontend/SC.scala:296:40 + reg [5:0] r_3; // src/main/scala/xiangshan/frontend/SC.scala:299:40 + reg [5:0] r_2; // src/main/scala/xiangshan/frontend/SC.scala:299:40 + reg [5:0] r_1; // src/main/scala/xiangshan/frontend/SC.scala:299:40 + reg [5:0] r_0; // src/main/scala/xiangshan/frontend/SC.scala:299:40 + reg resp_meta_scMeta_scPreds_0_r; // src/main/scala/xiangshan/frontend/SC.scala:298:40 + reg resp_meta_scMeta_scUsed_0_r; // src/main/scala/xiangshan/frontend/SC.scala:297:40 + reg resp_meta_scMeta_tageTakens_0_r; // src/main/scala/xiangshan/frontend/SC.scala:296:40 + reg [1:0] resp_meta_basecnts_1_r; // src/main/scala/xiangshan/frontend/Tage.scala:703:41 + reg resp_meta_takens_1_r; // src/main/scala/xiangshan/frontend/Tage.scala:702:41 + reg resp_meta_altDiffers_1_r; // src/main/scala/xiangshan/frontend/Tage.scala:700:41 + reg resp_meta_altUsed_1_r; // src/main/scala/xiangshan/frontend/Tage.scala:699:41 + reg [3:0] resp_meta_allocates_1_r; // src/main/scala/xiangshan/frontend/Tage.scala:686:40 + reg resp_meta_providerResps_1_r_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:669:49 + reg resp_meta_providerResps_1_r_u; // src/main/scala/xiangshan/frontend/Tage.scala:669:49 + reg [2:0] resp_meta_providerResps_1_r_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:669:49 + reg [1:0] resp_meta_providers_1_bits_r; // src/main/scala/xiangshan/frontend/Tage.scala:668:49 + reg resp_meta_providers_1_valid_r; // src/main/scala/xiangshan/frontend/Tage.scala:667:49 + reg [1:0] resp_meta_basecnts_0_r; // src/main/scala/xiangshan/frontend/Tage.scala:703:41 + reg resp_meta_takens_0_r; // src/main/scala/xiangshan/frontend/Tage.scala:702:41 + reg resp_meta_altDiffers_0_r; // src/main/scala/xiangshan/frontend/Tage.scala:700:41 + reg resp_meta_altUsed_0_r; // src/main/scala/xiangshan/frontend/Tage.scala:699:41 + reg [3:0] resp_meta_allocates_0_r; // src/main/scala/xiangshan/frontend/Tage.scala:686:40 + reg resp_meta_providerResps_0_r_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:669:49 + reg resp_meta_providerResps_0_r_u; // src/main/scala/xiangshan/frontend/Tage.scala:669:49 + reg [2:0] resp_meta_providerResps_0_r_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:669:49 + reg [1:0] resp_meta_providers_0_bits_r; // src/main/scala/xiangshan/frontend/Tage.scala:668:49 + reg resp_meta_providers_0_valid_r; // src/main/scala/xiangshan/frontend/Tage.scala:667:49 + wire [5:0] _scTables_3_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_3_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_3_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_3_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_2_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_2_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_2_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_2_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_1_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_1_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_1_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_1_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_0_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_0_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_0_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire [5:0] _scTables_0_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23 + wire _bt_io_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:557:19 + wire [1:0] _bt_io_s1_cnt_0; // src/main/scala/xiangshan/frontend/Tage.scala:557:19 + wire [1:0] _bt_io_s1_cnt_1; // src/main/scala/xiangshan/frontend/Tage.scala:557:19 + wire _tables_3_io_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_3_io_resps_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire [2:0] _tables_3_io_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_3_io_resps_0_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_3_io_resps_0_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_3_io_resps_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire [2:0] _tables_3_io_resps_1_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_3_io_resps_1_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_3_io_resps_1_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_2_io_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_2_io_resps_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire [2:0] _tables_2_io_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_2_io_resps_0_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_2_io_resps_0_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_2_io_resps_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire [2:0] _tables_2_io_resps_1_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_2_io_resps_1_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_2_io_resps_1_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_1_io_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_1_io_resps_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire [2:0] _tables_1_io_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_1_io_resps_0_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_1_io_resps_0_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_1_io_resps_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire [2:0] _tables_1_io_resps_1_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_1_io_resps_1_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_1_io_resps_1_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_0_io_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_0_io_resps_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire [2:0] _tables_0_io_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_0_io_resps_0_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_0_io_resps_0_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_0_io_resps_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire [2:0] _tables_0_io_resps_1_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_0_io_resps_1_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire _tables_0_io_resps_1_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + wire [35:0] _reset_vector_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 + reg [38:0] s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + reg REG; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 + reg REG_1; // src/main/scala/xiangshan/frontend/BPU.scala:190:16 + reg [6:0] bankTickCtrDistanceToTops_0; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 + reg [6:0] bankTickCtrDistanceToTops_1; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 + reg [6:0] bankTickCtrs_0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + reg [6:0] bankTickCtrs_1; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + reg [3:0] useAltOnNaCtrs_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_2; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_3; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_4; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_5; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_6; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_7; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_9; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_10; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_11; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_12; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_13; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_14; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_15; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_16; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_17; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_18; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_19; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_20; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_21; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_22; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_23; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_24; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_25; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_26; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_27; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_28; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_29; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_30; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_31; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_32; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_33; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_34; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_35; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_36; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_37; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_38; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_39; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_40; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_41; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_42; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_43; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_44; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_45; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_46; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_47; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_48; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_49; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_50; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_51; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_52; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_53; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_54; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_55; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_56; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_57; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_58; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_59; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_60; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_61; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_62; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_63; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_64; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_65; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_66; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_67; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_68; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_69; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_70; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_71; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_72; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_73; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_74; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_75; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_76; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_77; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_78; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_79; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_80; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_81; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_82; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_83; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_84; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_85; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_86; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_87; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_88; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_89; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_90; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_91; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_92; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_93; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_94; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_95; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_96; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_97; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_98; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_99; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_100; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_101; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_102; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_103; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_104; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_105; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_106; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_107; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_108; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_109; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_110; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_111; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_112; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_113; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_114; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_115; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_116; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_117; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_118; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_119; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_120; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_121; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_122; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_123; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_124; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_125; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_126; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_0_127; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_2; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_3; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_4; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_5; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_6; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_7; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_9; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_10; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_11; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_12; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_13; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_14; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_15; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_16; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_17; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_18; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_19; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_20; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_21; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_22; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_23; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_24; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_25; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_26; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_27; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_28; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_29; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_30; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_31; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_32; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_33; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_34; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_35; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_36; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_37; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_38; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_39; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_40; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_41; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_42; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_43; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_44; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_45; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_46; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_47; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_48; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_49; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_50; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_51; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_52; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_53; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_54; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_55; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_56; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_57; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_58; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_59; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_60; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_61; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_62; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_63; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_64; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_65; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_66; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_67; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_68; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_69; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_70; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_71; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_72; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_73; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_74; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_75; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_76; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_77; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_78; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_79; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_80; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_81; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_82; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_83; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_84; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_85; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_86; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_87; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_88; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_89; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_90; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_91; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_92; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_93; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_94; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_95; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_96; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_97; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_98; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_99; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_100; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_101; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_102; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_103; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_104; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_105; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_106; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_107; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_108; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_109; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_110; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_111; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_112; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_113; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_114; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_115; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_116; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_117; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_118; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_119; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_120; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_121; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_122; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_123; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_124; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_125; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_126; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg [3:0] useAltOnNaCtrs_1_127; // src/main/scala/xiangshan/frontend/Tage.scala:563:31 + reg s2_provideds_0; // src/main/scala/xiangshan/frontend/Tage.scala:593:38 + reg s2_provideds_1; // src/main/scala/xiangshan/frontend/Tage.scala:593:38 + reg [1:0] s2_providers_0; // src/main/scala/xiangshan/frontend/Tage.scala:594:38 + reg [1:0] s2_providers_1; // src/main/scala/xiangshan/frontend/Tage.scala:594:38 + reg [2:0] s2_providerResps_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:595:38 + reg s2_providerResps_0_u; // src/main/scala/xiangshan/frontend/Tage.scala:595:38 + reg s2_providerResps_0_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:595:38 + reg [2:0] s2_providerResps_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:595:38 + reg s2_providerResps_1_u; // src/main/scala/xiangshan/frontend/Tage.scala:595:38 + reg s2_providerResps_1_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:595:38 + reg s2_altUsed_0; // src/main/scala/xiangshan/frontend/Tage.scala:599:38 + reg s2_altUsed_1; // src/main/scala/xiangshan/frontend/Tage.scala:599:38 + reg s2_tageTakens_dup_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 + reg s2_tageTakens_dup_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 + reg s2_tageTakens_dup_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 + reg s2_tageTakens_dup_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 + reg s2_tageTakens_dup_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 + reg s2_tageTakens_dup_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 + reg s2_tageTakens_dup_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 + reg s2_tageTakens_dup_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58 + reg s2_finalAltPreds_0; // src/main/scala/xiangshan/frontend/Tage.scala:601:38 + reg s2_finalAltPreds_1; // src/main/scala/xiangshan/frontend/Tage.scala:601:38 + reg [1:0] s2_basecnts_0; // src/main/scala/xiangshan/frontend/Tage.scala:602:38 + reg [1:0] s2_basecnts_1; // src/main/scala/xiangshan/frontend/Tage.scala:602:38 + wire updateValids_0 = + io_update_bits_ftb_entry_brSlots_0_valid & io_update_valid + & ~io_update_bits_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/Tage.scala:614:{47,50} + wire updateValids_1 = + io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_tailSlot_sharing + & io_update_valid & ~io_update_bits_ftb_entry_always_taken_1 + & ~io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/Tage.scala:614:{50,84}, :615:7 + reg [3:0] allocatableSlots; // src/main/scala/xiangshan/frontend/Tage.scala:679:16 + reg tage_enable_dup_REG; // src/main/scala/xiangshan/frontend/Tage.scala:705:38 + wire bUpdateTakens_0 = updateValids_0 & io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :715:33 + wire updateProviderCorrect = io_update_bits_meta[76] == bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :720:{55,71} + wire needToAllocate = + updateValids_0 & io_update_bits_mispred_mask_0 + & ~(io_update_bits_meta[70] & updateProviderCorrect & io_update_bits_meta[84]); // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :720:71, :770:{53,56,96} + reg [63:0] allocLFSR_lfsr; // utility/src/main/scala/utility/LFSR64.scala:27:33 + wire [3:0] _longerHistoryTableMask_T_1 = 4'h1 << io_update_bits_meta[83:82]; // src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + wire [2:0] _GEN = _longerHistoryTableMask_T_1[2:0] | _longerHistoryTableMask_T_1[3:1]; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + wire [3:0] longerHistoryTableMask = + ~({&(io_update_bits_meta[83:82]), + _GEN[2], + _GEN[1] | (&(io_update_bits_meta[83:82])), + _GEN[0] | io_update_bits_meta[83:82] == 2'h2 | (&(io_update_bits_meta[83:82]))} + & {4{io_update_bits_meta[84]}}); // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :775:{40,91,97}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + wire _firstEntry_T = io_update_bits_meta[56] & longerHistoryTableMask[0]; // src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} + wire _firstEntry_T_1 = io_update_bits_meta[57] & longerHistoryTableMask[1]; // src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} + wire _firstEntry_T_2 = io_update_bits_meta[58] & longerHistoryTableMask[2]; // src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} + reg [3:0] allocatableSlots_1; // src/main/scala/xiangshan/frontend/Tage.scala:679:16 + reg tage_enable_dup_REG_1; // src/main/scala/xiangshan/frontend/Tage.scala:705:38 + wire bUpdateTakens_1 = updateValids_1 & io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :715:33 + wire updateProviderCorrect_1 = io_update_bits_meta[81] == bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :720:{55,71} + wire needToAllocate_1 = + updateValids_1 & io_update_bits_mispred_mask_1 + & ~(io_update_bits_meta[71] & updateProviderCorrect_1 & io_update_bits_meta[87]); // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :720:71, :770:{53,56,96} + reg [63:0] allocLFSR_lfsr_1; // utility/src/main/scala/utility/LFSR64.scala:27:33 + wire [3:0] _longerHistoryTableMask_T_11 = 4'h1 << io_update_bits_meta[86:85]; // src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + wire [2:0] _GEN_0 = + _longerHistoryTableMask_T_11[2:0] | _longerHistoryTableMask_T_11[3:1]; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + wire [3:0] longerHistoryTableMask_1 = + ~({&(io_update_bits_meta[86:85]), + _GEN_0[2], + _GEN_0[1] | (&(io_update_bits_meta[86:85])), + _GEN_0[0] | io_update_bits_meta[86:85] == 2'h2 | (&(io_update_bits_meta[86:85]))} + & {4{io_update_bits_meta[87]}}); // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :775:{40,91,97}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + wire _firstEntry_T_6 = io_update_bits_meta[60] & longerHistoryTableMask_1[0]; // src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} + wire _firstEntry_T_7 = io_update_bits_meta[61] & longerHistoryTableMask_1[1]; // src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} + wire _firstEntry_T_8 = io_update_bits_meta[62] & longerHistoryTableMask_1[2]; // src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} + reg tables_0_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + reg tables_0_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + reg tables_0_io_update_alloc_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + reg [2:0] tables_0_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + reg tables_0_io_update_uMask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + reg tables_0_io_update_us_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + reg tables_0_io_update_reset_u_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + reg tables_1_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + reg tables_1_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + reg tables_1_io_update_alloc_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + reg [2:0] tables_1_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + reg tables_1_io_update_uMask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + reg tables_1_io_update_us_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + reg tables_1_io_update_reset_u_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + reg tables_2_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + reg tables_2_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + reg tables_2_io_update_alloc_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + reg [2:0] tables_2_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + reg tables_2_io_update_uMask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + reg tables_2_io_update_us_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + reg tables_2_io_update_reset_u_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + reg tables_3_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + reg tables_3_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + reg tables_3_io_update_alloc_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + reg [2:0] tables_3_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + reg tables_3_io_update_uMask_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + reg tables_3_io_update_us_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + reg tables_3_io_update_reset_u_0_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + reg tables_0_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + reg tables_0_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + reg tables_0_io_update_alloc_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + reg [2:0] tables_0_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + reg tables_0_io_update_uMask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + reg tables_0_io_update_us_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + reg tables_0_io_update_reset_u_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + reg [38:0] tables_0_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + reg [7:0] tables_0_io_update_folded_hist_REG_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + reg [6:0] tables_0_io_update_folded_hist_REG_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + reg tables_1_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + reg tables_1_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + reg tables_1_io_update_alloc_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + reg [2:0] tables_1_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + reg tables_1_io_update_uMask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + reg tables_1_io_update_us_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + reg tables_1_io_update_reset_u_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + reg [38:0] tables_1_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + reg [6:0] tables_1_io_update_folded_hist_REG_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + reg [7:0] tables_1_io_update_folded_hist_REG_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + reg [10:0] tables_1_io_update_folded_hist_REG_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + reg tables_2_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + reg tables_2_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + reg tables_2_io_update_alloc_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + reg [2:0] tables_2_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + reg tables_2_io_update_uMask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + reg tables_2_io_update_us_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + reg tables_2_io_update_reset_u_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + reg [38:0] tables_2_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + reg [10:0] tables_2_io_update_folded_hist_REG_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + reg [6:0] tables_2_io_update_folded_hist_REG_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + reg [7:0] tables_2_io_update_folded_hist_REG_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + reg tables_3_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + reg tables_3_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + reg tables_3_io_update_alloc_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + reg [2:0] tables_3_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + reg tables_3_io_update_uMask_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + reg tables_3_io_update_us_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + reg tables_3_io_update_reset_u_1_REG; // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + reg [38:0] tables_3_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + reg [10:0] tables_3_io_update_folded_hist_REG_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + reg [7:0] tables_3_io_update_folded_hist_REG_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + reg [6:0] tables_3_io_update_folded_hist_REG_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + reg REG_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:848:31 + reg REG_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:848:31 + reg [1:0] REG_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:849:30 + reg [1:0] REG_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:849:30 + reg [38:0] bt_io_update_pc_REG; // src/main/scala/xiangshan/frontend/Tage.scala:850:29 + reg REG_4_0; // src/main/scala/xiangshan/frontend/Tage.scala:851:33 + reg REG_4_1; // src/main/scala/xiangshan/frontend/Tage.scala:851:33 + reg [4:0] scThresholds_0_ctr; // src/main/scala/xiangshan/frontend/SC.scala:229:52 + reg [7:0] scThresholds_0_thres; // src/main/scala/xiangshan/frontend/SC.scala:229:52 + reg [4:0] scThresholds_1_ctr; // src/main/scala/xiangshan/frontend/SC.scala:229:52 + reg [7:0] scThresholds_1_thres; // src/main/scala/xiangshan/frontend/SC.scala:229:52 + reg [8:0] s2_scTableSums_0; // src/main/scala/xiangshan/frontend/SC.scala:277:37 + reg [8:0] s2_scTableSums_1; // src/main/scala/xiangshan/frontend/SC.scala:277:37 + reg [2:0] s2_tagePrvdCtrCentered_r; // src/main/scala/xiangshan/frontend/SC.scala:278:61 + reg [5:0] s2_scResps_r_0_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_0_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_1_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_1_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_2_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_2_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_3_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_3_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg s3_pred_dup_0; // src/main/scala/xiangshan/frontend/SC.scala:318:54 + reg s3_pred_dup_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54 + reg s3_pred_dup_2; // src/main/scala/xiangshan/frontend/SC.scala:318:54 + reg s3_pred_dup_3; // src/main/scala/xiangshan/frontend/SC.scala:318:54 + reg sc_enable_dup_REG; // src/main/scala/xiangshan/frontend/SC.scala:319:38 + wire _GEN_1 = updateValids_0 & io_update_bits_meta[50]; // src/main/scala/xiangshan/frontend/SC.scala:328:29, src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40 + wire [7:0] _sum_T_8 = + 8'({io_update_bits_meta[5], io_update_bits_meta[5:0], 1'h1} + + {io_update_bits_meta[11], io_update_bits_meta[11:6], 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:618:40, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire [7:0] _sum_T_9 = + 8'({io_update_bits_meta[17], io_update_bits_meta[17:12], 1'h1} + + {io_update_bits_meta[23], io_update_bits_meta[23:18], 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:618:40, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire [8:0] _sum_T_10 = 9'({_sum_T_8[7], _sum_T_8} + {_sum_T_9[7], _sum_T_9}); // utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire [2:0] _sumAboveThreshold_T = io_update_bits_meta[76:74] ^ 3'h4; // src/main/scala/xiangshan/frontend/SC.scala:266:52, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :618:40 + wire [9:0] sum = + 10'({_sum_T_10[8], _sum_T_10} + + {{3{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8}); // src/main/scala/xiangshan/frontend/SC.scala:266:52, :334:74, src/main/scala/xiangshan/frontend/Tage.scala:565:14, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire _update_on_mispred_0_T = + io_update_bits_meta[48] != io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/SC.scala:348:40, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + reg [8:0] s2_scTableSums_1_0; // src/main/scala/xiangshan/frontend/SC.scala:277:37 + reg [8:0] s2_scTableSums_1_1; // src/main/scala/xiangshan/frontend/SC.scala:277:37 + reg [2:0] s2_tagePrvdCtrCentered_r_1; // src/main/scala/xiangshan/frontend/SC.scala:278:61 + reg [5:0] s2_scResps_r_1_0_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_1_0_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_1_1_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_1_1_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_1_2_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_1_2_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_1_3_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg [5:0] s2_scResps_r_1_3_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:283:41 + reg s3_pred_dup_0_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54 + reg s3_pred_dup_1_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54 + reg s3_pred_dup_2_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54 + reg s3_pred_dup_3_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54 + reg sc_enable_dup_REG_1; // src/main/scala/xiangshan/frontend/SC.scala:319:38 + wire _GEN_2 = updateValids_1 & io_update_bits_meta[51]; // src/main/scala/xiangshan/frontend/SC.scala:328:29, src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40 + wire [7:0] _sum_T_22 = + 8'({io_update_bits_meta[29], io_update_bits_meta[29:24], 1'h1} + + {io_update_bits_meta[35], io_update_bits_meta[35:30], 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:618:40, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire [7:0] _sum_T_23 = + 8'({io_update_bits_meta[41], io_update_bits_meta[41:36], 1'h1} + + {io_update_bits_meta[47], io_update_bits_meta[47:42], 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:618:40, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire [8:0] _sum_T_24 = 9'({_sum_T_22[7], _sum_T_22} + {_sum_T_23[7], _sum_T_23}); // utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire [2:0] _sumAboveThreshold_T_19 = io_update_bits_meta[81:79] ^ 3'h4; // src/main/scala/xiangshan/frontend/SC.scala:266:52, src/main/scala/xiangshan/frontend/Tage.scala:47:34, :618:40 + wire [9:0] sum_1 = + 10'({_sum_T_24[8], _sum_T_24} + + {{3{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8}); // src/main/scala/xiangshan/frontend/SC.scala:266:52, :334:74, src/main/scala/xiangshan/frontend/Tage.scala:565:14, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire _update_on_mispred_1_T = + io_update_bits_meta[49] != io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/SC.scala:348:40, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + reg scTables_0_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 + reg scTables_0_io_update_tagePreds_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 + reg scTables_0_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + reg [5:0] scTables_0_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 + reg scTables_1_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 + reg scTables_1_io_update_tagePreds_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 + reg scTables_1_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + reg [5:0] scTables_1_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 + reg scTables_2_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 + reg scTables_2_io_update_tagePreds_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 + reg scTables_2_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + reg [5:0] scTables_2_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 + reg scTables_3_io_update_mask_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 + reg scTables_3_io_update_tagePreds_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 + reg scTables_3_io_update_takens_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + reg [5:0] scTables_3_io_update_oldCtrs_0_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 + reg scTables_0_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 + reg scTables_0_io_update_tagePreds_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 + reg scTables_0_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + reg [5:0] scTables_0_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 + reg [38:0] scTables_0_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/SC.scala:381:44 + reg scTables_1_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 + reg scTables_1_io_update_tagePreds_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 + reg scTables_1_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + reg [5:0] scTables_1_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 + reg [38:0] scTables_1_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/SC.scala:381:44 + reg [3:0] scTables_1_io_update_folded_hist_REG_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:382:53 + reg scTables_2_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 + reg scTables_2_io_update_tagePreds_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 + reg scTables_2_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + reg [5:0] scTables_2_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 + reg [38:0] scTables_2_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/SC.scala:381:44 + reg [7:0] scTables_2_io_update_folded_hist_REG_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:382:53 + reg scTables_3_io_update_mask_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:377:49 + reg scTables_3_io_update_tagePreds_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:378:54 + reg scTables_3_io_update_takens_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + reg [5:0] scTables_3_io_update_oldCtrs_1_REG; // src/main/scala/xiangshan/frontend/SC.scala:380:54 + reg [38:0] scTables_3_io_update_pc_REG_1; // src/main/scala/xiangshan/frontend/SC.scala:381:44 + reg [7:0] scTables_3_io_update_folded_hist_REG_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:382:53 + wire [7:0] _s1_scTableSums_T_8 = + 8'({_scTables_0_io_resp_ctrs_0_0[5], _scTables_0_io_resp_ctrs_0_0, 1'h1} + + {_scTables_1_io_resp_ctrs_0_0[5], _scTables_1_io_resp_ctrs_0_0, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire [7:0] _s1_scTableSums_T_9 = + 8'({_scTables_2_io_resp_ctrs_0_0[5], _scTables_2_io_resp_ctrs_0_0, 1'h1} + + {_scTables_3_io_resp_ctrs_0_0[5], _scTables_3_io_resp_ctrs_0_0, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire [7:0] _s1_scTableSums_T_19 = + 8'({_scTables_0_io_resp_ctrs_0_1[5], _scTables_0_io_resp_ctrs_0_1, 1'h1} + + {_scTables_1_io_resp_ctrs_0_1[5], _scTables_1_io_resp_ctrs_0_1, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire [7:0] _s1_scTableSums_T_20 = + 8'({_scTables_2_io_resp_ctrs_0_1[5], _scTables_2_io_resp_ctrs_0_1, 1'h1} + + {_scTables_3_io_resp_ctrs_0_1[5], _scTables_3_io_resp_ctrs_0_1, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire [7:0] _s1_scTableSums_T_30 = + 8'({_scTables_0_io_resp_ctrs_1_0[5], _scTables_0_io_resp_ctrs_1_0, 1'h1} + + {_scTables_1_io_resp_ctrs_1_0[5], _scTables_1_io_resp_ctrs_1_0, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire [7:0] _s1_scTableSums_T_31 = + 8'({_scTables_2_io_resp_ctrs_1_0[5], _scTables_2_io_resp_ctrs_1_0, 1'h1} + + {_scTables_3_io_resp_ctrs_1_0[5], _scTables_3_io_resp_ctrs_1_0, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire [7:0] _s1_scTableSums_T_41 = + 8'({_scTables_0_io_resp_ctrs_1_1[5], _scTables_0_io_resp_ctrs_1_1, 1'h1} + + {_scTables_1_io_resp_ctrs_1_1[5], _scTables_1_io_resp_ctrs_1_1, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire [7:0] _s1_scTableSums_T_42 = + 8'({_scTables_2_io_resp_ctrs_1_1[5], _scTables_2_io_resp_ctrs_1_1, 1'h1} + + {_scTables_3_io_resp_ctrs_1_1[5], _scTables_3_io_resp_ctrs_1_1, 1'h1}); // src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/SC.scala:217:23, utility/src/main/scala/utility/ParallelMux.scala:115:82 + wire useAltCtr = + s1_pc_dup_0[7:1] == 7'h0 & useAltOnNaCtrs_0_0[3] | s1_pc_dup_0[7:1] == 7'h1 + & useAltOnNaCtrs_0_1[3] | s1_pc_dup_0[7:1] == 7'h2 & useAltOnNaCtrs_0_2[3] + | s1_pc_dup_0[7:1] == 7'h3 & useAltOnNaCtrs_0_3[3] | s1_pc_dup_0[7:1] == 7'h4 + & useAltOnNaCtrs_0_4[3] | s1_pc_dup_0[7:1] == 7'h5 & useAltOnNaCtrs_0_5[3] + | s1_pc_dup_0[7:1] == 7'h6 & useAltOnNaCtrs_0_6[3] | s1_pc_dup_0[7:1] == 7'h7 + & useAltOnNaCtrs_0_7[3] | s1_pc_dup_0[7:1] == 7'h8 & useAltOnNaCtrs_0_8[3] + | s1_pc_dup_0[7:1] == 7'h9 & useAltOnNaCtrs_0_9[3] | s1_pc_dup_0[7:1] == 7'hA + & useAltOnNaCtrs_0_10[3] | s1_pc_dup_0[7:1] == 7'hB & useAltOnNaCtrs_0_11[3] + | s1_pc_dup_0[7:1] == 7'hC & useAltOnNaCtrs_0_12[3] | s1_pc_dup_0[7:1] == 7'hD + & useAltOnNaCtrs_0_13[3] | s1_pc_dup_0[7:1] == 7'hE & useAltOnNaCtrs_0_14[3] + | s1_pc_dup_0[7:1] == 7'hF & useAltOnNaCtrs_0_15[3] | s1_pc_dup_0[7:1] == 7'h10 + & useAltOnNaCtrs_0_16[3] | s1_pc_dup_0[7:1] == 7'h11 & useAltOnNaCtrs_0_17[3] + | s1_pc_dup_0[7:1] == 7'h12 & useAltOnNaCtrs_0_18[3] | s1_pc_dup_0[7:1] == 7'h13 + & useAltOnNaCtrs_0_19[3] | s1_pc_dup_0[7:1] == 7'h14 & useAltOnNaCtrs_0_20[3] + | s1_pc_dup_0[7:1] == 7'h15 & useAltOnNaCtrs_0_21[3] | s1_pc_dup_0[7:1] == 7'h16 + & useAltOnNaCtrs_0_22[3] | s1_pc_dup_0[7:1] == 7'h17 & useAltOnNaCtrs_0_23[3] + | s1_pc_dup_0[7:1] == 7'h18 & useAltOnNaCtrs_0_24[3] | s1_pc_dup_0[7:1] == 7'h19 + & useAltOnNaCtrs_0_25[3] | s1_pc_dup_0[7:1] == 7'h1A & useAltOnNaCtrs_0_26[3] + | s1_pc_dup_0[7:1] == 7'h1B & useAltOnNaCtrs_0_27[3] | s1_pc_dup_0[7:1] == 7'h1C + & useAltOnNaCtrs_0_28[3] | s1_pc_dup_0[7:1] == 7'h1D & useAltOnNaCtrs_0_29[3] + | s1_pc_dup_0[7:1] == 7'h1E & useAltOnNaCtrs_0_30[3] | s1_pc_dup_0[7:1] == 7'h1F + & useAltOnNaCtrs_0_31[3] | s1_pc_dup_0[7:1] == 7'h20 & useAltOnNaCtrs_0_32[3] + | s1_pc_dup_0[7:1] == 7'h21 & useAltOnNaCtrs_0_33[3] | s1_pc_dup_0[7:1] == 7'h22 + & useAltOnNaCtrs_0_34[3] | s1_pc_dup_0[7:1] == 7'h23 & useAltOnNaCtrs_0_35[3] + | s1_pc_dup_0[7:1] == 7'h24 & useAltOnNaCtrs_0_36[3] | s1_pc_dup_0[7:1] == 7'h25 + & useAltOnNaCtrs_0_37[3] | s1_pc_dup_0[7:1] == 7'h26 & useAltOnNaCtrs_0_38[3] + | s1_pc_dup_0[7:1] == 7'h27 & useAltOnNaCtrs_0_39[3] | s1_pc_dup_0[7:1] == 7'h28 + & useAltOnNaCtrs_0_40[3] | s1_pc_dup_0[7:1] == 7'h29 & useAltOnNaCtrs_0_41[3] + | s1_pc_dup_0[7:1] == 7'h2A & useAltOnNaCtrs_0_42[3] | s1_pc_dup_0[7:1] == 7'h2B + & useAltOnNaCtrs_0_43[3] | s1_pc_dup_0[7:1] == 7'h2C & useAltOnNaCtrs_0_44[3] + | s1_pc_dup_0[7:1] == 7'h2D & useAltOnNaCtrs_0_45[3] | s1_pc_dup_0[7:1] == 7'h2E + & useAltOnNaCtrs_0_46[3] | s1_pc_dup_0[7:1] == 7'h2F & useAltOnNaCtrs_0_47[3] + | s1_pc_dup_0[7:1] == 7'h30 & useAltOnNaCtrs_0_48[3] | s1_pc_dup_0[7:1] == 7'h31 + & useAltOnNaCtrs_0_49[3] | s1_pc_dup_0[7:1] == 7'h32 & useAltOnNaCtrs_0_50[3] + | s1_pc_dup_0[7:1] == 7'h33 & useAltOnNaCtrs_0_51[3] | s1_pc_dup_0[7:1] == 7'h34 + & useAltOnNaCtrs_0_52[3] | s1_pc_dup_0[7:1] == 7'h35 & useAltOnNaCtrs_0_53[3] + | s1_pc_dup_0[7:1] == 7'h36 & useAltOnNaCtrs_0_54[3] | s1_pc_dup_0[7:1] == 7'h37 + & useAltOnNaCtrs_0_55[3] | s1_pc_dup_0[7:1] == 7'h38 & useAltOnNaCtrs_0_56[3] + | s1_pc_dup_0[7:1] == 7'h39 & useAltOnNaCtrs_0_57[3] | s1_pc_dup_0[7:1] == 7'h3A + & useAltOnNaCtrs_0_58[3] | s1_pc_dup_0[7:1] == 7'h3B & useAltOnNaCtrs_0_59[3] + | s1_pc_dup_0[7:1] == 7'h3C & useAltOnNaCtrs_0_60[3] | s1_pc_dup_0[7:1] == 7'h3D + & useAltOnNaCtrs_0_61[3] | s1_pc_dup_0[7:1] == 7'h3E & useAltOnNaCtrs_0_62[3] + | s1_pc_dup_0[7:1] == 7'h3F & useAltOnNaCtrs_0_63[3] | s1_pc_dup_0[7:1] == 7'h40 + & useAltOnNaCtrs_0_64[3] | s1_pc_dup_0[7:1] == 7'h41 & useAltOnNaCtrs_0_65[3] + | s1_pc_dup_0[7:1] == 7'h42 & useAltOnNaCtrs_0_66[3] | s1_pc_dup_0[7:1] == 7'h43 + & useAltOnNaCtrs_0_67[3] | s1_pc_dup_0[7:1] == 7'h44 & useAltOnNaCtrs_0_68[3] + | s1_pc_dup_0[7:1] == 7'h45 & useAltOnNaCtrs_0_69[3] | s1_pc_dup_0[7:1] == 7'h46 + & useAltOnNaCtrs_0_70[3] | s1_pc_dup_0[7:1] == 7'h47 & useAltOnNaCtrs_0_71[3] + | s1_pc_dup_0[7:1] == 7'h48 & useAltOnNaCtrs_0_72[3] | s1_pc_dup_0[7:1] == 7'h49 + & useAltOnNaCtrs_0_73[3] | s1_pc_dup_0[7:1] == 7'h4A & useAltOnNaCtrs_0_74[3] + | s1_pc_dup_0[7:1] == 7'h4B & useAltOnNaCtrs_0_75[3] | s1_pc_dup_0[7:1] == 7'h4C + & useAltOnNaCtrs_0_76[3] | s1_pc_dup_0[7:1] == 7'h4D & useAltOnNaCtrs_0_77[3] + | s1_pc_dup_0[7:1] == 7'h4E & useAltOnNaCtrs_0_78[3] | s1_pc_dup_0[7:1] == 7'h4F + & useAltOnNaCtrs_0_79[3] | s1_pc_dup_0[7:1] == 7'h50 & useAltOnNaCtrs_0_80[3] + | s1_pc_dup_0[7:1] == 7'h51 & useAltOnNaCtrs_0_81[3] | s1_pc_dup_0[7:1] == 7'h52 + & useAltOnNaCtrs_0_82[3] | s1_pc_dup_0[7:1] == 7'h53 & useAltOnNaCtrs_0_83[3] + | s1_pc_dup_0[7:1] == 7'h54 & useAltOnNaCtrs_0_84[3] | s1_pc_dup_0[7:1] == 7'h55 + & useAltOnNaCtrs_0_85[3] | s1_pc_dup_0[7:1] == 7'h56 & useAltOnNaCtrs_0_86[3] + | s1_pc_dup_0[7:1] == 7'h57 & useAltOnNaCtrs_0_87[3] | s1_pc_dup_0[7:1] == 7'h58 + & useAltOnNaCtrs_0_88[3] | s1_pc_dup_0[7:1] == 7'h59 & useAltOnNaCtrs_0_89[3] + | s1_pc_dup_0[7:1] == 7'h5A & useAltOnNaCtrs_0_90[3] | s1_pc_dup_0[7:1] == 7'h5B + & useAltOnNaCtrs_0_91[3] | s1_pc_dup_0[7:1] == 7'h5C & useAltOnNaCtrs_0_92[3] + | s1_pc_dup_0[7:1] == 7'h5D & useAltOnNaCtrs_0_93[3] | s1_pc_dup_0[7:1] == 7'h5E + & useAltOnNaCtrs_0_94[3] | s1_pc_dup_0[7:1] == 7'h5F & useAltOnNaCtrs_0_95[3] + | s1_pc_dup_0[7:1] == 7'h60 & useAltOnNaCtrs_0_96[3] | s1_pc_dup_0[7:1] == 7'h61 + & useAltOnNaCtrs_0_97[3] | s1_pc_dup_0[7:1] == 7'h62 & useAltOnNaCtrs_0_98[3] + | s1_pc_dup_0[7:1] == 7'h63 & useAltOnNaCtrs_0_99[3] | s1_pc_dup_0[7:1] == 7'h64 + & useAltOnNaCtrs_0_100[3] | s1_pc_dup_0[7:1] == 7'h65 & useAltOnNaCtrs_0_101[3] + | s1_pc_dup_0[7:1] == 7'h66 & useAltOnNaCtrs_0_102[3] | s1_pc_dup_0[7:1] == 7'h67 + & useAltOnNaCtrs_0_103[3] | s1_pc_dup_0[7:1] == 7'h68 & useAltOnNaCtrs_0_104[3] + | s1_pc_dup_0[7:1] == 7'h69 & useAltOnNaCtrs_0_105[3] | s1_pc_dup_0[7:1] == 7'h6A + & useAltOnNaCtrs_0_106[3] | s1_pc_dup_0[7:1] == 7'h6B & useAltOnNaCtrs_0_107[3] + | s1_pc_dup_0[7:1] == 7'h6C & useAltOnNaCtrs_0_108[3] | s1_pc_dup_0[7:1] == 7'h6D + & useAltOnNaCtrs_0_109[3] | s1_pc_dup_0[7:1] == 7'h6E & useAltOnNaCtrs_0_110[3] + | s1_pc_dup_0[7:1] == 7'h6F & useAltOnNaCtrs_0_111[3] | s1_pc_dup_0[7:1] == 7'h70 + & useAltOnNaCtrs_0_112[3] | s1_pc_dup_0[7:1] == 7'h71 & useAltOnNaCtrs_0_113[3] + | s1_pc_dup_0[7:1] == 7'h72 & useAltOnNaCtrs_0_114[3] | s1_pc_dup_0[7:1] == 7'h73 + & useAltOnNaCtrs_0_115[3] | s1_pc_dup_0[7:1] == 7'h74 & useAltOnNaCtrs_0_116[3] + | s1_pc_dup_0[7:1] == 7'h75 & useAltOnNaCtrs_0_117[3] | s1_pc_dup_0[7:1] == 7'h76 + & useAltOnNaCtrs_0_118[3] | s1_pc_dup_0[7:1] == 7'h77 & useAltOnNaCtrs_0_119[3] + | s1_pc_dup_0[7:1] == 7'h78 & useAltOnNaCtrs_0_120[3] | s1_pc_dup_0[7:1] == 7'h79 + & useAltOnNaCtrs_0_121[3] | s1_pc_dup_0[7:1] == 7'h7A & useAltOnNaCtrs_0_122[3] + | s1_pc_dup_0[7:1] == 7'h7B & useAltOnNaCtrs_0_123[3] | s1_pc_dup_0[7:1] == 7'h7C + & useAltOnNaCtrs_0_124[3] | s1_pc_dup_0[7:1] == 7'h7D & useAltOnNaCtrs_0_125[3] + | s1_pc_dup_0[7:1] == 7'h7E & useAltOnNaCtrs_0_126[3] | (&(s1_pc_dup_0[7:1])) + & useAltOnNaCtrs_0_127[3]; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :736:41 + wire _providerInfo_T = _tables_3_io_resps_0_valid | _tables_2_io_resps_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:65 + wire [2:0] s1_providerResps_0_ctr = + _providerInfo_T + ? (_tables_3_io_resps_0_valid + ? _tables_3_io_resps_0_bits_ctr + : _tables_2_io_resps_0_bits_ctr) + : _tables_1_io_resps_0_valid + ? _tables_1_io_resps_0_bits_ctr + : _tables_0_io_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + wire s1_provideds_0 = + _tables_0_io_resps_0_valid | _tables_1_io_resps_0_valid | _tables_2_io_resps_0_valid + | _tables_3_io_resps_0_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :656:47 + wire s1_altUsed_0 = + ~s1_provideds_0 + | (_providerInfo_T + ? (_tables_3_io_resps_0_valid + ? _tables_3_io_resps_0_bits_unconf & useAltCtr + : _tables_2_io_resps_0_bits_unconf & useAltCtr) + : _tables_1_io_resps_0_valid + ? _tables_1_io_resps_0_bits_unconf & useAltCtr + : _tables_0_io_resps_0_bits_unconf & useAltCtr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:549:21, :651:52, :656:47, :689:{28,38}, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + wire s1_tageTakens_0 = + s1_altUsed_0 ? _bt_io_s1_cnt_0[1] : s1_providerResps_0_ctr[2]; // src/main/scala/xiangshan/frontend/Tage.scala:557:19, :689:38, :691:10, :692:18, :693:30, utility/src/main/scala/utility/ParallelMux.scala:90:77 + wire _GEN_3 = io_update_bits_meta[83:82] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39 + wire _GEN_4 = updateValids_0 & io_update_bits_meta[84]; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :620:31, :754:22, :755:29, :756:39 + wire _GEN_5 = io_update_bits_meta[83:82] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39 + wire _GEN_6 = io_update_bits_meta[83:82] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39 + wire [1:0] maskedEntry = + io_update_bits_meta[56] & longerHistoryTableMask[0] & allocLFSR_lfsr[0] + ? 2'h0 + : io_update_bits_meta[57] & longerHistoryTableMask[1] & allocLFSR_lfsr[1] + ? 2'h1 + : {1'h1, + ~(io_update_bits_meta[58] & longerHistoryTableMask[2] & allocLFSR_lfsr[2])}; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:652:26, :774:29, :775:40, :776:40, :777:60, :778:{27,56}, :786:52, utility/src/main/scala/utility/LFSR64.scala:27:33 + wire [3:0] _allocate_T = + (io_update_bits_meta[59:56] & longerHistoryTableMask) >> maskedEntry; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/Tage.scala:618:40, :775:40, :776:40, :787:36 + wire [1:0] allocate = + _allocate_T[0] + ? maskedEntry + : _firstEntry_T ? 2'h0 : _firstEntry_T_1 ? 2'h1 : {1'h1, ~_firstEntry_T_2}; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:652:26, :776:40, :778:56, :787:{23,36} + wire _GEN_7 = allocate == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33 + wire _GEN_8 = needToAllocate & (|(io_update_bits_meta[59:56])) & _GEN_7; // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33 + wire _GEN_9 = allocate == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33 + wire _GEN_10 = needToAllocate & (|(io_update_bits_meta[59:56])) & _GEN_9; // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33 + wire _GEN_11 = allocate == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33 + wire _GEN_12 = needToAllocate & (|(io_update_bits_meta[59:56])) & _GEN_11; // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33 + wire _GEN_13 = needToAllocate & (|(io_update_bits_meta[59:56])) & (&allocate); // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :787:23, :790:27, :809:26, :810:33 + wire _GEN_14 = needToAllocate & (|(io_update_bits_meta[59:56])); // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :812:34 + wire updateResetU_0 = needToAllocate & (&bankTickCtrs_0); // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :622:31, :770:53, :790:27, :816:{29,59} + wire useAltCtr_1 = + s1_pc_dup_0[7:1] == 7'h0 & useAltOnNaCtrs_1_0[3] | s1_pc_dup_0[7:1] == 7'h1 + & useAltOnNaCtrs_1_1[3] | s1_pc_dup_0[7:1] == 7'h2 & useAltOnNaCtrs_1_2[3] + | s1_pc_dup_0[7:1] == 7'h3 & useAltOnNaCtrs_1_3[3] | s1_pc_dup_0[7:1] == 7'h4 + & useAltOnNaCtrs_1_4[3] | s1_pc_dup_0[7:1] == 7'h5 & useAltOnNaCtrs_1_5[3] + | s1_pc_dup_0[7:1] == 7'h6 & useAltOnNaCtrs_1_6[3] | s1_pc_dup_0[7:1] == 7'h7 + & useAltOnNaCtrs_1_7[3] | s1_pc_dup_0[7:1] == 7'h8 & useAltOnNaCtrs_1_8[3] + | s1_pc_dup_0[7:1] == 7'h9 & useAltOnNaCtrs_1_9[3] | s1_pc_dup_0[7:1] == 7'hA + & useAltOnNaCtrs_1_10[3] | s1_pc_dup_0[7:1] == 7'hB & useAltOnNaCtrs_1_11[3] + | s1_pc_dup_0[7:1] == 7'hC & useAltOnNaCtrs_1_12[3] | s1_pc_dup_0[7:1] == 7'hD + & useAltOnNaCtrs_1_13[3] | s1_pc_dup_0[7:1] == 7'hE & useAltOnNaCtrs_1_14[3] + | s1_pc_dup_0[7:1] == 7'hF & useAltOnNaCtrs_1_15[3] | s1_pc_dup_0[7:1] == 7'h10 + & useAltOnNaCtrs_1_16[3] | s1_pc_dup_0[7:1] == 7'h11 & useAltOnNaCtrs_1_17[3] + | s1_pc_dup_0[7:1] == 7'h12 & useAltOnNaCtrs_1_18[3] | s1_pc_dup_0[7:1] == 7'h13 + & useAltOnNaCtrs_1_19[3] | s1_pc_dup_0[7:1] == 7'h14 & useAltOnNaCtrs_1_20[3] + | s1_pc_dup_0[7:1] == 7'h15 & useAltOnNaCtrs_1_21[3] | s1_pc_dup_0[7:1] == 7'h16 + & useAltOnNaCtrs_1_22[3] | s1_pc_dup_0[7:1] == 7'h17 & useAltOnNaCtrs_1_23[3] + | s1_pc_dup_0[7:1] == 7'h18 & useAltOnNaCtrs_1_24[3] | s1_pc_dup_0[7:1] == 7'h19 + & useAltOnNaCtrs_1_25[3] | s1_pc_dup_0[7:1] == 7'h1A & useAltOnNaCtrs_1_26[3] + | s1_pc_dup_0[7:1] == 7'h1B & useAltOnNaCtrs_1_27[3] | s1_pc_dup_0[7:1] == 7'h1C + & useAltOnNaCtrs_1_28[3] | s1_pc_dup_0[7:1] == 7'h1D & useAltOnNaCtrs_1_29[3] + | s1_pc_dup_0[7:1] == 7'h1E & useAltOnNaCtrs_1_30[3] | s1_pc_dup_0[7:1] == 7'h1F + & useAltOnNaCtrs_1_31[3] | s1_pc_dup_0[7:1] == 7'h20 & useAltOnNaCtrs_1_32[3] + | s1_pc_dup_0[7:1] == 7'h21 & useAltOnNaCtrs_1_33[3] | s1_pc_dup_0[7:1] == 7'h22 + & useAltOnNaCtrs_1_34[3] | s1_pc_dup_0[7:1] == 7'h23 & useAltOnNaCtrs_1_35[3] + | s1_pc_dup_0[7:1] == 7'h24 & useAltOnNaCtrs_1_36[3] | s1_pc_dup_0[7:1] == 7'h25 + & useAltOnNaCtrs_1_37[3] | s1_pc_dup_0[7:1] == 7'h26 & useAltOnNaCtrs_1_38[3] + | s1_pc_dup_0[7:1] == 7'h27 & useAltOnNaCtrs_1_39[3] | s1_pc_dup_0[7:1] == 7'h28 + & useAltOnNaCtrs_1_40[3] | s1_pc_dup_0[7:1] == 7'h29 & useAltOnNaCtrs_1_41[3] + | s1_pc_dup_0[7:1] == 7'h2A & useAltOnNaCtrs_1_42[3] | s1_pc_dup_0[7:1] == 7'h2B + & useAltOnNaCtrs_1_43[3] | s1_pc_dup_0[7:1] == 7'h2C & useAltOnNaCtrs_1_44[3] + | s1_pc_dup_0[7:1] == 7'h2D & useAltOnNaCtrs_1_45[3] | s1_pc_dup_0[7:1] == 7'h2E + & useAltOnNaCtrs_1_46[3] | s1_pc_dup_0[7:1] == 7'h2F & useAltOnNaCtrs_1_47[3] + | s1_pc_dup_0[7:1] == 7'h30 & useAltOnNaCtrs_1_48[3] | s1_pc_dup_0[7:1] == 7'h31 + & useAltOnNaCtrs_1_49[3] | s1_pc_dup_0[7:1] == 7'h32 & useAltOnNaCtrs_1_50[3] + | s1_pc_dup_0[7:1] == 7'h33 & useAltOnNaCtrs_1_51[3] | s1_pc_dup_0[7:1] == 7'h34 + & useAltOnNaCtrs_1_52[3] | s1_pc_dup_0[7:1] == 7'h35 & useAltOnNaCtrs_1_53[3] + | s1_pc_dup_0[7:1] == 7'h36 & useAltOnNaCtrs_1_54[3] | s1_pc_dup_0[7:1] == 7'h37 + & useAltOnNaCtrs_1_55[3] | s1_pc_dup_0[7:1] == 7'h38 & useAltOnNaCtrs_1_56[3] + | s1_pc_dup_0[7:1] == 7'h39 & useAltOnNaCtrs_1_57[3] | s1_pc_dup_0[7:1] == 7'h3A + & useAltOnNaCtrs_1_58[3] | s1_pc_dup_0[7:1] == 7'h3B & useAltOnNaCtrs_1_59[3] + | s1_pc_dup_0[7:1] == 7'h3C & useAltOnNaCtrs_1_60[3] | s1_pc_dup_0[7:1] == 7'h3D + & useAltOnNaCtrs_1_61[3] | s1_pc_dup_0[7:1] == 7'h3E & useAltOnNaCtrs_1_62[3] + | s1_pc_dup_0[7:1] == 7'h3F & useAltOnNaCtrs_1_63[3] | s1_pc_dup_0[7:1] == 7'h40 + & useAltOnNaCtrs_1_64[3] | s1_pc_dup_0[7:1] == 7'h41 & useAltOnNaCtrs_1_65[3] + | s1_pc_dup_0[7:1] == 7'h42 & useAltOnNaCtrs_1_66[3] | s1_pc_dup_0[7:1] == 7'h43 + & useAltOnNaCtrs_1_67[3] | s1_pc_dup_0[7:1] == 7'h44 & useAltOnNaCtrs_1_68[3] + | s1_pc_dup_0[7:1] == 7'h45 & useAltOnNaCtrs_1_69[3] | s1_pc_dup_0[7:1] == 7'h46 + & useAltOnNaCtrs_1_70[3] | s1_pc_dup_0[7:1] == 7'h47 & useAltOnNaCtrs_1_71[3] + | s1_pc_dup_0[7:1] == 7'h48 & useAltOnNaCtrs_1_72[3] | s1_pc_dup_0[7:1] == 7'h49 + & useAltOnNaCtrs_1_73[3] | s1_pc_dup_0[7:1] == 7'h4A & useAltOnNaCtrs_1_74[3] + | s1_pc_dup_0[7:1] == 7'h4B & useAltOnNaCtrs_1_75[3] | s1_pc_dup_0[7:1] == 7'h4C + & useAltOnNaCtrs_1_76[3] | s1_pc_dup_0[7:1] == 7'h4D & useAltOnNaCtrs_1_77[3] + | s1_pc_dup_0[7:1] == 7'h4E & useAltOnNaCtrs_1_78[3] | s1_pc_dup_0[7:1] == 7'h4F + & useAltOnNaCtrs_1_79[3] | s1_pc_dup_0[7:1] == 7'h50 & useAltOnNaCtrs_1_80[3] + | s1_pc_dup_0[7:1] == 7'h51 & useAltOnNaCtrs_1_81[3] | s1_pc_dup_0[7:1] == 7'h52 + & useAltOnNaCtrs_1_82[3] | s1_pc_dup_0[7:1] == 7'h53 & useAltOnNaCtrs_1_83[3] + | s1_pc_dup_0[7:1] == 7'h54 & useAltOnNaCtrs_1_84[3] | s1_pc_dup_0[7:1] == 7'h55 + & useAltOnNaCtrs_1_85[3] | s1_pc_dup_0[7:1] == 7'h56 & useAltOnNaCtrs_1_86[3] + | s1_pc_dup_0[7:1] == 7'h57 & useAltOnNaCtrs_1_87[3] | s1_pc_dup_0[7:1] == 7'h58 + & useAltOnNaCtrs_1_88[3] | s1_pc_dup_0[7:1] == 7'h59 & useAltOnNaCtrs_1_89[3] + | s1_pc_dup_0[7:1] == 7'h5A & useAltOnNaCtrs_1_90[3] | s1_pc_dup_0[7:1] == 7'h5B + & useAltOnNaCtrs_1_91[3] | s1_pc_dup_0[7:1] == 7'h5C & useAltOnNaCtrs_1_92[3] + | s1_pc_dup_0[7:1] == 7'h5D & useAltOnNaCtrs_1_93[3] | s1_pc_dup_0[7:1] == 7'h5E + & useAltOnNaCtrs_1_94[3] | s1_pc_dup_0[7:1] == 7'h5F & useAltOnNaCtrs_1_95[3] + | s1_pc_dup_0[7:1] == 7'h60 & useAltOnNaCtrs_1_96[3] | s1_pc_dup_0[7:1] == 7'h61 + & useAltOnNaCtrs_1_97[3] | s1_pc_dup_0[7:1] == 7'h62 & useAltOnNaCtrs_1_98[3] + | s1_pc_dup_0[7:1] == 7'h63 & useAltOnNaCtrs_1_99[3] | s1_pc_dup_0[7:1] == 7'h64 + & useAltOnNaCtrs_1_100[3] | s1_pc_dup_0[7:1] == 7'h65 & useAltOnNaCtrs_1_101[3] + | s1_pc_dup_0[7:1] == 7'h66 & useAltOnNaCtrs_1_102[3] | s1_pc_dup_0[7:1] == 7'h67 + & useAltOnNaCtrs_1_103[3] | s1_pc_dup_0[7:1] == 7'h68 & useAltOnNaCtrs_1_104[3] + | s1_pc_dup_0[7:1] == 7'h69 & useAltOnNaCtrs_1_105[3] | s1_pc_dup_0[7:1] == 7'h6A + & useAltOnNaCtrs_1_106[3] | s1_pc_dup_0[7:1] == 7'h6B & useAltOnNaCtrs_1_107[3] + | s1_pc_dup_0[7:1] == 7'h6C & useAltOnNaCtrs_1_108[3] | s1_pc_dup_0[7:1] == 7'h6D + & useAltOnNaCtrs_1_109[3] | s1_pc_dup_0[7:1] == 7'h6E & useAltOnNaCtrs_1_110[3] + | s1_pc_dup_0[7:1] == 7'h6F & useAltOnNaCtrs_1_111[3] | s1_pc_dup_0[7:1] == 7'h70 + & useAltOnNaCtrs_1_112[3] | s1_pc_dup_0[7:1] == 7'h71 & useAltOnNaCtrs_1_113[3] + | s1_pc_dup_0[7:1] == 7'h72 & useAltOnNaCtrs_1_114[3] | s1_pc_dup_0[7:1] == 7'h73 + & useAltOnNaCtrs_1_115[3] | s1_pc_dup_0[7:1] == 7'h74 & useAltOnNaCtrs_1_116[3] + | s1_pc_dup_0[7:1] == 7'h75 & useAltOnNaCtrs_1_117[3] | s1_pc_dup_0[7:1] == 7'h76 + & useAltOnNaCtrs_1_118[3] | s1_pc_dup_0[7:1] == 7'h77 & useAltOnNaCtrs_1_119[3] + | s1_pc_dup_0[7:1] == 7'h78 & useAltOnNaCtrs_1_120[3] | s1_pc_dup_0[7:1] == 7'h79 + & useAltOnNaCtrs_1_121[3] | s1_pc_dup_0[7:1] == 7'h7A & useAltOnNaCtrs_1_122[3] + | s1_pc_dup_0[7:1] == 7'h7B & useAltOnNaCtrs_1_123[3] | s1_pc_dup_0[7:1] == 7'h7C + & useAltOnNaCtrs_1_124[3] | s1_pc_dup_0[7:1] == 7'h7D & useAltOnNaCtrs_1_125[3] + | s1_pc_dup_0[7:1] == 7'h7E & useAltOnNaCtrs_1_126[3] | (&(s1_pc_dup_0[7:1])) + & useAltOnNaCtrs_1_127[3]; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :736:41 + wire _providerInfo_T_5 = _tables_3_io_resps_1_valid | _tables_2_io_resps_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:65 + wire [2:0] s1_providerResps_1_ctr = + _providerInfo_T_5 + ? (_tables_3_io_resps_1_valid + ? _tables_3_io_resps_1_bits_ctr + : _tables_2_io_resps_1_bits_ctr) + : _tables_1_io_resps_1_valid + ? _tables_1_io_resps_1_bits_ctr + : _tables_0_io_resps_1_bits_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + wire s1_provideds_1 = + _tables_0_io_resps_1_valid | _tables_1_io_resps_1_valid | _tables_2_io_resps_1_valid + | _tables_3_io_resps_1_valid; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :656:47 + wire s1_altUsed_1 = + ~s1_provideds_1 + | (_providerInfo_T_5 + ? (_tables_3_io_resps_1_valid + ? _tables_3_io_resps_1_bits_unconf & useAltCtr_1 + : _tables_2_io_resps_1_bits_unconf & useAltCtr_1) + : _tables_1_io_resps_1_valid + ? _tables_1_io_resps_1_bits_unconf & useAltCtr_1 + : _tables_0_io_resps_1_bits_unconf & useAltCtr_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/Tage.scala:549:21, :651:52, :656:47, :689:{28,38}, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + wire s1_tageTakens_1 = + s1_altUsed_1 ? _bt_io_s1_cnt_1[1] : s1_providerResps_1_ctr[2]; // src/main/scala/xiangshan/frontend/Tage.scala:557:19, :689:38, :691:10, :692:18, :693:30, utility/src/main/scala/utility/ParallelMux.scala:90:77 + wire _GEN_15 = io_update_bits_meta[86:85] == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39 + wire _GEN_16 = updateValids_1 & io_update_bits_meta[87]; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :620:31, :754:22, :755:29, :756:39 + wire _GEN_17 = io_update_bits_meta[86:85] == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39 + wire _GEN_18 = io_update_bits_meta[86:85] == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26, :756:39 + wire [1:0] maskedEntry_1 = + io_update_bits_meta[60] & longerHistoryTableMask_1[0] & allocLFSR_lfsr_1[0] + ? 2'h0 + : io_update_bits_meta[61] & longerHistoryTableMask_1[1] & allocLFSR_lfsr_1[1] + ? 2'h1 + : {1'h1, + ~(io_update_bits_meta[62] & longerHistoryTableMask_1[2] + & allocLFSR_lfsr_1[2])}; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:652:26, :774:29, :775:40, :776:40, :777:60, :778:{27,56}, :786:52, utility/src/main/scala/utility/LFSR64.scala:27:33 + wire [3:0] _allocate_T_2 = + (io_update_bits_meta[63:60] & longerHistoryTableMask_1) >> maskedEntry_1; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/Tage.scala:618:40, :775:40, :776:40, :787:36 + wire [1:0] allocate_1 = + _allocate_T_2[0] + ? maskedEntry_1 + : _firstEntry_T_6 ? 2'h0 : _firstEntry_T_7 ? 2'h1 : {1'h1, ~_firstEntry_T_8}; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/BPU.scala:179:15, src/main/scala/xiangshan/frontend/Tage.scala:652:26, :776:40, :778:56, :787:{23,36} + wire _GEN_19 = allocate_1 == 2'h0; // src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33 + wire _GEN_20 = needToAllocate_1 & (|(io_update_bits_meta[63:60])) & _GEN_19; // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33 + wire _GEN_21 = allocate_1 == 2'h1; // src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33 + wire _GEN_22 = needToAllocate_1 & (|(io_update_bits_meta[63:60])) & _GEN_21; // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33 + wire _GEN_23 = allocate_1 == 2'h2; // src/main/scala/xiangshan/frontend/Tage.scala:652:26, :787:23, :810:33 + wire _GEN_24 = needToAllocate_1 & (|(io_update_bits_meta[63:60])) & _GEN_23; // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :810:33 + wire _GEN_25 = + needToAllocate_1 & (|(io_update_bits_meta[63:60])) & (&allocate_1); // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :787:23, :790:27, :809:26, :810:33 + wire _GEN_26 = needToAllocate_1 & (|(io_update_bits_meta[63:60])); // src/main/scala/xiangshan/frontend/Tage.scala:129:39, :618:40, :754:22, :770:53, :790:27, :809:26, :812:34 + wire updateResetU_1 = needToAllocate_1 & (&bankTickCtrs_1); // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :622:31, :770:53, :790:27, :816:{29,59} + wire [2:0] _s2_tagePrvdCtrCentered_T = s2_tagePrvdCtrCentered_r ^ 3'h4; // src/main/scala/xiangshan/frontend/SC.scala:266:52, :278:61, src/main/scala/xiangshan/frontend/Tage.scala:47:34 + wire [9:0] _GEN_27 = + {{3{_s2_tagePrvdCtrCentered_T[2]}}, _s2_tagePrvdCtrCentered_T, 4'h8}; // src/main/scala/xiangshan/frontend/SC.scala:266:52, :279:47, src/main/scala/xiangshan/frontend/Tage.scala:565:14 + wire [9:0] s2_totalSums_0 = 10'({s2_scTableSums_0[8], s2_scTableSums_0} + _GEN_27); // src/main/scala/xiangshan/frontend/SC.scala:277:37, :279:47 + wire [9:0] s2_totalSums_1 = 10'({s2_scTableSums_1[8], s2_scTableSums_1} + _GEN_27); // src/main/scala/xiangshan/frontend/SC.scala:277:37, :279:47 + wire [8:0] _GEN_28 = {1'h0, scThresholds_0_thres}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/SC.scala:229:52, :239:29 + wire [8:0] _GEN_29 = + {{2{_s2_tagePrvdCtrCentered_T[2]}}, _s2_tagePrvdCtrCentered_T, 4'h8}; // src/main/scala/xiangshan/frontend/SC.scala:266:52, :279:47, src/main/scala/xiangshan/frontend/Tage.scala:565:14 + wire _GEN_30 = + s2_tageTakens_dup_3_0 + ? $signed(s2_totalSums_1) > -10'sh1 + : $signed(s2_totalSums_0) > -10'sh1; // src/main/scala/xiangshan/frontend/SC.scala:279:47, :281:51, :288:12, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + wire s2_pred = + s2_provideds_0 + & (s2_tageTakens_dup_3_0 + ? $signed(s2_scTableSums_1) > $signed(9'(_GEN_28 - _GEN_29)) + & ~(s2_totalSums_1[9]) + | $signed(s2_scTableSums_1) < $signed(9'(9'(9'h0 - _GEN_28) - _GEN_29)) + & s2_totalSums_1[9] + : $signed(s2_scTableSums_0) > $signed(9'(_GEN_28 - _GEN_29)) + & ~(s2_totalSums_0[9]) + | $signed(s2_scTableSums_0) < $signed(9'(9'(9'h0 - _GEN_28) - _GEN_29)) + & s2_totalSums_0[9]) + ? _GEN_30 + : s2_tageTakens_dup_3_0; // src/main/scala/xiangshan/frontend/SC.scala:232:26, :233:24, :239:{14,29,41,58}, :240:{14,16,29,41}, :277:37, :279:47, :288:{12,29}, src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58 + wire [12:0] _GEN_31 = {1'h0, 12'({1'h0, scThresholds_0_thres, 3'h0} + 12'h15)}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/SC.scala:229:52, :239:29, :242:69, :266:47 + wire [12:0] _GEN_32 = {{6{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8}; // src/main/scala/xiangshan/frontend/SC.scala:239:29, :266:52, :334:74, src/main/scala/xiangshan/frontend/Tage.scala:565:14 + wire [12:0] _GEN_33 = {{3{sum[9]}}, sum}; // src/main/scala/xiangshan/frontend/SC.scala:239:14, :240:16, :334:74, :335:26 + wire [10:0] sumAboveThreshold_totalSum = + 11'({sum[9], sum} + {{4{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8}); // src/main/scala/xiangshan/frontend/SC.scala:238:28, :240:16, :266:52, :334:74, :335:26, src/main/scala/xiangshan/frontend/Tage.scala:565:14 + wire scUpdateMask_0_3 = + _GEN_1 + & (_update_on_mispred_0_T + | ~($signed(_GEN_33) > $signed(13'(_GEN_31 - _GEN_32)) + & ~(sumAboveThreshold_totalSum[10]) + | $signed(_GEN_33) < $signed(13'(13'(13'h0 - _GEN_31) - _GEN_32)) + & sumAboveThreshold_totalSum[10])); // src/main/scala/xiangshan/frontend/SC.scala:232:26, :233:24, :238:28, :239:{14,29,41,58}, :240:{14,16,29,41}, :246:32, :328:{29,56}, :343:29, :348:40, :357:{32,55} + wire [2:0] _s2_tagePrvdCtrCentered_T_2 = s2_tagePrvdCtrCentered_r_1 ^ 3'h4; // src/main/scala/xiangshan/frontend/SC.scala:266:52, :278:61, src/main/scala/xiangshan/frontend/Tage.scala:47:34 + wire [9:0] _GEN_34 = + {{3{_s2_tagePrvdCtrCentered_T_2[2]}}, _s2_tagePrvdCtrCentered_T_2, 4'h8}; // src/main/scala/xiangshan/frontend/SC.scala:266:52, :279:47, src/main/scala/xiangshan/frontend/Tage.scala:565:14 + wire [9:0] s2_totalSums_0_1 = + 10'({s2_scTableSums_1_0[8], s2_scTableSums_1_0} + _GEN_34); // src/main/scala/xiangshan/frontend/SC.scala:277:37, :279:47 + wire [9:0] s2_totalSums_1_1 = + 10'({s2_scTableSums_1_1[8], s2_scTableSums_1_1} + _GEN_34); // src/main/scala/xiangshan/frontend/SC.scala:277:37, :279:47 + wire [8:0] _GEN_35 = {1'h0, scThresholds_1_thres}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/SC.scala:229:52, :239:29 + wire [8:0] _GEN_36 = + {{2{_s2_tagePrvdCtrCentered_T_2[2]}}, _s2_tagePrvdCtrCentered_T_2, 4'h8}; // src/main/scala/xiangshan/frontend/SC.scala:266:52, :279:47, src/main/scala/xiangshan/frontend/Tage.scala:565:14 + wire _GEN_37 = + s2_tageTakens_dup_3_1 + ? $signed(s2_totalSums_1_1) > -10'sh1 + : $signed(s2_totalSums_0_1) > -10'sh1; // src/main/scala/xiangshan/frontend/SC.scala:279:47, :281:51, :288:12, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + wire s2_pred_1 = + s2_provideds_1 + & (s2_tageTakens_dup_3_1 + ? $signed(s2_scTableSums_1_1) > $signed(9'(_GEN_35 - _GEN_36)) + & ~(s2_totalSums_1_1[9]) + | $signed(s2_scTableSums_1_1) < $signed(9'(9'(9'h0 - _GEN_35) - _GEN_36)) + & s2_totalSums_1_1[9] + : $signed(s2_scTableSums_1_0) > $signed(9'(_GEN_35 - _GEN_36)) + & ~(s2_totalSums_0_1[9]) + | $signed(s2_scTableSums_1_0) < $signed(9'(9'(9'h0 - _GEN_35) - _GEN_36)) + & s2_totalSums_0_1[9]) + ? _GEN_37 + : s2_tageTakens_dup_3_1; // src/main/scala/xiangshan/frontend/SC.scala:232:26, :233:24, :239:{14,29,41,58}, :240:{14,16,29,41}, :277:37, :279:47, :288:{12,29}, src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58 + wire [12:0] _GEN_38 = {1'h0, 12'({1'h0, scThresholds_1_thres, 3'h0} + 12'h15)}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/SC.scala:229:52, :239:29, :242:69, :266:47 + wire [12:0] _GEN_39 = {{6{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8}; // src/main/scala/xiangshan/frontend/SC.scala:239:29, :266:52, :334:74, src/main/scala/xiangshan/frontend/Tage.scala:565:14 + wire [12:0] _GEN_40 = {{3{sum_1[9]}}, sum_1}; // src/main/scala/xiangshan/frontend/SC.scala:239:14, :240:16, :334:74, :335:26 + wire [10:0] sumAboveThreshold_totalSum_1 = + 11'({sum_1[9], sum_1} + + {{4{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8}); // src/main/scala/xiangshan/frontend/SC.scala:238:28, :240:16, :266:52, :334:74, :335:26, src/main/scala/xiangshan/frontend/Tage.scala:565:14 + wire scUpdateMask_1_3 = + _GEN_2 + & (_update_on_mispred_1_T + | ~($signed(_GEN_40) > $signed(13'(_GEN_38 - _GEN_39)) + & ~(sumAboveThreshold_totalSum_1[10]) + | $signed(_GEN_40) < $signed(13'(13'(13'h0 - _GEN_38) - _GEN_39)) + & sumAboveThreshold_totalSum_1[10])); // src/main/scala/xiangshan/frontend/SC.scala:232:26, :233:24, :238:28, :239:{14,29,41,58}, :240:{14,16,29,41}, :246:32, :328:{29,56}, :343:29, :348:40, :357:{32,55} + wire [1:0] s1_providers_0 = + _providerInfo_T + ? {1'h1, _tables_3_io_resps_0_valid} + : {1'h0, _tables_1_io_resps_0_valid}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, :179:15, src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + wire [3:0] _allocatableSlots_T_14 = 4'h1 << s1_providers_0; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/ParallelMux.scala:90:77 + wire [2:0] _GEN_41 = _allocatableSlots_T_14[2:0] | _allocatableSlots_T_14[3:1]; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + wire [1:0] s1_providers_1 = + _providerInfo_T_5 + ? {1'h1, _tables_3_io_resps_1_valid} + : {1'h0, _tables_1_io_resps_1_valid}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, :179:15, src/main/scala/xiangshan/frontend/Tage.scala:549:21, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + wire [3:0] _allocatableSlots_T_39 = 4'h1 << s1_providers_1; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/ParallelMux.scala:90:77 + wire [2:0] _GEN_42 = _allocatableSlots_T_39[2:0] | _allocatableSlots_T_39[3:1]; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + always @(posedge clock) begin + if (REG_1) // src/main/scala/xiangshan/frontend/BPU.scala:190:16 + s1_pc_dup_0 <= {3'h0, _reset_vector_delay_io_out}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39, src/main/scala/xiangshan/frontend/SC.scala:266:47, utility/src/main/scala/utility/Hold.scala:97:23 + else if (io_s0_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s1_pc_dup_0 <= io_in_bits_s0_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + REG <= reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 + REG_1 <= REG & ~reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24,39,42} + if (io_s1_fire_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_provideds_0 <= s1_provideds_0; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :656:47 + s2_provideds_1 <= s1_provideds_1; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :656:47 + s2_providers_0 <= s1_providers_0; // src/main/scala/xiangshan/frontend/Tage.scala:594:38, utility/src/main/scala/utility/ParallelMux.scala:90:77 + s2_providers_1 <= s1_providers_1; // src/main/scala/xiangshan/frontend/Tage.scala:594:38, utility/src/main/scala/utility/ParallelMux.scala:90:77 + s2_providerResps_0_ctr <= s1_providerResps_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, utility/src/main/scala/utility/ParallelMux.scala:90:77 + s2_providerResps_0_u <= + _providerInfo_T + ? (_tables_3_io_resps_0_valid + ? _tables_3_io_resps_0_bits_u + : _tables_2_io_resps_0_bits_u) + : _tables_1_io_resps_0_valid + ? _tables_1_io_resps_0_bits_u + : _tables_0_io_resps_0_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :595:38, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + s2_providerResps_0_unconf <= + _providerInfo_T + ? (_tables_3_io_resps_0_valid + ? _tables_3_io_resps_0_bits_unconf + : _tables_2_io_resps_0_bits_unconf) + : _tables_1_io_resps_0_valid + ? _tables_1_io_resps_0_bits_unconf + : _tables_0_io_resps_0_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :595:38, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + s2_providerResps_1_ctr <= s1_providerResps_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, utility/src/main/scala/utility/ParallelMux.scala:90:77 + s2_providerResps_1_u <= + _providerInfo_T_5 + ? (_tables_3_io_resps_1_valid + ? _tables_3_io_resps_1_bits_u + : _tables_2_io_resps_1_bits_u) + : _tables_1_io_resps_1_valid + ? _tables_1_io_resps_1_bits_u + : _tables_0_io_resps_1_bits_u; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :595:38, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + s2_providerResps_1_unconf <= + _providerInfo_T_5 + ? (_tables_3_io_resps_1_valid + ? _tables_3_io_resps_1_bits_unconf + : _tables_2_io_resps_1_bits_unconf) + : _tables_1_io_resps_1_valid + ? _tables_1_io_resps_1_bits_unconf + : _tables_0_io_resps_1_bits_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :595:38, utility/src/main/scala/utility/ParallelMux.scala:90:{65,77} + s2_altUsed_0 <= s1_altUsed_0; // src/main/scala/xiangshan/frontend/Tage.scala:599:38, :689:38 + s2_altUsed_1 <= s1_altUsed_1; // src/main/scala/xiangshan/frontend/Tage.scala:599:38, :689:38 + s2_tageTakens_dup_1_0 <= s1_tageTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 + s2_tageTakens_dup_1_1 <= s1_tageTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 + s2_finalAltPreds_0 <= _bt_io_s1_cnt_0[1]; // src/main/scala/xiangshan/frontend/Tage.scala:557:19, :601:38, :692:18 + s2_finalAltPreds_1 <= _bt_io_s1_cnt_1[1]; // src/main/scala/xiangshan/frontend/Tage.scala:557:19, :601:38, :692:18 + s2_basecnts_0 <= _bt_io_s1_cnt_0; // src/main/scala/xiangshan/frontend/Tage.scala:557:19, :602:38 + s2_basecnts_1 <= _bt_io_s1_cnt_1; // src/main/scala/xiangshan/frontend/Tage.scala:557:19, :602:38 + allocatableSlots <= + {~_tables_3_io_resps_0_valid & ~_tables_3_io_resps_0_bits_u, + ~_tables_2_io_resps_0_valid & ~_tables_2_io_resps_0_bits_u, + ~_tables_1_io_resps_0_valid & ~_tables_1_io_resps_0_bits_u, + ~_tables_0_io_resps_0_valid & ~_tables_0_io_resps_0_bits_u} + & ~({&s1_providers_0, + _GEN_41[2], + _GEN_41[1] | (&s1_providers_0), + _GEN_41[0] | s1_providers_0 == 2'h2 | (&s1_providers_0)} + & {4{s1_provideds_0}}); // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :652:26, :656:47, :679:16, :680:{41,50,53,65,72}, :681:{11,63}, :682:17, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53, :90:77 + allocatableSlots_1 <= + {~_tables_3_io_resps_1_valid & ~_tables_3_io_resps_1_bits_u, + ~_tables_2_io_resps_1_valid & ~_tables_2_io_resps_1_bits_u, + ~_tables_1_io_resps_1_valid & ~_tables_1_io_resps_1_bits_u, + ~_tables_0_io_resps_1_valid & ~_tables_0_io_resps_1_bits_u} + & ~({&s1_providers_1, + _GEN_42[2], + _GEN_42[1] | (&s1_providers_1), + _GEN_42[0] | s1_providers_1 == 2'h2 | (&s1_providers_1)} + & {4{s1_provideds_1}}); // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :652:26, :656:47, :679:16, :680:{41,50,53,65,72}, :681:{11,63}, :682:17, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53, :90:77 + end + if (io_s1_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_tageTakens_dup_0_0 <= s1_tageTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 + s2_tageTakens_dup_0_1 <= s1_tageTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 + end + if (io_s1_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_tageTakens_dup_2_0 <= s1_tageTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 + s2_tageTakens_dup_2_1 <= s1_tageTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 + end + if (io_s1_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_tageTakens_dup_3_0 <= s1_tageTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 + s2_tageTakens_dup_3_1 <= s1_tageTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :691:10 + s2_scTableSums_0 <= + 9'({_s1_scTableSums_T_8[7], _s1_scTableSums_T_8} + + {_s1_scTableSums_T_9[7], _s1_scTableSums_T_9}); // src/main/scala/xiangshan/frontend/SC.scala:277:37, utility/src/main/scala/utility/ParallelMux.scala:115:82 + s2_scTableSums_1 <= + 9'({_s1_scTableSums_T_19[7], _s1_scTableSums_T_19} + + {_s1_scTableSums_T_20[7], _s1_scTableSums_T_20}); // src/main/scala/xiangshan/frontend/SC.scala:277:37, utility/src/main/scala/utility/ParallelMux.scala:115:82 + s2_tagePrvdCtrCentered_r <= s1_providerResps_0_ctr; // src/main/scala/xiangshan/frontend/SC.scala:278:61, utility/src/main/scala/utility/ParallelMux.scala:90:77 + s2_scResps_r_0_ctrs_0_0 <= _scTables_0_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_0_ctrs_0_1 <= _scTables_0_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_1_ctrs_0_0 <= _scTables_1_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_1_ctrs_0_1 <= _scTables_1_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_2_ctrs_0_0 <= _scTables_2_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_2_ctrs_0_1 <= _scTables_2_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_3_ctrs_0_0 <= _scTables_3_io_resp_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_3_ctrs_0_1 <= _scTables_3_io_resp_ctrs_0_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scTableSums_1_0 <= + 9'({_s1_scTableSums_T_30[7], _s1_scTableSums_T_30} + + {_s1_scTableSums_T_31[7], _s1_scTableSums_T_31}); // src/main/scala/xiangshan/frontend/SC.scala:277:37, utility/src/main/scala/utility/ParallelMux.scala:115:82 + s2_scTableSums_1_1 <= + 9'({_s1_scTableSums_T_41[7], _s1_scTableSums_T_41} + + {_s1_scTableSums_T_42[7], _s1_scTableSums_T_42}); // src/main/scala/xiangshan/frontend/SC.scala:277:37, utility/src/main/scala/utility/ParallelMux.scala:115:82 + s2_tagePrvdCtrCentered_r_1 <= s1_providerResps_1_ctr; // src/main/scala/xiangshan/frontend/SC.scala:278:61, utility/src/main/scala/utility/ParallelMux.scala:90:77 + s2_scResps_r_1_0_ctrs_1_0 <= _scTables_0_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_1_0_ctrs_1_1 <= _scTables_0_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_1_1_ctrs_1_0 <= _scTables_1_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_1_1_ctrs_1_1 <= _scTables_1_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_1_2_ctrs_1_0 <= _scTables_2_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_1_2_ctrs_1_1 <= _scTables_2_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_1_3_ctrs_1_0 <= _scTables_3_io_resp_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + s2_scResps_r_1_3_ctrs_1_1 <= _scTables_3_io_resp_ctrs_1_1; // src/main/scala/xiangshan/frontend/SC.scala:217:23, :283:41 + end + if (io_s2_fire_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + resp_meta_providers_0_valid_r <= s2_provideds_0; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :667:49 + resp_meta_providers_0_bits_r <= s2_providers_0; // src/main/scala/xiangshan/frontend/Tage.scala:594:38, :668:49 + resp_meta_providerResps_0_r_ctr <= s2_providerResps_0_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49 + resp_meta_providerResps_0_r_u <= s2_providerResps_0_u; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49 + resp_meta_providerResps_0_r_unconf <= s2_providerResps_0_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49 + resp_meta_allocates_0_r <= allocatableSlots; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :686:40 + resp_meta_altUsed_0_r <= s2_altUsed_0; // src/main/scala/xiangshan/frontend/Tage.scala:599:38, :699:41 + resp_meta_altDiffers_0_r <= s2_finalAltPreds_0 != s2_providerResps_0_ctr[2]; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :601:38, :700:41, :701:{27,54} + resp_meta_takens_0_r <= s2_tageTakens_dup_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :702:41 + resp_meta_basecnts_0_r <= s2_basecnts_0; // src/main/scala/xiangshan/frontend/Tage.scala:602:38, :703:41 + resp_meta_providers_1_valid_r <= s2_provideds_1; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :667:49 + resp_meta_providers_1_bits_r <= s2_providers_1; // src/main/scala/xiangshan/frontend/Tage.scala:594:38, :668:49 + resp_meta_providerResps_1_r_ctr <= s2_providerResps_1_ctr; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49 + resp_meta_providerResps_1_r_u <= s2_providerResps_1_u; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49 + resp_meta_providerResps_1_r_unconf <= s2_providerResps_1_unconf; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :669:49 + resp_meta_allocates_1_r <= allocatableSlots_1; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :686:40 + resp_meta_altUsed_1_r <= s2_altUsed_1; // src/main/scala/xiangshan/frontend/Tage.scala:599:38, :699:41 + resp_meta_altDiffers_1_r <= s2_finalAltPreds_1 != s2_providerResps_1_ctr[2]; // src/main/scala/xiangshan/frontend/Tage.scala:595:38, :601:38, :700:41, :701:{27,54} + resp_meta_takens_1_r <= s2_tageTakens_dup_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :702:41 + resp_meta_basecnts_1_r <= s2_basecnts_1; // src/main/scala/xiangshan/frontend/Tage.scala:602:38, :703:41 + s3_pred_dup_1 <= s2_pred; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 + s3_pred_dup_1_1 <= s2_pred_1; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 + end + tage_enable_dup_REG <= io_ctrl_tage_enable; // src/main/scala/xiangshan/frontend/Tage.scala:705:38 + tage_enable_dup_REG_1 <= io_ctrl_tage_enable; // src/main/scala/xiangshan/frontend/Tage.scala:705:38 + tables_0_io_update_mask_0_REG <= _GEN_8 | _GEN_4 & _GEN_3; // src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 + tables_0_io_update_takens_0_REG <= bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 + tables_0_io_update_alloc_0_REG <= _GEN_14 & _GEN_7; // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :836:48 + tables_0_io_update_oldCtrs_0_REG <= io_update_bits_meta[76:74]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 + tables_0_io_update_uMask_0_REG <= + _GEN_8 | updateValids_0 & io_update_bits_meta[84] & _GEN_3 + & io_update_bits_meta[68]; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 + tables_0_io_update_us_0_REG <= ~_GEN_8 & updateProviderCorrect; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 + tables_0_io_update_reset_u_0_REG <= updateResetU_0; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 + tables_1_io_update_mask_0_REG <= _GEN_10 | _GEN_4 & _GEN_5; // src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 + tables_1_io_update_takens_0_REG <= bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 + tables_1_io_update_alloc_0_REG <= _GEN_14 & _GEN_9; // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :836:48 + tables_1_io_update_oldCtrs_0_REG <= io_update_bits_meta[76:74]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 + tables_1_io_update_uMask_0_REG <= + _GEN_10 | updateValids_0 & io_update_bits_meta[84] & _GEN_5 + & io_update_bits_meta[68]; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 + tables_1_io_update_us_0_REG <= ~_GEN_10 & updateProviderCorrect; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 + tables_1_io_update_reset_u_0_REG <= updateResetU_0; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 + tables_2_io_update_mask_0_REG <= _GEN_12 | _GEN_4 & _GEN_6; // src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 + tables_2_io_update_takens_0_REG <= bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 + tables_2_io_update_alloc_0_REG <= _GEN_14 & _GEN_11; // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :836:48 + tables_2_io_update_oldCtrs_0_REG <= io_update_bits_meta[76:74]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 + tables_2_io_update_uMask_0_REG <= + _GEN_12 | updateValids_0 & io_update_bits_meta[84] & _GEN_6 + & io_update_bits_meta[68]; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 + tables_2_io_update_us_0_REG <= ~_GEN_12 & updateProviderCorrect; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 + tables_2_io_update_reset_u_0_REG <= updateResetU_0; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 + tables_3_io_update_mask_0_REG <= _GEN_13 | _GEN_4 & (&(io_update_bits_meta[83:82])); // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 + tables_3_io_update_takens_0_REG <= bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 + tables_3_io_update_alloc_0_REG <= _GEN_14 & (&allocate); // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :787:23, :790:27, :809:26, :810:33, :812:34, :836:48 + tables_3_io_update_oldCtrs_0_REG <= io_update_bits_meta[76:74]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 + tables_3_io_update_uMask_0_REG <= + _GEN_13 | updateValids_0 & io_update_bits_meta[84] & (&(io_update_bits_meta[83:82])) + & io_update_bits_meta[68]; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 + tables_3_io_update_us_0_REG <= ~_GEN_13 & updateProviderCorrect; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 + tables_3_io_update_reset_u_0_REG <= updateResetU_0; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 + tables_0_io_update_mask_1_REG <= _GEN_20 | _GEN_16 & _GEN_15; // src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 + tables_0_io_update_takens_1_REG <= bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 + tables_0_io_update_alloc_1_REG <= _GEN_26 & _GEN_19; // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :836:48 + tables_0_io_update_oldCtrs_1_REG <= io_update_bits_meta[81:79]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 + tables_0_io_update_uMask_1_REG <= + _GEN_20 | updateValids_1 & io_update_bits_meta[87] & _GEN_15 + & io_update_bits_meta[69]; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 + tables_0_io_update_us_1_REG <= ~_GEN_20 & updateProviderCorrect_1; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 + tables_0_io_update_reset_u_1_REG <= updateResetU_1; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 + tables_0_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + tables_0_io_update_folded_hist_REG_1_hist_14_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + tables_0_io_update_folded_hist_REG_1_hist_7_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + tables_1_io_update_mask_1_REG <= _GEN_22 | _GEN_16 & _GEN_17; // src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 + tables_1_io_update_takens_1_REG <= bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 + tables_1_io_update_alloc_1_REG <= _GEN_26 & _GEN_21; // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :836:48 + tables_1_io_update_oldCtrs_1_REG <= io_update_bits_meta[81:79]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 + tables_1_io_update_uMask_1_REG <= + _GEN_22 | updateValids_1 & io_update_bits_meta[87] & _GEN_17 + & io_update_bits_meta[69]; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 + tables_1_io_update_us_1_REG <= ~_GEN_22 & updateProviderCorrect_1; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 + tables_1_io_update_reset_u_1_REG <= updateResetU_1; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 + tables_1_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + tables_1_io_update_folded_hist_REG_1_hist_15_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + tables_1_io_update_folded_hist_REG_1_hist_4_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + tables_1_io_update_folded_hist_REG_1_hist_1_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + tables_2_io_update_mask_1_REG <= _GEN_24 | _GEN_16 & _GEN_18; // src/main/scala/xiangshan/frontend/Tage.scala:620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 + tables_2_io_update_takens_1_REG <= bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 + tables_2_io_update_alloc_1_REG <= _GEN_26 & _GEN_23; // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :790:27, :809:26, :810:33, :812:34, :836:48 + tables_2_io_update_oldCtrs_1_REG <= io_update_bits_meta[81:79]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 + tables_2_io_update_uMask_1_REG <= + _GEN_24 | updateValids_1 & io_update_bits_meta[87] & _GEN_18 + & io_update_bits_meta[69]; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 + tables_2_io_update_us_1_REG <= ~_GEN_24 & updateProviderCorrect_1; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 + tables_2_io_update_reset_u_1_REG <= updateResetU_1; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 + tables_2_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + tables_2_io_update_folded_hist_REG_1_hist_17_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + tables_2_io_update_folded_hist_REG_1_hist_9_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + tables_2_io_update_folded_hist_REG_1_hist_3_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + tables_3_io_update_mask_1_REG <= _GEN_25 | _GEN_16 & (&(io_update_bits_meta[86:85])); // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :620:31, :754:22, :755:29, :756:39, :790:27, :809:26, :810:33, :834:48 + tables_3_io_update_takens_1_REG <= bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :835:48 + tables_3_io_update_alloc_1_REG <= _GEN_26 & (&allocate_1); // src/main/scala/xiangshan/frontend/Tage.scala:754:22, :787:23, :790:27, :809:26, :810:33, :812:34, :836:48 + tables_3_io_update_oldCtrs_1_REG <= io_update_bits_meta[81:79]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :837:48 + tables_3_io_update_uMask_1_REG <= + _GEN_25 | updateValids_1 & io_update_bits_meta[87] & (&(io_update_bits_meta[86:85])) + & io_update_bits_meta[69]; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :621:31, :754:22, :755:29, :756:39, :757:40, :790:27, :809:26, :810:33, :813:34, :839:48 + tables_3_io_update_us_1_REG <= ~_GEN_25 & updateProviderCorrect_1; // src/main/scala/xiangshan/frontend/Tage.scala:720:71, :754:22, :790:27, :809:26, :810:33, :814:30, :840:48 + tables_3_io_update_reset_u_1_REG <= updateResetU_1; // src/main/scala/xiangshan/frontend/Tage.scala:622:31, :790:27, :816:59, :841:48 + tables_3_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + tables_3_io_update_folded_hist_REG_1_hist_16_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + tables_3_io_update_folded_hist_REG_1_hist_8_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + tables_3_io_update_folded_hist_REG_1_hist_5_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + REG_2_0 <= updateValids_0 & io_update_bits_meta[70]; // src/main/scala/xiangshan/frontend/Tage.scala:614:47, :618:40, :740:64, :848:31 + REG_2_1 <= updateValids_1 & io_update_bits_meta[71]; // src/main/scala/xiangshan/frontend/Tage.scala:614:84, :618:40, :740:64, :848:31 + REG_3_0 <= io_update_bits_meta[65:64]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :849:30 + REG_3_1 <= io_update_bits_meta[67:66]; // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :849:30 + bt_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/Tage.scala:850:29 + REG_4_0 <= bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :851:33 + REG_4_1 <= bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:715:33, :851:33 + if (io_s2_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + resp_meta_scMeta_tageTakens_0_r <= s2_tageTakens_dup_3_0; // src/main/scala/xiangshan/frontend/SC.scala:296:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + resp_meta_scMeta_scUsed_0_r <= s2_provideds_0; // src/main/scala/xiangshan/frontend/SC.scala:297:40, src/main/scala/xiangshan/frontend/Tage.scala:593:38 + resp_meta_scMeta_scPreds_0_r <= _GEN_30; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :298:40 + r_0 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_0_ctrs_0_1 : s2_scResps_r_0_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + r_1 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_1_ctrs_0_1 : s2_scResps_r_1_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + r_2 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_2_ctrs_0_1 : s2_scResps_r_2_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + r_3 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_3_ctrs_0_1 : s2_scResps_r_3_ctrs_0_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + s3_pred_dup_3 <= s2_pred; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 + resp_meta_scMeta_tageTakens_1_r <= s2_tageTakens_dup_3_1; // src/main/scala/xiangshan/frontend/SC.scala:296:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + resp_meta_scMeta_scUsed_1_r <= s2_provideds_1; // src/main/scala/xiangshan/frontend/SC.scala:297:40, src/main/scala/xiangshan/frontend/Tage.scala:593:38 + resp_meta_scMeta_scPreds_1_r <= _GEN_37; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :298:40 + r_1_0 <= + s2_tageTakens_dup_3_1 ? s2_scResps_r_1_0_ctrs_1_1 : s2_scResps_r_1_0_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + r_1_1 <= + s2_tageTakens_dup_3_1 ? s2_scResps_r_1_1_ctrs_1_1 : s2_scResps_r_1_1_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + r_1_2 <= + s2_tageTakens_dup_3_1 ? s2_scResps_r_1_2_ctrs_1_1 : s2_scResps_r_1_2_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + r_1_3 <= + s2_tageTakens_dup_3_1 ? s2_scResps_r_1_3_ctrs_1_1 : s2_scResps_r_1_3_ctrs_1_0; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :284:30, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:600:58 + s3_pred_dup_3_1 <= s2_pred_1; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 + end + if (io_s2_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_pred_dup_0 <= s2_pred; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 + s3_pred_dup_0_1 <= s2_pred_1; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 + end + if (io_s2_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_pred_dup_2 <= s2_pred; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 + s3_pred_dup_2_1 <= s2_pred_1; // src/main/scala/xiangshan/frontend/SC.scala:288:12, :318:54 + end + sc_enable_dup_REG <= io_ctrl_sc_enable; // src/main/scala/xiangshan/frontend/SC.scala:319:38 + sc_enable_dup_REG_1 <= io_ctrl_sc_enable; // src/main/scala/xiangshan/frontend/SC.scala:319:38 + scTables_0_io_update_mask_0_REG <= scUpdateMask_0_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 + scTables_0_io_update_tagePreds_0_REG <= io_update_bits_meta[52]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_0_io_update_takens_0_REG <= io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + scTables_0_io_update_oldCtrs_0_REG <= io_update_bits_meta[5:0]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_1_io_update_mask_0_REG <= scUpdateMask_0_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 + scTables_1_io_update_tagePreds_0_REG <= io_update_bits_meta[52]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_1_io_update_takens_0_REG <= io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + scTables_1_io_update_oldCtrs_0_REG <= io_update_bits_meta[11:6]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_2_io_update_mask_0_REG <= scUpdateMask_0_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 + scTables_2_io_update_tagePreds_0_REG <= io_update_bits_meta[52]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_2_io_update_takens_0_REG <= io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + scTables_2_io_update_oldCtrs_0_REG <= io_update_bits_meta[17:12]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_3_io_update_mask_0_REG <= scUpdateMask_0_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 + scTables_3_io_update_tagePreds_0_REG <= io_update_bits_meta[52]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_3_io_update_takens_0_REG <= io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + scTables_3_io_update_oldCtrs_0_REG <= io_update_bits_meta[23:18]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_0_io_update_mask_1_REG <= scUpdateMask_1_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 + scTables_0_io_update_tagePreds_1_REG <= io_update_bits_meta[53]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_0_io_update_takens_1_REG <= io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + scTables_0_io_update_oldCtrs_1_REG <= io_update_bits_meta[29:24]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_0_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:381:44 + scTables_1_io_update_mask_1_REG <= scUpdateMask_1_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 + scTables_1_io_update_tagePreds_1_REG <= io_update_bits_meta[53]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_1_io_update_takens_1_REG <= io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + scTables_1_io_update_oldCtrs_1_REG <= io_update_bits_meta[35:30]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_1_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:381:44 + scTables_1_io_update_folded_hist_REG_1_hist_12_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:382:53 + scTables_2_io_update_mask_1_REG <= scUpdateMask_1_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 + scTables_2_io_update_tagePreds_1_REG <= io_update_bits_meta[53]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_2_io_update_takens_1_REG <= io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + scTables_2_io_update_oldCtrs_1_REG <= io_update_bits_meta[41:36]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_2_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:381:44 + scTables_2_io_update_folded_hist_REG_1_hist_11_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:382:53 + scTables_3_io_update_mask_1_REG <= scUpdateMask_1_3; // src/main/scala/xiangshan/frontend/SC.scala:246:32, :328:56, :357:55, :377:49 + scTables_3_io_update_tagePreds_1_REG <= io_update_bits_meta[53]; // src/main/scala/xiangshan/frontend/SC.scala:378:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_3_io_update_takens_1_REG <= io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/SC.scala:379:54 + scTables_3_io_update_oldCtrs_1_REG <= io_update_bits_meta[47:42]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + scTables_3_io_update_pc_REG_1 <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/SC.scala:381:44 + scTables_3_io_update_folded_hist_REG_1_hist_2_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/SC.scala:382:53 + end // always @(posedge) + wire [3:0] _allocFailureMask_T = ~(io_update_bits_meta[59:56]); // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :777:35 + wire [1:0] _GEN_43 = {1'h0, _allocFailureMask_T[0] & longerHistoryTableMask[0]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 + wire [1:0] _GEN_44 = {1'h0, _allocFailureMask_T[1] & longerHistoryTableMask[1]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 + wire [1:0] _GEN_45 = {1'h0, _allocFailureMask_T[2] & longerHistoryTableMask[2]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 + wire [1:0] _GEN_46 = {1'h0, _allocFailureMask_T[3] & longerHistoryTableMask[3]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 + wire [1:0] _GEN_47 = {1'h0, _firstEntry_T}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56 + wire [1:0] _GEN_48 = {1'h0, _firstEntry_T_1}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56 + wire [1:0] _GEN_49 = {1'h0, _firstEntry_T_2}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56 + wire [1:0] _GEN_50 = {1'h0, io_update_bits_meta[59] & longerHistoryTableMask[3]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} + wire tickInc = + 3'({1'h0, 2'(_GEN_43 + _GEN_44)} + + {1'h0, + 2'(_GEN_45 + + _GEN_46)}) > 3'({1'h0, 2'(_GEN_47 + _GEN_48)} + + {1'h0, 2'(_GEN_49 + _GEN_50)}); // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:778:{27,46,56} + wire [6:0] _GEN_51 = + {4'h0, + 3'(3'({1'h0, 2'(_GEN_43 + _GEN_44)} + {1'h0, 2'(_GEN_45 + _GEN_46)}) + - (3'({1'h0, 2'(_GEN_47 + _GEN_48)} + {1'h0, 2'(_GEN_49 + _GEN_50)})))}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :778:{27,56}, :780:{30,49,59}, :782:35 + wire tickDec = + 3'({1'h0, 2'(_GEN_47 + _GEN_48)} + + {1'h0, + 2'(_GEN_49 + + _GEN_50)}) > 3'({1'h0, 2'(_GEN_43 + _GEN_44)} + + {1'h0, 2'(_GEN_45 + _GEN_46)}); // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:778:{27,56}, :779:{27,42,52} + wire [6:0] _GEN_52 = + {4'h0, + 3'(3'({1'h0, 2'(_GEN_47 + _GEN_48)} + {1'h0, 2'(_GEN_49 + _GEN_50)}) + - (3'({1'h0, 2'(_GEN_43 + _GEN_44)} + {1'h0, 2'(_GEN_45 + _GEN_46)})))}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :778:{27,56}, :781:{30,45,55}, :783:35 + wire [3:0] _allocFailureMask_T_1 = ~(io_update_bits_meta[63:60]); // src/main/scala/xiangshan/frontend/Tage.scala:618:40, :777:35 + wire [1:0] _GEN_53 = {1'h0, _allocFailureMask_T_1[0] & longerHistoryTableMask_1[0]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 + wire [1:0] _GEN_54 = {1'h0, _allocFailureMask_T_1[1] & longerHistoryTableMask_1[1]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 + wire [1:0] _GEN_55 = {1'h0, _allocFailureMask_T_1[2] & longerHistoryTableMask_1[2]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 + wire [1:0] _GEN_56 = {1'h0, _allocFailureMask_T_1[3] & longerHistoryTableMask_1[3]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :777:{35,60}, :778:27 + wire [1:0] _GEN_57 = {1'h0, _firstEntry_T_6}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56 + wire [1:0] _GEN_58 = {1'h0, _firstEntry_T_7}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56 + wire [1:0] _GEN_59 = {1'h0, _firstEntry_T_8}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:776:40, :778:56 + wire [1:0] _GEN_60 = {1'h0, io_update_bits_meta[63] & longerHistoryTableMask_1[3]}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:775:40, :776:40, :777:60, :778:{27,56} + wire tickInc_1 = + 3'({1'h0, 2'(_GEN_53 + _GEN_54)} + + {1'h0, + 2'(_GEN_55 + + _GEN_56)}) > 3'({1'h0, 2'(_GEN_57 + _GEN_58)} + + {1'h0, 2'(_GEN_59 + _GEN_60)}); // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:778:{27,46,56} + wire [6:0] _GEN_61 = + {4'h0, + 3'(3'({1'h0, 2'(_GEN_53 + _GEN_54)} + {1'h0, 2'(_GEN_55 + _GEN_56)}) + - (3'({1'h0, 2'(_GEN_57 + _GEN_58)} + {1'h0, 2'(_GEN_59 + _GEN_60)})))}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :778:{27,56}, :780:{30,49,59}, :782:35 + wire tickDec_1 = + 3'({1'h0, 2'(_GEN_57 + _GEN_58)} + + {1'h0, + 2'(_GEN_59 + + _GEN_60)}) > 3'({1'h0, 2'(_GEN_53 + _GEN_54)} + + {1'h0, 2'(_GEN_55 + _GEN_56)}); // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:778:{27,56}, :779:{27,42,52} + wire [6:0] _GEN_62 = + {4'h0, + 3'(3'({1'h0, 2'(_GEN_57 + _GEN_58)} + {1'h0, 2'(_GEN_59 + _GEN_60)}) + - (3'({1'h0, 2'(_GEN_53 + _GEN_54)} + {1'h0, 2'(_GEN_55 + _GEN_56)})))}; // src/main/scala/xiangshan/frontend/BPU.scala:171:14, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :778:{27,56}, :781:{30,45,55}, :783:35 + wire _newThres_newCtr_T = (&scThresholds_0_ctr) & _update_on_mispred_0_T; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/SC.scala:229:52, :348:40 + wire _newThres_newCtr_T_2 = scThresholds_0_ctr == 5'h0 & ~_update_on_mispred_0_T; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/SC.scala:229:52, :348:40 + wire [4:0] _newThres_newCtr_T_3 = 5'(scThresholds_0_ctr + 5'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/SC.scala:229:52 + wire [4:0] _newThres_newCtr_T_5 = 5'(scThresholds_0_ctr - 5'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/SC.scala:229:52 + wire _GEN_63 = io_update_bits_meta[48] == io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:98:12, src/main/scala/xiangshan/frontend/SC.scala:348:40, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + wire [4:0] newThres_newCtr = + _newThres_newCtr_T + ? 5'h1F + : _newThres_newCtr_T_2 + ? 5'h0 + : _GEN_63 ? _newThres_newCtr_T_5 : _newThres_newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:{8,21}, :97:{10,26}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:348:40 + wire _newThres_res_ctr_T_4 = newThres_newCtr == 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:96:8, :97:10, src/main/scala/xiangshan/frontend/SC.scala:182:42 + wire _newThres_newCtr_T_9 = (&scThresholds_1_ctr) & _update_on_mispred_1_T; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/SC.scala:229:52, :348:40 + wire _newThres_newCtr_T_11 = + scThresholds_1_ctr == 5'h0 & ~_update_on_mispred_1_T; // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/SC.scala:229:52, :348:40 + wire [4:0] _newThres_newCtr_T_12 = 5'(scThresholds_1_ctr + 5'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/SC.scala:229:52 + wire [4:0] _newThres_newCtr_T_14 = 5'(scThresholds_1_ctr - 5'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/SC.scala:229:52 + wire _GEN_64 = io_update_bits_meta[49] == io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:98:12, src/main/scala/xiangshan/frontend/SC.scala:348:40, src/main/scala/xiangshan/frontend/Tage.scala:618:40 + wire [4:0] newThres_newCtr_1 = + _newThres_newCtr_T_9 + ? 5'h1F + : _newThres_newCtr_T_11 + ? 5'h0 + : _GEN_64 ? _newThres_newCtr_T_14 : _newThres_newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:{8,21}, :97:{10,26}, :98:{12,24,35}, src/main/scala/xiangshan/frontend/SC.scala:348:40 + wire _newThres_res_ctr_T_11 = newThres_newCtr_1 == 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:96:8, :97:10, src/main/scala/xiangshan/frontend/SC.scala:182:42 + wire [3:0] updateUseAltCtr = + (io_update_bits_pc[7:1] == 7'h0 ? useAltOnNaCtrs_0_0 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1 ? useAltOnNaCtrs_0_1 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2 ? useAltOnNaCtrs_0_2 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3 ? useAltOnNaCtrs_0_3 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4 ? useAltOnNaCtrs_0_4 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5 ? useAltOnNaCtrs_0_5 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6 ? useAltOnNaCtrs_0_6 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7 ? useAltOnNaCtrs_0_7 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h8 ? useAltOnNaCtrs_0_8 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h9 ? useAltOnNaCtrs_0_9 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hA ? useAltOnNaCtrs_0_10 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hB ? useAltOnNaCtrs_0_11 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hC ? useAltOnNaCtrs_0_12 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hD ? useAltOnNaCtrs_0_13 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hE ? useAltOnNaCtrs_0_14 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hF ? useAltOnNaCtrs_0_15 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h10 ? useAltOnNaCtrs_0_16 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h11 ? useAltOnNaCtrs_0_17 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h12 ? useAltOnNaCtrs_0_18 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h13 ? useAltOnNaCtrs_0_19 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h14 ? useAltOnNaCtrs_0_20 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h15 ? useAltOnNaCtrs_0_21 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h16 ? useAltOnNaCtrs_0_22 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h17 ? useAltOnNaCtrs_0_23 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h18 ? useAltOnNaCtrs_0_24 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h19 ? useAltOnNaCtrs_0_25 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1A ? useAltOnNaCtrs_0_26 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1B ? useAltOnNaCtrs_0_27 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1C ? useAltOnNaCtrs_0_28 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1D ? useAltOnNaCtrs_0_29 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1E ? useAltOnNaCtrs_0_30 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1F ? useAltOnNaCtrs_0_31 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h20 ? useAltOnNaCtrs_0_32 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h21 ? useAltOnNaCtrs_0_33 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h22 ? useAltOnNaCtrs_0_34 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h23 ? useAltOnNaCtrs_0_35 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h24 ? useAltOnNaCtrs_0_36 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h25 ? useAltOnNaCtrs_0_37 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h26 ? useAltOnNaCtrs_0_38 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h27 ? useAltOnNaCtrs_0_39 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h28 ? useAltOnNaCtrs_0_40 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h29 ? useAltOnNaCtrs_0_41 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2A ? useAltOnNaCtrs_0_42 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2B ? useAltOnNaCtrs_0_43 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2C ? useAltOnNaCtrs_0_44 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2D ? useAltOnNaCtrs_0_45 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2E ? useAltOnNaCtrs_0_46 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2F ? useAltOnNaCtrs_0_47 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h30 ? useAltOnNaCtrs_0_48 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h31 ? useAltOnNaCtrs_0_49 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h32 ? useAltOnNaCtrs_0_50 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h33 ? useAltOnNaCtrs_0_51 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h34 ? useAltOnNaCtrs_0_52 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h35 ? useAltOnNaCtrs_0_53 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h36 ? useAltOnNaCtrs_0_54 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h37 ? useAltOnNaCtrs_0_55 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h38 ? useAltOnNaCtrs_0_56 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h39 ? useAltOnNaCtrs_0_57 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3A ? useAltOnNaCtrs_0_58 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3B ? useAltOnNaCtrs_0_59 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3C ? useAltOnNaCtrs_0_60 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3D ? useAltOnNaCtrs_0_61 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3E ? useAltOnNaCtrs_0_62 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3F ? useAltOnNaCtrs_0_63 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h40 ? useAltOnNaCtrs_0_64 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h41 ? useAltOnNaCtrs_0_65 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h42 ? useAltOnNaCtrs_0_66 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h43 ? useAltOnNaCtrs_0_67 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h44 ? useAltOnNaCtrs_0_68 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h45 ? useAltOnNaCtrs_0_69 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h46 ? useAltOnNaCtrs_0_70 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h47 ? useAltOnNaCtrs_0_71 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h48 ? useAltOnNaCtrs_0_72 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h49 ? useAltOnNaCtrs_0_73 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4A ? useAltOnNaCtrs_0_74 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4B ? useAltOnNaCtrs_0_75 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4C ? useAltOnNaCtrs_0_76 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4D ? useAltOnNaCtrs_0_77 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4E ? useAltOnNaCtrs_0_78 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4F ? useAltOnNaCtrs_0_79 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h50 ? useAltOnNaCtrs_0_80 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h51 ? useAltOnNaCtrs_0_81 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h52 ? useAltOnNaCtrs_0_82 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h53 ? useAltOnNaCtrs_0_83 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h54 ? useAltOnNaCtrs_0_84 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h55 ? useAltOnNaCtrs_0_85 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h56 ? useAltOnNaCtrs_0_86 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h57 ? useAltOnNaCtrs_0_87 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h58 ? useAltOnNaCtrs_0_88 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h59 ? useAltOnNaCtrs_0_89 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5A ? useAltOnNaCtrs_0_90 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5B ? useAltOnNaCtrs_0_91 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5C ? useAltOnNaCtrs_0_92 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5D ? useAltOnNaCtrs_0_93 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5E ? useAltOnNaCtrs_0_94 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5F ? useAltOnNaCtrs_0_95 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h60 ? useAltOnNaCtrs_0_96 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h61 ? useAltOnNaCtrs_0_97 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h62 ? useAltOnNaCtrs_0_98 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h63 ? useAltOnNaCtrs_0_99 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h64 ? useAltOnNaCtrs_0_100 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h65 ? useAltOnNaCtrs_0_101 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h66 ? useAltOnNaCtrs_0_102 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h67 ? useAltOnNaCtrs_0_103 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h68 ? useAltOnNaCtrs_0_104 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h69 ? useAltOnNaCtrs_0_105 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6A ? useAltOnNaCtrs_0_106 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6B ? useAltOnNaCtrs_0_107 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6C ? useAltOnNaCtrs_0_108 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6D ? useAltOnNaCtrs_0_109 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6E ? useAltOnNaCtrs_0_110 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6F ? useAltOnNaCtrs_0_111 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h70 ? useAltOnNaCtrs_0_112 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h71 ? useAltOnNaCtrs_0_113 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h72 ? useAltOnNaCtrs_0_114 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h73 ? useAltOnNaCtrs_0_115 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h74 ? useAltOnNaCtrs_0_116 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h75 ? useAltOnNaCtrs_0_117 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h76 ? useAltOnNaCtrs_0_118 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h77 ? useAltOnNaCtrs_0_119 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h78 ? useAltOnNaCtrs_0_120 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h79 ? useAltOnNaCtrs_0_121 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7A ? useAltOnNaCtrs_0_122 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7B ? useAltOnNaCtrs_0_123 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7C ? useAltOnNaCtrs_0_124 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7D ? useAltOnNaCtrs_0_125 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7E ? useAltOnNaCtrs_0_126 : 4'h0) + | ((&(io_update_bits_pc[7:1])) ? useAltOnNaCtrs_0_127 : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :682:17, :736:41 + wire updateAltCorrect = io_update_bits_meta[65] == bUpdateTakens_0; // src/main/scala/xiangshan/frontend/Tage.scala:128:32, :715:33, :726:42 + wire _GEN_65 = + io_update_bits_meta[84] + & (io_update_bits_meta[76:74] == 3'h4 | io_update_bits_meta[76:74] == 3'h3) + & io_update_bits_meta[68]; // src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :618:40, :734:50 + wire _newCtr_T = (&updateUseAltCtr) & updateAltCorrect; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/Tage.scala:726:42 + wire _newCtr_T_2 = updateUseAltCtr == 4'h0 & ~updateAltCorrect; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{26,29}, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :726:42 + wire [3:0] _newCtr_T_3 = 4'(updateUseAltCtr + 4'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/BPU.scala:98:24 + wire [3:0] _newCtr_T_5 = 4'(updateUseAltCtr - 4'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:98:35 + wire [3:0] updateUseAltCtr_1 = + (io_update_bits_pc[7:1] == 7'h0 ? useAltOnNaCtrs_1_0 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1 ? useAltOnNaCtrs_1_1 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2 ? useAltOnNaCtrs_1_2 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3 ? useAltOnNaCtrs_1_3 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4 ? useAltOnNaCtrs_1_4 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5 ? useAltOnNaCtrs_1_5 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6 ? useAltOnNaCtrs_1_6 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7 ? useAltOnNaCtrs_1_7 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h8 ? useAltOnNaCtrs_1_8 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h9 ? useAltOnNaCtrs_1_9 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hA ? useAltOnNaCtrs_1_10 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hB ? useAltOnNaCtrs_1_11 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hC ? useAltOnNaCtrs_1_12 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hD ? useAltOnNaCtrs_1_13 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hE ? useAltOnNaCtrs_1_14 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hF ? useAltOnNaCtrs_1_15 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h10 ? useAltOnNaCtrs_1_16 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h11 ? useAltOnNaCtrs_1_17 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h12 ? useAltOnNaCtrs_1_18 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h13 ? useAltOnNaCtrs_1_19 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h14 ? useAltOnNaCtrs_1_20 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h15 ? useAltOnNaCtrs_1_21 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h16 ? useAltOnNaCtrs_1_22 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h17 ? useAltOnNaCtrs_1_23 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h18 ? useAltOnNaCtrs_1_24 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h19 ? useAltOnNaCtrs_1_25 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1A ? useAltOnNaCtrs_1_26 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1B ? useAltOnNaCtrs_1_27 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1C ? useAltOnNaCtrs_1_28 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1D ? useAltOnNaCtrs_1_29 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1E ? useAltOnNaCtrs_1_30 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1F ? useAltOnNaCtrs_1_31 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h20 ? useAltOnNaCtrs_1_32 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h21 ? useAltOnNaCtrs_1_33 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h22 ? useAltOnNaCtrs_1_34 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h23 ? useAltOnNaCtrs_1_35 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h24 ? useAltOnNaCtrs_1_36 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h25 ? useAltOnNaCtrs_1_37 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h26 ? useAltOnNaCtrs_1_38 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h27 ? useAltOnNaCtrs_1_39 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h28 ? useAltOnNaCtrs_1_40 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h29 ? useAltOnNaCtrs_1_41 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2A ? useAltOnNaCtrs_1_42 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2B ? useAltOnNaCtrs_1_43 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2C ? useAltOnNaCtrs_1_44 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2D ? useAltOnNaCtrs_1_45 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2E ? useAltOnNaCtrs_1_46 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2F ? useAltOnNaCtrs_1_47 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h30 ? useAltOnNaCtrs_1_48 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h31 ? useAltOnNaCtrs_1_49 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h32 ? useAltOnNaCtrs_1_50 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h33 ? useAltOnNaCtrs_1_51 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h34 ? useAltOnNaCtrs_1_52 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h35 ? useAltOnNaCtrs_1_53 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h36 ? useAltOnNaCtrs_1_54 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h37 ? useAltOnNaCtrs_1_55 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h38 ? useAltOnNaCtrs_1_56 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h39 ? useAltOnNaCtrs_1_57 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3A ? useAltOnNaCtrs_1_58 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3B ? useAltOnNaCtrs_1_59 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3C ? useAltOnNaCtrs_1_60 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3D ? useAltOnNaCtrs_1_61 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3E ? useAltOnNaCtrs_1_62 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3F ? useAltOnNaCtrs_1_63 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h40 ? useAltOnNaCtrs_1_64 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h41 ? useAltOnNaCtrs_1_65 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h42 ? useAltOnNaCtrs_1_66 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h43 ? useAltOnNaCtrs_1_67 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h44 ? useAltOnNaCtrs_1_68 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h45 ? useAltOnNaCtrs_1_69 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h46 ? useAltOnNaCtrs_1_70 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h47 ? useAltOnNaCtrs_1_71 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h48 ? useAltOnNaCtrs_1_72 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h49 ? useAltOnNaCtrs_1_73 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4A ? useAltOnNaCtrs_1_74 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4B ? useAltOnNaCtrs_1_75 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4C ? useAltOnNaCtrs_1_76 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4D ? useAltOnNaCtrs_1_77 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4E ? useAltOnNaCtrs_1_78 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4F ? useAltOnNaCtrs_1_79 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h50 ? useAltOnNaCtrs_1_80 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h51 ? useAltOnNaCtrs_1_81 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h52 ? useAltOnNaCtrs_1_82 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h53 ? useAltOnNaCtrs_1_83 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h54 ? useAltOnNaCtrs_1_84 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h55 ? useAltOnNaCtrs_1_85 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h56 ? useAltOnNaCtrs_1_86 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h57 ? useAltOnNaCtrs_1_87 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h58 ? useAltOnNaCtrs_1_88 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h59 ? useAltOnNaCtrs_1_89 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5A ? useAltOnNaCtrs_1_90 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5B ? useAltOnNaCtrs_1_91 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5C ? useAltOnNaCtrs_1_92 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5D ? useAltOnNaCtrs_1_93 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5E ? useAltOnNaCtrs_1_94 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5F ? useAltOnNaCtrs_1_95 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h60 ? useAltOnNaCtrs_1_96 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h61 ? useAltOnNaCtrs_1_97 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h62 ? useAltOnNaCtrs_1_98 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h63 ? useAltOnNaCtrs_1_99 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h64 ? useAltOnNaCtrs_1_100 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h65 ? useAltOnNaCtrs_1_101 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h66 ? useAltOnNaCtrs_1_102 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h67 ? useAltOnNaCtrs_1_103 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h68 ? useAltOnNaCtrs_1_104 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h69 ? useAltOnNaCtrs_1_105 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6A ? useAltOnNaCtrs_1_106 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6B ? useAltOnNaCtrs_1_107 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6C ? useAltOnNaCtrs_1_108 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6D ? useAltOnNaCtrs_1_109 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6E ? useAltOnNaCtrs_1_110 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6F ? useAltOnNaCtrs_1_111 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h70 ? useAltOnNaCtrs_1_112 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h71 ? useAltOnNaCtrs_1_113 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h72 ? useAltOnNaCtrs_1_114 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h73 ? useAltOnNaCtrs_1_115 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h74 ? useAltOnNaCtrs_1_116 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h75 ? useAltOnNaCtrs_1_117 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h76 ? useAltOnNaCtrs_1_118 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h77 ? useAltOnNaCtrs_1_119 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h78 ? useAltOnNaCtrs_1_120 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h79 ? useAltOnNaCtrs_1_121 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7A ? useAltOnNaCtrs_1_122 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7B ? useAltOnNaCtrs_1_123 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7C ? useAltOnNaCtrs_1_124 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7D ? useAltOnNaCtrs_1_125 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7E ? useAltOnNaCtrs_1_126 : 4'h0) + | ((&(io_update_bits_pc[7:1])) ? useAltOnNaCtrs_1_127 : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :682:17, :736:41 + wire updateAltCorrect_1 = io_update_bits_meta[67] == bUpdateTakens_1; // src/main/scala/xiangshan/frontend/Tage.scala:128:32, :715:33, :726:42 + wire _GEN_66 = + io_update_bits_meta[87] + & (io_update_bits_meta[81:79] == 3'h4 | io_update_bits_meta[81:79] == 3'h3) + & io_update_bits_meta[69]; // src/main/scala/xiangshan/frontend/Tage.scala:47:34, :48:34, :50:42, :618:40, :734:50 + wire _newCtr_T_9 = (&updateUseAltCtr_1) & updateAltCorrect_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/Tage.scala:726:42 + wire _newCtr_T_11 = updateUseAltCtr_1 == 4'h0 & ~updateAltCorrect_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{26,29}, src/main/scala/xiangshan/frontend/Tage.scala:682:17, :726:42 + wire [3:0] _newCtr_T_12 = 4'(updateUseAltCtr_1 + 4'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/BPU.scala:98:24 + wire [3:0] _newCtr_T_14 = 4'(updateUseAltCtr_1 - 4'h1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:98:35 + wire [9:0] _sumAbs_T_4 = $signed(sum) < 10'sh0 ? 10'(10'h0 - sum) : sum; // src/main/scala/xiangshan/frontend/SC.scala:240:16, :334:74, :335:26 + wire [9:0] _sumAbs_T_9 = $signed(sum_1) < 10'sh0 ? 10'(10'h0 - sum_1) : sum_1; // src/main/scala/xiangshan/frontend/SC.scala:240:16, :334:74, :335:26 + always @(posedge clock or posedge reset) begin + if (reset) begin + bankTickCtrDistanceToTops_0 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 + bankTickCtrDistanceToTops_1 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 + bankTickCtrs_0 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + bankTickCtrs_1 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + useAltOnNaCtrs_0_0 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_1 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_2 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_3 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_4 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_5 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_6 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_7 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_8 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_9 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_10 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_11 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_12 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_13 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_14 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_15 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_16 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_17 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_18 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_19 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_20 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_21 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_22 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_23 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_24 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_25 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_26 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_27 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_28 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_29 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_30 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_31 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_32 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_33 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_34 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_35 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_36 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_37 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_38 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_39 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_40 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_41 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_42 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_43 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_44 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_45 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_46 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_47 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_48 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_49 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_50 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_51 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_52 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_53 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_54 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_55 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_56 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_57 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_58 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_59 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_60 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_61 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_62 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_63 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_64 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_65 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_66 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_67 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_68 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_69 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_70 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_71 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_72 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_73 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_74 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_75 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_76 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_77 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_78 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_79 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_80 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_81 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_82 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_83 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_84 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_85 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_86 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_87 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_88 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_89 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_90 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_91 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_92 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_93 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_94 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_95 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_96 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_97 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_98 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_99 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_100 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_101 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_102 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_103 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_104 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_105 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_106 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_107 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_108 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_109 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_110 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_111 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_112 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_113 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_114 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_115 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_116 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_117 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_118 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_119 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_120 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_121 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_122 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_123 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_124 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_125 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_126 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_127 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_0 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_1 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_2 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_3 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_4 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_5 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_6 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_7 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_8 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_9 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_10 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_11 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_12 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_13 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_14 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_15 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_16 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_17 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_18 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_19 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_20 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_21 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_22 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_23 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_24 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_25 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_26 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_27 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_28 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_29 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_30 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_31 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_32 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_33 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_34 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_35 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_36 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_37 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_38 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_39 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_40 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_41 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_42 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_43 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_44 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_45 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_46 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_47 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_48 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_49 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_50 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_51 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_52 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_53 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_54 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_55 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_56 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_57 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_58 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_59 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_60 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_61 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_62 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_63 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_64 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_65 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_66 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_67 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_68 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_69 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_70 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_71 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_72 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_73 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_74 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_75 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_76 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_77 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_78 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_79 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_80 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_81 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_82 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_83 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_84 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_85 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_86 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_87 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_88 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_89 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_90 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_91 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_92 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_93 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_94 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_95 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_96 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_97 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_98 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_99 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_100 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_101 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_102 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_103 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_104 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_105 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_106 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_107 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_108 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_109 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_110 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_111 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_112 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_113 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_114 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_115 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_116 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_117 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_118 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_119 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_120 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_121 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_122 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_123 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_124 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_125 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_126 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_127 <= 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + allocLFSR_lfsr <= 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33 + allocLFSR_lfsr_1 <= 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33 + scThresholds_0_ctr <= 5'h10; // src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52 + scThresholds_0_thres <= 8'h6; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scThresholds_1_ctr <= 5'h10; // src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52 + scThresholds_1_thres <= 8'h6; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + end + else begin + if (needToAllocate) begin // src/main/scala/xiangshan/frontend/Tage.scala:770:53 + if (&bankTickCtrs_0) begin // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :816:29 + bankTickCtrDistanceToTops_0 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 + bankTickCtrs_0 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + end + else if (tickInc) begin // src/main/scala/xiangshan/frontend/Tage.scala:778:46 + if (_GEN_51 >= bankTickCtrDistanceToTops_0 & tickInc) begin // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :778:46, :782:{35,67} + bankTickCtrDistanceToTops_0 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45 + bankTickCtrs_0 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45 + end + else begin // src/main/scala/xiangshan/frontend/Tage.scala:782:67 + bankTickCtrDistanceToTops_0 <= 7'(bankTickCtrDistanceToTops_0 - _GEN_51); // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :782:35, :798:72 + bankTickCtrs_0 <= 7'(bankTickCtrs_0 + _GEN_51); // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :782:35, :797:46 + end + end + else if (tickDec) begin // src/main/scala/xiangshan/frontend/Tage.scala:779:42 + if (_GEN_52 >= bankTickCtrs_0 & tickDec) begin // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :779:42, :783:{35,54} + bankTickCtrDistanceToTops_0 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 + bankTickCtrs_0 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + end + else begin // src/main/scala/xiangshan/frontend/Tage.scala:783:54 + bankTickCtrDistanceToTops_0 <= 7'(bankTickCtrDistanceToTops_0 + _GEN_52); // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :783:35, :806:72 + bankTickCtrs_0 <= 7'(bankTickCtrs_0 - _GEN_52); // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :783:35, :805:46 + end + end + end + if (needToAllocate_1) begin // src/main/scala/xiangshan/frontend/Tage.scala:770:53 + if (&bankTickCtrs_1) begin // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :816:29 + bankTickCtrDistanceToTops_1 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 + bankTickCtrs_1 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + end + else if (tickInc_1) begin // src/main/scala/xiangshan/frontend/Tage.scala:778:46 + if (_GEN_61 >= bankTickCtrDistanceToTops_1 & tickInc_1) begin // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :778:46, :782:{35,67} + bankTickCtrDistanceToTops_1 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45 + bankTickCtrs_1 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45 + end + else begin // src/main/scala/xiangshan/frontend/Tage.scala:782:67 + bankTickCtrDistanceToTops_1 <= 7'(bankTickCtrDistanceToTops_1 - _GEN_61); // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :782:35, :798:72 + bankTickCtrs_1 <= 7'(bankTickCtrs_1 + _GEN_61); // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :782:35, :797:46 + end + end + else if (tickDec_1) begin // src/main/scala/xiangshan/frontend/Tage.scala:779:42 + if (_GEN_62 >= bankTickCtrs_1 & tickDec_1) begin // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :779:42, :783:{35,54} + bankTickCtrDistanceToTops_1 <= 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 + bankTickCtrs_1 <= 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + end + else begin // src/main/scala/xiangshan/frontend/Tage.scala:783:54 + bankTickCtrDistanceToTops_1 <= 7'(bankTickCtrDistanceToTops_1 + _GEN_62); // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :783:35, :806:72 + bankTickCtrs_1 <= 7'(bankTickCtrs_1 - _GEN_62); // src/main/scala/xiangshan/frontend/Tage.scala:562:45, :783:35, :805:46 + end + end + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h0) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_0 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_0 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_0 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_0 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_1 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_1 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_1 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_1 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_2 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_2 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_2 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_2 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_3 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_3 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_3 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_3 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_4 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_4 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_4 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_4 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_5 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_5 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_5 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_5 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_6 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_6 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_6 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_6 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h7) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_7 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_7 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_7 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_7 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h8) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_8 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_8 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_8 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_8 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h9) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_9 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_9 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_9 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_9 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'hA) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_10 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_10 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_10 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_10 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'hB) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_11 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_11 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_11 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_11 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'hC) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_12 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_12 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_12 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_12 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'hD) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_13 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_13 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_13 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_13 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'hE) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_14 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_14 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_14 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_14 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'hF) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_15 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_15 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_15 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_15 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h10) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_16 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_16 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_16 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_16 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h11) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_17 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_17 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_17 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_17 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h12) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_18 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_18 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_18 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_18 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h13) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_19 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_19 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_19 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_19 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h14) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_20 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_20 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_20 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_20 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h15) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_21 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_21 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_21 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_21 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h16) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_22 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_22 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_22 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_22 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h17) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_23 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_23 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_23 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_23 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h18) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_24 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_24 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_24 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_24 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h19) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_25 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_25 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_25 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_25 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_26 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_26 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_26 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_26 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_27 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_27 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_27 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_27 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_28 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_28 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_28 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_28 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_29 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_29 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_29 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_29 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_30 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_30 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_30 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_30 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h1F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_31 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_31 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_31 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_31 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h20) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_32 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_32 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_32 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_32 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h21) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_33 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_33 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_33 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_33 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h22) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_34 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_34 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_34 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_34 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h23) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_35 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_35 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_35 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_35 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h24) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_36 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_36 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_36 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_36 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h25) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_37 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_37 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_37 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_37 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h26) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_38 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_38 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_38 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_38 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h27) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_39 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_39 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_39 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_39 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h28) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_40 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_40 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_40 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_40 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h29) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_41 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_41 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_41 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_41 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_42 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_42 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_42 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_42 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_43 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_43 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_43 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_43 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_44 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_44 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_44 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_44 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_45 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_45 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_45 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_45 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_46 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_46 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_46 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_46 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h2F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_47 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_47 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_47 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_47 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h30) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_48 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_48 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_48 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_48 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h31) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_49 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_49 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_49 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_49 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h32) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_50 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_50 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_50 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_50 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h33) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_51 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_51 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_51 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_51 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h34) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_52 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_52 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_52 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_52 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h35) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_53 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_53 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_53 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_53 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h36) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_54 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_54 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_54 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_54 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h37) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_55 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_55 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_55 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_55 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h38) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_56 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_56 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_56 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_56 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h39) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_57 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_57 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_57 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_57 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_58 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_58 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_58 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_58 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_59 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_59 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_59 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_59 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_60 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_60 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_60 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_60 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_61 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_61 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_61 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_61 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_62 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_62 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_62 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_62 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h3F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_63 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_63 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_63 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_63 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h40) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_64 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_64 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_64 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_64 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h41) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_65 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_65 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_65 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_65 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h42) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_66 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_66 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_66 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_66 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h43) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_67 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_67 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_67 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_67 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h44) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_68 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_68 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_68 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_68 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h45) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_69 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_69 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_69 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_69 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h46) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_70 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_70 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_70 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_70 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h47) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_71 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_71 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_71 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_71 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h48) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_72 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_72 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_72 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_72 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h49) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_73 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_73 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_73 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_73 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_74 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_74 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_74 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_74 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_75 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_75 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_75 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_75 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_76 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_76 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_76 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_76 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_77 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_77 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_77 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_77 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_78 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_78 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_78 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_78 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h4F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_79 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_79 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_79 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_79 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h50) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_80 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_80 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_80 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_80 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h51) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_81 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_81 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_81 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_81 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h52) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_82 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_82 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_82 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_82 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h53) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_83 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_83 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_83 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_83 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h54) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_84 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_84 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_84 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_84 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h55) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_85 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_85 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_85 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_85 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h56) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_86 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_86 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_86 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_86 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h57) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_87 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_87 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_87 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_87 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h58) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_88 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_88 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_88 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_88 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h59) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_89 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_89 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_89 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_89 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_90 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_90 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_90 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_90 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_91 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_91 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_91 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_91 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_92 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_92 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_92 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_92 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_93 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_93 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_93 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_93 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_94 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_94 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_94 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_94 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h5F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_95 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_95 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_95 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_95 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h60) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_96 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_96 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_96 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_96 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h61) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_97 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_97 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_97 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_97 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h62) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_98 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_98 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_98 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_98 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h63) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_99 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_99 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_99 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_99 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h64) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_100 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_100 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_100 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_100 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h65) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_101 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_101 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_101 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_101 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h66) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_102 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_102 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_102 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_102 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h67) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_103 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_103 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_103 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_103 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h68) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_104 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_104 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_104 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_104 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h69) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_105 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_105 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_105 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_105 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_106 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_106 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_106 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_106 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_107 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_107 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_107 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_107 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_108 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_108 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_108 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_108 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_109 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_109 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_109 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_109 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_110 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_110 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_110 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_110 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h6F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_111 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_111 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_111 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_111 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h70) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_112 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_112 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_112 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_112 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h71) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_113 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_113 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_113 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_113 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h72) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_114 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_114 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_114 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_114 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h73) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_115 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_115 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_115 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_115 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h74) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_116 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_116 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_116 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_116 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h75) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_117 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_117 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_117 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_117 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h76) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_118 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_118 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_118 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_118 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h77) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_119 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_119 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_119 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_119 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h78) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_120 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_120 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_120 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_120 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h79) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_121 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_121 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_121 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_121 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h7A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_122 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_122 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_122 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_122 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h7B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_123 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_123 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_123 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_123 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h7C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_124 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_124 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_124 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_124 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h7D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_125 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_125 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_125 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_125 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & io_update_bits_pc[7:1] == 7'h7E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_126 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_126 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_126 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_126 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_0 & _GEN_65 & (&(io_update_bits_pc[7:1]))) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:47, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_0_127 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_0_127 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_127 <= _newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_0_127 <= _newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h0) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :562:45, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_0 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_0 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_0 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_0 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_1 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_1 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_1 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_1 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_2 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_2 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_2 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_2 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_3 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_3 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_3 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_3 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_4 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_4 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_4 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_4 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_5 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_5 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_5 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_5 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_6 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_6 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_6 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_6 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h7) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_7 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_7 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_7 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_7 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h8) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_8 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_8 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_8 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_8 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h9) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_9 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_9 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_9 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_9 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'hA) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_10 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_10 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_10 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_10 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'hB) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_11 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_11 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_11 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_11 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'hC) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_12 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_12 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_12 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_12 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'hD) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_13 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_13 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_13 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_13 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'hE) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_14 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_14 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_14 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_14 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'hF) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_15 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_15 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_15 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_15 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h10) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_16 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_16 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_16 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_16 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h11) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_17 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_17 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_17 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_17 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h12) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_18 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_18 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_18 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_18 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h13) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_19 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_19 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_19 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_19 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h14) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_20 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_20 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_20 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_20 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h15) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_21 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_21 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_21 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_21 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h16) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_22 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_22 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_22 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_22 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h17) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_23 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_23 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_23 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_23 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h18) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_24 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_24 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_24 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_24 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h19) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_25 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_25 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_25 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_25 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_26 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_26 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_26 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_26 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_27 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_27 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_27 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_27 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_28 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_28 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_28 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_28 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_29 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_29 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_29 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_29 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_30 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_30 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_30 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_30 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h1F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_31 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_31 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_31 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_31 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h20) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_32 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_32 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_32 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_32 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h21) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_33 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_33 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_33 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_33 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h22) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_34 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_34 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_34 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_34 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h23) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_35 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_35 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_35 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_35 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h24) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_36 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_36 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_36 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_36 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h25) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_37 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_37 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_37 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_37 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h26) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_38 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_38 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_38 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_38 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h27) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_39 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_39 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_39 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_39 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h28) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_40 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_40 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_40 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_40 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h29) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_41 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_41 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_41 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_41 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_42 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_42 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_42 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_42 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_43 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_43 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_43 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_43 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_44 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_44 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_44 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_44 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_45 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_45 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_45 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_45 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_46 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_46 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_46 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_46 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h2F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_47 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_47 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_47 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_47 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h30) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_48 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_48 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_48 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_48 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h31) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_49 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_49 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_49 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_49 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h32) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_50 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_50 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_50 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_50 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h33) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_51 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_51 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_51 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_51 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h34) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_52 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_52 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_52 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_52 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h35) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_53 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_53 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_53 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_53 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h36) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_54 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_54 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_54 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_54 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h37) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_55 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_55 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_55 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_55 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h38) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_56 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_56 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_56 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_56 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h39) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_57 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_57 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_57 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_57 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_58 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_58 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_58 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_58 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_59 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_59 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_59 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_59 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_60 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_60 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_60 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_60 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_61 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_61 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_61 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_61 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_62 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_62 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_62 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_62 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h3F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_63 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_63 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_63 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_63 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h40) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_64 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_64 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_64 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_64 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h41) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_65 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_65 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_65 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_65 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h42) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_66 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_66 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_66 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_66 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h43) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_67 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_67 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_67 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_67 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h44) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_68 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_68 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_68 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_68 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h45) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_69 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_69 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_69 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_69 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h46) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_70 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_70 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_70 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_70 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h47) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_71 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_71 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_71 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_71 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h48) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_72 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_72 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_72 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_72 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h49) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_73 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_73 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_73 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_73 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_74 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_74 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_74 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_74 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_75 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_75 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_75 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_75 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_76 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_76 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_76 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_76 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_77 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_77 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_77 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_77 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_78 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_78 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_78 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_78 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h4F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_79 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_79 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_79 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_79 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h50) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_80 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_80 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_80 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_80 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h51) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_81 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_81 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_81 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_81 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h52) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_82 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_82 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_82 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_82 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h53) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_83 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_83 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_83 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_83 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h54) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_84 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_84 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_84 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_84 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h55) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_85 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_85 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_85 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_85 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h56) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_86 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_86 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_86 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_86 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h57) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_87 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_87 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_87 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_87 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h58) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_88 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_88 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_88 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_88 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h59) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_89 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_89 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_89 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_89 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_90 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_90 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_90 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_90 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_91 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_91 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_91 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_91 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_92 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_92 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_92 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_92 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_93 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_93 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_93 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_93 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_94 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_94 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_94 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_94 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h5F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_95 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_95 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_95 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_95 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h60) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_96 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_96 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_96 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_96 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h61) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_97 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_97 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_97 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_97 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h62) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_98 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_98 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_98 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_98 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h63) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_99 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_99 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_99 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_99 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h64) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_100 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_100 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_100 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_100 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h65) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_101 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_101 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_101 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_101 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h66) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_102 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_102 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_102 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_102 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h67) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_103 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_103 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_103 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_103 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h68) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_104 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_104 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_104 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_104 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h69) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_105 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_105 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_105 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_105 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_106 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_106 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_106 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_106 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_107 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_107 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_107 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_107 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_108 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_108 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_108 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_108 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_109 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_109 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_109 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_109 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_110 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_110 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_110 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_110 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h6F) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_111 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_111 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_111 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_111 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h70) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_112 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_112 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_112 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_112 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h71) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_113 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_113 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_113 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_113 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h72) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_114 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_114 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_114 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_114 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h73) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_115 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_115 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_115 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_115 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h74) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_116 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_116 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_116 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_116 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h75) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_117 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_117 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_117 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_117 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h76) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_118 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_118 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_118 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_118 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h77) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_119 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_119 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_119 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_119 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h78) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_120 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_120 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_120 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_120 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h79) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_121 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_121 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_121 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_121 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h7A) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_122 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_122 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_122 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_122 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h7B) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_123 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_123 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_123 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_123 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h7C) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_124 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_124 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_124 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_124 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h7D) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_125 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_125 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_125 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_125 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & io_update_bits_pc[7:1] == 7'h7E) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_126 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_126 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_126 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_126 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (updateValids_1 & _GEN_66 & (&(io_update_bits_pc[7:1]))) begin // src/main/scala/xiangshan/frontend/Tage.scala:39:{35,53}, :563:31, :614:84, :733:22, :734:{50,71}, :736:41 + if (_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + useAltOnNaCtrs_1_127 <= 4'hF; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + useAltOnNaCtrs_1_127 <= 4'h0; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :682:17 + else if (updateAltCorrect_1) // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_127 <= _newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + else // src/main/scala/xiangshan/frontend/Tage.scala:726:42 + useAltOnNaCtrs_1_127 <= _newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/Tage.scala:563:31 + end + if (allocLFSR_lfsr == 64'h0) // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:24 + allocLFSR_lfsr <= 64'h1; // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:18 + else // utility/src/main/scala/utility/LFSR64.scala:31:24 + allocLFSR_lfsr <= + {allocLFSR_lfsr[0] ^ allocLFSR_lfsr[1] ^ allocLFSR_lfsr[3] ^ allocLFSR_lfsr[4], + allocLFSR_lfsr[63:1]}; // utility/src/main/scala/utility/LFSR64.scala:27:33, :29:{19,29,39,43,49}, :31:{41,51} + if (allocLFSR_lfsr_1 == 64'h0) // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:24 + allocLFSR_lfsr_1 <= 64'h1; // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:18 + else // utility/src/main/scala/utility/LFSR64.scala:31:24 + allocLFSR_lfsr_1 <= + {allocLFSR_lfsr_1[0] ^ allocLFSR_lfsr_1[1] ^ allocLFSR_lfsr_1[3] + ^ allocLFSR_lfsr_1[4], + allocLFSR_lfsr_1[63:1]}; // utility/src/main/scala/utility/LFSR64.scala:27:33, :29:{19,29,39,43,49}, :31:{41,51} + if (_GEN_1 & io_update_bits_meta[48] != io_update_bits_meta[52] + & _sumAbs_T_4 >= {2'h0, 8'(scThresholds_0_thres - 8'h4)} + & _sumAbs_T_4 <= {2'h0, 8'(scThresholds_0_thres - 8'h2)}) begin // src/main/scala/xiangshan/frontend/SC.scala:229:52, :328:{29,56}, :335:26, :346:38, :351:{45,54,70,79,86}, :353:27, src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26 + if ((&newThres_newCtr) | _newThres_res_ctr_T_4) // src/main/scala/xiangshan/frontend/BPU.scala:96:8, src/main/scala/xiangshan/frontend/SC.scala:181:42, :182:42, :195:39 + scThresholds_0_ctr <= 5'h10; // src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52 + else if (_newThres_newCtr_T) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + scThresholds_0_ctr <= 5'h1F; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/SC.scala:229:52 + else if (_newThres_newCtr_T_2) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + scThresholds_0_ctr <= 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/SC.scala:229:52 + else if (_GEN_63) // src/main/scala/xiangshan/frontend/BPU.scala:98:12, src/main/scala/xiangshan/frontend/SC.scala:348:40 + scThresholds_0_ctr <= _newThres_newCtr_T_5; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/SC.scala:229:52 + else // src/main/scala/xiangshan/frontend/BPU.scala:98:12, src/main/scala/xiangshan/frontend/SC.scala:348:40 + scThresholds_0_ctr <= _newThres_newCtr_T_3; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/SC.scala:229:52 + if ((&newThres_newCtr) & scThresholds_0_thres < 8'h20) // src/main/scala/xiangshan/frontend/BPU.scala:96:8, src/main/scala/xiangshan/frontend/SC.scala:181:42, :191:{43,57}, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scThresholds_0_thres <= 8'(scThresholds_0_thres + 8'h2); // src/main/scala/xiangshan/frontend/SC.scala:191:81, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + else if (_newThres_res_ctr_T_4 & scThresholds_0_thres > 8'h5) // src/main/scala/xiangshan/frontend/SC.scala:182:42, :192:{46,60}, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scThresholds_0_thres <= 8'(scThresholds_0_thres - 8'h2); // src/main/scala/xiangshan/frontend/SC.scala:192:84, :229:52 + end + if (_GEN_2 & io_update_bits_meta[49] != io_update_bits_meta[53] + & _sumAbs_T_9 >= {2'h0, 8'(scThresholds_1_thres - 8'h4)} + & _sumAbs_T_9 <= {2'h0, 8'(scThresholds_1_thres - 8'h2)}) begin // src/main/scala/xiangshan/frontend/SC.scala:229:52, :328:{29,56}, :335:26, :346:38, :351:{45,54,70,79,86}, :353:27, src/main/scala/xiangshan/frontend/Tage.scala:618:40, :652:26 + if ((&newThres_newCtr_1) | _newThres_res_ctr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:96:8, src/main/scala/xiangshan/frontend/SC.scala:181:42, :182:42, :195:39 + scThresholds_1_ctr <= 5'h10; // src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52 + else if (_newThres_newCtr_T_9) // src/main/scala/xiangshan/frontend/BPU.scala:96:21 + scThresholds_1_ctr <= 5'h1F; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/SC.scala:229:52 + else if (_newThres_newCtr_T_11) // src/main/scala/xiangshan/frontend/BPU.scala:97:26 + scThresholds_1_ctr <= 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/SC.scala:229:52 + else if (_GEN_64) // src/main/scala/xiangshan/frontend/BPU.scala:98:12, src/main/scala/xiangshan/frontend/SC.scala:348:40 + scThresholds_1_ctr <= _newThres_newCtr_T_14; // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/SC.scala:229:52 + else // src/main/scala/xiangshan/frontend/BPU.scala:98:12, src/main/scala/xiangshan/frontend/SC.scala:348:40 + scThresholds_1_ctr <= _newThres_newCtr_T_12; // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/SC.scala:229:52 + if ((&newThres_newCtr_1) & scThresholds_1_thres < 8'h20) // src/main/scala/xiangshan/frontend/BPU.scala:96:8, src/main/scala/xiangshan/frontend/SC.scala:181:42, :191:{43,57}, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scThresholds_1_thres <= 8'(scThresholds_1_thres + 8'h2); // src/main/scala/xiangshan/frontend/SC.scala:191:81, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + else if (_newThres_res_ctr_T_11 & scThresholds_1_thres > 8'h5) // src/main/scala/xiangshan/frontend/SC.scala:182:42, :192:{46,60}, :229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scThresholds_1_thres <= 8'(scThresholds_1_thres - 8'h2); // src/main/scala/xiangshan/frontend/SC.scala:192:84, :229:52 + end + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:231]; // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + initial begin // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + for (logic [7:0] i = 8'h0; i < 8'hE8; i += 8'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + end // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s1_pc_dup_0 = {_RANDOM[8'h0], _RANDOM[8'h1][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + REG = _RANDOM[8'hE][20]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + REG_1 = _RANDOM[8'hE][21]; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24}, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + bankTickCtrDistanceToTops_0 = _RANDOM[8'hE][28:22]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/Tage.scala:561:58, :924:7 + bankTickCtrDistanceToTops_1 = {_RANDOM[8'hE][31:29], _RANDOM[8'hF][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/Tage.scala:561:58, :924:7 + bankTickCtrs_0 = _RANDOM[8'hF][10:4]; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45, :924:7 + bankTickCtrs_1 = _RANDOM[8'hF][17:11]; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :562:45, :924:7 + useAltOnNaCtrs_0_0 = _RANDOM[8'hF][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :563:31, :924:7 + useAltOnNaCtrs_0_1 = _RANDOM[8'hF][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :563:31, :924:7 + useAltOnNaCtrs_0_2 = _RANDOM[8'hF][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :563:31, :924:7 + useAltOnNaCtrs_0_3 = {_RANDOM[8'hF][31:30], _RANDOM[8'h10][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:561:58, :563:31, :924:7 + useAltOnNaCtrs_0_4 = _RANDOM[8'h10][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_5 = _RANDOM[8'h10][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_6 = _RANDOM[8'h10][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_7 = _RANDOM[8'h10][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_8 = _RANDOM[8'h10][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_9 = _RANDOM[8'h10][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_10 = _RANDOM[8'h10][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_11 = {_RANDOM[8'h10][31:30], _RANDOM[8'h11][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_12 = _RANDOM[8'h11][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_13 = _RANDOM[8'h11][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_14 = _RANDOM[8'h11][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_15 = _RANDOM[8'h11][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_16 = _RANDOM[8'h11][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_17 = _RANDOM[8'h11][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_18 = _RANDOM[8'h11][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_19 = {_RANDOM[8'h11][31:30], _RANDOM[8'h12][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_20 = _RANDOM[8'h12][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_21 = _RANDOM[8'h12][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_22 = _RANDOM[8'h12][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_23 = _RANDOM[8'h12][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_24 = _RANDOM[8'h12][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_25 = _RANDOM[8'h12][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_26 = _RANDOM[8'h12][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_27 = {_RANDOM[8'h12][31:30], _RANDOM[8'h13][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_28 = _RANDOM[8'h13][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_29 = _RANDOM[8'h13][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_30 = _RANDOM[8'h13][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_31 = _RANDOM[8'h13][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_32 = _RANDOM[8'h13][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_33 = _RANDOM[8'h13][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_34 = _RANDOM[8'h13][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_35 = {_RANDOM[8'h13][31:30], _RANDOM[8'h14][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_36 = _RANDOM[8'h14][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_37 = _RANDOM[8'h14][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_38 = _RANDOM[8'h14][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_39 = _RANDOM[8'h14][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_40 = _RANDOM[8'h14][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_41 = _RANDOM[8'h14][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_42 = _RANDOM[8'h14][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_43 = {_RANDOM[8'h14][31:30], _RANDOM[8'h15][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_44 = _RANDOM[8'h15][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_45 = _RANDOM[8'h15][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_46 = _RANDOM[8'h15][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_47 = _RANDOM[8'h15][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_48 = _RANDOM[8'h15][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_49 = _RANDOM[8'h15][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_50 = _RANDOM[8'h15][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_51 = {_RANDOM[8'h15][31:30], _RANDOM[8'h16][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_52 = _RANDOM[8'h16][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_53 = _RANDOM[8'h16][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_54 = _RANDOM[8'h16][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_55 = _RANDOM[8'h16][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_56 = _RANDOM[8'h16][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_57 = _RANDOM[8'h16][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_58 = _RANDOM[8'h16][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_59 = {_RANDOM[8'h16][31:30], _RANDOM[8'h17][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_60 = _RANDOM[8'h17][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_61 = _RANDOM[8'h17][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_62 = _RANDOM[8'h17][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_63 = _RANDOM[8'h17][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_64 = _RANDOM[8'h17][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_65 = _RANDOM[8'h17][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_66 = _RANDOM[8'h17][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_67 = {_RANDOM[8'h17][31:30], _RANDOM[8'h18][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_68 = _RANDOM[8'h18][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_69 = _RANDOM[8'h18][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_70 = _RANDOM[8'h18][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_71 = _RANDOM[8'h18][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_72 = _RANDOM[8'h18][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_73 = _RANDOM[8'h18][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_74 = _RANDOM[8'h18][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_75 = {_RANDOM[8'h18][31:30], _RANDOM[8'h19][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_76 = _RANDOM[8'h19][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_77 = _RANDOM[8'h19][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_78 = _RANDOM[8'h19][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_79 = _RANDOM[8'h19][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_80 = _RANDOM[8'h19][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_81 = _RANDOM[8'h19][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_82 = _RANDOM[8'h19][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_83 = {_RANDOM[8'h19][31:30], _RANDOM[8'h1A][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_84 = _RANDOM[8'h1A][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_85 = _RANDOM[8'h1A][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_86 = _RANDOM[8'h1A][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_87 = _RANDOM[8'h1A][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_88 = _RANDOM[8'h1A][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_89 = _RANDOM[8'h1A][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_90 = _RANDOM[8'h1A][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_91 = {_RANDOM[8'h1A][31:30], _RANDOM[8'h1B][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_92 = _RANDOM[8'h1B][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_93 = _RANDOM[8'h1B][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_94 = _RANDOM[8'h1B][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_95 = _RANDOM[8'h1B][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_96 = _RANDOM[8'h1B][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_97 = _RANDOM[8'h1B][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_98 = _RANDOM[8'h1B][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_99 = {_RANDOM[8'h1B][31:30], _RANDOM[8'h1C][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_100 = _RANDOM[8'h1C][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_101 = _RANDOM[8'h1C][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_102 = _RANDOM[8'h1C][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_103 = _RANDOM[8'h1C][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_104 = _RANDOM[8'h1C][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_105 = _RANDOM[8'h1C][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_106 = _RANDOM[8'h1C][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_107 = {_RANDOM[8'h1C][31:30], _RANDOM[8'h1D][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_108 = _RANDOM[8'h1D][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_109 = _RANDOM[8'h1D][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_110 = _RANDOM[8'h1D][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_111 = _RANDOM[8'h1D][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_112 = _RANDOM[8'h1D][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_113 = _RANDOM[8'h1D][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_114 = _RANDOM[8'h1D][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_115 = {_RANDOM[8'h1D][31:30], _RANDOM[8'h1E][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_116 = _RANDOM[8'h1E][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_117 = _RANDOM[8'h1E][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_118 = _RANDOM[8'h1E][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_119 = _RANDOM[8'h1E][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_120 = _RANDOM[8'h1E][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_121 = _RANDOM[8'h1E][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_122 = _RANDOM[8'h1E][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_123 = {_RANDOM[8'h1E][31:30], _RANDOM[8'h1F][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_124 = _RANDOM[8'h1F][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_125 = _RANDOM[8'h1F][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_126 = _RANDOM[8'h1F][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_0_127 = _RANDOM[8'h1F][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_0 = _RANDOM[8'h1F][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_1 = _RANDOM[8'h1F][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_2 = _RANDOM[8'h1F][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_3 = {_RANDOM[8'h1F][31:30], _RANDOM[8'h20][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_4 = _RANDOM[8'h20][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_5 = _RANDOM[8'h20][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_6 = _RANDOM[8'h20][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_7 = _RANDOM[8'h20][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_8 = _RANDOM[8'h20][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_9 = _RANDOM[8'h20][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_10 = _RANDOM[8'h20][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_11 = {_RANDOM[8'h20][31:30], _RANDOM[8'h21][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_12 = _RANDOM[8'h21][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_13 = _RANDOM[8'h21][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_14 = _RANDOM[8'h21][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_15 = _RANDOM[8'h21][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_16 = _RANDOM[8'h21][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_17 = _RANDOM[8'h21][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_18 = _RANDOM[8'h21][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_19 = {_RANDOM[8'h21][31:30], _RANDOM[8'h22][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_20 = _RANDOM[8'h22][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_21 = _RANDOM[8'h22][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_22 = _RANDOM[8'h22][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_23 = _RANDOM[8'h22][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_24 = _RANDOM[8'h22][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_25 = _RANDOM[8'h22][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_26 = _RANDOM[8'h22][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_27 = {_RANDOM[8'h22][31:30], _RANDOM[8'h23][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_28 = _RANDOM[8'h23][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_29 = _RANDOM[8'h23][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_30 = _RANDOM[8'h23][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_31 = _RANDOM[8'h23][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_32 = _RANDOM[8'h23][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_33 = _RANDOM[8'h23][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_34 = _RANDOM[8'h23][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_35 = {_RANDOM[8'h23][31:30], _RANDOM[8'h24][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_36 = _RANDOM[8'h24][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_37 = _RANDOM[8'h24][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_38 = _RANDOM[8'h24][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_39 = _RANDOM[8'h24][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_40 = _RANDOM[8'h24][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_41 = _RANDOM[8'h24][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_42 = _RANDOM[8'h24][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_43 = {_RANDOM[8'h24][31:30], _RANDOM[8'h25][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_44 = _RANDOM[8'h25][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_45 = _RANDOM[8'h25][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_46 = _RANDOM[8'h25][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_47 = _RANDOM[8'h25][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_48 = _RANDOM[8'h25][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_49 = _RANDOM[8'h25][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_50 = _RANDOM[8'h25][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_51 = {_RANDOM[8'h25][31:30], _RANDOM[8'h26][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_52 = _RANDOM[8'h26][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_53 = _RANDOM[8'h26][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_54 = _RANDOM[8'h26][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_55 = _RANDOM[8'h26][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_56 = _RANDOM[8'h26][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_57 = _RANDOM[8'h26][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_58 = _RANDOM[8'h26][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_59 = {_RANDOM[8'h26][31:30], _RANDOM[8'h27][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_60 = _RANDOM[8'h27][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_61 = _RANDOM[8'h27][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_62 = _RANDOM[8'h27][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_63 = _RANDOM[8'h27][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_64 = _RANDOM[8'h27][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_65 = _RANDOM[8'h27][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_66 = _RANDOM[8'h27][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_67 = {_RANDOM[8'h27][31:30], _RANDOM[8'h28][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_68 = _RANDOM[8'h28][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_69 = _RANDOM[8'h28][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_70 = _RANDOM[8'h28][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_71 = _RANDOM[8'h28][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_72 = _RANDOM[8'h28][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_73 = _RANDOM[8'h28][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_74 = _RANDOM[8'h28][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_75 = {_RANDOM[8'h28][31:30], _RANDOM[8'h29][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_76 = _RANDOM[8'h29][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_77 = _RANDOM[8'h29][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_78 = _RANDOM[8'h29][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_79 = _RANDOM[8'h29][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_80 = _RANDOM[8'h29][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_81 = _RANDOM[8'h29][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_82 = _RANDOM[8'h29][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_83 = {_RANDOM[8'h29][31:30], _RANDOM[8'h2A][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_84 = _RANDOM[8'h2A][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_85 = _RANDOM[8'h2A][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_86 = _RANDOM[8'h2A][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_87 = _RANDOM[8'h2A][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_88 = _RANDOM[8'h2A][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_89 = _RANDOM[8'h2A][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_90 = _RANDOM[8'h2A][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_91 = {_RANDOM[8'h2A][31:30], _RANDOM[8'h2B][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_92 = _RANDOM[8'h2B][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_93 = _RANDOM[8'h2B][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_94 = _RANDOM[8'h2B][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_95 = _RANDOM[8'h2B][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_96 = _RANDOM[8'h2B][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_97 = _RANDOM[8'h2B][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_98 = _RANDOM[8'h2B][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_99 = {_RANDOM[8'h2B][31:30], _RANDOM[8'h2C][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_100 = _RANDOM[8'h2C][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_101 = _RANDOM[8'h2C][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_102 = _RANDOM[8'h2C][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_103 = _RANDOM[8'h2C][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_104 = _RANDOM[8'h2C][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_105 = _RANDOM[8'h2C][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_106 = _RANDOM[8'h2C][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_107 = {_RANDOM[8'h2C][31:30], _RANDOM[8'h2D][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_108 = _RANDOM[8'h2D][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_109 = _RANDOM[8'h2D][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_110 = _RANDOM[8'h2D][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_111 = _RANDOM[8'h2D][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_112 = _RANDOM[8'h2D][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_113 = _RANDOM[8'h2D][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_114 = _RANDOM[8'h2D][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_115 = {_RANDOM[8'h2D][31:30], _RANDOM[8'h2E][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_116 = _RANDOM[8'h2E][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_117 = _RANDOM[8'h2E][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_118 = _RANDOM[8'h2E][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_119 = _RANDOM[8'h2E][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_120 = _RANDOM[8'h2E][21:18]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_121 = _RANDOM[8'h2E][25:22]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_122 = _RANDOM[8'h2E][29:26]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_123 = {_RANDOM[8'h2E][31:30], _RANDOM[8'h2F][1:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_124 = _RANDOM[8'h2F][5:2]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_125 = _RANDOM[8'h2F][9:6]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_126 = _RANDOM[8'h2F][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + useAltOnNaCtrs_1_127 = _RANDOM[8'h2F][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :924:7 + s2_provideds_0 = _RANDOM[8'h32][0]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :924:7 + s2_provideds_1 = _RANDOM[8'h32][1]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :924:7 + s2_providers_0 = _RANDOM[8'h32][3:2]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :594:38, :924:7 + s2_providers_1 = _RANDOM[8'h32][5:4]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :594:38, :924:7 + s2_providerResps_0_ctr = _RANDOM[8'h32][8:6]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :595:38, :924:7 + s2_providerResps_0_u = _RANDOM[8'h32][9]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :595:38, :924:7 + s2_providerResps_0_unconf = _RANDOM[8'h32][10]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :595:38, :924:7 + s2_providerResps_1_ctr = _RANDOM[8'h32][13:11]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :595:38, :924:7 + s2_providerResps_1_u = _RANDOM[8'h32][14]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :595:38, :924:7 + s2_providerResps_1_unconf = _RANDOM[8'h32][15]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :595:38, :924:7 + s2_altUsed_0 = _RANDOM[8'h32][16]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :599:38, :924:7 + s2_altUsed_1 = _RANDOM[8'h32][17]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :599:38, :924:7 + s2_tageTakens_dup_0_0 = _RANDOM[8'h32][18]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 + s2_tageTakens_dup_0_1 = _RANDOM[8'h32][19]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 + s2_tageTakens_dup_1_0 = _RANDOM[8'h32][20]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 + s2_tageTakens_dup_1_1 = _RANDOM[8'h32][21]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 + s2_tageTakens_dup_2_0 = _RANDOM[8'h32][22]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 + s2_tageTakens_dup_2_1 = _RANDOM[8'h32][23]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 + s2_tageTakens_dup_3_0 = _RANDOM[8'h32][24]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 + s2_tageTakens_dup_3_1 = _RANDOM[8'h32][25]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :600:58, :924:7 + s2_finalAltPreds_0 = _RANDOM[8'h32][26]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :601:38, :924:7 + s2_finalAltPreds_1 = _RANDOM[8'h32][27]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :601:38, :924:7 + s2_basecnts_0 = _RANDOM[8'h32][29:28]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :602:38, :924:7 + s2_basecnts_1 = _RANDOM[8'h32][31:30]; // src/main/scala/xiangshan/frontend/Tage.scala:593:38, :602:38, :924:7 + resp_meta_providers_0_valid_r = _RANDOM[8'h33][2]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :924:7 + resp_meta_providers_0_bits_r = _RANDOM[8'h33][4:3]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :668:49, :924:7 + resp_meta_providerResps_0_r_ctr = _RANDOM[8'h33][7:5]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :669:49, :924:7 + resp_meta_providerResps_0_r_u = _RANDOM[8'h33][8]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :669:49, :924:7 + resp_meta_providerResps_0_r_unconf = _RANDOM[8'h33][9]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :669:49, :924:7 + allocatableSlots = _RANDOM[8'h33][13:10]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :679:16, :924:7 + resp_meta_allocates_0_r = _RANDOM[8'h33][17:14]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :686:40, :924:7 + resp_meta_altUsed_0_r = _RANDOM[8'h33][18]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :699:41, :924:7 + resp_meta_altDiffers_0_r = _RANDOM[8'h33][19]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :700:41, :924:7 + resp_meta_takens_0_r = _RANDOM[8'h33][20]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :702:41, :924:7 + resp_meta_basecnts_0_r = _RANDOM[8'h33][22:21]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :703:41, :924:7 + tage_enable_dup_REG = _RANDOM[8'h33][23]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :705:38, :924:7 + allocLFSR_lfsr = {_RANDOM[8'h33][31:24], _RANDOM[8'h34], _RANDOM[8'h35][23:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + resp_meta_providers_1_valid_r = _RANDOM[8'h35][24]; // src/main/scala/xiangshan/frontend/Tage.scala:667:49, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + resp_meta_providers_1_bits_r = _RANDOM[8'h35][26:25]; // src/main/scala/xiangshan/frontend/Tage.scala:668:49, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + resp_meta_providerResps_1_r_ctr = _RANDOM[8'h35][29:27]; // src/main/scala/xiangshan/frontend/Tage.scala:669:49, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + resp_meta_providerResps_1_r_u = _RANDOM[8'h35][30]; // src/main/scala/xiangshan/frontend/Tage.scala:669:49, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + resp_meta_providerResps_1_r_unconf = _RANDOM[8'h35][31]; // src/main/scala/xiangshan/frontend/Tage.scala:669:49, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + allocatableSlots_1 = _RANDOM[8'h36][3:0]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :924:7 + resp_meta_allocates_1_r = _RANDOM[8'h36][7:4]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :686:40, :924:7 + resp_meta_altUsed_1_r = _RANDOM[8'h36][8]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :699:41, :924:7 + resp_meta_altDiffers_1_r = _RANDOM[8'h36][9]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :700:41, :924:7 + resp_meta_takens_1_r = _RANDOM[8'h36][10]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :702:41, :924:7 + resp_meta_basecnts_1_r = _RANDOM[8'h36][12:11]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :703:41, :924:7 + tage_enable_dup_REG_1 = _RANDOM[8'h36][13]; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :705:38, :924:7 + allocLFSR_lfsr_1 = {_RANDOM[8'h36][31:14], _RANDOM[8'h37], _RANDOM[8'h38][13:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:679:16, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + tables_0_io_update_mask_0_REG = _RANDOM[8'h38][14]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + tables_0_io_update_takens_0_REG = _RANDOM[8'h38][15]; // src/main/scala/xiangshan/frontend/Tage.scala:835:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + tables_0_io_update_alloc_0_REG = _RANDOM[8'h38][16]; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + tables_0_io_update_oldCtrs_0_REG = _RANDOM[8'h38][19:17]; // src/main/scala/xiangshan/frontend/Tage.scala:837:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + tables_0_io_update_uMask_0_REG = _RANDOM[8'h38][20]; // src/main/scala/xiangshan/frontend/Tage.scala:839:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + tables_0_io_update_us_0_REG = _RANDOM[8'h38][21]; // src/main/scala/xiangshan/frontend/Tage.scala:840:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + tables_0_io_update_reset_u_0_REG = _RANDOM[8'h38][22]; // src/main/scala/xiangshan/frontend/Tage.scala:841:48, :924:7, utility/src/main/scala/utility/LFSR64.scala:27:33 + tables_1_io_update_mask_0_REG = _RANDOM[8'h46][18]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 + tables_1_io_update_takens_0_REG = _RANDOM[8'h46][19]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 + tables_1_io_update_alloc_0_REG = _RANDOM[8'h46][20]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :836:48, :924:7 + tables_1_io_update_oldCtrs_0_REG = _RANDOM[8'h46][23:21]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :837:48, :924:7 + tables_1_io_update_uMask_0_REG = _RANDOM[8'h46][24]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :839:48, :924:7 + tables_1_io_update_us_0_REG = _RANDOM[8'h46][25]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :840:48, :924:7 + tables_1_io_update_reset_u_0_REG = _RANDOM[8'h46][26]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :841:48, :924:7 + tables_2_io_update_mask_0_REG = _RANDOM[8'h54][22]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 + tables_2_io_update_takens_0_REG = _RANDOM[8'h54][23]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 + tables_2_io_update_alloc_0_REG = _RANDOM[8'h54][24]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :836:48, :924:7 + tables_2_io_update_oldCtrs_0_REG = _RANDOM[8'h54][27:25]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :837:48, :924:7 + tables_2_io_update_uMask_0_REG = _RANDOM[8'h54][28]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :839:48, :924:7 + tables_2_io_update_us_0_REG = _RANDOM[8'h54][29]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :840:48, :924:7 + tables_2_io_update_reset_u_0_REG = _RANDOM[8'h54][30]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :841:48, :924:7 + tables_3_io_update_mask_0_REG = _RANDOM[8'h62][26]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 + tables_3_io_update_takens_0_REG = _RANDOM[8'h62][27]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 + tables_3_io_update_alloc_0_REG = _RANDOM[8'h62][28]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :836:48, :924:7 + tables_3_io_update_oldCtrs_0_REG = _RANDOM[8'h62][31:29]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :837:48, :924:7 + tables_3_io_update_uMask_0_REG = _RANDOM[8'h63][0]; // src/main/scala/xiangshan/frontend/Tage.scala:839:48, :924:7 + tables_3_io_update_us_0_REG = _RANDOM[8'h63][1]; // src/main/scala/xiangshan/frontend/Tage.scala:839:48, :840:48, :924:7 + tables_3_io_update_reset_u_0_REG = _RANDOM[8'h63][2]; // src/main/scala/xiangshan/frontend/Tage.scala:839:48, :841:48, :924:7 + tables_0_io_update_mask_1_REG = _RANDOM[8'h70][30]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 + tables_0_io_update_takens_1_REG = _RANDOM[8'h70][31]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 + tables_0_io_update_alloc_1_REG = _RANDOM[8'h71][0]; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :924:7 + tables_0_io_update_oldCtrs_1_REG = _RANDOM[8'h71][3:1]; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :837:48, :924:7 + tables_0_io_update_uMask_1_REG = _RANDOM[8'h71][4]; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :839:48, :924:7 + tables_0_io_update_us_1_REG = _RANDOM[8'h71][5]; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :840:48, :924:7 + tables_0_io_update_reset_u_1_REG = _RANDOM[8'h71][6]; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :841:48, :924:7 + tables_0_io_update_pc_REG_1 = {_RANDOM[8'h71][31:7], _RANDOM[8'h72][13:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:836:48, :843:46, :924:7 + tables_0_io_update_folded_hist_REG_1_hist_14_folded_hist = _RANDOM[8'h73][18:11]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 + tables_0_io_update_folded_hist_REG_1_hist_7_folded_hist = _RANDOM[8'h75][6:0]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 + tables_1_io_update_mask_1_REG = _RANDOM[8'h7F][2]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 + tables_1_io_update_takens_1_REG = _RANDOM[8'h7F][3]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 + tables_1_io_update_alloc_1_REG = _RANDOM[8'h7F][4]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :836:48, :924:7 + tables_1_io_update_oldCtrs_1_REG = _RANDOM[8'h7F][7:5]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :837:48, :924:7 + tables_1_io_update_uMask_1_REG = _RANDOM[8'h7F][8]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :839:48, :924:7 + tables_1_io_update_us_1_REG = _RANDOM[8'h7F][9]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :840:48, :924:7 + tables_1_io_update_reset_u_1_REG = _RANDOM[8'h7F][10]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :841:48, :924:7 + tables_1_io_update_pc_REG_1 = {_RANDOM[8'h7F][31:11], _RANDOM[8'h80][17:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :843:46, :924:7 + tables_1_io_update_folded_hist_REG_1_hist_15_folded_hist = _RANDOM[8'h81][14:8]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 + tables_1_io_update_folded_hist_REG_1_hist_4_folded_hist = + {_RANDOM[8'h83][31:27], _RANDOM[8'h84][2:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 + tables_1_io_update_folded_hist_REG_1_hist_1_folded_hist = _RANDOM[8'h84][29:19]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 + tables_2_io_update_mask_1_REG = _RANDOM[8'h8D][6]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 + tables_2_io_update_takens_1_REG = _RANDOM[8'h8D][7]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 + tables_2_io_update_alloc_1_REG = _RANDOM[8'h8D][8]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :836:48, :924:7 + tables_2_io_update_oldCtrs_1_REG = _RANDOM[8'h8D][11:9]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :837:48, :924:7 + tables_2_io_update_uMask_1_REG = _RANDOM[8'h8D][12]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :839:48, :924:7 + tables_2_io_update_us_1_REG = _RANDOM[8'h8D][13]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :840:48, :924:7 + tables_2_io_update_reset_u_1_REG = _RANDOM[8'h8D][14]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :841:48, :924:7 + tables_2_io_update_pc_REG_1 = {_RANDOM[8'h8D][31:15], _RANDOM[8'h8E][21:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :843:46, :924:7 + tables_2_io_update_folded_hist_REG_1_hist_17_folded_hist = + {_RANDOM[8'h8E][31:22], _RANDOM[8'h8F][0]}; // src/main/scala/xiangshan/frontend/Tage.scala:843:46, :844:49, :924:7 + tables_2_io_update_folded_hist_REG_1_hist_9_folded_hist = _RANDOM[8'h90][31:25]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 + tables_2_io_update_folded_hist_REG_1_hist_3_folded_hist = _RANDOM[8'h92][14:7]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 + tables_3_io_update_mask_1_REG = _RANDOM[8'h9B][10]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :924:7 + tables_3_io_update_takens_1_REG = _RANDOM[8'h9B][11]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :835:48, :924:7 + tables_3_io_update_alloc_1_REG = _RANDOM[8'h9B][12]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :836:48, :924:7 + tables_3_io_update_oldCtrs_1_REG = _RANDOM[8'h9B][15:13]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :837:48, :924:7 + tables_3_io_update_uMask_1_REG = _RANDOM[8'h9B][16]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :839:48, :924:7 + tables_3_io_update_us_1_REG = _RANDOM[8'h9B][17]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :840:48, :924:7 + tables_3_io_update_reset_u_1_REG = _RANDOM[8'h9B][18]; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :841:48, :924:7 + tables_3_io_update_pc_REG_1 = {_RANDOM[8'h9B][31:19], _RANDOM[8'h9C][25:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:834:48, :843:46, :924:7 + tables_3_io_update_folded_hist_REG_1_hist_16_folded_hist = _RANDOM[8'h9D][15:5]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 + tables_3_io_update_folded_hist_REG_1_hist_8_folded_hist = _RANDOM[8'h9F][11:4]; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 + tables_3_io_update_folded_hist_REG_1_hist_5_folded_hist = + {_RANDOM[8'h9F][31:28], _RANDOM[8'hA0][2:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:844:49, :924:7 + REG_2_0 = _RANDOM[8'hA9][14]; // src/main/scala/xiangshan/frontend/Tage.scala:848:31, :924:7 + REG_2_1 = _RANDOM[8'hA9][15]; // src/main/scala/xiangshan/frontend/Tage.scala:848:31, :924:7 + REG_3_0 = _RANDOM[8'hA9][17:16]; // src/main/scala/xiangshan/frontend/Tage.scala:848:31, :849:30, :924:7 + REG_3_1 = _RANDOM[8'hA9][19:18]; // src/main/scala/xiangshan/frontend/Tage.scala:848:31, :849:30, :924:7 + bt_io_update_pc_REG = {_RANDOM[8'hA9][31:20], _RANDOM[8'hAA][26:0]}; // src/main/scala/xiangshan/frontend/Tage.scala:848:31, :850:29, :924:7 + REG_4_0 = _RANDOM[8'hAA][27]; // src/main/scala/xiangshan/frontend/Tage.scala:850:29, :851:33, :924:7 + REG_4_1 = _RANDOM[8'hAA][28]; // src/main/scala/xiangshan/frontend/Tage.scala:850:29, :851:33, :924:7 + scThresholds_0_ctr = _RANDOM[8'hAC][17:13]; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scThresholds_0_thres = _RANDOM[8'hAC][25:18]; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scThresholds_1_ctr = _RANDOM[8'hAC][30:26]; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scThresholds_1_thres = {_RANDOM[8'hAC][31], _RANDOM[8'hAD][6:0]}; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scTableSums_0 = _RANDOM[8'hAD][15:7]; // src/main/scala/xiangshan/frontend/SC.scala:229:52, :277:37, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scTableSums_1 = _RANDOM[8'hAD][24:16]; // src/main/scala/xiangshan/frontend/SC.scala:229:52, :277:37, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_tagePrvdCtrCentered_r = _RANDOM[8'hAD][27:25]; // src/main/scala/xiangshan/frontend/SC.scala:229:52, :278:61, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_0_ctrs_0_0 = {_RANDOM[8'hAD][31:28], _RANDOM[8'hAE][1:0]}; // src/main/scala/xiangshan/frontend/SC.scala:229:52, :283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_0_ctrs_0_1 = _RANDOM[8'hAE][7:2]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_1_ctrs_0_0 = _RANDOM[8'hAE][25:20]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_1_ctrs_0_1 = _RANDOM[8'hAE][31:26]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_2_ctrs_0_0 = _RANDOM[8'hAF][17:12]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_2_ctrs_0_1 = _RANDOM[8'hAF][23:18]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_3_ctrs_0_0 = _RANDOM[8'hB0][9:4]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_3_ctrs_0_1 = _RANDOM[8'hB0][15:10]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + resp_meta_scMeta_tageTakens_0_r = _RANDOM[8'hB0][30]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :296:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + resp_meta_scMeta_scUsed_0_r = _RANDOM[8'hB0][31]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :297:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + resp_meta_scMeta_scPreds_0_r = _RANDOM[8'hB1][0]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + r_0 = _RANDOM[8'hB1][6:1]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + r_1 = _RANDOM[8'hB1][12:7]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + r_2 = _RANDOM[8'hB1][18:13]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + r_3 = _RANDOM[8'hB1][24:19]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s3_pred_dup_0 = _RANDOM[8'hB1][25]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s3_pred_dup_1 = _RANDOM[8'hB1][26]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s3_pred_dup_2 = _RANDOM[8'hB1][27]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s3_pred_dup_3 = _RANDOM[8'hB1][28]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + sc_enable_dup_REG = _RANDOM[8'hB1][29]; // src/main/scala/xiangshan/frontend/SC.scala:298:40, :319:38, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scTableSums_1_0 = {_RANDOM[8'hB1][31:30], _RANDOM[8'hB2][6:0]}; // src/main/scala/xiangshan/frontend/SC.scala:277:37, :298:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scTableSums_1_1 = _RANDOM[8'hB2][15:7]; // src/main/scala/xiangshan/frontend/SC.scala:277:37, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_tagePrvdCtrCentered_r_1 = _RANDOM[8'hB2][18:16]; // src/main/scala/xiangshan/frontend/SC.scala:277:37, :278:61, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_1_0_ctrs_1_0 = {_RANDOM[8'hB2][31], _RANDOM[8'hB3][4:0]}; // src/main/scala/xiangshan/frontend/SC.scala:277:37, :283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_1_0_ctrs_1_1 = _RANDOM[8'hB3][10:5]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_1_1_ctrs_1_0 = _RANDOM[8'hB3][28:23]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_1_1_ctrs_1_1 = {_RANDOM[8'hB3][31:29], _RANDOM[8'hB4][2:0]}; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_1_2_ctrs_1_0 = _RANDOM[8'hB4][20:15]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_1_2_ctrs_1_1 = _RANDOM[8'hB4][26:21]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_1_3_ctrs_1_0 = _RANDOM[8'hB5][12:7]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s2_scResps_r_1_3_ctrs_1_1 = _RANDOM[8'hB5][18:13]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + resp_meta_scMeta_tageTakens_1_r = _RANDOM[8'hB5][21]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :296:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + resp_meta_scMeta_scUsed_1_r = _RANDOM[8'hB5][22]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :297:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + resp_meta_scMeta_scPreds_1_r = _RANDOM[8'hB5][23]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :298:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + r_1_0 = _RANDOM[8'hB5][29:24]; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + r_1_1 = {_RANDOM[8'hB5][31:30], _RANDOM[8'hB6][3:0]}; // src/main/scala/xiangshan/frontend/SC.scala:283:41, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + r_1_2 = _RANDOM[8'hB6][9:4]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + r_1_3 = _RANDOM[8'hB6][15:10]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s3_pred_dup_0_1 = _RANDOM[8'hB6][16]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s3_pred_dup_1_1 = _RANDOM[8'hB6][17]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s3_pred_dup_2_1 = _RANDOM[8'hB6][18]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + s3_pred_dup_3_1 = _RANDOM[8'hB6][19]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :318:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + sc_enable_dup_REG_1 = _RANDOM[8'hB6][20]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :319:38, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_0_io_update_mask_0_REG = _RANDOM[8'hB6][21]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_0_io_update_tagePreds_0_REG = _RANDOM[8'hB6][22]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_0_io_update_takens_0_REG = _RANDOM[8'hB6][23]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_0_io_update_oldCtrs_0_REG = _RANDOM[8'hB6][29:24]; // src/main/scala/xiangshan/frontend/SC.scala:299:40, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_1_io_update_mask_0_REG = _RANDOM[8'hBC][25]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_1_io_update_tagePreds_0_REG = _RANDOM[8'hBC][26]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_1_io_update_takens_0_REG = _RANDOM[8'hBC][27]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_1_io_update_oldCtrs_0_REG = {_RANDOM[8'hBC][31:28], _RANDOM[8'hBD][1:0]}; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_2_io_update_mask_0_REG = _RANDOM[8'hC2][29]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_2_io_update_tagePreds_0_REG = _RANDOM[8'hC2][30]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_2_io_update_takens_0_REG = _RANDOM[8'hC2][31]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_2_io_update_oldCtrs_0_REG = _RANDOM[8'hC3][5:0]; // src/main/scala/xiangshan/frontend/SC.scala:380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_3_io_update_mask_0_REG = _RANDOM[8'hC9][1]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_3_io_update_tagePreds_0_REG = _RANDOM[8'hC9][2]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_3_io_update_takens_0_REG = _RANDOM[8'hC9][3]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_3_io_update_oldCtrs_0_REG = _RANDOM[8'hC9][9:4]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_0_io_update_mask_1_REG = _RANDOM[8'hCF][5]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_0_io_update_tagePreds_1_REG = _RANDOM[8'hCF][6]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_0_io_update_takens_1_REG = _RANDOM[8'hCF][7]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_0_io_update_oldCtrs_1_REG = _RANDOM[8'hCF][13:8]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_0_io_update_pc_REG_1 = {_RANDOM[8'hCF][31:14], _RANDOM[8'hD0][20:0]}; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :381:44, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_1_io_update_mask_1_REG = _RANDOM[8'hD5][9]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_1_io_update_tagePreds_1_REG = _RANDOM[8'hD5][10]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_1_io_update_takens_1_REG = _RANDOM[8'hD5][11]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_1_io_update_oldCtrs_1_REG = _RANDOM[8'hD5][17:12]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_1_io_update_pc_REG_1 = {_RANDOM[8'hD5][31:18], _RANDOM[8'hD6][24:0]}; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :381:44, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_1_io_update_folded_hist_REG_1_hist_12_folded_hist = _RANDOM[8'hD8][10:7]; // src/main/scala/xiangshan/frontend/SC.scala:382:53, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_2_io_update_mask_1_REG = _RANDOM[8'hDB][13]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_2_io_update_tagePreds_1_REG = _RANDOM[8'hDB][14]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_2_io_update_takens_1_REG = _RANDOM[8'hDB][15]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_2_io_update_oldCtrs_1_REG = _RANDOM[8'hDB][21:16]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_2_io_update_pc_REG_1 = {_RANDOM[8'hDB][31:22], _RANDOM[8'hDC][28:0]}; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :381:44, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_2_io_update_folded_hist_REG_1_hist_11_folded_hist = + _RANDOM[8'hDE][22:15]; // src/main/scala/xiangshan/frontend/SC.scala:382:53, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_3_io_update_mask_1_REG = _RANDOM[8'hE1][17]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_3_io_update_tagePreds_1_REG = _RANDOM[8'hE1][18]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :378:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_3_io_update_takens_1_REG = _RANDOM[8'hE1][19]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :379:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_3_io_update_oldCtrs_1_REG = _RANDOM[8'hE1][25:20]; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :380:54, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_3_io_update_pc_REG_1 = + {_RANDOM[8'hE1][31:26], _RANDOM[8'hE2], _RANDOM[8'hE3][0]}; // src/main/scala/xiangshan/frontend/SC.scala:377:49, :381:44, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scTables_3_io_update_folded_hist_REG_1_hist_2_folded_hist = + {_RANDOM[8'hE6][31:26], _RANDOM[8'hE7][1:0]}; // src/main/scala/xiangshan/frontend/SC.scala:382:53, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + bankTickCtrDistanceToTops_0 = 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 + bankTickCtrDistanceToTops_1 = 7'h7F; // src/main/scala/xiangshan/frontend/Tage.scala:561:58 + bankTickCtrs_0 = 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + bankTickCtrs_1 = 7'h0; // src/main/scala/xiangshan/frontend/Tage.scala:562:45 + useAltOnNaCtrs_0_0 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_1 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_2 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_3 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_4 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_5 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_6 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_7 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_8 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_9 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_10 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_11 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_12 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_13 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_14 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_15 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_16 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_17 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_18 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_19 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_20 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_21 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_22 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_23 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_24 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_25 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_26 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_27 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_28 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_29 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_30 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_31 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_32 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_33 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_34 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_35 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_36 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_37 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_38 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_39 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_40 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_41 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_42 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_43 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_44 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_45 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_46 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_47 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_48 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_49 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_50 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_51 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_52 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_53 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_54 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_55 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_56 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_57 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_58 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_59 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_60 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_61 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_62 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_63 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_64 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_65 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_66 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_67 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_68 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_69 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_70 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_71 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_72 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_73 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_74 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_75 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_76 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_77 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_78 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_79 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_80 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_81 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_82 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_83 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_84 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_85 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_86 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_87 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_88 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_89 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_90 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_91 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_92 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_93 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_94 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_95 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_96 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_97 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_98 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_99 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_100 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_101 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_102 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_103 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_104 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_105 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_106 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_107 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_108 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_109 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_110 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_111 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_112 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_113 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_114 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_115 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_116 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_117 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_118 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_119 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_120 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_121 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_122 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_123 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_124 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_125 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_126 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_0_127 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_0 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_1 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_2 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_3 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_4 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_5 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_6 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_7 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_8 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_9 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_10 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_11 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_12 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_13 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_14 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_15 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_16 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_17 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_18 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_19 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_20 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_21 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_22 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_23 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_24 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_25 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_26 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_27 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_28 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_29 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_30 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_31 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_32 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_33 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_34 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_35 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_36 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_37 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_38 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_39 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_40 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_41 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_42 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_43 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_44 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_45 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_46 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_47 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_48 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_49 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_50 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_51 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_52 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_53 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_54 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_55 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_56 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_57 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_58 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_59 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_60 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_61 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_62 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_63 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_64 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_65 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_66 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_67 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_68 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_69 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_70 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_71 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_72 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_73 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_74 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_75 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_76 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_77 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_78 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_79 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_80 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_81 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_82 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_83 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_84 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_85 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_86 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_87 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_88 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_89 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_90 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_91 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_92 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_93 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_94 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_95 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_96 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_97 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_98 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_99 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_100 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_101 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_102 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_103 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_104 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_105 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_106 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_107 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_108 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_109 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_110 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_111 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_112 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_113 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_114 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_115 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_116 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_117 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_118 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_119 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_120 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_121 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_122 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_123 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_124 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_125 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_126 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + useAltOnNaCtrs_1_127 = 4'h8; // src/main/scala/xiangshan/frontend/Tage.scala:563:31, :565:14 + allocLFSR_lfsr = 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33 + allocLFSR_lfsr_1 = 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33 + scThresholds_0_ctr = 5'h10; // src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52 + scThresholds_0_thres = 8'h6; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + scThresholds_1_ctr = 5'h10; // src/main/scala/xiangshan/frontend/SC.scala:204:11, :229:52 + scThresholds_1_thres = 8'h6; // src/main/scala/xiangshan/frontend/SC.scala:229:52, src/main/scala/xiangshan/frontend/Tage.scala:924:7 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/Tage.scala:924:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + DelayN_2 reset_vector_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + .clock (clock), + .io_in (io_reset_vector), + .io_out (_reset_vector_delay_io_out) + ); + TageTable tables_0 ( // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + .clock (clock), + .reset (reset), + .io_req_ready (_tables_0_io_req_ready), + .io_req_valid (io_s0_fire_1), + .io_req_bits_pc (io_in_bits_s0_pc_1), + .io_req_bits_folded_hist_hist_14_folded_hist + (io_in_bits_folded_hist_1_hist_14_folded_hist), + .io_req_bits_folded_hist_hist_7_folded_hist + (io_in_bits_folded_hist_1_hist_7_folded_hist), + .io_resps_0_valid (_tables_0_io_resps_0_valid), + .io_resps_0_bits_ctr (_tables_0_io_resps_0_bits_ctr), + .io_resps_0_bits_u (_tables_0_io_resps_0_bits_u), + .io_resps_0_bits_unconf (_tables_0_io_resps_0_bits_unconf), + .io_resps_1_valid (_tables_0_io_resps_1_valid), + .io_resps_1_bits_ctr (_tables_0_io_resps_1_bits_ctr), + .io_resps_1_bits_u (_tables_0_io_resps_1_bits_u), + .io_resps_1_bits_unconf (_tables_0_io_resps_1_bits_unconf), + .io_update_pc (tables_0_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + .io_update_folded_hist_hist_14_folded_hist + (tables_0_io_update_folded_hist_REG_1_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + .io_update_folded_hist_hist_7_folded_hist + (tables_0_io_update_folded_hist_REG_1_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + .io_update_mask_0 (tables_0_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + .io_update_mask_1 (tables_0_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + .io_update_takens_0 (tables_0_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + .io_update_takens_1 (tables_0_io_update_takens_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + .io_update_alloc_0 (tables_0_io_update_alloc_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + .io_update_alloc_1 (tables_0_io_update_alloc_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + .io_update_oldCtrs_0 (tables_0_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + .io_update_oldCtrs_1 (tables_0_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + .io_update_uMask_0 (tables_0_io_update_uMask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + .io_update_uMask_1 (tables_0_io_update_uMask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + .io_update_us_0 (tables_0_io_update_us_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + .io_update_us_1 (tables_0_io_update_us_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + .io_update_reset_u_0 (tables_0_io_update_reset_u_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + .io_update_reset_u_1 (tables_0_io_update_reset_u_1_REG) // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + ); + TageTable_1 tables_1 ( // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + .clock (clock), + .reset (reset), + .io_req_ready (_tables_1_io_req_ready), + .io_req_valid (io_s0_fire_1), + .io_req_bits_pc (io_in_bits_s0_pc_1), + .io_req_bits_folded_hist_hist_15_folded_hist + (io_in_bits_folded_hist_1_hist_15_folded_hist), + .io_req_bits_folded_hist_hist_4_folded_hist + (io_in_bits_folded_hist_1_hist_4_folded_hist), + .io_req_bits_folded_hist_hist_1_folded_hist + (io_in_bits_folded_hist_1_hist_1_folded_hist), + .io_resps_0_valid (_tables_1_io_resps_0_valid), + .io_resps_0_bits_ctr (_tables_1_io_resps_0_bits_ctr), + .io_resps_0_bits_u (_tables_1_io_resps_0_bits_u), + .io_resps_0_bits_unconf (_tables_1_io_resps_0_bits_unconf), + .io_resps_1_valid (_tables_1_io_resps_1_valid), + .io_resps_1_bits_ctr (_tables_1_io_resps_1_bits_ctr), + .io_resps_1_bits_u (_tables_1_io_resps_1_bits_u), + .io_resps_1_bits_unconf (_tables_1_io_resps_1_bits_unconf), + .io_update_pc (tables_1_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + .io_update_folded_hist_hist_15_folded_hist + (tables_1_io_update_folded_hist_REG_1_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + .io_update_folded_hist_hist_4_folded_hist + (tables_1_io_update_folded_hist_REG_1_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + .io_update_folded_hist_hist_1_folded_hist + (tables_1_io_update_folded_hist_REG_1_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + .io_update_mask_0 (tables_1_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + .io_update_mask_1 (tables_1_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + .io_update_takens_0 (tables_1_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + .io_update_takens_1 (tables_1_io_update_takens_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + .io_update_alloc_0 (tables_1_io_update_alloc_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + .io_update_alloc_1 (tables_1_io_update_alloc_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + .io_update_oldCtrs_0 (tables_1_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + .io_update_oldCtrs_1 (tables_1_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + .io_update_uMask_0 (tables_1_io_update_uMask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + .io_update_uMask_1 (tables_1_io_update_uMask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + .io_update_us_0 (tables_1_io_update_us_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + .io_update_us_1 (tables_1_io_update_us_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + .io_update_reset_u_0 (tables_1_io_update_reset_u_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + .io_update_reset_u_1 (tables_1_io_update_reset_u_1_REG) // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + ); + TageTable_2 tables_2 ( // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + .clock (clock), + .reset (reset), + .io_req_ready (_tables_2_io_req_ready), + .io_req_valid (io_s0_fire_1), + .io_req_bits_pc (io_in_bits_s0_pc_1), + .io_req_bits_folded_hist_hist_17_folded_hist + (io_in_bits_folded_hist_1_hist_17_folded_hist), + .io_req_bits_folded_hist_hist_9_folded_hist + (io_in_bits_folded_hist_1_hist_9_folded_hist), + .io_req_bits_folded_hist_hist_3_folded_hist + (io_in_bits_folded_hist_1_hist_3_folded_hist), + .io_resps_0_valid (_tables_2_io_resps_0_valid), + .io_resps_0_bits_ctr (_tables_2_io_resps_0_bits_ctr), + .io_resps_0_bits_u (_tables_2_io_resps_0_bits_u), + .io_resps_0_bits_unconf (_tables_2_io_resps_0_bits_unconf), + .io_resps_1_valid (_tables_2_io_resps_1_valid), + .io_resps_1_bits_ctr (_tables_2_io_resps_1_bits_ctr), + .io_resps_1_bits_u (_tables_2_io_resps_1_bits_u), + .io_resps_1_bits_unconf (_tables_2_io_resps_1_bits_unconf), + .io_update_pc (tables_2_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + .io_update_folded_hist_hist_17_folded_hist + (tables_2_io_update_folded_hist_REG_1_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + .io_update_folded_hist_hist_9_folded_hist + (tables_2_io_update_folded_hist_REG_1_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + .io_update_folded_hist_hist_3_folded_hist + (tables_2_io_update_folded_hist_REG_1_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + .io_update_mask_0 (tables_2_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + .io_update_mask_1 (tables_2_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + .io_update_takens_0 (tables_2_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + .io_update_takens_1 (tables_2_io_update_takens_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + .io_update_alloc_0 (tables_2_io_update_alloc_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + .io_update_alloc_1 (tables_2_io_update_alloc_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + .io_update_oldCtrs_0 (tables_2_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + .io_update_oldCtrs_1 (tables_2_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + .io_update_uMask_0 (tables_2_io_update_uMask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + .io_update_uMask_1 (tables_2_io_update_uMask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + .io_update_us_0 (tables_2_io_update_us_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + .io_update_us_1 (tables_2_io_update_us_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + .io_update_reset_u_0 (tables_2_io_update_reset_u_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + .io_update_reset_u_1 (tables_2_io_update_reset_u_1_REG) // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + ); + TageTable_3 tables_3 ( // src/main/scala/xiangshan/frontend/Tage.scala:549:21 + .clock (clock), + .reset (reset), + .io_req_ready (_tables_3_io_req_ready), + .io_req_valid (io_s0_fire_1), + .io_req_bits_pc (io_in_bits_s0_pc_1), + .io_req_bits_folded_hist_hist_16_folded_hist + (io_in_bits_folded_hist_1_hist_16_folded_hist), + .io_req_bits_folded_hist_hist_8_folded_hist + (io_in_bits_folded_hist_1_hist_8_folded_hist), + .io_req_bits_folded_hist_hist_5_folded_hist + (io_in_bits_folded_hist_1_hist_5_folded_hist), + .io_resps_0_valid (_tables_3_io_resps_0_valid), + .io_resps_0_bits_ctr (_tables_3_io_resps_0_bits_ctr), + .io_resps_0_bits_u (_tables_3_io_resps_0_bits_u), + .io_resps_0_bits_unconf (_tables_3_io_resps_0_bits_unconf), + .io_resps_1_valid (_tables_3_io_resps_1_valid), + .io_resps_1_bits_ctr (_tables_3_io_resps_1_bits_ctr), + .io_resps_1_bits_u (_tables_3_io_resps_1_bits_u), + .io_resps_1_bits_unconf (_tables_3_io_resps_1_bits_unconf), + .io_update_pc (tables_3_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/Tage.scala:843:46 + .io_update_folded_hist_hist_16_folded_hist + (tables_3_io_update_folded_hist_REG_1_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + .io_update_folded_hist_hist_8_folded_hist + (tables_3_io_update_folded_hist_REG_1_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + .io_update_folded_hist_hist_5_folded_hist + (tables_3_io_update_folded_hist_REG_1_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/Tage.scala:844:49 + .io_update_mask_0 (tables_3_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + .io_update_mask_1 (tables_3_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:834:48 + .io_update_takens_0 (tables_3_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + .io_update_takens_1 (tables_3_io_update_takens_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:835:48 + .io_update_alloc_0 (tables_3_io_update_alloc_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + .io_update_alloc_1 (tables_3_io_update_alloc_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:836:48 + .io_update_oldCtrs_0 (tables_3_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + .io_update_oldCtrs_1 (tables_3_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:837:48 + .io_update_uMask_0 (tables_3_io_update_uMask_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + .io_update_uMask_1 (tables_3_io_update_uMask_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:839:48 + .io_update_us_0 (tables_3_io_update_us_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + .io_update_us_1 (tables_3_io_update_us_1_REG), // src/main/scala/xiangshan/frontend/Tage.scala:840:48 + .io_update_reset_u_0 (tables_3_io_update_reset_u_0_REG), // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + .io_update_reset_u_1 (tables_3_io_update_reset_u_1_REG) // src/main/scala/xiangshan/frontend/Tage.scala:841:48 + ); + TageBTable bt ( // src/main/scala/xiangshan/frontend/Tage.scala:557:19 + .clock (clock), + .reset (reset), + .io_req_ready (_bt_io_req_ready), + .io_req_valid (io_s0_fire_1), + .io_req_bits (io_in_bits_s0_pc_1), + .io_s1_cnt_0 (_bt_io_s1_cnt_0), + .io_s1_cnt_1 (_bt_io_s1_cnt_1), + .io_update_mask_0 (REG_2_0), // src/main/scala/xiangshan/frontend/Tage.scala:848:31 + .io_update_mask_1 (REG_2_1), // src/main/scala/xiangshan/frontend/Tage.scala:848:31 + .io_update_pc (bt_io_update_pc_REG), // src/main/scala/xiangshan/frontend/Tage.scala:850:29 + .io_update_cnt_0 (REG_3_0), // src/main/scala/xiangshan/frontend/Tage.scala:849:30 + .io_update_cnt_1 (REG_3_1), // src/main/scala/xiangshan/frontend/Tage.scala:849:30 + .io_update_takens_0 (REG_4_0), // src/main/scala/xiangshan/frontend/Tage.scala:851:33 + .io_update_takens_1 (REG_4_1) // src/main/scala/xiangshan/frontend/Tage.scala:851:33 + ); + SCTable scTables_0 ( // src/main/scala/xiangshan/frontend/SC.scala:217:23 + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_resp_ctrs_0_0 (_scTables_0_io_resp_ctrs_0_0), + .io_resp_ctrs_0_1 (_scTables_0_io_resp_ctrs_0_1), + .io_resp_ctrs_1_0 (_scTables_0_io_resp_ctrs_1_0), + .io_resp_ctrs_1_1 (_scTables_0_io_resp_ctrs_1_1), + .io_update_pc (scTables_0_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/SC.scala:381:44 + .io_update_mask_0 (scTables_0_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 + .io_update_mask_1 (scTables_0_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 + .io_update_oldCtrs_0 (scTables_0_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 + .io_update_oldCtrs_1 (scTables_0_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 + .io_update_tagePreds_0 (scTables_0_io_update_tagePreds_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 + .io_update_tagePreds_1 (scTables_0_io_update_tagePreds_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 + .io_update_takens_0 (scTables_0_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:379:54 + .io_update_takens_1 (scTables_0_io_update_takens_1_REG) // src/main/scala/xiangshan/frontend/SC.scala:379:54 + ); + SCTable_1 scTables_1 ( // src/main/scala/xiangshan/frontend/SC.scala:217:23 + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_12_folded_hist + (io_in_bits_folded_hist_3_hist_12_folded_hist), + .io_resp_ctrs_0_0 (_scTables_1_io_resp_ctrs_0_0), + .io_resp_ctrs_0_1 (_scTables_1_io_resp_ctrs_0_1), + .io_resp_ctrs_1_0 (_scTables_1_io_resp_ctrs_1_0), + .io_resp_ctrs_1_1 (_scTables_1_io_resp_ctrs_1_1), + .io_update_pc (scTables_1_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/SC.scala:381:44 + .io_update_folded_hist_hist_12_folded_hist + (scTables_1_io_update_folded_hist_REG_1_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/SC.scala:382:53 + .io_update_mask_0 (scTables_1_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 + .io_update_mask_1 (scTables_1_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 + .io_update_oldCtrs_0 (scTables_1_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 + .io_update_oldCtrs_1 (scTables_1_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 + .io_update_tagePreds_0 (scTables_1_io_update_tagePreds_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 + .io_update_tagePreds_1 (scTables_1_io_update_tagePreds_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 + .io_update_takens_0 (scTables_1_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:379:54 + .io_update_takens_1 (scTables_1_io_update_takens_1_REG) // src/main/scala/xiangshan/frontend/SC.scala:379:54 + ); + SCTable_2 scTables_2 ( // src/main/scala/xiangshan/frontend/SC.scala:217:23 + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_11_folded_hist + (io_in_bits_folded_hist_3_hist_11_folded_hist), + .io_resp_ctrs_0_0 (_scTables_2_io_resp_ctrs_0_0), + .io_resp_ctrs_0_1 (_scTables_2_io_resp_ctrs_0_1), + .io_resp_ctrs_1_0 (_scTables_2_io_resp_ctrs_1_0), + .io_resp_ctrs_1_1 (_scTables_2_io_resp_ctrs_1_1), + .io_update_pc (scTables_2_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/SC.scala:381:44 + .io_update_folded_hist_hist_11_folded_hist + (scTables_2_io_update_folded_hist_REG_1_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/SC.scala:382:53 + .io_update_mask_0 (scTables_2_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 + .io_update_mask_1 (scTables_2_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 + .io_update_oldCtrs_0 (scTables_2_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 + .io_update_oldCtrs_1 (scTables_2_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 + .io_update_tagePreds_0 (scTables_2_io_update_tagePreds_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 + .io_update_tagePreds_1 (scTables_2_io_update_tagePreds_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 + .io_update_takens_0 (scTables_2_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:379:54 + .io_update_takens_1 (scTables_2_io_update_takens_1_REG) // src/main/scala/xiangshan/frontend/SC.scala:379:54 + ); + SCTable_3 scTables_3 ( // src/main/scala/xiangshan/frontend/SC.scala:217:23 + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_2_folded_hist + (io_in_bits_folded_hist_3_hist_2_folded_hist), + .io_resp_ctrs_0_0 (_scTables_3_io_resp_ctrs_0_0), + .io_resp_ctrs_0_1 (_scTables_3_io_resp_ctrs_0_1), + .io_resp_ctrs_1_0 (_scTables_3_io_resp_ctrs_1_0), + .io_resp_ctrs_1_1 (_scTables_3_io_resp_ctrs_1_1), + .io_update_pc (scTables_3_io_update_pc_REG_1), // src/main/scala/xiangshan/frontend/SC.scala:381:44 + .io_update_folded_hist_hist_2_folded_hist + (scTables_3_io_update_folded_hist_REG_1_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/SC.scala:382:53 + .io_update_mask_0 (scTables_3_io_update_mask_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 + .io_update_mask_1 (scTables_3_io_update_mask_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:377:49 + .io_update_oldCtrs_0 (scTables_3_io_update_oldCtrs_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 + .io_update_oldCtrs_1 (scTables_3_io_update_oldCtrs_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:380:54 + .io_update_tagePreds_0 (scTables_3_io_update_tagePreds_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 + .io_update_tagePreds_1 (scTables_3_io_update_tagePreds_1_REG), // src/main/scala/xiangshan/frontend/SC.scala:378:54 + .io_update_takens_0 (scTables_3_io_update_takens_0_REG), // src/main/scala/xiangshan/frontend/SC.scala:379:54 + .io_update_takens_1 (scTables_3_io_update_takens_1_REG) // src/main/scala/xiangshan/frontend/SC.scala:379:54 + ); + assign io_out_s2_full_pred_0_br_taken_mask_0 = + tage_enable_dup_REG & s2_tageTakens_dup_0_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + assign io_out_s2_full_pred_0_br_taken_mask_1 = + tage_enable_dup_REG_1 & s2_tageTakens_dup_0_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + assign io_out_s2_full_pred_1_br_taken_mask_0 = + tage_enable_dup_REG & s2_tageTakens_dup_1_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + assign io_out_s2_full_pred_1_br_taken_mask_1 = + tage_enable_dup_REG_1 & s2_tageTakens_dup_1_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + assign io_out_s2_full_pred_2_br_taken_mask_0 = + tage_enable_dup_REG & s2_tageTakens_dup_2_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + assign io_out_s2_full_pred_2_br_taken_mask_1 = + tage_enable_dup_REG_1 & s2_tageTakens_dup_2_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + assign io_out_s2_full_pred_3_br_taken_mask_0 = + tage_enable_dup_REG & s2_tageTakens_dup_3_0; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + assign io_out_s2_full_pred_3_br_taken_mask_1 = + tage_enable_dup_REG_1 & s2_tageTakens_dup_3_1; // src/main/scala/xiangshan/frontend/Tage.scala:600:58, :605:10, :705:38, :707:26, :708:29, :924:7 + assign io_out_s3_full_pred_0_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_0; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 + assign io_out_s3_full_pred_0_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_0_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 + assign io_out_s3_full_pred_1_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 + assign io_out_s3_full_pred_1_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_1_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 + assign io_out_s3_full_pred_2_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_2; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 + assign io_out_s3_full_pred_2_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_2_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 + assign io_out_s3_full_pred_3_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_3; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 + assign io_out_s3_full_pred_3_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_3_1; // src/main/scala/xiangshan/frontend/SC.scala:318:54, :319:38, :322:28, :323:33, src/main/scala/xiangshan/frontend/Tage.scala:605:10, :924:7 + assign io_out_last_stage_meta = + {131'h0, + resp_meta_providers_1_valid_r, + resp_meta_providers_1_bits_r, + resp_meta_providers_0_valid_r, + resp_meta_providers_0_bits_r, + resp_meta_providerResps_1_r_ctr, + resp_meta_providerResps_1_r_u, + resp_meta_providerResps_1_r_unconf, + resp_meta_providerResps_0_r_ctr, + resp_meta_providerResps_0_r_u, + resp_meta_providerResps_0_r_unconf, + resp_meta_altUsed_1_r, + resp_meta_altUsed_0_r, + resp_meta_altDiffers_1_r, + resp_meta_altDiffers_0_r, + resp_meta_basecnts_1_r, + resp_meta_basecnts_0_r, + resp_meta_allocates_1_r, + resp_meta_allocates_0_r, + resp_meta_takens_1_r, + resp_meta_takens_0_r, + resp_meta_scMeta_tageTakens_1_r, + resp_meta_scMeta_tageTakens_0_r, + resp_meta_scMeta_scUsed_1_r, + resp_meta_scMeta_scUsed_0_r, + resp_meta_scMeta_scPreds_1_r, + resp_meta_scMeta_scPreds_0_r, + r_1_3, + r_1_2, + r_1_1, + r_1_0, + r_3, + r_2, + r_1, + r_0}; // src/main/scala/xiangshan/frontend/SC.scala:296:40, :297:40, :298:40, :299:40, src/main/scala/xiangshan/frontend/Tage.scala:606:26, :667:49, :668:49, :669:49, :686:40, :699:41, :700:41, :702:41, :703:41, :924:7 + assign io_s1_ready = + _tables_0_io_req_ready & _tables_1_io_req_ready & _tables_2_io_req_ready + & _tables_3_io_req_ready & _bt_io_req_ready; // src/main/scala/xiangshan/frontend/Tage.scala:549:21, :557:19, :854:60, :924:7 +endmodule + diff --git a/src/TageSC/array_4.sv b/src/TageSC/array_4.sv new file mode 100644 index 0000000..22347ed --- /dev/null +++ b/src/TageSC/array_4.sv @@ -0,0 +1,78 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module array_4( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + input [7:0] RW0_addr, + input RW0_en, + input RW0_clk, + input RW0_wmode, + input [15:0] RW0_wdata, + output [15:0] RW0_rdata, + input [15:0] RW0_wmask +); + + array_4_ext array_4_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + .RW0_addr (RW0_addr), + .RW0_en (RW0_en), + .RW0_clk (RW0_clk), + .RW0_wmode (RW0_wmode), + .RW0_wdata (RW0_wdata), + .RW0_rdata (RW0_rdata), + .RW0_wmask (RW0_wmask) + ); +endmodule + diff --git a/src/TageSC/array_5.sv b/src/TageSC/array_5.sv new file mode 100644 index 0000000..1cdac7c --- /dev/null +++ b/src/TageSC/array_5.sv @@ -0,0 +1,78 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module array_5( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + input [8:0] RW0_addr, + input RW0_en, + input RW0_clk, + input RW0_wmode, + input [23:0] RW0_wdata, + output [23:0] RW0_rdata, + input [1:0] RW0_wmask +); + + array_5_ext array_5_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + .RW0_addr (RW0_addr), + .RW0_en (RW0_en), + .RW0_clk (RW0_clk), + .RW0_wmode (RW0_wmode), + .RW0_wdata (RW0_wdata), + .RW0_rdata (RW0_rdata), + .RW0_wmask (RW0_wmask) + ); +endmodule + diff --git a/src/TageSC/array_6.sv b/src/TageSC/array_6.sv new file mode 100644 index 0000000..e0e1c02 --- /dev/null +++ b/src/TageSC/array_6.sv @@ -0,0 +1,82 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module array_6( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + input [8:0] R0_addr, + input R0_en, + input R0_clk, + output [15:0] R0_data, + input [8:0] W0_addr, + input W0_en, + input W0_clk, + input [15:0] W0_data, + input [7:0] W0_mask +); + + array_6_ext array_6_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + .R0_addr (R0_addr), + .R0_en (R0_en), + .R0_clk (R0_clk), + .R0_data (R0_data), + .W0_addr (W0_addr), + .W0_en (W0_en), + .W0_clk (W0_clk), + .W0_data (W0_data), + .W0_mask (W0_mask) + ); +endmodule + diff --git a/src/TageSC/array_7.sv b/src/TageSC/array_7.sv new file mode 100644 index 0000000..540116e --- /dev/null +++ b/src/TageSC/array_7.sv @@ -0,0 +1,82 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module array_7( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + input [7:0] R0_addr, + input R0_en, + input R0_clk, + output [23:0] R0_data, + input [7:0] W0_addr, + input W0_en, + input W0_clk, + input [23:0] W0_data, + input [3:0] W0_mask +); + + array_7_ext array_7_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26 + .R0_addr (R0_addr), + .R0_en (R0_en), + .R0_clk (R0_clk), + .R0_data (R0_data), + .W0_addr (W0_addr), + .W0_en (W0_en), + .W0_clk (W0_clk), + .W0_data (W0_data), + .W0_mask (W0_mask) + ); +endmodule + diff --git a/src/TageSC/data_mem_0_8x3.sv b/src/TageSC/data_mem_0_8x3.sv new file mode 100644 index 0000000..1dc4ba6 --- /dev/null +++ b/src/TageSC/data_mem_0_8x3.sv @@ -0,0 +1,89 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +// VCS coverage exclude_file +module data_mem_0_8x3( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + input [2:0] R0_addr, + input R0_en, + input R0_clk, + output [2:0] R0_data, + input [2:0] W0_addr, + input W0_en, + input W0_clk, + input [2:0] W0_data +); + + reg [2:0] Memory[0:7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + always @(posedge W0_clk) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + if (W0_en & 1'h1) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + Memory[W0_addr] <= W0_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + reg [31:0] _RANDOM_MEM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + `ifdef RANDOMIZE_MEM_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin + _RANDOM_MEM = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + Memory[i[2:0]] = _RANDOM_MEM[2:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + end // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 3'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 +endmodule + diff --git a/src/TageSC/data_mem_16x12.sv b/src/TageSC/data_mem_16x12.sv new file mode 100644 index 0000000..48bbe85 --- /dev/null +++ b/src/TageSC/data_mem_16x12.sv @@ -0,0 +1,97 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +// VCS coverage exclude_file +module data_mem_16x12( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + input [3:0] R0_addr, + input R0_en, + input R0_clk, + output [11:0] R0_data, + input [3:0] R1_addr, + input R1_en, + input R1_clk, + output [11:0] R1_data, + input [3:0] W0_addr, + input W0_en, + input W0_clk, + input [11:0] W0_data, + input [1:0] W0_mask +); + + reg [11:0] Memory[0:15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + always @(posedge W0_clk) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + if (W0_en & W0_mask[0]) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + Memory[W0_addr][32'h0 +: 6] <= W0_data[5:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + if (W0_en & W0_mask[1]) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + Memory[W0_addr][32'h6 +: 6] <= W0_data[11:6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + reg [31:0] _RANDOM_MEM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + `ifdef RANDOMIZE_MEM_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin + _RANDOM_MEM = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + Memory[i[3:0]] = _RANDOM_MEM[11:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + end // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 12'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + assign R1_data = R1_en ? Memory[R1_addr] : 12'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 +endmodule + diff --git a/src/TageSC/data_mem_8x4.sv b/src/TageSC/data_mem_8x4.sv new file mode 100644 index 0000000..540a7d9 --- /dev/null +++ b/src/TageSC/data_mem_8x4.sv @@ -0,0 +1,97 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +// VCS coverage exclude_file +module data_mem_8x4( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + input [2:0] R0_addr, + input R0_en, + input R0_clk, + output [3:0] R0_data, + input [2:0] R1_addr, + input R1_en, + input R1_clk, + output [3:0] R1_data, + input [2:0] W0_addr, + input W0_en, + input W0_clk, + input [3:0] W0_data, + input [1:0] W0_mask +); + + reg [3:0] Memory[0:7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + always @(posedge W0_clk) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + if (W0_en & W0_mask[0]) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + Memory[W0_addr][32'h0 +: 2] <= W0_data[1:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + if (W0_en & W0_mask[1]) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + Memory[W0_addr][32'h2 +: 2] <= W0_data[3:2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + reg [31:0] _RANDOM_MEM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + `ifdef RANDOMIZE_MEM_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin + _RANDOM_MEM = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + Memory[i[2:0]] = _RANDOM_MEM[3:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + end // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 4'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + assign R1_data = R1_en ? Memory[R1_addr] : 4'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 +endmodule + diff --git a/src/Tage_SC.txt b/src/Tage_SC.txt new file mode 100644 index 0000000..6c97f0d --- /dev/null +++ b/src/Tage_SC.txt @@ -0,0 +1,33 @@ +./src/TageSC/CAMTemplate.sv +./src/TageSC/CAMTemplate_32.sv +./src/TageSC/CAMTemplate_33.sv +./src/TageSC/FoldedSRAMTemplate.sv +./src/TageSC/FoldedSRAMTemplate_1.sv +./src/TageSC/FoldedSRAMTemplate_20.sv +./src/TageSC/SCTable.sv +./src/TageSC/SCTable_1.sv +./src/TageSC/SCTable_2.sv +./src/TageSC/SCTable_3.sv +./src/TageSC/SRAMTemplate_10.sv +./src/TageSC/SRAMTemplate_11.sv +./src/TageSC/SRAMTemplate_30.sv +./src/TageSC/SRAMTemplate_31.sv +./src/TageSC/TageBTable.sv +./src/TageSC/TageTable.sv +./src/TageSC/TageTable_1.sv +./src/TageSC/TageTable_2.sv +./src/TageSC/TageTable_3.sv +#./src/TageSC/Tage_SC.sv +./src/TageSC/array_4.sv +./src/TageSC/array_5.sv +./src/TageSC/array_6.sv +./src/TageSC/array_7.sv +./src/TageSC/data_mem_0_8x3.sv +./src/TageSC/data_mem_16x12.sv +./src/TageSC/data_mem_8x4.sv +# +./src/WrBypass/WrBypass.sv +./src/WrBypass/WrBypass_32.sv +./src/WrBypass/WrBypass_33.sv +./src/common/ext_sram.v +./src/common/DelayN_2.sv \ No newline at end of file diff --git a/src/WrBypass/WrBypass.sv b/src/WrBypass/WrBypass.sv new file mode 100644 index 0000000..13c7a8c --- /dev/null +++ b/src/WrBypass/WrBypass.sv @@ -0,0 +1,282 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module WrBypass( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + input clock, + input reset, + input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input [8:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input [2:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output io_hit_data_0_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output [2:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 +); + + wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + reg valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire [2:0] _hit_idx_T_2 = + {hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + wire [2:0] data_mem_io_hit_data_0_bits_MPORT_addr = + {|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4}, + |(_hit_idx_T_2[2:1]), + _hit_idx_T_2[2] | _hit_idx_T_2[0]}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + wire hit = + hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6 + | hits_oh_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:61:83, :63:29 + reg [6:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + wire [2:0] enq_idx = + {state_reg[6], + state_reg[6] + ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]} + : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13 + wire [2:0] state_reg_touch_way_sized = + hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37 + wire _GEN = enq_idx == 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_0 = enq_idx == 3'h1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_1 = enq_idx == 3'h2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_2 = enq_idx == 3'h3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_3 = enq_idx == 3'h4; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_4 = enq_idx == 3'h5; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_5 = enq_idx == 3'h6; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + always @(posedge clock or posedge reset) begin + if (reset) begin + valids_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_4 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_5 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_6 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_7 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + state_reg <= 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + end + else begin + if (io_wen) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + if (hit) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29 + valids_0_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h0 | valids_0_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 + valids_1_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h1 | valids_1_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 + valids_2_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h2 | valids_2_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 + valids_3_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h3 | valids_3_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 + valids_4_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h4 | valids_4_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 + valids_5_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h5 | valids_5_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 + valids_6_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h6 | valids_6_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 + valids_7_0 <= (&data_mem_io_hit_data_0_bits_MPORT_addr) | valids_7_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30 + end + else begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29 + valids_0_0 <= _GEN | ~_GEN & valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 + valids_1_0 <= _GEN_0 | ~_GEN_0 & valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 + valids_2_0 <= _GEN_1 | ~_GEN_1 & valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 + valids_3_0 <= _GEN_2 | ~_GEN_2 & valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 + valids_4_0 <= _GEN_3 | ~_GEN_3 & valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 + valids_5_0 <= _GEN_4 | ~_GEN_4 & valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 + valids_6_0 <= _GEN_5 | ~_GEN_5 & valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 + valids_7_0 <= (&enq_idx) | ~(&enq_idx) & valids_7_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30 + end + state_reg <= + {~(state_reg_touch_way_sized[2]), + state_reg_touch_way_sized[2] + ? {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[4], + state_reg_touch_way_sized[1] + ? state_reg[3] + : ~(state_reg_touch_way_sized[0])} + : state_reg[5:3], + state_reg_touch_way_sized[2] + ? state_reg[2:0] + : {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[1], + state_reg_touch_way_sized[1] + ? state_reg[0] + : ~(state_reg_touch_way_sized[0])}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37 + end + ever_written_0 <= io_wen & ~hit & _GEN | ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_1 <= io_wen & ~hit & _GEN_0 | ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_2 <= io_wen & ~hit & _GEN_1 | ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_3 <= io_wen & ~hit & _GEN_2 | ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_4 <= io_wen & ~hit & _GEN_3 | ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_5 <= io_wen & ~hit & _GEN_4 | ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_6 <= io_wen & ~hit & _GEN_5 | ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_7 <= io_wen & ~hit & (&enq_idx) | ever_written_7; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][8]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][9]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][10]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][11]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][12]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][13]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][14]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + state_reg = _RANDOM[/*Zero width*/ 1'b0][22:16]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + valids_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_4 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_5 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_6 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_7 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + state_reg = 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + CAMTemplate idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + .clock (clock), + .io_r_req_0_idx (io_write_idx), + .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), + .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), + .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), + .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), + .io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4), + .io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5), + .io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6), + .io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7), + .io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26} + .io_w_bits_data_idx (io_write_idx), + .io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12 + ); + data_mem_0_8x3 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + .R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 + .R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + .R0_clk (clock), + .R0_data (io_hit_data_0_bits), + .W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29 + .W0_en (io_wen), + .W0_clk (clock), + .W0_data (io_write_data_0) + ); + assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29 + assign io_hit_data_0_valid = + hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3 + & valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6 + & valids_6_0 | hits_oh_7 & valids_7_0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83 +endmodule + diff --git a/src/WrBypass/WrBypass_32.sv b/src/WrBypass/WrBypass_32.sv new file mode 100644 index 0000000..9e3abdc --- /dev/null +++ b/src/WrBypass/WrBypass_32.sv @@ -0,0 +1,358 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module WrBypass_32( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + input clock, + input reset, + input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input [10:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input [1:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input [1:0] io_write_data_1, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input io_write_way_mask_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input io_write_way_mask_1, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output io_hit_data_0_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output [1:0] io_hit_data_0_bits, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output io_hit_data_1_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output [1:0] io_hit_data_1_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 +); + + wire [3:0] _data_mem_ext_R0_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + wire [3:0] _data_mem_ext_R1_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + reg valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_7_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire [2:0] _hit_idx_T_2 = + {hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + wire [2:0] data_mem_io_hit_data_1_bits_MPORT_addr = + {|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4}, + |(_hit_idx_T_2[2:1]), + _hit_idx_T_2[2] | _hit_idx_T_2[0]}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + wire hit = + hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6 + | hits_oh_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:61:83, :63:29 + reg [6:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + wire [2:0] enq_idx = + {state_reg[6], + state_reg[6] + ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]} + : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13 + wire _GEN = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_0 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h1; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_1 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h2; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_2 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h3; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_3 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h4; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_4 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h5; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_5 = data_mem_io_hit_data_1_bits_MPORT_addr == 3'h6; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire [2:0] state_reg_touch_way_sized = + hit ? data_mem_io_hit_data_1_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37 + wire _GEN_6 = enq_idx == 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_7 = enq_idx == 3'h1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_8 = enq_idx == 3'h2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_9 = enq_idx == 3'h3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_10 = enq_idx == 3'h4; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_11 = enq_idx == 3'h5; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_12 = enq_idx == 3'h6; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + always @(posedge clock or posedge reset) begin + if (reset) begin + valids_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_0_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_4 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_5 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_6 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_7 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + state_reg <= 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + end + else begin + if (io_wen) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + if (hit) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29 + valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_7_0 <= + io_write_way_mask_0 & (&data_mem_io_hit_data_1_bits_MPORT_addr) | valids_7_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_7_1 <= + io_write_way_mask_1 & (&data_mem_io_hit_data_1_bits_MPORT_addr) | valids_7_1; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + end + else begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29 + valids_0_0 <= io_write_way_mask_0 & _GEN_6 | ~_GEN_6 & valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_0_1 <= io_write_way_mask_1 & _GEN_6 | ~_GEN_6 & valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_1_0 <= io_write_way_mask_0 & _GEN_7 | ~_GEN_7 & valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_1_1 <= io_write_way_mask_1 & _GEN_7 | ~_GEN_7 & valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_2_0 <= io_write_way_mask_0 & _GEN_8 | ~_GEN_8 & valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_2_1 <= io_write_way_mask_1 & _GEN_8 | ~_GEN_8 & valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_3_0 <= io_write_way_mask_0 & _GEN_9 | ~_GEN_9 & valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_3_1 <= io_write_way_mask_1 & _GEN_9 | ~_GEN_9 & valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_4_0 <= io_write_way_mask_0 & _GEN_10 | ~_GEN_10 & valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_4_1 <= io_write_way_mask_1 & _GEN_10 | ~_GEN_10 & valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_5_0 <= io_write_way_mask_0 & _GEN_11 | ~_GEN_11 & valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_5_1 <= io_write_way_mask_1 & _GEN_11 | ~_GEN_11 & valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_6_0 <= io_write_way_mask_0 & _GEN_12 | ~_GEN_12 & valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_6_1 <= io_write_way_mask_1 & _GEN_12 | ~_GEN_12 & valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_7_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_7_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_7_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_7_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + end + state_reg <= + {~(state_reg_touch_way_sized[2]), + state_reg_touch_way_sized[2] + ? {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[4], + state_reg_touch_way_sized[1] + ? state_reg[3] + : ~(state_reg_touch_way_sized[0])} + : state_reg[5:3], + state_reg_touch_way_sized[2] + ? state_reg[2:0] + : {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[1], + state_reg_touch_way_sized[1] + ? state_reg[0] + : ~(state_reg_touch_way_sized[0])}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37 + end + ever_written_0 <= io_wen & ~hit & (_GEN_6 | io_wen & _GEN_6) | ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_1 <= io_wen & ~hit & (_GEN_7 | io_wen & _GEN_7) | ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_2 <= io_wen & ~hit & (_GEN_8 | io_wen & _GEN_8) | ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_3 <= io_wen & ~hit & (_GEN_9 | io_wen & _GEN_9) | ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_4 <= io_wen & ~hit & (_GEN_10 | io_wen & _GEN_10) | ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_5 <= io_wen & ~hit & (_GEN_11 | io_wen & _GEN_11) | ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_6 <= io_wen & ~hit & (_GEN_12 | io_wen & _GEN_12) | ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_7 <= + io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_7; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_0_1 = _RANDOM[/*Zero width*/ 1'b0][1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_1 = _RANDOM[/*Zero width*/ 1'b0][3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_1 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][8]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_1 = _RANDOM[/*Zero width*/ 1'b0][9]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][10]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_1 = _RANDOM[/*Zero width*/ 1'b0][11]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][12]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_1 = _RANDOM[/*Zero width*/ 1'b0][13]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][14]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_1 = _RANDOM[/*Zero width*/ 1'b0][15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][16]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][17]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][18]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][19]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][20]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][21]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][22]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][23]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29 + state_reg = _RANDOM[/*Zero width*/ 1'b0][30:24]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + valids_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_0_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_4 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_5 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_6 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_7 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + state_reg = 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + CAMTemplate_32 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + .clock (clock), + .io_r_req_0_idx (io_write_idx), + .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), + .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), + .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), + .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), + .io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4), + .io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5), + .io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6), + .io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7), + .io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26} + .io_w_bits_data_idx (io_write_idx), + .io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12 + ); + data_mem_8x4 data_mem_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + .R0_addr (data_mem_io_hit_data_1_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 + .R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + .R0_clk (clock), + .R0_data (_data_mem_ext_R0_data), + .R1_addr (data_mem_io_hit_data_1_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 + .R1_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + .R1_clk (clock), + .R1_data (_data_mem_ext_R1_data), + .W0_addr (hit ? data_mem_io_hit_data_1_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29 + .W0_en (io_wen), + .W0_clk (clock), + .W0_data ({io_write_data_1, io_write_data_0}), // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + .W0_mask ({io_write_way_mask_1, io_write_way_mask_0}) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + ); + assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29 + assign io_hit_data_0_valid = + hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3 + & valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6 + & valids_6_0 | hits_oh_7 & valids_7_0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83 + assign io_hit_data_0_bits = _data_mem_ext_R1_data[1:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21 + assign io_hit_data_1_valid = + hits_oh_0 & valids_0_1 | hits_oh_1 & valids_1_1 | hits_oh_2 & valids_2_1 | hits_oh_3 + & valids_3_1 | hits_oh_4 & valids_4_1 | hits_oh_5 & valids_5_1 | hits_oh_6 + & valids_6_1 | hits_oh_7 & valids_7_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83 + assign io_hit_data_1_bits = _data_mem_ext_R0_data[3:2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21 +endmodule + diff --git a/src/WrBypass/WrBypass_33.sv b/src/WrBypass/WrBypass_33.sv new file mode 100644 index 0000000..de0d07d --- /dev/null +++ b/src/WrBypass/WrBypass_33.sv @@ -0,0 +1,583 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module WrBypass_33( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + input clock, + input reset, + input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input [7:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input [5:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input [5:0] io_write_data_1, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input io_write_way_mask_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input io_write_way_mask_1, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output io_hit_data_0_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output [5:0] io_hit_data_0_bits, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output io_hit_data_1_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output [5:0] io_hit_data_1_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 +); + + wire [11:0] _data_mem_ext_R0_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + wire [11:0] _data_mem_ext_R1_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_8; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_9; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_10; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_11; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_12; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_13; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_14; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_15; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + reg valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_7_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_8_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_8_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_9_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_9_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_10_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_10_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_11_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_11_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_12_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_12_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_13_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_13_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_14_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_14_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_15_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg valids_15_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23 + reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_8; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_9; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_10; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_11; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_12; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_13; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_14; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_15; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_8 = _idx_tag_cam_io_r_resp_0_8 & ever_written_8; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_9 = _idx_tag_cam_io_r_resp_0_9 & ever_written_9; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_10 = _idx_tag_cam_io_r_resp_0_10 & ever_written_10; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_11 = _idx_tag_cam_io_r_resp_0_11 & ever_written_11; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_12 = _idx_tag_cam_io_r_resp_0_12 & ever_written_12; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_13 = _idx_tag_cam_io_r_resp_0_13 & ever_written_13; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_14 = _idx_tag_cam_io_r_resp_0_14 & ever_written_14; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_15 = _idx_tag_cam_io_r_resp_0_15 & ever_written_15; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire [6:0] _hit_idx_T_2 = + {hits_oh_15, hits_oh_14, hits_oh_13, hits_oh_12, hits_oh_11, hits_oh_10, hits_oh_9} + | {hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4, hits_oh_3, hits_oh_2, hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + wire [2:0] _hit_idx_T_4 = _hit_idx_T_2[6:4] | _hit_idx_T_2[2:0]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28 + wire [3:0] data_mem_io_hit_data_1_bits_MPORT_addr = + {|{hits_oh_15, + hits_oh_14, + hits_oh_13, + hits_oh_12, + hits_oh_11, + hits_oh_10, + hits_oh_9, + hits_oh_8}, + |(_hit_idx_T_2[6:3]), + |(_hit_idx_T_4[2:1]), + _hit_idx_T_4[2] | _hit_idx_T_4[0]}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + wire hit = + hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6 + | hits_oh_7 | hits_oh_8 | hits_oh_9 | hits_oh_10 | hits_oh_11 | hits_oh_12 + | hits_oh_13 | hits_oh_14 | hits_oh_15; // src/main/scala/xiangshan/frontend/WrBypass.scala:61:83, :63:29 + reg [14:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + wire [3:0] enq_idx = + {state_reg[14], + state_reg[14] + ? {state_reg[13], + state_reg[13] + ? {state_reg[12], state_reg[12] ? state_reg[11] : state_reg[10]} + : {state_reg[9], state_reg[9] ? state_reg[8] : state_reg[7]}} + : {state_reg[6], + state_reg[6] + ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]} + : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13 + wire _GEN = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h0; // src/main/scala/chisel3/util/OneHot.scala:32:{10,14}, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_0 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h1; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_1 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h2; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_2 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h3; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_3 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h4; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_4 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h5; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_5 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h6; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_6 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h7; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_7 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h8; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_8 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'h9; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_9 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hA; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_10 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hB; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_11 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hC; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_12 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hD; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire _GEN_13 = data_mem_io_hit_data_1_bits_MPORT_addr == 4'hE; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30 + wire [3:0] state_reg_touch_way_sized = + hit ? data_mem_io_hit_data_1_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37 + wire _GEN_14 = enq_idx == 4'h0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:98:31 + wire _GEN_15 = enq_idx == 4'h1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_16 = enq_idx == 4'h2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_17 = enq_idx == 4'h3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_18 = enq_idx == 4'h4; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_19 = enq_idx == 4'h5; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_20 = enq_idx == 4'h6; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_21 = enq_idx == 4'h7; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_22 = enq_idx == 4'h8; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_23 = enq_idx == 4'h9; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_24 = enq_idx == 4'hA; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_25 = enq_idx == 4'hB; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_26 = enq_idx == 4'hC; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_27 = enq_idx == 4'hD; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + wire _GEN_28 = enq_idx == 4'hE; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31 + always @(posedge clock or posedge reset) begin + if (reset) begin + valids_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_0_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_8_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_8_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_9_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_9_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_10_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_10_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_11_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_11_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_12_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_12_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_13_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_13_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_14_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_14_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_15_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_15_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_4 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_5 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_6 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_7 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_8 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_9 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_10 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_11 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_12 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_13 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_14 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_15 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + state_reg <= 15'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + end + else begin + if (io_wen) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + if (hit) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29 + valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_7_0 <= io_write_way_mask_0 & _GEN_6 | valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_7_1 <= io_write_way_mask_1 & _GEN_6 | valids_7_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_8_0 <= io_write_way_mask_0 & _GEN_7 | valids_8_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_8_1 <= io_write_way_mask_1 & _GEN_7 | valids_8_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_9_0 <= io_write_way_mask_0 & _GEN_8 | valids_9_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_9_1 <= io_write_way_mask_1 & _GEN_8 | valids_9_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_10_0 <= io_write_way_mask_0 & _GEN_9 | valids_10_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_10_1 <= io_write_way_mask_1 & _GEN_9 | valids_10_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_11_0 <= io_write_way_mask_0 & _GEN_10 | valids_11_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_11_1 <= io_write_way_mask_1 & _GEN_10 | valids_11_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_12_0 <= io_write_way_mask_0 & _GEN_11 | valids_12_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_12_1 <= io_write_way_mask_1 & _GEN_11 | valids_12_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_13_0 <= io_write_way_mask_0 & _GEN_12 | valids_13_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_13_1 <= io_write_way_mask_1 & _GEN_12 | valids_13_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_14_0 <= io_write_way_mask_0 & _GEN_13 | valids_14_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_14_1 <= io_write_way_mask_1 & _GEN_13 | valids_14_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_15_0 <= + io_write_way_mask_0 & (&data_mem_io_hit_data_1_bits_MPORT_addr) | valids_15_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + valids_15_1 <= + io_write_way_mask_1 & (&data_mem_io_hit_data_1_bits_MPORT_addr) | valids_15_1; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :94:35, :95:30 + end + else begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29 + valids_0_0 <= io_write_way_mask_0 & _GEN_14 | ~_GEN_14 & valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_0_1 <= io_write_way_mask_1 & _GEN_14 | ~_GEN_14 & valids_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_1_0 <= io_write_way_mask_0 & _GEN_15 | ~_GEN_15 & valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_1_1 <= io_write_way_mask_1 & _GEN_15 | ~_GEN_15 & valids_1_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_2_0 <= io_write_way_mask_0 & _GEN_16 | ~_GEN_16 & valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_2_1 <= io_write_way_mask_1 & _GEN_16 | ~_GEN_16 & valids_2_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_3_0 <= io_write_way_mask_0 & _GEN_17 | ~_GEN_17 & valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_3_1 <= io_write_way_mask_1 & _GEN_17 | ~_GEN_17 & valids_3_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_4_0 <= io_write_way_mask_0 & _GEN_18 | ~_GEN_18 & valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_4_1 <= io_write_way_mask_1 & _GEN_18 | ~_GEN_18 & valids_4_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_5_0 <= io_write_way_mask_0 & _GEN_19 | ~_GEN_19 & valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_5_1 <= io_write_way_mask_1 & _GEN_19 | ~_GEN_19 & valids_5_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_6_0 <= io_write_way_mask_0 & _GEN_20 | ~_GEN_20 & valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_6_1 <= io_write_way_mask_1 & _GEN_20 | ~_GEN_20 & valids_6_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_7_0 <= io_write_way_mask_0 & _GEN_21 | ~_GEN_21 & valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_7_1 <= io_write_way_mask_1 & _GEN_21 | ~_GEN_21 & valids_7_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_8_0 <= io_write_way_mask_0 & _GEN_22 | ~_GEN_22 & valids_8_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_8_1 <= io_write_way_mask_1 & _GEN_22 | ~_GEN_22 & valids_8_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_9_0 <= io_write_way_mask_0 & _GEN_23 | ~_GEN_23 & valids_9_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_9_1 <= io_write_way_mask_1 & _GEN_23 | ~_GEN_23 & valids_9_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_10_0 <= io_write_way_mask_0 & _GEN_24 | ~_GEN_24 & valids_10_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_10_1 <= io_write_way_mask_1 & _GEN_24 | ~_GEN_24 & valids_10_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_11_0 <= io_write_way_mask_0 & _GEN_25 | ~_GEN_25 & valids_11_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_11_1 <= io_write_way_mask_1 & _GEN_25 | ~_GEN_25 & valids_11_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_12_0 <= io_write_way_mask_0 & _GEN_26 | ~_GEN_26 & valids_12_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_12_1 <= io_write_way_mask_1 & _GEN_26 | ~_GEN_26 & valids_12_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_13_0 <= io_write_way_mask_0 & _GEN_27 | ~_GEN_27 & valids_13_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_13_1 <= io_write_way_mask_1 & _GEN_27 | ~_GEN_27 & valids_13_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_14_0 <= io_write_way_mask_0 & _GEN_28 | ~_GEN_28 & valids_14_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_14_1 <= io_write_way_mask_1 & _GEN_28 | ~_GEN_28 & valids_14_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_15_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_15_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + valids_15_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_15_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :100:35, :101:30 + end + state_reg <= + {~(state_reg_touch_way_sized[3]), + state_reg_touch_way_sized[3] + ? {~(state_reg_touch_way_sized[2]), + state_reg_touch_way_sized[2] + ? {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[11], + state_reg_touch_way_sized[1] + ? state_reg[10] + : ~(state_reg_touch_way_sized[0])} + : state_reg[12:10], + state_reg_touch_way_sized[2] + ? state_reg[9:7] + : {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[8], + state_reg_touch_way_sized[1] + ? state_reg[7] + : ~(state_reg_touch_way_sized[0])}} + : state_reg[13:7], + state_reg_touch_way_sized[3] + ? state_reg[6:0] + : {~(state_reg_touch_way_sized[2]), + state_reg_touch_way_sized[2] + ? {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[4], + state_reg_touch_way_sized[1] + ? state_reg[3] + : ~(state_reg_touch_way_sized[0])} + : state_reg[5:3], + state_reg_touch_way_sized[2] + ? state_reg[2:0] + : {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[1], + state_reg_touch_way_sized[1] + ? state_reg[0] + : ~(state_reg_touch_way_sized[0])}}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37 + end + ever_written_0 <= io_wen & ~hit & (_GEN_14 | io_wen & _GEN_14) | ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_1 <= io_wen & ~hit & (_GEN_15 | io_wen & _GEN_15) | ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_2 <= io_wen & ~hit & (_GEN_16 | io_wen & _GEN_16) | ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_3 <= io_wen & ~hit & (_GEN_17 | io_wen & _GEN_17) | ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_4 <= io_wen & ~hit & (_GEN_18 | io_wen & _GEN_18) | ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_5 <= io_wen & ~hit & (_GEN_19 | io_wen & _GEN_19) | ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_6 <= io_wen & ~hit & (_GEN_20 | io_wen & _GEN_20) | ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_7 <= io_wen & ~hit & (_GEN_21 | io_wen & _GEN_21) | ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_8 <= io_wen & ~hit & (_GEN_22 | io_wen & _GEN_22) | ever_written_8; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_9 <= io_wen & ~hit & (_GEN_23 | io_wen & _GEN_23) | ever_written_9; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_10 <= io_wen & ~hit & (_GEN_24 | io_wen & _GEN_24) | ever_written_10; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_11 <= io_wen & ~hit & (_GEN_25 | io_wen & _GEN_25) | ever_written_11; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_12 <= io_wen & ~hit & (_GEN_26 | io_wen & _GEN_26) | ever_written_12; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_13 <= io_wen & ~hit & (_GEN_27 | io_wen & _GEN_27) | ever_written_13; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_14 <= io_wen & ~hit & (_GEN_28 | io_wen & _GEN_28) | ever_written_14; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_15 <= + io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_15; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + end // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + valids_0_0 = _RANDOM[1'h0][0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_0_1 = _RANDOM[1'h0][1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_0 = _RANDOM[1'h0][2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_1 = _RANDOM[1'h0][3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_0 = _RANDOM[1'h0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_1 = _RANDOM[1'h0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_0 = _RANDOM[1'h0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_1 = _RANDOM[1'h0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_0 = _RANDOM[1'h0][8]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_1 = _RANDOM[1'h0][9]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_0 = _RANDOM[1'h0][10]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_1 = _RANDOM[1'h0][11]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_0 = _RANDOM[1'h0][12]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_1 = _RANDOM[1'h0][13]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_0 = _RANDOM[1'h0][14]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_1 = _RANDOM[1'h0][15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_8_0 = _RANDOM[1'h0][16]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_8_1 = _RANDOM[1'h0][17]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_9_0 = _RANDOM[1'h0][18]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_9_1 = _RANDOM[1'h0][19]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_10_0 = _RANDOM[1'h0][20]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_10_1 = _RANDOM[1'h0][21]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_11_0 = _RANDOM[1'h0][22]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_11_1 = _RANDOM[1'h0][23]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_12_0 = _RANDOM[1'h0][24]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_12_1 = _RANDOM[1'h0][25]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_13_0 = _RANDOM[1'h0][26]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_13_1 = _RANDOM[1'h0][27]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_14_0 = _RANDOM[1'h0][28]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_14_1 = _RANDOM[1'h0][29]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_15_0 = _RANDOM[1'h0][30]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_15_1 = _RANDOM[1'h0][31]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + ever_written_0 = _RANDOM[1'h1][0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_1 = _RANDOM[1'h1][1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_2 = _RANDOM[1'h1][2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_3 = _RANDOM[1'h1][3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_4 = _RANDOM[1'h1][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_5 = _RANDOM[1'h1][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_6 = _RANDOM[1'h1][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_7 = _RANDOM[1'h1][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_8 = _RANDOM[1'h1][8]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_9 = _RANDOM[1'h1][9]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_10 = _RANDOM[1'h1][10]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_11 = _RANDOM[1'h1][11]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_12 = _RANDOM[1'h1][12]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_13 = _RANDOM[1'h1][13]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_14 = _RANDOM[1'h1][14]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_15 = _RANDOM[1'h1][15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + state_reg = _RANDOM[1'h1][30:16]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + valids_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_0_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_1_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_2_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_3_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_4_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_5_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_6_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_7_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_8_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_8_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_9_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_9_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_10_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_10_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_11_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_11_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_12_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_12_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_13_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_13_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_14_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_14_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_15_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + valids_15_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23 + ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_4 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_5 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_6 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_7 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_8 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_9 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_10 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_11 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_12 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_13 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_14 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_15 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + state_reg = 15'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + CAMTemplate_33 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + .clock (clock), + .io_r_req_0_idx (io_write_idx), + .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), + .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), + .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), + .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), + .io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4), + .io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5), + .io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6), + .io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7), + .io_r_resp_0_8 (_idx_tag_cam_io_r_resp_0_8), + .io_r_resp_0_9 (_idx_tag_cam_io_r_resp_0_9), + .io_r_resp_0_10 (_idx_tag_cam_io_r_resp_0_10), + .io_r_resp_0_11 (_idx_tag_cam_io_r_resp_0_11), + .io_r_resp_0_12 (_idx_tag_cam_io_r_resp_0_12), + .io_r_resp_0_13 (_idx_tag_cam_io_r_resp_0_13), + .io_r_resp_0_14 (_idx_tag_cam_io_r_resp_0_14), + .io_r_resp_0_15 (_idx_tag_cam_io_r_resp_0_15), + .io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26} + .io_w_bits_data_idx (io_write_idx), + .io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12 + ); + data_mem_16x12 data_mem_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + .R0_addr (data_mem_io_hit_data_1_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 + .R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + .R0_clk (clock), + .R0_data (_data_mem_ext_R0_data), + .R1_addr (data_mem_io_hit_data_1_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 + .R1_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + .R1_clk (clock), + .R1_data (_data_mem_ext_R1_data), + .W0_addr (hit ? data_mem_io_hit_data_1_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29 + .W0_en (io_wen), + .W0_clk (clock), + .W0_data ({io_write_data_1, io_write_data_0}), // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + .W0_mask ({io_write_way_mask_1, io_write_way_mask_0}) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + ); + assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29 + assign io_hit_data_0_valid = + hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3 + & valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6 + & valids_6_0 | hits_oh_7 & valids_7_0 | hits_oh_8 & valids_8_0 | hits_oh_9 + & valids_9_0 | hits_oh_10 & valids_10_0 | hits_oh_11 & valids_11_0 | hits_oh_12 + & valids_12_0 | hits_oh_13 & valids_13_0 | hits_oh_14 & valids_14_0 | hits_oh_15 + & valids_15_0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83 + assign io_hit_data_0_bits = _data_mem_ext_R1_data[5:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21 + assign io_hit_data_1_valid = + hits_oh_0 & valids_0_1 | hits_oh_1 & valids_1_1 | hits_oh_2 & valids_2_1 | hits_oh_3 + & valids_3_1 | hits_oh_4 & valids_4_1 | hits_oh_5 & valids_5_1 | hits_oh_6 + & valids_6_1 | hits_oh_7 & valids_7_1 | hits_oh_8 & valids_8_1 | hits_oh_9 + & valids_9_1 | hits_oh_10 & valids_10_1 | hits_oh_11 & valids_11_1 | hits_oh_12 + & valids_12_1 | hits_oh_13 & valids_13_1 | hits_oh_14 & valids_14_1 | hits_oh_15 + & valids_15_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83 + assign io_hit_data_1_bits = _data_mem_ext_R0_data[11:6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :54:21 +endmodule + diff --git a/src/WrBypass/WrBypass_41.sv b/src/WrBypass/WrBypass_41.sv new file mode 100644 index 0000000..420c0ae --- /dev/null +++ b/src/WrBypass/WrBypass_41.sv @@ -0,0 +1,159 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module WrBypass_41( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + input clock, + input reset, + input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input [7:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input [1:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output [1:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 +); + + wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire [1:0] data_mem_io_hit_data_0_bits_MPORT_addr = + {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + wire hit = + _idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29 + reg [2:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13 + wire [1:0] state_reg_touch_way_sized = + hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37 + always @(posedge clock or posedge reset) begin + if (reset) begin + ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + state_reg <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + end + else begin + ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31 + ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31 + ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + if (io_wen) // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + state_reg <= + {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1], + state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37 + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + state_reg = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + CAMTemplate_41 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + .clock (clock), + .io_r_req_0_idx (io_write_idx), + .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), + .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), + .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), + .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), + .io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26} + .io_w_bits_data_idx (io_write_idx), + .io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12 + ); + data_mem_0_4x2 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + .R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 + .R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + .R0_clk (clock), + .R0_data (io_hit_data_0_bits), + .W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29 + .W0_en (io_wen), + .W0_clk (clock), + .W0_data (io_write_data_0) + ); + assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29 +endmodule + diff --git a/src/WrBypass/WrBypass_43.sv b/src/WrBypass/WrBypass_43.sv new file mode 100644 index 0000000..b3782c0 --- /dev/null +++ b/src/WrBypass/WrBypass_43.sv @@ -0,0 +1,159 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module WrBypass_43( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + input clock, + input reset, + input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input [8:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + input [1:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + output [1:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 +); + + wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29 + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83 + wire [1:0] data_mem_io_hit_data_0_bits_MPORT_addr = + {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83 + wire hit = + _idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29 + reg [2:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13 + wire [1:0] state_reg_touch_way_sized = + hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37 + always @(posedge clock or posedge reset) begin + if (reset) begin + ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + state_reg <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + end + else begin + ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31 + ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31 + ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31 + if (io_wen) // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14 + state_reg <= + {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1], + state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37 + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29 + state_reg = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + CAMTemplate_43 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27 + .clock (clock), + .io_r_req_0_idx (io_write_idx), + .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), + .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), + .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), + .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), + .io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26} + .io_w_bits_data_idx (io_write_idx), + .io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12 + ); + data_mem_0_4x2 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21 + .R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10 + .R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7 + .R0_clk (clock), + .R0_data (io_hit_data_0_bits), + .W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29 + .W0_en (io_wen), + .W0_clk (clock), + .W0_data (io_write_data_0) + ); + assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29 +endmodule + diff --git a/src/common/Composer.sv b/src/common/Composer.sv new file mode 100644 index 0000000..7f5bb6b --- /dev/null +++ b/src/common/Composer.sv @@ -0,0 +1,2334 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module Composer( // src/main/scala/xiangshan/frontend/Composer.scala:26:7 + input clock, + input reset, + input [35:0] io_reset_vector, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [10:0] io_in_bits_folded_hist_1_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [10:0] io_in_bits_folded_hist_1_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_in_bits_folded_hist_1_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_1_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_in_bits_folded_hist_1_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_1_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_in_bits_folded_hist_1_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_in_bits_folded_hist_1_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_1_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_1_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [10:0] io_in_bits_folded_hist_1_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_3_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [8:0] io_in_bits_folded_hist_3_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_3_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [8:0] io_in_bits_folded_hist_3_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [8:0] io_in_bits_folded_hist_3_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_3_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_3_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_spec_info_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [1:0] io_out_last_stage_spec_info_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_spec_info_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [4:0] io_out_last_stage_spec_info_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_spec_info_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [4:0] io_out_last_stage_spec_info_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_spec_info_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [4:0] io_out_last_stage_spec_info_NOS_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_last_stage_spec_info_topAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_ctrl_ubtb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_ctrl_btb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_ctrl_tage_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_ctrl_sc_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_ctrl_ras_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s3_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s3_redirect_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_s1_ready, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [10:0] io_update_bits_spec_info_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [10:0] io_update_bits_spec_info_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_update_bits_spec_info_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [8:0] io_update_bits_spec_info_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [8:0] io_update_bits_spec_info_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_update_bits_spec_info_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_update_bits_spec_info_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [8:0] io_update_bits_spec_info_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [6:0] io_update_bits_spec_info_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [10:0] io_update_bits_spec_info_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [11:0] io_update_bits_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [19:0] io_update_bits_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_cfi_idx_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_cfi_idx_bits, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_jmp_taken, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_mispred_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_mispred_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_mispred_mask_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_old_entry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [218:0] io_update_bits_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_update_bits_full_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_level, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_redirect_bits_cfiUpdate_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_cfiUpdate_pd_isRVC, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_cfiUpdate_pd_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_cfiUpdate_pd_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_redirect_bits_cfiUpdate_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [1:0] io_redirect_bits_cfiUpdate_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_cfiUpdate_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [4:0] io_redirect_bits_cfiUpdate_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_cfiUpdate_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [4:0] io_redirect_bits_cfiUpdate_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_cfiUpdate_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [4:0] io_redirect_bits_cfiUpdate_NOS_value // src/main/scala/xiangshan/frontend/BPU.scala:171:14 +); + + wire _ras_io_ctrl_delay_io_out_ras_enable; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _ftb_io_ctrl_delay_io_out_btb_enable; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _tage_io_ctrl_delay_io_out_tage_enable; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _tage_io_ctrl_delay_io_out_sc_enable; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _ubtb_io_ctrl_delay_io_out_ubtb_enable; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _ittage_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_0_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [3:0] _ittage_io_out_s2_full_pred_0_offsets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [3:0] _ittage_io_out_s2_full_pred_0_offsets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_1_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [3:0] _ittage_io_out_s2_full_pred_1_offsets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [3:0] _ittage_io_out_s2_full_pred_1_offsets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_2_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [3:0] _ittage_io_out_s2_full_pred_2_offsets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [3:0] _ittage_io_out_s2_full_pred_2_offsets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_2_is_jalr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_2_is_call; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_2_is_ret; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_2_last_may_be_rvi_call; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_3_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [3:0] _ittage_io_out_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [3:0] _ittage_io_out_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_0_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_0_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_0_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_0_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_0_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_1_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_1_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_1_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_1_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_2_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_2_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_2_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_2_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_2_is_jalr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_2_is_call; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_2_is_ret; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_3_jalr_target; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [3:0] _ittage_io_out_s3_full_pred_3_offsets_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [3:0] _ittage_io_out_s3_full_pred_3_offsets_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [38:0] _ittage_io_out_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [218:0] _ittage_io_out_last_stage_meta; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_last_stage_ftb_entry_valid; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [3:0] _ittage_io_out_last_stage_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [11:0] _ittage_io_out_last_stage_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [1:0] _ittage_io_out_last_stage_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_last_stage_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_last_stage_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [3:0] _ittage_io_out_last_stage_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [19:0] _ittage_io_out_last_stage_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [1:0] _ittage_io_out_last_stage_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_last_stage_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_last_stage_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [3:0] _ittage_io_out_last_stage_ftb_entry_pftAddr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_last_stage_ftb_entry_carry; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_last_stage_ftb_entry_isCall; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_last_stage_ftb_entry_isRet; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_last_stage_ftb_entry_isJalr; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_last_stage_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_last_stage_ftb_entry_always_taken_0; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire _ittage_io_out_last_stage_ftb_entry_always_taken_1; // src/main/scala/xiangshan/Parameters.scala:113:26 + wire [218:0] _ras_io_out_last_stage_meta; // src/main/scala/xiangshan/Parameters.scala:112:23 + wire _tage_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire [218:0] _tage_io_out_last_stage_meta; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire _tage_io_s1_ready; // src/main/scala/xiangshan/Parameters.scala:111:24 + wire [218:0] _ubtb_io_out_last_stage_meta; // src/main/scala/xiangshan/Parameters.scala:109:23 + wire _ftb_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_0_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [3:0] _ftb_io_out_s2_full_pred_0_offsets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [3:0] _ftb_io_out_s2_full_pred_0_offsets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_1_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [3:0] _ftb_io_out_s2_full_pred_1_offsets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [3:0] _ftb_io_out_s2_full_pred_1_offsets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_2_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [3:0] _ftb_io_out_s2_full_pred_2_offsets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [3:0] _ftb_io_out_s2_full_pred_2_offsets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_2_is_jalr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_2_is_call; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_2_is_ret; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_2_last_may_be_rvi_call; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_3_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [3:0] _ftb_io_out_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [3:0] _ftb_io_out_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_0_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_0_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_0_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_0_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_0_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_1_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_1_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_1_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_1_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_2_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_2_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_2_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_2_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_2_is_jalr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_2_is_call; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_2_is_ret; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_3_jalr_target; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [3:0] _ftb_io_out_s3_full_pred_3_offsets_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [3:0] _ftb_io_out_s3_full_pred_3_offsets_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [38:0] _ftb_io_out_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [218:0] _ftb_io_out_last_stage_meta; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_last_stage_ftb_entry_valid; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [3:0] _ftb_io_out_last_stage_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [11:0] _ftb_io_out_last_stage_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [1:0] _ftb_io_out_last_stage_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_last_stage_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_last_stage_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [3:0] _ftb_io_out_last_stage_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [19:0] _ftb_io_out_last_stage_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [1:0] _ftb_io_out_last_stage_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_last_stage_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_last_stage_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire [3:0] _ftb_io_out_last_stage_ftb_entry_pftAddr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_last_stage_ftb_entry_carry; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_last_stage_ftb_entry_isCall; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_last_stage_ftb_entry_isRet; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_last_stage_ftb_entry_isJalr; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_last_stage_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_last_stage_ftb_entry_always_taken_0; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_out_last_stage_ftb_entry_always_taken_1; // src/main/scala/xiangshan/Parameters.scala:108:23 + wire _ftb_io_s1_ready; // src/main/scala/xiangshan/Parameters.scala:108:23 + FTB ftb ( // src/main/scala/xiangshan/Parameters.scala:108:23 + .clock (clock), + .reset (reset), + .io_reset_vector (io_reset_vector), + .io_in_bits_s0_pc_0 (io_in_bits_s0_pc_0), + .io_in_bits_s0_pc_1 (io_in_bits_s0_pc_1), + .io_in_bits_s0_pc_2 (io_in_bits_s0_pc_2), + .io_in_bits_s0_pc_3 (io_in_bits_s0_pc_3), + .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 + (_tage_io_out_s2_full_pred_0_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 + (_tage_io_out_s2_full_pred_0_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 + (_tage_io_out_s2_full_pred_1_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 + (_tage_io_out_s2_full_pred_1_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 + (_tage_io_out_s2_full_pred_2_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 + (_tage_io_out_s2_full_pred_2_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 + (_tage_io_out_s2_full_pred_3_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 + (_tage_io_out_s2_full_pred_3_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 + (_tage_io_out_s3_full_pred_0_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 + (_tage_io_out_s3_full_pred_0_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 + (_tage_io_out_s3_full_pred_1_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 + (_tage_io_out_s3_full_pred_1_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 + (_tage_io_out_s3_full_pred_2_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 + (_tage_io_out_s3_full_pred_2_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 + (_tage_io_out_s3_full_pred_3_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 + (_tage_io_out_s3_full_pred_3_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:111:24 + .io_out_s2_full_pred_0_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_0_br_taken_mask_0), + .io_out_s2_full_pred_0_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_0_br_taken_mask_1), + .io_out_s2_full_pred_0_slot_valids_0 + (_ftb_io_out_s2_full_pred_0_slot_valids_0), + .io_out_s2_full_pred_0_slot_valids_1 + (_ftb_io_out_s2_full_pred_0_slot_valids_1), + .io_out_s2_full_pred_0_targets_0 + (_ftb_io_out_s2_full_pred_0_targets_0), + .io_out_s2_full_pred_0_targets_1 + (_ftb_io_out_s2_full_pred_0_targets_1), + .io_out_s2_full_pred_0_jalr_target + (_ftb_io_out_s2_full_pred_0_jalr_target), + .io_out_s2_full_pred_0_offsets_0 + (_ftb_io_out_s2_full_pred_0_offsets_0), + .io_out_s2_full_pred_0_offsets_1 + (_ftb_io_out_s2_full_pred_0_offsets_1), + .io_out_s2_full_pred_0_fallThroughAddr + (_ftb_io_out_s2_full_pred_0_fallThroughAddr), + .io_out_s2_full_pred_0_is_br_sharing + (_ftb_io_out_s2_full_pred_0_is_br_sharing), + .io_out_s2_full_pred_0_hit (_ftb_io_out_s2_full_pred_0_hit), + .io_out_s2_full_pred_1_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_1_br_taken_mask_0), + .io_out_s2_full_pred_1_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_1_br_taken_mask_1), + .io_out_s2_full_pred_1_slot_valids_0 + (_ftb_io_out_s2_full_pred_1_slot_valids_0), + .io_out_s2_full_pred_1_slot_valids_1 + (_ftb_io_out_s2_full_pred_1_slot_valids_1), + .io_out_s2_full_pred_1_targets_0 + (_ftb_io_out_s2_full_pred_1_targets_0), + .io_out_s2_full_pred_1_targets_1 + (_ftb_io_out_s2_full_pred_1_targets_1), + .io_out_s2_full_pred_1_jalr_target + (_ftb_io_out_s2_full_pred_1_jalr_target), + .io_out_s2_full_pred_1_offsets_0 + (_ftb_io_out_s2_full_pred_1_offsets_0), + .io_out_s2_full_pred_1_offsets_1 + (_ftb_io_out_s2_full_pred_1_offsets_1), + .io_out_s2_full_pred_1_fallThroughAddr + (_ftb_io_out_s2_full_pred_1_fallThroughAddr), + .io_out_s2_full_pred_1_is_br_sharing + (_ftb_io_out_s2_full_pred_1_is_br_sharing), + .io_out_s2_full_pred_1_hit (_ftb_io_out_s2_full_pred_1_hit), + .io_out_s2_full_pred_2_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_2_br_taken_mask_0), + .io_out_s2_full_pred_2_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_2_br_taken_mask_1), + .io_out_s2_full_pred_2_slot_valids_0 + (_ftb_io_out_s2_full_pred_2_slot_valids_0), + .io_out_s2_full_pred_2_slot_valids_1 + (_ftb_io_out_s2_full_pred_2_slot_valids_1), + .io_out_s2_full_pred_2_targets_0 + (_ftb_io_out_s2_full_pred_2_targets_0), + .io_out_s2_full_pred_2_targets_1 + (_ftb_io_out_s2_full_pred_2_targets_1), + .io_out_s2_full_pred_2_jalr_target + (_ftb_io_out_s2_full_pred_2_jalr_target), + .io_out_s2_full_pred_2_offsets_0 + (_ftb_io_out_s2_full_pred_2_offsets_0), + .io_out_s2_full_pred_2_offsets_1 + (_ftb_io_out_s2_full_pred_2_offsets_1), + .io_out_s2_full_pred_2_fallThroughAddr + (_ftb_io_out_s2_full_pred_2_fallThroughAddr), + .io_out_s2_full_pred_2_is_jalr + (_ftb_io_out_s2_full_pred_2_is_jalr), + .io_out_s2_full_pred_2_is_call + (_ftb_io_out_s2_full_pred_2_is_call), + .io_out_s2_full_pred_2_is_ret + (_ftb_io_out_s2_full_pred_2_is_ret), + .io_out_s2_full_pred_2_last_may_be_rvi_call + (_ftb_io_out_s2_full_pred_2_last_may_be_rvi_call), + .io_out_s2_full_pred_2_is_br_sharing + (_ftb_io_out_s2_full_pred_2_is_br_sharing), + .io_out_s2_full_pred_2_hit (_ftb_io_out_s2_full_pred_2_hit), + .io_out_s2_full_pred_3_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_3_br_taken_mask_0), + .io_out_s2_full_pred_3_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_3_br_taken_mask_1), + .io_out_s2_full_pred_3_slot_valids_0 + (_ftb_io_out_s2_full_pred_3_slot_valids_0), + .io_out_s2_full_pred_3_slot_valids_1 + (_ftb_io_out_s2_full_pred_3_slot_valids_1), + .io_out_s2_full_pred_3_targets_0 + (_ftb_io_out_s2_full_pred_3_targets_0), + .io_out_s2_full_pred_3_targets_1 + (_ftb_io_out_s2_full_pred_3_targets_1), + .io_out_s2_full_pred_3_jalr_target + (_ftb_io_out_s2_full_pred_3_jalr_target), + .io_out_s2_full_pred_3_offsets_0 + (_ftb_io_out_s2_full_pred_3_offsets_0), + .io_out_s2_full_pred_3_offsets_1 + (_ftb_io_out_s2_full_pred_3_offsets_1), + .io_out_s2_full_pred_3_fallThroughAddr + (_ftb_io_out_s2_full_pred_3_fallThroughAddr), + .io_out_s2_full_pred_3_fallThroughErr + (_ftb_io_out_s2_full_pred_3_fallThroughErr), + .io_out_s2_full_pred_3_is_br_sharing + (_ftb_io_out_s2_full_pred_3_is_br_sharing), + .io_out_s2_full_pred_3_hit (_ftb_io_out_s2_full_pred_3_hit), + .io_out_s3_full_pred_0_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_0_br_taken_mask_0), + .io_out_s3_full_pred_0_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_0_br_taken_mask_1), + .io_out_s3_full_pred_0_slot_valids_0 + (_ftb_io_out_s3_full_pred_0_slot_valids_0), + .io_out_s3_full_pred_0_slot_valids_1 + (_ftb_io_out_s3_full_pred_0_slot_valids_1), + .io_out_s3_full_pred_0_targets_0 + (_ftb_io_out_s3_full_pred_0_targets_0), + .io_out_s3_full_pred_0_targets_1 + (_ftb_io_out_s3_full_pred_0_targets_1), + .io_out_s3_full_pred_0_jalr_target + (_ftb_io_out_s3_full_pred_0_jalr_target), + .io_out_s3_full_pred_0_fallThroughAddr + (_ftb_io_out_s3_full_pred_0_fallThroughAddr), + .io_out_s3_full_pred_0_fallThroughErr + (_ftb_io_out_s3_full_pred_0_fallThroughErr), + .io_out_s3_full_pred_0_is_br_sharing + (_ftb_io_out_s3_full_pred_0_is_br_sharing), + .io_out_s3_full_pred_0_hit (_ftb_io_out_s3_full_pred_0_hit), + .io_out_s3_full_pred_1_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_1_br_taken_mask_0), + .io_out_s3_full_pred_1_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_1_br_taken_mask_1), + .io_out_s3_full_pred_1_slot_valids_0 + (_ftb_io_out_s3_full_pred_1_slot_valids_0), + .io_out_s3_full_pred_1_slot_valids_1 + (_ftb_io_out_s3_full_pred_1_slot_valids_1), + .io_out_s3_full_pred_1_targets_0 + (_ftb_io_out_s3_full_pred_1_targets_0), + .io_out_s3_full_pred_1_targets_1 + (_ftb_io_out_s3_full_pred_1_targets_1), + .io_out_s3_full_pred_1_jalr_target + (_ftb_io_out_s3_full_pred_1_jalr_target), + .io_out_s3_full_pred_1_fallThroughAddr + (_ftb_io_out_s3_full_pred_1_fallThroughAddr), + .io_out_s3_full_pred_1_fallThroughErr + (_ftb_io_out_s3_full_pred_1_fallThroughErr), + .io_out_s3_full_pred_1_is_br_sharing + (_ftb_io_out_s3_full_pred_1_is_br_sharing), + .io_out_s3_full_pred_1_hit (_ftb_io_out_s3_full_pred_1_hit), + .io_out_s3_full_pred_2_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_2_br_taken_mask_0), + .io_out_s3_full_pred_2_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_2_br_taken_mask_1), + .io_out_s3_full_pred_2_slot_valids_0 + (_ftb_io_out_s3_full_pred_2_slot_valids_0), + .io_out_s3_full_pred_2_slot_valids_1 + (_ftb_io_out_s3_full_pred_2_slot_valids_1), + .io_out_s3_full_pred_2_targets_0 + (_ftb_io_out_s3_full_pred_2_targets_0), + .io_out_s3_full_pred_2_targets_1 + (_ftb_io_out_s3_full_pred_2_targets_1), + .io_out_s3_full_pred_2_jalr_target + (_ftb_io_out_s3_full_pred_2_jalr_target), + .io_out_s3_full_pred_2_fallThroughAddr + (_ftb_io_out_s3_full_pred_2_fallThroughAddr), + .io_out_s3_full_pred_2_fallThroughErr + (_ftb_io_out_s3_full_pred_2_fallThroughErr), + .io_out_s3_full_pred_2_is_jalr + (_ftb_io_out_s3_full_pred_2_is_jalr), + .io_out_s3_full_pred_2_is_call + (_ftb_io_out_s3_full_pred_2_is_call), + .io_out_s3_full_pred_2_is_ret + (_ftb_io_out_s3_full_pred_2_is_ret), + .io_out_s3_full_pred_2_is_br_sharing + (_ftb_io_out_s3_full_pred_2_is_br_sharing), + .io_out_s3_full_pred_2_hit (_ftb_io_out_s3_full_pred_2_hit), + .io_out_s3_full_pred_3_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_3_br_taken_mask_0), + .io_out_s3_full_pred_3_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_3_br_taken_mask_1), + .io_out_s3_full_pred_3_slot_valids_0 + (_ftb_io_out_s3_full_pred_3_slot_valids_0), + .io_out_s3_full_pred_3_slot_valids_1 + (_ftb_io_out_s3_full_pred_3_slot_valids_1), + .io_out_s3_full_pred_3_targets_0 + (_ftb_io_out_s3_full_pred_3_targets_0), + .io_out_s3_full_pred_3_targets_1 + (_ftb_io_out_s3_full_pred_3_targets_1), + .io_out_s3_full_pred_3_jalr_target + (_ftb_io_out_s3_full_pred_3_jalr_target), + .io_out_s3_full_pred_3_offsets_0 + (_ftb_io_out_s3_full_pred_3_offsets_0), + .io_out_s3_full_pred_3_offsets_1 + (_ftb_io_out_s3_full_pred_3_offsets_1), + .io_out_s3_full_pred_3_fallThroughAddr + (_ftb_io_out_s3_full_pred_3_fallThroughAddr), + .io_out_s3_full_pred_3_fallThroughErr + (_ftb_io_out_s3_full_pred_3_fallThroughErr), + .io_out_s3_full_pred_3_is_br_sharing + (_ftb_io_out_s3_full_pred_3_is_br_sharing), + .io_out_s3_full_pred_3_hit (_ftb_io_out_s3_full_pred_3_hit), + .io_out_last_stage_meta (_ftb_io_out_last_stage_meta), + .io_out_last_stage_ftb_entry_valid + (_ftb_io_out_last_stage_ftb_entry_valid), + .io_out_last_stage_ftb_entry_brSlots_0_offset + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_offset), + .io_out_last_stage_ftb_entry_brSlots_0_lower + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_lower), + .io_out_last_stage_ftb_entry_brSlots_0_tarStat + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_tarStat), + .io_out_last_stage_ftb_entry_brSlots_0_sharing + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_sharing), + .io_out_last_stage_ftb_entry_brSlots_0_valid + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_valid), + .io_out_last_stage_ftb_entry_tailSlot_offset + (_ftb_io_out_last_stage_ftb_entry_tailSlot_offset), + .io_out_last_stage_ftb_entry_tailSlot_lower + (_ftb_io_out_last_stage_ftb_entry_tailSlot_lower), + .io_out_last_stage_ftb_entry_tailSlot_tarStat + (_ftb_io_out_last_stage_ftb_entry_tailSlot_tarStat), + .io_out_last_stage_ftb_entry_tailSlot_sharing + (_ftb_io_out_last_stage_ftb_entry_tailSlot_sharing), + .io_out_last_stage_ftb_entry_tailSlot_valid + (_ftb_io_out_last_stage_ftb_entry_tailSlot_valid), + .io_out_last_stage_ftb_entry_pftAddr + (_ftb_io_out_last_stage_ftb_entry_pftAddr), + .io_out_last_stage_ftb_entry_carry + (_ftb_io_out_last_stage_ftb_entry_carry), + .io_out_last_stage_ftb_entry_isCall + (_ftb_io_out_last_stage_ftb_entry_isCall), + .io_out_last_stage_ftb_entry_isRet + (_ftb_io_out_last_stage_ftb_entry_isRet), + .io_out_last_stage_ftb_entry_isJalr + (_ftb_io_out_last_stage_ftb_entry_isJalr), + .io_out_last_stage_ftb_entry_last_may_be_rvi_call + (_ftb_io_out_last_stage_ftb_entry_last_may_be_rvi_call), + .io_out_last_stage_ftb_entry_always_taken_0 + (_ftb_io_out_last_stage_ftb_entry_always_taken_0), + .io_out_last_stage_ftb_entry_always_taken_1 + (_ftb_io_out_last_stage_ftb_entry_always_taken_1), + .io_ctrl_btb_enable + (_ftb_io_ctrl_delay_io_out_btb_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + .io_s0_fire_0 (io_s0_fire_0), + .io_s0_fire_1 (io_s0_fire_1), + .io_s0_fire_2 (io_s0_fire_2), + .io_s0_fire_3 (io_s0_fire_3), + .io_s1_fire_0 (io_s1_fire_0), + .io_s1_fire_1 (io_s1_fire_1), + .io_s1_fire_2 (io_s1_fire_2), + .io_s1_fire_3 (io_s1_fire_3), + .io_s2_fire_0 (io_s2_fire_0), + .io_s2_fire_1 (io_s2_fire_1), + .io_s2_fire_2 (io_s2_fire_2), + .io_s2_fire_3 (io_s2_fire_3), + .io_s1_ready (_ftb_io_s1_ready), + .io_update_valid (io_update_valid), + .io_update_bits_pc (io_update_bits_pc), + .io_update_bits_ftb_entry_valid (io_update_bits_ftb_entry_valid), + .io_update_bits_ftb_entry_brSlots_0_offset + (io_update_bits_ftb_entry_brSlots_0_offset), + .io_update_bits_ftb_entry_brSlots_0_lower + (io_update_bits_ftb_entry_brSlots_0_lower), + .io_update_bits_ftb_entry_brSlots_0_tarStat + (io_update_bits_ftb_entry_brSlots_0_tarStat), + .io_update_bits_ftb_entry_brSlots_0_sharing + (io_update_bits_ftb_entry_brSlots_0_sharing), + .io_update_bits_ftb_entry_brSlots_0_valid + (io_update_bits_ftb_entry_brSlots_0_valid), + .io_update_bits_ftb_entry_tailSlot_offset + (io_update_bits_ftb_entry_tailSlot_offset), + .io_update_bits_ftb_entry_tailSlot_lower + (io_update_bits_ftb_entry_tailSlot_lower), + .io_update_bits_ftb_entry_tailSlot_tarStat + (io_update_bits_ftb_entry_tailSlot_tarStat), + .io_update_bits_ftb_entry_tailSlot_sharing + (io_update_bits_ftb_entry_tailSlot_sharing), + .io_update_bits_ftb_entry_tailSlot_valid + (io_update_bits_ftb_entry_tailSlot_valid), + .io_update_bits_ftb_entry_pftAddr + (io_update_bits_ftb_entry_pftAddr), + .io_update_bits_ftb_entry_carry (io_update_bits_ftb_entry_carry), + .io_update_bits_ftb_entry_isCall + (io_update_bits_ftb_entry_isCall), + .io_update_bits_ftb_entry_isRet (io_update_bits_ftb_entry_isRet), + .io_update_bits_ftb_entry_isJalr + (io_update_bits_ftb_entry_isJalr), + .io_update_bits_ftb_entry_last_may_be_rvi_call + (io_update_bits_ftb_entry_last_may_be_rvi_call), + .io_update_bits_ftb_entry_always_taken_0 + (io_update_bits_ftb_entry_always_taken_0), + .io_update_bits_ftb_entry_always_taken_1 + (io_update_bits_ftb_entry_always_taken_1), + .io_update_bits_old_entry (io_update_bits_old_entry), + .io_update_bits_meta + ({122'h0, io_update_bits_meta[218:122]}) // src/main/scala/xiangshan/frontend/Composer.scala:77:27, :78:31 + ); + FauFTB ubtb ( // src/main/scala/xiangshan/Parameters.scala:109:23 + .clock (clock), + .reset (reset), + .io_reset_vector (io_reset_vector), + .io_in_bits_s0_pc_0 (io_in_bits_s0_pc_0), + .io_in_bits_s0_pc_1 (io_in_bits_s0_pc_1), + .io_in_bits_s0_pc_2 (io_in_bits_s0_pc_2), + .io_in_bits_s0_pc_3 (io_in_bits_s0_pc_3), + .io_out_s1_pc_0 (io_out_s1_pc_0), + .io_out_s1_pc_1 (io_out_s1_pc_1), + .io_out_s1_pc_2 (io_out_s1_pc_2), + .io_out_s1_pc_3 (io_out_s1_pc_3), + .io_out_s1_full_pred_0_br_taken_mask_0 (io_out_s1_full_pred_0_br_taken_mask_0), + .io_out_s1_full_pred_0_br_taken_mask_1 (io_out_s1_full_pred_0_br_taken_mask_1), + .io_out_s1_full_pred_0_slot_valids_0 (io_out_s1_full_pred_0_slot_valids_0), + .io_out_s1_full_pred_0_slot_valids_1 (io_out_s1_full_pred_0_slot_valids_1), + .io_out_s1_full_pred_0_targets_0 (io_out_s1_full_pred_0_targets_0), + .io_out_s1_full_pred_0_targets_1 (io_out_s1_full_pred_0_targets_1), + .io_out_s1_full_pred_0_offsets_0 (io_out_s1_full_pred_0_offsets_0), + .io_out_s1_full_pred_0_offsets_1 (io_out_s1_full_pred_0_offsets_1), + .io_out_s1_full_pred_0_fallThroughAddr (io_out_s1_full_pred_0_fallThroughAddr), + .io_out_s1_full_pred_0_is_br_sharing (io_out_s1_full_pred_0_is_br_sharing), + .io_out_s1_full_pred_0_hit (io_out_s1_full_pred_0_hit), + .io_out_s1_full_pred_1_br_taken_mask_0 (io_out_s1_full_pred_1_br_taken_mask_0), + .io_out_s1_full_pred_1_br_taken_mask_1 (io_out_s1_full_pred_1_br_taken_mask_1), + .io_out_s1_full_pred_1_slot_valids_0 (io_out_s1_full_pred_1_slot_valids_0), + .io_out_s1_full_pred_1_slot_valids_1 (io_out_s1_full_pred_1_slot_valids_1), + .io_out_s1_full_pred_1_targets_0 (io_out_s1_full_pred_1_targets_0), + .io_out_s1_full_pred_1_targets_1 (io_out_s1_full_pred_1_targets_1), + .io_out_s1_full_pred_1_offsets_0 (io_out_s1_full_pred_1_offsets_0), + .io_out_s1_full_pred_1_offsets_1 (io_out_s1_full_pred_1_offsets_1), + .io_out_s1_full_pred_1_fallThroughAddr (io_out_s1_full_pred_1_fallThroughAddr), + .io_out_s1_full_pred_1_is_br_sharing (io_out_s1_full_pred_1_is_br_sharing), + .io_out_s1_full_pred_1_hit (io_out_s1_full_pred_1_hit), + .io_out_s1_full_pred_2_br_taken_mask_0 (io_out_s1_full_pred_2_br_taken_mask_0), + .io_out_s1_full_pred_2_br_taken_mask_1 (io_out_s1_full_pred_2_br_taken_mask_1), + .io_out_s1_full_pred_2_slot_valids_0 (io_out_s1_full_pred_2_slot_valids_0), + .io_out_s1_full_pred_2_slot_valids_1 (io_out_s1_full_pred_2_slot_valids_1), + .io_out_s1_full_pred_2_targets_0 (io_out_s1_full_pred_2_targets_0), + .io_out_s1_full_pred_2_targets_1 (io_out_s1_full_pred_2_targets_1), + .io_out_s1_full_pred_2_offsets_0 (io_out_s1_full_pred_2_offsets_0), + .io_out_s1_full_pred_2_offsets_1 (io_out_s1_full_pred_2_offsets_1), + .io_out_s1_full_pred_2_fallThroughAddr (io_out_s1_full_pred_2_fallThroughAddr), + .io_out_s1_full_pred_2_is_br_sharing (io_out_s1_full_pred_2_is_br_sharing), + .io_out_s1_full_pred_2_hit (io_out_s1_full_pred_2_hit), + .io_out_s1_full_pred_3_br_taken_mask_0 (io_out_s1_full_pred_3_br_taken_mask_0), + .io_out_s1_full_pred_3_br_taken_mask_1 (io_out_s1_full_pred_3_br_taken_mask_1), + .io_out_s1_full_pred_3_slot_valids_0 (io_out_s1_full_pred_3_slot_valids_0), + .io_out_s1_full_pred_3_slot_valids_1 (io_out_s1_full_pred_3_slot_valids_1), + .io_out_s1_full_pred_3_targets_0 (io_out_s1_full_pred_3_targets_0), + .io_out_s1_full_pred_3_targets_1 (io_out_s1_full_pred_3_targets_1), + .io_out_s1_full_pred_3_offsets_0 (io_out_s1_full_pred_3_offsets_0), + .io_out_s1_full_pred_3_offsets_1 (io_out_s1_full_pred_3_offsets_1), + .io_out_s1_full_pred_3_fallThroughAddr (io_out_s1_full_pred_3_fallThroughAddr), + .io_out_s1_full_pred_3_fallThroughErr (io_out_s1_full_pred_3_fallThroughErr), + .io_out_s1_full_pred_3_is_br_sharing (io_out_s1_full_pred_3_is_br_sharing), + .io_out_s1_full_pred_3_hit (io_out_s1_full_pred_3_hit), + .io_out_last_stage_meta (_ubtb_io_out_last_stage_meta), + .io_ctrl_ubtb_enable (_ubtb_io_ctrl_delay_io_out_ubtb_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + .io_s0_fire_0 (io_s0_fire_0), + .io_s0_fire_1 (io_s0_fire_1), + .io_s0_fire_2 (io_s0_fire_2), + .io_s0_fire_3 (io_s0_fire_3), + .io_s1_fire_0 (io_s1_fire_0), + .io_s2_fire_0 (io_s2_fire_0), + .io_update_valid (io_update_valid), + .io_update_bits_pc (io_update_bits_pc), + .io_update_bits_ftb_entry_brSlots_0_offset + (io_update_bits_ftb_entry_brSlots_0_offset), + .io_update_bits_ftb_entry_brSlots_0_lower + (io_update_bits_ftb_entry_brSlots_0_lower), + .io_update_bits_ftb_entry_brSlots_0_tarStat + (io_update_bits_ftb_entry_brSlots_0_tarStat), + .io_update_bits_ftb_entry_brSlots_0_valid + (io_update_bits_ftb_entry_brSlots_0_valid), + .io_update_bits_ftb_entry_tailSlot_offset + (io_update_bits_ftb_entry_tailSlot_offset), + .io_update_bits_ftb_entry_tailSlot_lower (io_update_bits_ftb_entry_tailSlot_lower), + .io_update_bits_ftb_entry_tailSlot_tarStat + (io_update_bits_ftb_entry_tailSlot_tarStat), + .io_update_bits_ftb_entry_tailSlot_sharing + (io_update_bits_ftb_entry_tailSlot_sharing), + .io_update_bits_ftb_entry_tailSlot_valid (io_update_bits_ftb_entry_tailSlot_valid), + .io_update_bits_ftb_entry_pftAddr (io_update_bits_ftb_entry_pftAddr), + .io_update_bits_ftb_entry_carry (io_update_bits_ftb_entry_carry), + .io_update_bits_ftb_entry_always_taken_0 (io_update_bits_ftb_entry_always_taken_0), + .io_update_bits_ftb_entry_always_taken_1 (io_update_bits_ftb_entry_always_taken_1), + .io_update_bits_br_taken_mask_0 (io_update_bits_br_taken_mask_0), + .io_update_bits_br_taken_mask_1 (io_update_bits_br_taken_mask_1) + ); + Tage_SC tage ( // src/main/scala/xiangshan/Parameters.scala:111:24 + .clock (clock), + .reset (reset), + .io_reset_vector (io_reset_vector), + .io_in_bits_s0_pc_0 (io_in_bits_s0_pc_0), + .io_in_bits_s0_pc_1 (io_in_bits_s0_pc_1), + .io_in_bits_s0_pc_3 (io_in_bits_s0_pc_3), + .io_in_bits_folded_hist_1_hist_17_folded_hist + (io_in_bits_folded_hist_1_hist_17_folded_hist), + .io_in_bits_folded_hist_1_hist_16_folded_hist + (io_in_bits_folded_hist_1_hist_16_folded_hist), + .io_in_bits_folded_hist_1_hist_15_folded_hist + (io_in_bits_folded_hist_1_hist_15_folded_hist), + .io_in_bits_folded_hist_1_hist_14_folded_hist + (io_in_bits_folded_hist_1_hist_14_folded_hist), + .io_in_bits_folded_hist_1_hist_9_folded_hist + (io_in_bits_folded_hist_1_hist_9_folded_hist), + .io_in_bits_folded_hist_1_hist_8_folded_hist + (io_in_bits_folded_hist_1_hist_8_folded_hist), + .io_in_bits_folded_hist_1_hist_7_folded_hist + (io_in_bits_folded_hist_1_hist_7_folded_hist), + .io_in_bits_folded_hist_1_hist_5_folded_hist + (io_in_bits_folded_hist_1_hist_5_folded_hist), + .io_in_bits_folded_hist_1_hist_4_folded_hist + (io_in_bits_folded_hist_1_hist_4_folded_hist), + .io_in_bits_folded_hist_1_hist_3_folded_hist + (io_in_bits_folded_hist_1_hist_3_folded_hist), + .io_in_bits_folded_hist_1_hist_1_folded_hist + (io_in_bits_folded_hist_1_hist_1_folded_hist), + .io_in_bits_folded_hist_3_hist_12_folded_hist + (io_in_bits_folded_hist_3_hist_12_folded_hist), + .io_in_bits_folded_hist_3_hist_11_folded_hist + (io_in_bits_folded_hist_3_hist_11_folded_hist), + .io_in_bits_folded_hist_3_hist_2_folded_hist + (io_in_bits_folded_hist_3_hist_2_folded_hist), + .io_out_s2_full_pred_0_br_taken_mask_0 + (_tage_io_out_s2_full_pred_0_br_taken_mask_0), + .io_out_s2_full_pred_0_br_taken_mask_1 + (_tage_io_out_s2_full_pred_0_br_taken_mask_1), + .io_out_s2_full_pred_1_br_taken_mask_0 + (_tage_io_out_s2_full_pred_1_br_taken_mask_0), + .io_out_s2_full_pred_1_br_taken_mask_1 + (_tage_io_out_s2_full_pred_1_br_taken_mask_1), + .io_out_s2_full_pred_2_br_taken_mask_0 + (_tage_io_out_s2_full_pred_2_br_taken_mask_0), + .io_out_s2_full_pred_2_br_taken_mask_1 + (_tage_io_out_s2_full_pred_2_br_taken_mask_1), + .io_out_s2_full_pred_3_br_taken_mask_0 + (_tage_io_out_s2_full_pred_3_br_taken_mask_0), + .io_out_s2_full_pred_3_br_taken_mask_1 + (_tage_io_out_s2_full_pred_3_br_taken_mask_1), + .io_out_s3_full_pred_0_br_taken_mask_0 + (_tage_io_out_s3_full_pred_0_br_taken_mask_0), + .io_out_s3_full_pred_0_br_taken_mask_1 + (_tage_io_out_s3_full_pred_0_br_taken_mask_1), + .io_out_s3_full_pred_1_br_taken_mask_0 + (_tage_io_out_s3_full_pred_1_br_taken_mask_0), + .io_out_s3_full_pred_1_br_taken_mask_1 + (_tage_io_out_s3_full_pred_1_br_taken_mask_1), + .io_out_s3_full_pred_2_br_taken_mask_0 + (_tage_io_out_s3_full_pred_2_br_taken_mask_0), + .io_out_s3_full_pred_2_br_taken_mask_1 + (_tage_io_out_s3_full_pred_2_br_taken_mask_1), + .io_out_s3_full_pred_3_br_taken_mask_0 + (_tage_io_out_s3_full_pred_3_br_taken_mask_0), + .io_out_s3_full_pred_3_br_taken_mask_1 + (_tage_io_out_s3_full_pred_3_br_taken_mask_1), + .io_out_last_stage_meta + (_tage_io_out_last_stage_meta), + .io_ctrl_tage_enable + (_tage_io_ctrl_delay_io_out_tage_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + .io_ctrl_sc_enable + (_tage_io_ctrl_delay_io_out_sc_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + .io_s0_fire_0 (io_s0_fire_0), + .io_s0_fire_1 (io_s0_fire_1), + .io_s0_fire_3 (io_s0_fire_3), + .io_s1_fire_0 (io_s1_fire_0), + .io_s1_fire_1 (io_s1_fire_1), + .io_s1_fire_2 (io_s1_fire_2), + .io_s1_fire_3 (io_s1_fire_3), + .io_s2_fire_0 (io_s2_fire_0), + .io_s2_fire_1 (io_s2_fire_1), + .io_s2_fire_2 (io_s2_fire_2), + .io_s2_fire_3 (io_s2_fire_3), + .io_s1_ready (_tage_io_s1_ready), + .io_update_valid (io_update_valid), + .io_update_bits_pc (io_update_bits_pc), + .io_update_bits_spec_info_folded_hist_hist_17_folded_hist + (io_update_bits_spec_info_folded_hist_hist_17_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_16_folded_hist + (io_update_bits_spec_info_folded_hist_hist_16_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_15_folded_hist + (io_update_bits_spec_info_folded_hist_hist_15_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_14_folded_hist + (io_update_bits_spec_info_folded_hist_hist_14_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_12_folded_hist + (io_update_bits_spec_info_folded_hist_hist_12_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_11_folded_hist + (io_update_bits_spec_info_folded_hist_hist_11_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_9_folded_hist + (io_update_bits_spec_info_folded_hist_hist_9_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_8_folded_hist + (io_update_bits_spec_info_folded_hist_hist_8_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_7_folded_hist + (io_update_bits_spec_info_folded_hist_hist_7_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_5_folded_hist + (io_update_bits_spec_info_folded_hist_hist_5_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_4_folded_hist + (io_update_bits_spec_info_folded_hist_hist_4_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_3_folded_hist + (io_update_bits_spec_info_folded_hist_hist_3_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_2_folded_hist + (io_update_bits_spec_info_folded_hist_hist_2_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_1_folded_hist + (io_update_bits_spec_info_folded_hist_hist_1_folded_hist), + .io_update_bits_ftb_entry_brSlots_0_valid + (io_update_bits_ftb_entry_brSlots_0_valid), + .io_update_bits_ftb_entry_tailSlot_sharing + (io_update_bits_ftb_entry_tailSlot_sharing), + .io_update_bits_ftb_entry_tailSlot_valid + (io_update_bits_ftb_entry_tailSlot_valid), + .io_update_bits_ftb_entry_always_taken_0 + (io_update_bits_ftb_entry_always_taken_0), + .io_update_bits_ftb_entry_always_taken_1 + (io_update_bits_ftb_entry_always_taken_1), + .io_update_bits_br_taken_mask_0 + (io_update_bits_br_taken_mask_0), + .io_update_bits_br_taken_mask_1 + (io_update_bits_br_taken_mask_1), + .io_update_bits_mispred_mask_0 + (io_update_bits_mispred_mask_0), + .io_update_bits_mispred_mask_1 + (io_update_bits_mispred_mask_1), + .io_update_bits_meta + ({125'h0, io_update_bits_meta[218:125]}) // src/main/scala/xiangshan/frontend/Composer.scala:77:27, :78:31 + ); + RAS ras ( // src/main/scala/xiangshan/Parameters.scala:112:23 + .clock (clock), + .reset (reset), + .io_reset_vector (io_reset_vector), + .io_in_bits_s0_pc_0 (io_in_bits_s0_pc_0), + .io_in_bits_s0_pc_1 (io_in_bits_s0_pc_1), + .io_in_bits_s0_pc_2 (io_in_bits_s0_pc_2), + .io_in_bits_s0_pc_3 (io_in_bits_s0_pc_3), + .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_0_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_0_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0 + (_ittage_io_out_s2_full_pred_0_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1 + (_ittage_io_out_s2_full_pred_0_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_0_targets_0 + (_ittage_io_out_s2_full_pred_0_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_0_targets_1 + (_ittage_io_out_s2_full_pred_0_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_0_jalr_target + (_ittage_io_out_s2_full_pred_0_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_0_offsets_0 + (_ittage_io_out_s2_full_pred_0_offsets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_0_offsets_1 + (_ittage_io_out_s2_full_pred_0_offsets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr + (_ittage_io_out_s2_full_pred_0_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing + (_ittage_io_out_s2_full_pred_0_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_0_hit + (_ittage_io_out_s2_full_pred_0_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_1_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_1_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0 + (_ittage_io_out_s2_full_pred_1_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1 + (_ittage_io_out_s2_full_pred_1_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_1_targets_0 + (_ittage_io_out_s2_full_pred_1_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_1_targets_1 + (_ittage_io_out_s2_full_pred_1_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_1_jalr_target + (_ittage_io_out_s2_full_pred_1_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_1_offsets_0 + (_ittage_io_out_s2_full_pred_1_offsets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_1_offsets_1 + (_ittage_io_out_s2_full_pred_1_offsets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr + (_ittage_io_out_s2_full_pred_1_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing + (_ittage_io_out_s2_full_pred_1_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_1_hit + (_ittage_io_out_s2_full_pred_1_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_2_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_2_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0 + (_ittage_io_out_s2_full_pred_2_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1 + (_ittage_io_out_s2_full_pred_2_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_targets_0 + (_ittage_io_out_s2_full_pred_2_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_targets_1 + (_ittage_io_out_s2_full_pred_2_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_jalr_target + (_ittage_io_out_s2_full_pred_2_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_offsets_0 + (_ittage_io_out_s2_full_pred_2_offsets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_offsets_1 + (_ittage_io_out_s2_full_pred_2_offsets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr + (_ittage_io_out_s2_full_pred_2_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_is_jalr + (_ittage_io_out_s2_full_pred_2_is_jalr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_is_call + (_ittage_io_out_s2_full_pred_2_is_call), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_is_ret + (_ittage_io_out_s2_full_pred_2_is_ret), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call + (_ittage_io_out_s2_full_pred_2_last_may_be_rvi_call), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing + (_ittage_io_out_s2_full_pred_2_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_2_hit + (_ittage_io_out_s2_full_pred_2_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_3_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_3_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0 + (_ittage_io_out_s2_full_pred_3_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1 + (_ittage_io_out_s2_full_pred_3_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_3_targets_0 + (_ittage_io_out_s2_full_pred_3_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_3_targets_1 + (_ittage_io_out_s2_full_pred_3_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_3_jalr_target + (_ittage_io_out_s2_full_pred_3_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_3_offsets_0 + (_ittage_io_out_s2_full_pred_3_offsets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_3_offsets_1 + (_ittage_io_out_s2_full_pred_3_offsets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr + (_ittage_io_out_s2_full_pred_3_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr + (_ittage_io_out_s2_full_pred_3_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing + (_ittage_io_out_s2_full_pred_3_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s2_full_pred_3_hit + (_ittage_io_out_s2_full_pred_3_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_0_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_0_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0 + (_ittage_io_out_s3_full_pred_0_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1 + (_ittage_io_out_s3_full_pred_0_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_0_targets_0 + (_ittage_io_out_s3_full_pred_0_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_0_targets_1 + (_ittage_io_out_s3_full_pred_0_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_0_jalr_target + (_ittage_io_out_s3_full_pred_0_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr + (_ittage_io_out_s3_full_pred_0_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr + (_ittage_io_out_s3_full_pred_0_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing + (_ittage_io_out_s3_full_pred_0_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_0_hit + (_ittage_io_out_s3_full_pred_0_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_1_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_1_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0 + (_ittage_io_out_s3_full_pred_1_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1 + (_ittage_io_out_s3_full_pred_1_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_1_targets_0 + (_ittage_io_out_s3_full_pred_1_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_1_targets_1 + (_ittage_io_out_s3_full_pred_1_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_1_jalr_target + (_ittage_io_out_s3_full_pred_1_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr + (_ittage_io_out_s3_full_pred_1_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr + (_ittage_io_out_s3_full_pred_1_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing + (_ittage_io_out_s3_full_pred_1_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_1_hit + (_ittage_io_out_s3_full_pred_1_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_2_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_2_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0 + (_ittage_io_out_s3_full_pred_2_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1 + (_ittage_io_out_s3_full_pred_2_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_targets_0 + (_ittage_io_out_s3_full_pred_2_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_targets_1 + (_ittage_io_out_s3_full_pred_2_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_jalr_target + (_ittage_io_out_s3_full_pred_2_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr + (_ittage_io_out_s3_full_pred_2_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr + (_ittage_io_out_s3_full_pred_2_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_is_jalr + (_ittage_io_out_s3_full_pred_2_is_jalr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_is_call + (_ittage_io_out_s3_full_pred_2_is_call), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_is_ret + (_ittage_io_out_s3_full_pred_2_is_ret), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing + (_ittage_io_out_s3_full_pred_2_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_2_hit + (_ittage_io_out_s3_full_pred_2_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_3_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_3_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0 + (_ittage_io_out_s3_full_pred_3_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1 + (_ittage_io_out_s3_full_pred_3_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_3_targets_0 + (_ittage_io_out_s3_full_pred_3_targets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_3_targets_1 + (_ittage_io_out_s3_full_pred_3_targets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_3_jalr_target + (_ittage_io_out_s3_full_pred_3_jalr_target), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_3_offsets_0 + (_ittage_io_out_s3_full_pred_3_offsets_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_3_offsets_1 + (_ittage_io_out_s3_full_pred_3_offsets_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr + (_ittage_io_out_s3_full_pred_3_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr + (_ittage_io_out_s3_full_pred_3_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing + (_ittage_io_out_s3_full_pred_3_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_s3_full_pred_3_hit + (_ittage_io_out_s3_full_pred_3_hit), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_valid + (_ittage_io_out_last_stage_ftb_entry_valid), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset + (_ittage_io_out_last_stage_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower + (_ittage_io_out_last_stage_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat + (_ittage_io_out_last_stage_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing + (_ittage_io_out_last_stage_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid + (_ittage_io_out_last_stage_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr + (_ittage_io_out_last_stage_ftb_entry_pftAddr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_carry + (_ittage_io_out_last_stage_ftb_entry_carry), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_isCall + (_ittage_io_out_last_stage_ftb_entry_isCall), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_isRet + (_ittage_io_out_last_stage_ftb_entry_isRet), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr + (_ittage_io_out_last_stage_ftb_entry_isJalr), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call + (_ittage_io_out_last_stage_ftb_entry_last_may_be_rvi_call), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0 + (_ittage_io_out_last_stage_ftb_entry_always_taken_0), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1 + (_ittage_io_out_last_stage_ftb_entry_always_taken_1), // src/main/scala/xiangshan/Parameters.scala:113:26 + .io_out_s2_pc_0 (io_out_s2_pc_0), + .io_out_s2_pc_1 (io_out_s2_pc_1), + .io_out_s2_pc_2 (io_out_s2_pc_2), + .io_out_s2_pc_3 (io_out_s2_pc_3), + .io_out_s2_full_pred_0_br_taken_mask_0 + (io_out_s2_full_pred_0_br_taken_mask_0), + .io_out_s2_full_pred_0_br_taken_mask_1 + (io_out_s2_full_pred_0_br_taken_mask_1), + .io_out_s2_full_pred_0_slot_valids_0 + (io_out_s2_full_pred_0_slot_valids_0), + .io_out_s2_full_pred_0_slot_valids_1 + (io_out_s2_full_pred_0_slot_valids_1), + .io_out_s2_full_pred_0_targets_0 + (io_out_s2_full_pred_0_targets_0), + .io_out_s2_full_pred_0_targets_1 + (io_out_s2_full_pred_0_targets_1), + .io_out_s2_full_pred_0_offsets_0 + (io_out_s2_full_pred_0_offsets_0), + .io_out_s2_full_pred_0_offsets_1 + (io_out_s2_full_pred_0_offsets_1), + .io_out_s2_full_pred_0_fallThroughAddr + (io_out_s2_full_pred_0_fallThroughAddr), + .io_out_s2_full_pred_0_is_br_sharing + (io_out_s2_full_pred_0_is_br_sharing), + .io_out_s2_full_pred_0_hit + (io_out_s2_full_pred_0_hit), + .io_out_s2_full_pred_1_br_taken_mask_0 + (io_out_s2_full_pred_1_br_taken_mask_0), + .io_out_s2_full_pred_1_br_taken_mask_1 + (io_out_s2_full_pred_1_br_taken_mask_1), + .io_out_s2_full_pred_1_slot_valids_0 + (io_out_s2_full_pred_1_slot_valids_0), + .io_out_s2_full_pred_1_slot_valids_1 + (io_out_s2_full_pred_1_slot_valids_1), + .io_out_s2_full_pred_1_targets_0 + (io_out_s2_full_pred_1_targets_0), + .io_out_s2_full_pred_1_targets_1 + (io_out_s2_full_pred_1_targets_1), + .io_out_s2_full_pred_1_offsets_0 + (io_out_s2_full_pred_1_offsets_0), + .io_out_s2_full_pred_1_offsets_1 + (io_out_s2_full_pred_1_offsets_1), + .io_out_s2_full_pred_1_fallThroughAddr + (io_out_s2_full_pred_1_fallThroughAddr), + .io_out_s2_full_pred_1_is_br_sharing + (io_out_s2_full_pred_1_is_br_sharing), + .io_out_s2_full_pred_1_hit + (io_out_s2_full_pred_1_hit), + .io_out_s2_full_pred_2_br_taken_mask_0 + (io_out_s2_full_pred_2_br_taken_mask_0), + .io_out_s2_full_pred_2_br_taken_mask_1 + (io_out_s2_full_pred_2_br_taken_mask_1), + .io_out_s2_full_pred_2_slot_valids_0 + (io_out_s2_full_pred_2_slot_valids_0), + .io_out_s2_full_pred_2_slot_valids_1 + (io_out_s2_full_pred_2_slot_valids_1), + .io_out_s2_full_pred_2_targets_0 + (io_out_s2_full_pred_2_targets_0), + .io_out_s2_full_pred_2_targets_1 + (io_out_s2_full_pred_2_targets_1), + .io_out_s2_full_pred_2_offsets_0 + (io_out_s2_full_pred_2_offsets_0), + .io_out_s2_full_pred_2_offsets_1 + (io_out_s2_full_pred_2_offsets_1), + .io_out_s2_full_pred_2_fallThroughAddr + (io_out_s2_full_pred_2_fallThroughAddr), + .io_out_s2_full_pred_2_is_br_sharing + (io_out_s2_full_pred_2_is_br_sharing), + .io_out_s2_full_pred_2_hit + (io_out_s2_full_pred_2_hit), + .io_out_s2_full_pred_3_br_taken_mask_0 + (io_out_s2_full_pred_3_br_taken_mask_0), + .io_out_s2_full_pred_3_br_taken_mask_1 + (io_out_s2_full_pred_3_br_taken_mask_1), + .io_out_s2_full_pred_3_slot_valids_0 + (io_out_s2_full_pred_3_slot_valids_0), + .io_out_s2_full_pred_3_slot_valids_1 + (io_out_s2_full_pred_3_slot_valids_1), + .io_out_s2_full_pred_3_targets_0 + (io_out_s2_full_pred_3_targets_0), + .io_out_s2_full_pred_3_targets_1 + (io_out_s2_full_pred_3_targets_1), + .io_out_s2_full_pred_3_offsets_0 + (io_out_s2_full_pred_3_offsets_0), + .io_out_s2_full_pred_3_offsets_1 + (io_out_s2_full_pred_3_offsets_1), + .io_out_s2_full_pred_3_fallThroughAddr + (io_out_s2_full_pred_3_fallThroughAddr), + .io_out_s2_full_pred_3_fallThroughErr + (io_out_s2_full_pred_3_fallThroughErr), + .io_out_s2_full_pred_3_is_br_sharing + (io_out_s2_full_pred_3_is_br_sharing), + .io_out_s2_full_pred_3_hit + (io_out_s2_full_pred_3_hit), + .io_out_s3_pc_0 (io_out_s3_pc_0), + .io_out_s3_pc_1 (io_out_s3_pc_1), + .io_out_s3_pc_2 (io_out_s3_pc_2), + .io_out_s3_pc_3 (io_out_s3_pc_3), + .io_out_s3_full_pred_0_br_taken_mask_0 + (io_out_s3_full_pred_0_br_taken_mask_0), + .io_out_s3_full_pred_0_br_taken_mask_1 + (io_out_s3_full_pred_0_br_taken_mask_1), + .io_out_s3_full_pred_0_slot_valids_0 + (io_out_s3_full_pred_0_slot_valids_0), + .io_out_s3_full_pred_0_slot_valids_1 + (io_out_s3_full_pred_0_slot_valids_1), + .io_out_s3_full_pred_0_targets_0 + (io_out_s3_full_pred_0_targets_0), + .io_out_s3_full_pred_0_targets_1 + (io_out_s3_full_pred_0_targets_1), + .io_out_s3_full_pred_0_fallThroughAddr + (io_out_s3_full_pred_0_fallThroughAddr), + .io_out_s3_full_pred_0_fallThroughErr + (io_out_s3_full_pred_0_fallThroughErr), + .io_out_s3_full_pred_0_is_br_sharing + (io_out_s3_full_pred_0_is_br_sharing), + .io_out_s3_full_pred_0_hit + (io_out_s3_full_pred_0_hit), + .io_out_s3_full_pred_1_br_taken_mask_0 + (io_out_s3_full_pred_1_br_taken_mask_0), + .io_out_s3_full_pred_1_br_taken_mask_1 + (io_out_s3_full_pred_1_br_taken_mask_1), + .io_out_s3_full_pred_1_slot_valids_0 + (io_out_s3_full_pred_1_slot_valids_0), + .io_out_s3_full_pred_1_slot_valids_1 + (io_out_s3_full_pred_1_slot_valids_1), + .io_out_s3_full_pred_1_targets_0 + (io_out_s3_full_pred_1_targets_0), + .io_out_s3_full_pred_1_targets_1 + (io_out_s3_full_pred_1_targets_1), + .io_out_s3_full_pred_1_fallThroughAddr + (io_out_s3_full_pred_1_fallThroughAddr), + .io_out_s3_full_pred_1_fallThroughErr + (io_out_s3_full_pred_1_fallThroughErr), + .io_out_s3_full_pred_1_is_br_sharing + (io_out_s3_full_pred_1_is_br_sharing), + .io_out_s3_full_pred_1_hit + (io_out_s3_full_pred_1_hit), + .io_out_s3_full_pred_2_br_taken_mask_0 + (io_out_s3_full_pred_2_br_taken_mask_0), + .io_out_s3_full_pred_2_br_taken_mask_1 + (io_out_s3_full_pred_2_br_taken_mask_1), + .io_out_s3_full_pred_2_slot_valids_0 + (io_out_s3_full_pred_2_slot_valids_0), + .io_out_s3_full_pred_2_slot_valids_1 + (io_out_s3_full_pred_2_slot_valids_1), + .io_out_s3_full_pred_2_targets_0 + (io_out_s3_full_pred_2_targets_0), + .io_out_s3_full_pred_2_targets_1 + (io_out_s3_full_pred_2_targets_1), + .io_out_s3_full_pred_2_fallThroughAddr + (io_out_s3_full_pred_2_fallThroughAddr), + .io_out_s3_full_pred_2_fallThroughErr + (io_out_s3_full_pred_2_fallThroughErr), + .io_out_s3_full_pred_2_is_br_sharing + (io_out_s3_full_pred_2_is_br_sharing), + .io_out_s3_full_pred_2_hit + (io_out_s3_full_pred_2_hit), + .io_out_s3_full_pred_3_br_taken_mask_0 + (io_out_s3_full_pred_3_br_taken_mask_0), + .io_out_s3_full_pred_3_br_taken_mask_1 + (io_out_s3_full_pred_3_br_taken_mask_1), + .io_out_s3_full_pred_3_slot_valids_0 + (io_out_s3_full_pred_3_slot_valids_0), + .io_out_s3_full_pred_3_slot_valids_1 + (io_out_s3_full_pred_3_slot_valids_1), + .io_out_s3_full_pred_3_targets_0 + (io_out_s3_full_pred_3_targets_0), + .io_out_s3_full_pred_3_targets_1 + (io_out_s3_full_pred_3_targets_1), + .io_out_s3_full_pred_3_offsets_0 + (io_out_s3_full_pred_3_offsets_0), + .io_out_s3_full_pred_3_offsets_1 + (io_out_s3_full_pred_3_offsets_1), + .io_out_s3_full_pred_3_fallThroughAddr + (io_out_s3_full_pred_3_fallThroughAddr), + .io_out_s3_full_pred_3_fallThroughErr + (io_out_s3_full_pred_3_fallThroughErr), + .io_out_s3_full_pred_3_is_br_sharing + (io_out_s3_full_pred_3_is_br_sharing), + .io_out_s3_full_pred_3_hit + (io_out_s3_full_pred_3_hit), + .io_out_last_stage_meta + (_ras_io_out_last_stage_meta), + .io_out_last_stage_spec_info_ssp + (io_out_last_stage_spec_info_ssp), + .io_out_last_stage_spec_info_sctr + (io_out_last_stage_spec_info_sctr), + .io_out_last_stage_spec_info_TOSW_flag + (io_out_last_stage_spec_info_TOSW_flag), + .io_out_last_stage_spec_info_TOSW_value + (io_out_last_stage_spec_info_TOSW_value), + .io_out_last_stage_spec_info_TOSR_flag + (io_out_last_stage_spec_info_TOSR_flag), + .io_out_last_stage_spec_info_TOSR_value + (io_out_last_stage_spec_info_TOSR_value), + .io_out_last_stage_spec_info_NOS_flag + (io_out_last_stage_spec_info_NOS_flag), + .io_out_last_stage_spec_info_NOS_value + (io_out_last_stage_spec_info_NOS_value), + .io_out_last_stage_spec_info_topAddr + (io_out_last_stage_spec_info_topAddr), + .io_out_last_stage_ftb_entry_valid + (io_out_last_stage_ftb_entry_valid), + .io_out_last_stage_ftb_entry_brSlots_0_offset + (io_out_last_stage_ftb_entry_brSlots_0_offset), + .io_out_last_stage_ftb_entry_brSlots_0_lower + (io_out_last_stage_ftb_entry_brSlots_0_lower), + .io_out_last_stage_ftb_entry_brSlots_0_tarStat + (io_out_last_stage_ftb_entry_brSlots_0_tarStat), + .io_out_last_stage_ftb_entry_brSlots_0_sharing + (io_out_last_stage_ftb_entry_brSlots_0_sharing), + .io_out_last_stage_ftb_entry_brSlots_0_valid + (io_out_last_stage_ftb_entry_brSlots_0_valid), + .io_out_last_stage_ftb_entry_tailSlot_offset + (io_out_last_stage_ftb_entry_tailSlot_offset), + .io_out_last_stage_ftb_entry_tailSlot_lower + (io_out_last_stage_ftb_entry_tailSlot_lower), + .io_out_last_stage_ftb_entry_tailSlot_tarStat + (io_out_last_stage_ftb_entry_tailSlot_tarStat), + .io_out_last_stage_ftb_entry_tailSlot_sharing + (io_out_last_stage_ftb_entry_tailSlot_sharing), + .io_out_last_stage_ftb_entry_tailSlot_valid + (io_out_last_stage_ftb_entry_tailSlot_valid), + .io_out_last_stage_ftb_entry_pftAddr + (io_out_last_stage_ftb_entry_pftAddr), + .io_out_last_stage_ftb_entry_carry + (io_out_last_stage_ftb_entry_carry), + .io_out_last_stage_ftb_entry_isCall + (io_out_last_stage_ftb_entry_isCall), + .io_out_last_stage_ftb_entry_isRet + (io_out_last_stage_ftb_entry_isRet), + .io_out_last_stage_ftb_entry_isJalr + (io_out_last_stage_ftb_entry_isJalr), + .io_out_last_stage_ftb_entry_last_may_be_rvi_call + (io_out_last_stage_ftb_entry_last_may_be_rvi_call), + .io_out_last_stage_ftb_entry_always_taken_0 + (io_out_last_stage_ftb_entry_always_taken_0), + .io_out_last_stage_ftb_entry_always_taken_1 + (io_out_last_stage_ftb_entry_always_taken_1), + .io_ctrl_ras_enable + (_ras_io_ctrl_delay_io_out_ras_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + .io_s0_fire_0 (io_s0_fire_0), + .io_s0_fire_1 (io_s0_fire_1), + .io_s0_fire_2 (io_s0_fire_2), + .io_s0_fire_3 (io_s0_fire_3), + .io_s1_fire_0 (io_s1_fire_0), + .io_s1_fire_1 (io_s1_fire_1), + .io_s1_fire_2 (io_s1_fire_2), + .io_s1_fire_3 (io_s1_fire_3), + .io_s2_fire_0 (io_s2_fire_0), + .io_s2_fire_1 (io_s2_fire_1), + .io_s2_fire_2 (io_s2_fire_2), + .io_s2_fire_3 (io_s2_fire_3), + .io_s3_fire_2 (io_s3_fire_2), + .io_s3_redirect_2 (io_s3_redirect_2), + .io_update_valid (io_update_valid), + .io_update_bits_ftb_entry_tailSlot_offset + (io_update_bits_ftb_entry_tailSlot_offset), + .io_update_bits_ftb_entry_tailSlot_valid + (io_update_bits_ftb_entry_tailSlot_valid), + .io_update_bits_ftb_entry_isCall + (io_update_bits_ftb_entry_isCall), + .io_update_bits_ftb_entry_isRet + (io_update_bits_ftb_entry_isRet), + .io_update_bits_cfi_idx_valid + (io_update_bits_cfi_idx_valid), + .io_update_bits_cfi_idx_bits + (io_update_bits_cfi_idx_bits), + .io_update_bits_jmp_taken + (io_update_bits_jmp_taken), + .io_update_bits_meta (io_update_bits_meta), + .io_redirect_valid (io_redirect_valid), + .io_redirect_bits_level + (io_redirect_bits_level), + .io_redirect_bits_cfiUpdate_pc + (io_redirect_bits_cfiUpdate_pc), + .io_redirect_bits_cfiUpdate_pd_isRVC + (io_redirect_bits_cfiUpdate_pd_isRVC), + .io_redirect_bits_cfiUpdate_pd_isCall + (io_redirect_bits_cfiUpdate_pd_isCall), + .io_redirect_bits_cfiUpdate_pd_isRet + (io_redirect_bits_cfiUpdate_pd_isRet), + .io_redirect_bits_cfiUpdate_ssp + (io_redirect_bits_cfiUpdate_ssp), + .io_redirect_bits_cfiUpdate_sctr + (io_redirect_bits_cfiUpdate_sctr), + .io_redirect_bits_cfiUpdate_TOSW_flag + (io_redirect_bits_cfiUpdate_TOSW_flag), + .io_redirect_bits_cfiUpdate_TOSW_value + (io_redirect_bits_cfiUpdate_TOSW_value), + .io_redirect_bits_cfiUpdate_TOSR_flag + (io_redirect_bits_cfiUpdate_TOSR_flag), + .io_redirect_bits_cfiUpdate_TOSR_value + (io_redirect_bits_cfiUpdate_TOSR_value), + .io_redirect_bits_cfiUpdate_NOS_flag + (io_redirect_bits_cfiUpdate_NOS_flag), + .io_redirect_bits_cfiUpdate_NOS_value + (io_redirect_bits_cfiUpdate_NOS_value) + ); + ITTage ittage ( // src/main/scala/xiangshan/Parameters.scala:113:26 + .clock (clock), + .reset (reset), + .io_in_bits_s0_pc_3 (io_in_bits_s0_pc_3), + .io_in_bits_folded_hist_3_hist_14_folded_hist + (io_in_bits_folded_hist_3_hist_14_folded_hist), + .io_in_bits_folded_hist_3_hist_13_folded_hist + (io_in_bits_folded_hist_3_hist_13_folded_hist), + .io_in_bits_folded_hist_3_hist_12_folded_hist + (io_in_bits_folded_hist_3_hist_12_folded_hist), + .io_in_bits_folded_hist_3_hist_10_folded_hist + (io_in_bits_folded_hist_3_hist_10_folded_hist), + .io_in_bits_folded_hist_3_hist_6_folded_hist + (io_in_bits_folded_hist_3_hist_6_folded_hist), + .io_in_bits_folded_hist_3_hist_4_folded_hist + (io_in_bits_folded_hist_3_hist_4_folded_hist), + .io_in_bits_folded_hist_3_hist_3_folded_hist + (io_in_bits_folded_hist_3_hist_3_folded_hist), + .io_in_bits_folded_hist_3_hist_2_folded_hist + (io_in_bits_folded_hist_3_hist_2_folded_hist), + .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_0_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_0_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0 + (_ftb_io_out_s2_full_pred_0_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1 + (_ftb_io_out_s2_full_pred_0_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_0_targets_0 + (_ftb_io_out_s2_full_pred_0_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_0_targets_1 + (_ftb_io_out_s2_full_pred_0_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_0_jalr_target + (_ftb_io_out_s2_full_pred_0_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_0_offsets_0 + (_ftb_io_out_s2_full_pred_0_offsets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_0_offsets_1 + (_ftb_io_out_s2_full_pred_0_offsets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr + (_ftb_io_out_s2_full_pred_0_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing + (_ftb_io_out_s2_full_pred_0_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_0_hit + (_ftb_io_out_s2_full_pred_0_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_1_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_1_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0 + (_ftb_io_out_s2_full_pred_1_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1 + (_ftb_io_out_s2_full_pred_1_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_1_targets_0 + (_ftb_io_out_s2_full_pred_1_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_1_targets_1 + (_ftb_io_out_s2_full_pred_1_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_1_jalr_target + (_ftb_io_out_s2_full_pred_1_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_1_offsets_0 + (_ftb_io_out_s2_full_pred_1_offsets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_1_offsets_1 + (_ftb_io_out_s2_full_pred_1_offsets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr + (_ftb_io_out_s2_full_pred_1_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing + (_ftb_io_out_s2_full_pred_1_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_1_hit + (_ftb_io_out_s2_full_pred_1_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_2_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_2_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0 + (_ftb_io_out_s2_full_pred_2_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1 + (_ftb_io_out_s2_full_pred_2_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_targets_0 + (_ftb_io_out_s2_full_pred_2_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_targets_1 + (_ftb_io_out_s2_full_pred_2_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_jalr_target + (_ftb_io_out_s2_full_pred_2_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_offsets_0 + (_ftb_io_out_s2_full_pred_2_offsets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_offsets_1 + (_ftb_io_out_s2_full_pred_2_offsets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr + (_ftb_io_out_s2_full_pred_2_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_is_jalr + (_ftb_io_out_s2_full_pred_2_is_jalr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_is_call + (_ftb_io_out_s2_full_pred_2_is_call), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_is_ret + (_ftb_io_out_s2_full_pred_2_is_ret), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call + (_ftb_io_out_s2_full_pred_2_last_may_be_rvi_call), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing + (_ftb_io_out_s2_full_pred_2_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_2_hit + (_ftb_io_out_s2_full_pred_2_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_3_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_3_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0 + (_ftb_io_out_s2_full_pred_3_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1 + (_ftb_io_out_s2_full_pred_3_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_3_targets_0 + (_ftb_io_out_s2_full_pred_3_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_3_targets_1 + (_ftb_io_out_s2_full_pred_3_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_3_jalr_target + (_ftb_io_out_s2_full_pred_3_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_3_offsets_0 + (_ftb_io_out_s2_full_pred_3_offsets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_3_offsets_1 + (_ftb_io_out_s2_full_pred_3_offsets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr + (_ftb_io_out_s2_full_pred_3_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr + (_ftb_io_out_s2_full_pred_3_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing + (_ftb_io_out_s2_full_pred_3_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s2_full_pred_3_hit + (_ftb_io_out_s2_full_pred_3_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_0_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_0_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0 + (_ftb_io_out_s3_full_pred_0_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1 + (_ftb_io_out_s3_full_pred_0_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_0_targets_0 + (_ftb_io_out_s3_full_pred_0_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_0_targets_1 + (_ftb_io_out_s3_full_pred_0_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_0_jalr_target + (_ftb_io_out_s3_full_pred_0_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr + (_ftb_io_out_s3_full_pred_0_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr + (_ftb_io_out_s3_full_pred_0_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing + (_ftb_io_out_s3_full_pred_0_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_0_hit + (_ftb_io_out_s3_full_pred_0_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_1_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_1_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0 + (_ftb_io_out_s3_full_pred_1_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1 + (_ftb_io_out_s3_full_pred_1_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_1_targets_0 + (_ftb_io_out_s3_full_pred_1_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_1_targets_1 + (_ftb_io_out_s3_full_pred_1_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_1_jalr_target + (_ftb_io_out_s3_full_pred_1_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr + (_ftb_io_out_s3_full_pred_1_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr + (_ftb_io_out_s3_full_pred_1_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing + (_ftb_io_out_s3_full_pred_1_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_1_hit + (_ftb_io_out_s3_full_pred_1_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_2_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_2_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0 + (_ftb_io_out_s3_full_pred_2_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1 + (_ftb_io_out_s3_full_pred_2_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_targets_0 + (_ftb_io_out_s3_full_pred_2_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_targets_1 + (_ftb_io_out_s3_full_pred_2_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_jalr_target + (_ftb_io_out_s3_full_pred_2_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr + (_ftb_io_out_s3_full_pred_2_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr + (_ftb_io_out_s3_full_pred_2_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_is_jalr + (_ftb_io_out_s3_full_pred_2_is_jalr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_is_call + (_ftb_io_out_s3_full_pred_2_is_call), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_is_ret + (_ftb_io_out_s3_full_pred_2_is_ret), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing + (_ftb_io_out_s3_full_pred_2_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_2_hit + (_ftb_io_out_s3_full_pred_2_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_3_br_taken_mask_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_3_br_taken_mask_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0 + (_ftb_io_out_s3_full_pred_3_slot_valids_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1 + (_ftb_io_out_s3_full_pred_3_slot_valids_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_3_targets_0 + (_ftb_io_out_s3_full_pred_3_targets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_3_targets_1 + (_ftb_io_out_s3_full_pred_3_targets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_3_jalr_target + (_ftb_io_out_s3_full_pred_3_jalr_target), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_3_offsets_0 + (_ftb_io_out_s3_full_pred_3_offsets_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_3_offsets_1 + (_ftb_io_out_s3_full_pred_3_offsets_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr + (_ftb_io_out_s3_full_pred_3_fallThroughAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr + (_ftb_io_out_s3_full_pred_3_fallThroughErr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing + (_ftb_io_out_s3_full_pred_3_is_br_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_s3_full_pred_3_hit + (_ftb_io_out_s3_full_pred_3_hit), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_valid + (_ftb_io_out_last_stage_ftb_entry_valid), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset + (_ftb_io_out_last_stage_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower + (_ftb_io_out_last_stage_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat + (_ftb_io_out_last_stage_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing + (_ftb_io_out_last_stage_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid + (_ftb_io_out_last_stage_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr + (_ftb_io_out_last_stage_ftb_entry_pftAddr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_carry + (_ftb_io_out_last_stage_ftb_entry_carry), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_isCall + (_ftb_io_out_last_stage_ftb_entry_isCall), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_isRet + (_ftb_io_out_last_stage_ftb_entry_isRet), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr + (_ftb_io_out_last_stage_ftb_entry_isJalr), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call + (_ftb_io_out_last_stage_ftb_entry_last_may_be_rvi_call), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0 + (_ftb_io_out_last_stage_ftb_entry_always_taken_0), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1 + (_ftb_io_out_last_stage_ftb_entry_always_taken_1), // src/main/scala/xiangshan/Parameters.scala:108:23 + .io_out_s2_full_pred_0_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_0_br_taken_mask_0), + .io_out_s2_full_pred_0_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_0_br_taken_mask_1), + .io_out_s2_full_pred_0_slot_valids_0 + (_ittage_io_out_s2_full_pred_0_slot_valids_0), + .io_out_s2_full_pred_0_slot_valids_1 + (_ittage_io_out_s2_full_pred_0_slot_valids_1), + .io_out_s2_full_pred_0_targets_0 + (_ittage_io_out_s2_full_pred_0_targets_0), + .io_out_s2_full_pred_0_targets_1 + (_ittage_io_out_s2_full_pred_0_targets_1), + .io_out_s2_full_pred_0_jalr_target + (_ittage_io_out_s2_full_pred_0_jalr_target), + .io_out_s2_full_pred_0_offsets_0 + (_ittage_io_out_s2_full_pred_0_offsets_0), + .io_out_s2_full_pred_0_offsets_1 + (_ittage_io_out_s2_full_pred_0_offsets_1), + .io_out_s2_full_pred_0_fallThroughAddr + (_ittage_io_out_s2_full_pred_0_fallThroughAddr), + .io_out_s2_full_pred_0_is_br_sharing + (_ittage_io_out_s2_full_pred_0_is_br_sharing), + .io_out_s2_full_pred_0_hit + (_ittage_io_out_s2_full_pred_0_hit), + .io_out_s2_full_pred_1_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_1_br_taken_mask_0), + .io_out_s2_full_pred_1_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_1_br_taken_mask_1), + .io_out_s2_full_pred_1_slot_valids_0 + (_ittage_io_out_s2_full_pred_1_slot_valids_0), + .io_out_s2_full_pred_1_slot_valids_1 + (_ittage_io_out_s2_full_pred_1_slot_valids_1), + .io_out_s2_full_pred_1_targets_0 + (_ittage_io_out_s2_full_pred_1_targets_0), + .io_out_s2_full_pred_1_targets_1 + (_ittage_io_out_s2_full_pred_1_targets_1), + .io_out_s2_full_pred_1_jalr_target + (_ittage_io_out_s2_full_pred_1_jalr_target), + .io_out_s2_full_pred_1_offsets_0 + (_ittage_io_out_s2_full_pred_1_offsets_0), + .io_out_s2_full_pred_1_offsets_1 + (_ittage_io_out_s2_full_pred_1_offsets_1), + .io_out_s2_full_pred_1_fallThroughAddr + (_ittage_io_out_s2_full_pred_1_fallThroughAddr), + .io_out_s2_full_pred_1_is_br_sharing + (_ittage_io_out_s2_full_pred_1_is_br_sharing), + .io_out_s2_full_pred_1_hit + (_ittage_io_out_s2_full_pred_1_hit), + .io_out_s2_full_pred_2_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_2_br_taken_mask_0), + .io_out_s2_full_pred_2_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_2_br_taken_mask_1), + .io_out_s2_full_pred_2_slot_valids_0 + (_ittage_io_out_s2_full_pred_2_slot_valids_0), + .io_out_s2_full_pred_2_slot_valids_1 + (_ittage_io_out_s2_full_pred_2_slot_valids_1), + .io_out_s2_full_pred_2_targets_0 + (_ittage_io_out_s2_full_pred_2_targets_0), + .io_out_s2_full_pred_2_targets_1 + (_ittage_io_out_s2_full_pred_2_targets_1), + .io_out_s2_full_pred_2_jalr_target + (_ittage_io_out_s2_full_pred_2_jalr_target), + .io_out_s2_full_pred_2_offsets_0 + (_ittage_io_out_s2_full_pred_2_offsets_0), + .io_out_s2_full_pred_2_offsets_1 + (_ittage_io_out_s2_full_pred_2_offsets_1), + .io_out_s2_full_pred_2_fallThroughAddr + (_ittage_io_out_s2_full_pred_2_fallThroughAddr), + .io_out_s2_full_pred_2_is_jalr + (_ittage_io_out_s2_full_pred_2_is_jalr), + .io_out_s2_full_pred_2_is_call + (_ittage_io_out_s2_full_pred_2_is_call), + .io_out_s2_full_pred_2_is_ret + (_ittage_io_out_s2_full_pred_2_is_ret), + .io_out_s2_full_pred_2_last_may_be_rvi_call + (_ittage_io_out_s2_full_pred_2_last_may_be_rvi_call), + .io_out_s2_full_pred_2_is_br_sharing + (_ittage_io_out_s2_full_pred_2_is_br_sharing), + .io_out_s2_full_pred_2_hit + (_ittage_io_out_s2_full_pred_2_hit), + .io_out_s2_full_pred_3_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_3_br_taken_mask_0), + .io_out_s2_full_pred_3_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_3_br_taken_mask_1), + .io_out_s2_full_pred_3_slot_valids_0 + (_ittage_io_out_s2_full_pred_3_slot_valids_0), + .io_out_s2_full_pred_3_slot_valids_1 + (_ittage_io_out_s2_full_pred_3_slot_valids_1), + .io_out_s2_full_pred_3_targets_0 + (_ittage_io_out_s2_full_pred_3_targets_0), + .io_out_s2_full_pred_3_targets_1 + (_ittage_io_out_s2_full_pred_3_targets_1), + .io_out_s2_full_pred_3_jalr_target + (_ittage_io_out_s2_full_pred_3_jalr_target), + .io_out_s2_full_pred_3_offsets_0 + (_ittage_io_out_s2_full_pred_3_offsets_0), + .io_out_s2_full_pred_3_offsets_1 + (_ittage_io_out_s2_full_pred_3_offsets_1), + .io_out_s2_full_pred_3_fallThroughAddr + (_ittage_io_out_s2_full_pred_3_fallThroughAddr), + .io_out_s2_full_pred_3_fallThroughErr + (_ittage_io_out_s2_full_pred_3_fallThroughErr), + .io_out_s2_full_pred_3_is_br_sharing + (_ittage_io_out_s2_full_pred_3_is_br_sharing), + .io_out_s2_full_pred_3_hit + (_ittage_io_out_s2_full_pred_3_hit), + .io_out_s3_full_pred_0_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_0_br_taken_mask_0), + .io_out_s3_full_pred_0_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_0_br_taken_mask_1), + .io_out_s3_full_pred_0_slot_valids_0 + (_ittage_io_out_s3_full_pred_0_slot_valids_0), + .io_out_s3_full_pred_0_slot_valids_1 + (_ittage_io_out_s3_full_pred_0_slot_valids_1), + .io_out_s3_full_pred_0_targets_0 + (_ittage_io_out_s3_full_pred_0_targets_0), + .io_out_s3_full_pred_0_targets_1 + (_ittage_io_out_s3_full_pred_0_targets_1), + .io_out_s3_full_pred_0_jalr_target + (_ittage_io_out_s3_full_pred_0_jalr_target), + .io_out_s3_full_pred_0_fallThroughAddr + (_ittage_io_out_s3_full_pred_0_fallThroughAddr), + .io_out_s3_full_pred_0_fallThroughErr + (_ittage_io_out_s3_full_pred_0_fallThroughErr), + .io_out_s3_full_pred_0_is_br_sharing + (_ittage_io_out_s3_full_pred_0_is_br_sharing), + .io_out_s3_full_pred_0_hit + (_ittage_io_out_s3_full_pred_0_hit), + .io_out_s3_full_pred_1_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_1_br_taken_mask_0), + .io_out_s3_full_pred_1_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_1_br_taken_mask_1), + .io_out_s3_full_pred_1_slot_valids_0 + (_ittage_io_out_s3_full_pred_1_slot_valids_0), + .io_out_s3_full_pred_1_slot_valids_1 + (_ittage_io_out_s3_full_pred_1_slot_valids_1), + .io_out_s3_full_pred_1_targets_0 + (_ittage_io_out_s3_full_pred_1_targets_0), + .io_out_s3_full_pred_1_targets_1 + (_ittage_io_out_s3_full_pred_1_targets_1), + .io_out_s3_full_pred_1_jalr_target + (_ittage_io_out_s3_full_pred_1_jalr_target), + .io_out_s3_full_pred_1_fallThroughAddr + (_ittage_io_out_s3_full_pred_1_fallThroughAddr), + .io_out_s3_full_pred_1_fallThroughErr + (_ittage_io_out_s3_full_pred_1_fallThroughErr), + .io_out_s3_full_pred_1_is_br_sharing + (_ittage_io_out_s3_full_pred_1_is_br_sharing), + .io_out_s3_full_pred_1_hit + (_ittage_io_out_s3_full_pred_1_hit), + .io_out_s3_full_pred_2_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_2_br_taken_mask_0), + .io_out_s3_full_pred_2_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_2_br_taken_mask_1), + .io_out_s3_full_pred_2_slot_valids_0 + (_ittage_io_out_s3_full_pred_2_slot_valids_0), + .io_out_s3_full_pred_2_slot_valids_1 + (_ittage_io_out_s3_full_pred_2_slot_valids_1), + .io_out_s3_full_pred_2_targets_0 + (_ittage_io_out_s3_full_pred_2_targets_0), + .io_out_s3_full_pred_2_targets_1 + (_ittage_io_out_s3_full_pred_2_targets_1), + .io_out_s3_full_pred_2_jalr_target + (_ittage_io_out_s3_full_pred_2_jalr_target), + .io_out_s3_full_pred_2_fallThroughAddr + (_ittage_io_out_s3_full_pred_2_fallThroughAddr), + .io_out_s3_full_pred_2_fallThroughErr + (_ittage_io_out_s3_full_pred_2_fallThroughErr), + .io_out_s3_full_pred_2_is_jalr + (_ittage_io_out_s3_full_pred_2_is_jalr), + .io_out_s3_full_pred_2_is_call + (_ittage_io_out_s3_full_pred_2_is_call), + .io_out_s3_full_pred_2_is_ret + (_ittage_io_out_s3_full_pred_2_is_ret), + .io_out_s3_full_pred_2_is_br_sharing + (_ittage_io_out_s3_full_pred_2_is_br_sharing), + .io_out_s3_full_pred_2_hit + (_ittage_io_out_s3_full_pred_2_hit), + .io_out_s3_full_pred_3_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_3_br_taken_mask_0), + .io_out_s3_full_pred_3_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_3_br_taken_mask_1), + .io_out_s3_full_pred_3_slot_valids_0 + (_ittage_io_out_s3_full_pred_3_slot_valids_0), + .io_out_s3_full_pred_3_slot_valids_1 + (_ittage_io_out_s3_full_pred_3_slot_valids_1), + .io_out_s3_full_pred_3_targets_0 + (_ittage_io_out_s3_full_pred_3_targets_0), + .io_out_s3_full_pred_3_targets_1 + (_ittage_io_out_s3_full_pred_3_targets_1), + .io_out_s3_full_pred_3_jalr_target + (_ittage_io_out_s3_full_pred_3_jalr_target), + .io_out_s3_full_pred_3_offsets_0 + (_ittage_io_out_s3_full_pred_3_offsets_0), + .io_out_s3_full_pred_3_offsets_1 + (_ittage_io_out_s3_full_pred_3_offsets_1), + .io_out_s3_full_pred_3_fallThroughAddr + (_ittage_io_out_s3_full_pred_3_fallThroughAddr), + .io_out_s3_full_pred_3_fallThroughErr + (_ittage_io_out_s3_full_pred_3_fallThroughErr), + .io_out_s3_full_pred_3_is_br_sharing + (_ittage_io_out_s3_full_pred_3_is_br_sharing), + .io_out_s3_full_pred_3_hit + (_ittage_io_out_s3_full_pred_3_hit), + .io_out_last_stage_meta + (_ittage_io_out_last_stage_meta), + .io_out_last_stage_ftb_entry_valid + (_ittage_io_out_last_stage_ftb_entry_valid), + .io_out_last_stage_ftb_entry_brSlots_0_offset + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_offset), + .io_out_last_stage_ftb_entry_brSlots_0_lower + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_lower), + .io_out_last_stage_ftb_entry_brSlots_0_tarStat + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_tarStat), + .io_out_last_stage_ftb_entry_brSlots_0_sharing + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_sharing), + .io_out_last_stage_ftb_entry_brSlots_0_valid + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_valid), + .io_out_last_stage_ftb_entry_tailSlot_offset + (_ittage_io_out_last_stage_ftb_entry_tailSlot_offset), + .io_out_last_stage_ftb_entry_tailSlot_lower + (_ittage_io_out_last_stage_ftb_entry_tailSlot_lower), + .io_out_last_stage_ftb_entry_tailSlot_tarStat + (_ittage_io_out_last_stage_ftb_entry_tailSlot_tarStat), + .io_out_last_stage_ftb_entry_tailSlot_sharing + (_ittage_io_out_last_stage_ftb_entry_tailSlot_sharing), + .io_out_last_stage_ftb_entry_tailSlot_valid + (_ittage_io_out_last_stage_ftb_entry_tailSlot_valid), + .io_out_last_stage_ftb_entry_pftAddr + (_ittage_io_out_last_stage_ftb_entry_pftAddr), + .io_out_last_stage_ftb_entry_carry + (_ittage_io_out_last_stage_ftb_entry_carry), + .io_out_last_stage_ftb_entry_isCall + (_ittage_io_out_last_stage_ftb_entry_isCall), + .io_out_last_stage_ftb_entry_isRet + (_ittage_io_out_last_stage_ftb_entry_isRet), + .io_out_last_stage_ftb_entry_isJalr + (_ittage_io_out_last_stage_ftb_entry_isJalr), + .io_out_last_stage_ftb_entry_last_may_be_rvi_call + (_ittage_io_out_last_stage_ftb_entry_last_may_be_rvi_call), + .io_out_last_stage_ftb_entry_always_taken_0 + (_ittage_io_out_last_stage_ftb_entry_always_taken_0), + .io_out_last_stage_ftb_entry_always_taken_1 + (_ittage_io_out_last_stage_ftb_entry_always_taken_1), + .io_s0_fire_3 (io_s0_fire_3), + .io_s1_fire_3 (io_s1_fire_3), + .io_s2_fire_0 (io_s2_fire_0), + .io_s2_fire_1 (io_s2_fire_1), + .io_s2_fire_2 (io_s2_fire_2), + .io_s2_fire_3 (io_s2_fire_3), + .io_update_valid (io_update_valid), + .io_update_bits_pc (io_update_bits_pc), + .io_update_bits_spec_info_folded_hist_hist_14_folded_hist + (io_update_bits_spec_info_folded_hist_hist_14_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_13_folded_hist + (io_update_bits_spec_info_folded_hist_hist_13_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_12_folded_hist + (io_update_bits_spec_info_folded_hist_hist_12_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_10_folded_hist + (io_update_bits_spec_info_folded_hist_hist_10_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_6_folded_hist + (io_update_bits_spec_info_folded_hist_hist_6_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_4_folded_hist + (io_update_bits_spec_info_folded_hist_hist_4_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_3_folded_hist + (io_update_bits_spec_info_folded_hist_hist_3_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_2_folded_hist + (io_update_bits_spec_info_folded_hist_hist_2_folded_hist), + .io_update_bits_ftb_entry_tailSlot_offset + (io_update_bits_ftb_entry_tailSlot_offset), + .io_update_bits_ftb_entry_tailSlot_sharing + (io_update_bits_ftb_entry_tailSlot_sharing), + .io_update_bits_ftb_entry_tailSlot_valid + (io_update_bits_ftb_entry_tailSlot_valid), + .io_update_bits_ftb_entry_isRet + (io_update_bits_ftb_entry_isRet), + .io_update_bits_ftb_entry_isJalr + (io_update_bits_ftb_entry_isJalr), + .io_update_bits_cfi_idx_valid + (io_update_bits_cfi_idx_valid), + .io_update_bits_cfi_idx_bits + (io_update_bits_cfi_idx_bits), + .io_update_bits_jmp_taken + (io_update_bits_jmp_taken), + .io_update_bits_mispred_mask_2 + (io_update_bits_mispred_mask_2), + .io_update_bits_meta + ({25'h0, io_update_bits_meta[218:25]}), // src/main/scala/xiangshan/frontend/Composer.scala:59:22, :77:27, :78:31 + .io_update_bits_full_target + (io_update_bits_full_target) + ); + DelayN_1 ubtb_io_ctrl_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + .clock (clock), + .io_in_ubtb_enable (io_ctrl_ubtb_enable), + .io_in_btb_enable (io_ctrl_btb_enable), + .io_in_tage_enable (io_ctrl_tage_enable), + .io_in_sc_enable (io_ctrl_sc_enable), + .io_in_ras_enable (io_ctrl_ras_enable), + .io_out_ubtb_enable (_ubtb_io_ctrl_delay_io_out_ubtb_enable), + .io_out_btb_enable (/* unused */), + .io_out_tage_enable (/* unused */), + .io_out_sc_enable (/* unused */), + .io_out_ras_enable (/* unused */) + ); + DelayN_1 tage_io_ctrl_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + .clock (clock), + .io_in_ubtb_enable (io_ctrl_ubtb_enable), + .io_in_btb_enable (io_ctrl_btb_enable), + .io_in_tage_enable (io_ctrl_tage_enable), + .io_in_sc_enable (io_ctrl_sc_enable), + .io_in_ras_enable (io_ctrl_ras_enable), + .io_out_ubtb_enable (/* unused */), + .io_out_btb_enable (/* unused */), + .io_out_tage_enable (_tage_io_ctrl_delay_io_out_tage_enable), + .io_out_sc_enable (_tage_io_ctrl_delay_io_out_sc_enable), + .io_out_ras_enable (/* unused */) + ); + DelayN_1 ftb_io_ctrl_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + .clock (clock), + .io_in_ubtb_enable (io_ctrl_ubtb_enable), + .io_in_btb_enable (io_ctrl_btb_enable), + .io_in_tage_enable (io_ctrl_tage_enable), + .io_in_sc_enable (io_ctrl_sc_enable), + .io_in_ras_enable (io_ctrl_ras_enable), + .io_out_ubtb_enable (/* unused */), + .io_out_btb_enable (_ftb_io_ctrl_delay_io_out_btb_enable), + .io_out_tage_enable (/* unused */), + .io_out_sc_enable (/* unused */), + .io_out_ras_enable (/* unused */) + ); + DelayN_1 ras_io_ctrl_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + .clock (clock), + .io_in_ubtb_enable (io_ctrl_ubtb_enable), + .io_in_btb_enable (io_ctrl_btb_enable), + .io_in_tage_enable (io_ctrl_tage_enable), + .io_in_sc_enable (io_ctrl_sc_enable), + .io_in_ras_enable (io_ctrl_ras_enable), + .io_out_ubtb_enable (/* unused */), + .io_out_btb_enable (/* unused */), + .io_out_tage_enable (/* unused */), + .io_out_sc_enable (/* unused */), + .io_out_ras_enable (_ras_io_ctrl_delay_io_out_ras_enable) + ); + assign io_out_last_stage_meta = + {_ubtb_io_out_last_stage_meta[5:0], + _tage_io_out_last_stage_meta[87:0], + _ftb_io_out_last_stage_meta[2:0], + _ittage_io_out_last_stage_meta[96:0], + _ras_io_out_last_stage_meta[24:0]}; // src/main/scala/xiangshan/Parameters.scala:108:23, :109:23, :111:24, :112:23, :113:26, src/main/scala/xiangshan/frontend/Composer.scala:26:7, :59:64, :72:26 + assign io_s1_ready = _tage_io_s1_ready & _ftb_io_s1_ready; // src/main/scala/xiangshan/Parameters.scala:108:23, :111:24, src/main/scala/xiangshan/frontend/Composer.scala:26:7, :68:57 +endmodule + diff --git a/src/common/DelayN_2.sv b/src/common/DelayN_2.sv new file mode 100644 index 0000000..f5d4e31 --- /dev/null +++ b/src/common/DelayN_2.sv @@ -0,0 +1,102 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module DelayN_2( // utility/src/main/scala/utility/Hold.scala:83:7 + input clock, + input [35:0] io_in, // utility/src/main/scala/utility/Hold.scala:84:14 + output [35:0] io_out // utility/src/main/scala/utility/Hold.scala:84:14 +); + + reg [35:0] REG; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [35:0] REG_1; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [35:0] REG_2; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [35:0] REG_3; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [35:0] REG_4; // utility/src/main/scala/utility/Hold.scala:90:18 + always @(posedge clock) begin + REG <= io_in; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1 <= REG; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_2 <= REG_1; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_3 <= REG_2; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_4 <= REG_3; // utility/src/main/scala/utility/Hold.scala:90:18 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/Hold.scala:83:7 + `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:5]; // utility/src/main/scala/utility/Hold.scala:83:7 + initial begin // utility/src/main/scala/utility/Hold.scala:83:7 + `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7 + `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/Hold.scala:83:7 + for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin + _RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/Hold.scala:83:7 + end // utility/src/main/scala/utility/Hold.scala:83:7 + REG = {_RANDOM[3'h0], _RANDOM[3'h1][3:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1 = {_RANDOM[3'h1][31:4], _RANDOM[3'h2][7:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_2 = {_RANDOM[3'h2][31:8], _RANDOM[3'h3][11:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_3 = {_RANDOM[3'h3][31:12], _RANDOM[3'h4][15:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_4 = {_RANDOM[3'h4][31:16], _RANDOM[3'h5][19:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_out = REG_4; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 +endmodule + diff --git a/src/common/DelayN_4.sv b/src/common/DelayN_4.sv new file mode 100644 index 0000000..245ced5 --- /dev/null +++ b/src/common/DelayN_4.sv @@ -0,0 +1,93 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module DelayN_4( // utility/src/main/scala/utility/Hold.scala:83:7 + input clock, + input [38:0] io_in, // utility/src/main/scala/utility/Hold.scala:84:14 + output [38:0] io_out // utility/src/main/scala/utility/Hold.scala:84:14 +); + + reg [38:0] REG; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [38:0] REG_1; // utility/src/main/scala/utility/Hold.scala:90:18 + always @(posedge clock) begin + REG <= io_in; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1 <= REG; // utility/src/main/scala/utility/Hold.scala:90:18 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/Hold.scala:83:7 + `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; // utility/src/main/scala/utility/Hold.scala:83:7 + initial begin // utility/src/main/scala/utility/Hold.scala:83:7 + `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7 + `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/Hold.scala:83:7 + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/Hold.scala:83:7 + end // utility/src/main/scala/utility/Hold.scala:83:7 + REG = {_RANDOM[2'h0], _RANDOM[2'h1][6:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1 = {_RANDOM[2'h1][31:7], _RANDOM[2'h2][13:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_out = REG_1; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 +endmodule + diff --git a/src/common/DelayN_5.sv b/src/common/DelayN_5.sv new file mode 100644 index 0000000..c23389d --- /dev/null +++ b/src/common/DelayN_5.sv @@ -0,0 +1,255 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module DelayN_5( // utility/src/main/scala/utility/Hold.scala:83:7 + input clock, + input io_in_valid, // utility/src/main/scala/utility/Hold.scala:84:14 + input [3:0] io_in_brSlots_0_offset, // utility/src/main/scala/utility/Hold.scala:84:14 + input [11:0] io_in_brSlots_0_lower, // utility/src/main/scala/utility/Hold.scala:84:14 + input [1:0] io_in_brSlots_0_tarStat, // utility/src/main/scala/utility/Hold.scala:84:14 + input io_in_brSlots_0_sharing, // utility/src/main/scala/utility/Hold.scala:84:14 + input io_in_brSlots_0_valid, // utility/src/main/scala/utility/Hold.scala:84:14 + input [3:0] io_in_tailSlot_offset, // utility/src/main/scala/utility/Hold.scala:84:14 + input [19:0] io_in_tailSlot_lower, // utility/src/main/scala/utility/Hold.scala:84:14 + input [1:0] io_in_tailSlot_tarStat, // utility/src/main/scala/utility/Hold.scala:84:14 + input io_in_tailSlot_sharing, // utility/src/main/scala/utility/Hold.scala:84:14 + input io_in_tailSlot_valid, // utility/src/main/scala/utility/Hold.scala:84:14 + input [3:0] io_in_pftAddr, // utility/src/main/scala/utility/Hold.scala:84:14 + input io_in_carry, // utility/src/main/scala/utility/Hold.scala:84:14 + input io_in_isCall, // utility/src/main/scala/utility/Hold.scala:84:14 + input io_in_isRet, // utility/src/main/scala/utility/Hold.scala:84:14 + input io_in_isJalr, // utility/src/main/scala/utility/Hold.scala:84:14 + input io_in_last_may_be_rvi_call, // utility/src/main/scala/utility/Hold.scala:84:14 + input io_in_always_taken_0, // utility/src/main/scala/utility/Hold.scala:84:14 + input io_in_always_taken_1, // utility/src/main/scala/utility/Hold.scala:84:14 + output io_out_valid, // utility/src/main/scala/utility/Hold.scala:84:14 + output [3:0] io_out_brSlots_0_offset, // utility/src/main/scala/utility/Hold.scala:84:14 + output [11:0] io_out_brSlots_0_lower, // utility/src/main/scala/utility/Hold.scala:84:14 + output [1:0] io_out_brSlots_0_tarStat, // utility/src/main/scala/utility/Hold.scala:84:14 + output io_out_brSlots_0_sharing, // utility/src/main/scala/utility/Hold.scala:84:14 + output io_out_brSlots_0_valid, // utility/src/main/scala/utility/Hold.scala:84:14 + output [3:0] io_out_tailSlot_offset, // utility/src/main/scala/utility/Hold.scala:84:14 + output [19:0] io_out_tailSlot_lower, // utility/src/main/scala/utility/Hold.scala:84:14 + output [1:0] io_out_tailSlot_tarStat, // utility/src/main/scala/utility/Hold.scala:84:14 + output io_out_tailSlot_sharing, // utility/src/main/scala/utility/Hold.scala:84:14 + output io_out_tailSlot_valid, // utility/src/main/scala/utility/Hold.scala:84:14 + output [3:0] io_out_pftAddr, // utility/src/main/scala/utility/Hold.scala:84:14 + output io_out_carry, // utility/src/main/scala/utility/Hold.scala:84:14 + output io_out_isCall, // utility/src/main/scala/utility/Hold.scala:84:14 + output io_out_isRet, // utility/src/main/scala/utility/Hold.scala:84:14 + output io_out_isJalr, // utility/src/main/scala/utility/Hold.scala:84:14 + output io_out_last_may_be_rvi_call, // utility/src/main/scala/utility/Hold.scala:84:14 + output io_out_always_taken_0, // utility/src/main/scala/utility/Hold.scala:84:14 + output io_out_always_taken_1 // utility/src/main/scala/utility/Hold.scala:84:14 +); + + reg REG_valid; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [3:0] REG_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [11:0] REG_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [1:0] REG_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [3:0] REG_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [19:0] REG_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [1:0] REG_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [3:0] REG_pftAddr; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_carry; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_isCall; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_isRet; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_isJalr; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_always_taken_0; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_always_taken_1; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_1_valid; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [3:0] REG_1_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [11:0] REG_1_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [1:0] REG_1_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_1_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_1_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [3:0] REG_1_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [19:0] REG_1_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [1:0] REG_1_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_1_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_1_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:90:18 + reg [3:0] REG_1_pftAddr; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_1_carry; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_1_isCall; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_1_isRet; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_1_isJalr; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_1_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_1_always_taken_0; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_1_always_taken_1; // utility/src/main/scala/utility/Hold.scala:90:18 + always @(posedge clock) begin + REG_valid <= io_in_valid; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_brSlots_0_offset <= io_in_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_brSlots_0_lower <= io_in_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_brSlots_0_tarStat <= io_in_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_brSlots_0_sharing <= io_in_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_brSlots_0_valid <= io_in_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_tailSlot_offset <= io_in_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_tailSlot_lower <= io_in_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_tailSlot_tarStat <= io_in_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_tailSlot_sharing <= io_in_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_tailSlot_valid <= io_in_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_pftAddr <= io_in_pftAddr; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_carry <= io_in_carry; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_isCall <= io_in_isCall; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_isRet <= io_in_isRet; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_isJalr <= io_in_isJalr; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_last_may_be_rvi_call <= io_in_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_always_taken_0 <= io_in_always_taken_0; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_always_taken_1 <= io_in_always_taken_1; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_valid <= REG_valid; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_brSlots_0_offset <= REG_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_brSlots_0_lower <= REG_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_brSlots_0_tarStat <= REG_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_brSlots_0_sharing <= REG_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_brSlots_0_valid <= REG_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_tailSlot_offset <= REG_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_tailSlot_lower <= REG_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_tailSlot_tarStat <= REG_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_tailSlot_sharing <= REG_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_tailSlot_valid <= REG_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_pftAddr <= REG_pftAddr; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_carry <= REG_carry; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_isCall <= REG_isCall; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_isRet <= REG_isRet; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_isJalr <= REG_isJalr; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_last_may_be_rvi_call <= REG_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_always_taken_0 <= REG_always_taken_0; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1_always_taken_1 <= REG_always_taken_1; // utility/src/main/scala/utility/Hold.scala:90:18 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/Hold.scala:83:7 + `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; // utility/src/main/scala/utility/Hold.scala:83:7 + initial begin // utility/src/main/scala/utility/Hold.scala:83:7 + `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7 + `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/Hold.scala:83:7 + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; // utility/src/main/scala/utility/Hold.scala:83:7 + end // utility/src/main/scala/utility/Hold.scala:83:7 + REG_valid = _RANDOM[2'h0][0]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_brSlots_0_offset = _RANDOM[2'h0][4:1]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_brSlots_0_lower = _RANDOM[2'h0][16:5]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_brSlots_0_tarStat = _RANDOM[2'h0][18:17]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_brSlots_0_sharing = _RANDOM[2'h0][19]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_brSlots_0_valid = _RANDOM[2'h0][20]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_tailSlot_offset = _RANDOM[2'h0][24:21]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_tailSlot_lower = {_RANDOM[2'h0][31:25], _RANDOM[2'h1][12:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_tailSlot_tarStat = _RANDOM[2'h1][14:13]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_tailSlot_sharing = _RANDOM[2'h1][15]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_tailSlot_valid = _RANDOM[2'h1][16]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_pftAddr = _RANDOM[2'h1][20:17]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_carry = _RANDOM[2'h1][21]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_isCall = _RANDOM[2'h1][22]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_isRet = _RANDOM[2'h1][23]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_isJalr = _RANDOM[2'h1][24]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_last_may_be_rvi_call = _RANDOM[2'h1][25]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_always_taken_0 = _RANDOM[2'h1][26]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_always_taken_1 = _RANDOM[2'h1][27]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_valid = _RANDOM[2'h1][28]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_brSlots_0_offset = {_RANDOM[2'h1][31:29], _RANDOM[2'h2][0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_brSlots_0_lower = _RANDOM[2'h2][12:1]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_brSlots_0_tarStat = _RANDOM[2'h2][14:13]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_brSlots_0_sharing = _RANDOM[2'h2][15]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_brSlots_0_valid = _RANDOM[2'h2][16]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_tailSlot_offset = _RANDOM[2'h2][20:17]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_tailSlot_lower = {_RANDOM[2'h2][31:21], _RANDOM[2'h3][8:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_tailSlot_tarStat = _RANDOM[2'h3][10:9]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_tailSlot_sharing = _RANDOM[2'h3][11]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_tailSlot_valid = _RANDOM[2'h3][12]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_pftAddr = _RANDOM[2'h3][16:13]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_carry = _RANDOM[2'h3][17]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_isCall = _RANDOM[2'h3][18]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_isRet = _RANDOM[2'h3][19]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_isJalr = _RANDOM[2'h3][20]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_last_may_be_rvi_call = _RANDOM[2'h3][21]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_always_taken_0 = _RANDOM[2'h3][22]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1_always_taken_1 = _RANDOM[2'h3][23]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_out_valid = REG_1_valid; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_brSlots_0_offset = REG_1_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_brSlots_0_lower = REG_1_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_brSlots_0_tarStat = REG_1_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_brSlots_0_sharing = REG_1_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_brSlots_0_valid = REG_1_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_tailSlot_offset = REG_1_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_tailSlot_lower = REG_1_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_tailSlot_tarStat = REG_1_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_tailSlot_sharing = REG_1_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_tailSlot_valid = REG_1_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_pftAddr = REG_1_pftAddr; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_carry = REG_1_carry; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_isCall = REG_1_isCall; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_isRet = REG_1_isRet; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_isJalr = REG_1_isJalr; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_last_may_be_rvi_call = REG_1_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_always_taken_0 = REG_1_always_taken_0; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + assign io_out_always_taken_1 = REG_1_always_taken_1; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 +endmodule + diff --git a/src/common/DelayN_6.sv b/src/common/DelayN_6.sv new file mode 100644 index 0000000..71c228d --- /dev/null +++ b/src/common/DelayN_6.sv @@ -0,0 +1,91 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module DelayN_6( // utility/src/main/scala/utility/Hold.scala:83:7 + input clock, + input io_in, // utility/src/main/scala/utility/Hold.scala:84:14 + output io_out // utility/src/main/scala/utility/Hold.scala:84:14 +); + + reg REG; // utility/src/main/scala/utility/Hold.scala:90:18 + reg REG_1; // utility/src/main/scala/utility/Hold.scala:90:18 + always @(posedge clock) begin + REG <= io_in; // utility/src/main/scala/utility/Hold.scala:90:18 + REG_1 <= REG; // utility/src/main/scala/utility/Hold.scala:90:18 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/Hold.scala:83:7 + `ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/Hold.scala:83:7 + initial begin // utility/src/main/scala/utility/Hold.scala:83:7 + `ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7 + `INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/Hold.scala:83:7 + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/Hold.scala:83:7 + REG = _RANDOM[/*Zero width*/ 1'b0][0]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + REG_1 = _RANDOM[/*Zero width*/ 1'b0][1]; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_out = REG_1; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18 +endmodule + diff --git a/src/common/Predictor.sv b/src/common/Predictor.sv new file mode 100644 index 0000000..429e379 --- /dev/null +++ b/src/common/Predictor.sv @@ -0,0 +1,32777 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + input clock, + input reset, + input io_bpu_to_ftq_resp_ready, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [38:0] io_bpu_to_ftq_resp_bits_s1_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [38:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [38:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [3:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [3:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [38:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [38:0] io_bpu_to_ftq_resp_bits_s2_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s2_valid_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s2_hasRedirect_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s2_ftq_idx_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [5:0] io_bpu_to_ftq_resp_bits_s2_ftq_idx_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [38:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [38:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [3:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [3:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [38:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [38:0] io_bpu_to_ftq_resp_bits_s3_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s3_valid_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s3_hasRedirect_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s3_ftq_idx_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [5:0] io_bpu_to_ftq_resp_bits_s3_ftq_idx_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [38:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [38:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [3:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [3:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [38:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [218:0] io_bpu_to_ftq_resp_bits_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_0_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [2:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_lastBrNumOH, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [1:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [38:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_topAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [11:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [1:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [19:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [1:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_level, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [38:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_pc, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [3:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [1:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [3:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [2:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [38:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_target, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_taken, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [1:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_shift, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [38:0] io_ftq_to_bpu_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [3:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [11:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [1:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [19:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [1:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_cfi_idx_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [3:0] io_ftq_to_bpu_update_bits_cfi_idx_bits, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_jmp_taken, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_mispred_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_mispred_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_mispred_mask_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_update_bits_old_entry, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [218:0] io_ftq_to_bpu_update_bits_meta, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [38:0] io_ftq_to_bpu_update_bits_full_target, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ftq_to_bpu_enq_ptr_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [5:0] io_ftq_to_bpu_enq_ptr_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ctrl_ubtb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ctrl_btb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ctrl_tage_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ctrl_sc_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input io_ctrl_ras_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14 + input [35:0] io_reset_vector // src/main/scala/xiangshan/frontend/BPU.scala:222:14 +); + + wire s3_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:684:28 + wire s3_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:684:28 + wire s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:684:28 + wire s2_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:605:28 + wire s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:605:28 + wire s1_fire_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:374:60 + wire s1_fire_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:374:60 + wire s1_fire_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:374:60 + wire s1_fire_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:374:60 + wire _ghv_write_datas_255_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_254_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_253_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_252_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_251_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_250_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_249_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_248_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_247_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_246_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_245_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_244_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_243_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_242_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_241_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_240_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_239_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_238_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_237_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_236_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_235_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_234_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_233_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_232_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_231_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_230_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_229_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_228_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_227_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_226_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_225_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_224_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_223_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_222_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_221_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_220_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_219_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_218_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_217_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_216_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_215_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_214_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_213_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_212_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_211_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_210_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_209_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_208_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_207_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_206_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_205_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_204_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_203_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_202_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_201_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_200_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_199_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_198_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_197_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_196_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_195_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_194_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_193_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_192_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_191_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_190_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_189_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_188_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_187_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_186_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_185_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_184_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_183_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_182_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_181_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_180_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_179_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_178_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_177_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_176_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_175_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_174_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_173_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_172_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_171_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_170_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_169_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_168_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_167_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_166_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_165_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_164_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_163_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_162_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_161_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_160_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_159_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_158_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_157_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_156_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_155_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_154_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_153_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_152_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_151_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_150_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_149_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_148_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_147_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_146_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_145_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_144_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_143_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_142_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_141_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_140_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_139_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_138_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_137_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_136_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_135_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_134_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_133_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_132_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_131_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_130_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_129_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_128_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_127_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_126_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_125_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_124_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_123_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_122_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_121_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_120_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_119_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_118_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_117_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_116_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_115_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_114_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_113_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_112_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_111_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_110_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_109_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_108_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_107_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_106_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_105_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_104_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_103_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_102_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_101_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_100_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_99_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_98_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_97_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_96_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_95_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_94_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_93_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_92_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_91_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_90_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_89_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_88_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_87_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_86_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_85_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_84_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_83_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_82_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_81_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_80_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_79_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_78_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_77_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_76_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_75_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_74_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_73_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_72_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_71_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_70_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_69_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_68_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_67_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_66_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_65_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_64_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_63_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_62_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_61_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_60_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_59_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_58_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_57_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_56_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_55_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_54_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_53_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_52_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_51_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_50_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_49_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_48_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_47_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_46_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_45_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_44_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_43_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_42_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_41_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_40_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_39_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_38_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_37_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_36_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_35_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_34_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_33_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_32_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_31_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_30_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_29_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_28_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_27_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_26_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_25_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_24_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_23_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_22_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_21_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_20_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_19_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_18_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_17_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_16_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_15_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_14_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_13_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_12_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_11_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_10_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_9_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_8_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_7_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_6_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_5_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_4_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_3_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_2_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_1_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _ghv_write_datas_0_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [2:0] _s0_last_br_num_oh_dup_3_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [2:0] _s0_last_br_num_oh_dup_2_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [2:0] _s0_last_br_num_oh_dup_1_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ghist_ptr_dup_3_ppm_out_res_flag; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_ghist_ptr_dup_3_ppm_out_res_value; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ghist_ptr_dup_2_ppm_out_res_flag; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_ghist_ptr_dup_2_ppm_out_res_value; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ghist_ptr_dup_1_ppm_out_res_flag; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_ghist_ptr_dup_1_ppm_out_res_value; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire _s0_ghist_ptr_dup_0_ppm_out_res_flag; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_ghist_ptr_dup_0_ppm_out_res_value; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [3:0] _s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [3:0] _s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [3:0] _s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [38:0] _s0_pc_dup_3_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [38:0] _s0_pc_dup_2_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [38:0] _s0_pc_dup_1_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [38:0] _s0_pc_dup_0_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + wire [35:0] _reset_vector_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 + wire [38:0] _predictors_io_out_s1_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s1_full_pred_0_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s1_full_pred_0_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s1_full_pred_1_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s1_full_pred_1_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s1_full_pred_2_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s1_full_pred_2_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s1_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s1_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s1_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s2_full_pred_0_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s2_full_pred_0_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s2_full_pred_1_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s2_full_pred_1_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s2_full_pred_2_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s2_full_pred_2_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [3:0] _predictors_io_out_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_0_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_1_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_2_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire [38:0] _predictors_io_out_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _predictors_io_s1_ready; // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + wire _ctrl_delay_io_out_ubtb_enable; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _ctrl_delay_io_out_btb_enable; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _ctrl_delay_io_out_tage_enable; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _ctrl_delay_io_out_sc_enable; // utility/src/main/scala/utility/Hold.scala:97:23 + wire _ctrl_delay_io_out_ras_enable; // utility/src/main/scala/utility/Hold.scala:97:23 + reg s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:271:65 + reg s2_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:271:65 + reg s3_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:271:65 + reg [38:0] s0_pc_reg_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:276:49 + reg [38:0] s0_pc_reg_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:276:49 + reg [38:0] s0_pc_reg_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:276:49 + reg [38:0] s0_pc_reg_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:276:49 + reg REG; // src/main/scala/xiangshan/frontend/BPU.scala:277:24 + reg REG_1; // src/main/scala/xiangshan/frontend/BPU.scala:277:16 + reg [10:0] s0_folded_gh_reg_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [10:0] s0_folded_gh_reg_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [6:0] s0_folded_gh_reg_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [8:0] s0_folded_gh_reg_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [3:0] s0_folded_gh_reg_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [8:0] s0_folded_gh_reg_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [6:0] s0_folded_gh_reg_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [6:0] s0_folded_gh_reg_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [8:0] s0_folded_gh_reg_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [6:0] s0_folded_gh_reg_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [10:0] s0_folded_gh_reg_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [10:0] s0_folded_gh_reg_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [10:0] s0_folded_gh_reg_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [6:0] s0_folded_gh_reg_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [8:0] s0_folded_gh_reg_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [3:0] s0_folded_gh_reg_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [8:0] s0_folded_gh_reg_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [6:0] s0_folded_gh_reg_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [6:0] s0_folded_gh_reg_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [8:0] s0_folded_gh_reg_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [6:0] s0_folded_gh_reg_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [10:0] s0_folded_gh_reg_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [10:0] s0_folded_gh_reg_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [10:0] s0_folded_gh_reg_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [6:0] s0_folded_gh_reg_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [8:0] s0_folded_gh_reg_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [3:0] s0_folded_gh_reg_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [8:0] s0_folded_gh_reg_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [6:0] s0_folded_gh_reg_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [6:0] s0_folded_gh_reg_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [8:0] s0_folded_gh_reg_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [6:0] s0_folded_gh_reg_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [10:0] s0_folded_gh_reg_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [7:0] s0_folded_gh_reg_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + reg [10:0] s1_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [10:0] s1_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [6:0] s1_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [8:0] s1_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [3:0] s1_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [8:0] s1_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [6:0] s1_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [6:0] s1_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [8:0] s1_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [6:0] s1_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [10:0] s1_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [10:0] s1_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [10:0] s1_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [6:0] s1_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [8:0] s1_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [3:0] s1_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [8:0] s1_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [6:0] s1_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [6:0] s1_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [8:0] s1_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [6:0] s1_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [10:0] s1_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [10:0] s1_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [10:0] s1_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [6:0] s1_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [8:0] s1_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [3:0] s1_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [8:0] s1_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [6:0] s1_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [6:0] s1_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [8:0] s1_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [6:0] s1_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [10:0] s1_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [7:0] s1_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35 + reg [10:0] s2_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [10:0] s2_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [6:0] s2_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [8:0] s2_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [3:0] s2_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [8:0] s2_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [6:0] s2_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [6:0] s2_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [8:0] s2_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [6:0] s2_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [10:0] s2_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [10:0] s2_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [10:0] s2_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [6:0] s2_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [8:0] s2_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [3:0] s2_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [8:0] s2_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [6:0] s2_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [6:0] s2_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [8:0] s2_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [6:0] s2_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [10:0] s2_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [10:0] s2_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [10:0] s2_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [6:0] s2_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [8:0] s2_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [3:0] s2_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [8:0] s2_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [6:0] s2_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [6:0] s2_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [8:0] s2_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [6:0] s2_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [10:0] s2_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [7:0] s2_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35 + reg [10:0] s3_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [10:0] s3_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [6:0] s3_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [8:0] s3_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [3:0] s3_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [8:0] s3_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [6:0] s3_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [6:0] s3_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [8:0] s3_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [6:0] s3_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [10:0] s3_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [10:0] s3_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [10:0] s3_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [6:0] s3_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [8:0] s3_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [3:0] s3_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [8:0] s3_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [6:0] s3_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [6:0] s3_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [8:0] s3_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [6:0] s3_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [10:0] s3_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [10:0] s3_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [10:0] s3_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [6:0] s3_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [8:0] s3_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [3:0] s3_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [8:0] s3_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [6:0] s3_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [6:0] s3_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [8:0] s3_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [6:0] s3_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [10:0] s3_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [7:0] s3_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35 + reg [2:0] s0_last_br_num_oh_reg_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:291:73 + reg [2:0] s0_last_br_num_oh_reg_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:291:73 + reg [2:0] s0_last_br_num_oh_reg_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:291:73 + reg [2:0] s1_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:292:40 + reg [2:0] s1_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:292:40 + reg [2:0] s1_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:292:40 + reg [2:0] s2_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:293:40 + reg [2:0] s2_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:293:40 + reg [2:0] s2_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:293:40 + reg [2:0] s3_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:294:40 + reg [2:0] s3_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:294:40 + reg [2:0] s3_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:294:40 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46 + reg ghv_0; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_1; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_2; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_3; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_4; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_5; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_6; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_7; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_8; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_9; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_10; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_11; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_12; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_13; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_14; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_15; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_16; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_17; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_18; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_19; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_20; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_21; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_22; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_23; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_24; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_25; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_26; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_27; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_28; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_29; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_30; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_31; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_32; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_33; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_34; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_35; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_36; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_37; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_38; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_39; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_40; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_41; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_42; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_43; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_44; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_45; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_46; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_47; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_48; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_49; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_50; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_51; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_52; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_53; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_54; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_55; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_56; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_57; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_58; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_59; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_60; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_61; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_62; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_63; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_64; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_65; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_66; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_67; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_68; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_69; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_70; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_71; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_72; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_73; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_74; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_75; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_76; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_77; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_78; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_79; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_80; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_81; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_82; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_83; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_84; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_85; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_86; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_87; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_88; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_89; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_90; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_91; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_92; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_93; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_94; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_95; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_96; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_97; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_98; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_99; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_100; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_101; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_102; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_103; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_104; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_105; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_106; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_107; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_108; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_109; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_110; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_111; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_112; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_113; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_114; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_115; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_116; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_117; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_118; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_119; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_120; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_121; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_122; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_123; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_124; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_125; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_126; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_127; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_128; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_129; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_130; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_131; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_132; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_133; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_134; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_135; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_136; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_137; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_138; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_139; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_140; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_141; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_142; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_143; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_144; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_145; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_146; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_147; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_148; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_149; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_150; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_151; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_152; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_153; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_154; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_155; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_156; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_157; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_158; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_159; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_160; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_161; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_162; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_163; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_164; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_165; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_166; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_167; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_168; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_169; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_170; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_171; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_172; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_173; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_174; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_175; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_176; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_177; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_178; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_179; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_180; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_181; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_182; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_183; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_184; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_185; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_186; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_187; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_188; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_189; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_190; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_191; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_192; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_193; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_194; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_195; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_196; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_197; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_198; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_199; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_200; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_201; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_202; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_203; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_204; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_205; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_206; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_207; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_208; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_209; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_210; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_211; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_212; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_213; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_214; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_215; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_216; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_217; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_218; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_219; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_220; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_221; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_222; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_223; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_224; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_225; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_226; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_227; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_228; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_229; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_230; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_231; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_232; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_233; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_234; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_235; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_236; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_237; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_238; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_239; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_240; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_241; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_242; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_243; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_244; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_245; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_246; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_247; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_248; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_249; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_250; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_251; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_252; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_253; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_254; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg ghv_255; // src/main/scala/xiangshan/frontend/BPU.scala:311:20 + reg s0_ghist_ptr_reg_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + reg [7:0] s0_ghist_ptr_reg_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + reg s0_ghist_ptr_reg_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + reg [7:0] s0_ghist_ptr_reg_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + reg s0_ghist_ptr_reg_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + reg [7:0] s0_ghist_ptr_reg_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + reg s0_ghist_ptr_reg_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + reg [7:0] s0_ghist_ptr_reg_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + reg s1_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 + reg [7:0] s1_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 + reg s1_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 + reg [7:0] s1_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 + reg s1_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 + reg [7:0] s1_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 + reg s1_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 + reg [7:0] s1_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35 + reg s2_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 + reg [7:0] s2_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 + reg s2_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 + reg [7:0] s2_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 + reg s2_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 + reg [7:0] s2_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 + reg s2_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 + reg [7:0] s2_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35 + reg s3_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 + reg [7:0] s3_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 + reg s3_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 + reg [7:0] s3_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 + reg s3_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 + reg [7:0] s3_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 + reg s3_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 + reg [7:0] s3_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:325:35 + reg do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_level; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [38:0] do_redirect_dup_3_bits_cfiUpdate_pc; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_pd_isRVC; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_pd_isCall; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_pd_isRet; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [3:0] do_redirect_dup_3_bits_cfiUpdate_ssp; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [1:0] do_redirect_dup_3_bits_cfiUpdate_sctr; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_TOSW_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [4:0] do_redirect_dup_3_bits_cfiUpdate_TOSW_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_TOSR_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [4:0] do_redirect_dup_3_bits_cfiUpdate_TOSR_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_NOS_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [4:0] do_redirect_dup_3_bits_cfiUpdate_NOS_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [10:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [10:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [6:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [8:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [3:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [8:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [6:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [6:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [8:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [6:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [10:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [2:0] do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_histPtr_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [7:0] do_redirect_dup_3_bits_cfiUpdate_histPtr_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [38:0] do_redirect_dup_3_bits_cfiUpdate_target; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_taken; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg [1:0] thisBrNumOH_dup_shiftAmount; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + reg do_redirect_dup_3_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + wire s2_flush_dup_3 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :684:28 + wire s0_fire_dup_0 = + _predictors_io_s1_ready & (s1_fire_dup_0 | ~s1_valid_dup_3); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :365:{25,28}, :367:36, :374:60 + wire s0_fire_dup_1 = + _predictors_io_s1_ready & (s1_fire_dup_1 | ~s1_valid_dup_3); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :365:{25,28}, :367:36, :374:60 + wire s0_fire_dup_2 = + _predictors_io_s1_ready & (s1_fire_dup_2 | ~s1_valid_dup_3); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :365:{25,28}, :367:36, :374:60 + wire s0_fire_dup_3 = + _predictors_io_s1_ready & (s1_fire_dup_3 | ~s1_valid_dup_3); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :365:{25,28}, :367:36, :374:60 + assign s1_fire_dup_0 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :374:60 + assign s1_fire_dup_1 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :374:60 + assign s1_fire_dup_2 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :374:60 + assign s1_fire_dup_3 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :374:60 + wire [8:0] _GEN = {s1_ghist_ptr_dup_0_flag, s1_ghist_ptr_dup_0_value}; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1 = + 9'(_GEN - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3 = + 9'(_GEN + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5 = + 9'(_GEN + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _GEN_0 = {s1_ghist_ptr_dup_1_flag, s1_ghist_ptr_dup_1_value}; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7 = + 9'(_GEN_0 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9 = + 9'(_GEN_0 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11 = + 9'(_GEN_0 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _GEN_1 = {s1_ghist_ptr_dup_2_flag, s1_ghist_ptr_dup_2_value}; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13 = + 9'(_GEN_1 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15 = + 9'(_GEN_1 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17 = + 9'(_GEN_1 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _GEN_2 = {s1_ghist_ptr_dup_3_flag, s1_ghist_ptr_dup_3_value}; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19 = + 9'(_GEN_2 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21 = + 9'(_GEN_2 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23 = + 9'(_GEN_2 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire _s1_ghv_wdatas_WIRE_44494_1 = + _predictors_io_out_s1_full_pred_0_slot_valids_1 + & _predictors_io_out_s1_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 + wire _s1_predicted_ghist_ptr_dup_WIRE_56_0_0 = + ~_predictors_io_out_s1_full_pred_0_hit + | ~(_predictors_io_out_s1_full_pred_0_slot_valids_0 | _s1_ghv_wdatas_WIRE_44494_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _cfiIndex_bits_WIRE_18_0 = + _predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _cfiIndex_bits_T_94 = + _predictors_io_out_s1_full_pred_0_is_br_sharing + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire _s1_predicted_ghist_ptr_dup_WIRE_56_0_1 = + _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s1_predicted_ghist_ptr_dup_WIRE_56_0_2 = + _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s1_predicted_fh_dup_WIRE_21_1 = + _predictors_io_out_s1_full_pred_1_slot_valids_1 + & _predictors_io_out_s1_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 + wire _s1_predicted_ghist_ptr_dup_WIRE_56_1_0 = + ~_predictors_io_out_s1_full_pred_1_hit + | ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_predicted_fh_dup_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _cfiIndex_bits_WIRE_22_0 = + _predictors_io_out_s1_full_pred_1_slot_valids_0 + & _predictors_io_out_s1_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _cfiIndex_bits_T_115 = + _predictors_io_out_s1_full_pred_1_is_br_sharing + & _predictors_io_out_s1_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire _s1_predicted_ghist_ptr_dup_WIRE_56_1_1 = + _predictors_io_out_s1_full_pred_1_slot_valids_0 + & (_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit + | ~_s1_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s1_predicted_ghist_ptr_dup_WIRE_56_1_2 = + _s1_predicted_fh_dup_WIRE_21_1 + & ~(_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit) + & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s1_predicted_fh_dup_WIRE_35_1 = + _predictors_io_out_s1_full_pred_2_slot_valids_1 + & _predictors_io_out_s1_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 + wire _s1_predicted_ghist_ptr_dup_WIRE_56_2_0 = + ~_predictors_io_out_s1_full_pred_2_hit + | ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_predicted_fh_dup_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _cfiIndex_bits_WIRE_26_0 = + _predictors_io_out_s1_full_pred_2_slot_valids_0 + & _predictors_io_out_s1_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _cfiIndex_bits_T_136 = + _predictors_io_out_s1_full_pred_2_is_br_sharing + & _predictors_io_out_s1_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire _s1_predicted_ghist_ptr_dup_WIRE_56_2_1 = + _predictors_io_out_s1_full_pred_2_slot_valids_0 + & (_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit + | ~_s1_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s1_predicted_ghist_ptr_dup_WIRE_56_2_2 = + _s1_predicted_fh_dup_WIRE_35_1 + & ~(_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit) + & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s1_predicted_fh_dup_WIRE_49_1 = + _predictors_io_out_s1_full_pred_3_slot_valids_1 + & _predictors_io_out_s1_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 + wire _s1_predicted_ghist_ptr_dup_WIRE_56_3_0 = + ~_predictors_io_out_s1_full_pred_3_hit + | ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_predicted_fh_dup_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _cfiIndex_bits_WIRE_30_0 = + _predictors_io_out_s1_full_pred_3_slot_valids_0 + & _predictors_io_out_s1_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _cfiIndex_bits_T_157 = + _predictors_io_out_s1_full_pred_3_is_br_sharing + & _predictors_io_out_s1_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire _s1_predicted_ghist_ptr_dup_WIRE_56_3_1 = + _predictors_io_out_s1_full_pred_3_slot_valids_0 + & (_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit + | ~_s1_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s1_predicted_ghist_ptr_dup_WIRE_56_3_2 = + _s1_predicted_fh_dup_WIRE_49_1 + & ~(_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit) + & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s1_possible_predicted_fhs_dup_WIRE_4_1 = + _predictors_io_out_s1_full_pred_1_slot_valids_0 + & _predictors_io_out_s1_full_pred_1_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_1_hit | _s1_predicted_fh_dup_WIRE_21_1 + & _predictors_io_out_s1_full_pred_1_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :493:{74,90} + wire _s1_possible_predicted_fhs_dup_WIRE_4_2 = + _predictors_io_out_s1_full_pred_2_slot_valids_0 + & _predictors_io_out_s1_full_pred_2_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_2_hit | _s1_predicted_fh_dup_WIRE_35_1 + & _predictors_io_out_s1_full_pred_2_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :493:{74,90} + wire _s1_possible_predicted_fhs_dup_WIRE_4_3 = + _predictors_io_out_s1_full_pred_3_slot_valids_0 + & _predictors_io_out_s1_full_pred_3_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_3_hit | _s1_predicted_fh_dup_WIRE_49_1 + & _predictors_io_out_s1_full_pred_3_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :493:{74,90} + wire _s1_possible_predicted_fhs_dup_T_271 = + _s1_possible_predicted_fhs_dup_WIRE_4_1 + & (~_predictors_io_out_s1_full_pred_1_hit + | ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 + | _s1_predicted_fh_dup_WIRE_21_1)); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}, :493:90 + wire + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + = + _s1_possible_predicted_fhs_dup_WIRE_4_1 + & _predictors_io_out_s1_full_pred_1_slot_valids_0 + & (_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit + | ~_s1_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37}, :493:90 + wire + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + = + _s1_possible_predicted_fhs_dup_WIRE_4_1 & _s1_predicted_fh_dup_WIRE_21_1 + & ~(_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit) + & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :493:90 + wire _s1_possible_predicted_fhs_dup_T_274 = + _s1_possible_predicted_fhs_dup_WIRE_4_2 + & (~_predictors_io_out_s1_full_pred_2_hit + | ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 + | _s1_predicted_fh_dup_WIRE_35_1)); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}, :493:90 + wire + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + = + _s1_possible_predicted_fhs_dup_WIRE_4_2 + & _predictors_io_out_s1_full_pred_2_slot_valids_0 + & (_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit + | ~_s1_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37}, :493:90 + wire + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + = + _s1_possible_predicted_fhs_dup_WIRE_4_2 & _s1_predicted_fh_dup_WIRE_35_1 + & ~(_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit) + & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :493:90 + wire _s1_possible_predicted_fhs_dup_T_277 = + _s1_possible_predicted_fhs_dup_WIRE_4_3 + & (~_predictors_io_out_s1_full_pred_3_hit + | ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 + | _s1_predicted_fh_dup_WIRE_49_1)); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}, :493:90 + wire + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + = + _s1_possible_predicted_fhs_dup_WIRE_4_3 + & _predictors_io_out_s1_full_pred_3_slot_valids_0 + & (_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit + | ~_s1_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37}, :493:90 + wire + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + = + _s1_possible_predicted_fhs_dup_WIRE_4_3 & _s1_predicted_fh_dup_WIRE_49_1 + & ~(_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit) + & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :493:90 + wire _s1_predicted_fh_dup_WIRE_56_1_0 = + ~_predictors_io_out_s1_full_pred_1_hit + | ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_predicted_fh_dup_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _s1_predicted_fh_dup_WIRE_56_1_1 = + _predictors_io_out_s1_full_pred_1_slot_valids_0 + & (_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit + | ~_s1_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s1_predicted_fh_dup_WIRE_56_1_2 = + _s1_predicted_fh_dup_WIRE_21_1 + & ~(_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit) + & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s1_predicted_fh_dup_WIRE_56_2_0 = + ~_predictors_io_out_s1_full_pred_2_hit + | ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_predicted_fh_dup_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _s1_predicted_fh_dup_WIRE_56_2_1 = + _predictors_io_out_s1_full_pred_2_slot_valids_0 + & (_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit + | ~_s1_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s1_predicted_fh_dup_WIRE_56_2_2 = + _s1_predicted_fh_dup_WIRE_35_1 + & ~(_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit) + & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s1_predicted_fh_dup_WIRE_56_3_0 = + ~_predictors_io_out_s1_full_pred_3_hit + | ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_predicted_fh_dup_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _s1_predicted_fh_dup_WIRE_56_3_1 = + _predictors_io_out_s1_full_pred_3_slot_valids_0 + & (_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit + | ~_s1_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s1_predicted_fh_dup_WIRE_56_3_2 = + _s1_predicted_fh_dup_WIRE_49_1 + & ~(_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit) + & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire [255:0] _GEN_3 = + {{ghv_255}, + {ghv_254}, + {ghv_253}, + {ghv_252}, + {ghv_251}, + {ghv_250}, + {ghv_249}, + {ghv_248}, + {ghv_247}, + {ghv_246}, + {ghv_245}, + {ghv_244}, + {ghv_243}, + {ghv_242}, + {ghv_241}, + {ghv_240}, + {ghv_239}, + {ghv_238}, + {ghv_237}, + {ghv_236}, + {ghv_235}, + {ghv_234}, + {ghv_233}, + {ghv_232}, + {ghv_231}, + {ghv_230}, + {ghv_229}, + {ghv_228}, + {ghv_227}, + {ghv_226}, + {ghv_225}, + {ghv_224}, + {ghv_223}, + {ghv_222}, + {ghv_221}, + {ghv_220}, + {ghv_219}, + {ghv_218}, + {ghv_217}, + {ghv_216}, + {ghv_215}, + {ghv_214}, + {ghv_213}, + {ghv_212}, + {ghv_211}, + {ghv_210}, + {ghv_209}, + {ghv_208}, + {ghv_207}, + {ghv_206}, + {ghv_205}, + {ghv_204}, + {ghv_203}, + {ghv_202}, + {ghv_201}, + {ghv_200}, + {ghv_199}, + {ghv_198}, + {ghv_197}, + {ghv_196}, + {ghv_195}, + {ghv_194}, + {ghv_193}, + {ghv_192}, + {ghv_191}, + {ghv_190}, + {ghv_189}, + {ghv_188}, + {ghv_187}, + {ghv_186}, + {ghv_185}, + {ghv_184}, + {ghv_183}, + {ghv_182}, + {ghv_181}, + {ghv_180}, + {ghv_179}, + {ghv_178}, + {ghv_177}, + {ghv_176}, + {ghv_175}, + {ghv_174}, + {ghv_173}, + {ghv_172}, + {ghv_171}, + {ghv_170}, + {ghv_169}, + {ghv_168}, + {ghv_167}, + {ghv_166}, + {ghv_165}, + {ghv_164}, + {ghv_163}, + {ghv_162}, + {ghv_161}, + {ghv_160}, + {ghv_159}, + {ghv_158}, + {ghv_157}, + {ghv_156}, + {ghv_155}, + {ghv_154}, + {ghv_153}, + {ghv_152}, + {ghv_151}, + {ghv_150}, + {ghv_149}, + {ghv_148}, + {ghv_147}, + {ghv_146}, + {ghv_145}, + {ghv_144}, + {ghv_143}, + {ghv_142}, + {ghv_141}, + {ghv_140}, + {ghv_139}, + {ghv_138}, + {ghv_137}, + {ghv_136}, + {ghv_135}, + {ghv_134}, + {ghv_133}, + {ghv_132}, + {ghv_131}, + {ghv_130}, + {ghv_129}, + {ghv_128}, + {ghv_127}, + {ghv_126}, + {ghv_125}, + {ghv_124}, + {ghv_123}, + {ghv_122}, + {ghv_121}, + {ghv_120}, + {ghv_119}, + {ghv_118}, + {ghv_117}, + {ghv_116}, + {ghv_115}, + {ghv_114}, + {ghv_113}, + {ghv_112}, + {ghv_111}, + {ghv_110}, + {ghv_109}, + {ghv_108}, + {ghv_107}, + {ghv_106}, + {ghv_105}, + {ghv_104}, + {ghv_103}, + {ghv_102}, + {ghv_101}, + {ghv_100}, + {ghv_99}, + {ghv_98}, + {ghv_97}, + {ghv_96}, + {ghv_95}, + {ghv_94}, + {ghv_93}, + {ghv_92}, + {ghv_91}, + {ghv_90}, + {ghv_89}, + {ghv_88}, + {ghv_87}, + {ghv_86}, + {ghv_85}, + {ghv_84}, + {ghv_83}, + {ghv_82}, + {ghv_81}, + {ghv_80}, + {ghv_79}, + {ghv_78}, + {ghv_77}, + {ghv_76}, + {ghv_75}, + {ghv_74}, + {ghv_73}, + {ghv_72}, + {ghv_71}, + {ghv_70}, + {ghv_69}, + {ghv_68}, + {ghv_67}, + {ghv_66}, + {ghv_65}, + {ghv_64}, + {ghv_63}, + {ghv_62}, + {ghv_61}, + {ghv_60}, + {ghv_59}, + {ghv_58}, + {ghv_57}, + {ghv_56}, + {ghv_55}, + {ghv_54}, + {ghv_53}, + {ghv_52}, + {ghv_51}, + {ghv_50}, + {ghv_49}, + {ghv_48}, + {ghv_47}, + {ghv_46}, + {ghv_45}, + {ghv_44}, + {ghv_43}, + {ghv_42}, + {ghv_41}, + {ghv_40}, + {ghv_39}, + {ghv_38}, + {ghv_37}, + {ghv_36}, + {ghv_35}, + {ghv_34}, + {ghv_33}, + {ghv_32}, + {ghv_31}, + {ghv_30}, + {ghv_29}, + {ghv_28}, + {ghv_27}, + {ghv_26}, + {ghv_25}, + {ghv_24}, + {ghv_23}, + {ghv_22}, + {ghv_21}, + {ghv_20}, + {ghv_19}, + {ghv_18}, + {ghv_17}, + {ghv_16}, + {ghv_15}, + {ghv_14}, + {ghv_13}, + {ghv_12}, + {ghv_11}, + {ghv_10}, + {ghv_9}, + {ghv_8}, + {ghv_7}, + {ghv_6}, + {ghv_5}, + {ghv_4}, + {ghv_3}, + {ghv_2}, + {ghv_1}, + {ghv_0}}; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + wire s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0 = + _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2 = + _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3 = + _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0 = + _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0 = + _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2 = + _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3 = + _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0 = + _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0 = + _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2 = + _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3 = + _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0 = + _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s1_pred_info_takenMask_0_1 = + _predictors_io_out_s1_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_94 | ~_predictors_io_out_s1_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire [38:0] _GEN_4 = + _predictors_io_out_s1_full_pred_0_hit + ? 39'h0 + : 39'(_predictors_io_out_s1_pc_0 + 39'h20); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + wire s1_pred_info_takenMask_1_1 = + _predictors_io_out_s1_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_115 | ~_predictors_io_out_s1_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire [38:0] _GEN_5 = + _predictors_io_out_s1_full_pred_1_hit + ? 39'h0 + : 39'(_predictors_io_out_s1_pc_1 + 39'h20); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + wire s1_pred_info_takenMask_2_1 = + _predictors_io_out_s1_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_136 | ~_predictors_io_out_s1_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire [38:0] _GEN_6 = + _predictors_io_out_s1_full_pred_2_hit + ? 39'h0 + : 39'(_predictors_io_out_s1_pc_2 + 39'h20); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + wire s1_pred_info_takenMask_3_1 = + _predictors_io_out_s1_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_157 | ~_predictors_io_out_s1_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire [38:0] _GEN_7 = + _predictors_io_out_s1_full_pred_3_hit + ? 39'h0 + : 39'(_predictors_io_out_s1_pc_3 + 39'h20); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + wire _GEN_8 = + _predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_predicted_fh_dup_WIRE_21_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:41 + wire _GEN_9 = + _cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 + wire _GEN_10 = _GEN_9 | ~_s1_predicted_fh_dup_WIRE_21_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :488:{34,37} + wire _GEN_11 = + _predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_predicted_fh_dup_WIRE_35_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:41 + wire _GEN_12 = + _cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 + wire _GEN_13 = _GEN_12 | ~_s1_predicted_fh_dup_WIRE_35_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :488:{34,37} + wire _GEN_14 = + _predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_predicted_fh_dup_WIRE_49_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:41 + wire _GEN_15 = + _cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 + wire _GEN_16 = _GEN_15 | ~_s1_predicted_fh_dup_WIRE_49_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :488:{34,37} + wire _ghv_wens_0_T = + ~(|s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_1_T = + s1_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_2_T = + s1_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_3_T = + s1_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_4_T = + s1_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_5_T = + s1_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_6_T = + s1_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_7_T = + s1_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_8_T = + s1_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_9_T = + s1_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_10_T = + s1_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_11_T = + s1_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_12_T = + s1_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_13_T = + s1_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_14_T = + s1_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_15_T = + s1_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h10 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_16_T = + s1_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h11 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_17_T = + s1_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h12 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_18_T = + s1_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h13 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_19_T = + s1_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h14 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_20_T = + s1_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h15 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_21_T = + s1_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h16 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_22_T = + s1_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h17 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_23_T = + s1_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h18 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_24_T = + s1_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h19 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_25_T = + s1_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_26_T = + s1_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_27_T = + s1_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_28_T = + s1_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_29_T = + s1_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_30_T = + s1_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_31_T = + s1_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h20 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_32_T = + s1_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h21 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_33_T = + s1_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h22 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_34_T = + s1_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h23 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_35_T = + s1_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h24 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_36_T = + s1_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h25 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_37_T = + s1_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h26 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_38_T = + s1_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h27 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_39_T = + s1_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h28 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_40_T = + s1_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h29 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_41_T = + s1_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_42_T = + s1_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_43_T = + s1_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_44_T = + s1_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_45_T = + s1_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_46_T = + s1_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_47_T = + s1_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h30 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_48_T = + s1_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h31 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_49_T = + s1_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h32 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_50_T = + s1_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h33 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_51_T = + s1_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h34 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_52_T = + s1_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h35 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_53_T = + s1_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h36 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_54_T = + s1_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h37 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_55_T = + s1_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h38 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_56_T = + s1_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h39 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_57_T = + s1_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_58_T = + s1_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_59_T = + s1_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_60_T = + s1_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_61_T = + s1_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_62_T = + s1_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_63_T = + s1_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h40 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_64_T = + s1_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h41 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_65_T = + s1_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h42 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_66_T = + s1_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h43 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_67_T = + s1_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h44 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_68_T = + s1_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h45 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_69_T = + s1_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h46 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_70_T = + s1_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h47 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_71_T = + s1_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h48 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_72_T = + s1_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h49 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_73_T = + s1_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_74_T = + s1_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_75_T = + s1_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_76_T = + s1_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_77_T = + s1_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_78_T = + s1_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_79_T = + s1_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h50 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_80_T = + s1_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h51 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_81_T = + s1_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h52 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_82_T = + s1_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h53 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_83_T = + s1_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h54 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_84_T = + s1_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h55 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_85_T = + s1_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h56 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_86_T = + s1_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h57 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_87_T = + s1_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h58 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_88_T = + s1_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h59 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_89_T = + s1_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_90_T = + s1_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_91_T = + s1_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_92_T = + s1_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_93_T = + s1_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_94_T = + s1_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_95_T = + s1_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h60 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_96_T = + s1_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h61 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_97_T = + s1_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h62 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_98_T = + s1_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h63 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_99_T = + s1_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h64 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_100_T = + s1_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h65 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_101_T = + s1_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h66 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_102_T = + s1_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h67 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_103_T = + s1_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h68 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_104_T = + s1_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h69 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_105_T = + s1_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_106_T = + s1_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_107_T = + s1_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_108_T = + s1_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_109_T = + s1_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_110_T = + s1_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_111_T = + s1_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h70 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_112_T = + s1_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h71 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_113_T = + s1_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h72 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_114_T = + s1_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h73 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_115_T = + s1_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h74 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_116_T = + s1_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h75 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_117_T = + s1_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h76 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_118_T = + s1_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h77 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_119_T = + s1_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h78 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_120_T = + s1_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h79 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_121_T = + s1_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_122_T = + s1_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_123_T = + s1_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_124_T = + s1_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_125_T = + s1_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_126_T = + s1_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_127_T = + s1_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h80 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_128_T = + s1_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h81 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_129_T = + s1_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h82 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_130_T = + s1_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h83 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_131_T = + s1_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h84 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_132_T = + s1_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h85 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_133_T = + s1_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h86 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_134_T = + s1_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h87 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_135_T = + s1_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h88 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_136_T = + s1_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h89 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_137_T = + s1_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_138_T = + s1_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_139_T = + s1_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_140_T = + s1_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_141_T = + s1_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_142_T = + s1_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_143_T = + s1_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h90 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_144_T = + s1_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h91 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_145_T = + s1_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h92 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_146_T = + s1_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h93 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_147_T = + s1_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h94 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_148_T = + s1_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h95 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_149_T = + s1_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h96 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_150_T = + s1_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h97 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_151_T = + s1_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h98 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_152_T = + s1_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h99 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_153_T = + s1_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_154_T = + s1_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_155_T = + s1_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_156_T = + s1_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_157_T = + s1_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_158_T = + s1_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_159_T = + s1_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA0 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_160_T = + s1_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_161_T = + s1_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_162_T = + s1_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_163_T = + s1_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_164_T = + s1_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_165_T = + s1_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_166_T = + s1_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_167_T = + s1_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_168_T = + s1_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_169_T = + s1_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_170_T = + s1_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_171_T = + s1_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_172_T = + s1_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAD & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_173_T = + s1_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_174_T = + s1_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAF & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_175_T = + s1_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB0 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_176_T = + s1_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_177_T = + s1_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_178_T = + s1_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_179_T = + s1_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_180_T = + s1_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_181_T = + s1_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_182_T = + s1_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_183_T = + s1_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_184_T = + s1_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_185_T = + s1_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_186_T = + s1_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_187_T = + s1_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_188_T = + s1_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBD & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_189_T = + s1_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_190_T = + s1_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBF & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_191_T = + s1_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC0 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_192_T = + s1_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_193_T = + s1_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_194_T = + s1_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_195_T = + s1_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_196_T = + s1_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_197_T = + s1_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_198_T = + s1_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_199_T = + s1_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_200_T = + s1_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_201_T = + s1_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_202_T = + s1_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_203_T = + s1_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_204_T = + s1_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCD & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_205_T = + s1_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_206_T = + s1_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCF & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_207_T = + s1_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD0 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_208_T = + s1_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_209_T = + s1_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_210_T = + s1_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_211_T = + s1_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_212_T = + s1_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_213_T = + s1_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_214_T = + s1_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_215_T = + s1_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_216_T = + s1_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_217_T = + s1_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_218_T = + s1_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_219_T = + s1_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_220_T = + s1_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDD & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_221_T = + s1_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_222_T = + s1_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDF & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_223_T = + s1_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE0 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_224_T = + s1_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_225_T = + s1_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_226_T = + s1_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_227_T = + s1_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_228_T = + s1_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_229_T = + s1_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_230_T = + s1_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_231_T = + s1_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_232_T = + s1_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_233_T = + s1_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_234_T = + s1_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_235_T = + s1_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_236_T = + s1_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hED & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_237_T = + s1_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_238_T = + s1_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEF & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_239_T = + s1_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF0 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_240_T = + s1_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_241_T = + s1_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_242_T = + s1_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_243_T = + s1_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_244_T = + s1_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_245_T = + s1_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_246_T = + s1_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_247_T = + s1_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_248_T = + s1_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_249_T = + s1_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_250_T = + s1_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_251_T = + s1_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_252_T = + s1_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFD & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_253_T = + s1_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_254_T = + s1_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | (&s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_255_T = + (&s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | ~(|s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire [8:0] _GEN_17 = {s2_ghist_ptr_dup_0_flag, s2_ghist_ptr_dup_0_value}; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1 = + 9'(_GEN_17 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3 = + 9'(_GEN_17 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5 = + 9'(_GEN_17 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _GEN_18 = {s2_ghist_ptr_dup_1_flag, s2_ghist_ptr_dup_1_value}; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7 = + 9'(_GEN_18 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9 = + 9'(_GEN_18 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11 = + 9'(_GEN_18 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _GEN_19 = {s2_ghist_ptr_dup_2_flag, s2_ghist_ptr_dup_2_value}; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13 = + 9'(_GEN_19 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15 = + 9'(_GEN_19 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17 = + 9'(_GEN_19 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _GEN_20 = {s2_ghist_ptr_dup_3_flag, s2_ghist_ptr_dup_3_value}; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19 = + 9'(_GEN_20 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21 = + 9'(_GEN_20 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23 = + 9'(_GEN_20 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 = + _predictors_io_out_s2_full_pred_0_slot_valids_1 + & _predictors_io_out_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 + wire _s2_predicted_ghist_ptr_dup_WIRE_56_0_0 = + ~_predictors_io_out_s2_full_pred_0_hit + | ~(_predictors_io_out_s2_full_pred_0_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _selVecOH_T_66 = + _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _predictors_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _cfiIndex_bits_T_262 = + _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 = + _predictors_io_out_s2_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:474:27 + wire _s2_predicted_ghist_ptr_dup_WIRE_56_0_1 = + _predictors_io_out_s2_full_pred_0_slot_valids_0 + & (_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1) + & _predictors_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s2_predicted_ghist_ptr_dup_WIRE_56_0_2 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _predictors_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1 = + _predictors_io_out_s2_full_pred_1_slot_valids_1 + & _predictors_io_out_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 + wire _s2_predicted_ghist_ptr_dup_WIRE_56_1_0 = + ~_predictors_io_out_s2_full_pred_1_hit + | ~(_predictors_io_out_s2_full_pred_1_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _selVecOH_T_74 = + _predictors_io_out_s2_full_pred_1_slot_valids_0 + & _predictors_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _cfiIndex_bits_T_283 = + _predictors_io_out_s2_full_pred_1_is_br_sharing + & _predictors_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire _s2_predicted_ghist_ptr_dup_WIRE_56_1_1 = + _predictors_io_out_s2_full_pred_1_slot_valids_0 + & (_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1) + & _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s2_predicted_ghist_ptr_dup_WIRE_56_1_2 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1 + & ~(_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit) + & _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1 = + _predictors_io_out_s2_full_pred_2_slot_valids_1 + & _predictors_io_out_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 + wire _s2_predicted_ghist_ptr_dup_WIRE_56_2_0 = + ~_predictors_io_out_s2_full_pred_2_hit + | ~(_predictors_io_out_s2_full_pred_2_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _selVecOH_T_82 = + _predictors_io_out_s2_full_pred_2_slot_valids_0 + & _predictors_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _cfiIndex_bits_T_304 = + _predictors_io_out_s2_full_pred_2_is_br_sharing + & _predictors_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire _s2_predicted_ghist_ptr_dup_WIRE_56_2_1 = + _predictors_io_out_s2_full_pred_2_slot_valids_0 + & (_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1) + & _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s2_predicted_ghist_ptr_dup_WIRE_56_2_2 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1 + & ~(_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit) + & _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1 = + _predictors_io_out_s2_full_pred_3_slot_valids_1 + & _predictors_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 + wire _s2_predicted_ghist_ptr_dup_WIRE_56_3_0 = + ~_predictors_io_out_s2_full_pred_3_hit + | ~(_predictors_io_out_s2_full_pred_3_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _selVecOH_T_90 = + _predictors_io_out_s2_full_pred_3_slot_valids_0 + & _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _cfiIndex_bits_T_325 = + _predictors_io_out_s2_full_pred_3_is_br_sharing + & _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire _s2_predicted_ghist_ptr_dup_WIRE_56_3_1 = + _predictors_io_out_s2_full_pred_3_slot_valids_0 + & (_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1) + & _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s2_predicted_ghist_ptr_dup_WIRE_56_3_2 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1 + & ~(_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit) + & _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s2_predicted_fh_dup_WIRE_56_1_0 = + ~_predictors_io_out_s2_full_pred_1_hit + | ~(_predictors_io_out_s2_full_pred_1_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _s2_predicted_fh_dup_WIRE_56_1_1 = + _predictors_io_out_s2_full_pred_1_slot_valids_0 + & (_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1) + & _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s2_predicted_fh_dup_WIRE_56_1_2 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1 + & ~(_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit) + & _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s2_predicted_fh_dup_WIRE_56_2_0 = + ~_predictors_io_out_s2_full_pred_2_hit + | ~(_predictors_io_out_s2_full_pred_2_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _s2_predicted_fh_dup_WIRE_56_2_1 = + _predictors_io_out_s2_full_pred_2_slot_valids_0 + & (_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1) + & _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s2_predicted_fh_dup_WIRE_56_2_2 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1 + & ~(_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit) + & _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s2_predicted_fh_dup_WIRE_56_3_0 = + ~_predictors_io_out_s2_full_pred_3_hit + | ~(_predictors_io_out_s2_full_pred_3_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _s2_predicted_fh_dup_WIRE_56_3_1 = + _predictors_io_out_s2_full_pred_3_slot_valids_0 + & (_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1) + & _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s2_predicted_fh_dup_WIRE_56_3_2 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1 + & ~(_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit) + & _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0 = + _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2 = + _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3 = + _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0 = + _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0 = + _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2 = + _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3 = + _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0 = + _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0 = + _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2 = + _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3 = + _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0 = + _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + reg previous_s1_pred_info_hit_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_hit_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_hit_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_hit_3; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg [38:0] previous_s1_pred_info_target_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg [38:0] previous_s1_pred_info_target_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg [38:0] previous_s1_pred_info_target_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg [38:0] previous_s1_pred_info_target_3; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_lastBrPosOH_0_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_lastBrPosOH_0_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_lastBrPosOH_0_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_lastBrPosOH_1_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_lastBrPosOH_1_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_lastBrPosOH_1_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_lastBrPosOH_2_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_lastBrPosOH_2_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_lastBrPosOH_2_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_lastBrPosOH_3_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_lastBrPosOH_3_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_lastBrPosOH_3_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_taken_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_taken_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_taken_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_taken_3; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_takenMask_0_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_takenMask_0_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_takenMask_1_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_takenMask_1_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_takenMask_2_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_takenMask_2_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_takenMask_3_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg previous_s1_pred_info_takenMask_3_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg [3:0] previous_s1_pred_info_cfiIndex_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg [3:0] previous_s1_pred_info_cfiIndex_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg [3:0] previous_s1_pred_info_cfiIndex_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + reg [3:0] previous_s1_pred_info_cfiIndex_3; // src/main/scala/xiangshan/frontend/BPU.scala:600:40 + wire [38:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_0_3 = + 39'(_predictors_io_out_s2_pc_0 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + wire [38:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_1_3 = + 39'(_predictors_io_out_s2_pc_1 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + wire [38:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_2_3 = + 39'(_predictors_io_out_s2_pc_2 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + wire [38:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_3_3 = + 39'(_predictors_io_out_s2_pc_3 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + assign s2_redirect_dup_0 = + s2_valid_dup_3 + & (previous_s1_pred_info_takenMask_0_0 & previous_s1_pred_info_hit_0 + & _predictors_io_out_s2_full_pred_0_targets_0 != previous_s1_pred_info_target_0 + | ~previous_s1_pred_info_takenMask_0_0 & previous_s1_pred_info_takenMask_0_1 + & previous_s1_pred_info_hit_0 + & _predictors_io_out_s2_full_pred_0_targets_1 != previous_s1_pred_info_target_0 + | {previous_s1_pred_info_takenMask_0_1, + previous_s1_pred_info_takenMask_0_0} == 2'h0 & previous_s1_pred_info_hit_0 + & _predictors_io_out_s2_full_pred_0_fallThroughAddr != previous_s1_pred_info_target_0 + | ~previous_s1_pred_info_hit_0 + & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_0_3 != previous_s1_pred_info_target_0 + | {previous_s1_pred_info_lastBrPosOH_0_2, + previous_s1_pred_info_lastBrPosOH_0_1, + previous_s1_pred_info_lastBrPosOH_0_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 + & _predictors_io_out_s2_full_pred_0_hit) + & _predictors_io_out_s2_full_pred_0_hit, + _predictors_io_out_s2_full_pred_0_slot_valids_0 + & (_selVecOH_T_66 + & _predictors_io_out_s2_full_pred_0_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1) + & _predictors_io_out_s2_full_pred_0_hit, + ~_predictors_io_out_s2_full_pred_0_hit + | ~(_predictors_io_out_s2_full_pred_0_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1)} + | previous_s1_pred_info_taken_0 != (|{_predictors_io_out_s2_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_262 + | ~_predictors_io_out_s2_full_pred_0_is_br_sharing) + & _predictors_io_out_s2_full_pred_0_hit, + _selVecOH_T_66 + & _predictors_io_out_s2_full_pred_0_hit}) + | previous_s1_pred_info_taken_0 + & (|{_predictors_io_out_s2_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_262 | ~_predictors_io_out_s2_full_pred_0_is_br_sharing) + & _predictors_io_out_s2_full_pred_0_hit, + _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit}) + & previous_s1_pred_info_cfiIndex_0 != ((_selVecOH_T_66 + & _predictors_io_out_s2_full_pred_0_hit + ? _predictors_io_out_s2_full_pred_0_offsets_0 + : _predictors_io_out_s2_full_pred_0_offsets_1) + | {4{{_predictors_io_out_s2_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_262 + | ~_predictors_io_out_s2_full_pred_0_is_br_sharing) + & _predictors_io_out_s2_full_pred_0_hit, + _selVecOH_T_66 + & _predictors_io_out_s2_full_pred_0_hit} == 2'h0}})); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :535:64, :542:{112,119,127}, :543:97, :544:{147,153}, :600:40, :605:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:51, :421:{21,28,43}, :453:48, :458:69, :460:{25,47,50}, :467:38, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}, :505:47, :519:{46,53}, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + wire s2_redirect_dup_1 = + s2_valid_dup_3 + & (previous_s1_pred_info_takenMask_1_0 & previous_s1_pred_info_hit_1 + & _predictors_io_out_s2_full_pred_1_targets_0 != previous_s1_pred_info_target_1 + | ~previous_s1_pred_info_takenMask_1_0 & previous_s1_pred_info_takenMask_1_1 + & previous_s1_pred_info_hit_1 + & _predictors_io_out_s2_full_pred_1_targets_1 != previous_s1_pred_info_target_1 + | {previous_s1_pred_info_takenMask_1_1, + previous_s1_pred_info_takenMask_1_0} == 2'h0 & previous_s1_pred_info_hit_1 + & _predictors_io_out_s2_full_pred_1_fallThroughAddr != previous_s1_pred_info_target_1 + | ~previous_s1_pred_info_hit_1 + & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_1_3 != previous_s1_pred_info_target_1 + | {previous_s1_pred_info_lastBrPosOH_1_2, + previous_s1_pred_info_lastBrPosOH_1_1, + previous_s1_pred_info_lastBrPosOH_1_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1 + & ~(_selVecOH_T_74 + & _predictors_io_out_s2_full_pred_1_hit) + & _predictors_io_out_s2_full_pred_1_hit, + _predictors_io_out_s2_full_pred_1_slot_valids_0 + & (_selVecOH_T_74 + & _predictors_io_out_s2_full_pred_1_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1) + & _predictors_io_out_s2_full_pred_1_hit, + ~_predictors_io_out_s2_full_pred_1_hit + | ~(_predictors_io_out_s2_full_pred_1_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1)} + | previous_s1_pred_info_taken_1 != (|{_predictors_io_out_s2_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_283 + | ~_predictors_io_out_s2_full_pred_1_is_br_sharing) + & _predictors_io_out_s2_full_pred_1_hit, + _selVecOH_T_74 + & _predictors_io_out_s2_full_pred_1_hit}) + | previous_s1_pred_info_taken_1 + & (|{_predictors_io_out_s2_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_283 | ~_predictors_io_out_s2_full_pred_1_is_br_sharing) + & _predictors_io_out_s2_full_pred_1_hit, + _selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit}) + & previous_s1_pred_info_cfiIndex_1 != ((_selVecOH_T_74 + & _predictors_io_out_s2_full_pred_1_hit + ? _predictors_io_out_s2_full_pred_1_offsets_0 + : _predictors_io_out_s2_full_pred_1_offsets_1) + | {4{{_predictors_io_out_s2_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_283 + | ~_predictors_io_out_s2_full_pred_1_is_br_sharing) + & _predictors_io_out_s2_full_pred_1_hit, + _selVecOH_T_74 + & _predictors_io_out_s2_full_pred_1_hit} == 2'h0}})); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :535:64, :542:{112,119,127}, :543:97, :544:{147,153}, :600:40, :605:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:51, :421:{21,28,43}, :453:48, :458:69, :460:{25,47,50}, :467:38, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}, :505:47, :519:{46,53}, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + assign s2_redirect_dup_2 = + s2_valid_dup_3 + & (previous_s1_pred_info_takenMask_2_0 & previous_s1_pred_info_hit_2 + & _predictors_io_out_s2_full_pred_2_targets_0 != previous_s1_pred_info_target_2 + | ~previous_s1_pred_info_takenMask_2_0 & previous_s1_pred_info_takenMask_2_1 + & previous_s1_pred_info_hit_2 + & _predictors_io_out_s2_full_pred_2_targets_1 != previous_s1_pred_info_target_2 + | {previous_s1_pred_info_takenMask_2_1, + previous_s1_pred_info_takenMask_2_0} == 2'h0 & previous_s1_pred_info_hit_2 + & _predictors_io_out_s2_full_pred_2_fallThroughAddr != previous_s1_pred_info_target_2 + | ~previous_s1_pred_info_hit_2 + & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_2_3 != previous_s1_pred_info_target_2 + | {previous_s1_pred_info_lastBrPosOH_2_2, + previous_s1_pred_info_lastBrPosOH_2_1, + previous_s1_pred_info_lastBrPosOH_2_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1 + & ~(_selVecOH_T_82 + & _predictors_io_out_s2_full_pred_2_hit) + & _predictors_io_out_s2_full_pred_2_hit, + _predictors_io_out_s2_full_pred_2_slot_valids_0 + & (_selVecOH_T_82 + & _predictors_io_out_s2_full_pred_2_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1) + & _predictors_io_out_s2_full_pred_2_hit, + ~_predictors_io_out_s2_full_pred_2_hit + | ~(_predictors_io_out_s2_full_pred_2_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1)} + | previous_s1_pred_info_taken_2 != (|{_predictors_io_out_s2_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_304 + | ~_predictors_io_out_s2_full_pred_2_is_br_sharing) + & _predictors_io_out_s2_full_pred_2_hit, + _selVecOH_T_82 + & _predictors_io_out_s2_full_pred_2_hit}) + | previous_s1_pred_info_taken_2 + & (|{_predictors_io_out_s2_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_304 | ~_predictors_io_out_s2_full_pred_2_is_br_sharing) + & _predictors_io_out_s2_full_pred_2_hit, + _selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit}) + & previous_s1_pred_info_cfiIndex_2 != ((_selVecOH_T_82 + & _predictors_io_out_s2_full_pred_2_hit + ? _predictors_io_out_s2_full_pred_2_offsets_0 + : _predictors_io_out_s2_full_pred_2_offsets_1) + | {4{{_predictors_io_out_s2_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_304 + | ~_predictors_io_out_s2_full_pred_2_is_br_sharing) + & _predictors_io_out_s2_full_pred_2_hit, + _selVecOH_T_82 + & _predictors_io_out_s2_full_pred_2_hit} == 2'h0}})); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :535:64, :542:{112,119,127}, :543:97, :544:{147,153}, :600:40, :605:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:51, :421:{21,28,43}, :453:48, :458:69, :460:{25,47,50}, :467:38, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}, :505:47, :519:{46,53}, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + wire s2_redirect_dup_3 = + s2_valid_dup_3 + & (previous_s1_pred_info_takenMask_3_0 & previous_s1_pred_info_hit_3 + & _predictors_io_out_s2_full_pred_3_targets_0 != previous_s1_pred_info_target_3 + | ~previous_s1_pred_info_takenMask_3_0 & previous_s1_pred_info_takenMask_3_1 + & previous_s1_pred_info_hit_3 + & _predictors_io_out_s2_full_pred_3_targets_1 != previous_s1_pred_info_target_3 + | {previous_s1_pred_info_takenMask_3_1, + previous_s1_pred_info_takenMask_3_0} == 2'h0 & previous_s1_pred_info_hit_3 + & _predictors_io_out_s2_full_pred_3_fallThroughAddr != previous_s1_pred_info_target_3 + | ~previous_s1_pred_info_hit_3 + & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_3_3 != previous_s1_pred_info_target_3 + | {previous_s1_pred_info_lastBrPosOH_3_2, + previous_s1_pred_info_lastBrPosOH_3_1, + previous_s1_pred_info_lastBrPosOH_3_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1 + & ~(_selVecOH_T_90 + & _predictors_io_out_s2_full_pred_3_hit) + & _predictors_io_out_s2_full_pred_3_hit, + _predictors_io_out_s2_full_pred_3_slot_valids_0 + & (_selVecOH_T_90 + & _predictors_io_out_s2_full_pred_3_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1) + & _predictors_io_out_s2_full_pred_3_hit, + ~_predictors_io_out_s2_full_pred_3_hit + | ~(_predictors_io_out_s2_full_pred_3_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1)} + | previous_s1_pred_info_taken_3 != (|{_predictors_io_out_s2_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_325 + | ~_predictors_io_out_s2_full_pred_3_is_br_sharing) + & _predictors_io_out_s2_full_pred_3_hit, + _selVecOH_T_90 + & _predictors_io_out_s2_full_pred_3_hit}) + | previous_s1_pred_info_taken_3 + & (|{_predictors_io_out_s2_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_325 | ~_predictors_io_out_s2_full_pred_3_is_br_sharing) + & _predictors_io_out_s2_full_pred_3_hit, + _selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit}) + & previous_s1_pred_info_cfiIndex_3 != ((_selVecOH_T_90 + & _predictors_io_out_s2_full_pred_3_hit + ? _predictors_io_out_s2_full_pred_3_offsets_0 + : _predictors_io_out_s2_full_pred_3_offsets_1) + | {4{{_predictors_io_out_s2_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_325 + | ~_predictors_io_out_s2_full_pred_3_is_br_sharing) + & _predictors_io_out_s2_full_pred_3_hit, + _selVecOH_T_90 + & _predictors_io_out_s2_full_pred_3_hit} == 2'h0}})); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :535:64, :542:{112,119,127}, :543:97, :544:{147,153}, :600:40, :605:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:51, :421:{21,28,43}, :453:48, :458:69, :460:{25,47,50}, :467:38, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}, :505:47, :519:{46,53}, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + wire _GEN_21 = + _predictors_io_out_s2_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_262 | ~_predictors_io_out_s2_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire _GEN_22 = + _predictors_io_out_s2_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_283 | ~_predictors_io_out_s2_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire _GEN_23 = + _predictors_io_out_s2_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_304 | ~_predictors_io_out_s2_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire _GEN_24 = + _predictors_io_out_s2_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_325 | ~_predictors_io_out_s2_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire _GEN_25 = _selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 + wire _GEN_26 = _selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 + wire _GEN_27 = _selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 + wire _ghv_wens_0_T_1 = + ~(|s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_1_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_2_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_3_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_4_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_5_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_6_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_7_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_8_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_9_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_10_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_11_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_12_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_13_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_14_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_15_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h10 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_16_T_1 = + s2_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h11 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_17_T_1 = + s2_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_18_T_1 = + s2_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h13 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_19_T_1 = + s2_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h14 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_20_T_1 = + s2_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h15 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_21_T_1 = + s2_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h16 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_22_T_1 = + s2_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h17 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_23_T_1 = + s2_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h18 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_24_T_1 = + s2_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h19 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_25_T_1 = + s2_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_26_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_27_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_28_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_29_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_30_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_31_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h20 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_32_T_1 = + s2_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h21 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_33_T_1 = + s2_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h22 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_34_T_1 = + s2_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h23 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_35_T_1 = + s2_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h24 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_36_T_1 = + s2_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h25 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_37_T_1 = + s2_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h26 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_38_T_1 = + s2_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h27 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_39_T_1 = + s2_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h28 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_40_T_1 = + s2_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h29 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_41_T_1 = + s2_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_42_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_43_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_44_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_45_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_46_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_47_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h30 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_48_T_1 = + s2_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h31 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_49_T_1 = + s2_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h32 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_50_T_1 = + s2_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h33 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_51_T_1 = + s2_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h34 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_52_T_1 = + s2_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h35 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_53_T_1 = + s2_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h36 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_54_T_1 = + s2_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h37 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_55_T_1 = + s2_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h38 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_56_T_1 = + s2_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h39 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_57_T_1 = + s2_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_58_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_59_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_60_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_61_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_62_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_63_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h40 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_64_T_1 = + s2_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h41 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_65_T_1 = + s2_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h42 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_66_T_1 = + s2_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h43 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_67_T_1 = + s2_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h44 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_68_T_1 = + s2_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h45 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_69_T_1 = + s2_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h46 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_70_T_1 = + s2_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h47 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_71_T_1 = + s2_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h48 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_72_T_1 = + s2_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h49 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_73_T_1 = + s2_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_74_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_75_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_76_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_77_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_78_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_79_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h50 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_80_T_1 = + s2_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h51 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_81_T_1 = + s2_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h52 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_82_T_1 = + s2_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h53 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_83_T_1 = + s2_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h54 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_84_T_1 = + s2_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h55 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_85_T_1 = + s2_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h56 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_86_T_1 = + s2_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h57 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_87_T_1 = + s2_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h58 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_88_T_1 = + s2_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h59 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_89_T_1 = + s2_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_90_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_91_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_92_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_93_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_94_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_95_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h60 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_96_T_1 = + s2_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h61 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_97_T_1 = + s2_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h62 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_98_T_1 = + s2_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h63 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_99_T_1 = + s2_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h64 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_100_T_1 = + s2_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h65 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_101_T_1 = + s2_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h66 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_102_T_1 = + s2_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h67 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_103_T_1 = + s2_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h68 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_104_T_1 = + s2_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h69 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_105_T_1 = + s2_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_106_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_107_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_108_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_109_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_110_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_111_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h70 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_112_T_1 = + s2_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h71 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_113_T_1 = + s2_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h72 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_114_T_1 = + s2_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h73 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_115_T_1 = + s2_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h74 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_116_T_1 = + s2_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h75 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_117_T_1 = + s2_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h76 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_118_T_1 = + s2_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h77 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_119_T_1 = + s2_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h78 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_120_T_1 = + s2_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h79 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_121_T_1 = + s2_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_122_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_123_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_124_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_125_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_126_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_127_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h80 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_128_T_1 = + s2_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h81 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_129_T_1 = + s2_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h82 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_130_T_1 = + s2_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h83 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_131_T_1 = + s2_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h84 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_132_T_1 = + s2_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h85 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_133_T_1 = + s2_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h86 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_134_T_1 = + s2_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h87 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_135_T_1 = + s2_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h88 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_136_T_1 = + s2_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h89 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_137_T_1 = + s2_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_138_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_139_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_140_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_141_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_142_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_143_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h90 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_144_T_1 = + s2_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h91 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_145_T_1 = + s2_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h92 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_146_T_1 = + s2_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h93 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_147_T_1 = + s2_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h94 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_148_T_1 = + s2_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h95 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_149_T_1 = + s2_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h96 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_150_T_1 = + s2_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h97 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_151_T_1 = + s2_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h98 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_152_T_1 = + s2_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h99 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_153_T_1 = + s2_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_154_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_155_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_156_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_157_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_158_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_159_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_160_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_161_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_162_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_163_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_164_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_165_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_166_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_167_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_168_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_169_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_170_T_1 = + s2_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_171_T_1 = + s2_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_172_T_1 = + s2_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_173_T_1 = + s2_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_174_T_1 = + s2_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_175_T_1 = + s2_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_176_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_177_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_178_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_179_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_180_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_181_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_182_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_183_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_184_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_185_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_186_T_1 = + s2_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_187_T_1 = + s2_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_188_T_1 = + s2_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_189_T_1 = + s2_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_190_T_1 = + s2_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_191_T_1 = + s2_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_192_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_193_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_194_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_195_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_196_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_197_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_198_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_199_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_200_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_201_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_202_T_1 = + s2_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_203_T_1 = + s2_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_204_T_1 = + s2_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_205_T_1 = + s2_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_206_T_1 = + s2_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_207_T_1 = + s2_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_208_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_209_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_210_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_211_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_212_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_213_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_214_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_215_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_216_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_217_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_218_T_1 = + s2_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_219_T_1 = + s2_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_220_T_1 = + s2_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_221_T_1 = + s2_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_222_T_1 = + s2_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_223_T_1 = + s2_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_224_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_225_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_226_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_227_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_228_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_229_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_230_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_231_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_232_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_233_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_234_T_1 = + s2_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_235_T_1 = + s2_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_236_T_1 = + s2_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hED + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_237_T_1 = + s2_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_238_T_1 = + s2_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_239_T_1 = + s2_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_240_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_241_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_242_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_243_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_244_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_245_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_246_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_247_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_248_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_249_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_250_T_1 = + s2_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_251_T_1 = + s2_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_252_T_1 = + s2_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_253_T_1 = + s2_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_254_T_1 = + s2_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | (&s2_ghist_ptr_dup_0_value) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_255_T_1 = + (&s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | ~(|s2_ghist_ptr_dup_0_value) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire [8:0] _GEN_28 = {s3_ghist_ptr_dup_0_flag, s3_ghist_ptr_dup_0_value}; // src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1 = + 9'(_GEN_28 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3 = + 9'(_GEN_28 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5 = + 9'(_GEN_28 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _GEN_29 = {s3_ghist_ptr_dup_1_flag, s3_ghist_ptr_dup_1_value}; // src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7 = + 9'(_GEN_29 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9 = + 9'(_GEN_29 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11 = + 9'(_GEN_29 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _GEN_30 = {s3_ghist_ptr_dup_2_flag, s3_ghist_ptr_dup_2_value}; // src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13 = + 9'(_GEN_30 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15 = + 9'(_GEN_30 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17 = + 9'(_GEN_30 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _GEN_31 = {s3_ghist_ptr_dup_3_flag, s3_ghist_ptr_dup_3_value}; // src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19 = + 9'(_GEN_31 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21 = + 9'(_GEN_31 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23 = + 9'(_GEN_31 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire _s3_ghv_wdatas_WIRE_13797_1 = + _predictors_io_out_s3_full_pred_0_slot_valids_1 + & _predictors_io_out_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 + wire _s3_predicted_ghist_ptr_dup_WIRE_56_0_0 = + ~_predictors_io_out_s3_full_pred_0_hit + | ~(_predictors_io_out_s3_full_pred_0_slot_valids_0 | _s3_ghv_wdatas_WIRE_13797_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _selVecOH_T_98 = + _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _predictors_io_out_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _s3_redirect_on_jalr_target_dup_T_9 = + _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire _s3_both_first_taken_dup_T_7 = + _predictors_io_out_s3_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:474:27 + wire _s3_predicted_ghist_ptr_dup_WIRE_56_0_1 = + _predictors_io_out_s3_full_pred_0_slot_valids_0 + & (_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | ~_s3_ghv_wdatas_WIRE_13797_1) & _predictors_io_out_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s3_predicted_ghist_ptr_dup_WIRE_56_0_2 = + _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _predictors_io_out_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s3_predicted_fh_dup_WIRE_21_1 = + _predictors_io_out_s3_full_pred_1_slot_valids_1 + & _predictors_io_out_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 + wire _s3_predicted_ghist_ptr_dup_WIRE_56_1_0 = + ~_predictors_io_out_s3_full_pred_1_hit + | ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 | _s3_predicted_fh_dup_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _selVecOH_T_106 = + _predictors_io_out_s3_full_pred_1_slot_valids_0 + & _predictors_io_out_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _s3_redirect_on_jalr_target_dup_T_29 = + _predictors_io_out_s3_full_pred_1_is_br_sharing + & _predictors_io_out_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire _s3_predicted_ghist_ptr_dup_WIRE_56_1_1 = + _predictors_io_out_s3_full_pred_1_slot_valids_0 + & (_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit + | ~_s3_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s3_predicted_ghist_ptr_dup_WIRE_56_1_2 = + _s3_predicted_fh_dup_WIRE_21_1 + & ~(_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit) + & _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s3_predicted_fh_dup_WIRE_35_1 = + _predictors_io_out_s3_full_pred_2_slot_valids_1 + & _predictors_io_out_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 + wire _s3_predicted_ghist_ptr_dup_WIRE_56_2_0 = + ~_predictors_io_out_s3_full_pred_2_hit + | ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 | _s3_predicted_fh_dup_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _selVecOH_T_114 = + _predictors_io_out_s3_full_pred_2_slot_valids_0 + & _predictors_io_out_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _s3_redirect_on_jalr_target_dup_T_49 = + _predictors_io_out_s3_full_pred_2_is_br_sharing + & _predictors_io_out_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire _s3_predicted_ghist_ptr_dup_WIRE_56_2_1 = + _predictors_io_out_s3_full_pred_2_slot_valids_0 + & (_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit + | ~_s3_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s3_predicted_ghist_ptr_dup_WIRE_56_2_2 = + _s3_predicted_fh_dup_WIRE_35_1 + & ~(_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit) + & _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s3_predicted_fh_dup_WIRE_49_1 = + _predictors_io_out_s3_full_pred_3_slot_valids_1 + & _predictors_io_out_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48 + wire _s3_predicted_ghist_ptr_dup_WIRE_56_3_0 = + ~_predictors_io_out_s3_full_pred_3_hit + | ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 | _s3_predicted_fh_dup_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _selVecOH_T_122 = + _predictors_io_out_s3_full_pred_3_slot_valids_0 + & _predictors_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _s3_redirect_on_jalr_target_dup_T_69 = + _predictors_io_out_s3_full_pred_3_is_br_sharing + & _predictors_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire _s3_predicted_ghist_ptr_dup_WIRE_56_3_1 = + _predictors_io_out_s3_full_pred_3_slot_valids_0 + & (_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit + | ~_s3_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s3_predicted_ghist_ptr_dup_WIRE_56_3_2 = + _s3_predicted_fh_dup_WIRE_49_1 + & ~(_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit) + & _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s3_predicted_fh_dup_WIRE_56_1_0 = + ~_predictors_io_out_s3_full_pred_1_hit + | ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 | _s3_predicted_fh_dup_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _s3_predicted_fh_dup_WIRE_56_1_1 = + _predictors_io_out_s3_full_pred_1_slot_valids_0 + & (_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit + | ~_s3_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s3_predicted_fh_dup_WIRE_56_1_2 = + _s3_predicted_fh_dup_WIRE_21_1 + & ~(_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit) + & _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s3_predicted_fh_dup_WIRE_56_2_0 = + ~_predictors_io_out_s3_full_pred_2_hit + | ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 | _s3_predicted_fh_dup_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _s3_predicted_fh_dup_WIRE_56_2_1 = + _predictors_io_out_s3_full_pred_2_slot_valids_0 + & (_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit + | ~_s3_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s3_predicted_fh_dup_WIRE_56_2_2 = + _s3_predicted_fh_dup_WIRE_35_1 + & ~(_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit) + & _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire _s3_predicted_fh_dup_WIRE_56_3_0 = + ~_predictors_io_out_s3_full_pred_3_hit + | ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 | _s3_predicted_fh_dup_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + wire _s3_predicted_fh_dup_WIRE_56_3_1 = + _predictors_io_out_s3_full_pred_3_slot_valids_0 + & (_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit + | ~_s3_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97} + wire _s3_predicted_fh_dup_WIRE_56_3_2 = + _s3_predicted_fh_dup_WIRE_49_1 + & ~(_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit) + & _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97 + wire s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0 = + _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2 = + _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3 = + _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0 = + _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0 = + _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2 = + _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3 = + _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0 = + _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0 = + _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2 = + _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3 = + _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0 = + _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + reg [38:0] previous_s2_pred_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg [38:0] previous_s2_pred_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + reg previous_s2_pred_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:673:35 + wire _s3_redirect_on_target_dup_selVecOH_T_34 = + previous_s2_pred_full_pred_0_slot_valids_0 + & previous_s2_pred_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _s3_redirect_on_target_dup_selVecOH_T_42 = + previous_s2_pred_full_pred_1_slot_valids_0 + & previous_s2_pred_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _s3_redirect_on_target_dup_selVecOH_T_50 = + previous_s2_pred_full_pred_2_slot_valids_0 + & previous_s2_pred_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _s3_redirect_on_target_dup_selVecOH_T_58 = + previous_s2_pred_full_pred_3_slot_valids_0 + & previous_s2_pred_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _s3_redirect_on_target_dup_WIRE_1 = + _predictors_io_out_s3_full_pred_0_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_9 + | ~_predictors_io_out_s3_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire [38:0] _s3_redirect_on_target_dup_WIRE_1_3 = + 39'(_predictors_io_out_s3_pc_0 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + wire _s3_redirect_on_target_dup_WIRE_3_1 = + _predictors_io_out_s3_full_pred_1_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_29 + | ~_predictors_io_out_s3_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire [38:0] _s3_redirect_on_target_dup_WIRE_4_3 = + 39'(_predictors_io_out_s3_pc_1 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + wire _s3_redirect_on_target_dup_WIRE_6_1 = + _predictors_io_out_s3_full_pred_2_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_49 + | ~_predictors_io_out_s3_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire [38:0] _s3_redirect_on_target_dup_WIRE_7_3 = + 39'(_predictors_io_out_s3_pc_2 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + wire _s3_redirect_on_target_dup_WIRE_9_1 = + _predictors_io_out_s3_full_pred_3_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_69 + | ~_predictors_io_out_s3_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire [38:0] _s3_redirect_on_target_dup_WIRE_10_3 = + 39'(_predictors_io_out_s3_pc_3 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47 + wire _s3_redirect_on_target_dup_WIRE_13_1 = + previous_s2_pred_full_pred_0_slot_valids_1 + & (previous_s2_pred_full_pred_0_is_br_sharing + & previous_s2_pred_full_pred_0_br_taken_mask_1 + | ~previous_s2_pred_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire _s3_redirect_on_target_dup_WIRE_16_1 = + previous_s2_pred_full_pred_1_slot_valids_1 + & (previous_s2_pred_full_pred_1_is_br_sharing + & previous_s2_pred_full_pred_1_br_taken_mask_1 + | ~previous_s2_pred_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire _s3_redirect_on_target_dup_WIRE_19_1 = + previous_s2_pred_full_pred_2_slot_valids_1 + & (previous_s2_pred_full_pred_2_is_br_sharing + & previous_s2_pred_full_pred_2_br_taken_mask_1 + | ~previous_s2_pred_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire _s3_redirect_on_target_dup_WIRE_22_1 = + previous_s2_pred_full_pred_3_slot_valids_1 + & (previous_s2_pred_full_pred_3_is_br_sharing + & previous_s2_pred_full_pred_3_br_taken_mask_1 + | ~previous_s2_pred_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + assign s3_redirect_dup_0 = + s3_valid_dup_3 + & ({_s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit, + _selVecOH_T_98 + & _predictors_io_out_s3_full_pred_0_hit} != {previous_s2_pred_full_pred_0_br_taken_mask_1 + & previous_s2_pred_full_pred_0_slot_valids_1 + & previous_s2_pred_full_pred_0_is_br_sharing + & previous_s2_pred_full_pred_0_hit, + _s3_redirect_on_target_dup_selVecOH_T_34 + & previous_s2_pred_full_pred_0_hit} + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + & _s3_redirect_on_target_dup_selVecOH_T_34 & previous_s2_pred_full_pred_0_hit) + | ((_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + ? _predictors_io_out_s3_full_pred_0_targets_0 + : 39'h0) + | (~_selVecOH_T_98 & _s3_redirect_on_target_dup_WIRE_1 + & _predictors_io_out_s3_full_pred_0_hit + ? _predictors_io_out_s3_full_pred_0_targets_1 + : 39'h0) + | ({_s3_redirect_on_target_dup_WIRE_1, _selVecOH_T_98} == 2'h0 + & _predictors_io_out_s3_full_pred_0_hit + ? _predictors_io_out_s3_full_pred_0_fallThroughAddr + : 39'h0) + | (_predictors_io_out_s3_full_pred_0_hit + ? 39'h0 + : _s3_redirect_on_target_dup_WIRE_1_3)) != ((_s3_redirect_on_target_dup_selVecOH_T_34 + & previous_s2_pred_full_pred_0_hit + ? previous_s2_pred_full_pred_0_targets_0 + : 39'h0) + | (~_s3_redirect_on_target_dup_selVecOH_T_34 + & _s3_redirect_on_target_dup_WIRE_13_1 + & previous_s2_pred_full_pred_0_hit + ? previous_s2_pred_full_pred_0_targets_1 + : 39'h0) + | ({_s3_redirect_on_target_dup_WIRE_13_1, + _s3_redirect_on_target_dup_selVecOH_T_34} == 2'h0 + & previous_s2_pred_full_pred_0_hit + ? previous_s2_pred_full_pred_0_fallThroughAddr + : 39'h0) + | (previous_s2_pred_full_pred_0_hit + ? 39'h0 + : 39'(previous_s2_pred_pc_0 + + 39'h20))) + | _predictors_io_out_s3_full_pred_0_hit + & _predictors_io_out_s3_full_pred_0_fallThroughErr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :673:35, :675:{136,143,172}, :676:135, :677:110, :684:28, :685:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :473:32, :474:{27,63}, :505:47, :508:33 + wire s3_redirect_dup_1 = + s3_valid_dup_3 + & ({_predictors_io_out_s3_full_pred_1_br_taken_mask_1 + & _predictors_io_out_s3_full_pred_1_slot_valids_1 + & _predictors_io_out_s3_full_pred_1_is_br_sharing + & _predictors_io_out_s3_full_pred_1_hit, + _selVecOH_T_106 + & _predictors_io_out_s3_full_pred_1_hit} != {previous_s2_pred_full_pred_1_br_taken_mask_1 + & previous_s2_pred_full_pred_1_slot_valids_1 + & previous_s2_pred_full_pred_1_is_br_sharing + & previous_s2_pred_full_pred_1_hit, + _s3_redirect_on_target_dup_selVecOH_T_42 + & previous_s2_pred_full_pred_1_hit} + & ~(_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit + & _s3_redirect_on_target_dup_selVecOH_T_42 & previous_s2_pred_full_pred_1_hit) + | ((_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit + ? _predictors_io_out_s3_full_pred_1_targets_0 + : 39'h0) + | (~_selVecOH_T_106 & _s3_redirect_on_target_dup_WIRE_3_1 + & _predictors_io_out_s3_full_pred_1_hit + ? _predictors_io_out_s3_full_pred_1_targets_1 + : 39'h0) + | ({_s3_redirect_on_target_dup_WIRE_3_1, _selVecOH_T_106} == 2'h0 + & _predictors_io_out_s3_full_pred_1_hit + ? _predictors_io_out_s3_full_pred_1_fallThroughAddr + : 39'h0) + | (_predictors_io_out_s3_full_pred_1_hit + ? 39'h0 + : _s3_redirect_on_target_dup_WIRE_4_3)) != ((_s3_redirect_on_target_dup_selVecOH_T_42 + & previous_s2_pred_full_pred_1_hit + ? previous_s2_pred_full_pred_1_targets_0 + : 39'h0) + | (~_s3_redirect_on_target_dup_selVecOH_T_42 + & _s3_redirect_on_target_dup_WIRE_16_1 + & previous_s2_pred_full_pred_1_hit + ? previous_s2_pred_full_pred_1_targets_1 + : 39'h0) + | ({_s3_redirect_on_target_dup_WIRE_16_1, + _s3_redirect_on_target_dup_selVecOH_T_42} == 2'h0 + & previous_s2_pred_full_pred_1_hit + ? previous_s2_pred_full_pred_1_fallThroughAddr + : 39'h0) + | (previous_s2_pred_full_pred_1_hit + ? 39'h0 + : 39'(previous_s2_pred_pc_1 + + 39'h20))) + | _predictors_io_out_s3_full_pred_1_hit + & _predictors_io_out_s3_full_pred_1_fallThroughErr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :673:35, :675:{136,143,172}, :676:135, :677:110, :684:28, :685:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :473:32, :474:63, :505:47, :508:33 + assign s3_redirect_dup_2 = + s3_valid_dup_3 + & ({_predictors_io_out_s3_full_pred_2_br_taken_mask_1 + & _predictors_io_out_s3_full_pred_2_slot_valids_1 + & _predictors_io_out_s3_full_pred_2_is_br_sharing + & _predictors_io_out_s3_full_pred_2_hit, + _selVecOH_T_114 + & _predictors_io_out_s3_full_pred_2_hit} != {previous_s2_pred_full_pred_2_br_taken_mask_1 + & previous_s2_pred_full_pred_2_slot_valids_1 + & previous_s2_pred_full_pred_2_is_br_sharing + & previous_s2_pred_full_pred_2_hit, + _s3_redirect_on_target_dup_selVecOH_T_50 + & previous_s2_pred_full_pred_2_hit} + & ~(_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit + & _s3_redirect_on_target_dup_selVecOH_T_50 & previous_s2_pred_full_pred_2_hit) + | ((_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit + ? _predictors_io_out_s3_full_pred_2_targets_0 + : 39'h0) + | (~_selVecOH_T_114 & _s3_redirect_on_target_dup_WIRE_6_1 + & _predictors_io_out_s3_full_pred_2_hit + ? _predictors_io_out_s3_full_pred_2_targets_1 + : 39'h0) + | ({_s3_redirect_on_target_dup_WIRE_6_1, _selVecOH_T_114} == 2'h0 + & _predictors_io_out_s3_full_pred_2_hit + ? _predictors_io_out_s3_full_pred_2_fallThroughAddr + : 39'h0) + | (_predictors_io_out_s3_full_pred_2_hit + ? 39'h0 + : _s3_redirect_on_target_dup_WIRE_7_3)) != ((_s3_redirect_on_target_dup_selVecOH_T_50 + & previous_s2_pred_full_pred_2_hit + ? previous_s2_pred_full_pred_2_targets_0 + : 39'h0) + | (~_s3_redirect_on_target_dup_selVecOH_T_50 + & _s3_redirect_on_target_dup_WIRE_19_1 + & previous_s2_pred_full_pred_2_hit + ? previous_s2_pred_full_pred_2_targets_1 + : 39'h0) + | ({_s3_redirect_on_target_dup_WIRE_19_1, + _s3_redirect_on_target_dup_selVecOH_T_50} == 2'h0 + & previous_s2_pred_full_pred_2_hit + ? previous_s2_pred_full_pred_2_fallThroughAddr + : 39'h0) + | (previous_s2_pred_full_pred_2_hit + ? 39'h0 + : 39'(previous_s2_pred_pc_2 + + 39'h20))) + | _predictors_io_out_s3_full_pred_2_hit + & _predictors_io_out_s3_full_pred_2_fallThroughErr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :673:35, :675:{136,143,172}, :676:135, :677:110, :684:28, :685:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :473:32, :474:63, :505:47, :508:33 + assign s3_redirect_dup_3 = + s3_valid_dup_3 + & ({_predictors_io_out_s3_full_pred_3_br_taken_mask_1 + & _predictors_io_out_s3_full_pred_3_slot_valids_1 + & _predictors_io_out_s3_full_pred_3_is_br_sharing + & _predictors_io_out_s3_full_pred_3_hit, + _selVecOH_T_122 + & _predictors_io_out_s3_full_pred_3_hit} != {previous_s2_pred_full_pred_3_br_taken_mask_1 + & previous_s2_pred_full_pred_3_slot_valids_1 + & previous_s2_pred_full_pred_3_is_br_sharing + & previous_s2_pred_full_pred_3_hit, + _s3_redirect_on_target_dup_selVecOH_T_58 + & previous_s2_pred_full_pred_3_hit} + & ~(_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit + & _s3_redirect_on_target_dup_selVecOH_T_58 & previous_s2_pred_full_pred_3_hit) + | ((_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit + ? _predictors_io_out_s3_full_pred_3_targets_0 + : 39'h0) + | (~_selVecOH_T_122 & _s3_redirect_on_target_dup_WIRE_9_1 + & _predictors_io_out_s3_full_pred_3_hit + ? _predictors_io_out_s3_full_pred_3_targets_1 + : 39'h0) + | ({_s3_redirect_on_target_dup_WIRE_9_1, _selVecOH_T_122} == 2'h0 + & _predictors_io_out_s3_full_pred_3_hit + ? _predictors_io_out_s3_full_pred_3_fallThroughAddr + : 39'h0) + | (_predictors_io_out_s3_full_pred_3_hit + ? 39'h0 + : _s3_redirect_on_target_dup_WIRE_10_3)) != ((_s3_redirect_on_target_dup_selVecOH_T_58 + & previous_s2_pred_full_pred_3_hit + ? previous_s2_pred_full_pred_3_targets_0 + : 39'h0) + | (~_s3_redirect_on_target_dup_selVecOH_T_58 + & _s3_redirect_on_target_dup_WIRE_22_1 + & previous_s2_pred_full_pred_3_hit + ? previous_s2_pred_full_pred_3_targets_1 + : 39'h0) + | ({_s3_redirect_on_target_dup_WIRE_22_1, + _s3_redirect_on_target_dup_selVecOH_T_58} == 2'h0 + & previous_s2_pred_full_pred_3_hit + ? previous_s2_pred_full_pred_3_fallThroughAddr + : 39'h0) + | (previous_s2_pred_full_pred_3_hit + ? 39'h0 + : 39'(previous_s2_pred_pc_3 + + 39'h20))) + | _predictors_io_out_s3_full_pred_3_hit + & _predictors_io_out_s3_full_pred_3_fallThroughErr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :673:35, :675:{136,143,172}, :676:135, :677:110, :684:28, :685:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :473:32, :474:63, :505:47, :508:33 + wire _GEN_32 = + _predictors_io_out_s3_full_pred_0_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_9 + | ~_predictors_io_out_s3_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire _GEN_33 = + _predictors_io_out_s3_full_pred_1_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_29 + | ~_predictors_io_out_s3_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire _GEN_34 = + _predictors_io_out_s3_full_pred_2_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_49 + | ~_predictors_io_out_s3_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire _GEN_35 = + _predictors_io_out_s3_full_pred_3_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_69 + | ~_predictors_io_out_s3_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50} + wire _GEN_36 = _selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 + wire _GEN_37 = _selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 + wire _GEN_38 = _selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 + wire _ghv_wens_0_T_2 = + ~(|s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_1_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_2_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_3_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_4_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_5_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_6_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_7_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_8_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_9_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_10_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_11_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_12_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_13_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_14_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_15_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h10 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_16_T_2 = + s3_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h11 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_17_T_2 = + s3_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h12 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_18_T_2 = + s3_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h13 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_19_T_2 = + s3_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h14 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_20_T_2 = + s3_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h15 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_21_T_2 = + s3_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h16 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_22_T_2 = + s3_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h17 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_23_T_2 = + s3_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h18 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_24_T_2 = + s3_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h19 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_25_T_2 = + s3_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_26_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_27_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_28_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_29_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_30_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_31_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h20 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_32_T_2 = + s3_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h21 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_33_T_2 = + s3_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h22 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_34_T_2 = + s3_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h23 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_35_T_2 = + s3_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h24 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_36_T_2 = + s3_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h25 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_37_T_2 = + s3_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h26 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_38_T_2 = + s3_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h27 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_39_T_2 = + s3_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h28 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_40_T_2 = + s3_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h29 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_41_T_2 = + s3_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_42_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_43_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_44_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_45_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_46_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_47_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h30 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_48_T_2 = + s3_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h31 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_49_T_2 = + s3_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h32 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_50_T_2 = + s3_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h33 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_51_T_2 = + s3_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h34 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_52_T_2 = + s3_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h35 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_53_T_2 = + s3_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h36 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_54_T_2 = + s3_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h37 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_55_T_2 = + s3_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h38 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_56_T_2 = + s3_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h39 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_57_T_2 = + s3_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_58_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_59_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_60_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_61_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_62_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_63_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h40 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_64_T_2 = + s3_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h41 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_65_T_2 = + s3_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h42 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_66_T_2 = + s3_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h43 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_67_T_2 = + s3_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h44 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_68_T_2 = + s3_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h45 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_69_T_2 = + s3_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h46 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_70_T_2 = + s3_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h47 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_71_T_2 = + s3_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h48 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_72_T_2 = + s3_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h49 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_73_T_2 = + s3_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_74_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_75_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_76_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_77_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_78_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_79_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h50 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_80_T_2 = + s3_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h51 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_81_T_2 = + s3_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h52 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_82_T_2 = + s3_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h53 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_83_T_2 = + s3_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h54 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_84_T_2 = + s3_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h55 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_85_T_2 = + s3_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h56 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_86_T_2 = + s3_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h57 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_87_T_2 = + s3_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h58 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_88_T_2 = + s3_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h59 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_89_T_2 = + s3_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_90_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_91_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_92_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_93_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_94_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_95_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h60 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_96_T_2 = + s3_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h61 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_97_T_2 = + s3_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h62 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_98_T_2 = + s3_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h63 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_99_T_2 = + s3_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h64 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_100_T_2 = + s3_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h65 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_101_T_2 = + s3_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h66 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_102_T_2 = + s3_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h67 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_103_T_2 = + s3_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h68 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_104_T_2 = + s3_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h69 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_105_T_2 = + s3_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_106_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_107_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_108_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_109_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_110_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_111_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h70 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_112_T_2 = + s3_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h71 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_113_T_2 = + s3_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h72 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_114_T_2 = + s3_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h73 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_115_T_2 = + s3_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h74 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_116_T_2 = + s3_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h75 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_117_T_2 = + s3_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h76 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_118_T_2 = + s3_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h77 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_119_T_2 = + s3_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h78 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_120_T_2 = + s3_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h79 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_121_T_2 = + s3_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_122_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_123_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_124_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_125_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_126_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_127_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h80 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_128_T_2 = + s3_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h81 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_129_T_2 = + s3_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h82 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_130_T_2 = + s3_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h83 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_131_T_2 = + s3_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h84 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_132_T_2 = + s3_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h85 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_133_T_2 = + s3_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h86 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_134_T_2 = + s3_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h87 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_135_T_2 = + s3_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h88 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_136_T_2 = + s3_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h89 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_137_T_2 = + s3_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_138_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_139_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_140_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_141_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_142_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_143_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h90 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_144_T_2 = + s3_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h91 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_145_T_2 = + s3_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h92 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_146_T_2 = + s3_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h93 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_147_T_2 = + s3_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h94 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_148_T_2 = + s3_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h95 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_149_T_2 = + s3_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h96 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_150_T_2 = + s3_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h97 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_151_T_2 = + s3_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h98 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_152_T_2 = + s3_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h99 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_153_T_2 = + s3_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_154_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_155_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_156_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_157_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_158_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_159_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA0 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_160_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_161_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_162_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_163_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_164_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_165_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_166_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_167_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_168_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_169_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_170_T_2 = + s3_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_171_T_2 = + s3_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_172_T_2 = + s3_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAD & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_173_T_2 = + s3_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_174_T_2 = + s3_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAF & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_175_T_2 = + s3_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB0 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_176_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_177_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_178_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_179_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_180_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_181_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_182_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_183_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_184_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_185_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_186_T_2 = + s3_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_187_T_2 = + s3_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_188_T_2 = + s3_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBD & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_189_T_2 = + s3_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_190_T_2 = + s3_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBF & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_191_T_2 = + s3_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC0 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_192_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_193_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_194_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_195_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_196_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_197_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_198_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_199_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_200_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_201_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_202_T_2 = + s3_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_203_T_2 = + s3_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_204_T_2 = + s3_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCD & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_205_T_2 = + s3_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_206_T_2 = + s3_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCF & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_207_T_2 = + s3_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD0 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_208_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_209_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_210_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_211_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_212_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_213_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_214_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_215_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_216_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_217_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_218_T_2 = + s3_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_219_T_2 = + s3_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_220_T_2 = + s3_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDD & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_221_T_2 = + s3_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_222_T_2 = + s3_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDF & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_223_T_2 = + s3_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE0 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_224_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_225_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_226_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_227_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_228_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_229_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_230_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_231_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_232_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_233_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_234_T_2 = + s3_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_235_T_2 = + s3_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_236_T_2 = + s3_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hED & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_237_T_2 = + s3_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_238_T_2 = + s3_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEF & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_239_T_2 = + s3_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF0 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_240_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_241_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_242_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_243_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_244_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_245_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_246_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_247_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_248_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_249_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_250_T_2 = + s3_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_251_T_2 = + s3_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_252_T_2 = + s3_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFD & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_253_T_2 = + s3_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_254_T_2 = + s3_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | (&s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12 + wire _ghv_wens_255_T_2 = + (&s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | ~(|s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12 + reg s2_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:708:29 + reg [5:0] s2_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:708:29 + reg s3_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:709:29 + reg [5:0] s3_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:709:29 + reg predictors_io_update_REG_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [38:0] predictors_io_update_REG_bits_pc; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [10:0] + predictors_io_update_REG_bits_spec_info_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [10:0] + predictors_io_update_REG_bits_spec_info_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [6:0] + predictors_io_update_REG_bits_spec_info_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [7:0] + predictors_io_update_REG_bits_spec_info_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [8:0] + predictors_io_update_REG_bits_spec_info_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [3:0] + predictors_io_update_REG_bits_spec_info_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [7:0] + predictors_io_update_REG_bits_spec_info_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [8:0] + predictors_io_update_REG_bits_spec_info_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [6:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [7:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [6:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [8:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [6:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [7:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [7:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [7:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [10:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_ftb_entry_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [3:0] predictors_io_update_REG_bits_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [11:0] predictors_io_update_REG_bits_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [1:0] predictors_io_update_REG_bits_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [3:0] predictors_io_update_REG_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [19:0] predictors_io_update_REG_bits_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [1:0] predictors_io_update_REG_bits_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [3:0] predictors_io_update_REG_bits_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_ftb_entry_carry; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_ftb_entry_isCall; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_ftb_entry_isRet; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_ftb_entry_isJalr; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_cfi_idx_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [3:0] predictors_io_update_REG_bits_cfi_idx_bits; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_jmp_taken; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_mispred_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_mispred_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_mispred_mask_2; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg predictors_io_update_REG_bits_old_entry; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [218:0] predictors_io_update_REG_bits_meta; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + reg [38:0] predictors_io_update_REG_bits_full_target; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + wire [1:0] _shouldShiftVec_dup_T_46 = 2'(thisBrNumOH_dup_shiftAmount - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:156 + wire [3:0] _shouldShiftVec_dup_T_4 = 4'h1 << _shouldShiftVec_dup_T_46; // src/main/scala/xiangshan/frontend/BPU.scala:737:{147,156} + wire [1:0] _GEN_39 = _shouldShiftVec_dup_T_4[1:0] | _shouldShiftVec_dup_T_4[2:1]; // src/main/scala/xiangshan/frontend/BPU.scala:737:147, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + wire shouldShiftVec_dup_0_0 = + (|thisBrNumOH_dup_shiftAmount) + & (_GEN_39[0] | _shouldShiftVec_dup_T_46 == 2'h2 | (&_shouldShiftVec_dup_T_46)); // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :440:30, :737:{54,61,156}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53 + wire shouldShiftVec_dup_0_1 = + (|thisBrNumOH_dup_shiftAmount) & (_GEN_39[1] | (&_shouldShiftVec_dup_T_46)); // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:{54,61,156}, utility/src/main/scala/utility/ParallelMux.scala:36:53 + wire real_br_taken_mask_dup_0_0 = + thisBrNumOH_dup_shiftAmount == 2'h1 & do_redirect_dup_3_bits_cfiUpdate_taken + & do_redirect_dup_3_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :747:{44,65} + wire real_br_taken_mask_dup_0_1 = + thisBrNumOH_dup_shiftAmount == 2'h2 & do_redirect_dup_3_bits_cfiUpdate_taken + & do_redirect_dup_3_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :440:30, :747:{44,65} + wire [8:0] _updated_ptr_dup_flipped_new_ptr_T_6 = + 9'(9'h100 - {7'h0, thisBrNumOH_dup_shiftAmount}); // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50 + wire [8:0] _GEN_40 = + {do_redirect_dup_3_bits_cfiUpdate_histPtr_flag, + do_redirect_dup_3_bits_cfiUpdate_histPtr_value}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_1 = + 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50 + wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_3 = + 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50 + wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_5 = + 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50 + wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_7 = + 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50 + wire + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 = + do_redirect_dup_3_bits_cfiUpdate_taken & do_redirect_dup_3_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83 + wire _GEN_41 = + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[0] + | _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + wire [7:0] _updated_fh_dup_WIRE_1_0_hist_0_folded_hist = + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + wire _GEN_42 = + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[0] + | _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + wire [3:0] _updated_fh_dup_WIRE_1_0_hist_12_folded_hist = + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + wire _GEN_43 = + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[0] + | _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + wire [7:0] _updated_fh_dup_WIRE_1_0_hist_14_folded_hist = + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + wire [7:0] _updated_fh_dup_WIRE_2_0_hist_0_folded_hist = + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + wire [3:0] _updated_fh_dup_WIRE_2_0_hist_12_folded_hist = + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + wire [7:0] _updated_fh_dup_WIRE_2_0_hist_14_folded_hist = + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + wire [7:0] _updated_fh_dup_WIRE_3_0_hist_0_folded_hist = + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + wire [3:0] _updated_fh_dup_WIRE_3_0_hist_12_folded_hist = + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + wire [7:0] _updated_fh_dup_WIRE_3_0_hist_14_folded_hist = + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29 + wire [3:0] _GEN_44 = {2'h0, thisBrNumOH_dup_shiftAmount}; // src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + wire [3:0] _thisBrNumOH_dup_T_1 = 4'h1 << _GEN_44; // src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:737:147 + wire [3:0] _thisBrNumOH_dup_T_2 = 4'h1 << _GEN_44; // src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:737:147 + wire [3:0] _thisBrNumOH_dup_T_3 = 4'h1 << _GEN_44; // src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:737:147 + wire thisAheadFhOb_dup_1_afhob_0_bits_0 = + _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire thisAheadFhOb_dup_1_afhob_0_bits_2 = + _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire thisAheadFhOb_dup_1_afhob_0_bits_3 = + _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire thisAheadFhOb_dup_1_afhob_1_bits_0 = + _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire thisAheadFhOb_dup_2_afhob_0_bits_0 = + _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire thisAheadFhOb_dup_2_afhob_0_bits_2 = + _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire thisAheadFhOb_dup_2_afhob_0_bits_3 = + _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire thisAheadFhOb_dup_2_afhob_1_bits_0 = + _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire thisAheadFhOb_dup_3_afhob_0_bits_0 = + _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire thisAheadFhOb_dup_3_afhob_0_bits_2 = + _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire thisAheadFhOb_dup_3_afhob_0_bits_3 = + _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire thisAheadFhOb_dup_3_afhob_1_bits_0 = + _GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire _ghv_wens_0_T_3 = + ~(|do_redirect_dup_3_bits_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_1_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_2_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_3_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_4_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_5_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_6_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_7_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_8_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_9_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_10_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_11_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_12_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_13_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_14_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_15_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h10 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_16_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h10 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h11 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_17_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h11 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h12 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_18_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h12 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h13 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_19_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h13 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h14 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_20_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h14 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h15 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_21_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h15 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h16 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_22_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h16 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h17 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_23_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h17 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h18 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_24_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h18 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h19 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_25_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h19 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1A + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_26_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1A & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1B + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_27_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1B & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1C + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_28_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1C & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1D + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_29_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1D & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1E + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_30_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1E & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1F + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_31_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1F & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h20 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_32_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h20 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h21 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_33_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h21 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h22 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_34_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h22 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h23 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_35_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h23 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h24 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_36_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h24 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h25 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_37_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h25 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h26 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_38_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h26 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h27 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_39_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h27 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h28 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_40_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h28 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h29 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_41_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h29 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2A + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_42_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2A & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2B + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_43_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2B & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2C + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_44_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2C & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2D + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_45_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2D & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2E + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_46_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2E & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2F + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_47_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2F & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h30 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_48_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h30 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h31 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_49_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h31 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h32 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_50_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h32 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h33 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_51_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h33 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h34 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_52_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h34 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h35 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_53_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h35 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h36 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_54_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h36 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h37 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_55_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h37 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h38 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_56_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h38 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h39 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_57_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h39 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3A + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_58_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3A & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3B + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_59_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3B & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3C + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_60_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3C & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3D + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_61_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3D & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3E + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_62_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3E & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3F + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_63_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3F & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h40 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_64_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h40 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h41 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_65_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h41 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h42 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_66_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h42 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h43 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_67_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h43 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h44 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_68_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h44 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h45 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_69_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h45 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h46 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_70_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h46 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h47 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_71_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h47 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h48 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_72_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h48 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h49 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_73_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h49 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4A + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_74_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4A & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4B + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_75_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4B & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4C + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_76_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4C & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4D + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_77_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4D & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4E + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_78_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4E & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4F + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_79_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4F & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h50 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_80_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h50 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h51 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_81_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h51 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h52 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_82_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h52 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h53 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_83_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h53 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h54 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_84_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h54 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h55 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_85_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h55 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h56 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_86_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h56 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h57 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_87_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h57 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h58 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_88_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h58 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h59 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_89_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h59 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5A + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_90_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5A & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5B + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_91_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5B & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5C + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_92_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5C & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5D + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_93_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5D & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5E + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_94_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5E & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5F + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_95_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5F & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h60 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_96_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h60 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h61 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_97_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h61 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h62 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_98_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h62 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h63 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_99_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h63 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h64 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_100_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h64 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h65 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_101_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h65 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h66 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_102_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h66 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h67 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_103_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h67 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h68 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_104_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h68 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h69 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_105_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h69 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6A + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_106_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6A & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6B + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_107_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6B & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6C + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_108_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6C & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6D + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_109_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6D & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6E + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_110_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6E & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6F + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_111_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6F & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h70 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_112_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h70 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h71 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_113_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h71 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h72 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_114_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h72 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h73 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_115_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h73 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h74 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_116_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h74 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h75 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_117_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h75 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h76 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_118_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h76 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h77 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_119_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h77 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h78 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_120_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h78 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h79 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_121_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h79 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7A + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_122_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7A & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7B + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_123_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7B & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7C + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_124_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7C & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7D + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_125_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7D & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7E + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_126_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7E & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7F + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_127_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7F & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h80 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_128_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h80 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h81 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_129_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h81 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h82 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_130_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h82 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h83 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_131_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h83 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h84 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_132_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h84 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h85 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_133_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h85 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h86 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_134_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h86 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h87 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_135_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h87 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h88 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_136_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h88 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h89 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_137_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h89 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8A + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_138_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8A & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8B + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_139_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8B & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8C + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_140_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8C & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8D + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_141_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8D & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8E + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_142_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8E & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8F + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_143_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8F & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h90 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_144_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h90 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h91 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_145_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h91 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h92 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_146_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h92 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h93 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_147_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h93 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h94 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_148_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h94 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h95 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_149_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h95 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h96 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_150_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h96 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h97 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_151_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h97 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h98 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_152_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h98 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h99 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_153_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h99 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9A + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_154_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9A & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9B + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_155_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9B & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9C + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_156_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9C & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9D + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_157_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9D & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9E + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_158_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9E & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9F + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_159_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9F & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_160_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_161_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_162_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_163_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_164_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_165_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_166_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_167_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_168_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_169_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAA + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_170_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAA & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAB + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_171_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAB & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAC + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_172_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAC & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAD + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_173_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAD & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAE + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_174_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAE & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAF + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_175_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAF & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_176_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_177_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_178_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_179_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_180_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26 + wire _ghv_wens_181_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_182_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_183_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_184_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_185_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBA + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_186_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBA & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBB + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_187_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBB & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBC + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_188_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBC & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBD + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_189_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBD & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBE + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_190_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBE & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBF + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_191_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBF & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_192_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_193_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_194_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_195_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_196_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_197_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_198_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_199_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_200_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_201_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCA + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_202_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCA & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCB + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_203_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCB & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCC + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_204_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCC & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCD + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_205_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCD & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCE + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_206_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCE & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCF + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_207_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCF & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_208_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_209_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_210_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_211_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_212_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_213_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_214_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_215_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_216_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_217_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDA + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_218_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDA & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDB + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_219_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDB & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDC + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_220_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDC & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDD + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_221_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDD & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDE + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_222_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDE & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDF + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_223_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDF & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_224_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_225_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_226_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_227_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_228_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_229_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_230_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_231_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_232_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_233_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEA + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_234_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEA & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEB + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_235_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEB & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEC + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_236_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEC & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hED + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_237_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hED & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEE + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_238_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEE & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEF + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_239_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEF & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_240_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_241_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_242_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_243_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_244_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_245_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_246_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_247_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_248_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_249_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFA + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_250_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFA & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFB + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_251_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFB & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFC + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_252_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFC & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFD + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_253_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFD & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFE + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_254_T_3 = + do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFE & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | (&do_redirect_dup_3_bits_cfiUpdate_histPtr_value) + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + wire _ghv_wens_255_T_3 = + (&do_redirect_dup_3_bits_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 + & do_redirect_dup_3_valid | ~(|do_redirect_dup_3_bits_cfiUpdate_histPtr_value) + & shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26 + wire [3:0][10:0] _GEN_45 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[7:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9]}}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][10:0] _GEN_46 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[6:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][6:0] _GEN_47 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[3:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5]}}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_48 = + {{_updated_fh_dup_WIRE_1_0_hist_14_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[5:0], + 1'h0, + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[6:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {_updated_fh_dup_WIRE_1_0_hist_14_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][8:0] _GEN_49 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[6:4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[1:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7:4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][3:0] _GEN_50 = + {{_updated_fh_dup_WIRE_1_0_hist_12_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[1:0], + 1'h0, + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[2:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {_updated_fh_dup_WIRE_1_0_hist_12_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_51 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[5:2], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6:2], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][8:0] _GEN_52 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[6:5], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[2:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7:5], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][6:0] _GEN_53 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[1:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5:4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_54 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[4:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6]}}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][6:0] _GEN_55 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[4:1], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0], + 1'h0, + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5:1], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[6]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][8:0] _GEN_56 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[4:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][6:0] _GEN_57 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[4:0], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_58 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[5], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[2:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6:5], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_59 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[5:0], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_60 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[5:0], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][10:0] _GEN_61 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[8:2], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9:2], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_62 = + {{_updated_fh_dup_WIRE_1_0_hist_0_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[5:0], + 1'h0, + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[6:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {_updated_fh_dup_WIRE_1_0_hist_0_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][10:0] _GEN_63 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[7:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9]}}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][10:0] _GEN_64 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[6:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][6:0] _GEN_65 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[3:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5]}}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_66 = + {{_updated_fh_dup_WIRE_2_0_hist_14_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[5:0], + 1'h0, + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[6:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {_updated_fh_dup_WIRE_2_0_hist_14_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][8:0] _GEN_67 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[6:4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[1:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7:4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][3:0] _GEN_68 = + {{_updated_fh_dup_WIRE_2_0_hist_12_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[1:0], + 1'h0, + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[2:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {_updated_fh_dup_WIRE_2_0_hist_12_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_69 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[5:2], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6:2], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][8:0] _GEN_70 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[6:5], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[2:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7:5], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][6:0] _GEN_71 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[1:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5:4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_72 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[4:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6]}}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][6:0] _GEN_73 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[4:1], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0], + 1'h0, + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5:1], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[6]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][8:0] _GEN_74 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[4:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][6:0] _GEN_75 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[4:0], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_76 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[5], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[2:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6:5], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_77 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[5:0], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_78 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[5:0], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][10:0] _GEN_79 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[8:2], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9:2], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_80 = + {{_updated_fh_dup_WIRE_2_0_hist_0_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[5:0], + 1'h0, + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[6:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {_updated_fh_dup_WIRE_2_0_hist_0_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][10:0] _GEN_81 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[7:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9]}}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][10:0] _GEN_82 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[6:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][6:0] _GEN_83 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[3:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5]}}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_84 = + {{_updated_fh_dup_WIRE_3_0_hist_14_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[5:0], + 1'h0, + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[6:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {_updated_fh_dup_WIRE_3_0_hist_14_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][8:0] _GEN_85 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[6:4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[1:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7:4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][3:0] _GEN_86 = + {{_updated_fh_dup_WIRE_3_0_hist_12_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[1:0], + 1'h0, + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[2:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {_updated_fh_dup_WIRE_3_0_hist_12_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_87 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[5:2], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6:2], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][8:0] _GEN_88 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[6:5], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[2:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7:5], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][6:0] _GEN_89 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[1:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5:4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_90 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[4:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6]}}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][6:0] _GEN_91 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[4:1], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0], + 1'h0, + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5:1], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[6]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][8:0] _GEN_92 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}, + {{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[4:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][6:0] _GEN_93 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[4:0], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_94 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[5], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[2:0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6:5], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_95 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[5:0], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_96 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[5:0], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][10:0] _GEN_97 = + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[8:2], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9]}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9:2], + (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1], + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10]}}, + {do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire [3:0][7:0] _GEN_98 = + {{_updated_fh_dup_WIRE_3_0_hist_0_folded_hist}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[5:0], + 1'h0, + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[6:0], + _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}}, + {_updated_fh_dup_WIRE_3_0_hist_0_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + wire _GEN_99 = + _cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32 + wire s2_flush_dup_0 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :684:28 + wire s2_flush_dup_1 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :684:28 + wire s2_flush_dup_2 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :684:28 + wire s1_flush_dup_0 = s2_flush_dup_0 | s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :360:26, :605:28 + wire s1_flush_dup_1 = s2_flush_dup_1 | s2_redirect_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :360:26, :605:28 + wire s1_flush_dup_2 = s2_flush_dup_2 | s2_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :360:26, :605:28 + wire s1_flush_dup_3 = s2_flush_dup_3 | s2_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :360:26, :605:28 + wire _GEN_100 = s3_valid_dup_3 | io_ftq_to_bpu_redirect_valid; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :408:{26,37}, :409:26, :410:{26,37} + always @(posedge clock or posedge reset) begin + if (reset) begin + s1_valid_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65 + s2_valid_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65 + s3_valid_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65 + s0_folded_gh_reg_dup_1_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63 + s0_folded_gh_reg_dup_1_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63 + s0_folded_gh_reg_dup_2_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63 + s0_folded_gh_reg_dup_3_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s1_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35 + s1_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35 + s1_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35 + s1_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s2_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35 + s2_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35 + s2_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35 + s2_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s3_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35 + s3_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35 + s3_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35 + s3_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s0_last_br_num_oh_reg_dup_1 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76 + s0_last_br_num_oh_reg_dup_2 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76 + s0_last_br_num_oh_reg_dup_3 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76 + s1_last_br_num_oh_dup_1 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76} + s1_last_br_num_oh_dup_2 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76} + s1_last_br_num_oh_dup_3 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76} + s2_last_br_num_oh_dup_1 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40 + s2_last_br_num_oh_dup_2 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40 + s2_last_br_num_oh_dup_3 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40 + s3_last_br_num_oh_dup_1 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40 + s3_last_br_num_oh_dup_2 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40 + s3_last_br_num_oh_dup_3 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + ghv_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_4 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_5 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_6 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_7 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_8 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_9 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_10 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_11 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_12 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_13 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_14 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_15 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_16 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_17 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_18 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_19 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_20 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_21 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_22 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_23 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_24 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_25 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_26 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_27 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_28 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_29 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_30 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_31 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_32 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_33 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_34 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_35 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_36 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_37 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_38 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_39 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_40 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_41 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_42 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_43 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_44 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_45 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_46 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_47 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_48 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_49 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_50 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_51 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_52 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_53 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_54 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_55 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_56 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_57 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_58 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_59 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_60 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_61 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_62 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_63 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_64 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_65 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_66 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_67 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_68 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_69 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_70 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_71 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_72 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_73 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_74 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_75 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_76 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_77 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_78 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_79 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_80 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_81 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_82 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_83 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_84 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_85 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_86 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_87 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_88 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_89 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_90 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_91 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_92 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_93 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_94 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_95 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_96 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_97 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_98 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_99 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_100 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_101 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_102 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_103 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_104 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_105 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_106 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_107 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_108 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_109 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_110 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_111 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_112 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_113 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_114 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_115 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_116 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_117 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_118 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_119 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_120 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_121 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_122 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_123 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_124 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_125 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_126 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_127 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_128 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_129 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_130 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_131 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_132 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_133 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_134 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_135 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_136 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_137 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_138 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_139 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_140 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_141 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_142 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_143 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_144 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_145 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_146 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_147 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_148 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_149 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_150 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_151 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_152 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_153 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_154 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_155 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_156 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_157 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_158 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_159 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_160 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_161 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_162 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_163 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_164 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_165 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_166 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_167 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_168 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_169 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_170 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_171 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_172 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_173 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_174 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_175 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_176 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_177 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_178 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_179 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_180 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_181 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_182 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_183 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_184 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_185 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_186 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_187 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_188 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_189 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_190 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_191 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_192 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_193 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_194 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_195 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_196 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_197 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_198 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_199 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_200 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_201 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_202 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_203 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_204 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_205 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_206 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_207 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_208 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_209 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_210 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_211 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_212 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_213 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_214 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_215 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_216 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_217 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_218 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_219 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_220 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_221 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_222 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_223 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_224 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_225 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_226 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_227 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_228 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_229 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_230 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_231 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_232 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_233 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_234 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_235 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_236 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_237 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_238 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_239 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_240 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_241 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_242 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_243 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_244 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_245 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_246 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_247 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_248 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_249 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_250 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_251 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_252 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_253 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_254 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_255 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + s0_ghist_ptr_reg_dup_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 + s0_ghist_ptr_reg_dup_0_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 + s0_ghist_ptr_reg_dup_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 + s0_ghist_ptr_reg_dup_1_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 + s0_ghist_ptr_reg_dup_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 + s0_ghist_ptr_reg_dup_2_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 + s0_ghist_ptr_reg_dup_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 + s0_ghist_ptr_reg_dup_3_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 + s1_ghist_ptr_dup_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 + s1_ghist_ptr_dup_0_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 + s1_ghist_ptr_dup_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 + s1_ghist_ptr_dup_1_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 + s1_ghist_ptr_dup_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 + s1_ghist_ptr_dup_2_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 + s1_ghist_ptr_dup_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 + s1_ghist_ptr_dup_3_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 + s2_ghist_ptr_dup_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 + s2_ghist_ptr_dup_0_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 + s2_ghist_ptr_dup_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 + s2_ghist_ptr_dup_1_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 + s2_ghist_ptr_dup_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 + s2_ghist_ptr_dup_2_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 + s2_ghist_ptr_dup_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 + s2_ghist_ptr_dup_3_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 + s3_ghist_ptr_dup_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 + s3_ghist_ptr_dup_0_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + s3_ghist_ptr_dup_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 + s3_ghist_ptr_dup_1_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + s3_ghist_ptr_dup_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 + s3_ghist_ptr_dup_2_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + s3_ghist_ptr_dup_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 + s3_ghist_ptr_dup_3_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + do_redirect_dup_3_valid <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_level <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_pc <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_pd_isRVC <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_pd_isCall <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_pd_isRet <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_ssp <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_sctr <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSW_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSW_value <= 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSR_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSR_value <= 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_NOS_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_NOS_value <= 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :350:40 + do_redirect_dup_3_bits_cfiUpdate_histPtr_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_histPtr_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_target <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_taken <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + thisBrNumOH_dup_shiftAmount <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_addIntoHist <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + previous_s1_pred_info_hit_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_hit_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_hit_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_hit_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_target_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 + previous_s1_pred_info_target_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 + previous_s1_pred_info_target_2 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 + previous_s1_pred_info_target_3 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 + previous_s1_pred_info_lastBrPosOH_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_0_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_0_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_1_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_1_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_2_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_2_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_3_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_3_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_taken_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_taken_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_taken_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_taken_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_0_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_1_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_2_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_3_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_cfiIndex_0 <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_cfiIndex_1 <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_cfiIndex_2 <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_cfiIndex_3 <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s2_pred_pc_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_pc_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_pc_2 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_pc_3 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_0_br_taken_mask_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_0_br_taken_mask_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_0_slot_valids_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_0_slot_valids_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_0_targets_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_0_targets_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_0_fallThroughAddr <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_0_is_br_sharing <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_0_hit <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_1_br_taken_mask_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_1_br_taken_mask_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_1_slot_valids_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_1_slot_valids_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_1_targets_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_1_targets_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_1_fallThroughAddr <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_1_is_br_sharing <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_1_hit <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_2_br_taken_mask_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_2_br_taken_mask_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_2_slot_valids_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_2_slot_valids_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_2_targets_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_2_targets_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_2_fallThroughAddr <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_2_is_br_sharing <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_2_hit <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_3_br_taken_mask_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_3_br_taken_mask_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_3_slot_valids_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_3_slot_valids_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_3_targets_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_3_targets_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_3_fallThroughAddr <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_3_is_br_sharing <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_3_hit <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + end + else begin + s1_valid_dup_3 <= + ~io_ftq_to_bpu_redirect_valid + & (s0_fire_dup_3 + | ~(s1_flush_dup_3 | s1_fire_dup_3 | io_ftq_to_bpu_redirect_valid) + & (s0_fire_dup_2 + | ~(s1_flush_dup_2 | s1_fire_dup_2 | io_ftq_to_bpu_redirect_valid) + & (s0_fire_dup_1 + | ~(s1_flush_dup_1 | s1_fire_dup_1 | io_ftq_to_bpu_redirect_valid) + & (s0_fire_dup_0 | ~(s1_flush_dup_0 | s1_fire_dup_0) + & s1_valid_dup_3)))); // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :360:26, :367:36, :374:60, :383:{31,42}, :384:{31,42}, :385:{31,42}, :386:{31,42} + s2_valid_dup_3 <= + ~s2_flush_dup_3 + & (s1_fire_dup_3 + ? ~s1_flush_dup_3 + : ~(s2_valid_dup_3 | s2_flush_dup_2) + & (s1_fire_dup_2 + ? ~s1_flush_dup_2 + : ~(s2_valid_dup_3 | s2_flush_dup_1) + & (s1_fire_dup_1 + ? ~s1_flush_dup_1 + : ~(s2_valid_dup_3 | s2_flush_dup_0) & s1_fire_dup_0 + & ~s1_flush_dup_0))); // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :358:26, :360:26, :374:60, :395:{26,37}, :396:{26,37,40}, :397:{26,37} + s3_valid_dup_3 <= + ~io_ftq_to_bpu_redirect_valid + & (s2_valid_dup_3 + ? ~s2_flush_dup_3 + : ~_GEN_100 + & (s2_valid_dup_3 + ? ~s2_flush_dup_2 + : ~_GEN_100 + & (s2_valid_dup_3 + ? ~s2_flush_dup_1 + : ~_GEN_100 & s2_valid_dup_3 & ~s2_flush_dup_0))); // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :358:26, :383:{31,42}, :384:31, :408:{26,37}, :409:{26,37,40}, :410:{26,37} + s0_folded_gh_reg_dup_1_hist_17_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_16_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_15_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_14_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_13_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_12_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_11_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_10_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_9_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_8_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_7_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_6_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_5_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_4_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_3_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_2_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_1_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_1_hist_0_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_17_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_16_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_15_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_14_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_13_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_12_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_11_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_10_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_9_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_8_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_7_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_6_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_5_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_4_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_3_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_2_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_1_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_2_hist_0_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_17_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_16_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_15_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_14_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_13_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_12_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_11_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_10_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_9_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_8_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_7_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_6_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_5_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_4_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_3_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_2_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_1_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_folded_gh_reg_dup_3_hist_0_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (s0_fire_dup_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:367:36 + s1_folded_gh_dup_1_hist_17_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_16_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_15_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_14_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_13_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_12_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_11_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_10_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_9_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_8_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_7_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_6_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_5_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_4_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_3_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_2_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_1_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_1_hist_0_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_17_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_16_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_15_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_14_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_13_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_12_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_11_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_10_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_9_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_8_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_7_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_6_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_5_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_4_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_3_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_2_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_1_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_2_hist_0_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_17_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_16_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_15_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_14_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_13_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_12_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_11_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_10_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_9_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_8_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_7_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_6_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_5_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_4_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_3_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_2_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_1_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_folded_gh_dup_3_hist_0_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_last_br_num_oh_dup_1 <= _s0_last_br_num_oh_dup_1_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_last_br_num_oh_dup_2 <= _s0_last_br_num_oh_dup_2_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_last_br_num_oh_dup_3 <= _s0_last_br_num_oh_dup_3_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ghist_ptr_dup_0_flag <= _s0_ghist_ptr_dup_0_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ghist_ptr_dup_0_value <= _s0_ghist_ptr_dup_0_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ghist_ptr_dup_1_flag <= _s0_ghist_ptr_dup_1_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ghist_ptr_dup_1_value <= _s0_ghist_ptr_dup_1_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ghist_ptr_dup_2_flag <= _s0_ghist_ptr_dup_2_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ghist_ptr_dup_2_value <= _s0_ghist_ptr_dup_2_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ghist_ptr_dup_3_flag <= _s0_ghist_ptr_dup_3_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s1_ghist_ptr_dup_3_value <= _s0_ghist_ptr_dup_3_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + end + if (s1_fire_dup_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:374:60 + s2_folded_gh_dup_1_hist_17_folded_hist <= s1_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_16_folded_hist <= s1_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_15_folded_hist <= s1_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_14_folded_hist <= s1_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_13_folded_hist <= s1_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_12_folded_hist <= s1_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_11_folded_hist <= s1_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_10_folded_hist <= s1_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_9_folded_hist <= s1_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_8_folded_hist <= s1_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_7_folded_hist <= s1_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_6_folded_hist <= s1_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_5_folded_hist <= s1_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_4_folded_hist <= s1_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_3_folded_hist <= s1_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_2_folded_hist <= s1_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_1_folded_hist <= s1_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_1_hist_0_folded_hist <= s1_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_17_folded_hist <= s1_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_16_folded_hist <= s1_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_15_folded_hist <= s1_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_14_folded_hist <= s1_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_13_folded_hist <= s1_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_12_folded_hist <= s1_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_11_folded_hist <= s1_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_10_folded_hist <= s1_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_9_folded_hist <= s1_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_8_folded_hist <= s1_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_7_folded_hist <= s1_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_6_folded_hist <= s1_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_5_folded_hist <= s1_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_4_folded_hist <= s1_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_3_folded_hist <= s1_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_2_folded_hist <= s1_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_1_folded_hist <= s1_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_2_hist_0_folded_hist <= s1_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_17_folded_hist <= s1_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_16_folded_hist <= s1_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_15_folded_hist <= s1_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_14_folded_hist <= s1_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_13_folded_hist <= s1_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_12_folded_hist <= s1_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_11_folded_hist <= s1_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_10_folded_hist <= s1_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_9_folded_hist <= s1_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_8_folded_hist <= s1_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_7_folded_hist <= s1_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_6_folded_hist <= s1_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_5_folded_hist <= s1_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_4_folded_hist <= s1_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_3_folded_hist <= s1_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_2_folded_hist <= s1_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_1_folded_hist <= s1_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_folded_gh_dup_3_hist_0_folded_hist <= s1_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35 + s2_last_br_num_oh_dup_1 <= s1_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, :293:40 + s2_last_br_num_oh_dup_2 <= s1_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, :293:40 + s2_last_br_num_oh_dup_3 <= s1_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, :293:40 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46 + s2_ghist_ptr_dup_0_flag <= s1_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 + s2_ghist_ptr_dup_0_value <= s1_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 + s2_ghist_ptr_dup_1_flag <= s1_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 + s2_ghist_ptr_dup_1_value <= s1_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 + s2_ghist_ptr_dup_2_flag <= s1_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 + s2_ghist_ptr_dup_2_value <= s1_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 + s2_ghist_ptr_dup_3_flag <= s1_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 + s2_ghist_ptr_dup_3_value <= s1_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35 + end + if (s2_valid_dup_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:271:65 + s3_folded_gh_dup_1_hist_17_folded_hist <= s2_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_16_folded_hist <= s2_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_15_folded_hist <= s2_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_14_folded_hist <= s2_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_13_folded_hist <= s2_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_12_folded_hist <= s2_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_11_folded_hist <= s2_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_10_folded_hist <= s2_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_9_folded_hist <= s2_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_8_folded_hist <= s2_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_7_folded_hist <= s2_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_6_folded_hist <= s2_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_5_folded_hist <= s2_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_4_folded_hist <= s2_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_3_folded_hist <= s2_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_2_folded_hist <= s2_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_1_folded_hist <= s2_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_1_hist_0_folded_hist <= s2_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_17_folded_hist <= s2_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_16_folded_hist <= s2_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_15_folded_hist <= s2_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_14_folded_hist <= s2_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_13_folded_hist <= s2_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_12_folded_hist <= s2_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_11_folded_hist <= s2_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_10_folded_hist <= s2_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_9_folded_hist <= s2_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_8_folded_hist <= s2_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_7_folded_hist <= s2_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_6_folded_hist <= s2_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_5_folded_hist <= s2_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_4_folded_hist <= s2_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_3_folded_hist <= s2_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_2_folded_hist <= s2_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_1_folded_hist <= s2_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_2_hist_0_folded_hist <= s2_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_17_folded_hist <= s2_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_16_folded_hist <= s2_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_15_folded_hist <= s2_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_14_folded_hist <= s2_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_13_folded_hist <= s2_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_12_folded_hist <= s2_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_11_folded_hist <= s2_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_10_folded_hist <= s2_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_9_folded_hist <= s2_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_8_folded_hist <= s2_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_7_folded_hist <= s2_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_6_folded_hist <= s2_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_5_folded_hist <= s2_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_4_folded_hist <= s2_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_3_folded_hist <= s2_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_2_folded_hist <= s2_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_1_folded_hist <= s2_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_folded_gh_dup_3_hist_0_folded_hist <= s2_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35 + s3_last_br_num_oh_dup_1 <= s2_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:293:40, :294:40 + s3_last_br_num_oh_dup_2 <= s2_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:293:40, :294:40 + s3_last_br_num_oh_dup_3 <= s2_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:293:40, :294:40 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46 + s3_ghist_ptr_dup_0_flag <= s2_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 + s3_ghist_ptr_dup_0_value <= s2_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 + s3_ghist_ptr_dup_1_flag <= s2_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 + s3_ghist_ptr_dup_1_value <= s2_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 + s3_ghist_ptr_dup_2_flag <= s2_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 + s3_ghist_ptr_dup_2_value <= s2_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 + s3_ghist_ptr_dup_3_flag <= s2_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 + s3_ghist_ptr_dup_3_value <= s2_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35 + previous_s2_pred_pc_0 <= _predictors_io_out_s2_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_pc_1 <= _predictors_io_out_s2_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_pc_2 <= _predictors_io_out_s2_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_pc_3 <= _predictors_io_out_s2_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_0_br_taken_mask_0 <= + _predictors_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_0_br_taken_mask_1 <= + _predictors_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_0_slot_valids_0 <= + _predictors_io_out_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_0_slot_valids_1 <= + _predictors_io_out_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_0_targets_0 <= + _predictors_io_out_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_0_targets_1 <= + _predictors_io_out_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_0_fallThroughAddr <= + _predictors_io_out_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_0_is_br_sharing <= + _predictors_io_out_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_0_hit <= _predictors_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_1_br_taken_mask_0 <= + _predictors_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_1_br_taken_mask_1 <= + _predictors_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_1_slot_valids_0 <= + _predictors_io_out_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_1_slot_valids_1 <= + _predictors_io_out_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_1_targets_0 <= + _predictors_io_out_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_1_targets_1 <= + _predictors_io_out_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_1_fallThroughAddr <= + _predictors_io_out_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_1_is_br_sharing <= + _predictors_io_out_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_1_hit <= _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_2_br_taken_mask_0 <= + _predictors_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_2_br_taken_mask_1 <= + _predictors_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_2_slot_valids_0 <= + _predictors_io_out_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_2_slot_valids_1 <= + _predictors_io_out_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_2_targets_0 <= + _predictors_io_out_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_2_targets_1 <= + _predictors_io_out_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_2_fallThroughAddr <= + _predictors_io_out_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_2_is_br_sharing <= + _predictors_io_out_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_2_hit <= _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_3_br_taken_mask_0 <= + _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_3_br_taken_mask_1 <= + _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_3_slot_valids_0 <= + _predictors_io_out_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_3_slot_valids_1 <= + _predictors_io_out_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_3_targets_0 <= + _predictors_io_out_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_3_targets_1 <= + _predictors_io_out_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_3_fallThroughAddr <= + _predictors_io_out_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_3_is_br_sharing <= + _predictors_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + previous_s2_pred_full_pred_3_hit <= _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35 + end + s0_last_br_num_oh_reg_dup_1 <= _s0_last_br_num_oh_dup_1_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_last_br_num_oh_reg_dup_2 <= _s0_last_br_num_oh_dup_2_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_last_br_num_oh_reg_dup_3 <= _s0_last_br_num_oh_dup_3_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_0_T | _ghv_wens_0_T_1 | _ghv_wens_0_T_2 | _ghv_wens_0_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_0 <= _ghv_write_datas_0_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_1_T | _ghv_wens_1_T_1 | _ghv_wens_1_T_2 | _ghv_wens_1_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_1 <= _ghv_write_datas_1_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_2_T | _ghv_wens_2_T_1 | _ghv_wens_2_T_2 | _ghv_wens_2_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_2 <= _ghv_write_datas_2_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_3_T | _ghv_wens_3_T_1 | _ghv_wens_3_T_2 | _ghv_wens_3_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_3 <= _ghv_write_datas_3_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_4_T | _ghv_wens_4_T_1 | _ghv_wens_4_T_2 | _ghv_wens_4_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_4 <= _ghv_write_datas_4_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_5_T | _ghv_wens_5_T_1 | _ghv_wens_5_T_2 | _ghv_wens_5_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_5 <= _ghv_write_datas_5_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_6_T | _ghv_wens_6_T_1 | _ghv_wens_6_T_2 | _ghv_wens_6_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_6 <= _ghv_write_datas_6_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_7_T | _ghv_wens_7_T_1 | _ghv_wens_7_T_2 | _ghv_wens_7_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_7 <= _ghv_write_datas_7_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_8_T | _ghv_wens_8_T_1 | _ghv_wens_8_T_2 | _ghv_wens_8_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_8 <= _ghv_write_datas_8_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_9_T | _ghv_wens_9_T_1 | _ghv_wens_9_T_2 | _ghv_wens_9_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_9 <= _ghv_write_datas_9_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_10_T | _ghv_wens_10_T_1 | _ghv_wens_10_T_2 | _ghv_wens_10_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_10 <= _ghv_write_datas_10_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_11_T | _ghv_wens_11_T_1 | _ghv_wens_11_T_2 | _ghv_wens_11_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_11 <= _ghv_write_datas_11_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_12_T | _ghv_wens_12_T_1 | _ghv_wens_12_T_2 | _ghv_wens_12_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_12 <= _ghv_write_datas_12_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_13_T | _ghv_wens_13_T_1 | _ghv_wens_13_T_2 | _ghv_wens_13_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_13 <= _ghv_write_datas_13_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_14_T | _ghv_wens_14_T_1 | _ghv_wens_14_T_2 | _ghv_wens_14_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_14 <= _ghv_write_datas_14_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_15_T | _ghv_wens_15_T_1 | _ghv_wens_15_T_2 | _ghv_wens_15_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_15 <= _ghv_write_datas_15_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_16_T | _ghv_wens_16_T_1 | _ghv_wens_16_T_2 | _ghv_wens_16_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_16 <= _ghv_write_datas_16_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_17_T | _ghv_wens_17_T_1 | _ghv_wens_17_T_2 | _ghv_wens_17_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_17 <= _ghv_write_datas_17_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_18_T | _ghv_wens_18_T_1 | _ghv_wens_18_T_2 | _ghv_wens_18_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_18 <= _ghv_write_datas_18_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_19_T | _ghv_wens_19_T_1 | _ghv_wens_19_T_2 | _ghv_wens_19_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_19 <= _ghv_write_datas_19_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_20_T | _ghv_wens_20_T_1 | _ghv_wens_20_T_2 | _ghv_wens_20_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_20 <= _ghv_write_datas_20_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_21_T | _ghv_wens_21_T_1 | _ghv_wens_21_T_2 | _ghv_wens_21_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_21 <= _ghv_write_datas_21_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_22_T | _ghv_wens_22_T_1 | _ghv_wens_22_T_2 | _ghv_wens_22_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_22 <= _ghv_write_datas_22_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_23_T | _ghv_wens_23_T_1 | _ghv_wens_23_T_2 | _ghv_wens_23_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_23 <= _ghv_write_datas_23_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_24_T | _ghv_wens_24_T_1 | _ghv_wens_24_T_2 | _ghv_wens_24_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_24 <= _ghv_write_datas_24_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_25_T | _ghv_wens_25_T_1 | _ghv_wens_25_T_2 | _ghv_wens_25_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_25 <= _ghv_write_datas_25_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_26_T | _ghv_wens_26_T_1 | _ghv_wens_26_T_2 | _ghv_wens_26_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_26 <= _ghv_write_datas_26_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_27_T | _ghv_wens_27_T_1 | _ghv_wens_27_T_2 | _ghv_wens_27_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_27 <= _ghv_write_datas_27_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_28_T | _ghv_wens_28_T_1 | _ghv_wens_28_T_2 | _ghv_wens_28_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_28 <= _ghv_write_datas_28_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_29_T | _ghv_wens_29_T_1 | _ghv_wens_29_T_2 | _ghv_wens_29_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_29 <= _ghv_write_datas_29_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_30_T | _ghv_wens_30_T_1 | _ghv_wens_30_T_2 | _ghv_wens_30_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_30 <= _ghv_write_datas_30_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_31_T | _ghv_wens_31_T_1 | _ghv_wens_31_T_2 | _ghv_wens_31_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_31 <= _ghv_write_datas_31_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_32_T | _ghv_wens_32_T_1 | _ghv_wens_32_T_2 | _ghv_wens_32_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_32 <= _ghv_write_datas_32_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_33_T | _ghv_wens_33_T_1 | _ghv_wens_33_T_2 | _ghv_wens_33_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_33 <= _ghv_write_datas_33_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_34_T | _ghv_wens_34_T_1 | _ghv_wens_34_T_2 | _ghv_wens_34_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_34 <= _ghv_write_datas_34_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_35_T | _ghv_wens_35_T_1 | _ghv_wens_35_T_2 | _ghv_wens_35_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_35 <= _ghv_write_datas_35_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_36_T | _ghv_wens_36_T_1 | _ghv_wens_36_T_2 | _ghv_wens_36_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_36 <= _ghv_write_datas_36_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_37_T | _ghv_wens_37_T_1 | _ghv_wens_37_T_2 | _ghv_wens_37_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_37 <= _ghv_write_datas_37_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_38_T | _ghv_wens_38_T_1 | _ghv_wens_38_T_2 | _ghv_wens_38_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_38 <= _ghv_write_datas_38_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_39_T | _ghv_wens_39_T_1 | _ghv_wens_39_T_2 | _ghv_wens_39_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_39 <= _ghv_write_datas_39_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_40_T | _ghv_wens_40_T_1 | _ghv_wens_40_T_2 | _ghv_wens_40_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_40 <= _ghv_write_datas_40_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_41_T | _ghv_wens_41_T_1 | _ghv_wens_41_T_2 | _ghv_wens_41_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_41 <= _ghv_write_datas_41_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_42_T | _ghv_wens_42_T_1 | _ghv_wens_42_T_2 | _ghv_wens_42_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_42 <= _ghv_write_datas_42_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_43_T | _ghv_wens_43_T_1 | _ghv_wens_43_T_2 | _ghv_wens_43_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_43 <= _ghv_write_datas_43_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_44_T | _ghv_wens_44_T_1 | _ghv_wens_44_T_2 | _ghv_wens_44_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_44 <= _ghv_write_datas_44_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_45_T | _ghv_wens_45_T_1 | _ghv_wens_45_T_2 | _ghv_wens_45_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_45 <= _ghv_write_datas_45_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_46_T | _ghv_wens_46_T_1 | _ghv_wens_46_T_2 | _ghv_wens_46_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_46 <= _ghv_write_datas_46_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_47_T | _ghv_wens_47_T_1 | _ghv_wens_47_T_2 | _ghv_wens_47_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_47 <= _ghv_write_datas_47_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_48_T | _ghv_wens_48_T_1 | _ghv_wens_48_T_2 | _ghv_wens_48_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_48 <= _ghv_write_datas_48_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_49_T | _ghv_wens_49_T_1 | _ghv_wens_49_T_2 | _ghv_wens_49_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_49 <= _ghv_write_datas_49_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_50_T | _ghv_wens_50_T_1 | _ghv_wens_50_T_2 | _ghv_wens_50_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_50 <= _ghv_write_datas_50_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_51_T | _ghv_wens_51_T_1 | _ghv_wens_51_T_2 | _ghv_wens_51_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_51 <= _ghv_write_datas_51_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_52_T | _ghv_wens_52_T_1 | _ghv_wens_52_T_2 | _ghv_wens_52_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_52 <= _ghv_write_datas_52_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_53_T | _ghv_wens_53_T_1 | _ghv_wens_53_T_2 | _ghv_wens_53_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_53 <= _ghv_write_datas_53_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_54_T | _ghv_wens_54_T_1 | _ghv_wens_54_T_2 | _ghv_wens_54_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_54 <= _ghv_write_datas_54_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_55_T | _ghv_wens_55_T_1 | _ghv_wens_55_T_2 | _ghv_wens_55_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_55 <= _ghv_write_datas_55_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_56_T | _ghv_wens_56_T_1 | _ghv_wens_56_T_2 | _ghv_wens_56_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_56 <= _ghv_write_datas_56_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_57_T | _ghv_wens_57_T_1 | _ghv_wens_57_T_2 | _ghv_wens_57_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_57 <= _ghv_write_datas_57_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_58_T | _ghv_wens_58_T_1 | _ghv_wens_58_T_2 | _ghv_wens_58_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_58 <= _ghv_write_datas_58_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_59_T | _ghv_wens_59_T_1 | _ghv_wens_59_T_2 | _ghv_wens_59_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_59 <= _ghv_write_datas_59_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_60_T | _ghv_wens_60_T_1 | _ghv_wens_60_T_2 | _ghv_wens_60_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_60 <= _ghv_write_datas_60_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_61_T | _ghv_wens_61_T_1 | _ghv_wens_61_T_2 | _ghv_wens_61_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_61 <= _ghv_write_datas_61_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_62_T | _ghv_wens_62_T_1 | _ghv_wens_62_T_2 | _ghv_wens_62_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_62 <= _ghv_write_datas_62_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_63_T | _ghv_wens_63_T_1 | _ghv_wens_63_T_2 | _ghv_wens_63_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_63 <= _ghv_write_datas_63_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_64_T | _ghv_wens_64_T_1 | _ghv_wens_64_T_2 | _ghv_wens_64_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_64 <= _ghv_write_datas_64_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_65_T | _ghv_wens_65_T_1 | _ghv_wens_65_T_2 | _ghv_wens_65_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_65 <= _ghv_write_datas_65_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_66_T | _ghv_wens_66_T_1 | _ghv_wens_66_T_2 | _ghv_wens_66_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_66 <= _ghv_write_datas_66_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_67_T | _ghv_wens_67_T_1 | _ghv_wens_67_T_2 | _ghv_wens_67_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_67 <= _ghv_write_datas_67_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_68_T | _ghv_wens_68_T_1 | _ghv_wens_68_T_2 | _ghv_wens_68_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_68 <= _ghv_write_datas_68_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_69_T | _ghv_wens_69_T_1 | _ghv_wens_69_T_2 | _ghv_wens_69_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_69 <= _ghv_write_datas_69_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_70_T | _ghv_wens_70_T_1 | _ghv_wens_70_T_2 | _ghv_wens_70_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_70 <= _ghv_write_datas_70_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_71_T | _ghv_wens_71_T_1 | _ghv_wens_71_T_2 | _ghv_wens_71_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_71 <= _ghv_write_datas_71_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_72_T | _ghv_wens_72_T_1 | _ghv_wens_72_T_2 | _ghv_wens_72_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_72 <= _ghv_write_datas_72_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_73_T | _ghv_wens_73_T_1 | _ghv_wens_73_T_2 | _ghv_wens_73_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_73 <= _ghv_write_datas_73_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_74_T | _ghv_wens_74_T_1 | _ghv_wens_74_T_2 | _ghv_wens_74_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_74 <= _ghv_write_datas_74_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_75_T | _ghv_wens_75_T_1 | _ghv_wens_75_T_2 | _ghv_wens_75_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_75 <= _ghv_write_datas_75_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_76_T | _ghv_wens_76_T_1 | _ghv_wens_76_T_2 | _ghv_wens_76_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_76 <= _ghv_write_datas_76_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_77_T | _ghv_wens_77_T_1 | _ghv_wens_77_T_2 | _ghv_wens_77_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_77 <= _ghv_write_datas_77_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_78_T | _ghv_wens_78_T_1 | _ghv_wens_78_T_2 | _ghv_wens_78_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_78 <= _ghv_write_datas_78_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_79_T | _ghv_wens_79_T_1 | _ghv_wens_79_T_2 | _ghv_wens_79_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_79 <= _ghv_write_datas_79_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_80_T | _ghv_wens_80_T_1 | _ghv_wens_80_T_2 | _ghv_wens_80_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_80 <= _ghv_write_datas_80_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_81_T | _ghv_wens_81_T_1 | _ghv_wens_81_T_2 | _ghv_wens_81_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_81 <= _ghv_write_datas_81_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_82_T | _ghv_wens_82_T_1 | _ghv_wens_82_T_2 | _ghv_wens_82_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_82 <= _ghv_write_datas_82_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_83_T | _ghv_wens_83_T_1 | _ghv_wens_83_T_2 | _ghv_wens_83_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_83 <= _ghv_write_datas_83_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_84_T | _ghv_wens_84_T_1 | _ghv_wens_84_T_2 | _ghv_wens_84_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_84 <= _ghv_write_datas_84_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_85_T | _ghv_wens_85_T_1 | _ghv_wens_85_T_2 | _ghv_wens_85_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_85 <= _ghv_write_datas_85_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_86_T | _ghv_wens_86_T_1 | _ghv_wens_86_T_2 | _ghv_wens_86_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_86 <= _ghv_write_datas_86_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_87_T | _ghv_wens_87_T_1 | _ghv_wens_87_T_2 | _ghv_wens_87_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_87 <= _ghv_write_datas_87_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_88_T | _ghv_wens_88_T_1 | _ghv_wens_88_T_2 | _ghv_wens_88_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_88 <= _ghv_write_datas_88_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_89_T | _ghv_wens_89_T_1 | _ghv_wens_89_T_2 | _ghv_wens_89_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_89 <= _ghv_write_datas_89_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_90_T | _ghv_wens_90_T_1 | _ghv_wens_90_T_2 | _ghv_wens_90_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_90 <= _ghv_write_datas_90_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_91_T | _ghv_wens_91_T_1 | _ghv_wens_91_T_2 | _ghv_wens_91_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_91 <= _ghv_write_datas_91_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_92_T | _ghv_wens_92_T_1 | _ghv_wens_92_T_2 | _ghv_wens_92_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_92 <= _ghv_write_datas_92_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_93_T | _ghv_wens_93_T_1 | _ghv_wens_93_T_2 | _ghv_wens_93_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_93 <= _ghv_write_datas_93_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_94_T | _ghv_wens_94_T_1 | _ghv_wens_94_T_2 | _ghv_wens_94_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_94 <= _ghv_write_datas_94_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_95_T | _ghv_wens_95_T_1 | _ghv_wens_95_T_2 | _ghv_wens_95_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_95 <= _ghv_write_datas_95_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_96_T | _ghv_wens_96_T_1 | _ghv_wens_96_T_2 | _ghv_wens_96_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_96 <= _ghv_write_datas_96_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_97_T | _ghv_wens_97_T_1 | _ghv_wens_97_T_2 | _ghv_wens_97_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_97 <= _ghv_write_datas_97_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_98_T | _ghv_wens_98_T_1 | _ghv_wens_98_T_2 | _ghv_wens_98_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_98 <= _ghv_write_datas_98_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_99_T | _ghv_wens_99_T_1 | _ghv_wens_99_T_2 | _ghv_wens_99_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_99 <= _ghv_write_datas_99_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_100_T | _ghv_wens_100_T_1 | _ghv_wens_100_T_2 | _ghv_wens_100_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_100 <= _ghv_write_datas_100_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_101_T | _ghv_wens_101_T_1 | _ghv_wens_101_T_2 | _ghv_wens_101_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_101 <= _ghv_write_datas_101_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_102_T | _ghv_wens_102_T_1 | _ghv_wens_102_T_2 | _ghv_wens_102_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_102 <= _ghv_write_datas_102_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_103_T | _ghv_wens_103_T_1 | _ghv_wens_103_T_2 | _ghv_wens_103_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_103 <= _ghv_write_datas_103_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_104_T | _ghv_wens_104_T_1 | _ghv_wens_104_T_2 | _ghv_wens_104_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_104 <= _ghv_write_datas_104_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_105_T | _ghv_wens_105_T_1 | _ghv_wens_105_T_2 | _ghv_wens_105_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_105 <= _ghv_write_datas_105_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_106_T | _ghv_wens_106_T_1 | _ghv_wens_106_T_2 | _ghv_wens_106_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_106 <= _ghv_write_datas_106_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_107_T | _ghv_wens_107_T_1 | _ghv_wens_107_T_2 | _ghv_wens_107_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_107 <= _ghv_write_datas_107_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_108_T | _ghv_wens_108_T_1 | _ghv_wens_108_T_2 | _ghv_wens_108_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_108 <= _ghv_write_datas_108_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_109_T | _ghv_wens_109_T_1 | _ghv_wens_109_T_2 | _ghv_wens_109_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_109 <= _ghv_write_datas_109_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_110_T | _ghv_wens_110_T_1 | _ghv_wens_110_T_2 | _ghv_wens_110_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_110 <= _ghv_write_datas_110_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_111_T | _ghv_wens_111_T_1 | _ghv_wens_111_T_2 | _ghv_wens_111_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_111 <= _ghv_write_datas_111_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_112_T | _ghv_wens_112_T_1 | _ghv_wens_112_T_2 | _ghv_wens_112_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_112 <= _ghv_write_datas_112_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_113_T | _ghv_wens_113_T_1 | _ghv_wens_113_T_2 | _ghv_wens_113_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_113 <= _ghv_write_datas_113_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_114_T | _ghv_wens_114_T_1 | _ghv_wens_114_T_2 | _ghv_wens_114_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_114 <= _ghv_write_datas_114_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_115_T | _ghv_wens_115_T_1 | _ghv_wens_115_T_2 | _ghv_wens_115_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_115 <= _ghv_write_datas_115_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_116_T | _ghv_wens_116_T_1 | _ghv_wens_116_T_2 | _ghv_wens_116_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_116 <= _ghv_write_datas_116_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_117_T | _ghv_wens_117_T_1 | _ghv_wens_117_T_2 | _ghv_wens_117_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_117 <= _ghv_write_datas_117_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_118_T | _ghv_wens_118_T_1 | _ghv_wens_118_T_2 | _ghv_wens_118_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_118 <= _ghv_write_datas_118_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_119_T | _ghv_wens_119_T_1 | _ghv_wens_119_T_2 | _ghv_wens_119_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_119 <= _ghv_write_datas_119_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_120_T | _ghv_wens_120_T_1 | _ghv_wens_120_T_2 | _ghv_wens_120_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_120 <= _ghv_write_datas_120_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_121_T | _ghv_wens_121_T_1 | _ghv_wens_121_T_2 | _ghv_wens_121_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_121 <= _ghv_write_datas_121_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_122_T | _ghv_wens_122_T_1 | _ghv_wens_122_T_2 | _ghv_wens_122_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_122 <= _ghv_write_datas_122_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_123_T | _ghv_wens_123_T_1 | _ghv_wens_123_T_2 | _ghv_wens_123_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_123 <= _ghv_write_datas_123_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_124_T | _ghv_wens_124_T_1 | _ghv_wens_124_T_2 | _ghv_wens_124_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_124 <= _ghv_write_datas_124_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_125_T | _ghv_wens_125_T_1 | _ghv_wens_125_T_2 | _ghv_wens_125_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_125 <= _ghv_write_datas_125_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_126_T | _ghv_wens_126_T_1 | _ghv_wens_126_T_2 | _ghv_wens_126_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_126 <= _ghv_write_datas_126_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_127_T | _ghv_wens_127_T_1 | _ghv_wens_127_T_2 | _ghv_wens_127_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_127 <= _ghv_write_datas_127_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_128_T | _ghv_wens_128_T_1 | _ghv_wens_128_T_2 | _ghv_wens_128_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_128 <= _ghv_write_datas_128_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_129_T | _ghv_wens_129_T_1 | _ghv_wens_129_T_2 | _ghv_wens_129_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_129 <= _ghv_write_datas_129_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_130_T | _ghv_wens_130_T_1 | _ghv_wens_130_T_2 | _ghv_wens_130_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_130 <= _ghv_write_datas_130_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_131_T | _ghv_wens_131_T_1 | _ghv_wens_131_T_2 | _ghv_wens_131_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_131 <= _ghv_write_datas_131_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_132_T | _ghv_wens_132_T_1 | _ghv_wens_132_T_2 | _ghv_wens_132_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_132 <= _ghv_write_datas_132_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_133_T | _ghv_wens_133_T_1 | _ghv_wens_133_T_2 | _ghv_wens_133_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_133 <= _ghv_write_datas_133_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_134_T | _ghv_wens_134_T_1 | _ghv_wens_134_T_2 | _ghv_wens_134_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_134 <= _ghv_write_datas_134_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_135_T | _ghv_wens_135_T_1 | _ghv_wens_135_T_2 | _ghv_wens_135_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_135 <= _ghv_write_datas_135_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_136_T | _ghv_wens_136_T_1 | _ghv_wens_136_T_2 | _ghv_wens_136_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_136 <= _ghv_write_datas_136_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_137_T | _ghv_wens_137_T_1 | _ghv_wens_137_T_2 | _ghv_wens_137_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_137 <= _ghv_write_datas_137_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_138_T | _ghv_wens_138_T_1 | _ghv_wens_138_T_2 | _ghv_wens_138_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_138 <= _ghv_write_datas_138_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_139_T | _ghv_wens_139_T_1 | _ghv_wens_139_T_2 | _ghv_wens_139_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_139 <= _ghv_write_datas_139_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_140_T | _ghv_wens_140_T_1 | _ghv_wens_140_T_2 | _ghv_wens_140_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_140 <= _ghv_write_datas_140_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_141_T | _ghv_wens_141_T_1 | _ghv_wens_141_T_2 | _ghv_wens_141_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_141 <= _ghv_write_datas_141_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_142_T | _ghv_wens_142_T_1 | _ghv_wens_142_T_2 | _ghv_wens_142_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_142 <= _ghv_write_datas_142_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_143_T | _ghv_wens_143_T_1 | _ghv_wens_143_T_2 | _ghv_wens_143_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_143 <= _ghv_write_datas_143_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_144_T | _ghv_wens_144_T_1 | _ghv_wens_144_T_2 | _ghv_wens_144_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_144 <= _ghv_write_datas_144_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_145_T | _ghv_wens_145_T_1 | _ghv_wens_145_T_2 | _ghv_wens_145_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_145 <= _ghv_write_datas_145_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_146_T | _ghv_wens_146_T_1 | _ghv_wens_146_T_2 | _ghv_wens_146_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_146 <= _ghv_write_datas_146_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_147_T | _ghv_wens_147_T_1 | _ghv_wens_147_T_2 | _ghv_wens_147_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_147 <= _ghv_write_datas_147_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_148_T | _ghv_wens_148_T_1 | _ghv_wens_148_T_2 | _ghv_wens_148_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_148 <= _ghv_write_datas_148_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_149_T | _ghv_wens_149_T_1 | _ghv_wens_149_T_2 | _ghv_wens_149_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_149 <= _ghv_write_datas_149_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_150_T | _ghv_wens_150_T_1 | _ghv_wens_150_T_2 | _ghv_wens_150_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_150 <= _ghv_write_datas_150_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_151_T | _ghv_wens_151_T_1 | _ghv_wens_151_T_2 | _ghv_wens_151_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_151 <= _ghv_write_datas_151_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_152_T | _ghv_wens_152_T_1 | _ghv_wens_152_T_2 | _ghv_wens_152_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_152 <= _ghv_write_datas_152_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_153_T | _ghv_wens_153_T_1 | _ghv_wens_153_T_2 | _ghv_wens_153_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_153 <= _ghv_write_datas_153_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_154_T | _ghv_wens_154_T_1 | _ghv_wens_154_T_2 | _ghv_wens_154_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_154 <= _ghv_write_datas_154_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_155_T | _ghv_wens_155_T_1 | _ghv_wens_155_T_2 | _ghv_wens_155_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_155 <= _ghv_write_datas_155_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_156_T | _ghv_wens_156_T_1 | _ghv_wens_156_T_2 | _ghv_wens_156_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_156 <= _ghv_write_datas_156_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_157_T | _ghv_wens_157_T_1 | _ghv_wens_157_T_2 | _ghv_wens_157_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_157 <= _ghv_write_datas_157_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_158_T | _ghv_wens_158_T_1 | _ghv_wens_158_T_2 | _ghv_wens_158_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_158 <= _ghv_write_datas_158_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_159_T | _ghv_wens_159_T_1 | _ghv_wens_159_T_2 | _ghv_wens_159_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_159 <= _ghv_write_datas_159_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_160_T | _ghv_wens_160_T_1 | _ghv_wens_160_T_2 | _ghv_wens_160_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_160 <= _ghv_write_datas_160_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_161_T | _ghv_wens_161_T_1 | _ghv_wens_161_T_2 | _ghv_wens_161_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_161 <= _ghv_write_datas_161_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_162_T | _ghv_wens_162_T_1 | _ghv_wens_162_T_2 | _ghv_wens_162_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_162 <= _ghv_write_datas_162_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_163_T | _ghv_wens_163_T_1 | _ghv_wens_163_T_2 | _ghv_wens_163_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_163 <= _ghv_write_datas_163_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_164_T | _ghv_wens_164_T_1 | _ghv_wens_164_T_2 | _ghv_wens_164_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_164 <= _ghv_write_datas_164_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_165_T | _ghv_wens_165_T_1 | _ghv_wens_165_T_2 | _ghv_wens_165_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_165 <= _ghv_write_datas_165_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_166_T | _ghv_wens_166_T_1 | _ghv_wens_166_T_2 | _ghv_wens_166_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_166 <= _ghv_write_datas_166_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_167_T | _ghv_wens_167_T_1 | _ghv_wens_167_T_2 | _ghv_wens_167_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_167 <= _ghv_write_datas_167_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_168_T | _ghv_wens_168_T_1 | _ghv_wens_168_T_2 | _ghv_wens_168_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_168 <= _ghv_write_datas_168_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_169_T | _ghv_wens_169_T_1 | _ghv_wens_169_T_2 | _ghv_wens_169_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_169 <= _ghv_write_datas_169_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_170_T | _ghv_wens_170_T_1 | _ghv_wens_170_T_2 | _ghv_wens_170_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_170 <= _ghv_write_datas_170_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_171_T | _ghv_wens_171_T_1 | _ghv_wens_171_T_2 | _ghv_wens_171_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_171 <= _ghv_write_datas_171_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_172_T | _ghv_wens_172_T_1 | _ghv_wens_172_T_2 | _ghv_wens_172_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_172 <= _ghv_write_datas_172_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_173_T | _ghv_wens_173_T_1 | _ghv_wens_173_T_2 | _ghv_wens_173_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_173 <= _ghv_write_datas_173_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_174_T | _ghv_wens_174_T_1 | _ghv_wens_174_T_2 | _ghv_wens_174_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_174 <= _ghv_write_datas_174_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_175_T | _ghv_wens_175_T_1 | _ghv_wens_175_T_2 | _ghv_wens_175_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_175 <= _ghv_write_datas_175_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_176_T | _ghv_wens_176_T_1 | _ghv_wens_176_T_2 | _ghv_wens_176_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_176 <= _ghv_write_datas_176_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_177_T | _ghv_wens_177_T_1 | _ghv_wens_177_T_2 | _ghv_wens_177_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_177 <= _ghv_write_datas_177_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_178_T | _ghv_wens_178_T_1 | _ghv_wens_178_T_2 | _ghv_wens_178_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_178 <= _ghv_write_datas_178_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_179_T | _ghv_wens_179_T_1 | _ghv_wens_179_T_2 | _ghv_wens_179_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_179 <= _ghv_write_datas_179_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_180_T | _ghv_wens_180_T_1 | _ghv_wens_180_T_2 | _ghv_wens_180_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_180 <= _ghv_write_datas_180_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_181_T | _ghv_wens_181_T_1 | _ghv_wens_181_T_2 | _ghv_wens_181_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_181 <= _ghv_write_datas_181_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_182_T | _ghv_wens_182_T_1 | _ghv_wens_182_T_2 | _ghv_wens_182_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_182 <= _ghv_write_datas_182_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_183_T | _ghv_wens_183_T_1 | _ghv_wens_183_T_2 | _ghv_wens_183_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_183 <= _ghv_write_datas_183_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_184_T | _ghv_wens_184_T_1 | _ghv_wens_184_T_2 | _ghv_wens_184_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_184 <= _ghv_write_datas_184_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_185_T | _ghv_wens_185_T_1 | _ghv_wens_185_T_2 | _ghv_wens_185_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_185 <= _ghv_write_datas_185_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_186_T | _ghv_wens_186_T_1 | _ghv_wens_186_T_2 | _ghv_wens_186_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_186 <= _ghv_write_datas_186_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_187_T | _ghv_wens_187_T_1 | _ghv_wens_187_T_2 | _ghv_wens_187_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_187 <= _ghv_write_datas_187_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_188_T | _ghv_wens_188_T_1 | _ghv_wens_188_T_2 | _ghv_wens_188_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_188 <= _ghv_write_datas_188_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_189_T | _ghv_wens_189_T_1 | _ghv_wens_189_T_2 | _ghv_wens_189_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_189 <= _ghv_write_datas_189_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_190_T | _ghv_wens_190_T_1 | _ghv_wens_190_T_2 | _ghv_wens_190_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_190 <= _ghv_write_datas_190_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_191_T | _ghv_wens_191_T_1 | _ghv_wens_191_T_2 | _ghv_wens_191_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_191 <= _ghv_write_datas_191_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_192_T | _ghv_wens_192_T_1 | _ghv_wens_192_T_2 | _ghv_wens_192_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_192 <= _ghv_write_datas_192_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_193_T | _ghv_wens_193_T_1 | _ghv_wens_193_T_2 | _ghv_wens_193_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_193 <= _ghv_write_datas_193_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_194_T | _ghv_wens_194_T_1 | _ghv_wens_194_T_2 | _ghv_wens_194_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_194 <= _ghv_write_datas_194_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_195_T | _ghv_wens_195_T_1 | _ghv_wens_195_T_2 | _ghv_wens_195_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_195 <= _ghv_write_datas_195_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_196_T | _ghv_wens_196_T_1 | _ghv_wens_196_T_2 | _ghv_wens_196_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_196 <= _ghv_write_datas_196_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_197_T | _ghv_wens_197_T_1 | _ghv_wens_197_T_2 | _ghv_wens_197_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_197 <= _ghv_write_datas_197_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_198_T | _ghv_wens_198_T_1 | _ghv_wens_198_T_2 | _ghv_wens_198_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_198 <= _ghv_write_datas_198_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_199_T | _ghv_wens_199_T_1 | _ghv_wens_199_T_2 | _ghv_wens_199_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_199 <= _ghv_write_datas_199_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_200_T | _ghv_wens_200_T_1 | _ghv_wens_200_T_2 | _ghv_wens_200_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_200 <= _ghv_write_datas_200_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_201_T | _ghv_wens_201_T_1 | _ghv_wens_201_T_2 | _ghv_wens_201_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_201 <= _ghv_write_datas_201_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_202_T | _ghv_wens_202_T_1 | _ghv_wens_202_T_2 | _ghv_wens_202_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_202 <= _ghv_write_datas_202_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_203_T | _ghv_wens_203_T_1 | _ghv_wens_203_T_2 | _ghv_wens_203_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_203 <= _ghv_write_datas_203_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_204_T | _ghv_wens_204_T_1 | _ghv_wens_204_T_2 | _ghv_wens_204_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_204 <= _ghv_write_datas_204_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_205_T | _ghv_wens_205_T_1 | _ghv_wens_205_T_2 | _ghv_wens_205_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_205 <= _ghv_write_datas_205_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_206_T | _ghv_wens_206_T_1 | _ghv_wens_206_T_2 | _ghv_wens_206_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_206 <= _ghv_write_datas_206_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_207_T | _ghv_wens_207_T_1 | _ghv_wens_207_T_2 | _ghv_wens_207_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_207 <= _ghv_write_datas_207_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_208_T | _ghv_wens_208_T_1 | _ghv_wens_208_T_2 | _ghv_wens_208_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_208 <= _ghv_write_datas_208_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_209_T | _ghv_wens_209_T_1 | _ghv_wens_209_T_2 | _ghv_wens_209_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_209 <= _ghv_write_datas_209_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_210_T | _ghv_wens_210_T_1 | _ghv_wens_210_T_2 | _ghv_wens_210_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_210 <= _ghv_write_datas_210_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_211_T | _ghv_wens_211_T_1 | _ghv_wens_211_T_2 | _ghv_wens_211_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_211 <= _ghv_write_datas_211_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_212_T | _ghv_wens_212_T_1 | _ghv_wens_212_T_2 | _ghv_wens_212_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_212 <= _ghv_write_datas_212_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_213_T | _ghv_wens_213_T_1 | _ghv_wens_213_T_2 | _ghv_wens_213_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_213 <= _ghv_write_datas_213_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_214_T | _ghv_wens_214_T_1 | _ghv_wens_214_T_2 | _ghv_wens_214_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_214 <= _ghv_write_datas_214_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_215_T | _ghv_wens_215_T_1 | _ghv_wens_215_T_2 | _ghv_wens_215_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_215 <= _ghv_write_datas_215_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_216_T | _ghv_wens_216_T_1 | _ghv_wens_216_T_2 | _ghv_wens_216_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_216 <= _ghv_write_datas_216_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_217_T | _ghv_wens_217_T_1 | _ghv_wens_217_T_2 | _ghv_wens_217_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_217 <= _ghv_write_datas_217_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_218_T | _ghv_wens_218_T_1 | _ghv_wens_218_T_2 | _ghv_wens_218_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_218 <= _ghv_write_datas_218_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_219_T | _ghv_wens_219_T_1 | _ghv_wens_219_T_2 | _ghv_wens_219_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_219 <= _ghv_write_datas_219_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_220_T | _ghv_wens_220_T_1 | _ghv_wens_220_T_2 | _ghv_wens_220_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_220 <= _ghv_write_datas_220_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_221_T | _ghv_wens_221_T_1 | _ghv_wens_221_T_2 | _ghv_wens_221_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_221 <= _ghv_write_datas_221_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_222_T | _ghv_wens_222_T_1 | _ghv_wens_222_T_2 | _ghv_wens_222_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_222 <= _ghv_write_datas_222_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_223_T | _ghv_wens_223_T_1 | _ghv_wens_223_T_2 | _ghv_wens_223_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_223 <= _ghv_write_datas_223_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_224_T | _ghv_wens_224_T_1 | _ghv_wens_224_T_2 | _ghv_wens_224_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_224 <= _ghv_write_datas_224_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_225_T | _ghv_wens_225_T_1 | _ghv_wens_225_T_2 | _ghv_wens_225_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_225 <= _ghv_write_datas_225_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_226_T | _ghv_wens_226_T_1 | _ghv_wens_226_T_2 | _ghv_wens_226_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_226 <= _ghv_write_datas_226_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_227_T | _ghv_wens_227_T_1 | _ghv_wens_227_T_2 | _ghv_wens_227_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_227 <= _ghv_write_datas_227_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_228_T | _ghv_wens_228_T_1 | _ghv_wens_228_T_2 | _ghv_wens_228_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_228 <= _ghv_write_datas_228_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_229_T | _ghv_wens_229_T_1 | _ghv_wens_229_T_2 | _ghv_wens_229_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_229 <= _ghv_write_datas_229_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_230_T | _ghv_wens_230_T_1 | _ghv_wens_230_T_2 | _ghv_wens_230_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_230 <= _ghv_write_datas_230_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_231_T | _ghv_wens_231_T_1 | _ghv_wens_231_T_2 | _ghv_wens_231_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_231 <= _ghv_write_datas_231_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_232_T | _ghv_wens_232_T_1 | _ghv_wens_232_T_2 | _ghv_wens_232_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_232 <= _ghv_write_datas_232_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_233_T | _ghv_wens_233_T_1 | _ghv_wens_233_T_2 | _ghv_wens_233_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_233 <= _ghv_write_datas_233_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_234_T | _ghv_wens_234_T_1 | _ghv_wens_234_T_2 | _ghv_wens_234_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_234 <= _ghv_write_datas_234_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_235_T | _ghv_wens_235_T_1 | _ghv_wens_235_T_2 | _ghv_wens_235_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_235 <= _ghv_write_datas_235_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_236_T | _ghv_wens_236_T_1 | _ghv_wens_236_T_2 | _ghv_wens_236_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_236 <= _ghv_write_datas_236_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_237_T | _ghv_wens_237_T_1 | _ghv_wens_237_T_2 | _ghv_wens_237_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_237 <= _ghv_write_datas_237_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_238_T | _ghv_wens_238_T_1 | _ghv_wens_238_T_2 | _ghv_wens_238_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_238 <= _ghv_write_datas_238_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_239_T | _ghv_wens_239_T_1 | _ghv_wens_239_T_2 | _ghv_wens_239_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_239 <= _ghv_write_datas_239_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_240_T | _ghv_wens_240_T_1 | _ghv_wens_240_T_2 | _ghv_wens_240_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_240 <= _ghv_write_datas_240_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_241_T | _ghv_wens_241_T_1 | _ghv_wens_241_T_2 | _ghv_wens_241_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_241 <= _ghv_write_datas_241_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_242_T | _ghv_wens_242_T_1 | _ghv_wens_242_T_2 | _ghv_wens_242_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_242 <= _ghv_write_datas_242_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_243_T | _ghv_wens_243_T_1 | _ghv_wens_243_T_2 | _ghv_wens_243_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_243 <= _ghv_write_datas_243_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_244_T | _ghv_wens_244_T_1 | _ghv_wens_244_T_2 | _ghv_wens_244_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_244 <= _ghv_write_datas_244_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_245_T | _ghv_wens_245_T_1 | _ghv_wens_245_T_2 | _ghv_wens_245_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_245 <= _ghv_write_datas_245_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_246_T | _ghv_wens_246_T_1 | _ghv_wens_246_T_2 | _ghv_wens_246_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_246 <= _ghv_write_datas_246_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_247_T | _ghv_wens_247_T_1 | _ghv_wens_247_T_2 | _ghv_wens_247_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_247 <= _ghv_write_datas_247_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_248_T | _ghv_wens_248_T_1 | _ghv_wens_248_T_2 | _ghv_wens_248_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_248 <= _ghv_write_datas_248_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_249_T | _ghv_wens_249_T_1 | _ghv_wens_249_T_2 | _ghv_wens_249_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_249 <= _ghv_write_datas_249_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_250_T | _ghv_wens_250_T_1 | _ghv_wens_250_T_2 | _ghv_wens_250_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_250 <= _ghv_write_datas_250_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_251_T | _ghv_wens_251_T_1 | _ghv_wens_251_T_2 | _ghv_wens_251_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_251 <= _ghv_write_datas_251_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_252_T | _ghv_wens_252_T_1 | _ghv_wens_252_T_2 | _ghv_wens_252_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_252 <= _ghv_write_datas_252_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_253_T | _ghv_wens_253_T_1 | _ghv_wens_253_T_2 | _ghv_wens_253_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_253 <= _ghv_write_datas_253_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_254_T | _ghv_wens_254_T_1 | _ghv_wens_254_T_2 | _ghv_wens_254_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_254 <= _ghv_write_datas_254_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + if (_ghv_wens_255_T | _ghv_wens_255_T_1 | _ghv_wens_255_T_2 | _ghv_wens_255_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113 + ghv_255 <= _ghv_write_datas_255_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ghist_ptr_reg_dup_0_flag <= _s0_ghist_ptr_dup_0_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ghist_ptr_reg_dup_0_value <= _s0_ghist_ptr_dup_0_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ghist_ptr_reg_dup_1_flag <= _s0_ghist_ptr_dup_1_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ghist_ptr_reg_dup_1_value <= _s0_ghist_ptr_dup_1_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ghist_ptr_reg_dup_2_flag <= _s0_ghist_ptr_dup_2_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ghist_ptr_reg_dup_2_value <= _s0_ghist_ptr_dup_2_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ghist_ptr_reg_dup_3_flag <= _s0_ghist_ptr_dup_3_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_ghist_ptr_reg_dup_3_value <= _s0_ghist_ptr_dup_3_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + do_redirect_dup_3_valid <= io_ftq_to_bpu_redirect_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_level <= io_ftq_to_bpu_redirect_bits_level; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_pc <= io_ftq_to_bpu_redirect_bits_cfiUpdate_pc; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_pd_isRVC <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_pd_isCall <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_pd_isRet <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_ssp <= io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_sctr <= io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSW_flag <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSW_value <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSR_flag <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSR_value <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_NOS_flag <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_NOS_value <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_histPtr_flag <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_histPtr_value <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_target <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_target; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_taken <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_taken; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + thisBrNumOH_dup_shiftAmount <= io_ftq_to_bpu_redirect_bits_cfiUpdate_shift; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + do_redirect_dup_3_bits_cfiUpdate_addIntoHist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + if (s1_fire_dup_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:374:60 + previous_s1_pred_info_hit_0 <= _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40 + previous_s1_pred_info_hit_1 <= _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40 + previous_s1_pred_info_hit_2 <= _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40 + previous_s1_pred_info_hit_3 <= _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40 + previous_s1_pred_info_target_0 <= + (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_targets_0 + : 39'h0) + | (~_cfiIndex_bits_WIRE_18_0 & s1_pred_info_takenMask_0_1 + & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_targets_1 + : 39'h0) + | ({s1_pred_info_takenMask_0_1, _cfiIndex_bits_WIRE_18_0} == 2'h0 + & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_fallThroughAddr + : 39'h0) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 + previous_s1_pred_info_target_1 <= + (_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_targets_0 + : 39'h0) + | (~_cfiIndex_bits_WIRE_22_0 & s1_pred_info_takenMask_1_1 + & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_targets_1 + : 39'h0) + | ({s1_pred_info_takenMask_1_1, _cfiIndex_bits_WIRE_22_0} == 2'h0 + & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_fallThroughAddr + : 39'h0) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 + previous_s1_pred_info_target_2 <= + (_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_targets_0 + : 39'h0) + | (~_cfiIndex_bits_WIRE_26_0 & s1_pred_info_takenMask_2_1 + & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_targets_1 + : 39'h0) + | ({s1_pred_info_takenMask_2_1, _cfiIndex_bits_WIRE_26_0} == 2'h0 + & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_fallThroughAddr + : 39'h0) | _GEN_6; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 + previous_s1_pred_info_target_3 <= + (_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_targets_0 + : 39'h0) + | (~_cfiIndex_bits_WIRE_30_0 & s1_pred_info_takenMask_3_1 + & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_targets_1 + : 39'h0) + | ({s1_pred_info_takenMask_3_1, _cfiIndex_bits_WIRE_30_0} == 2'h0 + & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_fallThroughAddr + : 39'h0) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 + previous_s1_pred_info_lastBrPosOH_0_0 <= + ~_predictors_io_out_s1_full_pred_0_hit + | ~(_predictors_io_out_s1_full_pred_0_slot_valids_0 + | _s1_ghv_wdatas_WIRE_44494_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41} + previous_s1_pred_info_lastBrPosOH_0_1 <= + _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_GEN_99 | ~_s1_ghv_wdatas_WIRE_44494_1) + & _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :488:{34,37,97} + previous_s1_pred_info_lastBrPosOH_0_2 <= + _s1_ghv_wdatas_WIRE_44494_1 & ~_GEN_99 & _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :487:9, :488:97 + previous_s1_pred_info_lastBrPosOH_1_0 <= + ~_predictors_io_out_s1_full_pred_1_hit | ~_GEN_8; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:{14,19,22,41} + previous_s1_pred_info_lastBrPosOH_1_1 <= + _predictors_io_out_s1_full_pred_1_slot_valids_0 & _GEN_10 + & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:488:{34,97} + previous_s1_pred_info_lastBrPosOH_1_2 <= + _s1_predicted_fh_dup_WIRE_21_1 & ~_GEN_9 + & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :487:9, :488:97 + previous_s1_pred_info_lastBrPosOH_2_0 <= + ~_predictors_io_out_s1_full_pred_2_hit | ~_GEN_11; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:{14,19,22,41} + previous_s1_pred_info_lastBrPosOH_2_1 <= + _predictors_io_out_s1_full_pred_2_slot_valids_0 & _GEN_13 + & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:488:{34,97} + previous_s1_pred_info_lastBrPosOH_2_2 <= + _s1_predicted_fh_dup_WIRE_35_1 & ~_GEN_12 + & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :487:9, :488:97 + previous_s1_pred_info_lastBrPosOH_3_0 <= + ~_predictors_io_out_s1_full_pred_3_hit | ~_GEN_14; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:{14,19,22,41} + previous_s1_pred_info_lastBrPosOH_3_1 <= + _predictors_io_out_s1_full_pred_3_slot_valids_0 & _GEN_16 + & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:488:{34,97} + previous_s1_pred_info_lastBrPosOH_3_2 <= + _s1_predicted_fh_dup_WIRE_49_1 & ~_GEN_15 + & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :487:9, :488:97 + previous_s1_pred_info_taken_0 <= + |{_predictors_io_out_s1_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_94 | ~_predictors_io_out_s1_full_pred_0_is_br_sharing) + & _predictors_io_out_s1_full_pred_0_hit, + _cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :519:{46,53} + previous_s1_pred_info_taken_1 <= + |{_predictors_io_out_s1_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_115 | ~_predictors_io_out_s1_full_pred_1_is_br_sharing) + & _predictors_io_out_s1_full_pred_1_hit, + _cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :519:{46,53} + previous_s1_pred_info_taken_2 <= + |{_predictors_io_out_s1_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_136 | ~_predictors_io_out_s1_full_pred_2_is_br_sharing) + & _predictors_io_out_s1_full_pred_2_hit, + _cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :519:{46,53} + previous_s1_pred_info_taken_3 <= + |{_predictors_io_out_s1_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_157 | ~_predictors_io_out_s1_full_pred_3_is_br_sharing) + & _predictors_io_out_s1_full_pred_3_hit, + _cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :519:{46,53} + previous_s1_pred_info_takenMask_0_0 <= _cfiIndex_bits_WIRE_18_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + previous_s1_pred_info_takenMask_0_1 <= s1_pred_info_takenMask_0_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25 + previous_s1_pred_info_takenMask_1_0 <= _cfiIndex_bits_WIRE_22_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + previous_s1_pred_info_takenMask_1_1 <= s1_pred_info_takenMask_1_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25 + previous_s1_pred_info_takenMask_2_0 <= _cfiIndex_bits_WIRE_26_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + previous_s1_pred_info_takenMask_2_1 <= s1_pred_info_takenMask_2_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25 + previous_s1_pred_info_takenMask_3_0 <= _cfiIndex_bits_WIRE_30_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + previous_s1_pred_info_takenMask_3_1 <= s1_pred_info_takenMask_3_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25 + previous_s1_pred_info_cfiIndex_0 <= + (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_offsets_0 + : _predictors_io_out_s1_full_pred_0_offsets_1) + | {4{{_predictors_io_out_s1_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_94 + | ~_predictors_io_out_s1_full_pred_0_is_br_sharing) + & _predictors_io_out_s1_full_pred_0_hit, + _cfiIndex_bits_WIRE_18_0 + & _predictors_io_out_s1_full_pred_0_hit} == 2'h0}}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + previous_s1_pred_info_cfiIndex_1 <= + (_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_offsets_0 + : _predictors_io_out_s1_full_pred_1_offsets_1) + | {4{{_predictors_io_out_s1_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_115 + | ~_predictors_io_out_s1_full_pred_1_is_br_sharing) + & _predictors_io_out_s1_full_pred_1_hit, + _cfiIndex_bits_WIRE_22_0 + & _predictors_io_out_s1_full_pred_1_hit} == 2'h0}}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + previous_s1_pred_info_cfiIndex_2 <= + (_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_offsets_0 + : _predictors_io_out_s1_full_pred_2_offsets_1) + | {4{{_predictors_io_out_s1_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_136 + | ~_predictors_io_out_s1_full_pred_2_is_br_sharing) + & _predictors_io_out_s1_full_pred_2_hit, + _cfiIndex_bits_WIRE_26_0 + & _predictors_io_out_s1_full_pred_2_hit} == 2'h0}}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + previous_s1_pred_info_cfiIndex_3 <= + (_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_offsets_0 + : _predictors_io_out_s1_full_pred_3_offsets_1) + | {4{{_predictors_io_out_s1_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_157 + | ~_predictors_io_out_s1_full_pred_3_is_br_sharing) + & _predictors_io_out_s1_full_pred_3_hit, + _cfiIndex_bits_WIRE_30_0 + & _predictors_io_out_s1_full_pred_3_hit} == 2'h0}}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77 + end + end + end // always @(posedge, posedge) + wire [38:0] _GEN_101 = {3'h0, _reset_vector_delay_io_out}; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:58, :278:43, :292:76, utility/src/main/scala/utility/Hold.scala:97:23 + always @(posedge clock) begin + s0_pc_reg_dup_0 <= REG_1 ? _GEN_101 : _s0_pc_dup_0_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:{16,58}, :278:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_pc_reg_dup_1 <= REG_1 ? _GEN_101 : _s0_pc_dup_1_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:{16,58}, :278:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_pc_reg_dup_2 <= REG_1 ? _GEN_101 : _s0_pc_dup_2_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:{16,58}, :278:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + s0_pc_reg_dup_3 <= REG_1 ? _GEN_101 : _s0_pc_dup_3_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:{16,58}, :278:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + REG <= reset; // src/main/scala/xiangshan/frontend/BPU.scala:277:24 + REG_1 <= REG & ~reset; // src/main/scala/xiangshan/frontend/BPU.scala:277:{16,24,39,42} + if (s1_fire_dup_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:374:60 + s2_ftq_idx_flag <= io_ftq_to_bpu_enq_ptr_flag; // src/main/scala/xiangshan/frontend/BPU.scala:708:29 + s2_ftq_idx_value <= io_ftq_to_bpu_enq_ptr_value; // src/main/scala/xiangshan/frontend/BPU.scala:708:29 + end + if (s2_valid_dup_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:271:65 + s3_ftq_idx_flag <= s2_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:708:29, :709:29 + s3_ftq_idx_value <= s2_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:708:29, :709:29 + end + predictors_io_update_REG_valid <= io_ftq_to_bpu_update_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_pc <= io_ftq_to_bpu_update_bits_pc; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_17_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_16_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_15_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_14_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_13_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_12_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_11_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_10_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_9_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_8_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_7_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_6_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_5_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_4_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_3_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_2_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_1_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_valid <= + io_ftq_to_bpu_update_bits_ftb_entry_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_brSlots_0_offset <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_brSlots_0_lower <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_brSlots_0_tarStat <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_brSlots_0_sharing <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_brSlots_0_valid <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_tailSlot_offset <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_tailSlot_lower <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_tailSlot_tarStat <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_tailSlot_sharing <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_tailSlot_valid <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_pftAddr <= + io_ftq_to_bpu_update_bits_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_carry <= + io_ftq_to_bpu_update_bits_ftb_entry_carry; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_isCall <= + io_ftq_to_bpu_update_bits_ftb_entry_isCall; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_isRet <= + io_ftq_to_bpu_update_bits_ftb_entry_isRet; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_isJalr <= + io_ftq_to_bpu_update_bits_ftb_entry_isJalr; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_last_may_be_rvi_call <= + io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_always_taken_0 <= + io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_ftb_entry_always_taken_1 <= + io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_cfi_idx_valid <= + io_ftq_to_bpu_update_bits_cfi_idx_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_cfi_idx_bits <= io_ftq_to_bpu_update_bits_cfi_idx_bits; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_br_taken_mask_0 <= + io_ftq_to_bpu_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_br_taken_mask_1 <= + io_ftq_to_bpu_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_jmp_taken <= io_ftq_to_bpu_update_bits_jmp_taken; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_mispred_mask_0 <= + io_ftq_to_bpu_update_bits_mispred_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_mispred_mask_1 <= + io_ftq_to_bpu_update_bits_mispred_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_mispred_mask_2 <= + io_ftq_to_bpu_update_bits_mispred_mask_2; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_old_entry <= io_ftq_to_bpu_update_bits_old_entry; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_meta <= io_ftq_to_bpu_update_bits_meta; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + predictors_io_update_REG_bits_full_target <= io_ftq_to_bpu_update_bits_full_target; // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:180]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + initial begin // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + for (logic [7:0] i = 8'h0; i < 8'hB5; i += 8'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + end // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + s1_valid_dup_3 = _RANDOM[8'h3][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65 + s2_valid_dup_3 = _RANDOM[8'h3][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65 + s3_valid_dup_3 = _RANDOM[8'h3][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65 + s0_pc_reg_dup_0 = {_RANDOM[8'h3][31:30], _RANDOM[8'h4], _RANDOM[8'h5][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65, :276:49 + s0_pc_reg_dup_1 = {_RANDOM[8'h5][31:5], _RANDOM[8'h6][11:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49 + s0_pc_reg_dup_2 = {_RANDOM[8'h6][31:12], _RANDOM[8'h7][18:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49 + s0_pc_reg_dup_3 = {_RANDOM[8'h7][31:19], _RANDOM[8'h8][25:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49 + REG = _RANDOM[8'h8][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49, :277:24 + REG_1 = _RANDOM[8'h8][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49, :277:16 + s0_folded_gh_reg_dup_1_hist_17_folded_hist = _RANDOM[8'h11][15:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_16_folded_hist = _RANDOM[8'h11][26:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_15_folded_hist = + {_RANDOM[8'h11][31:27], _RANDOM[8'h12][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_14_folded_hist = _RANDOM[8'h12][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_13_folded_hist = _RANDOM[8'h12][18:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_12_folded_hist = _RANDOM[8'h12][22:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_11_folded_hist = _RANDOM[8'h12][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_10_folded_hist = + {_RANDOM[8'h12][31], _RANDOM[8'h13][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_9_folded_hist = _RANDOM[8'h13][14:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_8_folded_hist = _RANDOM[8'h13][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_7_folded_hist = _RANDOM[8'h13][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_6_folded_hist = + {_RANDOM[8'h13][31:30], _RANDOM[8'h14][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_5_folded_hist = _RANDOM[8'h14][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_4_folded_hist = _RANDOM[8'h14][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_3_folded_hist = _RANDOM[8'h14][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_2_folded_hist = + {_RANDOM[8'h14][31:30], _RANDOM[8'h15][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_1_folded_hist = _RANDOM[8'h15][16:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_0_folded_hist = _RANDOM[8'h15][24:17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_17_folded_hist = + {_RANDOM[8'h15][31:25], _RANDOM[8'h16][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_16_folded_hist = _RANDOM[8'h16][14:4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_15_folded_hist = _RANDOM[8'h16][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_14_folded_hist = _RANDOM[8'h16][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_13_folded_hist = + {_RANDOM[8'h16][31:30], _RANDOM[8'h17][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_12_folded_hist = _RANDOM[8'h17][10:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_11_folded_hist = _RANDOM[8'h17][18:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_10_folded_hist = _RANDOM[8'h17][27:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_9_folded_hist = + {_RANDOM[8'h17][31:28], _RANDOM[8'h18][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_8_folded_hist = _RANDOM[8'h18][10:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_7_folded_hist = _RANDOM[8'h18][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_6_folded_hist = _RANDOM[8'h18][26:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_5_folded_hist = + {_RANDOM[8'h18][31:27], _RANDOM[8'h19][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_4_folded_hist = _RANDOM[8'h19][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_3_folded_hist = _RANDOM[8'h19][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_2_folded_hist = _RANDOM[8'h19][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_1_folded_hist = + {_RANDOM[8'h19][31:26], _RANDOM[8'h1A][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_0_folded_hist = _RANDOM[8'h1A][12:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_17_folded_hist = _RANDOM[8'h1A][23:13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_16_folded_hist = + {_RANDOM[8'h1A][31:24], _RANDOM[8'h1B][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_15_folded_hist = _RANDOM[8'h1B][9:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_14_folded_hist = _RANDOM[8'h1B][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_13_folded_hist = _RANDOM[8'h1B][26:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_12_folded_hist = _RANDOM[8'h1B][30:27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_11_folded_hist = + {_RANDOM[8'h1B][31], _RANDOM[8'h1C][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_10_folded_hist = _RANDOM[8'h1C][15:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_9_folded_hist = _RANDOM[8'h1C][22:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_8_folded_hist = _RANDOM[8'h1C][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_7_folded_hist = + {_RANDOM[8'h1C][31], _RANDOM[8'h1D][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_6_folded_hist = _RANDOM[8'h1D][14:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_5_folded_hist = _RANDOM[8'h1D][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_4_folded_hist = _RANDOM[8'h1D][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_3_folded_hist = + {_RANDOM[8'h1D][31:30], _RANDOM[8'h1E][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_2_folded_hist = _RANDOM[8'h1E][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_1_folded_hist = _RANDOM[8'h1E][24:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_0_folded_hist = + {_RANDOM[8'h1E][31:25], _RANDOM[8'h1F][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s1_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h23][31:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_16_folded_hist = _RANDOM[8'h24][10:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_15_folded_hist = _RANDOM[8'h24][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h24][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_13_folded_hist = + {_RANDOM[8'h24][31:26], _RANDOM[8'h25][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h25][6:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h25][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_10_folded_hist = _RANDOM[8'h25][23:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h25][30:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_8_folded_hist = {_RANDOM[8'h25][31], _RANDOM[8'h26][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h26][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_6_folded_hist = _RANDOM[8'h26][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h26][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_4_folded_hist = + {_RANDOM[8'h26][31:30], _RANDOM[8'h27][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h27][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_2_folded_hist = _RANDOM[8'h27][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_1_folded_hist = + {_RANDOM[8'h27][31:22], _RANDOM[8'h28][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_0_folded_hist = _RANDOM[8'h28][8:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_17_folded_hist = _RANDOM[8'h28][19:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h28][30:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_15_folded_hist = + {_RANDOM[8'h28][31], _RANDOM[8'h29][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h29][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_13_folded_hist = _RANDOM[8'h29][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h29][26:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_11_folded_hist = + {_RANDOM[8'h29][31:27], _RANDOM[8'h2A][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h2A][11:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_9_folded_hist = _RANDOM[8'h2A][18:12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h2A][26:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_7_folded_hist = + {_RANDOM[8'h2A][31:27], _RANDOM[8'h2B][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h2B][10:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_5_folded_hist = _RANDOM[8'h2B][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h2B][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_3_folded_hist = + {_RANDOM[8'h2B][31:26], _RANDOM[8'h2C][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h2C][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_1_folded_hist = _RANDOM[8'h2C][20:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h2C][28:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_17_folded_hist = + {_RANDOM[8'h2C][31:29], _RANDOM[8'h2D][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_16_folded_hist = _RANDOM[8'h2D][18:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h2D][25:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_14_folded_hist = + {_RANDOM[8'h2D][31:26], _RANDOM[8'h2E][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h2E][10:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h2E][14:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_11_folded_hist = _RANDOM[8'h2E][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h2E][31:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_9_folded_hist = _RANDOM[8'h2F][6:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h2F][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_7_folded_hist = _RANDOM[8'h2F][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h2F][30:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_5_folded_hist = {_RANDOM[8'h2F][31], _RANDOM[8'h30][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h30][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_3_folded_hist = _RANDOM[8'h30][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h30][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_1_folded_hist = + {_RANDOM[8'h30][31:30], _RANDOM[8'h31][8:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_0_folded_hist = _RANDOM[8'h31][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s2_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h36][15:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_16_folded_hist = _RANDOM[8'h36][26:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_15_folded_hist = + {_RANDOM[8'h36][31:27], _RANDOM[8'h37][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h37][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_13_folded_hist = _RANDOM[8'h37][18:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h37][22:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h37][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_10_folded_hist = + {_RANDOM[8'h37][31], _RANDOM[8'h38][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h38][14:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_8_folded_hist = _RANDOM[8'h38][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h38][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_6_folded_hist = + {_RANDOM[8'h38][31:30], _RANDOM[8'h39][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h39][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_4_folded_hist = _RANDOM[8'h39][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h39][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_2_folded_hist = + {_RANDOM[8'h39][31:30], _RANDOM[8'h3A][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_1_folded_hist = _RANDOM[8'h3A][16:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_0_folded_hist = _RANDOM[8'h3A][24:17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_17_folded_hist = + {_RANDOM[8'h3A][31:25], _RANDOM[8'h3B][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h3B][14:4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_15_folded_hist = _RANDOM[8'h3B][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h3B][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_13_folded_hist = + {_RANDOM[8'h3B][31:30], _RANDOM[8'h3C][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h3C][10:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_11_folded_hist = _RANDOM[8'h3C][18:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h3C][27:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_9_folded_hist = + {_RANDOM[8'h3C][31:28], _RANDOM[8'h3D][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h3D][10:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_7_folded_hist = _RANDOM[8'h3D][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h3D][26:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_5_folded_hist = + {_RANDOM[8'h3D][31:27], _RANDOM[8'h3E][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h3E][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_3_folded_hist = _RANDOM[8'h3E][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h3E][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_1_folded_hist = + {_RANDOM[8'h3E][31:26], _RANDOM[8'h3F][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h3F][12:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_17_folded_hist = _RANDOM[8'h3F][23:13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_16_folded_hist = + {_RANDOM[8'h3F][31:24], _RANDOM[8'h40][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h40][9:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_14_folded_hist = _RANDOM[8'h40][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h40][26:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h40][30:27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_11_folded_hist = + {_RANDOM[8'h40][31], _RANDOM[8'h41][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h41][15:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_9_folded_hist = _RANDOM[8'h41][22:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h41][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_7_folded_hist = {_RANDOM[8'h41][31], _RANDOM[8'h42][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h42][14:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_5_folded_hist = _RANDOM[8'h42][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h42][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_3_folded_hist = + {_RANDOM[8'h42][31:30], _RANDOM[8'h43][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h43][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_1_folded_hist = _RANDOM[8'h43][24:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_0_folded_hist = + {_RANDOM[8'h43][31:25], _RANDOM[8'h44][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s3_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h48][31:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_16_folded_hist = _RANDOM[8'h49][10:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_15_folded_hist = _RANDOM[8'h49][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h49][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_13_folded_hist = + {_RANDOM[8'h49][31:26], _RANDOM[8'h4A][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h4A][6:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h4A][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_10_folded_hist = _RANDOM[8'h4A][23:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h4A][30:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_8_folded_hist = {_RANDOM[8'h4A][31], _RANDOM[8'h4B][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h4B][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_6_folded_hist = _RANDOM[8'h4B][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h4B][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_4_folded_hist = + {_RANDOM[8'h4B][31:30], _RANDOM[8'h4C][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h4C][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_2_folded_hist = _RANDOM[8'h4C][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_1_folded_hist = + {_RANDOM[8'h4C][31:22], _RANDOM[8'h4D][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_0_folded_hist = _RANDOM[8'h4D][8:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_17_folded_hist = _RANDOM[8'h4D][19:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h4D][30:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_15_folded_hist = + {_RANDOM[8'h4D][31], _RANDOM[8'h4E][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h4E][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_13_folded_hist = _RANDOM[8'h4E][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h4E][26:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_11_folded_hist = + {_RANDOM[8'h4E][31:27], _RANDOM[8'h4F][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h4F][11:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_9_folded_hist = _RANDOM[8'h4F][18:12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h4F][26:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_7_folded_hist = + {_RANDOM[8'h4F][31:27], _RANDOM[8'h50][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h50][10:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_5_folded_hist = _RANDOM[8'h50][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h50][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_3_folded_hist = + {_RANDOM[8'h50][31:26], _RANDOM[8'h51][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h51][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_1_folded_hist = _RANDOM[8'h51][20:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h51][28:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_17_folded_hist = + {_RANDOM[8'h51][31:29], _RANDOM[8'h52][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_16_folded_hist = _RANDOM[8'h52][18:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h52][25:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_14_folded_hist = + {_RANDOM[8'h52][31:26], _RANDOM[8'h53][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h53][10:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h53][14:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_11_folded_hist = _RANDOM[8'h53][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h53][31:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_9_folded_hist = _RANDOM[8'h54][6:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h54][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_7_folded_hist = _RANDOM[8'h54][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h54][30:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_5_folded_hist = {_RANDOM[8'h54][31], _RANDOM[8'h55][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h55][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_3_folded_hist = _RANDOM[8'h55][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h55][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_1_folded_hist = + {_RANDOM[8'h55][31:30], _RANDOM[8'h56][8:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_0_folded_hist = _RANDOM[8'h56][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s0_last_br_num_oh_reg_dup_1 = _RANDOM[8'h56][22:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35, :291:73 + s0_last_br_num_oh_reg_dup_2 = _RANDOM[8'h56][25:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35, :291:73 + s0_last_br_num_oh_reg_dup_3 = _RANDOM[8'h56][28:26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35, :291:73 + s1_last_br_num_oh_dup_1 = _RANDOM[8'h57][2:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40 + s1_last_br_num_oh_dup_2 = _RANDOM[8'h57][5:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40 + s1_last_br_num_oh_dup_3 = _RANDOM[8'h57][8:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40 + s2_last_br_num_oh_dup_1 = _RANDOM[8'h57][14:12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :293:40 + s2_last_br_num_oh_dup_2 = _RANDOM[8'h57][17:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :293:40 + s2_last_br_num_oh_dup_3 = _RANDOM[8'h57][20:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :293:40 + s3_last_br_num_oh_dup_1 = _RANDOM[8'h57][26:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :294:40 + s3_last_br_num_oh_dup_2 = _RANDOM[8'h57][29:27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :294:40 + s3_last_br_num_oh_dup_3 = {_RANDOM[8'h57][31:30], _RANDOM[8'h58][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :294:40 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 = _RANDOM[8'h58][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 = _RANDOM[8'h58][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 = _RANDOM[8'h58][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 = _RANDOM[8'h58][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 = _RANDOM[8'h58][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 = _RANDOM[8'h58][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 = _RANDOM[8'h58][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 = _RANDOM[8'h59][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 = _RANDOM[8'h59][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 = _RANDOM[8'h59][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 = _RANDOM[8'h59][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 = _RANDOM[8'h59][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 = _RANDOM[8'h59][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 = _RANDOM[8'h59][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 = _RANDOM[8'h59][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 = _RANDOM[8'h59][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 = _RANDOM[8'h59][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 = _RANDOM[8'h59][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 = _RANDOM[8'h59][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 = _RANDOM[8'h59][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 = _RANDOM[8'h59][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 = _RANDOM[8'h59][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 = _RANDOM[8'h59][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 = _RANDOM[8'h59][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 = _RANDOM[8'h59][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 = _RANDOM[8'h59][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 = _RANDOM[8'h59][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 = _RANDOM[8'h59][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 = _RANDOM[8'h59][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 = _RANDOM[8'h59][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 = _RANDOM[8'h59][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 = _RANDOM[8'h59][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 = _RANDOM[8'h59][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 = _RANDOM[8'h59][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 = _RANDOM[8'h59][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 = _RANDOM[8'h59][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 = _RANDOM[8'h59][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 = _RANDOM[8'h59][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 = _RANDOM[8'h59][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 = _RANDOM[8'h5A][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 = _RANDOM[8'h5A][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 = _RANDOM[8'h5A][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 = _RANDOM[8'h5A][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 = _RANDOM[8'h5A][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 = _RANDOM[8'h5A][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 = _RANDOM[8'h5A][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 = _RANDOM[8'h5A][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 = _RANDOM[8'h5A][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 = _RANDOM[8'h5A][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 = _RANDOM[8'h5A][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 = _RANDOM[8'h5A][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 = _RANDOM[8'h5A][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 = _RANDOM[8'h5A][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 = _RANDOM[8'h5A][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 = _RANDOM[8'h5A][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 = _RANDOM[8'h5A][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 = _RANDOM[8'h5A][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 = _RANDOM[8'h5A][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 = _RANDOM[8'h5A][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 = _RANDOM[8'h5A][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 = _RANDOM[8'h5A][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 = _RANDOM[8'h5A][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 = _RANDOM[8'h5A][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 = _RANDOM[8'h5A][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 = _RANDOM[8'h5A][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 = _RANDOM[8'h5A][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 = _RANDOM[8'h5A][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 = _RANDOM[8'h5A][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 = _RANDOM[8'h5A][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 = _RANDOM[8'h5A][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 = _RANDOM[8'h5A][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 = _RANDOM[8'h5B][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h5B][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h5B][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h5B][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h5B][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h5B][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h5B][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h5B][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h5C][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h5C][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h5C][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h5C][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h5C][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h5C][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h5C][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h5C][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h5C][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h5C][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h5C][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h5C][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h5C][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h5C][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h5C][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h5C][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h5C][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h5C][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h5C][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h5C][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h5C][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h5C][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h5C][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h5C][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h5C][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h5C][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h5C][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h5C][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h5C][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h5C][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h5C][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h5D][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h5D][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h5D][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h5D][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h5D][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h5D][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h5D][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h5D][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h5D][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h5D][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h5D][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h5D][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h5D][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h5D][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h5D][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h5D][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h5D][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h5D][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h5D][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h5D][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h5D][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h5D][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h5D][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h5D][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h5D][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h5D][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h5D][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h5D][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h5D][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h5D][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h5D][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h5E][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h5E][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h5E][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h5E][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h5E][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h5E][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h5E][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h5E][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h5F][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h5F][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h5F][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h5F][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h5F][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h5F][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h5F][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h5F][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h5F][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h5F][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h5F][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h5F][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h5F][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h5F][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h5F][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h5F][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h5F][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h5F][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h5F][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h5F][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h5F][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h5F][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h5F][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h5F][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h5F][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h5F][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h5F][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h5F][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h5F][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h5F][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h5F][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h60][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h60][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h60][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h60][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h60][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h60][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h60][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h60][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h60][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h60][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h60][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h60][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h60][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h60][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h60][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h60][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h60][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h60][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h60][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h60][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h60][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h60][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h60][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h60][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h60][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h60][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h60][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h60][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h60][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h60][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h60][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h61][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h61][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h61][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h61][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h61][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h61][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h61][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h61][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h62][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h62][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h62][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h62][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h62][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h62][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h62][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h62][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h62][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h62][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h62][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h62][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h62][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h62][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h62][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h62][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h62][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h62][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h62][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h62][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h62][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h62][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h62][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h62][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h62][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h62][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h62][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h62][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h62][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h62][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h62][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h63][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h63][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h63][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h63][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h63][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h63][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h63][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h63][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h63][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h63][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h63][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h63][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h63][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h63][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h63][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h63][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h63][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h63][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h63][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h63][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h63][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h63][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h63][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h63][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h63][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h63][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h63][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h63][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h63][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h63][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h63][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h64][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + ghv_0 = _RANDOM[8'h64][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_1 = _RANDOM[8'h64][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_2 = _RANDOM[8'h64][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_3 = _RANDOM[8'h64][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_4 = _RANDOM[8'h64][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_5 = _RANDOM[8'h64][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_6 = _RANDOM[8'h64][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_7 = _RANDOM[8'h64][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_8 = _RANDOM[8'h64][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_9 = _RANDOM[8'h64][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_10 = _RANDOM[8'h64][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_11 = _RANDOM[8'h64][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_12 = _RANDOM[8'h64][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_13 = _RANDOM[8'h64][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_14 = _RANDOM[8'h64][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_15 = _RANDOM[8'h64][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_16 = _RANDOM[8'h64][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_17 = _RANDOM[8'h64][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_18 = _RANDOM[8'h64][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_19 = _RANDOM[8'h64][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_20 = _RANDOM[8'h64][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_21 = _RANDOM[8'h64][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_22 = _RANDOM[8'h64][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_23 = _RANDOM[8'h64][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_24 = _RANDOM[8'h64][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_25 = _RANDOM[8'h64][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_26 = _RANDOM[8'h64][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_27 = _RANDOM[8'h64][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_28 = _RANDOM[8'h64][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_29 = _RANDOM[8'h64][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_30 = _RANDOM[8'h64][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20 + ghv_31 = _RANDOM[8'h65][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_32 = _RANDOM[8'h65][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_33 = _RANDOM[8'h65][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_34 = _RANDOM[8'h65][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_35 = _RANDOM[8'h65][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_36 = _RANDOM[8'h65][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_37 = _RANDOM[8'h65][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_38 = _RANDOM[8'h65][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_39 = _RANDOM[8'h65][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_40 = _RANDOM[8'h65][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_41 = _RANDOM[8'h65][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_42 = _RANDOM[8'h65][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_43 = _RANDOM[8'h65][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_44 = _RANDOM[8'h65][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_45 = _RANDOM[8'h65][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_46 = _RANDOM[8'h65][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_47 = _RANDOM[8'h65][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_48 = _RANDOM[8'h65][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_49 = _RANDOM[8'h65][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_50 = _RANDOM[8'h65][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_51 = _RANDOM[8'h65][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_52 = _RANDOM[8'h65][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_53 = _RANDOM[8'h65][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_54 = _RANDOM[8'h65][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_55 = _RANDOM[8'h65][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_56 = _RANDOM[8'h65][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_57 = _RANDOM[8'h65][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_58 = _RANDOM[8'h65][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_59 = _RANDOM[8'h65][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_60 = _RANDOM[8'h65][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_61 = _RANDOM[8'h65][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_62 = _RANDOM[8'h65][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_63 = _RANDOM[8'h66][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_64 = _RANDOM[8'h66][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_65 = _RANDOM[8'h66][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_66 = _RANDOM[8'h66][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_67 = _RANDOM[8'h66][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_68 = _RANDOM[8'h66][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_69 = _RANDOM[8'h66][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_70 = _RANDOM[8'h66][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_71 = _RANDOM[8'h66][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_72 = _RANDOM[8'h66][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_73 = _RANDOM[8'h66][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_74 = _RANDOM[8'h66][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_75 = _RANDOM[8'h66][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_76 = _RANDOM[8'h66][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_77 = _RANDOM[8'h66][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_78 = _RANDOM[8'h66][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_79 = _RANDOM[8'h66][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_80 = _RANDOM[8'h66][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_81 = _RANDOM[8'h66][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_82 = _RANDOM[8'h66][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_83 = _RANDOM[8'h66][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_84 = _RANDOM[8'h66][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_85 = _RANDOM[8'h66][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_86 = _RANDOM[8'h66][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_87 = _RANDOM[8'h66][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_88 = _RANDOM[8'h66][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_89 = _RANDOM[8'h66][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_90 = _RANDOM[8'h66][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_91 = _RANDOM[8'h66][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_92 = _RANDOM[8'h66][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_93 = _RANDOM[8'h66][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_94 = _RANDOM[8'h66][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_95 = _RANDOM[8'h67][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_96 = _RANDOM[8'h67][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_97 = _RANDOM[8'h67][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_98 = _RANDOM[8'h67][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_99 = _RANDOM[8'h67][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_100 = _RANDOM[8'h67][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_101 = _RANDOM[8'h67][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_102 = _RANDOM[8'h67][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_103 = _RANDOM[8'h67][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_104 = _RANDOM[8'h67][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_105 = _RANDOM[8'h67][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_106 = _RANDOM[8'h67][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_107 = _RANDOM[8'h67][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_108 = _RANDOM[8'h67][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_109 = _RANDOM[8'h67][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_110 = _RANDOM[8'h67][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_111 = _RANDOM[8'h67][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_112 = _RANDOM[8'h67][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_113 = _RANDOM[8'h67][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_114 = _RANDOM[8'h67][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_115 = _RANDOM[8'h67][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_116 = _RANDOM[8'h67][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_117 = _RANDOM[8'h67][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_118 = _RANDOM[8'h67][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_119 = _RANDOM[8'h67][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_120 = _RANDOM[8'h67][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_121 = _RANDOM[8'h67][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_122 = _RANDOM[8'h67][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_123 = _RANDOM[8'h67][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_124 = _RANDOM[8'h67][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_125 = _RANDOM[8'h67][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_126 = _RANDOM[8'h67][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_127 = _RANDOM[8'h68][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_128 = _RANDOM[8'h68][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_129 = _RANDOM[8'h68][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_130 = _RANDOM[8'h68][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_131 = _RANDOM[8'h68][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_132 = _RANDOM[8'h68][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_133 = _RANDOM[8'h68][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_134 = _RANDOM[8'h68][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_135 = _RANDOM[8'h68][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_136 = _RANDOM[8'h68][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_137 = _RANDOM[8'h68][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_138 = _RANDOM[8'h68][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_139 = _RANDOM[8'h68][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_140 = _RANDOM[8'h68][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_141 = _RANDOM[8'h68][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_142 = _RANDOM[8'h68][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_143 = _RANDOM[8'h68][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_144 = _RANDOM[8'h68][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_145 = _RANDOM[8'h68][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_146 = _RANDOM[8'h68][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_147 = _RANDOM[8'h68][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_148 = _RANDOM[8'h68][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_149 = _RANDOM[8'h68][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_150 = _RANDOM[8'h68][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_151 = _RANDOM[8'h68][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_152 = _RANDOM[8'h68][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_153 = _RANDOM[8'h68][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_154 = _RANDOM[8'h68][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_155 = _RANDOM[8'h68][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_156 = _RANDOM[8'h68][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_157 = _RANDOM[8'h68][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_158 = _RANDOM[8'h68][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_159 = _RANDOM[8'h69][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_160 = _RANDOM[8'h69][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_161 = _RANDOM[8'h69][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_162 = _RANDOM[8'h69][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_163 = _RANDOM[8'h69][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_164 = _RANDOM[8'h69][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_165 = _RANDOM[8'h69][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_166 = _RANDOM[8'h69][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_167 = _RANDOM[8'h69][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_168 = _RANDOM[8'h69][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_169 = _RANDOM[8'h69][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_170 = _RANDOM[8'h69][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_171 = _RANDOM[8'h69][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_172 = _RANDOM[8'h69][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_173 = _RANDOM[8'h69][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_174 = _RANDOM[8'h69][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_175 = _RANDOM[8'h69][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_176 = _RANDOM[8'h69][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_177 = _RANDOM[8'h69][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_178 = _RANDOM[8'h69][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_179 = _RANDOM[8'h69][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_180 = _RANDOM[8'h69][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_181 = _RANDOM[8'h69][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_182 = _RANDOM[8'h69][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_183 = _RANDOM[8'h69][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_184 = _RANDOM[8'h69][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_185 = _RANDOM[8'h69][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_186 = _RANDOM[8'h69][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_187 = _RANDOM[8'h69][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_188 = _RANDOM[8'h69][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_189 = _RANDOM[8'h69][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_190 = _RANDOM[8'h69][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_191 = _RANDOM[8'h6A][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_192 = _RANDOM[8'h6A][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_193 = _RANDOM[8'h6A][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_194 = _RANDOM[8'h6A][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_195 = _RANDOM[8'h6A][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_196 = _RANDOM[8'h6A][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_197 = _RANDOM[8'h6A][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_198 = _RANDOM[8'h6A][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_199 = _RANDOM[8'h6A][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_200 = _RANDOM[8'h6A][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_201 = _RANDOM[8'h6A][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_202 = _RANDOM[8'h6A][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_203 = _RANDOM[8'h6A][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_204 = _RANDOM[8'h6A][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_205 = _RANDOM[8'h6A][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_206 = _RANDOM[8'h6A][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_207 = _RANDOM[8'h6A][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_208 = _RANDOM[8'h6A][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_209 = _RANDOM[8'h6A][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_210 = _RANDOM[8'h6A][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_211 = _RANDOM[8'h6A][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_212 = _RANDOM[8'h6A][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_213 = _RANDOM[8'h6A][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_214 = _RANDOM[8'h6A][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_215 = _RANDOM[8'h6A][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_216 = _RANDOM[8'h6A][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_217 = _RANDOM[8'h6A][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_218 = _RANDOM[8'h6A][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_219 = _RANDOM[8'h6A][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_220 = _RANDOM[8'h6A][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_221 = _RANDOM[8'h6A][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_222 = _RANDOM[8'h6A][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_223 = _RANDOM[8'h6B][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_224 = _RANDOM[8'h6B][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_225 = _RANDOM[8'h6B][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_226 = _RANDOM[8'h6B][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_227 = _RANDOM[8'h6B][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_228 = _RANDOM[8'h6B][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_229 = _RANDOM[8'h6B][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_230 = _RANDOM[8'h6B][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_231 = _RANDOM[8'h6B][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_232 = _RANDOM[8'h6B][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_233 = _RANDOM[8'h6B][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_234 = _RANDOM[8'h6B][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_235 = _RANDOM[8'h6B][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_236 = _RANDOM[8'h6B][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_237 = _RANDOM[8'h6B][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_238 = _RANDOM[8'h6B][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_239 = _RANDOM[8'h6B][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_240 = _RANDOM[8'h6B][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_241 = _RANDOM[8'h6B][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_242 = _RANDOM[8'h6B][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_243 = _RANDOM[8'h6B][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_244 = _RANDOM[8'h6B][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_245 = _RANDOM[8'h6B][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_246 = _RANDOM[8'h6B][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_247 = _RANDOM[8'h6B][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_248 = _RANDOM[8'h6B][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_249 = _RANDOM[8'h6B][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_250 = _RANDOM[8'h6B][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_251 = _RANDOM[8'h6B][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_252 = _RANDOM[8'h6B][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_253 = _RANDOM[8'h6B][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_254 = _RANDOM[8'h6B][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + ghv_255 = _RANDOM[8'h6C][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20 + s0_ghist_ptr_reg_dup_0_flag = _RANDOM[8'h6C][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 + s0_ghist_ptr_reg_dup_0_value = _RANDOM[8'h6C][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 + s0_ghist_ptr_reg_dup_1_flag = _RANDOM[8'h6C][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 + s0_ghist_ptr_reg_dup_1_value = _RANDOM[8'h6C][18:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 + s0_ghist_ptr_reg_dup_2_flag = _RANDOM[8'h6C][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 + s0_ghist_ptr_reg_dup_2_value = _RANDOM[8'h6C][27:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 + s0_ghist_ptr_reg_dup_3_flag = _RANDOM[8'h6C][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 + s0_ghist_ptr_reg_dup_3_value = {_RANDOM[8'h6C][31:29], _RANDOM[8'h6D][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63 + s1_ghist_ptr_dup_0_flag = _RANDOM[8'h6D][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35 + s1_ghist_ptr_dup_0_value = _RANDOM[8'h6D][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35 + s1_ghist_ptr_dup_1_flag = _RANDOM[8'h6D][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35 + s1_ghist_ptr_dup_1_value = _RANDOM[8'h6D][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35 + s1_ghist_ptr_dup_2_flag = _RANDOM[8'h6D][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35 + s1_ghist_ptr_dup_2_value = _RANDOM[8'h6D][31:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35 + s1_ghist_ptr_dup_3_flag = _RANDOM[8'h6E][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 + s1_ghist_ptr_dup_3_value = _RANDOM[8'h6E][8:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 + s2_ghist_ptr_dup_0_flag = _RANDOM[8'h6E][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35 + s2_ghist_ptr_dup_0_value = _RANDOM[8'h6E][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35 + s2_ghist_ptr_dup_1_flag = _RANDOM[8'h6E][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35 + s2_ghist_ptr_dup_1_value = _RANDOM[8'h6E][26:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35 + s2_ghist_ptr_dup_2_flag = _RANDOM[8'h6E][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35 + s2_ghist_ptr_dup_2_value = {_RANDOM[8'h6E][31:28], _RANDOM[8'h6F][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35 + s2_ghist_ptr_dup_3_flag = _RANDOM[8'h6F][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 + s2_ghist_ptr_dup_3_value = _RANDOM[8'h6F][12:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 + s3_ghist_ptr_dup_0_flag = _RANDOM[8'h6F][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35 + s3_ghist_ptr_dup_0_value = _RANDOM[8'h6F][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35 + s3_ghist_ptr_dup_1_flag = _RANDOM[8'h6F][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35 + s3_ghist_ptr_dup_1_value = _RANDOM[8'h6F][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35 + s3_ghist_ptr_dup_2_flag = _RANDOM[8'h6F][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35 + s3_ghist_ptr_dup_2_value = _RANDOM[8'h70][7:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + s3_ghist_ptr_dup_3_flag = _RANDOM[8'h70][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + s3_ghist_ptr_dup_3_value = _RANDOM[8'h70][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + do_redirect_dup_3_valid = _RANDOM[8'h70][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, :350:40 + do_redirect_dup_3_bits_level = _RANDOM[8'h71][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_pc = + {_RANDOM[8'h71][31:9], _RANDOM[8'h72][15:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_pd_isRVC = _RANDOM[8'h72][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_pd_isCall = _RANDOM[8'h72][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_pd_isRet = _RANDOM[8'h72][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_ssp = _RANDOM[8'h72][25:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_sctr = _RANDOM[8'h72][27:26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSW_flag = _RANDOM[8'h72][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSW_value = + {_RANDOM[8'h72][31:29], _RANDOM[8'h73][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSR_flag = _RANDOM[8'h73][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSR_value = _RANDOM[8'h73][7:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_NOS_flag = _RANDOM[8'h73][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_NOS_value = _RANDOM[8'h73][13:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist = + _RANDOM[8'h74][31:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist = + _RANDOM[8'h75][10:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist = + _RANDOM[8'h75][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist = + _RANDOM[8'h75][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist = + {_RANDOM[8'h75][31:26], _RANDOM[8'h76][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist = + _RANDOM[8'h76][6:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist = + _RANDOM[8'h76][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist = + _RANDOM[8'h76][23:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist = + _RANDOM[8'h76][30:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist = + {_RANDOM[8'h76][31], _RANDOM[8'h77][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist = + _RANDOM[8'h77][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist = + _RANDOM[8'h77][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist = + _RANDOM[8'h77][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist = + {_RANDOM[8'h77][31:30], _RANDOM[8'h78][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist = + _RANDOM[8'h78][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist = + _RANDOM[8'h78][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist = + {_RANDOM[8'h78][31:22], _RANDOM[8'h79][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist = + _RANDOM[8'h79][8:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 = _RANDOM[8'h79][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 = _RANDOM[8'h79][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 = _RANDOM[8'h79][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3 = _RANDOM[8'h79][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 = _RANDOM[8'h79][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 = _RANDOM[8'h79][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2 = _RANDOM[8'h79][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 = _RANDOM[8'h79][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 = _RANDOM[8'h79][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 = _RANDOM[8'h79][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3 = _RANDOM[8'h79][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 = _RANDOM[8'h79][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 = _RANDOM[8'h79][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 = _RANDOM[8'h79][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3 = _RANDOM[8'h79][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 = _RANDOM[8'h79][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 = _RANDOM[8'h79][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 = _RANDOM[8'h79][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3 = _RANDOM[8'h79][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 = _RANDOM[8'h79][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 = _RANDOM[8'h79][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 = _RANDOM[8'h79][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3 = _RANDOM[8'h7A][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH = _RANDOM[8'h7A][3:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_histPtr_flag = _RANDOM[8'h7A][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_histPtr_value = _RANDOM[8'h7A][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_target = + {_RANDOM[8'h7B][31:9], _RANDOM[8'h7C][15:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_taken = _RANDOM[8'h7C][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + thisBrNumOH_dup_shiftAmount = _RANDOM[8'h7C][19:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_addIntoHist = _RANDOM[8'h7C][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + previous_s1_pred_info_hit_0 = _RANDOM[8'h7F][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_hit_1 = _RANDOM[8'h7F][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_hit_2 = _RANDOM[8'h7F][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_hit_3 = _RANDOM[8'h7F][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_target_0 = {_RANDOM[8'h7F][31:7], _RANDOM[8'h80][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_target_1 = {_RANDOM[8'h80][31:14], _RANDOM[8'h81][20:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_target_2 = {_RANDOM[8'h81][31:21], _RANDOM[8'h82][27:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_target_3 = + {_RANDOM[8'h82][31:28], _RANDOM[8'h83], _RANDOM[8'h84][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_lastBrPosOH_0_0 = _RANDOM[8'h84][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_lastBrPosOH_0_1 = _RANDOM[8'h84][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_lastBrPosOH_0_2 = _RANDOM[8'h84][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_lastBrPosOH_1_0 = _RANDOM[8'h84][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_lastBrPosOH_1_1 = _RANDOM[8'h84][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_lastBrPosOH_1_2 = _RANDOM[8'h84][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_lastBrPosOH_2_0 = _RANDOM[8'h84][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_lastBrPosOH_2_1 = _RANDOM[8'h84][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_lastBrPosOH_2_2 = _RANDOM[8'h84][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_lastBrPosOH_3_0 = _RANDOM[8'h84][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_lastBrPosOH_3_1 = _RANDOM[8'h84][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_lastBrPosOH_3_2 = _RANDOM[8'h84][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_taken_0 = _RANDOM[8'h84][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_taken_1 = _RANDOM[8'h84][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_taken_2 = _RANDOM[8'h84][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_taken_3 = _RANDOM[8'h84][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_takenMask_0_0 = _RANDOM[8'h84][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_takenMask_0_1 = _RANDOM[8'h84][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_takenMask_1_0 = _RANDOM[8'h84][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_takenMask_1_1 = _RANDOM[8'h84][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_takenMask_2_0 = _RANDOM[8'h84][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_takenMask_2_1 = _RANDOM[8'h84][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_takenMask_3_0 = _RANDOM[8'h84][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_takenMask_3_1 = _RANDOM[8'h84][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_cfiIndex_0 = _RANDOM[8'h84][30:27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_cfiIndex_1 = {_RANDOM[8'h84][31], _RANDOM[8'h85][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_cfiIndex_2 = _RANDOM[8'h85][6:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s1_pred_info_cfiIndex_3 = _RANDOM[8'h85][10:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40 + previous_s2_pred_pc_0 = {_RANDOM[8'h85][31:11], _RANDOM[8'h86][17:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40, :673:35 + previous_s2_pred_pc_1 = {_RANDOM[8'h86][31:18], _RANDOM[8'h87][24:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_pc_2 = {_RANDOM[8'h87][31:25], _RANDOM[8'h88]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_pc_3 = {_RANDOM[8'h89], _RANDOM[8'h8A][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_0_br_taken_mask_0 = _RANDOM[8'h8A][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_0_br_taken_mask_1 = _RANDOM[8'h8A][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_0_slot_valids_0 = _RANDOM[8'h8A][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_0_slot_valids_1 = _RANDOM[8'h8A][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_0_targets_0 = + {_RANDOM[8'h8A][31:26], _RANDOM[8'h8B], _RANDOM[8'h8C][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_0_targets_1 = + {_RANDOM[8'h8C][31:1], _RANDOM[8'h8D][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_0_fallThroughAddr = + {_RANDOM[8'h8E][31:23], _RANDOM[8'h8F][29:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_0_is_br_sharing = _RANDOM[8'h90][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_0_hit = _RANDOM[8'h90][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_1_br_taken_mask_0 = _RANDOM[8'h90][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_1_br_taken_mask_1 = _RANDOM[8'h90][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_1_slot_valids_0 = _RANDOM[8'h90][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_1_slot_valids_1 = _RANDOM[8'h90][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_1_targets_0 = + {_RANDOM[8'h90][31:10], _RANDOM[8'h91][16:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_1_targets_1 = + {_RANDOM[8'h91][31:17], _RANDOM[8'h92][23:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_1_fallThroughAddr = + {_RANDOM[8'h94][31:7], _RANDOM[8'h95][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_1_is_br_sharing = _RANDOM[8'h95][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_1_hit = _RANDOM[8'h95][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_2_br_taken_mask_0 = _RANDOM[8'h95][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_2_br_taken_mask_1 = _RANDOM[8'h95][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_2_slot_valids_0 = _RANDOM[8'h95][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_2_slot_valids_1 = _RANDOM[8'h95][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_2_targets_0 = + {_RANDOM[8'h95][31:26], _RANDOM[8'h96], _RANDOM[8'h97][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_2_targets_1 = + {_RANDOM[8'h97][31:1], _RANDOM[8'h98][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_2_fallThroughAddr = + {_RANDOM[8'h99][31:23], _RANDOM[8'h9A][29:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_2_is_br_sharing = _RANDOM[8'h9B][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_2_hit = _RANDOM[8'h9B][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_3_br_taken_mask_0 = _RANDOM[8'h9B][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_3_br_taken_mask_1 = _RANDOM[8'h9B][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_3_slot_valids_0 = _RANDOM[8'h9B][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_3_slot_valids_1 = _RANDOM[8'h9B][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_3_targets_0 = + {_RANDOM[8'h9B][31:10], _RANDOM[8'h9C][16:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_3_targets_1 = + {_RANDOM[8'h9C][31:17], _RANDOM[8'h9D][23:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_3_fallThroughAddr = + {_RANDOM[8'h9F][31:7], _RANDOM[8'hA0][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_3_is_br_sharing = _RANDOM[8'hA0][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + previous_s2_pred_full_pred_3_hit = _RANDOM[8'hA0][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35 + s2_ftq_idx_flag = _RANDOM[8'hA0][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35, :708:29 + s2_ftq_idx_value = _RANDOM[8'hA0][28:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35, :708:29 + s3_ftq_idx_flag = _RANDOM[8'hA0][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35, :709:29 + s3_ftq_idx_value = {_RANDOM[8'hA0][31:30], _RANDOM[8'hA1][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35, :709:29 + predictors_io_update_REG_valid = _RANDOM[8'hA1][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :709:29, :727:34 + predictors_io_update_REG_bits_pc = {_RANDOM[8'hA1][31:5], _RANDOM[8'hA2][11:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :709:29, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_17_folded_hist = + _RANDOM[8'hA2][22:12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_16_folded_hist = + {_RANDOM[8'hA2][31:23], _RANDOM[8'hA3][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_15_folded_hist = + _RANDOM[8'hA3][8:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_14_folded_hist = + _RANDOM[8'hA3][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_13_folded_hist = + _RANDOM[8'hA3][25:17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_12_folded_hist = + _RANDOM[8'hA3][29:26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_11_folded_hist = + {_RANDOM[8'hA3][31:30], _RANDOM[8'hA4][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_10_folded_hist = + _RANDOM[8'hA4][14:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_9_folded_hist = + _RANDOM[8'hA4][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_8_folded_hist = + _RANDOM[8'hA4][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_7_folded_hist = + {_RANDOM[8'hA4][31:30], _RANDOM[8'hA5][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_6_folded_hist = + _RANDOM[8'hA5][13:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_5_folded_hist = + _RANDOM[8'hA5][20:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_4_folded_hist = + _RANDOM[8'hA5][28:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_3_folded_hist = + {_RANDOM[8'hA5][31:29], _RANDOM[8'hA6][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_2_folded_hist = + _RANDOM[8'hA6][12:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_spec_info_folded_hist_hist_1_folded_hist = + _RANDOM[8'hA6][23:13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_valid = _RANDOM[8'hAA][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_brSlots_0_offset = _RANDOM[8'hAA][7:4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_brSlots_0_lower = _RANDOM[8'hAA][19:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_brSlots_0_tarStat = _RANDOM[8'hAA][21:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_brSlots_0_sharing = _RANDOM[8'hAA][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_brSlots_0_valid = _RANDOM[8'hAA][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_tailSlot_offset = _RANDOM[8'hAA][27:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_tailSlot_lower = + {_RANDOM[8'hAA][31:28], _RANDOM[8'hAB][15:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_tailSlot_tarStat = _RANDOM[8'hAB][17:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_tailSlot_sharing = _RANDOM[8'hAB][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_tailSlot_valid = _RANDOM[8'hAB][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_pftAddr = _RANDOM[8'hAB][23:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_carry = _RANDOM[8'hAB][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_isCall = _RANDOM[8'hAB][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_isRet = _RANDOM[8'hAB][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_isJalr = _RANDOM[8'hAB][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_last_may_be_rvi_call = _RANDOM[8'hAB][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_always_taken_0 = _RANDOM[8'hAB][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_ftb_entry_always_taken_1 = _RANDOM[8'hAB][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_cfi_idx_valid = _RANDOM[8'hAB][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_cfi_idx_bits = _RANDOM[8'hAC][3:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_br_taken_mask_0 = _RANDOM[8'hAC][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_br_taken_mask_1 = _RANDOM[8'hAC][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_jmp_taken = _RANDOM[8'hAC][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_mispred_mask_0 = _RANDOM[8'hAC][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_mispred_mask_1 = _RANDOM[8'hAC][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_mispred_mask_2 = _RANDOM[8'hAC][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_old_entry = _RANDOM[8'hAC][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_meta = + {_RANDOM[8'hAC][31:17], + _RANDOM[8'hAD], + _RANDOM[8'hAE], + _RANDOM[8'hAF], + _RANDOM[8'hB0], + _RANDOM[8'hB1], + _RANDOM[8'hB2], + _RANDOM[8'hB3][11:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + predictors_io_update_REG_bits_full_target = + {_RANDOM[8'hB3][31:12], _RANDOM[8'hB4][18:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + s1_valid_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65 + s2_valid_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65 + s3_valid_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65 + s0_folded_gh_reg_dup_1_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63 + s0_folded_gh_reg_dup_1_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_1_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_1_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63 + s0_folded_gh_reg_dup_2_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_2_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_2_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63 + s0_folded_gh_reg_dup_3_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s0_folded_gh_reg_dup_3_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84} + s0_folded_gh_reg_dup_3_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63 + s1_folded_gh_dup_1_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35 + s1_folded_gh_dup_1_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_1_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_1_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35 + s1_folded_gh_dup_2_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_2_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_2_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35 + s1_folded_gh_dup_3_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s1_folded_gh_dup_3_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35 + s1_folded_gh_dup_3_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35 + s2_folded_gh_dup_1_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35 + s2_folded_gh_dup_1_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_1_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_1_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35 + s2_folded_gh_dup_2_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_2_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_2_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35 + s2_folded_gh_dup_3_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s2_folded_gh_dup_3_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35 + s2_folded_gh_dup_3_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35 + s3_folded_gh_dup_1_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35 + s3_folded_gh_dup_1_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_1_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_1_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35 + s3_folded_gh_dup_2_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_2_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_2_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35 + s3_folded_gh_dup_3_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s3_folded_gh_dup_3_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35 + s3_folded_gh_dup_3_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + s0_last_br_num_oh_reg_dup_1 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76 + s0_last_br_num_oh_reg_dup_2 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76 + s0_last_br_num_oh_reg_dup_3 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76 + s1_last_br_num_oh_dup_1 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76} + s1_last_br_num_oh_dup_2 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76} + s1_last_br_num_oh_dup_3 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76} + s2_last_br_num_oh_dup_1 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40 + s2_last_br_num_oh_dup_2 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40 + s2_last_br_num_oh_dup_3 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40 + s3_last_br_num_oh_dup_1 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40 + s3_last_br_num_oh_dup_2 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40 + s3_last_br_num_oh_dup_3 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46 + ghv_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_4 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_5 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_6 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_7 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_8 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_9 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_10 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_11 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_12 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_13 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_14 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_15 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_16 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_17 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_18 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_19 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_20 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_21 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_22 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_23 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_24 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_25 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_26 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_27 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_28 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_29 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_30 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_31 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_32 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_33 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_34 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_35 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_36 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_37 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_38 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_39 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_40 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_41 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_42 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_43 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_44 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_45 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_46 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_47 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_48 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_49 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_50 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_51 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_52 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_53 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_54 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_55 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_56 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_57 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_58 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_59 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_60 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_61 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_62 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_63 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_64 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_65 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_66 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_67 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_68 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_69 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_70 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_71 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_72 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_73 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_74 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_75 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_76 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_77 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_78 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_79 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_80 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_81 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_82 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_83 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_84 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_85 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_86 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_87 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_88 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_89 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_90 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_91 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_92 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_93 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_94 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_95 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_96 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_97 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_98 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_99 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_100 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_101 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_102 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_103 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_104 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_105 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_106 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_107 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_108 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_109 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_110 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_111 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_112 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_113 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_114 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_115 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_116 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_117 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_118 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_119 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_120 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_121 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_122 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_123 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_124 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_125 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_126 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_127 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_128 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_129 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_130 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_131 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_132 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_133 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_134 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_135 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_136 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_137 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_138 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_139 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_140 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_141 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_142 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_143 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_144 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_145 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_146 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_147 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_148 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_149 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_150 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_151 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_152 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_153 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_154 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_155 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_156 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_157 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_158 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_159 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_160 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_161 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_162 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_163 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_164 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_165 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_166 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_167 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_168 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_169 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_170 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_171 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_172 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_173 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_174 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_175 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_176 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_177 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_178 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_179 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_180 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_181 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_182 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_183 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_184 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_185 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_186 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_187 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_188 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_189 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_190 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_191 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_192 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_193 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_194 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_195 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_196 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_197 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_198 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_199 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_200 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_201 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_202 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_203 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_204 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_205 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_206 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_207 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_208 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_209 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_210 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_211 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_212 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_213 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_214 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_215 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_216 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_217 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_218 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_219 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_220 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_221 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_222 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_223 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_224 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_225 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_226 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_227 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_228 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_229 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_230 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_231 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_232 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_233 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_234 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_235 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_236 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_237 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_238 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_239 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_240 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_241 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_242 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_243 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_244 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_245 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_246 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_247 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_248 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_249 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_250 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_251 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_252 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_253 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_254 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + ghv_255 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20 + s0_ghist_ptr_reg_dup_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 + s0_ghist_ptr_reg_dup_0_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 + s0_ghist_ptr_reg_dup_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 + s0_ghist_ptr_reg_dup_1_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 + s0_ghist_ptr_reg_dup_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 + s0_ghist_ptr_reg_dup_2_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 + s0_ghist_ptr_reg_dup_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63 + s0_ghist_ptr_reg_dup_3_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63 + s1_ghist_ptr_dup_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 + s1_ghist_ptr_dup_0_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 + s1_ghist_ptr_dup_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 + s1_ghist_ptr_dup_1_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 + s1_ghist_ptr_dup_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 + s1_ghist_ptr_dup_2_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 + s1_ghist_ptr_dup_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35 + s1_ghist_ptr_dup_3_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35 + s2_ghist_ptr_dup_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 + s2_ghist_ptr_dup_0_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 + s2_ghist_ptr_dup_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 + s2_ghist_ptr_dup_1_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 + s2_ghist_ptr_dup_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 + s2_ghist_ptr_dup_2_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 + s2_ghist_ptr_dup_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35 + s2_ghist_ptr_dup_3_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35 + s3_ghist_ptr_dup_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 + s3_ghist_ptr_dup_0_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + s3_ghist_ptr_dup_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 + s3_ghist_ptr_dup_1_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + s3_ghist_ptr_dup_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 + s3_ghist_ptr_dup_2_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + s3_ghist_ptr_dup_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35 + s3_ghist_ptr_dup_3_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + do_redirect_dup_3_valid = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_level = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_pc = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_pd_isRVC = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_pd_isCall = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_pd_isRet = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_ssp = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_sctr = 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSW_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSW_value = 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSR_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_TOSR_value = 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_NOS_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_NOS_value = 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40 + do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :350:40 + do_redirect_dup_3_bits_cfiUpdate_histPtr_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + do_redirect_dup_3_bits_cfiUpdate_histPtr_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40 + do_redirect_dup_3_bits_cfiUpdate_target = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_taken = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + thisBrNumOH_dup_shiftAmount = 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40 + do_redirect_dup_3_bits_cfiUpdate_addIntoHist = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40 + previous_s1_pred_info_hit_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_hit_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_hit_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_hit_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_target_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 + previous_s1_pred_info_target_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 + previous_s1_pred_info_target_2 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 + previous_s1_pred_info_target_3 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40 + previous_s1_pred_info_lastBrPosOH_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_0_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_0_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_1_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_1_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_2_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_2_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_3_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_lastBrPosOH_3_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_taken_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_taken_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_taken_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_taken_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_0_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_1_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_2_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_takenMask_3_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_cfiIndex_0 = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_cfiIndex_1 = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_cfiIndex_2 = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s1_pred_info_cfiIndex_3 = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40 + previous_s2_pred_pc_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_pc_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_pc_2 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_pc_3 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_0_br_taken_mask_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_0_br_taken_mask_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_0_slot_valids_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_0_slot_valids_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_0_targets_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_0_targets_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_0_fallThroughAddr = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_0_is_br_sharing = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_0_hit = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_1_br_taken_mask_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_1_br_taken_mask_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_1_slot_valids_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_1_slot_valids_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_1_targets_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_1_targets_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_1_fallThroughAddr = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_1_is_br_sharing = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_1_hit = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_2_br_taken_mask_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_2_br_taken_mask_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_2_slot_valids_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_2_slot_valids_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_2_targets_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_2_targets_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_2_fallThroughAddr = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_2_is_br_sharing = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_2_hit = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_3_br_taken_mask_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_3_br_taken_mask_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_3_slot_valids_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_3_slot_valids_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_3_targets_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_3_targets_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_3_fallThroughAddr = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35 + previous_s2_pred_full_pred_3_is_br_sharing = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + previous_s2_pred_full_pred_3_hit = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/BPU.scala:221:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + DelayN_1 ctrl_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + .clock (clock), + .io_in_ubtb_enable (io_ctrl_ubtb_enable), + .io_in_btb_enable (io_ctrl_btb_enable), + .io_in_tage_enable (io_ctrl_tage_enable), + .io_in_sc_enable (io_ctrl_sc_enable), + .io_in_ras_enable (io_ctrl_ras_enable), + .io_out_ubtb_enable (_ctrl_delay_io_out_ubtb_enable), + .io_out_btb_enable (_ctrl_delay_io_out_btb_enable), + .io_out_tage_enable (_ctrl_delay_io_out_tage_enable), + .io_out_sc_enable (_ctrl_delay_io_out_sc_enable), + .io_out_ras_enable (_ctrl_delay_io_out_ras_enable) + ); + Composer predictors ( // src/main/scala/xiangshan/frontend/BPU.scala:225:26 + .clock (clock), + .reset (reset), + .io_reset_vector (io_reset_vector), + .io_in_bits_s0_pc_0 (_s0_pc_dup_0_ppm_out_res), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_s0_pc_1 (_s0_pc_dup_1_ppm_out_res), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_s0_pc_2 (_s0_pc_dup_2_ppm_out_res), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_s0_pc_3 (_s0_pc_dup_3_ppm_out_res), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_1_hist_17_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_1_hist_16_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_1_hist_15_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_1_hist_14_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_1_hist_9_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_1_hist_8_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_1_hist_7_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_1_hist_5_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_1_hist_4_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_1_hist_3_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_1_hist_1_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_3_hist_14_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_3_hist_13_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_3_hist_12_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_3_hist_11_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_3_hist_10_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_3_hist_6_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_3_hist_4_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_3_hist_3_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_in_bits_folded_hist_3_hist_2_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .io_out_s1_pc_0 + (_predictors_io_out_s1_pc_0), + .io_out_s1_pc_1 + (_predictors_io_out_s1_pc_1), + .io_out_s1_pc_2 + (_predictors_io_out_s1_pc_2), + .io_out_s1_pc_3 + (_predictors_io_out_s1_pc_3), + .io_out_s1_full_pred_0_br_taken_mask_0 + (_predictors_io_out_s1_full_pred_0_br_taken_mask_0), + .io_out_s1_full_pred_0_br_taken_mask_1 + (_predictors_io_out_s1_full_pred_0_br_taken_mask_1), + .io_out_s1_full_pred_0_slot_valids_0 + (_predictors_io_out_s1_full_pred_0_slot_valids_0), + .io_out_s1_full_pred_0_slot_valids_1 + (_predictors_io_out_s1_full_pred_0_slot_valids_1), + .io_out_s1_full_pred_0_targets_0 + (_predictors_io_out_s1_full_pred_0_targets_0), + .io_out_s1_full_pred_0_targets_1 + (_predictors_io_out_s1_full_pred_0_targets_1), + .io_out_s1_full_pred_0_offsets_0 + (_predictors_io_out_s1_full_pred_0_offsets_0), + .io_out_s1_full_pred_0_offsets_1 + (_predictors_io_out_s1_full_pred_0_offsets_1), + .io_out_s1_full_pred_0_fallThroughAddr + (_predictors_io_out_s1_full_pred_0_fallThroughAddr), + .io_out_s1_full_pred_0_is_br_sharing + (_predictors_io_out_s1_full_pred_0_is_br_sharing), + .io_out_s1_full_pred_0_hit + (_predictors_io_out_s1_full_pred_0_hit), + .io_out_s1_full_pred_1_br_taken_mask_0 + (_predictors_io_out_s1_full_pred_1_br_taken_mask_0), + .io_out_s1_full_pred_1_br_taken_mask_1 + (_predictors_io_out_s1_full_pred_1_br_taken_mask_1), + .io_out_s1_full_pred_1_slot_valids_0 + (_predictors_io_out_s1_full_pred_1_slot_valids_0), + .io_out_s1_full_pred_1_slot_valids_1 + (_predictors_io_out_s1_full_pred_1_slot_valids_1), + .io_out_s1_full_pred_1_targets_0 + (_predictors_io_out_s1_full_pred_1_targets_0), + .io_out_s1_full_pred_1_targets_1 + (_predictors_io_out_s1_full_pred_1_targets_1), + .io_out_s1_full_pred_1_offsets_0 + (_predictors_io_out_s1_full_pred_1_offsets_0), + .io_out_s1_full_pred_1_offsets_1 + (_predictors_io_out_s1_full_pred_1_offsets_1), + .io_out_s1_full_pred_1_fallThroughAddr + (_predictors_io_out_s1_full_pred_1_fallThroughAddr), + .io_out_s1_full_pred_1_is_br_sharing + (_predictors_io_out_s1_full_pred_1_is_br_sharing), + .io_out_s1_full_pred_1_hit + (_predictors_io_out_s1_full_pred_1_hit), + .io_out_s1_full_pred_2_br_taken_mask_0 + (_predictors_io_out_s1_full_pred_2_br_taken_mask_0), + .io_out_s1_full_pred_2_br_taken_mask_1 + (_predictors_io_out_s1_full_pred_2_br_taken_mask_1), + .io_out_s1_full_pred_2_slot_valids_0 + (_predictors_io_out_s1_full_pred_2_slot_valids_0), + .io_out_s1_full_pred_2_slot_valids_1 + (_predictors_io_out_s1_full_pred_2_slot_valids_1), + .io_out_s1_full_pred_2_targets_0 + (_predictors_io_out_s1_full_pred_2_targets_0), + .io_out_s1_full_pred_2_targets_1 + (_predictors_io_out_s1_full_pred_2_targets_1), + .io_out_s1_full_pred_2_offsets_0 + (_predictors_io_out_s1_full_pred_2_offsets_0), + .io_out_s1_full_pred_2_offsets_1 + (_predictors_io_out_s1_full_pred_2_offsets_1), + .io_out_s1_full_pred_2_fallThroughAddr + (_predictors_io_out_s1_full_pred_2_fallThroughAddr), + .io_out_s1_full_pred_2_is_br_sharing + (_predictors_io_out_s1_full_pred_2_is_br_sharing), + .io_out_s1_full_pred_2_hit + (_predictors_io_out_s1_full_pred_2_hit), + .io_out_s1_full_pred_3_br_taken_mask_0 + (_predictors_io_out_s1_full_pred_3_br_taken_mask_0), + .io_out_s1_full_pred_3_br_taken_mask_1 + (_predictors_io_out_s1_full_pred_3_br_taken_mask_1), + .io_out_s1_full_pred_3_slot_valids_0 + (_predictors_io_out_s1_full_pred_3_slot_valids_0), + .io_out_s1_full_pred_3_slot_valids_1 + (_predictors_io_out_s1_full_pred_3_slot_valids_1), + .io_out_s1_full_pred_3_targets_0 + (_predictors_io_out_s1_full_pred_3_targets_0), + .io_out_s1_full_pred_3_targets_1 + (_predictors_io_out_s1_full_pred_3_targets_1), + .io_out_s1_full_pred_3_offsets_0 + (_predictors_io_out_s1_full_pred_3_offsets_0), + .io_out_s1_full_pred_3_offsets_1 + (_predictors_io_out_s1_full_pred_3_offsets_1), + .io_out_s1_full_pred_3_fallThroughAddr + (_predictors_io_out_s1_full_pred_3_fallThroughAddr), + .io_out_s1_full_pred_3_fallThroughErr + (io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughErr), + .io_out_s1_full_pred_3_is_br_sharing + (_predictors_io_out_s1_full_pred_3_is_br_sharing), + .io_out_s1_full_pred_3_hit + (_predictors_io_out_s1_full_pred_3_hit), + .io_out_s2_pc_0 + (_predictors_io_out_s2_pc_0), + .io_out_s2_pc_1 + (_predictors_io_out_s2_pc_1), + .io_out_s2_pc_2 + (_predictors_io_out_s2_pc_2), + .io_out_s2_pc_3 + (_predictors_io_out_s2_pc_3), + .io_out_s2_full_pred_0_br_taken_mask_0 + (_predictors_io_out_s2_full_pred_0_br_taken_mask_0), + .io_out_s2_full_pred_0_br_taken_mask_1 + (_predictors_io_out_s2_full_pred_0_br_taken_mask_1), + .io_out_s2_full_pred_0_slot_valids_0 + (_predictors_io_out_s2_full_pred_0_slot_valids_0), + .io_out_s2_full_pred_0_slot_valids_1 + (_predictors_io_out_s2_full_pred_0_slot_valids_1), + .io_out_s2_full_pred_0_targets_0 + (_predictors_io_out_s2_full_pred_0_targets_0), + .io_out_s2_full_pred_0_targets_1 + (_predictors_io_out_s2_full_pred_0_targets_1), + .io_out_s2_full_pred_0_offsets_0 + (_predictors_io_out_s2_full_pred_0_offsets_0), + .io_out_s2_full_pred_0_offsets_1 + (_predictors_io_out_s2_full_pred_0_offsets_1), + .io_out_s2_full_pred_0_fallThroughAddr + (_predictors_io_out_s2_full_pred_0_fallThroughAddr), + .io_out_s2_full_pred_0_is_br_sharing + (_predictors_io_out_s2_full_pred_0_is_br_sharing), + .io_out_s2_full_pred_0_hit + (_predictors_io_out_s2_full_pred_0_hit), + .io_out_s2_full_pred_1_br_taken_mask_0 + (_predictors_io_out_s2_full_pred_1_br_taken_mask_0), + .io_out_s2_full_pred_1_br_taken_mask_1 + (_predictors_io_out_s2_full_pred_1_br_taken_mask_1), + .io_out_s2_full_pred_1_slot_valids_0 + (_predictors_io_out_s2_full_pred_1_slot_valids_0), + .io_out_s2_full_pred_1_slot_valids_1 + (_predictors_io_out_s2_full_pred_1_slot_valids_1), + .io_out_s2_full_pred_1_targets_0 + (_predictors_io_out_s2_full_pred_1_targets_0), + .io_out_s2_full_pred_1_targets_1 + (_predictors_io_out_s2_full_pred_1_targets_1), + .io_out_s2_full_pred_1_offsets_0 + (_predictors_io_out_s2_full_pred_1_offsets_0), + .io_out_s2_full_pred_1_offsets_1 + (_predictors_io_out_s2_full_pred_1_offsets_1), + .io_out_s2_full_pred_1_fallThroughAddr + (_predictors_io_out_s2_full_pred_1_fallThroughAddr), + .io_out_s2_full_pred_1_is_br_sharing + (_predictors_io_out_s2_full_pred_1_is_br_sharing), + .io_out_s2_full_pred_1_hit + (_predictors_io_out_s2_full_pred_1_hit), + .io_out_s2_full_pred_2_br_taken_mask_0 + (_predictors_io_out_s2_full_pred_2_br_taken_mask_0), + .io_out_s2_full_pred_2_br_taken_mask_1 + (_predictors_io_out_s2_full_pred_2_br_taken_mask_1), + .io_out_s2_full_pred_2_slot_valids_0 + (_predictors_io_out_s2_full_pred_2_slot_valids_0), + .io_out_s2_full_pred_2_slot_valids_1 + (_predictors_io_out_s2_full_pred_2_slot_valids_1), + .io_out_s2_full_pred_2_targets_0 + (_predictors_io_out_s2_full_pred_2_targets_0), + .io_out_s2_full_pred_2_targets_1 + (_predictors_io_out_s2_full_pred_2_targets_1), + .io_out_s2_full_pred_2_offsets_0 + (_predictors_io_out_s2_full_pred_2_offsets_0), + .io_out_s2_full_pred_2_offsets_1 + (_predictors_io_out_s2_full_pred_2_offsets_1), + .io_out_s2_full_pred_2_fallThroughAddr + (_predictors_io_out_s2_full_pred_2_fallThroughAddr), + .io_out_s2_full_pred_2_is_br_sharing + (_predictors_io_out_s2_full_pred_2_is_br_sharing), + .io_out_s2_full_pred_2_hit + (_predictors_io_out_s2_full_pred_2_hit), + .io_out_s2_full_pred_3_br_taken_mask_0 + (_predictors_io_out_s2_full_pred_3_br_taken_mask_0), + .io_out_s2_full_pred_3_br_taken_mask_1 + (_predictors_io_out_s2_full_pred_3_br_taken_mask_1), + .io_out_s2_full_pred_3_slot_valids_0 + (_predictors_io_out_s2_full_pred_3_slot_valids_0), + .io_out_s2_full_pred_3_slot_valids_1 + (_predictors_io_out_s2_full_pred_3_slot_valids_1), + .io_out_s2_full_pred_3_targets_0 + (_predictors_io_out_s2_full_pred_3_targets_0), + .io_out_s2_full_pred_3_targets_1 + (_predictors_io_out_s2_full_pred_3_targets_1), + .io_out_s2_full_pred_3_offsets_0 + (_predictors_io_out_s2_full_pred_3_offsets_0), + .io_out_s2_full_pred_3_offsets_1 + (_predictors_io_out_s2_full_pred_3_offsets_1), + .io_out_s2_full_pred_3_fallThroughAddr + (_predictors_io_out_s2_full_pred_3_fallThroughAddr), + .io_out_s2_full_pred_3_fallThroughErr + (io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughErr), + .io_out_s2_full_pred_3_is_br_sharing + (_predictors_io_out_s2_full_pred_3_is_br_sharing), + .io_out_s2_full_pred_3_hit + (_predictors_io_out_s2_full_pred_3_hit), + .io_out_s3_pc_0 + (_predictors_io_out_s3_pc_0), + .io_out_s3_pc_1 + (_predictors_io_out_s3_pc_1), + .io_out_s3_pc_2 + (_predictors_io_out_s3_pc_2), + .io_out_s3_pc_3 + (_predictors_io_out_s3_pc_3), + .io_out_s3_full_pred_0_br_taken_mask_0 + (_predictors_io_out_s3_full_pred_0_br_taken_mask_0), + .io_out_s3_full_pred_0_br_taken_mask_1 + (_predictors_io_out_s3_full_pred_0_br_taken_mask_1), + .io_out_s3_full_pred_0_slot_valids_0 + (_predictors_io_out_s3_full_pred_0_slot_valids_0), + .io_out_s3_full_pred_0_slot_valids_1 + (_predictors_io_out_s3_full_pred_0_slot_valids_1), + .io_out_s3_full_pred_0_targets_0 + (_predictors_io_out_s3_full_pred_0_targets_0), + .io_out_s3_full_pred_0_targets_1 + (_predictors_io_out_s3_full_pred_0_targets_1), + .io_out_s3_full_pred_0_fallThroughAddr + (_predictors_io_out_s3_full_pred_0_fallThroughAddr), + .io_out_s3_full_pred_0_fallThroughErr + (_predictors_io_out_s3_full_pred_0_fallThroughErr), + .io_out_s3_full_pred_0_is_br_sharing + (_predictors_io_out_s3_full_pred_0_is_br_sharing), + .io_out_s3_full_pred_0_hit + (_predictors_io_out_s3_full_pred_0_hit), + .io_out_s3_full_pred_1_br_taken_mask_0 + (_predictors_io_out_s3_full_pred_1_br_taken_mask_0), + .io_out_s3_full_pred_1_br_taken_mask_1 + (_predictors_io_out_s3_full_pred_1_br_taken_mask_1), + .io_out_s3_full_pred_1_slot_valids_0 + (_predictors_io_out_s3_full_pred_1_slot_valids_0), + .io_out_s3_full_pred_1_slot_valids_1 + (_predictors_io_out_s3_full_pred_1_slot_valids_1), + .io_out_s3_full_pred_1_targets_0 + (_predictors_io_out_s3_full_pred_1_targets_0), + .io_out_s3_full_pred_1_targets_1 + (_predictors_io_out_s3_full_pred_1_targets_1), + .io_out_s3_full_pred_1_fallThroughAddr + (_predictors_io_out_s3_full_pred_1_fallThroughAddr), + .io_out_s3_full_pred_1_fallThroughErr + (_predictors_io_out_s3_full_pred_1_fallThroughErr), + .io_out_s3_full_pred_1_is_br_sharing + (_predictors_io_out_s3_full_pred_1_is_br_sharing), + .io_out_s3_full_pred_1_hit + (_predictors_io_out_s3_full_pred_1_hit), + .io_out_s3_full_pred_2_br_taken_mask_0 + (_predictors_io_out_s3_full_pred_2_br_taken_mask_0), + .io_out_s3_full_pred_2_br_taken_mask_1 + (_predictors_io_out_s3_full_pred_2_br_taken_mask_1), + .io_out_s3_full_pred_2_slot_valids_0 + (_predictors_io_out_s3_full_pred_2_slot_valids_0), + .io_out_s3_full_pred_2_slot_valids_1 + (_predictors_io_out_s3_full_pred_2_slot_valids_1), + .io_out_s3_full_pred_2_targets_0 + (_predictors_io_out_s3_full_pred_2_targets_0), + .io_out_s3_full_pred_2_targets_1 + (_predictors_io_out_s3_full_pred_2_targets_1), + .io_out_s3_full_pred_2_fallThroughAddr + (_predictors_io_out_s3_full_pred_2_fallThroughAddr), + .io_out_s3_full_pred_2_fallThroughErr + (_predictors_io_out_s3_full_pred_2_fallThroughErr), + .io_out_s3_full_pred_2_is_br_sharing + (_predictors_io_out_s3_full_pred_2_is_br_sharing), + .io_out_s3_full_pred_2_hit + (_predictors_io_out_s3_full_pred_2_hit), + .io_out_s3_full_pred_3_br_taken_mask_0 + (_predictors_io_out_s3_full_pred_3_br_taken_mask_0), + .io_out_s3_full_pred_3_br_taken_mask_1 + (_predictors_io_out_s3_full_pred_3_br_taken_mask_1), + .io_out_s3_full_pred_3_slot_valids_0 + (_predictors_io_out_s3_full_pred_3_slot_valids_0), + .io_out_s3_full_pred_3_slot_valids_1 + (_predictors_io_out_s3_full_pred_3_slot_valids_1), + .io_out_s3_full_pred_3_targets_0 + (_predictors_io_out_s3_full_pred_3_targets_0), + .io_out_s3_full_pred_3_targets_1 + (_predictors_io_out_s3_full_pred_3_targets_1), + .io_out_s3_full_pred_3_offsets_0 + (io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_0), + .io_out_s3_full_pred_3_offsets_1 + (io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_1), + .io_out_s3_full_pred_3_fallThroughAddr + (_predictors_io_out_s3_full_pred_3_fallThroughAddr), + .io_out_s3_full_pred_3_fallThroughErr + (_predictors_io_out_s3_full_pred_3_fallThroughErr), + .io_out_s3_full_pred_3_is_br_sharing + (_predictors_io_out_s3_full_pred_3_is_br_sharing), + .io_out_s3_full_pred_3_hit + (_predictors_io_out_s3_full_pred_3_hit), + .io_out_last_stage_meta + (io_bpu_to_ftq_resp_bits_last_stage_meta), + .io_out_last_stage_spec_info_ssp + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_ssp), + .io_out_last_stage_spec_info_sctr + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_sctr), + .io_out_last_stage_spec_info_TOSW_flag + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_flag), + .io_out_last_stage_spec_info_TOSW_value + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_value), + .io_out_last_stage_spec_info_TOSR_flag + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_flag), + .io_out_last_stage_spec_info_TOSR_value + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_value), + .io_out_last_stage_spec_info_NOS_flag + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_flag), + .io_out_last_stage_spec_info_NOS_value + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_value), + .io_out_last_stage_spec_info_topAddr + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_topAddr), + .io_out_last_stage_ftb_entry_valid + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_valid), + .io_out_last_stage_ftb_entry_brSlots_0_offset + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_offset), + .io_out_last_stage_ftb_entry_brSlots_0_lower + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_lower), + .io_out_last_stage_ftb_entry_brSlots_0_tarStat + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_tarStat), + .io_out_last_stage_ftb_entry_brSlots_0_sharing + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_sharing), + .io_out_last_stage_ftb_entry_brSlots_0_valid + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_valid), + .io_out_last_stage_ftb_entry_tailSlot_offset + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_offset), + .io_out_last_stage_ftb_entry_tailSlot_lower + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_lower), + .io_out_last_stage_ftb_entry_tailSlot_tarStat + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_tarStat), + .io_out_last_stage_ftb_entry_tailSlot_sharing + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_sharing), + .io_out_last_stage_ftb_entry_tailSlot_valid + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_valid), + .io_out_last_stage_ftb_entry_pftAddr + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_pftAddr), + .io_out_last_stage_ftb_entry_carry + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_carry), + .io_out_last_stage_ftb_entry_isCall + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isCall), + .io_out_last_stage_ftb_entry_isRet + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isRet), + .io_out_last_stage_ftb_entry_isJalr + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isJalr), + .io_out_last_stage_ftb_entry_last_may_be_rvi_call + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_last_may_be_rvi_call), + .io_out_last_stage_ftb_entry_always_taken_0 + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_0), + .io_out_last_stage_ftb_entry_always_taken_1 + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_1), + .io_ctrl_ubtb_enable + (_ctrl_delay_io_out_ubtb_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + .io_ctrl_btb_enable + (_ctrl_delay_io_out_btb_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + .io_ctrl_tage_enable + (_ctrl_delay_io_out_tage_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + .io_ctrl_sc_enable + (_ctrl_delay_io_out_sc_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + .io_ctrl_ras_enable + (_ctrl_delay_io_out_ras_enable), // utility/src/main/scala/utility/Hold.scala:97:23 + .io_s0_fire_0 (s0_fire_dup_0), // src/main/scala/xiangshan/frontend/BPU.scala:367:36 + .io_s0_fire_1 (s0_fire_dup_1), // src/main/scala/xiangshan/frontend/BPU.scala:367:36 + .io_s0_fire_2 (s0_fire_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:367:36 + .io_s0_fire_3 (s0_fire_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:367:36 + .io_s1_fire_0 (s1_fire_dup_0), // src/main/scala/xiangshan/frontend/BPU.scala:374:60 + .io_s1_fire_1 (s1_fire_dup_1), // src/main/scala/xiangshan/frontend/BPU.scala:374:60 + .io_s1_fire_2 (s1_fire_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:374:60 + .io_s1_fire_3 (s1_fire_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:374:60 + .io_s2_fire_0 (s2_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65 + .io_s2_fire_1 (s2_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65 + .io_s2_fire_2 (s2_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65 + .io_s2_fire_3 (s2_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65 + .io_s3_fire_2 (s3_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65 + .io_s3_redirect_2 (s3_redirect_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:684:28 + .io_s1_ready (_predictors_io_s1_ready), + .io_update_valid + (predictors_io_update_REG_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_pc + (predictors_io_update_REG_bits_pc), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_17_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_16_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_15_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_14_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_13_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_12_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_11_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_10_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_9_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_8_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_7_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_6_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_5_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_4_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_3_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_2_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_spec_info_folded_hist_hist_1_folded_hist + (predictors_io_update_REG_bits_spec_info_folded_hist_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_valid + (predictors_io_update_REG_bits_ftb_entry_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_brSlots_0_offset + (predictors_io_update_REG_bits_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_brSlots_0_lower + (predictors_io_update_REG_bits_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_brSlots_0_tarStat + (predictors_io_update_REG_bits_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_brSlots_0_sharing + (predictors_io_update_REG_bits_ftb_entry_brSlots_0_sharing), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_brSlots_0_valid + (predictors_io_update_REG_bits_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_tailSlot_offset + (predictors_io_update_REG_bits_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_tailSlot_lower + (predictors_io_update_REG_bits_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_tailSlot_tarStat + (predictors_io_update_REG_bits_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_tailSlot_sharing + (predictors_io_update_REG_bits_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_tailSlot_valid + (predictors_io_update_REG_bits_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_pftAddr + (predictors_io_update_REG_bits_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_carry + (predictors_io_update_REG_bits_ftb_entry_carry), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_isCall + (predictors_io_update_REG_bits_ftb_entry_isCall), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_isRet + (predictors_io_update_REG_bits_ftb_entry_isRet), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_isJalr + (predictors_io_update_REG_bits_ftb_entry_isJalr), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_last_may_be_rvi_call + (predictors_io_update_REG_bits_ftb_entry_last_may_be_rvi_call), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_always_taken_0 + (predictors_io_update_REG_bits_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_ftb_entry_always_taken_1 + (predictors_io_update_REG_bits_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_cfi_idx_valid + (predictors_io_update_REG_bits_cfi_idx_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_cfi_idx_bits + (predictors_io_update_REG_bits_cfi_idx_bits), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_br_taken_mask_0 + (predictors_io_update_REG_bits_br_taken_mask_0), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_br_taken_mask_1 + (predictors_io_update_REG_bits_br_taken_mask_1), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_jmp_taken + (predictors_io_update_REG_bits_jmp_taken), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_mispred_mask_0 + (predictors_io_update_REG_bits_mispred_mask_0), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_mispred_mask_1 + (predictors_io_update_REG_bits_mispred_mask_1), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_mispred_mask_2 + (predictors_io_update_REG_bits_mispred_mask_2), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_old_entry + (predictors_io_update_REG_bits_old_entry), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_meta + (predictors_io_update_REG_bits_meta), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_update_bits_full_target + (predictors_io_update_REG_bits_full_target), // src/main/scala/xiangshan/frontend/BPU.scala:727:34 + .io_redirect_valid (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .io_redirect_bits_level + (do_redirect_dup_3_bits_level), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .io_redirect_bits_cfiUpdate_pc + (do_redirect_dup_3_bits_cfiUpdate_pc), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .io_redirect_bits_cfiUpdate_pd_isRVC + (do_redirect_dup_3_bits_cfiUpdate_pd_isRVC), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .io_redirect_bits_cfiUpdate_pd_isCall + (do_redirect_dup_3_bits_cfiUpdate_pd_isCall), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .io_redirect_bits_cfiUpdate_pd_isRet + (do_redirect_dup_3_bits_cfiUpdate_pd_isRet), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .io_redirect_bits_cfiUpdate_ssp + (do_redirect_dup_3_bits_cfiUpdate_ssp), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .io_redirect_bits_cfiUpdate_sctr + (do_redirect_dup_3_bits_cfiUpdate_sctr), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .io_redirect_bits_cfiUpdate_TOSW_flag + (do_redirect_dup_3_bits_cfiUpdate_TOSW_flag), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .io_redirect_bits_cfiUpdate_TOSW_value + (do_redirect_dup_3_bits_cfiUpdate_TOSW_value), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .io_redirect_bits_cfiUpdate_TOSR_flag + (do_redirect_dup_3_bits_cfiUpdate_TOSR_flag), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .io_redirect_bits_cfiUpdate_TOSR_value + (do_redirect_dup_3_bits_cfiUpdate_TOSR_value), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .io_redirect_bits_cfiUpdate_NOS_flag + (do_redirect_dup_3_bits_cfiUpdate_NOS_flag), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .io_redirect_bits_cfiUpdate_NOS_value + (do_redirect_dup_3_bits_cfiUpdate_NOS_value) // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + ); + DelayN_2 reset_vector_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + .clock (clock), + .io_in (io_reset_vector), + .io_out (_reset_vector_delay_io_out) + ); + PriorityMuxModule s0_pc_dup_0_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_target_sel + (s2_redirect_dup_0 & ~s3_redirect_dup_0 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_target_src + ((_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + ? _predictors_io_out_s2_full_pred_0_targets_0 + : 39'h0) + | (~_selVecOH_T_66 & _GEN_21 & _predictors_io_out_s2_full_pred_0_hit + ? _predictors_io_out_s2_full_pred_0_targets_1 + : 39'h0) + | ({_GEN_21, _selVecOH_T_66} == 2'h0 & _predictors_io_out_s2_full_pred_0_hit + ? _predictors_io_out_s2_full_pred_0_fallThroughAddr + : 39'h0) + | (_predictors_io_out_s2_full_pred_0_hit + ? 39'h0 + : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_0_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 + .s1_target_sel + (s1_valid_dup_3 & ~s2_redirect_dup_0 & ~s3_redirect_dup_0 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_target_src + ((_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_targets_0 + : 39'h0) + | (~_cfiIndex_bits_WIRE_18_0 & s1_pred_info_takenMask_0_1 + & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_targets_1 + : 39'h0) + | ({s1_pred_info_takenMask_0_1, _cfiIndex_bits_WIRE_18_0} == 2'h0 + & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_fallThroughAddr + : 39'h0) | _GEN_4), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 + .s3_target_sel (s3_redirect_dup_0 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_target_src + ((_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + ? _predictors_io_out_s3_full_pred_0_targets_0 + : 39'h0) + | (~_selVecOH_T_98 & _GEN_32 & _predictors_io_out_s3_full_pred_0_hit + ? _predictors_io_out_s3_full_pred_0_targets_1 + : 39'h0) + | ({_GEN_32, _selVecOH_T_98} == 2'h0 & _predictors_io_out_s3_full_pred_0_hit + ? _predictors_io_out_s3_full_pred_0_fallThroughAddr + : 39'h0) + | (_predictors_io_out_s3_full_pred_0_hit + ? 39'h0 + : _s3_redirect_on_target_dup_WIRE_1_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 + .redirect_target_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_target_src (do_redirect_dup_3_bits_cfiUpdate_target), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .stallPC_src (s0_pc_reg_dup_0), // src/main/scala/xiangshan/frontend/BPU.scala:276:49 + .out_res (_s0_pc_dup_0_ppm_out_res) + ); + PriorityMuxModule s0_pc_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_target_sel + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_target_src + ((_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit + ? _predictors_io_out_s2_full_pred_1_targets_0 + : 39'h0) + | (~_selVecOH_T_74 & _GEN_22 & _predictors_io_out_s2_full_pred_1_hit + ? _predictors_io_out_s2_full_pred_1_targets_1 + : 39'h0) + | ({_GEN_22, _selVecOH_T_74} == 2'h0 & _predictors_io_out_s2_full_pred_1_hit + ? _predictors_io_out_s2_full_pred_1_fallThroughAddr + : 39'h0) + | (_predictors_io_out_s2_full_pred_1_hit + ? 39'h0 + : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_1_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 + .s1_target_sel + (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_target_src + ((_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_targets_0 + : 39'h0) + | (~_cfiIndex_bits_WIRE_22_0 & s1_pred_info_takenMask_1_1 + & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_targets_1 + : 39'h0) + | ({s1_pred_info_takenMask_1_1, _cfiIndex_bits_WIRE_22_0} == 2'h0 + & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_fallThroughAddr + : 39'h0) | _GEN_5), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 + .s3_target_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_target_src + ((_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit + ? _predictors_io_out_s3_full_pred_1_targets_0 + : 39'h0) + | (~_selVecOH_T_106 & _GEN_33 & _predictors_io_out_s3_full_pred_1_hit + ? _predictors_io_out_s3_full_pred_1_targets_1 + : 39'h0) + | ({_GEN_33, _selVecOH_T_106} == 2'h0 & _predictors_io_out_s3_full_pred_1_hit + ? _predictors_io_out_s3_full_pred_1_fallThroughAddr + : 39'h0) + | (_predictors_io_out_s3_full_pred_1_hit + ? 39'h0 + : _s3_redirect_on_target_dup_WIRE_4_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 + .redirect_target_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_target_src (do_redirect_dup_3_bits_cfiUpdate_target), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .stallPC_src (s0_pc_reg_dup_1), // src/main/scala/xiangshan/frontend/BPU.scala:276:49 + .out_res (_s0_pc_dup_1_ppm_out_res) + ); + PriorityMuxModule s0_pc_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_target_sel + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_target_src + ((_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit + ? _predictors_io_out_s2_full_pred_2_targets_0 + : 39'h0) + | (~_selVecOH_T_82 & _GEN_23 & _predictors_io_out_s2_full_pred_2_hit + ? _predictors_io_out_s2_full_pred_2_targets_1 + : 39'h0) + | ({_GEN_23, _selVecOH_T_82} == 2'h0 & _predictors_io_out_s2_full_pred_2_hit + ? _predictors_io_out_s2_full_pred_2_fallThroughAddr + : 39'h0) + | (_predictors_io_out_s2_full_pred_2_hit + ? 39'h0 + : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_2_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 + .s1_target_sel + (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_target_src + ((_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_targets_0 + : 39'h0) + | (~_cfiIndex_bits_WIRE_26_0 & s1_pred_info_takenMask_2_1 + & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_targets_1 + : 39'h0) + | ({s1_pred_info_takenMask_2_1, _cfiIndex_bits_WIRE_26_0} == 2'h0 + & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_fallThroughAddr + : 39'h0) | _GEN_6), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 + .s3_target_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_target_src + ((_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit + ? _predictors_io_out_s3_full_pred_2_targets_0 + : 39'h0) + | (~_selVecOH_T_114 & _GEN_34 & _predictors_io_out_s3_full_pred_2_hit + ? _predictors_io_out_s3_full_pred_2_targets_1 + : 39'h0) + | ({_GEN_34, _selVecOH_T_114} == 2'h0 & _predictors_io_out_s3_full_pred_2_hit + ? _predictors_io_out_s3_full_pred_2_fallThroughAddr + : 39'h0) + | (_predictors_io_out_s3_full_pred_2_hit + ? 39'h0 + : _s3_redirect_on_target_dup_WIRE_7_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 + .redirect_target_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_target_src (do_redirect_dup_3_bits_cfiUpdate_target), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .stallPC_src (s0_pc_reg_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:276:49 + .out_res (_s0_pc_dup_2_ppm_out_res) + ); + PriorityMuxModule s0_pc_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_target_sel + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_target_src + ((_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit + ? _predictors_io_out_s2_full_pred_3_targets_0 + : 39'h0) + | (~_selVecOH_T_90 & _GEN_24 & _predictors_io_out_s2_full_pred_3_hit + ? _predictors_io_out_s2_full_pred_3_targets_1 + : 39'h0) + | ({_GEN_24, _selVecOH_T_90} == 2'h0 & _predictors_io_out_s2_full_pred_3_hit + ? _predictors_io_out_s2_full_pred_3_fallThroughAddr + : 39'h0) + | (_predictors_io_out_s2_full_pred_3_hit + ? 39'h0 + : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_3_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 + .s1_target_sel + (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_target_src + ((_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_targets_0 + : 39'h0) + | (~_cfiIndex_bits_WIRE_30_0 & s1_pred_info_takenMask_3_1 + & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_targets_1 + : 39'h0) + | ({s1_pred_info_takenMask_3_1, _cfiIndex_bits_WIRE_30_0} == 2'h0 + & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_fallThroughAddr + : 39'h0) | _GEN_7), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25 + .s3_target_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_target_src + ((_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit + ? _predictors_io_out_s3_full_pred_3_targets_0 + : 39'h0) + | (~_selVecOH_T_122 & _GEN_35 & _predictors_io_out_s3_full_pred_3_hit + ? _predictors_io_out_s3_full_pred_3_targets_1 + : 39'h0) + | ({_GEN_35, _selVecOH_T_122} == 2'h0 & _predictors_io_out_s3_full_pred_3_hit + ? _predictors_io_out_s3_full_pred_3_fallThroughAddr + : 39'h0) + | (_predictors_io_out_s3_full_pred_3_hit + ? 39'h0 + : _s3_redirect_on_target_dup_WIRE_10_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47 + .redirect_target_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_target_src (do_redirect_dup_3_bits_cfiUpdate_target), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .stallPC_src (s0_pc_reg_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:276:49 + .out_res (_s0_pc_dup_3_ppm_out_res) + ); + PriorityMuxModule_4 s0_folded_gh_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_FGH_sel + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_FGH_src_hist_17_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_17_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_17_folded_hist[9], + s2_folded_gh_dup_1_hist_17_folded_hist[8:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_17_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s2_folded_gh_dup_1_hist_17_folded_hist[8], + s2_folded_gh_dup_1_hist_17_folded_hist[7:0], + s2_folded_gh_dup_1_hist_17_folded_hist[10], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_17_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_16_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_16_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_16_folded_hist[9], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s2_folded_gh_dup_1_hist_16_folded_hist[8], + s2_folded_gh_dup_1_hist_16_folded_hist[7:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_16_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s2_folded_gh_dup_1_hist_16_folded_hist[8], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s2_folded_gh_dup_1_hist_16_folded_hist[7], + s2_folded_gh_dup_1_hist_16_folded_hist[6:0], + s2_folded_gh_dup_1_hist_16_folded_hist[10], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_16_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_15_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_15_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_15_folded_hist[5], + s2_folded_gh_dup_1_hist_15_folded_hist[4:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_15_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s2_folded_gh_dup_1_hist_15_folded_hist[4], + s2_folded_gh_dup_1_hist_15_folded_hist[3:0], + s2_folded_gh_dup_1_hist_15_folded_hist[6], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_15_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_14_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_14_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_14_folded_hist[6:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {s2_folded_gh_dup_1_hist_14_folded_hist[5:0], + 1'h0, + _predictors_io_out_s2_full_pred_1_br_taken_mask_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s2_FGH_src_hist_13_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_13_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_13_folded_hist[7:4], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_13_folded_hist[3], + s2_folded_gh_dup_1_hist_13_folded_hist[2:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_13_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {s2_folded_gh_dup_1_hist_13_folded_hist[6:4], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_13_folded_hist[3], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s2_folded_gh_dup_1_hist_13_folded_hist[2], + s2_folded_gh_dup_1_hist_13_folded_hist[1:0], + s2_folded_gh_dup_1_hist_13_folded_hist[8], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_13_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_12_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_12_folded_hist : 4'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_12_folded_hist[2:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0} + : 4'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {s2_folded_gh_dup_1_hist_12_folded_hist[1:0], + 1'h0, + _predictors_io_out_s2_full_pred_1_br_taken_mask_1} + : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s2_FGH_src_hist_11_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_11_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_11_folded_hist[6:2], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2) + ^ s2_folded_gh_dup_1_hist_11_folded_hist[1], + s2_folded_gh_dup_1_hist_11_folded_hist[0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_11_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {s2_folded_gh_dup_1_hist_11_folded_hist[5:2], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2) + ^ s2_folded_gh_dup_1_hist_11_folded_hist[1], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3) + ^ s2_folded_gh_dup_1_hist_11_folded_hist[0], + s2_folded_gh_dup_1_hist_11_folded_hist[7], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_11_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_10_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_10_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_10_folded_hist[7:5], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_10_folded_hist[4], + s2_folded_gh_dup_1_hist_10_folded_hist[3:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_10_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {s2_folded_gh_dup_1_hist_10_folded_hist[6:5], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_10_folded_hist[4], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s2_folded_gh_dup_1_hist_10_folded_hist[3], + s2_folded_gh_dup_1_hist_10_folded_hist[2:0], + s2_folded_gh_dup_1_hist_10_folded_hist[8], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_10_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_9_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_9_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_9_folded_hist[5:4], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_9_folded_hist[3], + s2_folded_gh_dup_1_hist_9_folded_hist[2:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_9_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {s2_folded_gh_dup_1_hist_9_folded_hist[4], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_9_folded_hist[3], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s2_folded_gh_dup_1_hist_9_folded_hist[2], + s2_folded_gh_dup_1_hist_9_folded_hist[1:0], + s2_folded_gh_dup_1_hist_9_folded_hist[6], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_9_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_8_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_8_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s2_folded_gh_dup_1_hist_8_folded_hist[6], + s2_folded_gh_dup_1_hist_8_folded_hist[5:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_8_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s2_folded_gh_dup_1_hist_8_folded_hist[5], + s2_folded_gh_dup_1_hist_8_folded_hist[4:0], + s2_folded_gh_dup_1_hist_8_folded_hist[7], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s2_folded_gh_dup_1_hist_8_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_7_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_7_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_7_folded_hist[5:1], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) + ^ s2_folded_gh_dup_1_hist_7_folded_hist[0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_7_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {s2_folded_gh_dup_1_hist_7_folded_hist[4:1], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) + ^ s2_folded_gh_dup_1_hist_7_folded_hist[0], + 1'h0, + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_7_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_6_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_6_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_6_folded_hist[7], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s2_folded_gh_dup_1_hist_6_folded_hist[6], + s2_folded_gh_dup_1_hist_6_folded_hist[5:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_6_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s2_folded_gh_dup_1_hist_6_folded_hist[6], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) + ^ s2_folded_gh_dup_1_hist_6_folded_hist[5], + s2_folded_gh_dup_1_hist_6_folded_hist[4:0], + s2_folded_gh_dup_1_hist_6_folded_hist[8], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_6_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_5_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_5_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_5_folded_hist[5:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s2_folded_gh_dup_1_hist_5_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {s2_folded_gh_dup_1_hist_5_folded_hist[4:0], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s2_folded_gh_dup_1_hist_5_folded_hist[6], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s2_folded_gh_dup_1_hist_5_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_4_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_4_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_4_folded_hist[6:5], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_4_folded_hist[4], + s2_folded_gh_dup_1_hist_4_folded_hist[3:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_4_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {s2_folded_gh_dup_1_hist_4_folded_hist[5], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_4_folded_hist[4], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s2_folded_gh_dup_1_hist_4_folded_hist[3], + s2_folded_gh_dup_1_hist_4_folded_hist[2:0], + s2_folded_gh_dup_1_hist_4_folded_hist[7], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_4_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_3_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_3_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_3_folded_hist[6:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_3_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {s2_folded_gh_dup_1_hist_3_folded_hist[5:0], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_3_folded_hist[7], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s2_folded_gh_dup_1_hist_3_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_2_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_2_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_2_folded_hist[6:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s2_folded_gh_dup_1_hist_2_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {s2_folded_gh_dup_1_hist_2_folded_hist[5:0], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s2_folded_gh_dup_1_hist_2_folded_hist[7], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) + ^ s2_folded_gh_dup_1_hist_2_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_1_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_1_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_1_folded_hist[9:2], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_1_folded_hist[1], + s2_folded_gh_dup_1_hist_1_folded_hist[0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_1_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {s2_folded_gh_dup_1_hist_1_folded_hist[8:2], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_1_folded_hist[1], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s2_folded_gh_dup_1_hist_1_folded_hist[0], + s2_folded_gh_dup_1_hist_1_folded_hist[10], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_1_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_0_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_0_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_1 + ? {s2_folded_gh_dup_1_hist_0_folded_hist[6:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_1_2 + ? {s2_folded_gh_dup_1_hist_0_folded_hist[5:0], + 1'h0, + _predictors_io_out_s2_full_pred_1_br_taken_mask_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s1_FGH_sel + (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_FGH_src_hist_17_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_17_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_17_folded_hist[9], + s1_folded_gh_dup_1_hist_17_folded_hist[8:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ s1_folded_gh_dup_1_hist_17_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s1_folded_gh_dup_1_hist_17_folded_hist[8], + s1_folded_gh_dup_1_hist_17_folded_hist[7:0], + s1_folded_gh_dup_1_hist_17_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_17_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_16_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_16_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_16_folded_hist[9], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s1_folded_gh_dup_1_hist_16_folded_hist[8], + s1_folded_gh_dup_1_hist_16_folded_hist[7:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ s1_folded_gh_dup_1_hist_16_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s1_folded_gh_dup_1_hist_16_folded_hist[8], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s1_folded_gh_dup_1_hist_16_folded_hist[7], + s1_folded_gh_dup_1_hist_16_folded_hist[6:0], + s1_folded_gh_dup_1_hist_16_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ s1_folded_gh_dup_1_hist_16_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_15_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_15_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_15_folded_hist[5], + s1_folded_gh_dup_1_hist_15_folded_hist[4:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ s1_folded_gh_dup_1_hist_15_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s1_folded_gh_dup_1_hist_15_folded_hist[4], + s1_folded_gh_dup_1_hist_15_folded_hist[3:0], + s1_folded_gh_dup_1_hist_15_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_15_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_14_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 + ? {s1_folded_gh_dup_1_hist_14_folded_hist[7:1], + s1_folded_gh_dup_1_hist_14_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_271} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_14_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {s1_folded_gh_dup_1_hist_14_folded_hist[5:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + .s1_FGH_src_hist_13_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_13_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_13_folded_hist[7:4], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_13_folded_hist[3], + s1_folded_gh_dup_1_hist_13_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ s1_folded_gh_dup_1_hist_13_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {s1_folded_gh_dup_1_hist_13_folded_hist[6:4], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_13_folded_hist[3], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s1_folded_gh_dup_1_hist_13_folded_hist[2], + s1_folded_gh_dup_1_hist_13_folded_hist[1:0], + s1_folded_gh_dup_1_hist_13_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ s1_folded_gh_dup_1_hist_13_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_12_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 + ? {s1_folded_gh_dup_1_hist_12_folded_hist[3:1], + s1_folded_gh_dup_1_hist_12_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_271} + : 4'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_12_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0} + : 4'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {s1_folded_gh_dup_1_hist_12_folded_hist[1:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1} + : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + .s1_FGH_src_hist_11_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_11_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_11_folded_hist[6:2], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2) + ^ s1_folded_gh_dup_1_hist_11_folded_hist[1], + s1_folded_gh_dup_1_hist_11_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ s1_folded_gh_dup_1_hist_11_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {s1_folded_gh_dup_1_hist_11_folded_hist[5:2], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2) + ^ s1_folded_gh_dup_1_hist_11_folded_hist[1], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3) + ^ s1_folded_gh_dup_1_hist_11_folded_hist[0], + s1_folded_gh_dup_1_hist_11_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ s1_folded_gh_dup_1_hist_11_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_10_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_10_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_10_folded_hist[7:5], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_10_folded_hist[4], + s1_folded_gh_dup_1_hist_10_folded_hist[3:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ s1_folded_gh_dup_1_hist_10_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {s1_folded_gh_dup_1_hist_10_folded_hist[6:5], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_10_folded_hist[4], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s1_folded_gh_dup_1_hist_10_folded_hist[3], + s1_folded_gh_dup_1_hist_10_folded_hist[2:0], + s1_folded_gh_dup_1_hist_10_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ s1_folded_gh_dup_1_hist_10_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_9_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_9_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_9_folded_hist[5:4], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_9_folded_hist[3], + s1_folded_gh_dup_1_hist_9_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ s1_folded_gh_dup_1_hist_9_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {s1_folded_gh_dup_1_hist_9_folded_hist[4], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_9_folded_hist[3], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s1_folded_gh_dup_1_hist_9_folded_hist[2], + s1_folded_gh_dup_1_hist_9_folded_hist[1:0], + s1_folded_gh_dup_1_hist_9_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ s1_folded_gh_dup_1_hist_9_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_8_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_8_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s1_folded_gh_dup_1_hist_8_folded_hist[6], + s1_folded_gh_dup_1_hist_8_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ s1_folded_gh_dup_1_hist_8_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s1_folded_gh_dup_1_hist_8_folded_hist[5], + s1_folded_gh_dup_1_hist_8_folded_hist[4:0], + s1_folded_gh_dup_1_hist_8_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s1_folded_gh_dup_1_hist_8_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_7_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_7_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_7_folded_hist[5:1], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) + ^ s1_folded_gh_dup_1_hist_7_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ s1_folded_gh_dup_1_hist_7_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {s1_folded_gh_dup_1_hist_7_folded_hist[4:1], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) + ^ s1_folded_gh_dup_1_hist_7_folded_hist[0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ s1_folded_gh_dup_1_hist_7_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_6_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_6_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_6_folded_hist[7], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s1_folded_gh_dup_1_hist_6_folded_hist[6], + s1_folded_gh_dup_1_hist_6_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ s1_folded_gh_dup_1_hist_6_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s1_folded_gh_dup_1_hist_6_folded_hist[6], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) + ^ s1_folded_gh_dup_1_hist_6_folded_hist[5], + s1_folded_gh_dup_1_hist_6_folded_hist[4:0], + s1_folded_gh_dup_1_hist_6_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ s1_folded_gh_dup_1_hist_6_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_5_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_5_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_5_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s1_folded_gh_dup_1_hist_5_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {s1_folded_gh_dup_1_hist_5_folded_hist[4:0], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s1_folded_gh_dup_1_hist_5_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s1_folded_gh_dup_1_hist_5_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_4_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_4_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_4_folded_hist[6:5], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_4_folded_hist[4], + s1_folded_gh_dup_1_hist_4_folded_hist[3:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ s1_folded_gh_dup_1_hist_4_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {s1_folded_gh_dup_1_hist_4_folded_hist[5], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_4_folded_hist[4], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s1_folded_gh_dup_1_hist_4_folded_hist[3], + s1_folded_gh_dup_1_hist_4_folded_hist[2:0], + s1_folded_gh_dup_1_hist_4_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ s1_folded_gh_dup_1_hist_4_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_3_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_3_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_3_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_3_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {s1_folded_gh_dup_1_hist_3_folded_hist[5:0], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_3_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s1_folded_gh_dup_1_hist_3_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_2_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_2_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_2_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s1_folded_gh_dup_1_hist_2_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {s1_folded_gh_dup_1_hist_2_folded_hist[5:0], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s1_folded_gh_dup_1_hist_2_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) + ^ s1_folded_gh_dup_1_hist_2_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_1_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_1_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_1_folded_hist[9:2], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_1_folded_hist[1], + s1_folded_gh_dup_1_hist_1_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0 + ^ s1_folded_gh_dup_1_hist_1_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {s1_folded_gh_dup_1_hist_1_folded_hist[8:2], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_1_folded_hist[1], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s1_folded_gh_dup_1_hist_1_folded_hist[0], + s1_folded_gh_dup_1_hist_1_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1 + ^ s1_folded_gh_dup_1_hist_1_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_0_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_1_0 + ? {s1_folded_gh_dup_1_hist_0_folded_hist[7:1], + s1_folded_gh_dup_1_hist_0_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_271} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_1 + ? {s1_folded_gh_dup_1_hist_0_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_1_2 + ? {s1_folded_gh_dup_1_hist_0_folded_hist[5:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + .s3_FGH_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_FGH_src_hist_17_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_17_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_17_folded_hist[9], + s3_folded_gh_dup_1_hist_17_folded_hist[8:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_17_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s3_folded_gh_dup_1_hist_17_folded_hist[8], + s3_folded_gh_dup_1_hist_17_folded_hist[7:0], + s3_folded_gh_dup_1_hist_17_folded_hist[10], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_17_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_16_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_16_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_16_folded_hist[9], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s3_folded_gh_dup_1_hist_16_folded_hist[8], + s3_folded_gh_dup_1_hist_16_folded_hist[7:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_16_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s3_folded_gh_dup_1_hist_16_folded_hist[8], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s3_folded_gh_dup_1_hist_16_folded_hist[7], + s3_folded_gh_dup_1_hist_16_folded_hist[6:0], + s3_folded_gh_dup_1_hist_16_folded_hist[10], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_16_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_15_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_15_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_15_folded_hist[5], + s3_folded_gh_dup_1_hist_15_folded_hist[4:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_15_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s3_folded_gh_dup_1_hist_15_folded_hist[4], + s3_folded_gh_dup_1_hist_15_folded_hist[3:0], + s3_folded_gh_dup_1_hist_15_folded_hist[6], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_15_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_14_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_14_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_14_folded_hist[6:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {s3_folded_gh_dup_1_hist_14_folded_hist[5:0], + 1'h0, + _predictors_io_out_s3_full_pred_1_br_taken_mask_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s3_FGH_src_hist_13_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_13_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_13_folded_hist[7:4], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_13_folded_hist[3], + s3_folded_gh_dup_1_hist_13_folded_hist[2:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_13_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {s3_folded_gh_dup_1_hist_13_folded_hist[6:4], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_13_folded_hist[3], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s3_folded_gh_dup_1_hist_13_folded_hist[2], + s3_folded_gh_dup_1_hist_13_folded_hist[1:0], + s3_folded_gh_dup_1_hist_13_folded_hist[8], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_13_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_12_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_12_folded_hist : 4'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_12_folded_hist[2:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0} + : 4'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {s3_folded_gh_dup_1_hist_12_folded_hist[1:0], + 1'h0, + _predictors_io_out_s3_full_pred_1_br_taken_mask_1} + : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s3_FGH_src_hist_11_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_11_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_11_folded_hist[6:2], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2) + ^ s3_folded_gh_dup_1_hist_11_folded_hist[1], + s3_folded_gh_dup_1_hist_11_folded_hist[0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_11_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {s3_folded_gh_dup_1_hist_11_folded_hist[5:2], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2) + ^ s3_folded_gh_dup_1_hist_11_folded_hist[1], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3) + ^ s3_folded_gh_dup_1_hist_11_folded_hist[0], + s3_folded_gh_dup_1_hist_11_folded_hist[7], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_11_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_10_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_10_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_10_folded_hist[7:5], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_10_folded_hist[4], + s3_folded_gh_dup_1_hist_10_folded_hist[3:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_10_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {s3_folded_gh_dup_1_hist_10_folded_hist[6:5], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_10_folded_hist[4], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s3_folded_gh_dup_1_hist_10_folded_hist[3], + s3_folded_gh_dup_1_hist_10_folded_hist[2:0], + s3_folded_gh_dup_1_hist_10_folded_hist[8], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_10_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_9_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_9_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_9_folded_hist[5:4], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_9_folded_hist[3], + s3_folded_gh_dup_1_hist_9_folded_hist[2:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_9_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {s3_folded_gh_dup_1_hist_9_folded_hist[4], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_9_folded_hist[3], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s3_folded_gh_dup_1_hist_9_folded_hist[2], + s3_folded_gh_dup_1_hist_9_folded_hist[1:0], + s3_folded_gh_dup_1_hist_9_folded_hist[6], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_9_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_8_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_8_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s3_folded_gh_dup_1_hist_8_folded_hist[6], + s3_folded_gh_dup_1_hist_8_folded_hist[5:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_8_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s3_folded_gh_dup_1_hist_8_folded_hist[5], + s3_folded_gh_dup_1_hist_8_folded_hist[4:0], + s3_folded_gh_dup_1_hist_8_folded_hist[7], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s3_folded_gh_dup_1_hist_8_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_7_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_7_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_7_folded_hist[5:1], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) + ^ s3_folded_gh_dup_1_hist_7_folded_hist[0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_7_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {s3_folded_gh_dup_1_hist_7_folded_hist[4:1], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) + ^ s3_folded_gh_dup_1_hist_7_folded_hist[0], + 1'h0, + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_7_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_6_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_6_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_6_folded_hist[7], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s3_folded_gh_dup_1_hist_6_folded_hist[6], + s3_folded_gh_dup_1_hist_6_folded_hist[5:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_6_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s3_folded_gh_dup_1_hist_6_folded_hist[6], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) + ^ s3_folded_gh_dup_1_hist_6_folded_hist[5], + s3_folded_gh_dup_1_hist_6_folded_hist[4:0], + s3_folded_gh_dup_1_hist_6_folded_hist[8], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_6_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_5_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_5_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_5_folded_hist[5:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s3_folded_gh_dup_1_hist_5_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {s3_folded_gh_dup_1_hist_5_folded_hist[4:0], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s3_folded_gh_dup_1_hist_5_folded_hist[6], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s3_folded_gh_dup_1_hist_5_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_4_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_4_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_4_folded_hist[6:5], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_4_folded_hist[4], + s3_folded_gh_dup_1_hist_4_folded_hist[3:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_4_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {s3_folded_gh_dup_1_hist_4_folded_hist[5], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_4_folded_hist[4], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s3_folded_gh_dup_1_hist_4_folded_hist[3], + s3_folded_gh_dup_1_hist_4_folded_hist[2:0], + s3_folded_gh_dup_1_hist_4_folded_hist[7], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_4_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_3_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_3_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_3_folded_hist[6:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_3_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {s3_folded_gh_dup_1_hist_3_folded_hist[5:0], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_3_folded_hist[7], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s3_folded_gh_dup_1_hist_3_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_2_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_2_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_2_folded_hist[6:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s3_folded_gh_dup_1_hist_2_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {s3_folded_gh_dup_1_hist_2_folded_hist[5:0], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s3_folded_gh_dup_1_hist_2_folded_hist[7], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) + ^ s3_folded_gh_dup_1_hist_2_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_1_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_1_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_1_folded_hist[9:2], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_1_folded_hist[1], + s3_folded_gh_dup_1_hist_1_folded_hist[0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_1_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {s3_folded_gh_dup_1_hist_1_folded_hist[8:2], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_1_folded_hist[1], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s3_folded_gh_dup_1_hist_1_folded_hist[0], + s3_folded_gh_dup_1_hist_1_folded_hist[10], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_1_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_0_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_0_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_1 + ? {s3_folded_gh_dup_1_hist_0_folded_hist[6:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_1_2 + ? {s3_folded_gh_dup_1_hist_0_folded_hist[5:0], + 1'h0, + _predictors_io_out_s3_full_pred_1_br_taken_mask_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .redirect_FGHT_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_FGHT_src_hist_17_folded_hist (_GEN_45[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_16_folded_hist (_GEN_46[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_15_folded_hist (_GEN_47[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_14_folded_hist (_GEN_48[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_13_folded_hist (_GEN_49[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_12_folded_hist (_GEN_50[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_11_folded_hist (_GEN_51[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_10_folded_hist (_GEN_52[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_9_folded_hist (_GEN_53[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_8_folded_hist (_GEN_54[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_7_folded_hist (_GEN_55[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_6_folded_hist (_GEN_56[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_5_folded_hist (_GEN_57[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_4_folded_hist (_GEN_58[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_3_folded_hist (_GEN_59[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_2_folded_hist (_GEN_60[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_1_folded_hist (_GEN_61[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_0_folded_hist (_GEN_62[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_1_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_1_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_1_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_1_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_1_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_1_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_1_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_1_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_1_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_1_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_1_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_1_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_1_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_1_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_1_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_1_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_1_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_1_hist_0_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .out_res_hist_17_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist), + .out_res_hist_16_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist), + .out_res_hist_15_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist), + .out_res_hist_14_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist), + .out_res_hist_13_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist), + .out_res_hist_12_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist), + .out_res_hist_11_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist), + .out_res_hist_10_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist), + .out_res_hist_9_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist), + .out_res_hist_8_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist), + .out_res_hist_7_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist), + .out_res_hist_6_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist), + .out_res_hist_5_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist), + .out_res_hist_4_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist), + .out_res_hist_3_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist), + .out_res_hist_2_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist), + .out_res_hist_1_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist), + .out_res_hist_0_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist) + ); + PriorityMuxModule_4 s0_folded_gh_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_FGH_sel + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_FGH_src_hist_17_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_17_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_17_folded_hist[9], + s2_folded_gh_dup_2_hist_17_folded_hist[8:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_17_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s2_folded_gh_dup_2_hist_17_folded_hist[8], + s2_folded_gh_dup_2_hist_17_folded_hist[7:0], + s2_folded_gh_dup_2_hist_17_folded_hist[10], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_17_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_16_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_16_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_16_folded_hist[9], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s2_folded_gh_dup_2_hist_16_folded_hist[8], + s2_folded_gh_dup_2_hist_16_folded_hist[7:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_16_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s2_folded_gh_dup_2_hist_16_folded_hist[8], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s2_folded_gh_dup_2_hist_16_folded_hist[7], + s2_folded_gh_dup_2_hist_16_folded_hist[6:0], + s2_folded_gh_dup_2_hist_16_folded_hist[10], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_16_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_15_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_15_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_15_folded_hist[5], + s2_folded_gh_dup_2_hist_15_folded_hist[4:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_15_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s2_folded_gh_dup_2_hist_15_folded_hist[4], + s2_folded_gh_dup_2_hist_15_folded_hist[3:0], + s2_folded_gh_dup_2_hist_15_folded_hist[6], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_15_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_14_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_14_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_14_folded_hist[6:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {s2_folded_gh_dup_2_hist_14_folded_hist[5:0], + 1'h0, + _predictors_io_out_s2_full_pred_2_br_taken_mask_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s2_FGH_src_hist_13_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_13_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_13_folded_hist[7:4], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_13_folded_hist[3], + s2_folded_gh_dup_2_hist_13_folded_hist[2:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_13_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {s2_folded_gh_dup_2_hist_13_folded_hist[6:4], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_13_folded_hist[3], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s2_folded_gh_dup_2_hist_13_folded_hist[2], + s2_folded_gh_dup_2_hist_13_folded_hist[1:0], + s2_folded_gh_dup_2_hist_13_folded_hist[8], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_13_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_12_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_12_folded_hist : 4'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_12_folded_hist[2:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0} + : 4'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {s2_folded_gh_dup_2_hist_12_folded_hist[1:0], + 1'h0, + _predictors_io_out_s2_full_pred_2_br_taken_mask_1} + : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s2_FGH_src_hist_11_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_11_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_11_folded_hist[6:2], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2) + ^ s2_folded_gh_dup_2_hist_11_folded_hist[1], + s2_folded_gh_dup_2_hist_11_folded_hist[0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_11_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {s2_folded_gh_dup_2_hist_11_folded_hist[5:2], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2) + ^ s2_folded_gh_dup_2_hist_11_folded_hist[1], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3) + ^ s2_folded_gh_dup_2_hist_11_folded_hist[0], + s2_folded_gh_dup_2_hist_11_folded_hist[7], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_11_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_10_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_10_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_10_folded_hist[7:5], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_10_folded_hist[4], + s2_folded_gh_dup_2_hist_10_folded_hist[3:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_10_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {s2_folded_gh_dup_2_hist_10_folded_hist[6:5], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_10_folded_hist[4], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s2_folded_gh_dup_2_hist_10_folded_hist[3], + s2_folded_gh_dup_2_hist_10_folded_hist[2:0], + s2_folded_gh_dup_2_hist_10_folded_hist[8], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_10_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_9_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_9_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_9_folded_hist[5:4], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_9_folded_hist[3], + s2_folded_gh_dup_2_hist_9_folded_hist[2:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_9_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {s2_folded_gh_dup_2_hist_9_folded_hist[4], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_9_folded_hist[3], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s2_folded_gh_dup_2_hist_9_folded_hist[2], + s2_folded_gh_dup_2_hist_9_folded_hist[1:0], + s2_folded_gh_dup_2_hist_9_folded_hist[6], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_9_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_8_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_8_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s2_folded_gh_dup_2_hist_8_folded_hist[6], + s2_folded_gh_dup_2_hist_8_folded_hist[5:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_8_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s2_folded_gh_dup_2_hist_8_folded_hist[5], + s2_folded_gh_dup_2_hist_8_folded_hist[4:0], + s2_folded_gh_dup_2_hist_8_folded_hist[7], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s2_folded_gh_dup_2_hist_8_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_7_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_7_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_7_folded_hist[5:1], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) + ^ s2_folded_gh_dup_2_hist_7_folded_hist[0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_7_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {s2_folded_gh_dup_2_hist_7_folded_hist[4:1], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) + ^ s2_folded_gh_dup_2_hist_7_folded_hist[0], + 1'h0, + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_7_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_6_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_6_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_6_folded_hist[7], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s2_folded_gh_dup_2_hist_6_folded_hist[6], + s2_folded_gh_dup_2_hist_6_folded_hist[5:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_6_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s2_folded_gh_dup_2_hist_6_folded_hist[6], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) + ^ s2_folded_gh_dup_2_hist_6_folded_hist[5], + s2_folded_gh_dup_2_hist_6_folded_hist[4:0], + s2_folded_gh_dup_2_hist_6_folded_hist[8], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_6_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_5_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_5_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_5_folded_hist[5:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s2_folded_gh_dup_2_hist_5_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {s2_folded_gh_dup_2_hist_5_folded_hist[4:0], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s2_folded_gh_dup_2_hist_5_folded_hist[6], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s2_folded_gh_dup_2_hist_5_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_4_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_4_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_4_folded_hist[6:5], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_4_folded_hist[4], + s2_folded_gh_dup_2_hist_4_folded_hist[3:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_4_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {s2_folded_gh_dup_2_hist_4_folded_hist[5], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_4_folded_hist[4], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s2_folded_gh_dup_2_hist_4_folded_hist[3], + s2_folded_gh_dup_2_hist_4_folded_hist[2:0], + s2_folded_gh_dup_2_hist_4_folded_hist[7], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_4_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_3_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_3_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_3_folded_hist[6:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_3_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {s2_folded_gh_dup_2_hist_3_folded_hist[5:0], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_3_folded_hist[7], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s2_folded_gh_dup_2_hist_3_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_2_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_2_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_2_folded_hist[6:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s2_folded_gh_dup_2_hist_2_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {s2_folded_gh_dup_2_hist_2_folded_hist[5:0], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s2_folded_gh_dup_2_hist_2_folded_hist[7], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) + ^ s2_folded_gh_dup_2_hist_2_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_1_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_1_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_1_folded_hist[9:2], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_1_folded_hist[1], + s2_folded_gh_dup_2_hist_1_folded_hist[0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_1_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {s2_folded_gh_dup_2_hist_1_folded_hist[8:2], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_1_folded_hist[1], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s2_folded_gh_dup_2_hist_1_folded_hist[0], + s2_folded_gh_dup_2_hist_1_folded_hist[10], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_1_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_0_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_0_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_1 + ? {s2_folded_gh_dup_2_hist_0_folded_hist[6:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_2_2 + ? {s2_folded_gh_dup_2_hist_0_folded_hist[5:0], + 1'h0, + _predictors_io_out_s2_full_pred_2_br_taken_mask_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s1_FGH_sel + (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_FGH_src_hist_17_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_17_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_17_folded_hist[9], + s1_folded_gh_dup_2_hist_17_folded_hist[8:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ s1_folded_gh_dup_2_hist_17_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s1_folded_gh_dup_2_hist_17_folded_hist[8], + s1_folded_gh_dup_2_hist_17_folded_hist[7:0], + s1_folded_gh_dup_2_hist_17_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_17_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_16_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_16_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_16_folded_hist[9], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s1_folded_gh_dup_2_hist_16_folded_hist[8], + s1_folded_gh_dup_2_hist_16_folded_hist[7:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ s1_folded_gh_dup_2_hist_16_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s1_folded_gh_dup_2_hist_16_folded_hist[8], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s1_folded_gh_dup_2_hist_16_folded_hist[7], + s1_folded_gh_dup_2_hist_16_folded_hist[6:0], + s1_folded_gh_dup_2_hist_16_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ s1_folded_gh_dup_2_hist_16_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_15_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_15_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_15_folded_hist[5], + s1_folded_gh_dup_2_hist_15_folded_hist[4:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ s1_folded_gh_dup_2_hist_15_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s1_folded_gh_dup_2_hist_15_folded_hist[4], + s1_folded_gh_dup_2_hist_15_folded_hist[3:0], + s1_folded_gh_dup_2_hist_15_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_15_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_14_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 + ? {s1_folded_gh_dup_2_hist_14_folded_hist[7:1], + s1_folded_gh_dup_2_hist_14_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_274} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_14_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {s1_folded_gh_dup_2_hist_14_folded_hist[5:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + .s1_FGH_src_hist_13_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_13_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_13_folded_hist[7:4], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_13_folded_hist[3], + s1_folded_gh_dup_2_hist_13_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ s1_folded_gh_dup_2_hist_13_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {s1_folded_gh_dup_2_hist_13_folded_hist[6:4], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_13_folded_hist[3], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s1_folded_gh_dup_2_hist_13_folded_hist[2], + s1_folded_gh_dup_2_hist_13_folded_hist[1:0], + s1_folded_gh_dup_2_hist_13_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ s1_folded_gh_dup_2_hist_13_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_12_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 + ? {s1_folded_gh_dup_2_hist_12_folded_hist[3:1], + s1_folded_gh_dup_2_hist_12_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_274} + : 4'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_12_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0} + : 4'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {s1_folded_gh_dup_2_hist_12_folded_hist[1:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1} + : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + .s1_FGH_src_hist_11_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_11_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_11_folded_hist[6:2], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2) + ^ s1_folded_gh_dup_2_hist_11_folded_hist[1], + s1_folded_gh_dup_2_hist_11_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ s1_folded_gh_dup_2_hist_11_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {s1_folded_gh_dup_2_hist_11_folded_hist[5:2], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2) + ^ s1_folded_gh_dup_2_hist_11_folded_hist[1], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3) + ^ s1_folded_gh_dup_2_hist_11_folded_hist[0], + s1_folded_gh_dup_2_hist_11_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ s1_folded_gh_dup_2_hist_11_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_10_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_10_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_10_folded_hist[7:5], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_10_folded_hist[4], + s1_folded_gh_dup_2_hist_10_folded_hist[3:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ s1_folded_gh_dup_2_hist_10_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {s1_folded_gh_dup_2_hist_10_folded_hist[6:5], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_10_folded_hist[4], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s1_folded_gh_dup_2_hist_10_folded_hist[3], + s1_folded_gh_dup_2_hist_10_folded_hist[2:0], + s1_folded_gh_dup_2_hist_10_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ s1_folded_gh_dup_2_hist_10_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_9_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_9_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_9_folded_hist[5:4], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_9_folded_hist[3], + s1_folded_gh_dup_2_hist_9_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ s1_folded_gh_dup_2_hist_9_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {s1_folded_gh_dup_2_hist_9_folded_hist[4], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_9_folded_hist[3], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s1_folded_gh_dup_2_hist_9_folded_hist[2], + s1_folded_gh_dup_2_hist_9_folded_hist[1:0], + s1_folded_gh_dup_2_hist_9_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ s1_folded_gh_dup_2_hist_9_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_8_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_8_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s1_folded_gh_dup_2_hist_8_folded_hist[6], + s1_folded_gh_dup_2_hist_8_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ s1_folded_gh_dup_2_hist_8_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s1_folded_gh_dup_2_hist_8_folded_hist[5], + s1_folded_gh_dup_2_hist_8_folded_hist[4:0], + s1_folded_gh_dup_2_hist_8_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s1_folded_gh_dup_2_hist_8_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_7_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_7_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_7_folded_hist[5:1], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) + ^ s1_folded_gh_dup_2_hist_7_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ s1_folded_gh_dup_2_hist_7_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {s1_folded_gh_dup_2_hist_7_folded_hist[4:1], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) + ^ s1_folded_gh_dup_2_hist_7_folded_hist[0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ s1_folded_gh_dup_2_hist_7_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_6_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_6_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_6_folded_hist[7], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s1_folded_gh_dup_2_hist_6_folded_hist[6], + s1_folded_gh_dup_2_hist_6_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ s1_folded_gh_dup_2_hist_6_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s1_folded_gh_dup_2_hist_6_folded_hist[6], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) + ^ s1_folded_gh_dup_2_hist_6_folded_hist[5], + s1_folded_gh_dup_2_hist_6_folded_hist[4:0], + s1_folded_gh_dup_2_hist_6_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ s1_folded_gh_dup_2_hist_6_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_5_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_5_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_5_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s1_folded_gh_dup_2_hist_5_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {s1_folded_gh_dup_2_hist_5_folded_hist[4:0], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s1_folded_gh_dup_2_hist_5_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s1_folded_gh_dup_2_hist_5_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_4_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_4_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_4_folded_hist[6:5], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_4_folded_hist[4], + s1_folded_gh_dup_2_hist_4_folded_hist[3:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ s1_folded_gh_dup_2_hist_4_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {s1_folded_gh_dup_2_hist_4_folded_hist[5], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_4_folded_hist[4], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s1_folded_gh_dup_2_hist_4_folded_hist[3], + s1_folded_gh_dup_2_hist_4_folded_hist[2:0], + s1_folded_gh_dup_2_hist_4_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ s1_folded_gh_dup_2_hist_4_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_3_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_3_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_3_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_3_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {s1_folded_gh_dup_2_hist_3_folded_hist[5:0], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_3_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s1_folded_gh_dup_2_hist_3_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_2_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_2_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_2_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s1_folded_gh_dup_2_hist_2_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {s1_folded_gh_dup_2_hist_2_folded_hist[5:0], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s1_folded_gh_dup_2_hist_2_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) + ^ s1_folded_gh_dup_2_hist_2_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_1_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_1_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_1_folded_hist[9:2], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_1_folded_hist[1], + s1_folded_gh_dup_2_hist_1_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0 + ^ s1_folded_gh_dup_2_hist_1_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {s1_folded_gh_dup_2_hist_1_folded_hist[8:2], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_1_folded_hist[1], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s1_folded_gh_dup_2_hist_1_folded_hist[0], + s1_folded_gh_dup_2_hist_1_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1 + ^ s1_folded_gh_dup_2_hist_1_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_0_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_2_0 + ? {s1_folded_gh_dup_2_hist_0_folded_hist[7:1], + s1_folded_gh_dup_2_hist_0_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_274} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_1 + ? {s1_folded_gh_dup_2_hist_0_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_2_2 + ? {s1_folded_gh_dup_2_hist_0_folded_hist[5:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + .s3_FGH_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_FGH_src_hist_17_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_17_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_17_folded_hist[9], + s3_folded_gh_dup_2_hist_17_folded_hist[8:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_17_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s3_folded_gh_dup_2_hist_17_folded_hist[8], + s3_folded_gh_dup_2_hist_17_folded_hist[7:0], + s3_folded_gh_dup_2_hist_17_folded_hist[10], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_17_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_16_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_16_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_16_folded_hist[9], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s3_folded_gh_dup_2_hist_16_folded_hist[8], + s3_folded_gh_dup_2_hist_16_folded_hist[7:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_16_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s3_folded_gh_dup_2_hist_16_folded_hist[8], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s3_folded_gh_dup_2_hist_16_folded_hist[7], + s3_folded_gh_dup_2_hist_16_folded_hist[6:0], + s3_folded_gh_dup_2_hist_16_folded_hist[10], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_16_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_15_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_15_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_15_folded_hist[5], + s3_folded_gh_dup_2_hist_15_folded_hist[4:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_15_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s3_folded_gh_dup_2_hist_15_folded_hist[4], + s3_folded_gh_dup_2_hist_15_folded_hist[3:0], + s3_folded_gh_dup_2_hist_15_folded_hist[6], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_15_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_14_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_14_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_14_folded_hist[6:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {s3_folded_gh_dup_2_hist_14_folded_hist[5:0], + 1'h0, + _predictors_io_out_s3_full_pred_2_br_taken_mask_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s3_FGH_src_hist_13_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_13_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_13_folded_hist[7:4], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_13_folded_hist[3], + s3_folded_gh_dup_2_hist_13_folded_hist[2:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_13_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {s3_folded_gh_dup_2_hist_13_folded_hist[6:4], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_13_folded_hist[3], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s3_folded_gh_dup_2_hist_13_folded_hist[2], + s3_folded_gh_dup_2_hist_13_folded_hist[1:0], + s3_folded_gh_dup_2_hist_13_folded_hist[8], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_13_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_12_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_12_folded_hist : 4'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_12_folded_hist[2:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0} + : 4'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {s3_folded_gh_dup_2_hist_12_folded_hist[1:0], + 1'h0, + _predictors_io_out_s3_full_pred_2_br_taken_mask_1} + : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s3_FGH_src_hist_11_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_11_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_11_folded_hist[6:2], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2) + ^ s3_folded_gh_dup_2_hist_11_folded_hist[1], + s3_folded_gh_dup_2_hist_11_folded_hist[0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_11_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {s3_folded_gh_dup_2_hist_11_folded_hist[5:2], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2) + ^ s3_folded_gh_dup_2_hist_11_folded_hist[1], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3) + ^ s3_folded_gh_dup_2_hist_11_folded_hist[0], + s3_folded_gh_dup_2_hist_11_folded_hist[7], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_11_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_10_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_10_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_10_folded_hist[7:5], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_10_folded_hist[4], + s3_folded_gh_dup_2_hist_10_folded_hist[3:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_10_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {s3_folded_gh_dup_2_hist_10_folded_hist[6:5], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_10_folded_hist[4], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s3_folded_gh_dup_2_hist_10_folded_hist[3], + s3_folded_gh_dup_2_hist_10_folded_hist[2:0], + s3_folded_gh_dup_2_hist_10_folded_hist[8], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_10_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_9_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_9_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_9_folded_hist[5:4], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_9_folded_hist[3], + s3_folded_gh_dup_2_hist_9_folded_hist[2:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_9_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {s3_folded_gh_dup_2_hist_9_folded_hist[4], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_9_folded_hist[3], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s3_folded_gh_dup_2_hist_9_folded_hist[2], + s3_folded_gh_dup_2_hist_9_folded_hist[1:0], + s3_folded_gh_dup_2_hist_9_folded_hist[6], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_9_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_8_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_8_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s3_folded_gh_dup_2_hist_8_folded_hist[6], + s3_folded_gh_dup_2_hist_8_folded_hist[5:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_8_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s3_folded_gh_dup_2_hist_8_folded_hist[5], + s3_folded_gh_dup_2_hist_8_folded_hist[4:0], + s3_folded_gh_dup_2_hist_8_folded_hist[7], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s3_folded_gh_dup_2_hist_8_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_7_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_7_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_7_folded_hist[5:1], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) + ^ s3_folded_gh_dup_2_hist_7_folded_hist[0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_7_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {s3_folded_gh_dup_2_hist_7_folded_hist[4:1], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) + ^ s3_folded_gh_dup_2_hist_7_folded_hist[0], + 1'h0, + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_7_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_6_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_6_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_6_folded_hist[7], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s3_folded_gh_dup_2_hist_6_folded_hist[6], + s3_folded_gh_dup_2_hist_6_folded_hist[5:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_6_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s3_folded_gh_dup_2_hist_6_folded_hist[6], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) + ^ s3_folded_gh_dup_2_hist_6_folded_hist[5], + s3_folded_gh_dup_2_hist_6_folded_hist[4:0], + s3_folded_gh_dup_2_hist_6_folded_hist[8], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_6_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_5_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_5_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_5_folded_hist[5:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s3_folded_gh_dup_2_hist_5_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {s3_folded_gh_dup_2_hist_5_folded_hist[4:0], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s3_folded_gh_dup_2_hist_5_folded_hist[6], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s3_folded_gh_dup_2_hist_5_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_4_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_4_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_4_folded_hist[6:5], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_4_folded_hist[4], + s3_folded_gh_dup_2_hist_4_folded_hist[3:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_4_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {s3_folded_gh_dup_2_hist_4_folded_hist[5], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_4_folded_hist[4], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s3_folded_gh_dup_2_hist_4_folded_hist[3], + s3_folded_gh_dup_2_hist_4_folded_hist[2:0], + s3_folded_gh_dup_2_hist_4_folded_hist[7], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_4_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_3_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_3_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_3_folded_hist[6:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_3_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {s3_folded_gh_dup_2_hist_3_folded_hist[5:0], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_3_folded_hist[7], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s3_folded_gh_dup_2_hist_3_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_2_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_2_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_2_folded_hist[6:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s3_folded_gh_dup_2_hist_2_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {s3_folded_gh_dup_2_hist_2_folded_hist[5:0], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s3_folded_gh_dup_2_hist_2_folded_hist[7], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) + ^ s3_folded_gh_dup_2_hist_2_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_1_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_1_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_1_folded_hist[9:2], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_1_folded_hist[1], + s3_folded_gh_dup_2_hist_1_folded_hist[0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_1_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {s3_folded_gh_dup_2_hist_1_folded_hist[8:2], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_1_folded_hist[1], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s3_folded_gh_dup_2_hist_1_folded_hist[0], + s3_folded_gh_dup_2_hist_1_folded_hist[10], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_1_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_0_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_0_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_1 + ? {s3_folded_gh_dup_2_hist_0_folded_hist[6:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_2_2 + ? {s3_folded_gh_dup_2_hist_0_folded_hist[5:0], + 1'h0, + _predictors_io_out_s3_full_pred_2_br_taken_mask_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .redirect_FGHT_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_FGHT_src_hist_17_folded_hist (_GEN_63[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_16_folded_hist (_GEN_64[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_15_folded_hist (_GEN_65[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_14_folded_hist (_GEN_66[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_13_folded_hist (_GEN_67[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_12_folded_hist (_GEN_68[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_11_folded_hist (_GEN_69[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_10_folded_hist (_GEN_70[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_9_folded_hist (_GEN_71[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_8_folded_hist (_GEN_72[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_7_folded_hist (_GEN_73[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_6_folded_hist (_GEN_74[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_5_folded_hist (_GEN_75[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_4_folded_hist (_GEN_76[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_3_folded_hist (_GEN_77[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_2_folded_hist (_GEN_78[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_1_folded_hist (_GEN_79[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_0_folded_hist (_GEN_80[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_2_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_2_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_2_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_2_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_2_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_2_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_2_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_2_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_2_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_2_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_2_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_2_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_2_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_2_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_2_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_2_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_2_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_2_hist_0_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .out_res_hist_17_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist), + .out_res_hist_16_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist), + .out_res_hist_15_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist), + .out_res_hist_14_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist), + .out_res_hist_13_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist), + .out_res_hist_12_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist), + .out_res_hist_11_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist), + .out_res_hist_10_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist), + .out_res_hist_9_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist), + .out_res_hist_8_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist), + .out_res_hist_7_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist), + .out_res_hist_6_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist), + .out_res_hist_5_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist), + .out_res_hist_4_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist), + .out_res_hist_3_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist), + .out_res_hist_2_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist), + .out_res_hist_1_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist), + .out_res_hist_0_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist) + ); + PriorityMuxModule_4 s0_folded_gh_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_FGH_sel + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_FGH_src_hist_17_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_17_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_17_folded_hist[9], + s2_folded_gh_dup_3_hist_17_folded_hist[8:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_17_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s2_folded_gh_dup_3_hist_17_folded_hist[8], + s2_folded_gh_dup_3_hist_17_folded_hist[7:0], + s2_folded_gh_dup_3_hist_17_folded_hist[10], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_17_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_16_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_16_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_16_folded_hist[9], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s2_folded_gh_dup_3_hist_16_folded_hist[8], + s2_folded_gh_dup_3_hist_16_folded_hist[7:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_16_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s2_folded_gh_dup_3_hist_16_folded_hist[8], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s2_folded_gh_dup_3_hist_16_folded_hist[7], + s2_folded_gh_dup_3_hist_16_folded_hist[6:0], + s2_folded_gh_dup_3_hist_16_folded_hist[10], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_16_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_15_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_15_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_15_folded_hist[5], + s2_folded_gh_dup_3_hist_15_folded_hist[4:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_15_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s2_folded_gh_dup_3_hist_15_folded_hist[4], + s2_folded_gh_dup_3_hist_15_folded_hist[3:0], + s2_folded_gh_dup_3_hist_15_folded_hist[6], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_15_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_14_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_14_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_14_folded_hist[6:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {s2_folded_gh_dup_3_hist_14_folded_hist[5:0], + 1'h0, + _predictors_io_out_s2_full_pred_3_br_taken_mask_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s2_FGH_src_hist_13_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_13_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_13_folded_hist[7:4], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_13_folded_hist[3], + s2_folded_gh_dup_3_hist_13_folded_hist[2:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_13_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {s2_folded_gh_dup_3_hist_13_folded_hist[6:4], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_13_folded_hist[3], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s2_folded_gh_dup_3_hist_13_folded_hist[2], + s2_folded_gh_dup_3_hist_13_folded_hist[1:0], + s2_folded_gh_dup_3_hist_13_folded_hist[8], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_13_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_12_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_12_folded_hist : 4'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_12_folded_hist[2:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0} + : 4'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {s2_folded_gh_dup_3_hist_12_folded_hist[1:0], + 1'h0, + _predictors_io_out_s2_full_pred_3_br_taken_mask_1} + : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s2_FGH_src_hist_11_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_11_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_11_folded_hist[6:2], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2) + ^ s2_folded_gh_dup_3_hist_11_folded_hist[1], + s2_folded_gh_dup_3_hist_11_folded_hist[0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_11_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {s2_folded_gh_dup_3_hist_11_folded_hist[5:2], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2) + ^ s2_folded_gh_dup_3_hist_11_folded_hist[1], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3) + ^ s2_folded_gh_dup_3_hist_11_folded_hist[0], + s2_folded_gh_dup_3_hist_11_folded_hist[7], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_11_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_10_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_10_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_10_folded_hist[7:5], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_10_folded_hist[4], + s2_folded_gh_dup_3_hist_10_folded_hist[3:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_10_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {s2_folded_gh_dup_3_hist_10_folded_hist[6:5], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_10_folded_hist[4], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s2_folded_gh_dup_3_hist_10_folded_hist[3], + s2_folded_gh_dup_3_hist_10_folded_hist[2:0], + s2_folded_gh_dup_3_hist_10_folded_hist[8], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_10_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_9_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_9_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_9_folded_hist[5:4], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_9_folded_hist[3], + s2_folded_gh_dup_3_hist_9_folded_hist[2:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_9_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {s2_folded_gh_dup_3_hist_9_folded_hist[4], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_9_folded_hist[3], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s2_folded_gh_dup_3_hist_9_folded_hist[2], + s2_folded_gh_dup_3_hist_9_folded_hist[1:0], + s2_folded_gh_dup_3_hist_9_folded_hist[6], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_9_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_8_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_8_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s2_folded_gh_dup_3_hist_8_folded_hist[6], + s2_folded_gh_dup_3_hist_8_folded_hist[5:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_8_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s2_folded_gh_dup_3_hist_8_folded_hist[5], + s2_folded_gh_dup_3_hist_8_folded_hist[4:0], + s2_folded_gh_dup_3_hist_8_folded_hist[7], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s2_folded_gh_dup_3_hist_8_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_7_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_7_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_7_folded_hist[5:1], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) + ^ s2_folded_gh_dup_3_hist_7_folded_hist[0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_7_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {s2_folded_gh_dup_3_hist_7_folded_hist[4:1], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) + ^ s2_folded_gh_dup_3_hist_7_folded_hist[0], + 1'h0, + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_7_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_6_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_6_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_6_folded_hist[7], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s2_folded_gh_dup_3_hist_6_folded_hist[6], + s2_folded_gh_dup_3_hist_6_folded_hist[5:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_6_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s2_folded_gh_dup_3_hist_6_folded_hist[6], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) + ^ s2_folded_gh_dup_3_hist_6_folded_hist[5], + s2_folded_gh_dup_3_hist_6_folded_hist[4:0], + s2_folded_gh_dup_3_hist_6_folded_hist[8], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_6_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_5_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_5_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_5_folded_hist[5:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s2_folded_gh_dup_3_hist_5_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {s2_folded_gh_dup_3_hist_5_folded_hist[4:0], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s2_folded_gh_dup_3_hist_5_folded_hist[6], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s2_folded_gh_dup_3_hist_5_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_4_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_4_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_4_folded_hist[6:5], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_4_folded_hist[4], + s2_folded_gh_dup_3_hist_4_folded_hist[3:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_4_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {s2_folded_gh_dup_3_hist_4_folded_hist[5], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_4_folded_hist[4], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s2_folded_gh_dup_3_hist_4_folded_hist[3], + s2_folded_gh_dup_3_hist_4_folded_hist[2:0], + s2_folded_gh_dup_3_hist_4_folded_hist[7], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_4_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_3_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_3_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_3_folded_hist[6:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_3_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {s2_folded_gh_dup_3_hist_3_folded_hist[5:0], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_3_folded_hist[7], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s2_folded_gh_dup_3_hist_3_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_2_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_2_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_2_folded_hist[6:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s2_folded_gh_dup_3_hist_2_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {s2_folded_gh_dup_3_hist_2_folded_hist[5:0], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s2_folded_gh_dup_3_hist_2_folded_hist[7], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) + ^ s2_folded_gh_dup_3_hist_2_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_1_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_1_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_1_folded_hist[9:2], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_1_folded_hist[1], + s2_folded_gh_dup_3_hist_1_folded_hist[0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_1_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {s2_folded_gh_dup_3_hist_1_folded_hist[8:2], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_1_folded_hist[1], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s2_folded_gh_dup_3_hist_1_folded_hist[0], + s2_folded_gh_dup_3_hist_1_folded_hist[10], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_1_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s2_FGH_src_hist_0_folded_hist + ((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_0_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_1 + ? {s2_folded_gh_dup_3_hist_0_folded_hist[6:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0} + : 8'h0) + | (_s2_predicted_fh_dup_WIRE_56_3_2 + ? {s2_folded_gh_dup_3_hist_0_folded_hist[5:0], + 1'h0, + _predictors_io_out_s2_full_pred_3_br_taken_mask_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s1_FGH_sel + (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_FGH_src_hist_17_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_17_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_17_folded_hist[9], + s1_folded_gh_dup_3_hist_17_folded_hist[8:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ s1_folded_gh_dup_3_hist_17_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s1_folded_gh_dup_3_hist_17_folded_hist[8], + s1_folded_gh_dup_3_hist_17_folded_hist[7:0], + s1_folded_gh_dup_3_hist_17_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_17_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_16_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_16_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_16_folded_hist[9], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s1_folded_gh_dup_3_hist_16_folded_hist[8], + s1_folded_gh_dup_3_hist_16_folded_hist[7:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ s1_folded_gh_dup_3_hist_16_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s1_folded_gh_dup_3_hist_16_folded_hist[8], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s1_folded_gh_dup_3_hist_16_folded_hist[7], + s1_folded_gh_dup_3_hist_16_folded_hist[6:0], + s1_folded_gh_dup_3_hist_16_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ s1_folded_gh_dup_3_hist_16_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_15_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_15_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_15_folded_hist[5], + s1_folded_gh_dup_3_hist_15_folded_hist[4:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ s1_folded_gh_dup_3_hist_15_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s1_folded_gh_dup_3_hist_15_folded_hist[4], + s1_folded_gh_dup_3_hist_15_folded_hist[3:0], + s1_folded_gh_dup_3_hist_15_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_15_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_14_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 + ? {s1_folded_gh_dup_3_hist_14_folded_hist[7:1], + s1_folded_gh_dup_3_hist_14_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_277} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_14_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {s1_folded_gh_dup_3_hist_14_folded_hist[5:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + .s1_FGH_src_hist_13_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_13_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_13_folded_hist[7:4], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_13_folded_hist[3], + s1_folded_gh_dup_3_hist_13_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ s1_folded_gh_dup_3_hist_13_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {s1_folded_gh_dup_3_hist_13_folded_hist[6:4], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_13_folded_hist[3], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s1_folded_gh_dup_3_hist_13_folded_hist[2], + s1_folded_gh_dup_3_hist_13_folded_hist[1:0], + s1_folded_gh_dup_3_hist_13_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ s1_folded_gh_dup_3_hist_13_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_12_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 + ? {s1_folded_gh_dup_3_hist_12_folded_hist[3:1], + s1_folded_gh_dup_3_hist_12_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_277} + : 4'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_12_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0} + : 4'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {s1_folded_gh_dup_3_hist_12_folded_hist[1:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1} + : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + .s1_FGH_src_hist_11_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_11_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_11_folded_hist[6:2], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2) + ^ s1_folded_gh_dup_3_hist_11_folded_hist[1], + s1_folded_gh_dup_3_hist_11_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ s1_folded_gh_dup_3_hist_11_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {s1_folded_gh_dup_3_hist_11_folded_hist[5:2], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2) + ^ s1_folded_gh_dup_3_hist_11_folded_hist[1], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3) + ^ s1_folded_gh_dup_3_hist_11_folded_hist[0], + s1_folded_gh_dup_3_hist_11_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ s1_folded_gh_dup_3_hist_11_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_10_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_10_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_10_folded_hist[7:5], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_10_folded_hist[4], + s1_folded_gh_dup_3_hist_10_folded_hist[3:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ s1_folded_gh_dup_3_hist_10_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {s1_folded_gh_dup_3_hist_10_folded_hist[6:5], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_10_folded_hist[4], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s1_folded_gh_dup_3_hist_10_folded_hist[3], + s1_folded_gh_dup_3_hist_10_folded_hist[2:0], + s1_folded_gh_dup_3_hist_10_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ s1_folded_gh_dup_3_hist_10_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_9_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_9_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_9_folded_hist[5:4], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_9_folded_hist[3], + s1_folded_gh_dup_3_hist_9_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ s1_folded_gh_dup_3_hist_9_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {s1_folded_gh_dup_3_hist_9_folded_hist[4], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_9_folded_hist[3], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s1_folded_gh_dup_3_hist_9_folded_hist[2], + s1_folded_gh_dup_3_hist_9_folded_hist[1:0], + s1_folded_gh_dup_3_hist_9_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ s1_folded_gh_dup_3_hist_9_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_8_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_8_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s1_folded_gh_dup_3_hist_8_folded_hist[6], + s1_folded_gh_dup_3_hist_8_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ s1_folded_gh_dup_3_hist_8_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s1_folded_gh_dup_3_hist_8_folded_hist[5], + s1_folded_gh_dup_3_hist_8_folded_hist[4:0], + s1_folded_gh_dup_3_hist_8_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s1_folded_gh_dup_3_hist_8_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_7_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_7_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_7_folded_hist[5:1], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) + ^ s1_folded_gh_dup_3_hist_7_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ s1_folded_gh_dup_3_hist_7_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {s1_folded_gh_dup_3_hist_7_folded_hist[4:1], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) + ^ s1_folded_gh_dup_3_hist_7_folded_hist[0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ s1_folded_gh_dup_3_hist_7_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_6_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_6_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_6_folded_hist[7], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s1_folded_gh_dup_3_hist_6_folded_hist[6], + s1_folded_gh_dup_3_hist_6_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ s1_folded_gh_dup_3_hist_6_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s1_folded_gh_dup_3_hist_6_folded_hist[6], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) + ^ s1_folded_gh_dup_3_hist_6_folded_hist[5], + s1_folded_gh_dup_3_hist_6_folded_hist[4:0], + s1_folded_gh_dup_3_hist_6_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ s1_folded_gh_dup_3_hist_6_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_5_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_5_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_5_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s1_folded_gh_dup_3_hist_5_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {s1_folded_gh_dup_3_hist_5_folded_hist[4:0], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s1_folded_gh_dup_3_hist_5_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s1_folded_gh_dup_3_hist_5_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_4_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_4_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_4_folded_hist[6:5], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_4_folded_hist[4], + s1_folded_gh_dup_3_hist_4_folded_hist[3:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ s1_folded_gh_dup_3_hist_4_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {s1_folded_gh_dup_3_hist_4_folded_hist[5], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_4_folded_hist[4], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s1_folded_gh_dup_3_hist_4_folded_hist[3], + s1_folded_gh_dup_3_hist_4_folded_hist[2:0], + s1_folded_gh_dup_3_hist_4_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ s1_folded_gh_dup_3_hist_4_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_3_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_3_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_3_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_3_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {s1_folded_gh_dup_3_hist_3_folded_hist[5:0], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_3_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s1_folded_gh_dup_3_hist_3_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_2_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_2_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_2_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s1_folded_gh_dup_3_hist_2_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {s1_folded_gh_dup_3_hist_2_folded_hist[5:0], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s1_folded_gh_dup_3_hist_2_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) + ^ s1_folded_gh_dup_3_hist_2_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_1_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_1_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_1_folded_hist[9:2], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_1_folded_hist[1], + s1_folded_gh_dup_3_hist_1_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0 + ^ s1_folded_gh_dup_3_hist_1_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {s1_folded_gh_dup_3_hist_1_folded_hist[8:2], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_1_folded_hist[1], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s1_folded_gh_dup_3_hist_1_folded_hist[0], + s1_folded_gh_dup_3_hist_1_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 + ^ s1_folded_gh_dup_3_hist_1_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s1_FGH_src_hist_0_folded_hist + ((_s1_predicted_fh_dup_WIRE_56_3_0 + ? {s1_folded_gh_dup_3_hist_0_folded_hist[7:1], + s1_folded_gh_dup_3_hist_0_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_277} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_1 + ? {s1_folded_gh_dup_3_hist_0_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0} + : 8'h0) + | (_s1_predicted_fh_dup_WIRE_56_3_2 + ? {s1_folded_gh_dup_3_hist_0_folded_hist[5:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97 + .s3_FGH_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_FGH_src_hist_17_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_17_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_17_folded_hist[9], + s3_folded_gh_dup_3_hist_17_folded_hist[8:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_17_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s3_folded_gh_dup_3_hist_17_folded_hist[8], + s3_folded_gh_dup_3_hist_17_folded_hist[7:0], + s3_folded_gh_dup_3_hist_17_folded_hist[10], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_17_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_16_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_16_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_16_folded_hist[9], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s3_folded_gh_dup_3_hist_16_folded_hist[8], + s3_folded_gh_dup_3_hist_16_folded_hist[7:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_16_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s3_folded_gh_dup_3_hist_16_folded_hist[8], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s3_folded_gh_dup_3_hist_16_folded_hist[7], + s3_folded_gh_dup_3_hist_16_folded_hist[6:0], + s3_folded_gh_dup_3_hist_16_folded_hist[10], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_16_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_15_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_15_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_15_folded_hist[5], + s3_folded_gh_dup_3_hist_15_folded_hist[4:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_15_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s3_folded_gh_dup_3_hist_15_folded_hist[4], + s3_folded_gh_dup_3_hist_15_folded_hist[3:0], + s3_folded_gh_dup_3_hist_15_folded_hist[6], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_15_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_14_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_14_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_14_folded_hist[6:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {s3_folded_gh_dup_3_hist_14_folded_hist[5:0], + 1'h0, + _predictors_io_out_s3_full_pred_3_br_taken_mask_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s3_FGH_src_hist_13_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_13_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_13_folded_hist[7:4], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_13_folded_hist[3], + s3_folded_gh_dup_3_hist_13_folded_hist[2:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_13_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {s3_folded_gh_dup_3_hist_13_folded_hist[6:4], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_13_folded_hist[3], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s3_folded_gh_dup_3_hist_13_folded_hist[2], + s3_folded_gh_dup_3_hist_13_folded_hist[1:0], + s3_folded_gh_dup_3_hist_13_folded_hist[8], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_13_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_12_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_12_folded_hist : 4'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_12_folded_hist[2:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0} + : 4'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {s3_folded_gh_dup_3_hist_12_folded_hist[1:0], + 1'h0, + _predictors_io_out_s3_full_pred_3_br_taken_mask_1} + : 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .s3_FGH_src_hist_11_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_11_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_11_folded_hist[6:2], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2) + ^ s3_folded_gh_dup_3_hist_11_folded_hist[1], + s3_folded_gh_dup_3_hist_11_folded_hist[0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_11_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {s3_folded_gh_dup_3_hist_11_folded_hist[5:2], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2) + ^ s3_folded_gh_dup_3_hist_11_folded_hist[1], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3) + ^ s3_folded_gh_dup_3_hist_11_folded_hist[0], + s3_folded_gh_dup_3_hist_11_folded_hist[7], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_11_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_10_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_10_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_10_folded_hist[7:5], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_10_folded_hist[4], + s3_folded_gh_dup_3_hist_10_folded_hist[3:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_10_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {s3_folded_gh_dup_3_hist_10_folded_hist[6:5], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_10_folded_hist[4], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s3_folded_gh_dup_3_hist_10_folded_hist[3], + s3_folded_gh_dup_3_hist_10_folded_hist[2:0], + s3_folded_gh_dup_3_hist_10_folded_hist[8], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_10_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_9_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_9_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_9_folded_hist[5:4], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_9_folded_hist[3], + s3_folded_gh_dup_3_hist_9_folded_hist[2:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_9_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {s3_folded_gh_dup_3_hist_9_folded_hist[4], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_9_folded_hist[3], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s3_folded_gh_dup_3_hist_9_folded_hist[2], + s3_folded_gh_dup_3_hist_9_folded_hist[1:0], + s3_folded_gh_dup_3_hist_9_folded_hist[6], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_9_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_8_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_8_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s3_folded_gh_dup_3_hist_8_folded_hist[6], + s3_folded_gh_dup_3_hist_8_folded_hist[5:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_8_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s3_folded_gh_dup_3_hist_8_folded_hist[5], + s3_folded_gh_dup_3_hist_8_folded_hist[4:0], + s3_folded_gh_dup_3_hist_8_folded_hist[7], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s3_folded_gh_dup_3_hist_8_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_7_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_7_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_7_folded_hist[5:1], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) + ^ s3_folded_gh_dup_3_hist_7_folded_hist[0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_7_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {s3_folded_gh_dup_3_hist_7_folded_hist[4:1], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) + ^ s3_folded_gh_dup_3_hist_7_folded_hist[0], + 1'h0, + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_7_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_6_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_6_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_6_folded_hist[7], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s3_folded_gh_dup_3_hist_6_folded_hist[6], + s3_folded_gh_dup_3_hist_6_folded_hist[5:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_6_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s3_folded_gh_dup_3_hist_6_folded_hist[6], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) + ^ s3_folded_gh_dup_3_hist_6_folded_hist[5], + s3_folded_gh_dup_3_hist_6_folded_hist[4:0], + s3_folded_gh_dup_3_hist_6_folded_hist[8], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_6_folded_hist[7]} + : 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_5_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_5_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_5_folded_hist[5:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s3_folded_gh_dup_3_hist_5_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {s3_folded_gh_dup_3_hist_5_folded_hist[4:0], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s3_folded_gh_dup_3_hist_5_folded_hist[6], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s3_folded_gh_dup_3_hist_5_folded_hist[5]} + : 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_4_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_4_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_4_folded_hist[6:5], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_4_folded_hist[4], + s3_folded_gh_dup_3_hist_4_folded_hist[3:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_4_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {s3_folded_gh_dup_3_hist_4_folded_hist[5], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_4_folded_hist[4], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s3_folded_gh_dup_3_hist_4_folded_hist[3], + s3_folded_gh_dup_3_hist_4_folded_hist[2:0], + s3_folded_gh_dup_3_hist_4_folded_hist[7], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_4_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_3_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_3_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_3_folded_hist[6:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_3_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {s3_folded_gh_dup_3_hist_3_folded_hist[5:0], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_3_folded_hist[7], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s3_folded_gh_dup_3_hist_3_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_2_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_2_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_2_folded_hist[6:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s3_folded_gh_dup_3_hist_2_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {s3_folded_gh_dup_3_hist_2_folded_hist[5:0], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s3_folded_gh_dup_3_hist_2_folded_hist[7], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) + ^ s3_folded_gh_dup_3_hist_2_folded_hist[6]} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_1_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_1_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_1_folded_hist[9:2], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_1_folded_hist[1], + s3_folded_gh_dup_3_hist_1_folded_hist[0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_1_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {s3_folded_gh_dup_3_hist_1_folded_hist[8:2], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_1_folded_hist[1], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s3_folded_gh_dup_3_hist_1_folded_hist[0], + s3_folded_gh_dup_3_hist_1_folded_hist[10], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_1_folded_hist[9]} + : 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97 + .s3_FGH_src_hist_0_folded_hist + ((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_0_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_1 + ? {s3_folded_gh_dup_3_hist_0_folded_hist[6:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0} + : 8'h0) + | (_s3_predicted_fh_dup_WIRE_56_3_2 + ? {s3_folded_gh_dup_3_hist_0_folded_hist[5:0], + 1'h0, + _predictors_io_out_s3_full_pred_3_br_taken_mask_1} + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97 + .redirect_FGHT_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_FGHT_src_hist_17_folded_hist (_GEN_81[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_16_folded_hist (_GEN_82[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_15_folded_hist (_GEN_83[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_14_folded_hist (_GEN_84[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_13_folded_hist (_GEN_85[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_12_folded_hist (_GEN_86[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_11_folded_hist (_GEN_87[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_10_folded_hist (_GEN_88[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_9_folded_hist (_GEN_89[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_8_folded_hist (_GEN_90[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_7_folded_hist (_GEN_91[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_6_folded_hist (_GEN_92[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_5_folded_hist (_GEN_93[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_4_folded_hist (_GEN_94[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_3_folded_hist (_GEN_95[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_2_folded_hist (_GEN_96[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_1_folded_hist (_GEN_97[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .redirect_FGHT_src_hist_0_folded_hist (_GEN_98[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24 + .stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_3_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_3_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_3_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_3_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_3_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_3_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_3_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_3_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_3_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_3_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_3_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_3_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_3_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_3_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_3_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_3_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_3_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_3_hist_0_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63 + .out_res_hist_17_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist), + .out_res_hist_16_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist), + .out_res_hist_15_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist), + .out_res_hist_14_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist), + .out_res_hist_13_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist), + .out_res_hist_12_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist), + .out_res_hist_11_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist), + .out_res_hist_10_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist), + .out_res_hist_9_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist), + .out_res_hist_8_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist), + .out_res_hist_7_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist), + .out_res_hist_6_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist), + .out_res_hist_5_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist), + .out_res_hist_4_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist), + .out_res_hist_3_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist), + .out_res_hist_2_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist), + .out_res_hist_1_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist), + .out_res_hist_0_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist) + ); + PriorityMuxModule_8 s0_ghist_ptr_dup_0_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_GHPtr_sel + (s2_redirect_dup_0 & ~s3_redirect_dup_0 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_GHPtr_src_flag + (_s2_predicted_ghist_ptr_dup_WIRE_56_0_0 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[8]) + | _s2_predicted_ghist_ptr_dup_WIRE_56_0_1 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[8]) + | _s2_predicted_ghist_ptr_dup_WIRE_56_0_2 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .s2_GHPtr_src_value + ((_s2_predicted_ghist_ptr_dup_WIRE_56_0_0 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_WIRE_56_0_1 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_WIRE_56_0_2 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[7:0] + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .s1_GHPtr_sel + (s1_valid_dup_3 & ~s2_redirect_dup_0 & ~s3_redirect_dup_0 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_GHPtr_src_flag + (_s1_predicted_ghist_ptr_dup_WIRE_56_0_0 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[8]) + | _s1_predicted_ghist_ptr_dup_WIRE_56_0_1 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[8]) + | _s1_predicted_ghist_ptr_dup_WIRE_56_0_2 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .s1_GHPtr_src_value + ((_s1_predicted_ghist_ptr_dup_WIRE_56_0_0 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_WIRE_56_0_1 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_WIRE_56_0_2 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[7:0] + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .s3_GHPtr_sel (s3_redirect_dup_0 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_GHPtr_src_flag + (_s3_predicted_ghist_ptr_dup_WIRE_56_0_0 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[8]) + | _s3_predicted_ghist_ptr_dup_WIRE_56_0_1 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[8]) + | _s3_predicted_ghist_ptr_dup_WIRE_56_0_2 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .s3_GHPtr_src_value + ((_s3_predicted_ghist_ptr_dup_WIRE_56_0_0 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_WIRE_56_0_1 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_WIRE_56_0_2 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[7:0] + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .redirect_GHPtr_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_1[8])), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_1[7:0]), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_0_flag), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_0_value), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + .out_res_flag (_s0_ghist_ptr_dup_0_ppm_out_res_flag), + .out_res_value (_s0_ghist_ptr_dup_0_ppm_out_res_value) + ); + PriorityMuxModule_8 s0_ghist_ptr_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_GHPtr_sel + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_GHPtr_src_flag + (_s2_predicted_ghist_ptr_dup_WIRE_56_1_0 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[8]) + | _s2_predicted_ghist_ptr_dup_WIRE_56_1_1 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[8]) + | _s2_predicted_ghist_ptr_dup_WIRE_56_1_2 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .s2_GHPtr_src_value + ((_s2_predicted_ghist_ptr_dup_WIRE_56_1_0 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_WIRE_56_1_1 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_WIRE_56_1_2 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[7:0] + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .s1_GHPtr_sel + (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_GHPtr_src_flag + (_s1_predicted_ghist_ptr_dup_WIRE_56_1_0 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[8]) + | _s1_predicted_ghist_ptr_dup_WIRE_56_1_1 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[8]) + | _s1_predicted_ghist_ptr_dup_WIRE_56_1_2 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .s1_GHPtr_src_value + ((_s1_predicted_ghist_ptr_dup_WIRE_56_1_0 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_WIRE_56_1_1 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_WIRE_56_1_2 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[7:0] + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .s3_GHPtr_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_GHPtr_src_flag + (_s3_predicted_ghist_ptr_dup_WIRE_56_1_0 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[8]) + | _s3_predicted_ghist_ptr_dup_WIRE_56_1_1 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[8]) + | _s3_predicted_ghist_ptr_dup_WIRE_56_1_2 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .s3_GHPtr_src_value + ((_s3_predicted_ghist_ptr_dup_WIRE_56_1_0 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_WIRE_56_1_1 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_WIRE_56_1_2 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[7:0] + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .redirect_GHPtr_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_3[8])), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_3[7:0]), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_1_flag), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_1_value), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + .out_res_flag (_s0_ghist_ptr_dup_1_ppm_out_res_flag), + .out_res_value (_s0_ghist_ptr_dup_1_ppm_out_res_value) + ); + PriorityMuxModule_8 s0_ghist_ptr_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_GHPtr_sel + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_GHPtr_src_flag + (_s2_predicted_ghist_ptr_dup_WIRE_56_2_0 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[8]) + | _s2_predicted_ghist_ptr_dup_WIRE_56_2_1 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[8]) + | _s2_predicted_ghist_ptr_dup_WIRE_56_2_2 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .s2_GHPtr_src_value + ((_s2_predicted_ghist_ptr_dup_WIRE_56_2_0 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_WIRE_56_2_1 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_WIRE_56_2_2 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[7:0] + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .s1_GHPtr_sel + (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_GHPtr_src_flag + (_s1_predicted_ghist_ptr_dup_WIRE_56_2_0 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[8]) + | _s1_predicted_ghist_ptr_dup_WIRE_56_2_1 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[8]) + | _s1_predicted_ghist_ptr_dup_WIRE_56_2_2 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .s1_GHPtr_src_value + ((_s1_predicted_ghist_ptr_dup_WIRE_56_2_0 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_WIRE_56_2_1 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_WIRE_56_2_2 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[7:0] + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .s3_GHPtr_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_GHPtr_src_flag + (_s3_predicted_ghist_ptr_dup_WIRE_56_2_0 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[8]) + | _s3_predicted_ghist_ptr_dup_WIRE_56_2_1 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[8]) + | _s3_predicted_ghist_ptr_dup_WIRE_56_2_2 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .s3_GHPtr_src_value + ((_s3_predicted_ghist_ptr_dup_WIRE_56_2_0 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_WIRE_56_2_1 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_WIRE_56_2_2 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[7:0] + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .redirect_GHPtr_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_5[8])), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_5[7:0]), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_2_flag), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_2_value), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + .out_res_flag (_s0_ghist_ptr_dup_2_ppm_out_res_flag), + .out_res_value (_s0_ghist_ptr_dup_2_ppm_out_res_value) + ); + PriorityMuxModule_8 s0_ghist_ptr_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_GHPtr_sel + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_GHPtr_src_flag + (_s2_predicted_ghist_ptr_dup_WIRE_56_3_0 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[8]) + | _s2_predicted_ghist_ptr_dup_WIRE_56_3_1 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[8]) + | _s2_predicted_ghist_ptr_dup_WIRE_56_3_2 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .s2_GHPtr_src_value + ((_s2_predicted_ghist_ptr_dup_WIRE_56_3_0 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_WIRE_56_3_1 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_WIRE_56_3_2 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[7:0] + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .s1_GHPtr_sel + (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_GHPtr_src_flag + (_s1_predicted_ghist_ptr_dup_WIRE_56_3_0 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[8]) + | _s1_predicted_ghist_ptr_dup_WIRE_56_3_1 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[8]) + | _s1_predicted_ghist_ptr_dup_WIRE_56_3_2 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .s1_GHPtr_src_value + ((_s1_predicted_ghist_ptr_dup_WIRE_56_3_0 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_WIRE_56_3_1 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_WIRE_56_3_2 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[7:0] + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .s3_GHPtr_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_GHPtr_src_flag + (_s3_predicted_ghist_ptr_dup_WIRE_56_3_0 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[8]) + | _s3_predicted_ghist_ptr_dup_WIRE_56_3_1 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[8]) + | _s3_predicted_ghist_ptr_dup_WIRE_56_3_2 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .s3_GHPtr_src_value + ((_s3_predicted_ghist_ptr_dup_WIRE_56_3_0 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_WIRE_56_3_1 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_WIRE_56_3_2 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[7:0] + : 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .redirect_GHPtr_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_7[8])), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21 + .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_7[7:0]), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_3_flag), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_3_value), // src/main/scala/xiangshan/frontend/BPU.scala:322:63 + .out_res_flag (_s0_ghist_ptr_dup_3_ppm_out_res_flag), + .out_res_value (_s0_ghist_ptr_dup_3_ppm_out_res_value) + ); + PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_AFHOB_sel + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_sel + (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_AFHOB_src_afhob_5_bits_0 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_5_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_5_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_5_bits_3 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_4_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_4_bits_3 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_3_bits_0 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_3_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_3_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_2_bits_0 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_2_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_2_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_2_bits_3 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_1_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_1_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_0_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .out_res_afhob_5_bits_0 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0), + .out_res_afhob_5_bits_1 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1), + .out_res_afhob_5_bits_2 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2), + .out_res_afhob_5_bits_3 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3), + .out_res_afhob_4_bits_0 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0), + .out_res_afhob_4_bits_1 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1), + .out_res_afhob_4_bits_2 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2), + .out_res_afhob_4_bits_3 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_3), + .out_res_afhob_3_bits_0 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0), + .out_res_afhob_3_bits_1 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1), + .out_res_afhob_3_bits_2 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2), + .out_res_afhob_3_bits_3 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3), + .out_res_afhob_2_bits_0 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0), + .out_res_afhob_2_bits_1 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1), + .out_res_afhob_2_bits_2 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2), + .out_res_afhob_2_bits_3 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3), + .out_res_afhob_1_bits_0 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0), + .out_res_afhob_1_bits_1 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1), + .out_res_afhob_1_bits_2 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2), + .out_res_afhob_1_bits_3 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3), + .out_res_afhob_0_bits_0 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0), + .out_res_afhob_0_bits_1 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1), + .out_res_afhob_0_bits_2 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2), + .out_res_afhob_0_bits_3 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3) + ); + PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_AFHOB_sel + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_sel + (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_AFHOB_src_afhob_5_bits_0 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_5_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_5_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_5_bits_3 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_4_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_4_bits_3 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_3_bits_0 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_3_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_3_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_2_bits_0 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_2_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_2_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_2_bits_3 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_1_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_1_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_0_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .out_res_afhob_5_bits_0 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0), + .out_res_afhob_5_bits_1 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1), + .out_res_afhob_5_bits_2 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2), + .out_res_afhob_5_bits_3 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3), + .out_res_afhob_4_bits_0 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0), + .out_res_afhob_4_bits_1 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1), + .out_res_afhob_4_bits_2 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2), + .out_res_afhob_4_bits_3 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3), + .out_res_afhob_3_bits_0 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0), + .out_res_afhob_3_bits_1 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1), + .out_res_afhob_3_bits_2 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2), + .out_res_afhob_3_bits_3 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3), + .out_res_afhob_2_bits_0 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0), + .out_res_afhob_2_bits_1 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1), + .out_res_afhob_2_bits_2 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2), + .out_res_afhob_2_bits_3 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3), + .out_res_afhob_1_bits_0 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0), + .out_res_afhob_1_bits_1 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1), + .out_res_afhob_1_bits_2 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2), + .out_res_afhob_1_bits_3 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3), + .out_res_afhob_0_bits_0 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0), + .out_res_afhob_0_bits_1 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1), + .out_res_afhob_0_bits_2 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2), + .out_res_afhob_0_bits_3 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3) + ); + PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_AFHOB_sel + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_sel + (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_AFHOB_src_afhob_5_bits_0 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_5_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_5_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_5_bits_3 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_4_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_4_bits_3 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_3_bits_0 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_3_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_3_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_2_bits_0 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_2_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_2_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_2_bits_3 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_1_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_1_bits_2 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_0_bits_1 + (_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + .redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20 + .stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85 + .out_res_afhob_5_bits_0 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0), + .out_res_afhob_5_bits_1 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1), + .out_res_afhob_5_bits_2 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2), + .out_res_afhob_5_bits_3 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3), + .out_res_afhob_4_bits_0 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0), + .out_res_afhob_4_bits_1 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1), + .out_res_afhob_4_bits_2 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2), + .out_res_afhob_4_bits_3 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_3), + .out_res_afhob_3_bits_0 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0), + .out_res_afhob_3_bits_1 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1), + .out_res_afhob_3_bits_2 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2), + .out_res_afhob_3_bits_3 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3), + .out_res_afhob_2_bits_0 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0), + .out_res_afhob_2_bits_1 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1), + .out_res_afhob_2_bits_2 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2), + .out_res_afhob_2_bits_3 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3), + .out_res_afhob_1_bits_0 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0), + .out_res_afhob_1_bits_1 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1), + .out_res_afhob_1_bits_2 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2), + .out_res_afhob_1_bits_3 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3), + .out_res_afhob_0_bits_0 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0), + .out_res_afhob_0_bits_1 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1), + .out_res_afhob_0_bits_2 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2), + .out_res_afhob_0_bits_3 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3) + ); + PriorityMuxModule_16 s0_last_br_num_oh_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_BrNumOH_sel + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_BrNumOH_src + ({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1 & ~_GEN_25 + & _predictors_io_out_s2_full_pred_1_hit, + _predictors_io_out_s2_full_pred_1_slot_valids_0 + & (_GEN_25 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1) + & _predictors_io_out_s2_full_pred_1_hit, + ~_predictors_io_out_s2_full_pred_1_hit + | ~(_predictors_io_out_s2_full_pred_1_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :614:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97} + .s1_BrNumOH_sel + (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_BrNumOH_src + ({_s1_predicted_fh_dup_WIRE_21_1 & ~_GEN_9 & _predictors_io_out_s1_full_pred_1_hit, + _predictors_io_out_s1_full_pred_1_slot_valids_0 & _GEN_10 + & _predictors_io_out_s1_full_pred_1_hit, + ~_predictors_io_out_s1_full_pred_1_hit | ~_GEN_8}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :511:118, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,97} + .s3_BrNumOH_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_BrNumOH_src + ({_s3_predicted_fh_dup_WIRE_21_1 & ~_GEN_36 & _predictors_io_out_s3_full_pred_1_hit, + _predictors_io_out_s3_full_pred_1_slot_valids_0 + & (_GEN_36 | ~_s3_predicted_fh_dup_WIRE_21_1) + & _predictors_io_out_s3_full_pred_1_hit, + ~_predictors_io_out_s3_full_pred_1_hit + | ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 + | _s3_predicted_fh_dup_WIRE_21_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :699:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97} + .redirect_BrNumOH_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_BrNumOH_src (_thisBrNumOH_dup_T_1[2:0]), // src/main/scala/chisel3/util/OneHot.scala:65:{12,27} + .stallBrNumOH_src (s0_last_br_num_oh_reg_dup_1), // src/main/scala/xiangshan/frontend/BPU.scala:291:73 + .out_res (_s0_last_br_num_oh_dup_1_ppm_out_res) + ); + PriorityMuxModule_16 s0_last_br_num_oh_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_BrNumOH_sel + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_BrNumOH_src + ({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1 & ~_GEN_26 + & _predictors_io_out_s2_full_pred_2_hit, + _predictors_io_out_s2_full_pred_2_slot_valids_0 + & (_GEN_26 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1) + & _predictors_io_out_s2_full_pred_2_hit, + ~_predictors_io_out_s2_full_pred_2_hit + | ~(_predictors_io_out_s2_full_pred_2_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :614:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97} + .s1_BrNumOH_sel + (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_BrNumOH_src + ({_s1_predicted_fh_dup_WIRE_35_1 & ~_GEN_12 & _predictors_io_out_s1_full_pred_2_hit, + _predictors_io_out_s1_full_pred_2_slot_valids_0 & _GEN_13 + & _predictors_io_out_s1_full_pred_2_hit, + ~_predictors_io_out_s1_full_pred_2_hit | ~_GEN_11}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :511:118, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,97} + .s3_BrNumOH_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_BrNumOH_src + ({_s3_predicted_fh_dup_WIRE_35_1 & ~_GEN_37 & _predictors_io_out_s3_full_pred_2_hit, + _predictors_io_out_s3_full_pred_2_slot_valids_0 + & (_GEN_37 | ~_s3_predicted_fh_dup_WIRE_35_1) + & _predictors_io_out_s3_full_pred_2_hit, + ~_predictors_io_out_s3_full_pred_2_hit + | ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 + | _s3_predicted_fh_dup_WIRE_35_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :699:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97} + .redirect_BrNumOH_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_BrNumOH_src (_thisBrNumOH_dup_T_2[2:0]), // src/main/scala/chisel3/util/OneHot.scala:65:{12,27} + .stallBrNumOH_src (s0_last_br_num_oh_reg_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:291:73 + .out_res (_s0_last_br_num_oh_dup_2_ppm_out_res) + ); + PriorityMuxModule_16 s0_last_br_num_oh_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_BrNumOH_sel + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_BrNumOH_src + ({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1 & ~_GEN_27 + & _predictors_io_out_s2_full_pred_3_hit, + _predictors_io_out_s2_full_pred_3_slot_valids_0 + & (_GEN_27 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1) + & _predictors_io_out_s2_full_pred_3_hit, + ~_predictors_io_out_s2_full_pred_3_hit + | ~(_predictors_io_out_s2_full_pred_3_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :614:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97} + .s1_BrNumOH_sel + (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 + & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_BrNumOH_src + ({_s1_predicted_fh_dup_WIRE_49_1 & ~_GEN_15 & _predictors_io_out_s1_full_pred_3_hit, + _predictors_io_out_s1_full_pred_3_slot_valids_0 & _GEN_16 + & _predictors_io_out_s1_full_pred_3_hit, + ~_predictors_io_out_s1_full_pred_3_hit | ~_GEN_14}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :511:118, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,97} + .s3_BrNumOH_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_BrNumOH_src + ({_s3_predicted_fh_dup_WIRE_49_1 & ~_GEN_38 & _predictors_io_out_s3_full_pred_3_hit, + _predictors_io_out_s3_full_pred_3_slot_valids_0 + & (_GEN_38 | ~_s3_predicted_fh_dup_WIRE_49_1) + & _predictors_io_out_s3_full_pred_3_hit, + ~_predictors_io_out_s3_full_pred_3_hit + | ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 + | _s3_predicted_fh_dup_WIRE_49_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :699:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97} + .redirect_BrNumOH_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40 + .redirect_BrNumOH_src (_thisBrNumOH_dup_T_3[2:0]), // src/main/scala/chisel3/util/OneHot.scala:65:{12,27} + .stallBrNumOH_src (s0_last_br_num_oh_reg_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:291:73 + .out_res (_s0_last_br_num_oh_dup_3_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_0_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_0_T_1 & ~_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (~(|s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:58, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_0_T & ~_ghv_wens_0_T_1 & ~_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (~(|s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :494:58, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (~(|s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:58, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (~(|do_redirect_dup_3_bits_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :760:50, :763:52 + .out_res (_ghv_write_datas_0_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_1_T_1 & ~_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_1_T & ~_ghv_wens_1_T_1 & ~_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_1_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_2_T_1 & ~_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_2_T & ~_ghv_wens_2_T_1 & ~_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_2_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_3_T_1 & ~_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_3_T & ~_ghv_wens_3_T_1 & ~_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_3_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_4_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_4_T_1 & ~_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_4_T & ~_ghv_wens_4_T_1 & ~_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_4_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_5_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_5_T_1 & ~_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_5_T & ~_ghv_wens_5_T_1 & ~_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_5_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_6_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_6_T_1 & ~_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_6_T & ~_ghv_wens_6_T_1 & ~_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_6_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_7_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_7_T_1 & ~_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_7_T & ~_ghv_wens_7_T_1 & ~_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_7_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_8_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_8_T_1 & ~_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_8_T & ~_ghv_wens_8_T_1 & ~_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_8_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_9_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_9_T_1 & ~_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_9_T & ~_ghv_wens_9_T_1 & ~_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_9_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_10_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_10_T_1 & ~_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_10_T & ~_ghv_wens_10_T_1 & ~_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_10_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_11_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_11_T_1 & ~_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_11_T & ~_ghv_wens_11_T_1 & ~_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_11_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_12_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_12_T_1 & ~_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_12_T & ~_ghv_wens_12_T_1 & ~_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_12_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_13_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_13_T_1 & ~_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_13_T & ~_ghv_wens_13_T_1 & ~_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_13_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_14_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_14_T_1 & ~_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_14_T & ~_ghv_wens_14_T_1 & ~_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_14_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_15_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_15_T_1 & ~_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h10 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_15_T & ~_ghv_wens_15_T_1 & ~_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h10 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h10 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h10 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_15_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_16_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_16_T_1 & ~_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h11 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_16_T & ~_ghv_wens_16_T_1 & ~_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h11 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h11 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h10 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h11 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_16_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_17_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_17_T_1 & ~_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_17_T & ~_ghv_wens_17_T_1 & ~_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h12 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h12 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h11 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h12 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_17_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_18_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_18_T_1 & ~_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h13 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_18_T & ~_ghv_wens_18_T_1 & ~_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h13 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h13 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h12 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h13 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_18_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_19_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_19_T_1 & ~_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h14 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_19_T & ~_ghv_wens_19_T_1 & ~_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h14 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h14 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h13 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h14 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_19_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_20_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_20_T_1 & ~_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h15 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_20_T & ~_ghv_wens_20_T_1 & ~_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h15 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h15 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h14 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h15 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_20_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_21_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_21_T_1 & ~_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h16 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_21_T & ~_ghv_wens_21_T_1 & ~_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h16 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h16 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h15 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h16 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_21_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_22_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_22_T_1 & ~_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h17 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_22_T & ~_ghv_wens_22_T_1 & ~_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h17 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h17 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h16 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h17 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_22_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_23_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_23_T_1 & ~_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h18 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_23_T & ~_ghv_wens_23_T_1 & ~_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h18 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h18 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h17 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h18 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_23_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_24_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_24_T_1 & ~_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h19 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_24_T & ~_ghv_wens_24_T_1 & ~_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h19 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h19 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h18 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h19 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_24_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_25_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_25_T_1 & ~_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_25_T & ~_ghv_wens_25_T_1 & ~_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h19 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1A & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_25_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_26_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_26_T_1 & ~_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_26_T & ~_ghv_wens_26_T_1 & ~_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1A & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1B & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_26_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_27_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_27_T_1 & ~_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_27_T & ~_ghv_wens_27_T_1 & ~_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1B & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1C & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_27_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_28_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_28_T_1 & ~_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_28_T & ~_ghv_wens_28_T_1 & ~_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1C & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1D & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_28_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_29_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_29_T_1 & ~_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_29_T & ~_ghv_wens_29_T_1 & ~_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1D & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1E & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_29_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_30_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_30_T_1 & ~_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_30_T & ~_ghv_wens_30_T_1 & ~_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1E & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1F & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_30_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_31_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_31_T_1 & ~_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h20 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_31_T & ~_ghv_wens_31_T_1 & ~_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h20 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h20 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1F & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h20 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_31_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_32_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_32_T_1 & ~_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h21 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_32_T & ~_ghv_wens_32_T_1 & ~_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h21 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h21 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h20 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h21 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_32_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_33_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_33_T_1 & ~_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h22 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_33_T & ~_ghv_wens_33_T_1 & ~_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h22 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h22 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h21 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h22 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_33_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_34_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_34_T_1 & ~_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h23 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_34_T & ~_ghv_wens_34_T_1 & ~_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h23 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h23 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h22 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h23 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_34_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_35_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_35_T_1 & ~_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h24 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_35_T & ~_ghv_wens_35_T_1 & ~_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h24 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h24 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h23 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h24 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_35_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_36_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_36_T_1 & ~_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h25 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_36_T & ~_ghv_wens_36_T_1 & ~_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h25 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h25 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h24 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h25 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_36_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_37_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_37_T_1 & ~_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h26 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_37_T & ~_ghv_wens_37_T_1 & ~_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h26 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h26 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h25 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h26 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_37_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_38_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_38_T_1 & ~_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h27 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_38_T & ~_ghv_wens_38_T_1 & ~_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h27 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h27 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h26 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h27 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_38_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_39_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_39_T_1 & ~_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h28 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_39_T & ~_ghv_wens_39_T_1 & ~_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h28 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h28 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h27 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h28 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_39_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_40_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_40_T_1 & ~_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h29 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_40_T & ~_ghv_wens_40_T_1 & ~_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h29 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h29 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h28 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h29 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_40_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_41_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_41_T_1 & ~_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_41_T & ~_ghv_wens_41_T_1 & ~_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h29 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2A & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_41_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_42_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_42_T_1 & ~_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_42_T & ~_ghv_wens_42_T_1 & ~_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2A & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2B & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_42_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_43_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_43_T_1 & ~_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_43_T & ~_ghv_wens_43_T_1 & ~_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2B & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2C & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_43_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_44_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_44_T_1 & ~_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_44_T & ~_ghv_wens_44_T_1 & ~_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2C & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2D & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_44_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_45_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_45_T_1 & ~_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_45_T & ~_ghv_wens_45_T_1 & ~_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2D & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2E & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_45_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_46_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_46_T_1 & ~_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_46_T & ~_ghv_wens_46_T_1 & ~_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2E & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2F & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_46_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_47_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_47_T_1 & ~_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h30 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_47_T & ~_ghv_wens_47_T_1 & ~_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h30 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h30 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2F & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h30 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_47_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_48_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_48_T_1 & ~_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h31 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_48_T & ~_ghv_wens_48_T_1 & ~_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h31 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h31 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h30 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h31 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_48_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_49_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_49_T_1 & ~_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h32 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_49_T & ~_ghv_wens_49_T_1 & ~_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h32 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h32 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h31 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h32 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_49_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_50_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_50_T_1 & ~_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h33 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_50_T & ~_ghv_wens_50_T_1 & ~_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h33 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h33 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h32 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h33 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_50_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_51_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_51_T_1 & ~_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h34 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_51_T & ~_ghv_wens_51_T_1 & ~_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h34 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h34 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h33 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h34 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_51_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_52_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_52_T_1 & ~_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h35 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_52_T & ~_ghv_wens_52_T_1 & ~_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h35 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h35 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h34 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h35 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_52_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_53_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_53_T_1 & ~_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h36 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_53_T & ~_ghv_wens_53_T_1 & ~_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h36 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h36 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h35 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h36 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_53_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_54_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_54_T_1 & ~_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h37 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_54_T & ~_ghv_wens_54_T_1 & ~_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h37 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h37 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h36 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h37 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_54_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_55_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_55_T_1 & ~_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h38 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_55_T & ~_ghv_wens_55_T_1 & ~_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h38 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h38 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h37 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h38 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_55_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_56_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_56_T_1 & ~_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h39 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_56_T & ~_ghv_wens_56_T_1 & ~_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h39 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h39 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h38 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h39 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_56_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_57_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_57_T_1 & ~_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_57_T & ~_ghv_wens_57_T_1 & ~_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h39 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3A & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_57_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_58_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_58_T_1 & ~_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_58_T & ~_ghv_wens_58_T_1 & ~_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3A & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3B & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_58_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_59_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_59_T_1 & ~_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_59_T & ~_ghv_wens_59_T_1 & ~_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3B & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3C & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_59_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_60_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_60_T_1 & ~_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_60_T & ~_ghv_wens_60_T_1 & ~_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3C & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3D & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_60_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_61_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_61_T_1 & ~_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_61_T & ~_ghv_wens_61_T_1 & ~_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3D & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3E & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_61_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_62_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_62_T_1 & ~_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_62_T & ~_ghv_wens_62_T_1 & ~_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3E & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3F & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_62_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_63_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_63_T_1 & ~_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h40 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_63_T & ~_ghv_wens_63_T_1 & ~_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h40 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h40 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3F & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h40 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_63_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_64_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_64_T_1 & ~_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h41 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_64_T & ~_ghv_wens_64_T_1 & ~_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h41 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h41 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h40 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h41 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_64_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_65_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_65_T_1 & ~_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h42 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_65_T & ~_ghv_wens_65_T_1 & ~_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h42 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h42 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h41 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h42 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_65_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_66_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_66_T_1 & ~_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h43 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_66_T & ~_ghv_wens_66_T_1 & ~_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h43 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h43 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h42 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h43 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_66_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_67_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_67_T_1 & ~_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h44 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_67_T & ~_ghv_wens_67_T_1 & ~_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h44 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h44 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h43 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h44 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_67_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_68_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_68_T_1 & ~_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h45 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_68_T & ~_ghv_wens_68_T_1 & ~_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h45 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h45 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h44 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h45 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_68_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_69_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_69_T_1 & ~_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h46 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_69_T & ~_ghv_wens_69_T_1 & ~_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h46 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h46 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h45 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h46 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_69_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_70_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_70_T_1 & ~_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h47 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_70_T & ~_ghv_wens_70_T_1 & ~_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h47 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h47 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h46 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h47 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_70_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_71_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_71_T_1 & ~_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h48 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_71_T & ~_ghv_wens_71_T_1 & ~_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h48 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h48 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h47 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h48 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_71_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_72_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_72_T_1 & ~_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h49 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_72_T & ~_ghv_wens_72_T_1 & ~_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h49 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h49 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h48 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h49 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_72_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_73_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_73_T_1 & ~_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_73_T & ~_ghv_wens_73_T_1 & ~_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h49 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4A & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_73_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_74_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_74_T_1 & ~_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_74_T & ~_ghv_wens_74_T_1 & ~_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4A & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4B & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_74_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_75_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_75_T_1 & ~_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_75_T & ~_ghv_wens_75_T_1 & ~_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4B & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4C & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_75_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_76_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_76_T_1 & ~_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_76_T & ~_ghv_wens_76_T_1 & ~_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4C & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4D & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_76_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_77_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_77_T_1 & ~_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_77_T & ~_ghv_wens_77_T_1 & ~_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4D & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4E & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_77_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_78_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_78_T_1 & ~_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_78_T & ~_ghv_wens_78_T_1 & ~_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4E & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4F & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_78_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_79_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_79_T_1 & ~_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h50 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_79_T & ~_ghv_wens_79_T_1 & ~_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h50 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h50 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4F & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h50 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_79_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_80_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_80_T_1 & ~_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h51 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_80_T & ~_ghv_wens_80_T_1 & ~_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h51 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h51 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h50 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h51 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_80_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_81_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_81_T_1 & ~_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h52 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_81_T & ~_ghv_wens_81_T_1 & ~_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h52 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h52 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h51 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h52 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_81_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_82_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_82_T_1 & ~_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h53 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_82_T & ~_ghv_wens_82_T_1 & ~_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h53 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h53 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h52 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h53 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_82_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_83_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_83_T_1 & ~_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h54 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_83_T & ~_ghv_wens_83_T_1 & ~_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h54 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h54 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h53 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h54 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_83_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_84_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_84_T_1 & ~_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h55 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_84_T & ~_ghv_wens_84_T_1 & ~_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h55 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h55 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h54 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h55 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_84_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_85_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_85_T_1 & ~_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h56 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_85_T & ~_ghv_wens_85_T_1 & ~_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h56 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h56 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h55 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h56 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_85_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_86_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_86_T_1 & ~_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h57 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_86_T & ~_ghv_wens_86_T_1 & ~_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h57 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h57 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h56 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h57 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_86_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_87_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_87_T_1 & ~_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h58 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_87_T & ~_ghv_wens_87_T_1 & ~_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h58 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h58 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h57 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h58 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_87_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_88_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_88_T_1 & ~_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h59 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_88_T & ~_ghv_wens_88_T_1 & ~_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h59 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h59 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h58 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h59 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_88_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_89_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_89_T_1 & ~_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_89_T & ~_ghv_wens_89_T_1 & ~_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h59 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5A & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_89_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_90_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_90_T_1 & ~_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_90_T & ~_ghv_wens_90_T_1 & ~_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5A & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5B & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_90_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_91_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_91_T_1 & ~_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_91_T & ~_ghv_wens_91_T_1 & ~_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5B & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5C & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_91_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_92_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_92_T_1 & ~_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_92_T & ~_ghv_wens_92_T_1 & ~_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5C & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5D & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_92_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_93_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_93_T_1 & ~_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_93_T & ~_ghv_wens_93_T_1 & ~_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5D & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5E & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_93_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_94_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_94_T_1 & ~_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_94_T & ~_ghv_wens_94_T_1 & ~_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5E & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5F & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_94_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_95_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_95_T_1 & ~_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h60 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_95_T & ~_ghv_wens_95_T_1 & ~_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h60 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h60 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5F & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h60 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_95_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_96_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_96_T_1 & ~_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h61 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_96_T & ~_ghv_wens_96_T_1 & ~_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h61 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h61 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h60 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h61 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_96_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_97_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_97_T_1 & ~_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h62 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_97_T & ~_ghv_wens_97_T_1 & ~_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h62 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h62 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h61 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h62 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_97_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_98_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_98_T_1 & ~_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h63 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_98_T & ~_ghv_wens_98_T_1 & ~_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h63 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h63 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h62 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h63 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_98_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_99_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_99_T_1 & ~_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h64 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_99_T & ~_ghv_wens_99_T_1 & ~_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h64 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h64 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h63 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h64 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_99_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_100_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_100_T_1 & ~_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h65 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_100_T & ~_ghv_wens_100_T_1 & ~_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h65 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h65 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h64 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h65 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_100_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_101_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_101_T_1 & ~_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h66 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_101_T & ~_ghv_wens_101_T_1 & ~_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h66 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h66 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h65 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h66 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_101_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_102_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_102_T_1 & ~_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h67 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_102_T & ~_ghv_wens_102_T_1 & ~_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h67 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h67 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h66 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h67 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_102_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_103_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_103_T_1 & ~_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h68 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_103_T & ~_ghv_wens_103_T_1 & ~_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h68 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h68 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h67 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h68 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_103_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_104_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_104_T_1 & ~_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h69 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_104_T & ~_ghv_wens_104_T_1 & ~_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h69 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h69 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h68 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h69 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_104_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_105_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_105_T_1 & ~_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_105_T & ~_ghv_wens_105_T_1 & ~_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h69 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6A & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_105_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_106_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_106_T_1 & ~_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_106_T & ~_ghv_wens_106_T_1 & ~_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6A & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6B & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_106_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_107_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_107_T_1 & ~_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_107_T & ~_ghv_wens_107_T_1 & ~_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6B & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6C & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_107_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_108_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_108_T_1 & ~_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_108_T & ~_ghv_wens_108_T_1 & ~_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6C & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6D & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_108_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_109_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_109_T_1 & ~_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_109_T & ~_ghv_wens_109_T_1 & ~_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6D & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6E & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_109_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_110_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_110_T_1 & ~_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_110_T & ~_ghv_wens_110_T_1 & ~_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6E & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6F & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_110_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_111_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_111_T_1 & ~_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h70 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_111_T & ~_ghv_wens_111_T_1 & ~_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h70 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h70 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6F & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h70 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_111_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_112_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_112_T_1 & ~_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h71 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_112_T & ~_ghv_wens_112_T_1 & ~_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h71 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h71 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h70 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h71 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_112_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_113_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_113_T_1 & ~_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h72 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_113_T & ~_ghv_wens_113_T_1 & ~_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h72 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h72 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h71 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h72 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_113_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_114_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_114_T_1 & ~_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h73 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_114_T & ~_ghv_wens_114_T_1 & ~_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h73 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h73 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h72 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h73 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_114_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_115_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_115_T_1 & ~_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h74 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_115_T & ~_ghv_wens_115_T_1 & ~_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h74 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h74 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h73 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h74 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_115_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_116_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_116_T_1 & ~_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h75 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_116_T & ~_ghv_wens_116_T_1 & ~_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h75 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h75 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h74 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h75 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_116_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_117_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_117_T_1 & ~_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h76 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_117_T & ~_ghv_wens_117_T_1 & ~_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h76 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h76 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h75 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h76 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_117_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_118_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_118_T_1 & ~_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h77 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_118_T & ~_ghv_wens_118_T_1 & ~_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h77 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h77 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h76 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h77 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_118_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_119_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_119_T_1 & ~_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h78 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_119_T & ~_ghv_wens_119_T_1 & ~_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h78 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h78 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h77 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h78 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_119_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_120_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_120_T_1 & ~_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h79 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_120_T & ~_ghv_wens_120_T_1 & ~_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h79 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h79 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h78 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h79 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_120_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_121_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_121_T_1 & ~_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_121_T & ~_ghv_wens_121_T_1 & ~_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h79 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7A & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_121_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_122_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_122_T_1 & ~_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_122_T & ~_ghv_wens_122_T_1 & ~_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7A & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7B & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_122_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_123_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_123_T_1 & ~_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_123_T & ~_ghv_wens_123_T_1 & ~_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7B & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7C & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_123_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_124_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_124_T_1 & ~_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_124_T & ~_ghv_wens_124_T_1 & ~_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7C & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7D & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_124_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_125_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_125_T_1 & ~_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_125_T & ~_ghv_wens_125_T_1 & ~_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7D & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7E & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_125_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_126_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_126_T_1 & ~_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_126_T & ~_ghv_wens_126_T_1 & ~_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7E & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7F & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_126_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_127_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_127_T_1 & ~_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h80 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_127_T & ~_ghv_wens_127_T_1 & ~_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h80 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h80 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7F & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h80 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_127_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_128_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_128_T_1 & ~_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h81 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_128_T & ~_ghv_wens_128_T_1 & ~_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h81 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h81 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h80 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h81 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_128_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_129_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_129_T_1 & ~_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h82 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_129_T & ~_ghv_wens_129_T_1 & ~_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h82 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h82 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h81 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h82 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_129_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_130_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_130_T_1 & ~_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h83 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_130_T & ~_ghv_wens_130_T_1 & ~_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h83 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h83 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h82 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h83 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_130_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_131_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_131_T_1 & ~_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h84 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_131_T & ~_ghv_wens_131_T_1 & ~_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h84 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h84 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h83 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h84 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_131_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_132_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_132_T_1 & ~_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h85 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_132_T & ~_ghv_wens_132_T_1 & ~_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h85 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h85 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h84 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h85 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_132_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_133_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_133_T_1 & ~_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h86 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_133_T & ~_ghv_wens_133_T_1 & ~_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h86 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h86 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h85 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h86 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_133_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_134_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_134_T_1 & ~_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h87 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_134_T & ~_ghv_wens_134_T_1 & ~_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h87 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h87 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h86 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h87 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_134_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_135_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_135_T_1 & ~_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h88 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_135_T & ~_ghv_wens_135_T_1 & ~_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h88 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h88 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h87 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h88 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_135_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_136_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_136_T_1 & ~_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h89 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_136_T & ~_ghv_wens_136_T_1 & ~_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h89 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h89 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h88 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h89 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_136_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_137_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_137_T_1 & ~_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_137_T & ~_ghv_wens_137_T_1 & ~_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h89 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8A & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_137_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_138_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_138_T_1 & ~_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_138_T & ~_ghv_wens_138_T_1 & ~_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8A & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8B & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_138_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_139_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_139_T_1 & ~_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_139_T & ~_ghv_wens_139_T_1 & ~_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8B & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8C & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_139_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_140_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_140_T_1 & ~_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_140_T & ~_ghv_wens_140_T_1 & ~_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8C & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8D & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_140_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_141_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_141_T_1 & ~_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_141_T & ~_ghv_wens_141_T_1 & ~_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8D & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8E & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_141_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_142_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_142_T_1 & ~_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_142_T & ~_ghv_wens_142_T_1 & ~_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8E & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8F & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_142_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_143_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_143_T_1 & ~_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h90 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_143_T & ~_ghv_wens_143_T_1 & ~_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h90 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h90 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8F & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h90 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_143_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_144_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_144_T_1 & ~_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h91 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_144_T & ~_ghv_wens_144_T_1 & ~_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h91 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h91 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h90 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h91 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_144_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_145_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_145_T_1 & ~_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h92 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_145_T & ~_ghv_wens_145_T_1 & ~_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h92 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h92 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h91 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h92 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_145_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_146_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_146_T_1 & ~_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h93 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_146_T & ~_ghv_wens_146_T_1 & ~_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h93 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h93 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h92 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h93 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_146_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_147_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_147_T_1 & ~_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h94 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_147_T & ~_ghv_wens_147_T_1 & ~_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h94 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h94 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h93 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h94 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_147_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_148_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_148_T_1 & ~_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h95 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_148_T & ~_ghv_wens_148_T_1 & ~_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h95 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h95 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h94 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h95 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_148_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_149_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_149_T_1 & ~_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h96 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_149_T & ~_ghv_wens_149_T_1 & ~_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h96 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h96 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h95 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h96 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_149_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_150_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_150_T_1 & ~_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h97 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_150_T & ~_ghv_wens_150_T_1 & ~_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h97 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h97 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h96 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h97 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_150_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_151_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_151_T_1 & ~_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h98 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_151_T & ~_ghv_wens_151_T_1 & ~_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h98 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h98 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h97 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h98 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_151_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_152_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_152_T_1 & ~_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h99 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_152_T & ~_ghv_wens_152_T_1 & ~_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h99 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h99 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h98 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h99 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_152_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_153_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_153_T_1 & ~_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_153_T & ~_ghv_wens_153_T_1 & ~_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9A & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9A & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h99 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9A & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_153_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_154_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_154_T_1 & ~_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_154_T & ~_ghv_wens_154_T_1 & ~_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9B & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9B & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9A & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9B & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_154_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_155_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_155_T_1 & ~_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_155_T & ~_ghv_wens_155_T_1 & ~_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9C & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9C & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9B & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9C & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_155_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_156_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_156_T_1 & ~_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_156_T & ~_ghv_wens_156_T_1 & ~_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9D & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9D & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9C & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9D & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_156_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_157_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_157_T_1 & ~_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_157_T & ~_ghv_wens_157_T_1 & ~_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9E & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9E & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9D & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9E & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_157_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_158_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_158_T_1 & ~_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_158_T & ~_ghv_wens_158_T_1 & ~_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9F & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9F & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9E & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9F & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_158_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_159_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_159_T_1 & ~_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_159_T & ~_ghv_wens_159_T_1 & ~_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA0 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA0 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9F & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA0 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_159_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_160_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_160_T_1 & ~_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_160_T & ~_ghv_wens_160_T_1 & ~_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA0 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA1 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_160_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_161_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_161_T_1 & ~_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_161_T & ~_ghv_wens_161_T_1 & ~_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA1 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA2 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_161_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_162_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_162_T_1 & ~_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_162_T & ~_ghv_wens_162_T_1 & ~_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA2 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA3 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_162_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_163_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_163_T_1 & ~_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_163_T & ~_ghv_wens_163_T_1 & ~_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA3 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA4 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_163_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_164_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_164_T_1 & ~_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_164_T & ~_ghv_wens_164_T_1 & ~_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA4 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA5 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_164_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_165_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_165_T_1 & ~_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_165_T & ~_ghv_wens_165_T_1 & ~_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA5 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA6 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_165_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_166_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_166_T_1 & ~_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_166_T & ~_ghv_wens_166_T_1 & ~_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA6 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA7 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_166_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_167_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_167_T_1 & ~_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_167_T & ~_ghv_wens_167_T_1 & ~_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA7 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA8 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_167_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_168_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_168_T_1 & ~_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_168_T & ~_ghv_wens_168_T_1 & ~_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA8 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA9 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_168_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_169_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_169_T_1 & ~_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hAA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_169_T & ~_ghv_wens_169_T_1 & ~_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA9 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAA & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_169_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_170_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_170_T_1 & ~_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hAB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_170_T & ~_ghv_wens_170_T_1 & ~_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAA & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAB & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_170_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_171_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_171_T_1 & ~_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hAC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_171_T & ~_ghv_wens_171_T_1 & ~_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAB & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAC & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_171_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_172_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_172_T_1 & ~_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hAD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_172_T & ~_ghv_wens_172_T_1 & ~_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAD & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAD & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAC & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAD & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_172_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_173_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_173_T_1 & ~_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hAE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_173_T & ~_ghv_wens_173_T_1 & ~_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAD & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAE & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_173_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_174_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_174_T_1 & ~_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hAF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_174_T & ~_ghv_wens_174_T_1 & ~_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAF & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAF & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAE & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAF & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_174_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_175_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_175_T_1 & ~_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_175_T & ~_ghv_wens_175_T_1 & ~_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB0 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB0 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAF & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB0 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_175_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_176_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_176_T_1 & ~_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_176_T & ~_ghv_wens_176_T_1 & ~_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB0 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB1 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_176_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_177_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_177_T_1 & ~_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_177_T & ~_ghv_wens_177_T_1 & ~_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB1 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB2 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_177_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_178_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_178_T_1 & ~_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_178_T & ~_ghv_wens_178_T_1 & ~_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB2 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB3 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_178_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_179_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_179_T_1 & ~_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_179_T & ~_ghv_wens_179_T_1 & ~_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB3 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB4 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_179_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_180_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_180_T_1 & ~_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_180_T & ~_ghv_wens_180_T_1 & ~_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB4 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB5 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52 + .out_res (_ghv_write_datas_180_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_181_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_181_T_1 & ~_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_181_T & ~_ghv_wens_181_T_1 & ~_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB5 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB6 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_181_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_182_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_182_T_1 & ~_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_182_T & ~_ghv_wens_182_T_1 & ~_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB6 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB7 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_182_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_183_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_183_T_1 & ~_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_183_T & ~_ghv_wens_183_T_1 & ~_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB7 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB8 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_183_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_184_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_184_T_1 & ~_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_184_T & ~_ghv_wens_184_T_1 & ~_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB8 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB9 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_184_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_185_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_185_T_1 & ~_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hBA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_185_T & ~_ghv_wens_185_T_1 & ~_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB9 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBA & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_185_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_186_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_186_T_1 & ~_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hBB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_186_T & ~_ghv_wens_186_T_1 & ~_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBA & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBB & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_186_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_187_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_187_T_1 & ~_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hBC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_187_T & ~_ghv_wens_187_T_1 & ~_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBB & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBC & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_187_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_188_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_188_T_1 & ~_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hBD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_188_T & ~_ghv_wens_188_T_1 & ~_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBD & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBD & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBC & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBD & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_188_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_189_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_189_T_1 & ~_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hBE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_189_T & ~_ghv_wens_189_T_1 & ~_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBD & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBE & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_189_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_190_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_190_T_1 & ~_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hBF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_190_T & ~_ghv_wens_190_T_1 & ~_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBF & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBF & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBE & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBF & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_190_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_191_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_191_T_1 & ~_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_191_T & ~_ghv_wens_191_T_1 & ~_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC0 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC0 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBF & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC0 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_191_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_192_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_192_T_1 & ~_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_192_T & ~_ghv_wens_192_T_1 & ~_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC0 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC1 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_192_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_193_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_193_T_1 & ~_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_193_T & ~_ghv_wens_193_T_1 & ~_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC1 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC2 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_193_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_194_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_194_T_1 & ~_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_194_T & ~_ghv_wens_194_T_1 & ~_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC2 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC3 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_194_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_195_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_195_T_1 & ~_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_195_T & ~_ghv_wens_195_T_1 & ~_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC3 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC4 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_195_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_196_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_196_T_1 & ~_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_196_T & ~_ghv_wens_196_T_1 & ~_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC4 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC5 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_196_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_197_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_197_T_1 & ~_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_197_T & ~_ghv_wens_197_T_1 & ~_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC5 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC6 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_197_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_198_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_198_T_1 & ~_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_198_T & ~_ghv_wens_198_T_1 & ~_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC6 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC7 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_198_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_199_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_199_T_1 & ~_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_199_T & ~_ghv_wens_199_T_1 & ~_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC7 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC8 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_199_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_200_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_200_T_1 & ~_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_200_T & ~_ghv_wens_200_T_1 & ~_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC8 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC9 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_200_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_201_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_201_T_1 & ~_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hCA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_201_T & ~_ghv_wens_201_T_1 & ~_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC9 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCA & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_201_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_202_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_202_T_1 & ~_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hCB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_202_T & ~_ghv_wens_202_T_1 & ~_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCA & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCB & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_202_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_203_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_203_T_1 & ~_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hCC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_203_T & ~_ghv_wens_203_T_1 & ~_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCB & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCC & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_203_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_204_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_204_T_1 & ~_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hCD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_204_T & ~_ghv_wens_204_T_1 & ~_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCD & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCD & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCC & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCD & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_204_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_205_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_205_T_1 & ~_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hCE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_205_T & ~_ghv_wens_205_T_1 & ~_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCD & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCE & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_205_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_206_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_206_T_1 & ~_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hCF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_206_T & ~_ghv_wens_206_T_1 & ~_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCF & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCF & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCE & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCF & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_206_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_207_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_207_T_1 & ~_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_207_T & ~_ghv_wens_207_T_1 & ~_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD0 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD0 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCF & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD0 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_207_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_208_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_208_T_1 & ~_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_208_T & ~_ghv_wens_208_T_1 & ~_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD0 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD1 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_208_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_209_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_209_T_1 & ~_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_209_T & ~_ghv_wens_209_T_1 & ~_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD1 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD2 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_209_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_210_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_210_T_1 & ~_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_210_T & ~_ghv_wens_210_T_1 & ~_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD2 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD3 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_210_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_211_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_211_T_1 & ~_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_211_T & ~_ghv_wens_211_T_1 & ~_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD3 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD4 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_211_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_212_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_212_T_1 & ~_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_212_T & ~_ghv_wens_212_T_1 & ~_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD4 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD5 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_212_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_213_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_213_T_1 & ~_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_213_T & ~_ghv_wens_213_T_1 & ~_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD5 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD6 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_213_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_214_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_214_T_1 & ~_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_214_T & ~_ghv_wens_214_T_1 & ~_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD6 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD7 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_214_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_215_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_215_T_1 & ~_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_215_T & ~_ghv_wens_215_T_1 & ~_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD7 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD8 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_215_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_216_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_216_T_1 & ~_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_216_T & ~_ghv_wens_216_T_1 & ~_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD8 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD9 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_216_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_217_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_217_T_1 & ~_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hDA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_217_T & ~_ghv_wens_217_T_1 & ~_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD9 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDA & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_217_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_218_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_218_T_1 & ~_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hDB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_218_T & ~_ghv_wens_218_T_1 & ~_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDA & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDB & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_218_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_219_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_219_T_1 & ~_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hDC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_219_T & ~_ghv_wens_219_T_1 & ~_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDB & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDC & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_219_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_220_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_220_T_1 & ~_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hDD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_220_T & ~_ghv_wens_220_T_1 & ~_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDD & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDD & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDC & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDD & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_220_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_221_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_221_T_1 & ~_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hDE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_221_T & ~_ghv_wens_221_T_1 & ~_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDD & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDE & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_221_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_222_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_222_T_1 & ~_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hDF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_222_T & ~_ghv_wens_222_T_1 & ~_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDF & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDF & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDE & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDF & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_222_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_223_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_223_T_1 & ~_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_223_T & ~_ghv_wens_223_T_1 & ~_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE0 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE0 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDF & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE0 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_223_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_224_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_224_T_1 & ~_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_224_T & ~_ghv_wens_224_T_1 & ~_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE0 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE1 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_224_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_225_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_225_T_1 & ~_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_225_T & ~_ghv_wens_225_T_1 & ~_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE1 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE2 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_225_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_226_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_226_T_1 & ~_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_226_T & ~_ghv_wens_226_T_1 & ~_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE2 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE3 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_226_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_227_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_227_T_1 & ~_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_227_T & ~_ghv_wens_227_T_1 & ~_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE3 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE4 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_227_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_228_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_228_T_1 & ~_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_228_T & ~_ghv_wens_228_T_1 & ~_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE4 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE5 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_228_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_229_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_229_T_1 & ~_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_229_T & ~_ghv_wens_229_T_1 & ~_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE5 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE6 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_229_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_230_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_230_T_1 & ~_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_230_T & ~_ghv_wens_230_T_1 & ~_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE6 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE7 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_230_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_231_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_231_T_1 & ~_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_231_T & ~_ghv_wens_231_T_1 & ~_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE7 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE8 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_231_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_232_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_232_T_1 & ~_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_232_T & ~_ghv_wens_232_T_1 & ~_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE8 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE9 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_232_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_233_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_233_T_1 & ~_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hEA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_233_T & ~_ghv_wens_233_T_1 & ~_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE9 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEA & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_233_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_234_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_234_T_1 & ~_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hEB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_234_T & ~_ghv_wens_234_T_1 & ~_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEA & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEB & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_234_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_235_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_235_T_1 & ~_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hEC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_235_T & ~_ghv_wens_235_T_1 & ~_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEB & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEC & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_235_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_236_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_236_T_1 & ~_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hED + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_236_T & ~_ghv_wens_236_T_1 & ~_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hED & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hED & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEC & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hED & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_236_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_237_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_237_T_1 & ~_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hEE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_237_T & ~_ghv_wens_237_T_1 & ~_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hED & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEE & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_237_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_238_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_238_T_1 & ~_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hEF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_238_T & ~_ghv_wens_238_T_1 & ~_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEF & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEF & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEE & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEF & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_238_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_239_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_239_T_1 & ~_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_239_T & ~_ghv_wens_239_T_1 & ~_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF0 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF0 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEF & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF0 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_239_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_240_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_240_T_1 & ~_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_240_T & ~_ghv_wens_240_T_1 & ~_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF1 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF1 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF0 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF1 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_240_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_241_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_241_T_1 & ~_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_241_T & ~_ghv_wens_241_T_1 & ~_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF2 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF2 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF1 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF2 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_241_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_242_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_242_T_1 & ~_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_242_T & ~_ghv_wens_242_T_1 & ~_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF3 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF3 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF2 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF3 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_242_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_243_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_243_T_1 & ~_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_243_T & ~_ghv_wens_243_T_1 & ~_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF4 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF4 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF3 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF4 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_243_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_244_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_244_T_1 & ~_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_244_T & ~_ghv_wens_244_T_1 & ~_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF5 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF5 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF4 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF5 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_244_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_245_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_245_T_1 & ~_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_245_T & ~_ghv_wens_245_T_1 & ~_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF6 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF6 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF5 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF6 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_245_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_246_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_246_T_1 & ~_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_246_T & ~_ghv_wens_246_T_1 & ~_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF7 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF7 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF6 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF7 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_246_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_247_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_247_T_1 & ~_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_247_T & ~_ghv_wens_247_T_1 & ~_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF8 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF8 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF7 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF8 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_247_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_248_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_248_T_1 & ~_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_248_T & ~_ghv_wens_248_T_1 & ~_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF9 & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF9 & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF8 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF9 & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_248_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_249_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_249_T_1 & ~_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hFA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_249_T & ~_ghv_wens_249_T_1 & ~_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFA & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFA & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF9 & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFA & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_249_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_250_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_250_T_1 & ~_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hFB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_250_T & ~_ghv_wens_250_T_1 & ~_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFB & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFB & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFA & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFB & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_250_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_251_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_251_T_1 & ~_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hFC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_251_T & ~_ghv_wens_251_T_1 & ~_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFC & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFC & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFB & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFC & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_251_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_252_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_252_T_1 & ~_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hFD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_252_T & ~_ghv_wens_252_T_1 & ~_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFD & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFD & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFC & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFD & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_252_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_253_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_253_T_1 & ~_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hFE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_253_T & ~_ghv_wens_253_T_1 & ~_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFE & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFE & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFD & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFE & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_253_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_254_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_254_T_1 & ~_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | (&s2_ghist_ptr_dup_0_value) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_254_T & ~_ghv_wens_254_T_1 & ~_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | (&s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | (&s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + (do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFE & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 | (&do_redirect_dup_3_bits_cfiUpdate_histPtr_value) + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15 + .out_res (_ghv_write_datas_254_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_255_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25 + .s2_new_bit_0_sel (_ghv_wens_255_T_1 & ~_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s2_new_bit_0_src + ((&s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit + | ~(|s2_ghist_ptr_dup_0_value) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 + & ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:58, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .s1_new_bit_0_sel + (_ghv_wens_255_T & ~_ghv_wens_255_T_1 & ~_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s1_new_bit_0_src + ((&s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit + | ~(|s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_WIRE_44494_1 + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :494:58, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90} + .s3_new_bit_0_sel (_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120} + .s3_new_bit_0_src + ((&s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit + | ~(|s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_WIRE_13797_1 + & ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:58, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12 + .redirect_new_bit_0_src + ((&do_redirect_dup_3_bits_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 | ~(|do_redirect_dup_3_bits_cfiUpdate_histPtr_value) + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :760:50, :763:52 + .out_res (_ghv_write_datas_255_ppm_out_res) + ); + assign io_bpu_to_ftq_resp_valid = + s1_valid_dup_3 | s2_valid_dup_3 & s2_redirect_dup_2 | s3_valid_dup_3 + & s3_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65, :419:{20,42}, :420:20, :605:28, :684:28 + assign io_bpu_to_ftq_resp_bits_s1_pc_3 = _predictors_io_out_s1_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_0 = + _predictors_io_out_s1_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_1 = + _predictors_io_out_s1_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_0 = + _predictors_io_out_s1_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_1 = + _predictors_io_out_s1_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_0 = + _predictors_io_out_s1_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_1 = + _predictors_io_out_s1_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_0 = + _predictors_io_out_s1_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_1 = + _predictors_io_out_s1_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughAddr = + _predictors_io_out_s1_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_is_br_sharing = + _predictors_io_out_s1_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_hit = + _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s2_pc_3 = _predictors_io_out_s2_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s2_valid_3 = s2_valid_dup_3 & ~s2_flush_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65, :358:26, :717:{32,35} + assign io_bpu_to_ftq_resp_bits_s2_hasRedirect_3 = s2_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :605:28 + assign io_bpu_to_ftq_resp_bits_s2_ftq_idx_flag = s2_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :708:29 + assign io_bpu_to_ftq_resp_bits_s2_ftq_idx_value = s2_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :708:29 + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_0 = + _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_1 = + _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_0 = + _predictors_io_out_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_1 = + _predictors_io_out_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_0 = + _predictors_io_out_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_1 = + _predictors_io_out_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_0 = + _predictors_io_out_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_1 = + _predictors_io_out_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughAddr = + _predictors_io_out_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_is_br_sharing = + _predictors_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_hit = + _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s3_pc_3 = _predictors_io_out_s3_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s3_valid_3 = + s3_valid_dup_3 & ~io_ftq_to_bpu_redirect_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65, :722:{32,35} + assign io_bpu_to_ftq_resp_bits_s3_hasRedirect_3 = s3_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :684:28 + assign io_bpu_to_ftq_resp_bits_s3_ftq_idx_flag = s3_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :709:29 + assign io_bpu_to_ftq_resp_bits_s3_ftq_idx_value = s3_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :709:29 + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_0 = + _predictors_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_1 = + _predictors_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_0 = + _predictors_io_out_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_1 = + _predictors_io_out_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_0 = + _predictors_io_out_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_1 = + _predictors_io_out_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughAddr = + _predictors_io_out_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughErr = + _predictors_io_out_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_is_br_sharing = + _predictors_io_out_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_hit = + _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_17_folded_hist = + s3_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_16_folded_hist = + s3_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_15_folded_hist = + s3_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_14_folded_hist = + s3_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_13_folded_hist = + s3_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_12_folded_hist = + s3_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_11_folded_hist = + s3_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_10_folded_hist = + s3_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_9_folded_hist = + s3_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_8_folded_hist = + s3_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_7_folded_hist = + s3_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_6_folded_hist = + s3_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_5_folded_hist = + s3_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_4_folded_hist = + s3_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_3_folded_hist = + s3_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_2_folded_hist = + s3_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_1_folded_hist = + s3_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_0_folded_hist = + s3_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_0 = + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_1 = + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_2 = + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_3 = + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_0 = + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_1 = + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_2 = + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_3 = + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_0 = + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_1 = + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_2 = + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_3 = + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_0 = + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_1 = + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_2 = + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_3 = + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_0 = + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_1 = + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_2 = + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_3 = + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_0 = + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_1 = + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_2 = + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_3 = + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_lastBrNumOH = + s3_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_flag = + s3_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_value = + s3_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35 +endmodule + diff --git a/src/common/ext_sram.v b/src/common/ext_sram.v new file mode 100644 index 0000000..af55435 --- /dev/null +++ b/src/common/ext_sram.v @@ -0,0 +1,1711 @@ + +module array_ext( + input RW0_clk, + input [6:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [3:0] RW0_wmask, + input [99:0] RW0_wdata, + output [99:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [6:0] reg_RW0_addr; + reg [99:0] ram [127:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 128; initvar = initvar+1) + ram[initvar] = {4 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<4;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*25 +: 25] <= RW0_wdata[i*25 +: 25]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [127:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[99:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_0_ext( + input RW0_clk, + input [6:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [1:0] RW0_wmask, + input [1023:0] RW0_wdata, + output [1023:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [6:0] reg_RW0_addr; + reg [1023:0] ram [127:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 128; initvar = initvar+1) + ram[initvar] = {32 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<2;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*512 +: 512] <= RW0_wdata[i*512 +: 512]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [1023:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[1023:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_1_ext( + input RW0_clk, + input [6:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [3:0] RW0_wmask, + input [127:0] RW0_wdata, + output [127:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [6:0] reg_RW0_addr; + reg [127:0] ram [127:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 128; initvar = initvar+1) + ram[initvar] = {4 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<4;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*32 +: 32] <= RW0_wdata[i*32 +: 32]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [127:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[127:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_2_ext( + input RW0_clk, + input [7:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [3:0] RW0_wmask, + input [99:0] RW0_wdata, + output [99:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [7:0] reg_RW0_addr; + reg [99:0] ram [255:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 256; initvar = initvar+1) + ram[initvar] = {4 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<4;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*25 +: 25] <= RW0_wdata[i*25 +: 25]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [127:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[99:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_3_ext( + input RW0_clk, + input [8:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [3:0] RW0_wmask, + input [319:0] RW0_wdata, + output [319:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [8:0] reg_RW0_addr; + reg [319:0] ram [511:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 512; initvar = initvar+1) + ram[initvar] = {10 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<4;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*80 +: 80] <= RW0_wdata[i*80 +: 80]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [319:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[319:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_4_ext( + input RW0_clk, + input [7:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [15:0] RW0_wmask, + input [15:0] RW0_wdata, + output [15:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [7:0] reg_RW0_addr; + reg [15:0] ram [255:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 256; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<16;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*1 +: 1] <= RW0_wdata[i*1 +: 1]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[15:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_5_ext( + input RW0_clk, + input [8:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [1:0] RW0_wmask, + input [23:0] RW0_wdata, + output [23:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [8:0] reg_RW0_addr; + reg [23:0] ram [511:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 512; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<2;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*12 +: 12] <= RW0_wdata[i*12 +: 12]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[23:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_6_ext( + input W0_clk, + input [8:0] W0_addr, + input W0_en, + input [15:0] W0_data, + input [7:0] W0_mask, + input R0_clk, + input [8:0] R0_addr, + input R0_en, + output [15:0] R0_data +); + + reg reg_R0_ren; + reg [8:0] reg_R0_addr; + reg [15:0] ram [511:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 512; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_R0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge R0_clk) + reg_R0_ren <= R0_en; + always @(posedge R0_clk) + if (R0_en) reg_R0_addr <= R0_addr; + always @(posedge W0_clk) + if (W0_en) begin + if (W0_mask[0]) ram[W0_addr][1:0] <= W0_data[1:0]; + if (W0_mask[1]) ram[W0_addr][3:2] <= W0_data[3:2]; + if (W0_mask[2]) ram[W0_addr][5:4] <= W0_data[5:4]; + if (W0_mask[3]) ram[W0_addr][7:6] <= W0_data[7:6]; + if (W0_mask[4]) ram[W0_addr][9:8] <= W0_data[9:8]; + if (W0_mask[5]) ram[W0_addr][11:10] <= W0_data[11:10]; + if (W0_mask[6]) ram[W0_addr][13:12] <= W0_data[13:12]; + if (W0_mask[7]) ram[W0_addr][15:14] <= W0_data[15:14]; + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] R0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + R0_random = {$random}; + reg_R0_ren = R0_random[0]; + end + `endif + always @(posedge R0_clk) R0_random <= {$random}; + assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[15:0]; + `else + assign R0_data = ram[reg_R0_addr]; + `endif + +endmodule +module array_7_ext( + input W0_clk, + input [7:0] W0_addr, + input W0_en, + input [23:0] W0_data, + input [3:0] W0_mask, + input R0_clk, + input [7:0] R0_addr, + input R0_en, + output [23:0] R0_data +); + + reg reg_R0_ren; + reg [7:0] reg_R0_addr; + reg [23:0] ram [255:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 256; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_R0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge R0_clk) + reg_R0_ren <= R0_en; + always @(posedge R0_clk) + if (R0_en) reg_R0_addr <= R0_addr; + always @(posedge W0_clk) + if (W0_en) begin + if (W0_mask[0]) ram[W0_addr][5:0] <= W0_data[5:0]; + if (W0_mask[1]) ram[W0_addr][11:6] <= W0_data[11:6]; + if (W0_mask[2]) ram[W0_addr][17:12] <= W0_data[17:12]; + if (W0_mask[3]) ram[W0_addr][23:18] <= W0_data[23:18]; + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] R0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + R0_random = {$random}; + reg_R0_ren = R0_random[0]; + end + `endif + always @(posedge R0_clk) R0_random <= {$random}; + assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[23:0]; + `else + assign R0_data = ram[reg_R0_addr]; + `endif + +endmodule +module array_0_0_ext( + input RW0_clk, + input [6:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [49:0] RW0_wdata, + output [49:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [6:0] reg_RW0_addr; + reg [49:0] ram [127:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 128; initvar = initvar+1) + ram[initvar] = {2 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<1;i=i+1) begin + ram[RW0_addr][i*50 +: 50] <= RW0_wdata[i*50 +: 50]; + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [63:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[49:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_8_ext( + input RW0_clk, + input [6:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [1:0] RW0_wmask, + input [99:0] RW0_wdata, + output [99:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [6:0] reg_RW0_addr; + reg [99:0] ram [127:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 128; initvar = initvar+1) + ram[initvar] = {4 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<2;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*50 +: 50] <= RW0_wdata[i*50 +: 50]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [127:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[99:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_0_1_ext( + input W0_clk, + input [5:0] W0_addr, + input W0_en, + input [246:0] W0_data, + input R0_clk, + input [5:0] R0_addr, + input R0_en, + output [246:0] R0_data +); + + reg reg_R0_ren; + reg [5:0] reg_R0_addr; + reg [246:0] ram [63:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 64; initvar = initvar+1) + ram[initvar] = {8 {$random}}; + reg_R0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge R0_clk) + reg_R0_ren <= R0_en; + always @(posedge R0_clk) + if (R0_en) reg_R0_addr <= R0_addr; + always @(posedge W0_clk) + if (W0_en) begin + ram[W0_addr][246:0] <= W0_data[246:0]; + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [255:0] R0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + R0_random = {$random, $random, $random, $random, $random, $random, $random, $random}; + reg_R0_ren = R0_random[0]; + end + `endif + always @(posedge R0_clk) R0_random <= {$random, $random, $random, $random, $random, $random, $random, $random}; + assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[246:0]; + `else + assign R0_data = ram[reg_R0_addr]; + `endif + +endmodule +module array_0_2_ext( + input W0_clk, + input [5:0] W0_addr, + input W0_en, + input [218:0] W0_data, + input R0_clk, + input [5:0] R0_addr, + input R0_en, + output [218:0] R0_data +); + + reg reg_R0_ren; + reg [5:0] reg_R0_addr; + reg [218:0] ram [63:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 64; initvar = initvar+1) + ram[initvar] = {7 {$random}}; + reg_R0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge R0_clk) + reg_R0_ren <= R0_en; + always @(posedge R0_clk) + if (R0_en) reg_R0_addr <= R0_addr; + always @(posedge W0_clk) + if (W0_en) begin + ram[W0_addr][218:0] <= W0_data[218:0]; + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [223:0] R0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + R0_random = {$random, $random, $random, $random, $random, $random, $random}; + reg_R0_ren = R0_random[0]; + end + `endif + always @(posedge R0_clk) R0_random <= {$random, $random, $random, $random, $random, $random, $random}; + assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[218:0]; + `else + assign R0_data = ram[reg_R0_addr]; + `endif + +endmodule +module array_0_3_ext( + input RW0_clk, + input [7:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [63:0] RW0_wdata, + output [63:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [7:0] reg_RW0_addr; + reg [63:0] ram [255:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 256; initvar = initvar+1) + ram[initvar] = {2 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<1;i=i+1) begin + ram[RW0_addr][i*64 +: 64] <= RW0_wdata[i*64 +: 64]; + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [63:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[63:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_9_ext( + input RW0_clk, + input [7:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [3:0] RW0_wmask, + input [95:0] RW0_wdata, + output [95:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [7:0] reg_RW0_addr; + reg [95:0] ram [255:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 256; initvar = initvar+1) + ram[initvar] = {3 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<4;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*24 +: 24] <= RW0_wdata[i*24 +: 24]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [95:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[95:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_10_ext( + input RW0_clk, + input [7:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [3:0] RW0_wmask, + input [23:0] RW0_wdata, + output [23:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [7:0] reg_RW0_addr; + reg [23:0] ram [255:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 256; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<4;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*6 +: 6] <= RW0_wdata[i*6 +: 6]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[23:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_11_ext( + input RW0_clk, + input [2:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [3:0] RW0_wmask, + input [1039:0] RW0_wdata, + output [1039:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [2:0] reg_RW0_addr; + reg [1039:0] ram [7:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 8; initvar = initvar+1) + ram[initvar] = {33 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<4;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*260 +: 260] <= RW0_wdata[i*260 +: 260]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [1055:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[1039:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_12_ext( + input RW0_clk, + input [4:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [7:0] RW0_wmask, + input [2647:0] RW0_wdata, + output [2647:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [4:0] reg_RW0_addr; + reg [2647:0] ram [31:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 32; initvar = initvar+1) + ram[initvar] = {83 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<8;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*331 +: 331] <= RW0_wdata[i*331 +: 331]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [2655:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[2647:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_13_ext( + input RW0_clk, + input [4:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [1:0] RW0_wmask, + input [147:0] RW0_wdata, + output [147:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [4:0] reg_RW0_addr; + reg [147:0] ram [31:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 32; initvar = initvar+1) + ram[initvar] = {5 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<2;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*74 +: 74] <= RW0_wdata[i*74 +: 74]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [159:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[147:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_0_4_ext( + input RW0_clk, + input [7:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [12:0] RW0_wdata, + output [12:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [7:0] reg_RW0_addr; + reg [12:0] ram [255:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 256; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<1;i=i+1) begin + ram[RW0_addr][i*13 +: 13] <= RW0_wdata[i*13 +: 13]; + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[12:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_14_ext( + input RW0_clk, + input [9:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [15:0] RW0_wmask, + input [383:0] RW0_wdata, + output [383:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [9:0] reg_RW0_addr; + reg [383:0] ram [1023:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 1024; initvar = initvar+1) + ram[initvar] = {12 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<16;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*24 +: 24] <= RW0_wdata[i*24 +: 24]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [383:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[383:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_15_ext( + input RW0_clk, + input [8:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [7:0] RW0_wmask, + input [151:0] RW0_wdata, + output [151:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [8:0] reg_RW0_addr; + reg [151:0] ram [511:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 512; initvar = initvar+1) + ram[initvar] = {5 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<8;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*19 +: 19] <= RW0_wdata[i*19 +: 19]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [159:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[151:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_16_ext( + input RW0_clk, + input [8:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [7:0] RW0_wmask, + input [87:0] RW0_wdata, + output [87:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [8:0] reg_RW0_addr; + reg [87:0] ram [511:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 512; initvar = initvar+1) + ram[initvar] = {3 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<8;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*11 +: 11] <= RW0_wdata[i*11 +: 11]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [95:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[87:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_0_5_ext( + input RW0_clk, + input [8:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [6:0] RW0_wdata, + output [6:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [8:0] reg_RW0_addr; + reg [6:0] ram [511:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 512; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<1;i=i+1) begin + ram[RW0_addr][i*7 +: 7] <= RW0_wdata[i*7 +: 7]; + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[6:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_0_6_ext( + input RW0_clk, + input [11:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [511:0] RW0_wdata, + output [511:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [11:0] reg_RW0_addr; + reg [511:0] ram [4095:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 4096; initvar = initvar+1) + ram[initvar] = {16 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<1;i=i+1) begin + ram[RW0_addr][i*512 +: 512] <= RW0_wdata[i*512 +: 512]; + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [511:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[511:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_17_ext( + input RW0_clk, + input [9:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [15:0] RW0_wmask, + input [7743:0] RW0_wdata, + output [7743:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [9:0] reg_RW0_addr; + reg [7743:0] ram [1023:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 1024; initvar = initvar+1) + ram[initvar] = {242 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<16;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*484 +: 484] <= RW0_wdata[i*484 +: 484]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [7743:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[7743:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_0_7_ext( + input RW0_clk, + input [13:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [63:0] RW0_wdata, + output [63:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [13:0] reg_RW0_addr; + reg [63:0] ram [16383:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 16384; initvar = initvar+1) + ram[initvar] = {2 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<1;i=i+1) begin + ram[RW0_addr][i*64 +: 64] <= RW0_wdata[i*64 +: 64]; + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [63:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[63:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_0_8_ext( + input RW0_clk, + input [13:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [31:0] RW0_wdata, + output [31:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [13:0] reg_RW0_addr; + reg [31:0] ram [16383:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 16384; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<1;i=i+1) begin + ram[RW0_addr][i*32 +: 32] <= RW0_wdata[i*32 +: 32]; + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[31:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_18_ext( + input RW0_clk, + input [9:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [9:0] RW0_wmask, + input [19:0] RW0_wdata, + output [19:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [9:0] reg_RW0_addr; + reg [19:0] ram [1023:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 1024; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<10;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*2 +: 2] <= RW0_wdata[i*2 +: 2]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[19:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_19_ext( + input RW0_clk, + input [9:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [9:0] RW0_wmask, + input [179:0] RW0_wdata, + output [179:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [9:0] reg_RW0_addr; + reg [179:0] ram [1023:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 1024; initvar = initvar+1) + ram[initvar] = {6 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<10;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*18 +: 18] <= RW0_wdata[i*18 +: 18]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [191:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[179:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_20_ext( + input RW0_clk, + input [9:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [9:0] RW0_wmask, + input [59:0] RW0_wdata, + output [59:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [9:0] reg_RW0_addr; + reg [59:0] ram [1023:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 1024; initvar = initvar+1) + ram[initvar] = {2 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<10;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*6 +: 6] <= RW0_wdata[i*6 +: 6]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [63:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[59:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_21_ext( + input RW0_clk, + input [11:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [15:0] RW0_wmask, + input [95:0] RW0_wdata, + output [95:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [11:0] reg_RW0_addr; + reg [95:0] ram [4095:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 4096; initvar = initvar+1) + ram[initvar] = {3 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<16;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*6 +: 6] <= RW0_wdata[i*6 +: 6]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [95:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[95:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_22_ext( + input RW0_clk, + input [11:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [15:0] RW0_wmask, + input [255:0] RW0_wdata, + output [255:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [11:0] reg_RW0_addr; + reg [255:0] ram [4095:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 4096; initvar = initvar+1) + ram[initvar] = {8 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<16;i=i+1) begin + if(RW0_wmask[i]) begin + ram[RW0_addr][i*16 +: 16] <= RW0_wdata[i*16 +: 16]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [255:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[255:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule +module array_0_9_ext( + input RW0_clk, + input [11:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [14:0] RW0_wdata, + output [14:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [11:0] reg_RW0_addr; + reg [14:0] ram [4095:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 4096; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for(i=0;i<1;i=i+1) begin + ram[RW0_addr][i*15 +: 15] <= RW0_wdata[i*15 +: 15]; + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[14:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule \ No newline at end of file diff --git a/src/uFTB.txt b/src/uFTB.txt new file mode 100644 index 0000000..c249f0e --- /dev/null +++ b/src/uFTB.txt @@ -0,0 +1,3 @@ +./src/uFTB/FauFTBWay.sv +./src/common/ext_sram.v +./src/common/DelayN_2.sv \ No newline at end of file diff --git a/src/uFTB/FauFTB.sv b/src/uFTB/FauFTB.sv new file mode 100644 index 0000000..567d9c7 --- /dev/null +++ b/src/uFTB/FauFTB.sv @@ -0,0 +1,4738 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FauFTB( // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + input clock, + input reset, + input [35:0] io_reset_vector, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s1_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s1_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s1_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_ctrl_ubtb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [11:0] io_update_bits_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [19:0] io_update_bits_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_br_taken_mask_1 // src/main/scala/xiangshan/frontend/BPU.scala:171:14 +); + + reg [4:0] resp_meta_pred_way_r_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:123:34 + reg resp_meta_hit_r_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:122:29 + wire [3:0] _ways_31_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_31_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_31_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_31_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_31_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_31_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_31_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_31_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_31_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_31_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_31_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_31_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_31_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_31_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_31_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_30_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_30_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_30_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_30_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_30_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_30_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_30_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_30_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_30_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_30_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_30_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_30_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_30_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_30_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_30_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_29_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_29_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_29_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_29_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_29_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_29_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_29_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_29_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_29_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_29_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_29_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_29_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_29_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_29_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_29_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_28_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_28_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_28_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_28_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_28_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_28_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_28_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_28_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_28_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_28_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_28_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_28_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_28_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_28_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_28_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_27_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_27_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_27_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_27_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_27_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_27_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_27_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_27_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_27_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_27_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_27_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_27_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_27_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_27_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_27_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_26_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_26_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_26_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_26_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_26_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_26_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_26_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_26_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_26_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_26_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_26_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_26_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_26_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_26_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_26_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_25_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_25_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_25_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_25_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_25_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_25_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_25_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_25_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_25_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_25_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_25_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_25_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_25_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_25_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_25_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_24_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_24_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_24_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_24_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_24_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_24_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_24_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_24_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_24_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_24_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_24_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_24_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_24_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_24_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_24_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_23_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_23_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_23_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_23_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_23_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_23_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_23_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_23_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_23_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_23_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_23_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_23_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_23_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_23_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_23_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_22_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_22_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_22_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_22_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_22_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_22_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_22_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_22_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_22_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_22_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_22_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_22_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_22_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_22_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_22_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_21_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_21_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_21_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_21_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_21_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_21_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_21_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_21_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_21_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_21_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_21_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_21_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_21_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_21_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_21_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_20_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_20_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_20_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_20_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_20_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_20_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_20_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_20_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_20_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_20_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_20_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_20_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_20_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_20_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_20_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_19_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_19_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_19_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_19_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_19_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_19_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_19_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_19_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_19_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_19_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_19_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_19_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_19_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_19_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_19_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_18_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_18_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_18_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_18_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_18_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_18_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_18_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_18_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_18_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_18_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_18_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_18_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_18_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_18_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_18_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_17_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_17_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_17_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_17_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_17_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_17_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_17_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_17_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_17_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_17_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_17_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_17_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_17_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_17_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_17_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_16_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_16_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_16_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_16_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_16_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_16_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_16_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_16_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_16_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_16_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_16_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_16_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_16_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_16_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_16_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_15_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_15_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_15_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_15_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_15_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_15_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_15_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_15_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_15_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_15_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_15_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_15_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_15_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_15_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_15_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_14_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_14_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_14_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_14_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_14_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_14_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_14_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_14_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_14_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_14_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_14_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_14_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_14_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_14_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_14_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_13_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_13_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_13_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_13_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_13_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_13_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_13_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_13_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_13_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_13_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_13_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_13_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_13_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_13_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_13_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_12_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_12_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_12_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_12_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_12_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_12_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_12_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_12_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_12_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_12_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_12_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_12_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_12_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_12_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_12_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_11_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_11_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_11_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_11_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_11_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_11_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_11_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_11_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_11_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_11_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_11_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_11_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_11_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_11_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_11_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_10_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_10_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_10_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_10_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_10_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_10_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_10_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_10_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_10_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_10_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_10_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_10_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_10_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_10_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_10_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_9_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_9_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_9_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_9_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_9_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_9_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_9_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_9_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_9_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_9_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_9_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_9_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_9_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_9_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_9_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_8_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_8_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_8_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_8_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_8_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_8_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_8_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_8_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_8_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_8_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_8_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_8_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_8_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_8_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_8_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_7_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_7_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_7_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_7_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_7_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_7_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_7_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_7_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_7_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_7_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_7_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_7_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_7_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_7_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_7_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_6_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_6_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_6_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_6_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_6_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_6_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_6_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_6_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_6_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_6_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_6_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_6_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_6_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_6_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_6_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_5_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_5_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_5_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_5_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_5_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_5_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_5_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_5_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_5_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_5_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_5_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_5_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_5_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_5_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_5_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_4_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_4_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_4_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_4_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_4_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_4_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_4_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_4_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_4_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_4_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_4_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_4_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_4_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_4_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_4_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_3_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_3_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_3_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_3_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_3_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_3_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_3_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_3_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_3_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_3_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_3_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_3_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_3_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_3_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_3_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_2_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_2_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_2_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_2_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_2_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_2_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_2_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_2_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_2_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_2_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_2_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_2_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_2_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_2_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_2_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_1_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_1_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_1_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_1_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_1_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_1_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_1_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_1_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_1_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_1_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_1_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_1_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_1_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_1_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_1_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_0_io_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [11:0] _ways_0_io_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_0_io_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_0_io_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_0_io_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [19:0] _ways_0_io_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [1:0] _ways_0_io_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_0_io_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_0_io_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _ways_0_io_resp_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_0_io_resp_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_0_io_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_0_io_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_0_io_resp_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _ways_0_io_update_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [35:0] _reset_vector_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 + reg [38:0] s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + reg [38:0] s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + reg [38:0] s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + reg [38:0] s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + reg REG; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 + reg REG_1; // src/main/scala/xiangshan/frontend/BPU.scala:190:16 + reg [1:0] ctrs_0_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_0_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_1_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_1_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_2_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_2_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_3_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_3_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_4_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_4_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_5_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_5_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_6_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_6_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_7_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_7_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_8_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_8_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_9_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_9_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_10_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_10_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_11_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_11_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_12_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_12_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_13_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_13_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_14_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_14_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_15_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_15_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_16_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_16_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_17_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_17_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_18_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_18_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_19_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_19_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_20_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_20_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_21_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_21_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_22_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_22_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_23_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_23_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_24_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_24_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_25_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_25_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_26_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_26_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_27_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_27_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_28_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_28_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_29_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_29_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_30_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_30_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_31_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [1:0] ctrs_31_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + reg [30:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + wire [31:0] s1_hit_oh = + {_ways_31_io_resp_hit, + _ways_30_io_resp_hit, + _ways_29_io_resp_hit, + _ways_28_io_resp_hit, + _ways_27_io_resp_hit, + _ways_26_io_resp_hit, + _ways_25_io_resp_hit, + _ways_24_io_resp_hit, + _ways_23_io_resp_hit, + _ways_22_io_resp_hit, + _ways_21_io_resp_hit, + _ways_20_io_resp_hit, + _ways_19_io_resp_hit, + _ways_18_io_resp_hit, + _ways_17_io_resp_hit, + _ways_16_io_resp_hit, + _ways_15_io_resp_hit, + _ways_14_io_resp_hit, + _ways_13_io_resp_hit, + _ways_12_io_resp_hit, + _ways_11_io_resp_hit, + _ways_10_io_resp_hit, + _ways_9_io_resp_hit, + _ways_8_io_resp_hit, + _ways_7_io_resp_hit, + _ways_6_io_resp_hit, + _ways_5_io_resp_hit, + _ways_4_io_resp_hit, + _ways_3_io_resp_hit, + _ways_2_io_resp_hit, + _ways_1_io_resp_hit, + _ways_0_io_resp_hit}; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :101:52 + wire _target_T_18 = _ways_0_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_19 = _ways_0_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_20 = _ways_0_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_0_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_0_io_resp_carry, _ways_0_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire [38:0] _s1_possible_full_preds_31_fallThroughAddr_T = 39'(s1_pc_dup_0 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FrontendBundle.scala:550:47 + wire _target_T_45 = _ways_1_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_46 = _ways_1_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_47 = _ways_1_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_1_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_1_io_resp_carry, _ways_1_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_72 = _ways_2_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_73 = _ways_2_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_74 = _ways_2_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_2_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_2_io_resp_carry, _ways_2_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_99 = _ways_3_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_100 = _ways_3_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_101 = _ways_3_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_3_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_3_io_resp_carry, _ways_3_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_126 = _ways_4_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_127 = _ways_4_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_128 = _ways_4_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_4_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_4_io_resp_carry, _ways_4_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_153 = _ways_5_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_154 = _ways_5_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_155 = _ways_5_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_5_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_5_io_resp_carry, _ways_5_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_180 = _ways_6_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_181 = _ways_6_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_182 = _ways_6_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_6_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_6_io_resp_carry, _ways_6_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_207 = _ways_7_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_208 = _ways_7_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_209 = _ways_7_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_7_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_7_io_resp_carry, _ways_7_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_234 = _ways_8_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_235 = _ways_8_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_236 = _ways_8_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_8_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_8_io_resp_carry, _ways_8_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_261 = _ways_9_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_262 = _ways_9_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_263 = _ways_9_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_9_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_9_io_resp_carry, _ways_9_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_288 = _ways_10_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_289 = _ways_10_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_290 = _ways_10_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_10_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_10_io_resp_carry, _ways_10_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_315 = _ways_11_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_316 = _ways_11_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_317 = _ways_11_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_11_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_11_io_resp_carry, _ways_11_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_342 = _ways_12_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_343 = _ways_12_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_344 = _ways_12_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_12_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_12_io_resp_carry, _ways_12_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_369 = _ways_13_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_370 = _ways_13_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_371 = _ways_13_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_13_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_13_io_resp_carry, _ways_13_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_396 = _ways_14_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_397 = _ways_14_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_398 = _ways_14_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_14_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_14_io_resp_carry, _ways_14_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_423 = _ways_15_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_424 = _ways_15_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_425 = _ways_15_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_15_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_15_io_resp_carry, _ways_15_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_450 = _ways_16_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_451 = _ways_16_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_452 = _ways_16_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_16_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_16_io_resp_carry, _ways_16_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_477 = _ways_17_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_478 = _ways_17_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_479 = _ways_17_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_17_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_17_io_resp_carry, _ways_17_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_504 = _ways_18_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_505 = _ways_18_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_506 = _ways_18_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_18_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_18_io_resp_carry, _ways_18_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_531 = _ways_19_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_532 = _ways_19_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_533 = _ways_19_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_19_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_19_io_resp_carry, _ways_19_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_558 = _ways_20_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_559 = _ways_20_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_560 = _ways_20_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_20_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_20_io_resp_carry, _ways_20_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_585 = _ways_21_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_586 = _ways_21_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_587 = _ways_21_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_21_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_21_io_resp_carry, _ways_21_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_612 = _ways_22_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_613 = _ways_22_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_614 = _ways_22_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_22_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_22_io_resp_carry, _ways_22_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_639 = _ways_23_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_640 = _ways_23_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_641 = _ways_23_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_23_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_23_io_resp_carry, _ways_23_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_666 = _ways_24_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_667 = _ways_24_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_668 = _ways_24_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_24_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_24_io_resp_carry, _ways_24_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_693 = _ways_25_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_694 = _ways_25_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_695 = _ways_25_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_25_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_25_io_resp_carry, _ways_25_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_720 = _ways_26_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_721 = _ways_26_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_722 = _ways_26_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_26_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_26_io_resp_carry, _ways_26_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_747 = _ways_27_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_748 = _ways_27_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_749 = _ways_27_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_27_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_27_io_resp_carry, _ways_27_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_774 = _ways_28_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_775 = _ways_28_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_776 = _ways_28_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_28_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_28_io_resp_carry, _ways_28_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_801 = _ways_29_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_802 = _ways_29_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_803 = _ways_29_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_29_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_29_io_resp_carry, _ways_29_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_828 = _ways_30_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_829 = _ways_30_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_830 = _ways_30_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_30_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_30_io_resp_carry, _ways_30_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _target_T_855 = _ways_31_io_resp_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _target_T_856 = _ways_31_io_resp_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire _target_T_857 = _ways_31_io_resp_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire s1_possible_full_preds_31_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_31_io_resp_carry, _ways_31_io_resp_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34 + wire _s1_hit_full_pred_WIRE_1 = + _ways_0_io_resp_hit & _ways_0_io_resp_tailSlot_valid + & _ways_0_io_resp_tailSlot_sharing | _ways_1_io_resp_hit + & _ways_1_io_resp_tailSlot_valid & _ways_1_io_resp_tailSlot_sharing + | _ways_2_io_resp_hit & _ways_2_io_resp_tailSlot_valid + & _ways_2_io_resp_tailSlot_sharing | _ways_3_io_resp_hit + & _ways_3_io_resp_tailSlot_valid & _ways_3_io_resp_tailSlot_sharing + | _ways_4_io_resp_hit & _ways_4_io_resp_tailSlot_valid + & _ways_4_io_resp_tailSlot_sharing | _ways_5_io_resp_hit + & _ways_5_io_resp_tailSlot_valid & _ways_5_io_resp_tailSlot_sharing + | _ways_6_io_resp_hit & _ways_6_io_resp_tailSlot_valid + & _ways_6_io_resp_tailSlot_sharing | _ways_7_io_resp_hit + & _ways_7_io_resp_tailSlot_valid & _ways_7_io_resp_tailSlot_sharing + | _ways_8_io_resp_hit & _ways_8_io_resp_tailSlot_valid + & _ways_8_io_resp_tailSlot_sharing | _ways_9_io_resp_hit + & _ways_9_io_resp_tailSlot_valid & _ways_9_io_resp_tailSlot_sharing + | _ways_10_io_resp_hit & _ways_10_io_resp_tailSlot_valid + & _ways_10_io_resp_tailSlot_sharing | _ways_11_io_resp_hit + & _ways_11_io_resp_tailSlot_valid & _ways_11_io_resp_tailSlot_sharing + | _ways_12_io_resp_hit & _ways_12_io_resp_tailSlot_valid + & _ways_12_io_resp_tailSlot_sharing | _ways_13_io_resp_hit + & _ways_13_io_resp_tailSlot_valid & _ways_13_io_resp_tailSlot_sharing + | _ways_14_io_resp_hit & _ways_14_io_resp_tailSlot_valid + & _ways_14_io_resp_tailSlot_sharing | _ways_15_io_resp_hit + & _ways_15_io_resp_tailSlot_valid & _ways_15_io_resp_tailSlot_sharing + | _ways_16_io_resp_hit & _ways_16_io_resp_tailSlot_valid + & _ways_16_io_resp_tailSlot_sharing | _ways_17_io_resp_hit + & _ways_17_io_resp_tailSlot_valid & _ways_17_io_resp_tailSlot_sharing + | _ways_18_io_resp_hit & _ways_18_io_resp_tailSlot_valid + & _ways_18_io_resp_tailSlot_sharing | _ways_19_io_resp_hit + & _ways_19_io_resp_tailSlot_valid & _ways_19_io_resp_tailSlot_sharing + | _ways_20_io_resp_hit & _ways_20_io_resp_tailSlot_valid + & _ways_20_io_resp_tailSlot_sharing | _ways_21_io_resp_hit + & _ways_21_io_resp_tailSlot_valid & _ways_21_io_resp_tailSlot_sharing + | _ways_22_io_resp_hit & _ways_22_io_resp_tailSlot_valid + & _ways_22_io_resp_tailSlot_sharing | _ways_23_io_resp_hit + & _ways_23_io_resp_tailSlot_valid & _ways_23_io_resp_tailSlot_sharing + | _ways_24_io_resp_hit & _ways_24_io_resp_tailSlot_valid + & _ways_24_io_resp_tailSlot_sharing | _ways_25_io_resp_hit + & _ways_25_io_resp_tailSlot_valid & _ways_25_io_resp_tailSlot_sharing + | _ways_26_io_resp_hit & _ways_26_io_resp_tailSlot_valid + & _ways_26_io_resp_tailSlot_sharing | _ways_27_io_resp_hit + & _ways_27_io_resp_tailSlot_valid & _ways_27_io_resp_tailSlot_sharing + | _ways_28_io_resp_hit & _ways_28_io_resp_tailSlot_valid + & _ways_28_io_resp_tailSlot_sharing | _ways_29_io_resp_hit + & _ways_29_io_resp_tailSlot_valid & _ways_29_io_resp_tailSlot_sharing + | _ways_30_io_resp_hit & _ways_30_io_resp_tailSlot_valid + & _ways_30_io_resp_tailSlot_sharing | _ways_31_io_resp_hit + & _ways_31_io_resp_tailSlot_valid & _ways_31_io_resp_tailSlot_sharing; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [38:0] _s1_hit_full_pred_WIRE_8 = + (_ways_0_io_resp_hit + ? (s1_possible_full_preds_0_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_0_io_resp_carry ? 34'(s1_pc_dup_0[38:5] + 34'h1) : s1_pc_dup_0[38:5], + _ways_0_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_1_io_resp_hit + ? (s1_possible_full_preds_1_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_1_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_1_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_2_io_resp_hit + ? (s1_possible_full_preds_2_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_2_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_2_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_3_io_resp_hit + ? (s1_possible_full_preds_3_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_3_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_3_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_4_io_resp_hit + ? (s1_possible_full_preds_4_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_4_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_4_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_5_io_resp_hit + ? (s1_possible_full_preds_5_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_5_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_5_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_6_io_resp_hit + ? (s1_possible_full_preds_6_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_6_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_6_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_7_io_resp_hit + ? (s1_possible_full_preds_7_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_7_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_7_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_8_io_resp_hit + ? (s1_possible_full_preds_8_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_8_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_8_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_9_io_resp_hit + ? (s1_possible_full_preds_9_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_9_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_9_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_10_io_resp_hit + ? (s1_possible_full_preds_10_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_10_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_10_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_11_io_resp_hit + ? (s1_possible_full_preds_11_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_11_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_11_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_12_io_resp_hit + ? (s1_possible_full_preds_12_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_12_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_12_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_13_io_resp_hit + ? (s1_possible_full_preds_13_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_13_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_13_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_14_io_resp_hit + ? (s1_possible_full_preds_14_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_14_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_14_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_15_io_resp_hit + ? (s1_possible_full_preds_15_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_15_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_15_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_16_io_resp_hit + ? (s1_possible_full_preds_16_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_16_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_16_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_17_io_resp_hit + ? (s1_possible_full_preds_17_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_17_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_17_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_18_io_resp_hit + ? (s1_possible_full_preds_18_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_18_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_18_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_19_io_resp_hit + ? (s1_possible_full_preds_19_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_19_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_19_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_20_io_resp_hit + ? (s1_possible_full_preds_20_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_20_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_20_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_21_io_resp_hit + ? (s1_possible_full_preds_21_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_21_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_21_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_22_io_resp_hit + ? (s1_possible_full_preds_22_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_22_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_22_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_23_io_resp_hit + ? (s1_possible_full_preds_23_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_23_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_23_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_24_io_resp_hit + ? (s1_possible_full_preds_24_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_24_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_24_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_25_io_resp_hit + ? (s1_possible_full_preds_25_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_25_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_25_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_26_io_resp_hit + ? (s1_possible_full_preds_26_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_26_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_26_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_27_io_resp_hit + ? (s1_possible_full_preds_27_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_27_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_27_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_28_io_resp_hit + ? (s1_possible_full_preds_28_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_28_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_28_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_29_io_resp_hit + ? (s1_possible_full_preds_29_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_29_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_29_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_30_io_resp_hit + ? (s1_possible_full_preds_30_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_30_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_30_io_resp_pftAddr, + 1'h0}) + : 39'h0) + | (_ways_31_io_resp_hit + ? (s1_possible_full_preds_31_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_31_io_resp_carry + ? 34'(s1_pc_dup_0[38:5] + 34'h1) + : s1_pc_dup_0[38:5], + _ways_31_io_resp_pftAddr, + 1'h0}) + : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47} + wire [3:0] _s1_hit_full_pred_WIRE_10 = + (_ways_0_io_resp_hit ? _ways_0_io_resp_brSlots_0_offset : 4'h0) + | (_ways_1_io_resp_hit ? _ways_1_io_resp_brSlots_0_offset : 4'h0) + | (_ways_2_io_resp_hit ? _ways_2_io_resp_brSlots_0_offset : 4'h0) + | (_ways_3_io_resp_hit ? _ways_3_io_resp_brSlots_0_offset : 4'h0) + | (_ways_4_io_resp_hit ? _ways_4_io_resp_brSlots_0_offset : 4'h0) + | (_ways_5_io_resp_hit ? _ways_5_io_resp_brSlots_0_offset : 4'h0) + | (_ways_6_io_resp_hit ? _ways_6_io_resp_brSlots_0_offset : 4'h0) + | (_ways_7_io_resp_hit ? _ways_7_io_resp_brSlots_0_offset : 4'h0) + | (_ways_8_io_resp_hit ? _ways_8_io_resp_brSlots_0_offset : 4'h0) + | (_ways_9_io_resp_hit ? _ways_9_io_resp_brSlots_0_offset : 4'h0) + | (_ways_10_io_resp_hit ? _ways_10_io_resp_brSlots_0_offset : 4'h0) + | (_ways_11_io_resp_hit ? _ways_11_io_resp_brSlots_0_offset : 4'h0) + | (_ways_12_io_resp_hit ? _ways_12_io_resp_brSlots_0_offset : 4'h0) + | (_ways_13_io_resp_hit ? _ways_13_io_resp_brSlots_0_offset : 4'h0) + | (_ways_14_io_resp_hit ? _ways_14_io_resp_brSlots_0_offset : 4'h0) + | (_ways_15_io_resp_hit ? _ways_15_io_resp_brSlots_0_offset : 4'h0) + | (_ways_16_io_resp_hit ? _ways_16_io_resp_brSlots_0_offset : 4'h0) + | (_ways_17_io_resp_hit ? _ways_17_io_resp_brSlots_0_offset : 4'h0) + | (_ways_18_io_resp_hit ? _ways_18_io_resp_brSlots_0_offset : 4'h0) + | (_ways_19_io_resp_hit ? _ways_19_io_resp_brSlots_0_offset : 4'h0) + | (_ways_20_io_resp_hit ? _ways_20_io_resp_brSlots_0_offset : 4'h0) + | (_ways_21_io_resp_hit ? _ways_21_io_resp_brSlots_0_offset : 4'h0) + | (_ways_22_io_resp_hit ? _ways_22_io_resp_brSlots_0_offset : 4'h0) + | (_ways_23_io_resp_hit ? _ways_23_io_resp_brSlots_0_offset : 4'h0) + | (_ways_24_io_resp_hit ? _ways_24_io_resp_brSlots_0_offset : 4'h0) + | (_ways_25_io_resp_hit ? _ways_25_io_resp_brSlots_0_offset : 4'h0) + | (_ways_26_io_resp_hit ? _ways_26_io_resp_brSlots_0_offset : 4'h0) + | (_ways_27_io_resp_hit ? _ways_27_io_resp_brSlots_0_offset : 4'h0) + | (_ways_28_io_resp_hit ? _ways_28_io_resp_brSlots_0_offset : 4'h0) + | (_ways_29_io_resp_hit ? _ways_29_io_resp_brSlots_0_offset : 4'h0) + | (_ways_30_io_resp_hit ? _ways_30_io_resp_brSlots_0_offset : 4'h0) + | (_ways_31_io_resp_hit ? _ways_31_io_resp_brSlots_0_offset : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [3:0] _s1_hit_full_pred_WIRE_11 = + (_ways_0_io_resp_hit ? _ways_0_io_resp_tailSlot_offset : 4'h0) + | (_ways_1_io_resp_hit ? _ways_1_io_resp_tailSlot_offset : 4'h0) + | (_ways_2_io_resp_hit ? _ways_2_io_resp_tailSlot_offset : 4'h0) + | (_ways_3_io_resp_hit ? _ways_3_io_resp_tailSlot_offset : 4'h0) + | (_ways_4_io_resp_hit ? _ways_4_io_resp_tailSlot_offset : 4'h0) + | (_ways_5_io_resp_hit ? _ways_5_io_resp_tailSlot_offset : 4'h0) + | (_ways_6_io_resp_hit ? _ways_6_io_resp_tailSlot_offset : 4'h0) + | (_ways_7_io_resp_hit ? _ways_7_io_resp_tailSlot_offset : 4'h0) + | (_ways_8_io_resp_hit ? _ways_8_io_resp_tailSlot_offset : 4'h0) + | (_ways_9_io_resp_hit ? _ways_9_io_resp_tailSlot_offset : 4'h0) + | (_ways_10_io_resp_hit ? _ways_10_io_resp_tailSlot_offset : 4'h0) + | (_ways_11_io_resp_hit ? _ways_11_io_resp_tailSlot_offset : 4'h0) + | (_ways_12_io_resp_hit ? _ways_12_io_resp_tailSlot_offset : 4'h0) + | (_ways_13_io_resp_hit ? _ways_13_io_resp_tailSlot_offset : 4'h0) + | (_ways_14_io_resp_hit ? _ways_14_io_resp_tailSlot_offset : 4'h0) + | (_ways_15_io_resp_hit ? _ways_15_io_resp_tailSlot_offset : 4'h0) + | (_ways_16_io_resp_hit ? _ways_16_io_resp_tailSlot_offset : 4'h0) + | (_ways_17_io_resp_hit ? _ways_17_io_resp_tailSlot_offset : 4'h0) + | (_ways_18_io_resp_hit ? _ways_18_io_resp_tailSlot_offset : 4'h0) + | (_ways_19_io_resp_hit ? _ways_19_io_resp_tailSlot_offset : 4'h0) + | (_ways_20_io_resp_hit ? _ways_20_io_resp_tailSlot_offset : 4'h0) + | (_ways_21_io_resp_hit ? _ways_21_io_resp_tailSlot_offset : 4'h0) + | (_ways_22_io_resp_hit ? _ways_22_io_resp_tailSlot_offset : 4'h0) + | (_ways_23_io_resp_hit ? _ways_23_io_resp_tailSlot_offset : 4'h0) + | (_ways_24_io_resp_hit ? _ways_24_io_resp_tailSlot_offset : 4'h0) + | (_ways_25_io_resp_hit ? _ways_25_io_resp_tailSlot_offset : 4'h0) + | (_ways_26_io_resp_hit ? _ways_26_io_resp_tailSlot_offset : 4'h0) + | (_ways_27_io_resp_hit ? _ways_27_io_resp_tailSlot_offset : 4'h0) + | (_ways_28_io_resp_hit ? _ways_28_io_resp_tailSlot_offset : 4'h0) + | (_ways_29_io_resp_hit ? _ways_29_io_resp_tailSlot_offset : 4'h0) + | (_ways_30_io_resp_hit ? _ways_30_io_resp_tailSlot_offset : 4'h0) + | (_ways_31_io_resp_hit ? _ways_31_io_resp_tailSlot_offset : 4'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [38:0] _GEN = + (_ways_0_io_resp_hit + ? {(_ways_0_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_0_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_0_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_0_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_1_io_resp_hit + ? {(_ways_1_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_1_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_1_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_1_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_2_io_resp_hit + ? {(_ways_2_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_2_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_2_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_2_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_3_io_resp_hit + ? {(_ways_3_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_3_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_3_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_3_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_4_io_resp_hit + ? {(_ways_4_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_4_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_4_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_4_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_5_io_resp_hit + ? {(_ways_5_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_5_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_5_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_5_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_6_io_resp_hit + ? {(_ways_6_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_6_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_6_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_6_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_7_io_resp_hit + ? {(_ways_7_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_7_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_7_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_7_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_8_io_resp_hit + ? {(_ways_8_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_8_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_8_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_8_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_9_io_resp_hit + ? {(_ways_9_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_9_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_9_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_9_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_10_io_resp_hit + ? {(_ways_10_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_10_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_10_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_10_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_11_io_resp_hit + ? {(_ways_11_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_11_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_11_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_11_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_12_io_resp_hit + ? {(_ways_12_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_12_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_12_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_12_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_13_io_resp_hit + ? {(_ways_13_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_13_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_13_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_13_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_14_io_resp_hit + ? {(_ways_14_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_14_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_14_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_14_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_15_io_resp_hit + ? {(_ways_15_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_15_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_15_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_15_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:97:10, :175:26, :186:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire [38:0] _GEN_0 = + (_ways_16_io_resp_hit + ? {(_ways_16_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_16_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_16_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_16_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_17_io_resp_hit + ? {(_ways_17_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_17_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_17_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_17_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_18_io_resp_hit + ? {(_ways_18_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_18_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_18_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_18_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_19_io_resp_hit + ? {(_ways_19_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_19_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_19_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_19_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_20_io_resp_hit + ? {(_ways_20_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_20_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_20_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_20_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_21_io_resp_hit + ? {(_ways_21_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_21_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_21_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_21_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_22_io_resp_hit + ? {(_ways_22_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_22_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_22_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_22_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_23_io_resp_hit + ? {(_ways_23_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_23_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_23_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_23_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_24_io_resp_hit + ? {(_ways_24_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_24_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_24_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_24_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_25_io_resp_hit + ? {(_ways_25_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_25_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_25_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_25_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_26_io_resp_hit + ? {(_ways_26_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_26_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_26_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_26_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_27_io_resp_hit + ? {(_ways_27_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_27_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_27_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_27_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_28_io_resp_hit + ? {(_ways_28_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_28_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_28_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_28_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_29_io_resp_hit + ? {(_ways_29_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_29_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_29_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_29_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_30_io_resp_hit + ? {(_ways_30_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_30_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_30_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_30_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0) + | (_ways_31_io_resp_hit + ? {(_ways_31_io_resp_brSlots_0_tarStat == 2'h1 + ? 26'(s1_pc_dup_0[38:13] + 26'h1) + : 26'h0) + | (_ways_31_io_resp_brSlots_0_tarStat == 2'h2 + ? 26'(s1_pc_dup_0[38:13] - 26'h1) + : 26'h0) + | (_ways_31_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_31_io_resp_brSlots_0_lower, + 1'h0} + : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:97:10, :175:26, :186:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73 + wire [38:0] _s1_hit_full_pred_WIRE_14 = _GEN | _GEN_0; // src/main/scala/chisel3/util/Mux.scala:30:73 + wire [38:0] _GEN_1 = + (_ways_0_io_resp_hit + ? {_ways_0_io_resp_tailSlot_sharing + ? {(_target_T_18 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_19 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_20 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_0_io_resp_tailSlot_lower[11:0]} + : {(_target_T_18 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_19 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_20 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_0_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_1_io_resp_hit + ? {_ways_1_io_resp_tailSlot_sharing + ? {(_target_T_45 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_46 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_47 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_1_io_resp_tailSlot_lower[11:0]} + : {(_target_T_45 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_46 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_47 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_1_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_2_io_resp_hit + ? {_ways_2_io_resp_tailSlot_sharing + ? {(_target_T_72 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_73 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_74 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_2_io_resp_tailSlot_lower[11:0]} + : {(_target_T_72 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_73 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_74 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_2_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_3_io_resp_hit + ? {_ways_3_io_resp_tailSlot_sharing + ? {(_target_T_99 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_100 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_101 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_3_io_resp_tailSlot_lower[11:0]} + : {(_target_T_99 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_100 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_101 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_3_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_4_io_resp_hit + ? {_ways_4_io_resp_tailSlot_sharing + ? {(_target_T_126 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_127 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_128 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_4_io_resp_tailSlot_lower[11:0]} + : {(_target_T_126 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_127 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_128 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_4_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_5_io_resp_hit + ? {_ways_5_io_resp_tailSlot_sharing + ? {(_target_T_153 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_154 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_155 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_5_io_resp_tailSlot_lower[11:0]} + : {(_target_T_153 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_154 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_155 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_5_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_6_io_resp_hit + ? {_ways_6_io_resp_tailSlot_sharing + ? {(_target_T_180 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_181 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_182 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_6_io_resp_tailSlot_lower[11:0]} + : {(_target_T_180 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_181 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_182 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_6_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_7_io_resp_hit + ? {_ways_7_io_resp_tailSlot_sharing + ? {(_target_T_207 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_208 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_209 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_7_io_resp_tailSlot_lower[11:0]} + : {(_target_T_207 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_208 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_209 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_7_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_8_io_resp_hit + ? {_ways_8_io_resp_tailSlot_sharing + ? {(_target_T_234 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_235 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_236 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_8_io_resp_tailSlot_lower[11:0]} + : {(_target_T_234 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_235 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_236 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_8_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_9_io_resp_hit + ? {_ways_9_io_resp_tailSlot_sharing + ? {(_target_T_261 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_262 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_263 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_9_io_resp_tailSlot_lower[11:0]} + : {(_target_T_261 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_262 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_263 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_9_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_10_io_resp_hit + ? {_ways_10_io_resp_tailSlot_sharing + ? {(_target_T_288 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_289 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_290 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_10_io_resp_tailSlot_lower[11:0]} + : {(_target_T_288 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_289 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_290 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_10_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_11_io_resp_hit + ? {_ways_11_io_resp_tailSlot_sharing + ? {(_target_T_315 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_316 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_317 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_11_io_resp_tailSlot_lower[11:0]} + : {(_target_T_315 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_316 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_317 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_11_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_12_io_resp_hit + ? {_ways_12_io_resp_tailSlot_sharing + ? {(_target_T_342 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_343 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_344 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_12_io_resp_tailSlot_lower[11:0]} + : {(_target_T_342 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_343 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_344 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_12_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_13_io_resp_hit + ? {_ways_13_io_resp_tailSlot_sharing + ? {(_target_T_369 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_370 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_371 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_13_io_resp_tailSlot_lower[11:0]} + : {(_target_T_369 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_370 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_371 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_13_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_14_io_resp_hit + ? {_ways_14_io_resp_tailSlot_sharing + ? {(_target_T_396 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_397 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_398 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_14_io_resp_tailSlot_lower[11:0]} + : {(_target_T_396 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_397 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_398 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_14_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_15_io_resp_hit + ? {_ways_15_io_resp_tailSlot_sharing + ? {(_target_T_423 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_424 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_425 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_15_io_resp_tailSlot_lower[11:0]} + : {(_target_T_423 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_424 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_425 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_15_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [38:0] _GEN_2 = + (_ways_16_io_resp_hit + ? {_ways_16_io_resp_tailSlot_sharing + ? {(_target_T_450 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_451 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_452 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_16_io_resp_tailSlot_lower[11:0]} + : {(_target_T_450 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_451 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_452 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_16_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_17_io_resp_hit + ? {_ways_17_io_resp_tailSlot_sharing + ? {(_target_T_477 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_478 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_479 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_17_io_resp_tailSlot_lower[11:0]} + : {(_target_T_477 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_478 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_479 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_17_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_18_io_resp_hit + ? {_ways_18_io_resp_tailSlot_sharing + ? {(_target_T_504 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_505 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_506 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_18_io_resp_tailSlot_lower[11:0]} + : {(_target_T_504 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_505 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_506 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_18_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_19_io_resp_hit + ? {_ways_19_io_resp_tailSlot_sharing + ? {(_target_T_531 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_532 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_533 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_19_io_resp_tailSlot_lower[11:0]} + : {(_target_T_531 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_532 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_533 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_19_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_20_io_resp_hit + ? {_ways_20_io_resp_tailSlot_sharing + ? {(_target_T_558 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_559 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_560 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_20_io_resp_tailSlot_lower[11:0]} + : {(_target_T_558 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_559 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_560 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_20_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_21_io_resp_hit + ? {_ways_21_io_resp_tailSlot_sharing + ? {(_target_T_585 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_586 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_587 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_21_io_resp_tailSlot_lower[11:0]} + : {(_target_T_585 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_586 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_587 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_21_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_22_io_resp_hit + ? {_ways_22_io_resp_tailSlot_sharing + ? {(_target_T_612 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_613 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_614 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_22_io_resp_tailSlot_lower[11:0]} + : {(_target_T_612 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_613 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_614 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_22_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_23_io_resp_hit + ? {_ways_23_io_resp_tailSlot_sharing + ? {(_target_T_639 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_640 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_641 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_23_io_resp_tailSlot_lower[11:0]} + : {(_target_T_639 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_640 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_641 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_23_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_24_io_resp_hit + ? {_ways_24_io_resp_tailSlot_sharing + ? {(_target_T_666 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_667 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_668 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_24_io_resp_tailSlot_lower[11:0]} + : {(_target_T_666 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_667 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_668 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_24_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_25_io_resp_hit + ? {_ways_25_io_resp_tailSlot_sharing + ? {(_target_T_693 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_694 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_695 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_25_io_resp_tailSlot_lower[11:0]} + : {(_target_T_693 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_694 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_695 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_25_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_26_io_resp_hit + ? {_ways_26_io_resp_tailSlot_sharing + ? {(_target_T_720 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_721 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_722 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_26_io_resp_tailSlot_lower[11:0]} + : {(_target_T_720 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_721 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_722 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_26_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_27_io_resp_hit + ? {_ways_27_io_resp_tailSlot_sharing + ? {(_target_T_747 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_748 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_749 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_27_io_resp_tailSlot_lower[11:0]} + : {(_target_T_747 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_748 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_749 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_27_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_28_io_resp_hit + ? {_ways_28_io_resp_tailSlot_sharing + ? {(_target_T_774 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_775 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_776 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_28_io_resp_tailSlot_lower[11:0]} + : {(_target_T_774 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_775 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_776 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_28_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_29_io_resp_hit + ? {_ways_29_io_resp_tailSlot_sharing + ? {(_target_T_801 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_802 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_803 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_29_io_resp_tailSlot_lower[11:0]} + : {(_target_T_801 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_802 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_803 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_29_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_30_io_resp_hit + ? {_ways_30_io_resp_tailSlot_sharing + ? {(_target_T_828 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_829 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_830 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_30_io_resp_tailSlot_lower[11:0]} + : {(_target_T_828 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_829 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_830 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_30_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0) + | (_ways_31_io_resp_hit + ? {_ways_31_io_resp_tailSlot_sharing + ? {(_target_T_855 ? 26'(s1_pc_dup_0[38:13] + 26'h1) : 26'h0) + | (_target_T_856 ? 26'(s1_pc_dup_0[38:13] - 26'h1) : 26'h0) + | (_target_T_857 ? s1_pc_dup_0[38:13] : 26'h0), + _ways_31_io_resp_tailSlot_lower[11:0]} + : {(_target_T_855 ? 18'(s1_pc_dup_0[38:21] + 18'h1) : 18'h0) + | (_target_T_856 ? 18'(s1_pc_dup_0[38:21] - 18'h1) : 18'h0) + | (_target_T_857 ? s1_pc_dup_0[38:21] : 18'h0), + _ways_31_io_resp_tailSlot_lower}, + 1'h0} + : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, :186:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [38:0] _s1_hit_full_pred_WIRE_15 = _GEN_1 | _GEN_2; // src/main/scala/chisel3/util/Mux.scala:30:73 + wire _s1_hit_full_pred_WIRE_17 = + _ways_0_io_resp_hit & _ways_0_io_resp_brSlots_0_valid | _ways_1_io_resp_hit + & _ways_1_io_resp_brSlots_0_valid | _ways_2_io_resp_hit + & _ways_2_io_resp_brSlots_0_valid | _ways_3_io_resp_hit + & _ways_3_io_resp_brSlots_0_valid | _ways_4_io_resp_hit + & _ways_4_io_resp_brSlots_0_valid | _ways_5_io_resp_hit + & _ways_5_io_resp_brSlots_0_valid | _ways_6_io_resp_hit + & _ways_6_io_resp_brSlots_0_valid | _ways_7_io_resp_hit + & _ways_7_io_resp_brSlots_0_valid | _ways_8_io_resp_hit + & _ways_8_io_resp_brSlots_0_valid | _ways_9_io_resp_hit + & _ways_9_io_resp_brSlots_0_valid | _ways_10_io_resp_hit + & _ways_10_io_resp_brSlots_0_valid | _ways_11_io_resp_hit + & _ways_11_io_resp_brSlots_0_valid | _ways_12_io_resp_hit + & _ways_12_io_resp_brSlots_0_valid | _ways_13_io_resp_hit + & _ways_13_io_resp_brSlots_0_valid | _ways_14_io_resp_hit + & _ways_14_io_resp_brSlots_0_valid | _ways_15_io_resp_hit + & _ways_15_io_resp_brSlots_0_valid | _ways_16_io_resp_hit + & _ways_16_io_resp_brSlots_0_valid | _ways_17_io_resp_hit + & _ways_17_io_resp_brSlots_0_valid | _ways_18_io_resp_hit + & _ways_18_io_resp_brSlots_0_valid | _ways_19_io_resp_hit + & _ways_19_io_resp_brSlots_0_valid | _ways_20_io_resp_hit + & _ways_20_io_resp_brSlots_0_valid | _ways_21_io_resp_hit + & _ways_21_io_resp_brSlots_0_valid | _ways_22_io_resp_hit + & _ways_22_io_resp_brSlots_0_valid | _ways_23_io_resp_hit + & _ways_23_io_resp_brSlots_0_valid | _ways_24_io_resp_hit + & _ways_24_io_resp_brSlots_0_valid | _ways_25_io_resp_hit + & _ways_25_io_resp_brSlots_0_valid | _ways_26_io_resp_hit + & _ways_26_io_resp_brSlots_0_valid | _ways_27_io_resp_hit + & _ways_27_io_resp_brSlots_0_valid | _ways_28_io_resp_hit + & _ways_28_io_resp_brSlots_0_valid | _ways_29_io_resp_hit + & _ways_29_io_resp_brSlots_0_valid | _ways_30_io_resp_hit + & _ways_30_io_resp_brSlots_0_valid | _ways_31_io_resp_hit + & _ways_31_io_resp_brSlots_0_valid; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _s1_hit_full_pred_WIRE_18 = + _ways_0_io_resp_hit & _ways_0_io_resp_tailSlot_valid | _ways_1_io_resp_hit + & _ways_1_io_resp_tailSlot_valid | _ways_2_io_resp_hit + & _ways_2_io_resp_tailSlot_valid | _ways_3_io_resp_hit + & _ways_3_io_resp_tailSlot_valid | _ways_4_io_resp_hit + & _ways_4_io_resp_tailSlot_valid | _ways_5_io_resp_hit + & _ways_5_io_resp_tailSlot_valid | _ways_6_io_resp_hit + & _ways_6_io_resp_tailSlot_valid | _ways_7_io_resp_hit + & _ways_7_io_resp_tailSlot_valid | _ways_8_io_resp_hit + & _ways_8_io_resp_tailSlot_valid | _ways_9_io_resp_hit + & _ways_9_io_resp_tailSlot_valid | _ways_10_io_resp_hit + & _ways_10_io_resp_tailSlot_valid | _ways_11_io_resp_hit + & _ways_11_io_resp_tailSlot_valid | _ways_12_io_resp_hit + & _ways_12_io_resp_tailSlot_valid | _ways_13_io_resp_hit + & _ways_13_io_resp_tailSlot_valid | _ways_14_io_resp_hit + & _ways_14_io_resp_tailSlot_valid | _ways_15_io_resp_hit + & _ways_15_io_resp_tailSlot_valid | _ways_16_io_resp_hit + & _ways_16_io_resp_tailSlot_valid | _ways_17_io_resp_hit + & _ways_17_io_resp_tailSlot_valid | _ways_18_io_resp_hit + & _ways_18_io_resp_tailSlot_valid | _ways_19_io_resp_hit + & _ways_19_io_resp_tailSlot_valid | _ways_20_io_resp_hit + & _ways_20_io_resp_tailSlot_valid | _ways_21_io_resp_hit + & _ways_21_io_resp_tailSlot_valid | _ways_22_io_resp_hit + & _ways_22_io_resp_tailSlot_valid | _ways_23_io_resp_hit + & _ways_23_io_resp_tailSlot_valid | _ways_24_io_resp_hit + & _ways_24_io_resp_tailSlot_valid | _ways_25_io_resp_hit + & _ways_25_io_resp_tailSlot_valid | _ways_26_io_resp_hit + & _ways_26_io_resp_tailSlot_valid | _ways_27_io_resp_hit + & _ways_27_io_resp_tailSlot_valid | _ways_28_io_resp_hit + & _ways_28_io_resp_tailSlot_valid | _ways_29_io_resp_hit + & _ways_29_io_resp_tailSlot_valid | _ways_30_io_resp_hit + & _ways_30_io_resp_tailSlot_valid | _ways_31_io_resp_hit + & _ways_31_io_resp_tailSlot_valid; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire _s1_hit_full_pred_WIRE_20 = + _ways_0_io_resp_hit & (ctrs_0_0[1] | _ways_0_io_resp_always_taken_0) + | _ways_1_io_resp_hit & (ctrs_1_0[1] | _ways_1_io_resp_always_taken_0) + | _ways_2_io_resp_hit & (ctrs_2_0[1] | _ways_2_io_resp_always_taken_0) + | _ways_3_io_resp_hit & (ctrs_3_0[1] | _ways_3_io_resp_always_taken_0) + | _ways_4_io_resp_hit & (ctrs_4_0[1] | _ways_4_io_resp_always_taken_0) + | _ways_5_io_resp_hit & (ctrs_5_0[1] | _ways_5_io_resp_always_taken_0) + | _ways_6_io_resp_hit & (ctrs_6_0[1] | _ways_6_io_resp_always_taken_0) + | _ways_7_io_resp_hit & (ctrs_7_0[1] | _ways_7_io_resp_always_taken_0) + | _ways_8_io_resp_hit & (ctrs_8_0[1] | _ways_8_io_resp_always_taken_0) + | _ways_9_io_resp_hit & (ctrs_9_0[1] | _ways_9_io_resp_always_taken_0) + | _ways_10_io_resp_hit & (ctrs_10_0[1] | _ways_10_io_resp_always_taken_0) + | _ways_11_io_resp_hit & (ctrs_11_0[1] | _ways_11_io_resp_always_taken_0) + | _ways_12_io_resp_hit & (ctrs_12_0[1] | _ways_12_io_resp_always_taken_0) + | _ways_13_io_resp_hit & (ctrs_13_0[1] | _ways_13_io_resp_always_taken_0) + | _ways_14_io_resp_hit & (ctrs_14_0[1] | _ways_14_io_resp_always_taken_0) + | _ways_15_io_resp_hit & (ctrs_15_0[1] | _ways_15_io_resp_always_taken_0) + | _ways_16_io_resp_hit & (ctrs_16_0[1] | _ways_16_io_resp_always_taken_0) + | _ways_17_io_resp_hit & (ctrs_17_0[1] | _ways_17_io_resp_always_taken_0) + | _ways_18_io_resp_hit & (ctrs_18_0[1] | _ways_18_io_resp_always_taken_0) + | _ways_19_io_resp_hit & (ctrs_19_0[1] | _ways_19_io_resp_always_taken_0) + | _ways_20_io_resp_hit & (ctrs_20_0[1] | _ways_20_io_resp_always_taken_0) + | _ways_21_io_resp_hit & (ctrs_21_0[1] | _ways_21_io_resp_always_taken_0) + | _ways_22_io_resp_hit & (ctrs_22_0[1] | _ways_22_io_resp_always_taken_0) + | _ways_23_io_resp_hit & (ctrs_23_0[1] | _ways_23_io_resp_always_taken_0) + | _ways_24_io_resp_hit & (ctrs_24_0[1] | _ways_24_io_resp_always_taken_0) + | _ways_25_io_resp_hit & (ctrs_25_0[1] | _ways_25_io_resp_always_taken_0) + | _ways_26_io_resp_hit & (ctrs_26_0[1] | _ways_26_io_resp_always_taken_0) + | _ways_27_io_resp_hit & (ctrs_27_0[1] | _ways_27_io_resp_always_taken_0) + | _ways_28_io_resp_hit & (ctrs_28_0[1] | _ways_28_io_resp_always_taken_0) + | _ways_29_io_resp_hit & (ctrs_29_0[1] | _ways_29_io_resp_always_taken_0) + | _ways_30_io_resp_hit & (ctrs_30_0[1] | _ways_30_io_resp_always_taken_0) + | _ways_31_io_resp_hit & (ctrs_31_0[1] | _ways_31_io_resp_always_taken_0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73, :111:{34,38} + wire _s1_hit_full_pred_WIRE_21 = + _ways_0_io_resp_hit & (ctrs_0_1[1] | _ways_0_io_resp_always_taken_1) + | _ways_1_io_resp_hit & (ctrs_1_1[1] | _ways_1_io_resp_always_taken_1) + | _ways_2_io_resp_hit & (ctrs_2_1[1] | _ways_2_io_resp_always_taken_1) + | _ways_3_io_resp_hit & (ctrs_3_1[1] | _ways_3_io_resp_always_taken_1) + | _ways_4_io_resp_hit & (ctrs_4_1[1] | _ways_4_io_resp_always_taken_1) + | _ways_5_io_resp_hit & (ctrs_5_1[1] | _ways_5_io_resp_always_taken_1) + | _ways_6_io_resp_hit & (ctrs_6_1[1] | _ways_6_io_resp_always_taken_1) + | _ways_7_io_resp_hit & (ctrs_7_1[1] | _ways_7_io_resp_always_taken_1) + | _ways_8_io_resp_hit & (ctrs_8_1[1] | _ways_8_io_resp_always_taken_1) + | _ways_9_io_resp_hit & (ctrs_9_1[1] | _ways_9_io_resp_always_taken_1) + | _ways_10_io_resp_hit & (ctrs_10_1[1] | _ways_10_io_resp_always_taken_1) + | _ways_11_io_resp_hit & (ctrs_11_1[1] | _ways_11_io_resp_always_taken_1) + | _ways_12_io_resp_hit & (ctrs_12_1[1] | _ways_12_io_resp_always_taken_1) + | _ways_13_io_resp_hit & (ctrs_13_1[1] | _ways_13_io_resp_always_taken_1) + | _ways_14_io_resp_hit & (ctrs_14_1[1] | _ways_14_io_resp_always_taken_1) + | _ways_15_io_resp_hit & (ctrs_15_1[1] | _ways_15_io_resp_always_taken_1) + | _ways_16_io_resp_hit & (ctrs_16_1[1] | _ways_16_io_resp_always_taken_1) + | _ways_17_io_resp_hit & (ctrs_17_1[1] | _ways_17_io_resp_always_taken_1) + | _ways_18_io_resp_hit & (ctrs_18_1[1] | _ways_18_io_resp_always_taken_1) + | _ways_19_io_resp_hit & (ctrs_19_1[1] | _ways_19_io_resp_always_taken_1) + | _ways_20_io_resp_hit & (ctrs_20_1[1] | _ways_20_io_resp_always_taken_1) + | _ways_21_io_resp_hit & (ctrs_21_1[1] | _ways_21_io_resp_always_taken_1) + | _ways_22_io_resp_hit & (ctrs_22_1[1] | _ways_22_io_resp_always_taken_1) + | _ways_23_io_resp_hit & (ctrs_23_1[1] | _ways_23_io_resp_always_taken_1) + | _ways_24_io_resp_hit & (ctrs_24_1[1] | _ways_24_io_resp_always_taken_1) + | _ways_25_io_resp_hit & (ctrs_25_1[1] | _ways_25_io_resp_always_taken_1) + | _ways_26_io_resp_hit & (ctrs_26_1[1] | _ways_26_io_resp_always_taken_1) + | _ways_27_io_resp_hit & (ctrs_27_1[1] | _ways_27_io_resp_always_taken_1) + | _ways_28_io_resp_hit & (ctrs_28_1[1] | _ways_28_io_resp_always_taken_1) + | _ways_29_io_resp_hit & (ctrs_29_1[1] | _ways_29_io_resp_always_taken_1) + | _ways_30_io_resp_hit & (ctrs_30_1[1] | _ways_30_io_resp_always_taken_1) + | _ways_31_io_resp_hit & (ctrs_31_1[1] | _ways_31_io_resp_always_taken_1); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :92:73, :111:{34,38} + reg fauftb_enable; // src/main/scala/xiangshan/frontend/FauFTB.scala:116:30 + wire _io_out_s1_full_pred_3_hit_T = (|s1_hit_oh) & fauftb_enable; // src/main/scala/xiangshan/frontend/FauFTB.scala:101:52, :102:26, :116:30, :118:44 + reg resp_meta_hit_r; // src/main/scala/xiangshan/frontend/FauFTB.scala:122:39 + reg [4:0] resp_meta_pred_way_r; // src/main/scala/xiangshan/frontend/FauFTB.scala:123:44 + reg replacer_touch_ways_0_valid_REG; // src/main/scala/xiangshan/frontend/FauFTB.scala:127:42 + reg [4:0] replacer_touch_ways_0_bits_r; // src/main/scala/xiangshan/frontend/FauFTB.scala:128:44 + reg u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27 + reg [15:0] u_s1_tag; // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + reg [31:0] u_s1_hit_oh; // src/main/scala/xiangshan/frontend/FauFTB.scala:149:33 + reg u_s1_hit; // src/main/scala/xiangshan/frontend/FauFTB.scala:150:33 + wire [31:0] u_s1_write_way_oh = + u_s1_hit + ? u_s1_hit_oh + : 32'h1 + << {27'h0, + state_reg[30], + state_reg[30] + ? {state_reg[29], + state_reg[29] + ? {state_reg[28], + state_reg[28] + ? {state_reg[27], state_reg[27] ? state_reg[26] : state_reg[25]} + : {state_reg[24], state_reg[24] ? state_reg[23] : state_reg[22]}} + : {state_reg[21], + state_reg[21] + ? {state_reg[20], state_reg[20] ? state_reg[19] : state_reg[18]} + : {state_reg[17], state_reg[17] ? state_reg[16] : state_reg[15]}}} + : {state_reg[14], + state_reg[14] + ? {state_reg[13], + state_reg[13] + ? {state_reg[12], state_reg[12] ? state_reg[11] : state_reg[10]} + : {state_reg[9], state_reg[9] ? state_reg[8] : state_reg[7]}} + : {state_reg[6], + state_reg[6] + ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]} + : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/FauFTB.scala:149:33, :150:33, :152:30 + reg [3:0] u_s1_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + reg [11:0] u_s1_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + reg [1:0] u_s1_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + reg u_s1_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + reg [3:0] u_s1_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + reg [19:0] u_s1_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + reg [1:0] u_s1_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + reg u_s1_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + reg u_s1_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + reg [3:0] u_s1_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + reg u_s1_ftb_entry_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + reg u_s1_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + reg u_s1_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + wire u_s1_ways_write_valid_0 = u_s1_write_way_oh[0] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_1 = u_s1_write_way_oh[1] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_2 = u_s1_write_way_oh[2] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_3 = u_s1_write_way_oh[3] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_4 = u_s1_write_way_oh[4] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_5 = u_s1_write_way_oh[5] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_6 = u_s1_write_way_oh[6] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_7 = u_s1_write_way_oh[7] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_8 = u_s1_write_way_oh[8] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_9 = u_s1_write_way_oh[9] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_10 = u_s1_write_way_oh[10] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_11 = u_s1_write_way_oh[11] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_12 = u_s1_write_way_oh[12] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_13 = u_s1_write_way_oh[13] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_14 = u_s1_write_way_oh[14] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_15 = u_s1_write_way_oh[15] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_16 = u_s1_write_way_oh[16] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_17 = u_s1_write_way_oh[17] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_18 = u_s1_write_way_oh[18] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_19 = u_s1_write_way_oh[19] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_20 = u_s1_write_way_oh[20] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_21 = u_s1_write_way_oh[21] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_22 = u_s1_write_way_oh[22] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_23 = u_s1_write_way_oh[23] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_24 = u_s1_write_way_oh[24] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_25 = u_s1_write_way_oh[25] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_26 = u_s1_write_way_oh[26] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_27 = u_s1_write_way_oh[27] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_28 = u_s1_write_way_oh[28] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_29 = u_s1_write_way_oh[29] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_30 = u_s1_write_way_oh[30] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + wire u_s1_ways_write_valid_31 = u_s1_write_way_oh[31] & u_s1_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27, :152:30, :154:{83,94} + reg u_s1_br_update_valids_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:162:40 + reg u_s1_br_update_valids_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:162:40 + reg u_s1_br_takens_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + reg u_s1_br_takens_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + wire [38:0] _GEN_3 = {3'h0, _reset_vector_delay_io_out}; // src/main/scala/xiangshan/frontend/BPU.scala:191:39, utility/src/main/scala/utility/Hold.scala:97:23 + wire [31:0] u_s0_hit_oh = + {_ways_31_io_update_hit, + _ways_30_io_update_hit, + _ways_29_io_update_hit, + _ways_28_io_update_hit, + _ways_27_io_update_hit, + _ways_26_io_update_hit, + _ways_25_io_update_hit, + _ways_24_io_update_hit, + _ways_23_io_update_hit, + _ways_22_io_update_hit, + _ways_21_io_update_hit, + _ways_20_io_update_hit, + _ways_19_io_update_hit, + _ways_18_io_update_hit, + _ways_17_io_update_hit, + _ways_16_io_update_hit, + _ways_15_io_update_hit, + _ways_14_io_update_hit, + _ways_13_io_update_hit, + _ways_12_io_update_hit, + _ways_11_io_update_hit, + _ways_10_io_update_hit, + _ways_9_io_update_hit, + _ways_8_io_update_hit, + _ways_7_io_update_hit, + _ways_6_io_update_hit, + _ways_5_io_update_hit, + _ways_4_io_update_hit, + _ways_3_io_update_hit, + _ways_2_io_update_hit, + _ways_1_io_update_hit, + _ways_0_io_update_hit}; // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47, :139:56 + wire [14:0] _s1_hit_way_T_1 = + {_ways_31_io_resp_hit, + _ways_30_io_resp_hit, + _ways_29_io_resp_hit, + _ways_28_io_resp_hit, + _ways_27_io_resp_hit, + _ways_26_io_resp_hit, + _ways_25_io_resp_hit, + _ways_24_io_resp_hit, + _ways_23_io_resp_hit, + _ways_22_io_resp_hit, + _ways_21_io_resp_hit, + _ways_20_io_resp_hit, + _ways_19_io_resp_hit, + _ways_18_io_resp_hit, + _ways_17_io_resp_hit} + | {_ways_15_io_resp_hit, + _ways_14_io_resp_hit, + _ways_13_io_resp_hit, + _ways_12_io_resp_hit, + _ways_11_io_resp_hit, + _ways_10_io_resp_hit, + _ways_9_io_resp_hit, + _ways_8_io_resp_hit, + _ways_7_io_resp_hit, + _ways_6_io_resp_hit, + _ways_5_io_resp_hit, + _ways_4_io_resp_hit, + _ways_3_io_resp_hit, + _ways_2_io_resp_hit, + _ways_1_io_resp_hit}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + wire [6:0] _s1_hit_way_T_3 = _s1_hit_way_T_1[14:8] | _s1_hit_way_T_1[6:0]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28 + wire [2:0] _s1_hit_way_T_5 = _s1_hit_way_T_3[6:4] | _s1_hit_way_T_3[2:0]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28 + wire [4:0] s1_hit_way = + {|{_ways_31_io_resp_hit, + _ways_30_io_resp_hit, + _ways_29_io_resp_hit, + _ways_28_io_resp_hit, + _ways_27_io_resp_hit, + _ways_26_io_resp_hit, + _ways_25_io_resp_hit, + _ways_24_io_resp_hit, + _ways_23_io_resp_hit, + _ways_22_io_resp_hit, + _ways_21_io_resp_hit, + _ways_20_io_resp_hit, + _ways_19_io_resp_hit, + _ways_18_io_resp_hit, + _ways_17_io_resp_hit, + _ways_16_io_resp_hit}, + |(_s1_hit_way_T_1[14:7]), + |(_s1_hit_way_T_3[6:3]), + |(_s1_hit_way_T_5[2:1]), + _s1_hit_way_T_5[2] | _s1_hit_way_T_5[0]}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + always @(posedge clock) begin + if (REG_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16 + s1_pc_dup_0 <= _GEN_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + s1_pc_dup_1 <= _GEN_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + s1_pc_dup_2 <= _GEN_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + s1_pc_dup_3 <= _GEN_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + end + else begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16 + if (io_s0_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s1_pc_dup_0 <= io_in_bits_s0_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + if (io_s0_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s1_pc_dup_1 <= io_in_bits_s0_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + if (io_s0_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s1_pc_dup_2 <= io_in_bits_s0_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + if (io_s0_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s1_pc_dup_3 <= io_in_bits_s0_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + end + REG <= reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 + REG_1 <= REG & ~reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24,39,42} + fauftb_enable <= io_ctrl_ubtb_enable; // src/main/scala/xiangshan/frontend/FauFTB.scala:116:30 + if (io_s1_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + resp_meta_hit_r <= |s1_hit_oh; // src/main/scala/xiangshan/frontend/FauFTB.scala:101:52, :102:26, :122:39 + resp_meta_pred_way_r <= s1_hit_way; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/FauFTB.scala:123:44 + end + if (io_s2_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + resp_meta_hit_r_1 <= resp_meta_hit_r; // src/main/scala/xiangshan/frontend/FauFTB.scala:122:{29,39} + resp_meta_pred_way_r_1 <= resp_meta_pred_way_r; // src/main/scala/xiangshan/frontend/FauFTB.scala:123:{34,44} + end + replacer_touch_ways_0_valid_REG <= io_s1_fire_0 & (|s1_hit_oh); // src/main/scala/xiangshan/frontend/FauFTB.scala:101:52, :102:26, :127:{42,54} + if (io_s1_fire_0 & (|s1_hit_oh)) // src/main/scala/xiangshan/frontend/FauFTB.scala:101:52, :102:26, :128:68 + replacer_touch_ways_0_bits_r <= s1_hit_way; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/FauFTB.scala:128:44 + u_s1_valid <= io_update_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27 + if (io_update_valid) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + u_s1_tag <= io_update_bits_pc[16:1]; // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28, :148:33 + u_s1_hit_oh <= u_s0_hit_oh; // src/main/scala/xiangshan/frontend/FauFTB.scala:139:56, :149:33 + u_s1_hit <= |u_s0_hit_oh; // src/main/scala/xiangshan/frontend/FauFTB.scala:139:56, :140:30, :150:33 + u_s1_ftb_entry_brSlots_0_offset <= io_update_bits_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + u_s1_ftb_entry_brSlots_0_lower <= io_update_bits_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + u_s1_ftb_entry_brSlots_0_tarStat <= io_update_bits_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + u_s1_ftb_entry_brSlots_0_valid <= io_update_bits_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + u_s1_ftb_entry_tailSlot_offset <= io_update_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + u_s1_ftb_entry_tailSlot_lower <= io_update_bits_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + u_s1_ftb_entry_tailSlot_tarStat <= io_update_bits_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + u_s1_ftb_entry_tailSlot_sharing <= io_update_bits_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + u_s1_ftb_entry_tailSlot_valid <= io_update_bits_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + u_s1_ftb_entry_pftAddr <= io_update_bits_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + u_s1_ftb_entry_carry <= io_update_bits_ftb_entry_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + u_s1_ftb_entry_always_taken_0 <= io_update_bits_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + u_s1_ftb_entry_always_taken_1 <= io_update_bits_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + u_s1_br_update_valids_0 <= + io_update_bits_ftb_entry_brSlots_0_valid & io_update_valid + & ~io_update_bits_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:143:{47,50}, :162:40 + u_s1_br_update_valids_1 <= + io_update_bits_ftb_entry_tailSlot_valid + & io_update_bits_ftb_entry_tailSlot_sharing & io_update_valid + & ~io_update_bits_ftb_entry_always_taken_1 & ~io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:143:{50,84}, :144:7, :162:40 + u_s1_br_takens_0 <= io_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + u_s1_br_takens_1 <= io_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + end + end // always @(posedge) + wire [14:0] _replacer_touch_ways_1_bits_T_1 = + u_s1_write_way_oh[31:17] | u_s1_write_way_oh[15:1]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/FauFTB.scala:152:30 + wire [6:0] _replacer_touch_ways_1_bits_T_3 = + _replacer_touch_ways_1_bits_T_1[14:8] | _replacer_touch_ways_1_bits_T_1[6:0]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28 + wire [2:0] _replacer_touch_ways_1_bits_T_5 = + _replacer_touch_ways_1_bits_T_3[6:4] | _replacer_touch_ways_1_bits_T_3[2:0]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28 + wire _replacer_touch_ways_1_bits_T_7 = + _replacer_touch_ways_1_bits_T_5[2] | _replacer_touch_ways_1_bits_T_5[0]; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28 + wire [14:0] _state_reg_T_52 = + replacer_touch_ways_0_bits_r[4] + ? {~(replacer_touch_ways_0_bits_r[3]), + replacer_touch_ways_0_bits_r[3] + ? {~(replacer_touch_ways_0_bits_r[2]), + replacer_touch_ways_0_bits_r[2] + ? {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[26], + replacer_touch_ways_0_bits_r[1] + ? state_reg[25] + : ~(replacer_touch_ways_0_bits_r[0])} + : state_reg[27:25], + replacer_touch_ways_0_bits_r[2] + ? state_reg[24:22] + : {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[23], + replacer_touch_ways_0_bits_r[1] + ? state_reg[22] + : ~(replacer_touch_ways_0_bits_r[0])}} + : state_reg[28:22], + replacer_touch_ways_0_bits_r[3] + ? state_reg[21:15] + : {~(replacer_touch_ways_0_bits_r[2]), + replacer_touch_ways_0_bits_r[2] + ? {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[19], + replacer_touch_ways_0_bits_r[1] + ? state_reg[18] + : ~(replacer_touch_ways_0_bits_r[0])} + : state_reg[20:18], + replacer_touch_ways_0_bits_r[2] + ? state_reg[17:15] + : {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[16], + replacer_touch_ways_0_bits_r[1] + ? state_reg[15] + : ~(replacer_touch_ways_0_bits_r[0])}}} + : state_reg[29:15]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FauFTB.scala:128:44 + wire [14:0] _state_reg_T_105 = + replacer_touch_ways_0_bits_r[4] + ? state_reg[14:0] + : {~(replacer_touch_ways_0_bits_r[3]), + replacer_touch_ways_0_bits_r[3] + ? {~(replacer_touch_ways_0_bits_r[2]), + replacer_touch_ways_0_bits_r[2] + ? {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[11], + replacer_touch_ways_0_bits_r[1] + ? state_reg[10] + : ~(replacer_touch_ways_0_bits_r[0])} + : state_reg[12:10], + replacer_touch_ways_0_bits_r[2] + ? state_reg[9:7] + : {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[8], + replacer_touch_ways_0_bits_r[1] + ? state_reg[7] + : ~(replacer_touch_ways_0_bits_r[0])}} + : state_reg[13:7], + replacer_touch_ways_0_bits_r[3] + ? state_reg[6:0] + : {~(replacer_touch_ways_0_bits_r[2]), + replacer_touch_ways_0_bits_r[2] + ? {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[4], + replacer_touch_ways_0_bits_r[1] + ? state_reg[3] + : ~(replacer_touch_ways_0_bits_r[0])} + : state_reg[5:3], + replacer_touch_ways_0_bits_r[2] + ? state_reg[2:0] + : {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[1], + replacer_touch_ways_0_bits_r[1] + ? state_reg[0] + : ~(replacer_touch_ways_0_bits_r[0])}}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/FauFTB.scala:128:44 + wire [29:0] _state_reg_T_107 = + replacer_touch_ways_0_valid_REG + ? {_state_reg_T_52, _state_reg_T_105} + : state_reg[29:0]; // rocket-chip/src/main/scala/util/Replacement.scala:22:56, :168:72, :202:12, :203:16, :206:16, src/main/scala/xiangshan/frontend/FauFTB.scala:127:42 + always @(posedge clock or posedge reset) begin + if (reset) begin + ctrs_0_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_0_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_1_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_1_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_2_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_2_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_3_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_3_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_4_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_4_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_5_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_5_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_6_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_6_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_7_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_7_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_8_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_8_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_9_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_9_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_10_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_10_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_11_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_11_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_12_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_12_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_13_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_13_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_14_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_14_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_15_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_15_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_16_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_16_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_17_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_17_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_18_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_18_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_19_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_19_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_20_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_20_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_21_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_21_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_22_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_22_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_23_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_23_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_24_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_24_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_25_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_25_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_26_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_26_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_27_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_27_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_28_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_28_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_29_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_29_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_30_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_30_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_31_0 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_31_1 <= 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + state_reg <= 31'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + end + else begin + if (u_s1_ways_write_valid_0 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_0_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_0_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_0_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_0_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_0_0 <= 2'(ctrs_0_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_0_0 <= 2'(ctrs_0_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_0 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_0_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_0_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_0_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_0_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_0_1 <= 2'(ctrs_0_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_0_1 <= 2'(ctrs_0_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_1 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_1_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_1_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_1_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_1_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_1_0 <= 2'(ctrs_1_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_1_0 <= 2'(ctrs_1_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_1 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_1_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_1_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_1_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_1_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_1_1 <= 2'(ctrs_1_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_1_1 <= 2'(ctrs_1_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_2 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_2_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_2_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_2_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_2_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_2_0 <= 2'(ctrs_2_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_2_0 <= 2'(ctrs_2_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_2 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_2_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_2_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_2_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_2_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_2_1 <= 2'(ctrs_2_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_2_1 <= 2'(ctrs_2_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_3 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_3_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_3_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_3_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_3_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_3_0 <= 2'(ctrs_3_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_3_0 <= 2'(ctrs_3_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_3 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_3_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_3_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_3_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_3_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_3_1 <= 2'(ctrs_3_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_3_1 <= 2'(ctrs_3_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_4 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_4_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_4_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_4_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_4_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_4_0 <= 2'(ctrs_4_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_4_0 <= 2'(ctrs_4_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_4 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_4_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_4_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_4_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_4_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_4_1 <= 2'(ctrs_4_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_4_1 <= 2'(ctrs_4_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_5 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_5_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_5_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_5_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_5_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_5_0 <= 2'(ctrs_5_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_5_0 <= 2'(ctrs_5_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_5 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_5_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_5_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_5_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_5_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_5_1 <= 2'(ctrs_5_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_5_1 <= 2'(ctrs_5_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_6 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_6_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_6_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_6_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_6_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_6_0 <= 2'(ctrs_6_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_6_0 <= 2'(ctrs_6_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_6 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_6_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_6_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_6_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_6_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_6_1 <= 2'(ctrs_6_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_6_1 <= 2'(ctrs_6_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_7 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_7_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_7_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_7_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_7_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_7_0 <= 2'(ctrs_7_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_7_0 <= 2'(ctrs_7_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_7 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_7_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_7_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_7_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_7_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_7_1 <= 2'(ctrs_7_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_7_1 <= 2'(ctrs_7_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_8 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_8_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_8_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_8_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_8_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_8_0 <= 2'(ctrs_8_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_8_0 <= 2'(ctrs_8_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_8 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_8_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_8_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_8_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_8_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_8_1 <= 2'(ctrs_8_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_8_1 <= 2'(ctrs_8_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_9 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_9_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_9_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_9_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_9_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_9_0 <= 2'(ctrs_9_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_9_0 <= 2'(ctrs_9_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_9 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_9_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_9_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_9_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_9_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_9_1 <= 2'(ctrs_9_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_9_1 <= 2'(ctrs_9_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_10 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_10_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_10_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_10_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_10_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_10_0 <= 2'(ctrs_10_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_10_0 <= 2'(ctrs_10_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_10 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_10_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_10_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_10_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_10_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_10_1 <= 2'(ctrs_10_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_10_1 <= 2'(ctrs_10_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_11 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_11_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_11_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_11_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_11_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_11_0 <= 2'(ctrs_11_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_11_0 <= 2'(ctrs_11_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_11 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_11_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_11_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_11_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_11_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_11_1 <= 2'(ctrs_11_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_11_1 <= 2'(ctrs_11_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_12 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_12_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_12_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_12_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_12_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_12_0 <= 2'(ctrs_12_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_12_0 <= 2'(ctrs_12_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_12 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_12_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_12_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_12_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_12_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_12_1 <= 2'(ctrs_12_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_12_1 <= 2'(ctrs_12_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_13 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_13_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_13_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_13_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_13_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_13_0 <= 2'(ctrs_13_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_13_0 <= 2'(ctrs_13_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_13 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_13_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_13_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_13_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_13_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_13_1 <= 2'(ctrs_13_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_13_1 <= 2'(ctrs_13_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_14 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_14_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_14_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_14_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_14_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_14_0 <= 2'(ctrs_14_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_14_0 <= 2'(ctrs_14_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_14 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_14_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_14_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_14_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_14_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_14_1 <= 2'(ctrs_14_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_14_1 <= 2'(ctrs_14_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_15 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_15_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_15_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_15_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_15_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_15_0 <= 2'(ctrs_15_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_15_0 <= 2'(ctrs_15_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_15 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_15_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_15_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_15_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_15_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_15_1 <= 2'(ctrs_15_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_15_1 <= 2'(ctrs_15_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_16 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_16_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_16_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_16_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_16_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_16_0 <= 2'(ctrs_16_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_16_0 <= 2'(ctrs_16_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_16 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_16_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_16_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_16_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_16_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_16_1 <= 2'(ctrs_16_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_16_1 <= 2'(ctrs_16_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_17 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_17_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_17_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_17_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_17_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_17_0 <= 2'(ctrs_17_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_17_0 <= 2'(ctrs_17_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_17 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_17_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_17_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_17_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_17_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_17_1 <= 2'(ctrs_17_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_17_1 <= 2'(ctrs_17_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_18 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_18_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_18_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_18_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_18_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_18_0 <= 2'(ctrs_18_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_18_0 <= 2'(ctrs_18_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_18 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_18_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_18_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_18_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_18_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_18_1 <= 2'(ctrs_18_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_18_1 <= 2'(ctrs_18_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_19 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_19_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_19_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_19_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_19_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_19_0 <= 2'(ctrs_19_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_19_0 <= 2'(ctrs_19_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_19 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_19_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_19_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_19_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_19_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_19_1 <= 2'(ctrs_19_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_19_1 <= 2'(ctrs_19_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_20 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_20_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_20_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_20_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_20_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_20_0 <= 2'(ctrs_20_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_20_0 <= 2'(ctrs_20_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_20 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_20_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_20_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_20_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_20_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_20_1 <= 2'(ctrs_20_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_20_1 <= 2'(ctrs_20_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_21 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_21_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_21_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_21_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_21_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_21_0 <= 2'(ctrs_21_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_21_0 <= 2'(ctrs_21_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_21 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_21_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_21_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_21_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_21_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_21_1 <= 2'(ctrs_21_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_21_1 <= 2'(ctrs_21_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_22 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_22_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_22_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_22_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_22_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_22_0 <= 2'(ctrs_22_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_22_0 <= 2'(ctrs_22_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_22 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_22_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_22_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_22_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_22_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_22_1 <= 2'(ctrs_22_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_22_1 <= 2'(ctrs_22_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_23 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_23_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_23_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_23_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_23_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_23_0 <= 2'(ctrs_23_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_23_0 <= 2'(ctrs_23_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_23 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_23_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_23_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_23_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_23_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_23_1 <= 2'(ctrs_23_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_23_1 <= 2'(ctrs_23_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_24 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_24_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_24_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_24_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_24_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_24_0 <= 2'(ctrs_24_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_24_0 <= 2'(ctrs_24_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_24 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_24_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_24_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_24_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_24_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_24_1 <= 2'(ctrs_24_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_24_1 <= 2'(ctrs_24_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_25 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_25_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_25_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_25_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_25_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_25_0 <= 2'(ctrs_25_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_25_0 <= 2'(ctrs_25_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_25 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_25_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_25_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_25_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_25_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_25_1 <= 2'(ctrs_25_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_25_1 <= 2'(ctrs_25_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_26 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_26_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_26_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_26_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_26_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_26_0 <= 2'(ctrs_26_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_26_0 <= 2'(ctrs_26_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_26 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_26_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_26_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_26_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_26_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_26_1 <= 2'(ctrs_26_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_26_1 <= 2'(ctrs_26_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_27 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_27_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_27_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_27_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_27_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_27_0 <= 2'(ctrs_27_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_27_0 <= 2'(ctrs_27_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_27 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_27_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_27_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_27_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_27_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_27_1 <= 2'(ctrs_27_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_27_1 <= 2'(ctrs_27_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_28 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_28_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_28_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_28_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_28_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_28_0 <= 2'(ctrs_28_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_28_0 <= 2'(ctrs_28_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_28 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_28_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_28_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_28_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_28_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_28_1 <= 2'(ctrs_28_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_28_1 <= 2'(ctrs_28_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_29 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_29_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_29_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_29_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_29_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_29_0 <= 2'(ctrs_29_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_29_0 <= 2'(ctrs_29_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_29 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_29_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_29_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_29_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_29_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_29_1 <= 2'(ctrs_29_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_29_1 <= 2'(ctrs_29_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_30 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_30_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_30_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_30_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_30_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_30_0 <= 2'(ctrs_30_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_30_0 <= 2'(ctrs_30_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_30 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_30_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_30_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_30_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_30_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_30_1 <= 2'(ctrs_30_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_30_1 <= 2'(ctrs_30_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_31 & u_s1_br_update_valids_0) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_31_0) & u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_31_0 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_31_0 == 2'h0 & ~u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_31_0 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_0) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_31_0 <= 2'(ctrs_31_0 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_31_0 <= 2'(ctrs_31_0 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (u_s1_ways_write_valid_31 & u_s1_br_update_valids_1) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :154:94, :162:40, :165:37, :167:42, :168:23 + if ((&ctrs_31_1) & u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_31_1 <= 2'h3; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (ctrs_31_1 == 2'h0 & ~u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:{10,26,29}, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73, :163:40 + ctrs_31_1 <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:97:10, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else if (u_s1_br_takens_1) // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_31_1 <= 2'(ctrs_31_1 + 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/FTB.scala:98:19, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + else // src/main/scala/xiangshan/frontend/FauFTB.scala:163:40 + ctrs_31_1 <= 2'(ctrs_31_1 - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + end + if (replacer_touch_ways_0_valid_REG | u_s1_valid) begin // rocket-chip/src/main/scala/util/package.scala:73:59, src/main/scala/xiangshan/frontend/FauFTB.scala:127:42, :147:27 + if (u_s1_valid) // src/main/scala/xiangshan/frontend/FauFTB.scala:147:27 + state_reg <= + {~(|(u_s1_write_way_oh[31:16])), + (|(u_s1_write_way_oh[31:16])) + ? {~(|(_replacer_touch_ways_1_bits_T_1[14:7])), + (|(_replacer_touch_ways_1_bits_T_1[14:7])) + ? {~(|(_replacer_touch_ways_1_bits_T_3[6:3])), + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[26], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[25] + : ~_replacer_touch_ways_1_bits_T_7} + : _state_reg_T_107[27:25], + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? _state_reg_T_107[24:22] + : {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[23], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[22] + : ~_replacer_touch_ways_1_bits_T_7}} + : _state_reg_T_107[28:22], + (|(_replacer_touch_ways_1_bits_T_1[14:7])) + ? _state_reg_T_107[21:15] + : {~(|(_replacer_touch_ways_1_bits_T_3[6:3])), + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[19], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[18] + : ~_replacer_touch_ways_1_bits_T_7} + : _state_reg_T_107[20:18], + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? _state_reg_T_107[17:15] + : {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[16], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[15] + : ~_replacer_touch_ways_1_bits_T_7}}} + : _state_reg_T_107[29:15], + (|(u_s1_write_way_oh[31:16])) + ? _state_reg_T_107[14:0] + : {~(|(_replacer_touch_ways_1_bits_T_1[14:7])), + (|(_replacer_touch_ways_1_bits_T_1[14:7])) + ? {~(|(_replacer_touch_ways_1_bits_T_3[6:3])), + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[11], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[10] + : ~_replacer_touch_ways_1_bits_T_7} + : _state_reg_T_107[12:10], + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? _state_reg_T_107[9:7] + : {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[8], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[7] + : ~_replacer_touch_ways_1_bits_T_7}} + : _state_reg_T_107[13:7], + (|(_replacer_touch_ways_1_bits_T_1[14:7])) + ? _state_reg_T_107[6:0] + : {~(|(_replacer_touch_ways_1_bits_T_3[6:3])), + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[4], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[3] + : ~_replacer_touch_ways_1_bits_T_7} + : _state_reg_T_107[5:3], + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? _state_reg_T_107[2:0] + : {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[1], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[0] + : ~_replacer_touch_ways_1_bits_T_7}}}}; // rocket-chip/src/main/scala/util/Replacement.scala:22:56, :168:72, :196:33, :198:38, :202:12, :203:16, :206:16, :218:7, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{14,28}, src/main/scala/xiangshan/frontend/FauFTB.scala:152:30 + else if (replacer_touch_ways_0_valid_REG) // src/main/scala/xiangshan/frontend/FauFTB.scala:127:42 + state_reg <= + {~(replacer_touch_ways_0_bits_r[4]), _state_reg_T_52, _state_reg_T_105}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, src/main/scala/xiangshan/frontend/FauFTB.scala:128:44 + end + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:23]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + initial begin // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + for (logic [4:0] i = 5'h0; i < 5'h18; i += 5'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + end // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + s1_pc_dup_0 = {_RANDOM[5'h0], _RANDOM[5'h1][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + s1_pc_dup_1 = {_RANDOM[5'h1][31:7], _RANDOM[5'h2][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + s1_pc_dup_2 = {_RANDOM[5'h2][31:14], _RANDOM[5'h3][20:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + s1_pc_dup_3 = {_RANDOM[5'h3][31:21], _RANDOM[5'h4][27:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + REG = _RANDOM[5'hE][20]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + REG_1 = _RANDOM[5'hE][21]; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24}, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + ctrs_0_0 = _RANDOM[5'hE][23:22]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_0_1 = _RANDOM[5'hE][25:24]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_1_0 = _RANDOM[5'hE][27:26]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_1_1 = _RANDOM[5'hE][29:28]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_2_0 = _RANDOM[5'hE][31:30]; // src/main/scala/xiangshan/frontend/BPU.scala:190:24, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_2_1 = _RANDOM[5'hF][1:0]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_3_0 = _RANDOM[5'hF][3:2]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_3_1 = _RANDOM[5'hF][5:4]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_4_0 = _RANDOM[5'hF][7:6]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_4_1 = _RANDOM[5'hF][9:8]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_5_0 = _RANDOM[5'hF][11:10]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_5_1 = _RANDOM[5'hF][13:12]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_6_0 = _RANDOM[5'hF][15:14]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_6_1 = _RANDOM[5'hF][17:16]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_7_0 = _RANDOM[5'hF][19:18]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_7_1 = _RANDOM[5'hF][21:20]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_8_0 = _RANDOM[5'hF][23:22]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_8_1 = _RANDOM[5'hF][25:24]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_9_0 = _RANDOM[5'hF][27:26]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_9_1 = _RANDOM[5'hF][29:28]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_10_0 = _RANDOM[5'hF][31:30]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_10_1 = _RANDOM[5'h10][1:0]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_11_0 = _RANDOM[5'h10][3:2]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_11_1 = _RANDOM[5'h10][5:4]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_12_0 = _RANDOM[5'h10][7:6]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_12_1 = _RANDOM[5'h10][9:8]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_13_0 = _RANDOM[5'h10][11:10]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_13_1 = _RANDOM[5'h10][13:12]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_14_0 = _RANDOM[5'h10][15:14]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_14_1 = _RANDOM[5'h10][17:16]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_15_0 = _RANDOM[5'h10][19:18]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_15_1 = _RANDOM[5'h10][21:20]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_16_0 = _RANDOM[5'h10][23:22]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_16_1 = _RANDOM[5'h10][25:24]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_17_0 = _RANDOM[5'h10][27:26]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_17_1 = _RANDOM[5'h10][29:28]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_18_0 = _RANDOM[5'h10][31:30]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_18_1 = _RANDOM[5'h11][1:0]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_19_0 = _RANDOM[5'h11][3:2]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_19_1 = _RANDOM[5'h11][5:4]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_20_0 = _RANDOM[5'h11][7:6]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_20_1 = _RANDOM[5'h11][9:8]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_21_0 = _RANDOM[5'h11][11:10]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_21_1 = _RANDOM[5'h11][13:12]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_22_0 = _RANDOM[5'h11][15:14]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_22_1 = _RANDOM[5'h11][17:16]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_23_0 = _RANDOM[5'h11][19:18]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_23_1 = _RANDOM[5'h11][21:20]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_24_0 = _RANDOM[5'h11][23:22]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_24_1 = _RANDOM[5'h11][25:24]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_25_0 = _RANDOM[5'h11][27:26]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_25_1 = _RANDOM[5'h11][29:28]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_26_0 = _RANDOM[5'h11][31:30]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_26_1 = _RANDOM[5'h12][1:0]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_27_0 = _RANDOM[5'h12][3:2]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_27_1 = _RANDOM[5'h12][5:4]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_28_0 = _RANDOM[5'h12][7:6]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_28_1 = _RANDOM[5'h12][9:8]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_29_0 = _RANDOM[5'h12][11:10]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_29_1 = _RANDOM[5'h12][13:12]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_30_0 = _RANDOM[5'h12][15:14]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_30_1 = _RANDOM[5'h12][17:16]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_31_0 = _RANDOM[5'h12][19:18]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + ctrs_31_1 = _RANDOM[5'h12][21:20]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + state_reg = {_RANDOM[5'h12][31:22], _RANDOM[5'h13][20:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :92:73 + fauftb_enable = _RANDOM[5'h13][21]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :116:30 + resp_meta_hit_r = _RANDOM[5'h13][22]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :122:39 + resp_meta_hit_r_1 = _RANDOM[5'h13][23]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :122:29 + resp_meta_pred_way_r = _RANDOM[5'h13][28:24]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:44 + resp_meta_pred_way_r_1 = {_RANDOM[5'h13][31:29], _RANDOM[5'h14][1:0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:34 + replacer_touch_ways_0_valid_REG = _RANDOM[5'h14][2]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:34, :127:42 + replacer_touch_ways_0_bits_r = _RANDOM[5'h14][7:3]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:34, :128:44 + u_s1_valid = _RANDOM[5'h14][8]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:34, :147:27 + u_s1_tag = _RANDOM[5'h14][24:9]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:34, :148:33 + u_s1_hit_oh = {_RANDOM[5'h14][31:25], _RANDOM[5'h15][24:0]}; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :123:34, :149:33 + u_s1_hit = _RANDOM[5'h15][25]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :149:33, :150:33 + u_s1_ftb_entry_brSlots_0_offset = _RANDOM[5'h15][30:27]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :149:33, :153:33 + u_s1_ftb_entry_brSlots_0_lower = {_RANDOM[5'h15][31], _RANDOM[5'h16][10:0]}; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :149:33, :153:33 + u_s1_ftb_entry_brSlots_0_tarStat = _RANDOM[5'h16][12:11]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 + u_s1_ftb_entry_brSlots_0_valid = _RANDOM[5'h16][14]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 + u_s1_ftb_entry_tailSlot_offset = _RANDOM[5'h16][18:15]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 + u_s1_ftb_entry_tailSlot_lower = {_RANDOM[5'h16][31:19], _RANDOM[5'h17][6:0]}; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 + u_s1_ftb_entry_tailSlot_tarStat = _RANDOM[5'h17][8:7]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 + u_s1_ftb_entry_tailSlot_sharing = _RANDOM[5'h17][9]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 + u_s1_ftb_entry_tailSlot_valid = _RANDOM[5'h17][10]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 + u_s1_ftb_entry_pftAddr = _RANDOM[5'h17][14:11]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 + u_s1_ftb_entry_carry = _RANDOM[5'h17][15]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 + u_s1_ftb_entry_always_taken_0 = _RANDOM[5'h17][20]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 + u_s1_ftb_entry_always_taken_1 = _RANDOM[5'h17][21]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33 + u_s1_br_update_valids_0 = _RANDOM[5'h17][22]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33, :162:40 + u_s1_br_update_valids_1 = _RANDOM[5'h17][23]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33, :162:40 + u_s1_br_takens_0 = _RANDOM[5'h17][24]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33, :163:40 + u_s1_br_takens_1 = _RANDOM[5'h17][25]; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :153:33, :163:40 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + ctrs_0_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_0_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_1_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_1_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_2_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_2_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_3_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_3_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_4_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_4_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_5_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_5_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_6_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_6_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_7_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_7_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_8_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_8_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_9_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_9_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_10_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_10_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_11_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_11_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_12_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_12_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_13_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_13_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_14_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_14_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_15_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_15_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_16_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_16_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_17_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_17_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_18_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_18_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_19_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_19_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_20_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_20_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_21_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_21_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_22_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_22_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_23_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_23_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_24_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_24_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_25_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_25_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_26_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_26_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_27_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_27_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_28_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_28_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_29_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_29_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_30_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_30_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_31_0 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + ctrs_31_1 = 2'h2; // src/main/scala/xiangshan/frontend/FauFTB.scala:92:73 + state_reg = 31'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72 + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + DelayN_2 reset_vector_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + .clock (clock), + .io_in (io_reset_vector), + .io_out (_reset_vector_delay_io_out) + ); + FauFTBWay ways_0 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_0_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_0_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_0_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_0_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_0_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_0_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_0_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_0_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_0_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_0_io_resp_pftAddr), + .io_resp_carry (_ways_0_io_resp_carry), + .io_resp_always_taken_0 (_ways_0_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_0_io_resp_always_taken_1), + .io_resp_hit (_ways_0_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_0_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_1 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_1_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_1_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_1_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_1_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_1_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_1_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_1_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_1_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_1_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_1_io_resp_pftAddr), + .io_resp_carry (_ways_1_io_resp_carry), + .io_resp_always_taken_0 (_ways_1_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_1_io_resp_always_taken_1), + .io_resp_hit (_ways_1_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_1_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_2 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_2_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_2_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_2_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_2_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_2_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_2_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_2_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_2_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_2_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_2_io_resp_pftAddr), + .io_resp_carry (_ways_2_io_resp_carry), + .io_resp_always_taken_0 (_ways_2_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_2_io_resp_always_taken_1), + .io_resp_hit (_ways_2_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_2_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_2), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_3 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_3_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_3_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_3_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_3_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_3_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_3_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_3_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_3_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_3_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_3_io_resp_pftAddr), + .io_resp_carry (_ways_3_io_resp_carry), + .io_resp_always_taken_0 (_ways_3_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_3_io_resp_always_taken_1), + .io_resp_hit (_ways_3_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_3_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_3), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_4 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_4_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_4_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_4_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_4_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_4_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_4_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_4_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_4_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_4_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_4_io_resp_pftAddr), + .io_resp_carry (_ways_4_io_resp_carry), + .io_resp_always_taken_0 (_ways_4_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_4_io_resp_always_taken_1), + .io_resp_hit (_ways_4_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_4_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_4), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_5 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_5_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_5_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_5_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_5_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_5_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_5_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_5_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_5_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_5_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_5_io_resp_pftAddr), + .io_resp_carry (_ways_5_io_resp_carry), + .io_resp_always_taken_0 (_ways_5_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_5_io_resp_always_taken_1), + .io_resp_hit (_ways_5_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_5_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_5), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_6 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_6_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_6_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_6_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_6_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_6_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_6_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_6_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_6_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_6_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_6_io_resp_pftAddr), + .io_resp_carry (_ways_6_io_resp_carry), + .io_resp_always_taken_0 (_ways_6_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_6_io_resp_always_taken_1), + .io_resp_hit (_ways_6_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_6_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_6), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_7 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_7_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_7_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_7_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_7_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_7_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_7_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_7_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_7_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_7_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_7_io_resp_pftAddr), + .io_resp_carry (_ways_7_io_resp_carry), + .io_resp_always_taken_0 (_ways_7_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_7_io_resp_always_taken_1), + .io_resp_hit (_ways_7_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_7_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_7), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_8 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_8_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_8_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_8_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_8_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_8_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_8_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_8_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_8_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_8_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_8_io_resp_pftAddr), + .io_resp_carry (_ways_8_io_resp_carry), + .io_resp_always_taken_0 (_ways_8_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_8_io_resp_always_taken_1), + .io_resp_hit (_ways_8_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_8_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_8), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_9 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_9_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_9_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_9_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_9_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_9_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_9_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_9_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_9_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_9_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_9_io_resp_pftAddr), + .io_resp_carry (_ways_9_io_resp_carry), + .io_resp_always_taken_0 (_ways_9_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_9_io_resp_always_taken_1), + .io_resp_hit (_ways_9_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_9_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_9), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_10 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_10_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_10_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_10_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_10_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_10_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_10_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_10_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_10_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_10_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_10_io_resp_pftAddr), + .io_resp_carry (_ways_10_io_resp_carry), + .io_resp_always_taken_0 (_ways_10_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_10_io_resp_always_taken_1), + .io_resp_hit (_ways_10_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_10_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_10), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_11 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_11_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_11_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_11_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_11_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_11_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_11_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_11_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_11_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_11_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_11_io_resp_pftAddr), + .io_resp_carry (_ways_11_io_resp_carry), + .io_resp_always_taken_0 (_ways_11_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_11_io_resp_always_taken_1), + .io_resp_hit (_ways_11_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_11_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_11), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_12 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_12_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_12_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_12_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_12_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_12_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_12_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_12_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_12_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_12_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_12_io_resp_pftAddr), + .io_resp_carry (_ways_12_io_resp_carry), + .io_resp_always_taken_0 (_ways_12_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_12_io_resp_always_taken_1), + .io_resp_hit (_ways_12_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_12_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_12), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_13 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_13_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_13_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_13_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_13_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_13_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_13_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_13_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_13_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_13_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_13_io_resp_pftAddr), + .io_resp_carry (_ways_13_io_resp_carry), + .io_resp_always_taken_0 (_ways_13_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_13_io_resp_always_taken_1), + .io_resp_hit (_ways_13_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_13_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_13), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_14 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_14_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_14_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_14_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_14_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_14_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_14_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_14_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_14_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_14_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_14_io_resp_pftAddr), + .io_resp_carry (_ways_14_io_resp_carry), + .io_resp_always_taken_0 (_ways_14_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_14_io_resp_always_taken_1), + .io_resp_hit (_ways_14_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_14_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_14), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_15 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_15_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_15_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_15_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_15_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_15_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_15_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_15_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_15_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_15_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_15_io_resp_pftAddr), + .io_resp_carry (_ways_15_io_resp_carry), + .io_resp_always_taken_0 (_ways_15_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_15_io_resp_always_taken_1), + .io_resp_hit (_ways_15_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_15_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_15), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_16 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_16_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_16_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_16_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_16_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_16_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_16_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_16_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_16_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_16_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_16_io_resp_pftAddr), + .io_resp_carry (_ways_16_io_resp_carry), + .io_resp_always_taken_0 (_ways_16_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_16_io_resp_always_taken_1), + .io_resp_hit (_ways_16_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_16_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_16), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_17 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_17_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_17_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_17_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_17_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_17_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_17_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_17_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_17_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_17_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_17_io_resp_pftAddr), + .io_resp_carry (_ways_17_io_resp_carry), + .io_resp_always_taken_0 (_ways_17_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_17_io_resp_always_taken_1), + .io_resp_hit (_ways_17_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_17_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_17), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_18 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_18_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_18_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_18_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_18_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_18_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_18_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_18_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_18_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_18_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_18_io_resp_pftAddr), + .io_resp_carry (_ways_18_io_resp_carry), + .io_resp_always_taken_0 (_ways_18_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_18_io_resp_always_taken_1), + .io_resp_hit (_ways_18_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_18_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_18), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_19 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_19_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_19_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_19_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_19_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_19_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_19_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_19_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_19_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_19_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_19_io_resp_pftAddr), + .io_resp_carry (_ways_19_io_resp_carry), + .io_resp_always_taken_0 (_ways_19_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_19_io_resp_always_taken_1), + .io_resp_hit (_ways_19_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_19_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_19), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_20 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_20_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_20_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_20_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_20_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_20_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_20_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_20_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_20_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_20_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_20_io_resp_pftAddr), + .io_resp_carry (_ways_20_io_resp_carry), + .io_resp_always_taken_0 (_ways_20_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_20_io_resp_always_taken_1), + .io_resp_hit (_ways_20_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_20_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_20), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_21 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_21_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_21_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_21_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_21_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_21_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_21_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_21_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_21_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_21_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_21_io_resp_pftAddr), + .io_resp_carry (_ways_21_io_resp_carry), + .io_resp_always_taken_0 (_ways_21_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_21_io_resp_always_taken_1), + .io_resp_hit (_ways_21_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_21_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_21), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_22 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_22_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_22_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_22_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_22_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_22_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_22_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_22_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_22_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_22_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_22_io_resp_pftAddr), + .io_resp_carry (_ways_22_io_resp_carry), + .io_resp_always_taken_0 (_ways_22_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_22_io_resp_always_taken_1), + .io_resp_hit (_ways_22_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_22_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_22), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_23 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_23_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_23_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_23_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_23_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_23_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_23_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_23_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_23_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_23_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_23_io_resp_pftAddr), + .io_resp_carry (_ways_23_io_resp_carry), + .io_resp_always_taken_0 (_ways_23_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_23_io_resp_always_taken_1), + .io_resp_hit (_ways_23_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_23_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_23), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_24 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_24_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_24_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_24_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_24_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_24_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_24_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_24_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_24_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_24_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_24_io_resp_pftAddr), + .io_resp_carry (_ways_24_io_resp_carry), + .io_resp_always_taken_0 (_ways_24_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_24_io_resp_always_taken_1), + .io_resp_hit (_ways_24_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_24_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_24), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_25 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_25_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_25_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_25_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_25_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_25_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_25_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_25_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_25_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_25_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_25_io_resp_pftAddr), + .io_resp_carry (_ways_25_io_resp_carry), + .io_resp_always_taken_0 (_ways_25_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_25_io_resp_always_taken_1), + .io_resp_hit (_ways_25_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_25_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_25), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_26 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_26_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_26_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_26_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_26_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_26_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_26_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_26_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_26_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_26_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_26_io_resp_pftAddr), + .io_resp_carry (_ways_26_io_resp_carry), + .io_resp_always_taken_0 (_ways_26_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_26_io_resp_always_taken_1), + .io_resp_hit (_ways_26_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_26_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_26), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_27 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_27_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_27_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_27_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_27_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_27_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_27_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_27_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_27_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_27_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_27_io_resp_pftAddr), + .io_resp_carry (_ways_27_io_resp_carry), + .io_resp_always_taken_0 (_ways_27_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_27_io_resp_always_taken_1), + .io_resp_hit (_ways_27_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_27_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_27), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_28 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_28_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_28_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_28_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_28_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_28_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_28_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_28_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_28_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_28_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_28_io_resp_pftAddr), + .io_resp_carry (_ways_28_io_resp_carry), + .io_resp_always_taken_0 (_ways_28_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_28_io_resp_always_taken_1), + .io_resp_hit (_ways_28_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_28_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_28), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_29 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_29_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_29_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_29_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_29_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_29_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_29_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_29_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_29_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_29_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_29_io_resp_pftAddr), + .io_resp_carry (_ways_29_io_resp_carry), + .io_resp_always_taken_0 (_ways_29_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_29_io_resp_always_taken_1), + .io_resp_hit (_ways_29_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_29_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_29), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_30 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_30_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_30_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_30_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_30_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_30_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_30_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_30_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_30_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_30_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_30_io_resp_pftAddr), + .io_resp_carry (_ways_30_io_resp_carry), + .io_resp_always_taken_0 (_ways_30_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_30_io_resp_always_taken_1), + .io_resp_hit (_ways_30_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_30_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_30), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + FauFTBWay ways_31 ( // src/main/scala/xiangshan/frontend/FauFTB.scala:90:47 + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_resp_brSlots_0_offset (_ways_31_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_31_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_31_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_31_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_31_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_31_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_31_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_31_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_31_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_31_io_resp_pftAddr), + .io_resp_carry (_ways_31_io_resp_carry), + .io_resp_always_taken_0 (_ways_31_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_31_io_resp_always_taken_1), + .io_resp_hit (_ways_31_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), // src/main/scala/xiangshan/frontend/FauFTB.scala:39:28 + .io_update_hit (_ways_31_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_31), // src/main/scala/xiangshan/frontend/FauFTB.scala:154:94 + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_carry (u_s1_ftb_entry_carry), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/FauFTB.scala:153:33 + .io_write_tag (u_s1_tag) // src/main/scala/xiangshan/frontend/FauFTB.scala:148:33 + ); + assign io_out_s1_pc_0 = s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_pc_1 = s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_pc_2 = s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_pc_3 = s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_0_br_taken_mask_0 = _s1_hit_full_pred_WIRE_20; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_0_br_taken_mask_1 = _s1_hit_full_pred_WIRE_21; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_0_slot_valids_0 = _s1_hit_full_pred_WIRE_17; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_0_slot_valids_1 = _s1_hit_full_pred_WIRE_18; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_0_targets_0 = _s1_hit_full_pred_WIRE_14; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_0_targets_1 = _s1_hit_full_pred_WIRE_15; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_0_offsets_0 = _s1_hit_full_pred_WIRE_10; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_0_offsets_1 = _s1_hit_full_pred_WIRE_11; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_0_fallThroughAddr = _s1_hit_full_pred_WIRE_8; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_0_is_br_sharing = _s1_hit_full_pred_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_0_hit = _io_out_s1_full_pred_3_hit_T; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :118:44 + assign io_out_s1_full_pred_1_br_taken_mask_0 = _s1_hit_full_pred_WIRE_20; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_1_br_taken_mask_1 = _s1_hit_full_pred_WIRE_21; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_1_slot_valids_0 = _s1_hit_full_pred_WIRE_17; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_1_slot_valids_1 = _s1_hit_full_pred_WIRE_18; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_1_targets_0 = _s1_hit_full_pred_WIRE_14; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_1_targets_1 = _s1_hit_full_pred_WIRE_15; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_1_offsets_0 = _s1_hit_full_pred_WIRE_10; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_1_offsets_1 = _s1_hit_full_pred_WIRE_11; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_1_fallThroughAddr = _s1_hit_full_pred_WIRE_8; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_1_is_br_sharing = _s1_hit_full_pred_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_1_hit = _io_out_s1_full_pred_3_hit_T; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :118:44 + assign io_out_s1_full_pred_2_br_taken_mask_0 = _s1_hit_full_pred_WIRE_20; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_2_br_taken_mask_1 = _s1_hit_full_pred_WIRE_21; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_2_slot_valids_0 = _s1_hit_full_pred_WIRE_17; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_2_slot_valids_1 = _s1_hit_full_pred_WIRE_18; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_2_targets_0 = _s1_hit_full_pred_WIRE_14; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_2_targets_1 = _s1_hit_full_pred_WIRE_15; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_2_offsets_0 = _s1_hit_full_pred_WIRE_10; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_2_offsets_1 = _s1_hit_full_pred_WIRE_11; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_2_fallThroughAddr = _s1_hit_full_pred_WIRE_8; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_2_is_br_sharing = _s1_hit_full_pred_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_2_hit = _io_out_s1_full_pred_3_hit_T; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :118:44 + assign io_out_s1_full_pred_3_br_taken_mask_0 = _s1_hit_full_pred_WIRE_20; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_3_br_taken_mask_1 = _s1_hit_full_pred_WIRE_21; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_3_slot_valids_0 = _s1_hit_full_pred_WIRE_17; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_3_slot_valids_1 = _s1_hit_full_pred_WIRE_18; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_3_targets_0 = _s1_hit_full_pred_WIRE_14; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_3_targets_1 = _s1_hit_full_pred_WIRE_15; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_3_offsets_0 = _s1_hit_full_pred_WIRE_10; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_3_offsets_1 = _s1_hit_full_pred_WIRE_11; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_3_fallThroughAddr = _s1_hit_full_pred_WIRE_8; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_3_fallThroughErr = + _ways_0_io_resp_hit & s1_possible_full_preds_0_fallThroughErr | _ways_1_io_resp_hit + & s1_possible_full_preds_1_fallThroughErr | _ways_2_io_resp_hit + & s1_possible_full_preds_2_fallThroughErr | _ways_3_io_resp_hit + & s1_possible_full_preds_3_fallThroughErr | _ways_4_io_resp_hit + & s1_possible_full_preds_4_fallThroughErr | _ways_5_io_resp_hit + & s1_possible_full_preds_5_fallThroughErr | _ways_6_io_resp_hit + & s1_possible_full_preds_6_fallThroughErr | _ways_7_io_resp_hit + & s1_possible_full_preds_7_fallThroughErr | _ways_8_io_resp_hit + & s1_possible_full_preds_8_fallThroughErr | _ways_9_io_resp_hit + & s1_possible_full_preds_9_fallThroughErr | _ways_10_io_resp_hit + & s1_possible_full_preds_10_fallThroughErr | _ways_11_io_resp_hit + & s1_possible_full_preds_11_fallThroughErr | _ways_12_io_resp_hit + & s1_possible_full_preds_12_fallThroughErr | _ways_13_io_resp_hit + & s1_possible_full_preds_13_fallThroughErr | _ways_14_io_resp_hit + & s1_possible_full_preds_14_fallThroughErr | _ways_15_io_resp_hit + & s1_possible_full_preds_15_fallThroughErr | _ways_16_io_resp_hit + & s1_possible_full_preds_16_fallThroughErr | _ways_17_io_resp_hit + & s1_possible_full_preds_17_fallThroughErr | _ways_18_io_resp_hit + & s1_possible_full_preds_18_fallThroughErr | _ways_19_io_resp_hit + & s1_possible_full_preds_19_fallThroughErr | _ways_20_io_resp_hit + & s1_possible_full_preds_20_fallThroughErr | _ways_21_io_resp_hit + & s1_possible_full_preds_21_fallThroughErr | _ways_22_io_resp_hit + & s1_possible_full_preds_22_fallThroughErr | _ways_23_io_resp_hit + & s1_possible_full_preds_23_fallThroughErr | _ways_24_io_resp_hit + & s1_possible_full_preds_24_fallThroughErr | _ways_25_io_resp_hit + & s1_possible_full_preds_25_fallThroughErr | _ways_26_io_resp_hit + & s1_possible_full_preds_26_fallThroughErr | _ways_27_io_resp_hit + & s1_possible_full_preds_27_fallThroughErr | _ways_28_io_resp_hit + & s1_possible_full_preds_28_fallThroughErr | _ways_29_io_resp_hit + & s1_possible_full_preds_29_fallThroughErr | _ways_30_io_resp_hit + & s1_possible_full_preds_30_fallThroughErr | _ways_31_io_resp_hit + & s1_possible_full_preds_31_fallThroughErr; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :90:47, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34 + assign io_out_s1_full_pred_3_is_br_sharing = _s1_hit_full_pred_WIRE_1; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FauFTB.scala:78:7 + assign io_out_s1_full_pred_3_hit = _io_out_s1_full_pred_3_hit_T; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :118:44 + assign io_out_last_stage_meta = {213'h0, resp_meta_pred_way_r_1, resp_meta_hit_r_1}; // src/main/scala/xiangshan/frontend/FauFTB.scala:78:7, :121:26, :122:29, :123:34 +endmodule + diff --git a/src/uFTB/FauFTBWay.sv b/src/uFTB/FauFTBWay.sv new file mode 100644 index 0000000..2d84b56 --- /dev/null +++ b/src/uFTB/FauFTBWay.sv @@ -0,0 +1,187 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FauFTBWay( // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + input clock, + input reset, + input [15:0] io_req_tag, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output [3:0] io_resp_brSlots_0_offset, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output [11:0] io_resp_brSlots_0_lower, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output [1:0] io_resp_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output io_resp_brSlots_0_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output [3:0] io_resp_tailSlot_offset, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output [19:0] io_resp_tailSlot_lower, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output [1:0] io_resp_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output io_resp_tailSlot_sharing, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output io_resp_tailSlot_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output [3:0] io_resp_pftAddr, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output io_resp_carry, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output io_resp_always_taken_0, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output io_resp_always_taken_1, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output io_resp_hit, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input [15:0] io_update_req_tag, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + output io_update_hit, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input io_write_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input [3:0] io_write_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input [11:0] io_write_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input [1:0] io_write_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input io_write_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input [3:0] io_write_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input [19:0] io_write_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input [1:0] io_write_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input io_write_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input io_write_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input [3:0] io_write_entry_pftAddr, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input io_write_entry_carry, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input io_write_entry_always_taken_0, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input io_write_entry_always_taken_1, // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + input [15:0] io_write_tag // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 +); + + reg [3:0] data_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + reg [11:0] data_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + reg [1:0] data_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + reg data_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + reg [3:0] data_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + reg [19:0] data_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + reg [1:0] data_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + reg data_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + reg data_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + reg [3:0] data_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + reg data_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + reg data_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + reg data_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + reg [15:0] tag; // src/main/scala/xiangshan/frontend/FauFTB.scala:58:16 + reg valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:59:22 + always @(posedge clock) begin + if (io_write_valid) begin // src/main/scala/xiangshan/frontend/FauFTB.scala:45:14 + data_brSlots_0_offset <= io_write_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + data_brSlots_0_lower <= io_write_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + data_brSlots_0_tarStat <= io_write_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + data_brSlots_0_valid <= io_write_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + data_tailSlot_offset <= io_write_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + data_tailSlot_lower <= io_write_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + data_tailSlot_tarStat <= io_write_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + data_tailSlot_sharing <= io_write_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + data_tailSlot_valid <= io_write_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + data_pftAddr <= io_write_entry_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + data_carry <= io_write_entry_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + data_always_taken_0 <= io_write_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + data_always_taken_1 <= io_write_entry_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:57:17 + tag <= io_write_tag; // src/main/scala/xiangshan/frontend/FauFTB.scala:58:16 + end + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) + valid <= 1'h0; // src/main/scala/xiangshan/frontend/FauFTB.scala:59:22 + else + valid <= io_write_valid & ~valid | valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:59:22, :68:25, :69:{11,19}, :70:13 + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + initial begin // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + end // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + data_brSlots_0_offset = _RANDOM[2'h0][4:1]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + data_brSlots_0_lower = _RANDOM[2'h0][16:5]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + data_brSlots_0_tarStat = _RANDOM[2'h0][18:17]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + data_brSlots_0_valid = _RANDOM[2'h0][20]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + data_tailSlot_offset = _RANDOM[2'h0][24:21]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + data_tailSlot_lower = {_RANDOM[2'h0][31:25], _RANDOM[2'h1][12:0]}; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + data_tailSlot_tarStat = _RANDOM[2'h1][14:13]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + data_tailSlot_sharing = _RANDOM[2'h1][15]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + data_tailSlot_valid = _RANDOM[2'h1][16]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + data_pftAddr = _RANDOM[2'h1][20:17]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + data_carry = _RANDOM[2'h1][21]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + data_always_taken_0 = _RANDOM[2'h1][26]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + data_always_taken_1 = _RANDOM[2'h1][27]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + tag = {_RANDOM[2'h1][31:28], _RANDOM[2'h2][11:0]}; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17, :58:16 + valid = _RANDOM[2'h2][12]; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22 + `endif // RANDOMIZE_REG_INIT + if (reset) // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + valid = 1'h0; // src/main/scala/xiangshan/frontend/FauFTB.scala:59:22 + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_resp_brSlots_0_offset = data_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + assign io_resp_brSlots_0_lower = data_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + assign io_resp_brSlots_0_tarStat = data_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + assign io_resp_brSlots_0_valid = data_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + assign io_resp_tailSlot_offset = data_tailSlot_offset; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + assign io_resp_tailSlot_lower = data_tailSlot_lower; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + assign io_resp_tailSlot_tarStat = data_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + assign io_resp_tailSlot_sharing = data_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + assign io_resp_tailSlot_valid = data_tailSlot_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + assign io_resp_pftAddr = data_pftAddr; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + assign io_resp_carry = data_carry; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + assign io_resp_always_taken_0 = data_always_taken_0; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + assign io_resp_always_taken_1 = data_always_taken_1; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :57:17 + assign io_resp_hit = tag == io_req_tag & valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22, :62:{22,37} + assign io_update_hit = + tag == io_update_req_tag & valid | io_write_tag == io_update_req_tag & io_write_valid; // src/main/scala/xiangshan/frontend/FauFTB.scala:44:7, :58:16, :59:22, :64:{26,49,59}, :65:{35,58} +endmodule +