forked from OSchip/UnityChipVerification
103 lines
4.6 KiB
Systemverilog
103 lines
4.6 KiB
Systemverilog
// Generated by CIRCT firtool-1.61.0
|
|
// Standard header to adapt well known macros for register randomization.
|
|
`ifndef RANDOMIZE
|
|
`ifdef RANDOMIZE_MEM_INIT
|
|
`define RANDOMIZE
|
|
`endif // RANDOMIZE_MEM_INIT
|
|
`endif // not def RANDOMIZE
|
|
`ifndef RANDOMIZE
|
|
`ifdef RANDOMIZE_REG_INIT
|
|
`define RANDOMIZE
|
|
`endif // RANDOMIZE_REG_INIT
|
|
`endif // not def RANDOMIZE
|
|
|
|
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
|
|
`ifndef RANDOM
|
|
`define RANDOM $random
|
|
`endif // not def RANDOM
|
|
|
|
// Users can define INIT_RANDOM as general code that gets injected into the
|
|
// initializer block for modules with registers.
|
|
`ifndef INIT_RANDOM
|
|
`define INIT_RANDOM
|
|
`endif // not def INIT_RANDOM
|
|
|
|
// If using random initialization, you can also define RANDOMIZE_DELAY to
|
|
// customize the delay used, otherwise 0.002 is used.
|
|
`ifndef RANDOMIZE_DELAY
|
|
`define RANDOMIZE_DELAY 0.002
|
|
`endif // not def RANDOMIZE_DELAY
|
|
|
|
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
|
|
`ifndef INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE
|
|
`ifdef VERILATOR
|
|
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
|
|
`else // VERILATOR
|
|
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
|
|
`endif // VERILATOR
|
|
`else // RANDOMIZE
|
|
`define INIT_RANDOM_PROLOG_
|
|
`endif // RANDOMIZE
|
|
`endif // not def INIT_RANDOM_PROLOG_
|
|
|
|
// Include register initializers in init blocks unless synthesis is set
|
|
`ifndef SYNTHESIS
|
|
`ifndef ENABLE_INITIAL_REG_
|
|
`define ENABLE_INITIAL_REG_
|
|
`endif // not def ENABLE_INITIAL_REG_
|
|
`endif // not def SYNTHESIS
|
|
|
|
// Include rmemory initializers in init blocks unless synthesis is set
|
|
`ifndef SYNTHESIS
|
|
`ifndef ENABLE_INITIAL_MEM_
|
|
`define ENABLE_INITIAL_MEM_
|
|
`endif // not def ENABLE_INITIAL_MEM_
|
|
`endif // not def SYNTHESIS
|
|
|
|
module DelayN_2( // utility/src/main/scala/utility/Hold.scala:83:7
|
|
input clock,
|
|
input [35:0] io_in, // utility/src/main/scala/utility/Hold.scala:84:14
|
|
output [35:0] io_out // utility/src/main/scala/utility/Hold.scala:84:14
|
|
);
|
|
|
|
reg [35:0] REG; // utility/src/main/scala/utility/Hold.scala:90:18
|
|
reg [35:0] REG_1; // utility/src/main/scala/utility/Hold.scala:90:18
|
|
reg [35:0] REG_2; // utility/src/main/scala/utility/Hold.scala:90:18
|
|
reg [35:0] REG_3; // utility/src/main/scala/utility/Hold.scala:90:18
|
|
reg [35:0] REG_4; // utility/src/main/scala/utility/Hold.scala:90:18
|
|
always @(posedge clock) begin
|
|
REG <= io_in; // utility/src/main/scala/utility/Hold.scala:90:18
|
|
REG_1 <= REG; // utility/src/main/scala/utility/Hold.scala:90:18
|
|
REG_2 <= REG_1; // utility/src/main/scala/utility/Hold.scala:90:18
|
|
REG_3 <= REG_2; // utility/src/main/scala/utility/Hold.scala:90:18
|
|
REG_4 <= REG_3; // utility/src/main/scala/utility/Hold.scala:90:18
|
|
end // always @(posedge)
|
|
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/Hold.scala:83:7
|
|
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
|
|
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
|
|
`endif // FIRRTL_BEFORE_INITIAL
|
|
logic [31:0] _RANDOM[0:5]; // utility/src/main/scala/utility/Hold.scala:83:7
|
|
initial begin // utility/src/main/scala/utility/Hold.scala:83:7
|
|
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7
|
|
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/Hold.scala:83:7
|
|
`endif // INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/Hold.scala:83:7
|
|
for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin
|
|
_RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/Hold.scala:83:7
|
|
end // utility/src/main/scala/utility/Hold.scala:83:7
|
|
REG = {_RANDOM[3'h0], _RANDOM[3'h1][3:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
|
|
REG_1 = {_RANDOM[3'h1][31:4], _RANDOM[3'h2][7:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
|
|
REG_2 = {_RANDOM[3'h2][31:8], _RANDOM[3'h3][11:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
|
|
REG_3 = {_RANDOM[3'h3][31:12], _RANDOM[3'h4][15:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
|
|
REG_4 = {_RANDOM[3'h4][31:16], _RANDOM[3'h5][19:0]}; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
|
|
`endif // RANDOMIZE_REG_INIT
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
|
|
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/Hold.scala:83:7
|
|
`endif // FIRRTL_AFTER_INITIAL
|
|
`endif // ENABLE_INITIAL_REG_
|
|
assign io_out = REG_4; // utility/src/main/scala/utility/Hold.scala:83:7, :90:18
|
|
endmodule
|
|
|