forked from OSchip/UnityChipVerification
1618 lines
163 KiB
Systemverilog
1618 lines
163 KiB
Systemverilog
// Generated by CIRCT firtool-1.61.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module FTB( // src/main/scala/xiangshan/frontend/FTB.scala:284:7
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input clock,
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input reset,
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input [35:0] io_reset_vector, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_s0_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_s0_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_s0_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [3:0] io_out_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [3:0] io_out_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [3:0] io_out_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [3:0] io_out_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [3:0] io_out_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [3:0] io_out_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_2_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [3:0] io_out_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [3:0] io_out_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [3:0] io_out_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [3:0] io_out_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [38:0] io_out_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output io_out_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_ctrl_btb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s0_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s0_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s0_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s1_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s1_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s1_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s1_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s2_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s2_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s2_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_s1_ready, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [38:0] io_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [3:0] io_update_bits_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [11:0] io_update_bits_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [19:0] io_update_bits_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [3:0] io_update_bits_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_old_entry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [218:0] io_update_bits_meta // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
);
|
|
|
|
wire _write_valid_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _delay2_entry_delay_io_out_valid; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire [3:0] _delay2_entry_delay_io_out_brSlots_0_offset; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire [11:0] _delay2_entry_delay_io_out_brSlots_0_lower; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire [1:0] _delay2_entry_delay_io_out_brSlots_0_tarStat; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _delay2_entry_delay_io_out_brSlots_0_sharing; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _delay2_entry_delay_io_out_brSlots_0_valid; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire [3:0] _delay2_entry_delay_io_out_tailSlot_offset; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire [19:0] _delay2_entry_delay_io_out_tailSlot_lower; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire [1:0] _delay2_entry_delay_io_out_tailSlot_tarStat; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _delay2_entry_delay_io_out_tailSlot_sharing; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _delay2_entry_delay_io_out_tailSlot_valid; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire [3:0] _delay2_entry_delay_io_out_pftAddr; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _delay2_entry_delay_io_out_carry; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _delay2_entry_delay_io_out_isCall; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _delay2_entry_delay_io_out_isRet; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _delay2_entry_delay_io_out_isJalr; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _delay2_entry_delay_io_out_last_may_be_rvi_call; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _delay2_entry_delay_io_out_always_taken_0; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _delay2_entry_delay_io_out_always_taken_1; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire [38:0] _delay2_pc_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _ftbBank_io_req_pc_ready; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_read_resp_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire [3:0] _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire [11:0] _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire [1:0] _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_read_resp_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire [3:0] _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire [19:0] _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire [1:0] _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire [3:0] _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_read_resp_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_read_resp_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_read_resp_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_read_resp_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_read_hits_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire [1:0] _ftbBank_io_read_hits_bits; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire _ftbBank_io_update_hits_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire [1:0] _ftbBank_io_update_hits_bits; // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
wire [35:0] _reset_vector_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
reg [38:0] s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
reg [38:0] s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
reg [38:0] s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
reg [38:0] s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
reg [38:0] s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86
|
|
reg [38:0] s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86
|
|
reg [38:0] s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86
|
|
reg [38:0] s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86
|
|
reg [38:0] s3_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:188:86
|
|
reg [38:0] s3_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:188:86
|
|
reg [38:0] s3_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:188:86
|
|
reg [38:0] s3_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:188:86
|
|
reg REG; // src/main/scala/xiangshan/frontend/BPU.scala:190:24
|
|
reg REG_1; // src/main/scala/xiangshan/frontend/BPU.scala:190:16
|
|
reg s2_ftb_entry_dup_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [3:0] s2_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [11:0] s2_ftb_entry_dup_0_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [1:0] s2_ftb_entry_dup_0_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_0_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [3:0] s2_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [19:0] s2_ftb_entry_dup_0_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [1:0] s2_ftb_entry_dup_0_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [3:0] s2_ftb_entry_dup_0_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_0_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_0_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_0_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_0_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_0_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [3:0] s2_ftb_entry_dup_1_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [11:0] s2_ftb_entry_dup_1_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [1:0] s2_ftb_entry_dup_1_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [3:0] s2_ftb_entry_dup_1_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [19:0] s2_ftb_entry_dup_1_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [1:0] s2_ftb_entry_dup_1_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [3:0] s2_ftb_entry_dup_1_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_1_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [3:0] s2_ftb_entry_dup_2_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [11:0] s2_ftb_entry_dup_2_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [1:0] s2_ftb_entry_dup_2_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [3:0] s2_ftb_entry_dup_2_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [19:0] s2_ftb_entry_dup_2_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [1:0] s2_ftb_entry_dup_2_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [3:0] s2_ftb_entry_dup_2_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_2_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_2_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [3:0] s2_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [11:0] s2_ftb_entry_dup_3_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [1:0] s2_ftb_entry_dup_3_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [3:0] s2_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [19:0] s2_ftb_entry_dup_3_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [1:0] s2_ftb_entry_dup_3_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg s2_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
|
|
reg [3:0] s2_ftb_entry_dup_3_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
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reg s2_ftb_entry_dup_3_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
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reg s2_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
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reg s2_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55
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reg s3_ftb_entry_dup_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg [3:0] s3_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg [11:0] s3_ftb_entry_dup_0_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg [1:0] s3_ftb_entry_dup_0_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg s3_ftb_entry_dup_0_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg s3_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg [3:0] s3_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg [19:0] s3_ftb_entry_dup_0_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg [1:0] s3_ftb_entry_dup_0_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg s3_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg s3_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg [3:0] s3_ftb_entry_dup_0_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
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reg s3_ftb_entry_dup_0_carry; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg s3_ftb_entry_dup_0_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg s3_ftb_entry_dup_0_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg s3_ftb_entry_dup_0_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg s3_ftb_entry_dup_0_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg s3_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg s3_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
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reg [11:0] s3_ftb_entry_dup_1_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
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reg [1:0] s3_ftb_entry_dup_1_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
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reg s3_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
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reg [19:0] s3_ftb_entry_dup_1_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
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reg [1:0] s3_ftb_entry_dup_1_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
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reg s3_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
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reg s3_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
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reg [3:0] s3_ftb_entry_dup_1_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
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reg s3_ftb_entry_dup_1_carry; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
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reg s3_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg [11:0] s3_ftb_entry_dup_2_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg [1:0] s3_ftb_entry_dup_2_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg [19:0] s3_ftb_entry_dup_2_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg [1:0] s3_ftb_entry_dup_2_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg [3:0] s3_ftb_entry_dup_2_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_2_carry; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg [3:0] s3_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg [11:0] s3_ftb_entry_dup_3_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg [1:0] s3_ftb_entry_dup_3_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg [3:0] s3_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg [19:0] s3_ftb_entry_dup_3_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg [1:0] s3_ftb_entry_dup_3_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg [3:0] s3_ftb_entry_dup_3_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_3_carry; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
reg s3_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:429:88
|
|
wire io_out_last_stage_meta_e_hit =
|
|
_ftbBank_io_read_hits_valid & io_ctrl_btb_enable; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :431:43
|
|
reg s2_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:432:49
|
|
reg s2_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:432:49
|
|
reg s2_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:432:49
|
|
reg s2_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:432:49
|
|
reg s3_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:433:76
|
|
reg s3_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:433:76
|
|
reg s3_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:433:76
|
|
reg s3_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:433:76
|
|
reg [25:0] higher_r; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
reg [25:0] higher_r_1; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_1; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_1; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire _target_T_18 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55
|
|
wire _target_T_19 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55
|
|
wire _target_T_20 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55
|
|
reg [17:0] higher_r_2; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [17:0] higher_plus_one_r_2; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [17:0] higher_minus_one_r_2; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire [38:0] _io_out_s2_full_pred_0_targets_1_output =
|
|
{s2_ftb_entry_dup_0_tailSlot_sharing
|
|
? {(_target_T_18 ? higher_plus_one_r_1 : 26'h0)
|
|
| (_target_T_19 ? higher_minus_one_r_1 : 26'h0)
|
|
| (_target_T_20 ? higher_r_1 : 26'h0),
|
|
s2_ftb_entry_dup_0_tailSlot_lower[11:0]}
|
|
: {(_target_T_18 ? higher_plus_one_r_2 : 18'h0)
|
|
| (_target_T_19 ? higher_minus_one_r_2 : 18'h0)
|
|
| (_target_T_20 ? higher_r_2 : 18'h0),
|
|
s2_ftb_entry_dup_0_tailSlot_lower},
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55
|
|
reg io_out_s2_full_pred_0_fallThroughAddr_stashed_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36
|
|
reg [25:0] higher_r_3; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_3; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_3; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
reg [25:0] higher_r_4; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_4; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_4; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire _target_T_45 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55
|
|
wire _target_T_46 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55
|
|
wire _target_T_47 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55
|
|
reg [17:0] higher_r_5; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [17:0] higher_plus_one_r_5; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [17:0] higher_minus_one_r_5; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire [38:0] _io_out_s2_full_pred_1_targets_1_output =
|
|
{s2_ftb_entry_dup_1_tailSlot_sharing
|
|
? {(_target_T_45 ? higher_plus_one_r_4 : 26'h0)
|
|
| (_target_T_46 ? higher_minus_one_r_4 : 26'h0)
|
|
| (_target_T_47 ? higher_r_4 : 26'h0),
|
|
s2_ftb_entry_dup_1_tailSlot_lower[11:0]}
|
|
: {(_target_T_45 ? higher_plus_one_r_5 : 18'h0)
|
|
| (_target_T_46 ? higher_minus_one_r_5 : 18'h0)
|
|
| (_target_T_47 ? higher_r_5 : 18'h0),
|
|
s2_ftb_entry_dup_1_tailSlot_lower},
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55
|
|
reg io_out_s2_full_pred_1_fallThroughAddr_stashed_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36
|
|
reg [25:0] higher_r_6; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_6; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_6; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
reg [25:0] higher_r_7; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_7; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_7; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire _target_T_72 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55
|
|
wire _target_T_73 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55
|
|
wire _target_T_74 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55
|
|
reg [17:0] higher_r_8; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [17:0] higher_plus_one_r_8; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [17:0] higher_minus_one_r_8; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire [38:0] _io_out_s2_full_pred_2_targets_1_output =
|
|
{s2_ftb_entry_dup_2_tailSlot_sharing
|
|
? {(_target_T_72 ? higher_plus_one_r_7 : 26'h0)
|
|
| (_target_T_73 ? higher_minus_one_r_7 : 26'h0)
|
|
| (_target_T_74 ? higher_r_7 : 26'h0),
|
|
s2_ftb_entry_dup_2_tailSlot_lower[11:0]}
|
|
: {(_target_T_72 ? higher_plus_one_r_8 : 18'h0)
|
|
| (_target_T_73 ? higher_minus_one_r_8 : 18'h0)
|
|
| (_target_T_74 ? higher_r_8 : 18'h0),
|
|
s2_ftb_entry_dup_2_tailSlot_lower},
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55
|
|
reg io_out_s2_full_pred_2_fallThroughAddr_stashed_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36
|
|
reg [25:0] higher_r_9; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_9; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_9; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
reg [25:0] higher_r_10; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_10; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_10; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire _target_T_99 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :428:55
|
|
wire _target_T_100 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :428:55
|
|
wire _target_T_101 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :428:55
|
|
reg [17:0] higher_r_11; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [17:0] higher_plus_one_r_11; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [17:0] higher_minus_one_r_11; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire [38:0] _io_out_s2_full_pred_3_targets_1_output =
|
|
{s2_ftb_entry_dup_3_tailSlot_sharing
|
|
? {(_target_T_99 ? higher_plus_one_r_10 : 26'h0)
|
|
| (_target_T_100 ? higher_minus_one_r_10 : 26'h0)
|
|
| (_target_T_101 ? higher_r_10 : 26'h0),
|
|
s2_ftb_entry_dup_3_tailSlot_lower[11:0]}
|
|
: {(_target_T_99 ? higher_plus_one_r_11 : 18'h0)
|
|
| (_target_T_100 ? higher_minus_one_r_11 : 18'h0)
|
|
| (_target_T_101 ? higher_r_11 : 18'h0),
|
|
s2_ftb_entry_dup_3_tailSlot_lower},
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :428:55
|
|
wire _io_out_s2_full_pred_3_fallThroughErr_output =
|
|
{1'h0, s2_pc_dup_3[4:1]} >= {s2_ftb_entry_dup_3_carry, s2_ftb_entry_dup_3_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34
|
|
reg io_out_s2_full_pred_3_fallThroughAddr_stashed_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36
|
|
reg [25:0] higher_r_12; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_12; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_12; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
reg [25:0] higher_r_13; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_13; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_13; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire _target_T_126 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88
|
|
wire _target_T_127 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88
|
|
wire _target_T_128 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88
|
|
reg [17:0] higher_r_14; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [17:0] higher_plus_one_r_14; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [17:0] higher_minus_one_r_14; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire [38:0] _io_out_s3_full_pred_0_targets_1_output =
|
|
{s3_ftb_entry_dup_0_tailSlot_sharing
|
|
? {(_target_T_126 ? higher_plus_one_r_13 : 26'h0)
|
|
| (_target_T_127 ? higher_minus_one_r_13 : 26'h0)
|
|
| (_target_T_128 ? higher_r_13 : 26'h0),
|
|
s3_ftb_entry_dup_0_tailSlot_lower[11:0]}
|
|
: {(_target_T_126 ? higher_plus_one_r_14 : 18'h0)
|
|
| (_target_T_127 ? higher_minus_one_r_14 : 18'h0)
|
|
| (_target_T_128 ? higher_r_14 : 18'h0),
|
|
s3_ftb_entry_dup_0_tailSlot_lower},
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88
|
|
wire _io_out_s3_full_pred_0_fallThroughErr_output =
|
|
{1'h0, s3_pc_dup_0[4:1]} >= {s3_ftb_entry_dup_0_carry, s3_ftb_entry_dup_0_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34
|
|
reg [25:0] higher_r_15; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_15; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_15; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
reg [25:0] higher_r_16; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_16; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_16; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire _target_T_153 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88
|
|
wire _target_T_154 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88
|
|
wire _target_T_155 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88
|
|
reg [17:0] higher_r_17; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [17:0] higher_plus_one_r_17; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [17:0] higher_minus_one_r_17; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire [38:0] _io_out_s3_full_pred_1_targets_1_output =
|
|
{s3_ftb_entry_dup_1_tailSlot_sharing
|
|
? {(_target_T_153 ? higher_plus_one_r_16 : 26'h0)
|
|
| (_target_T_154 ? higher_minus_one_r_16 : 26'h0)
|
|
| (_target_T_155 ? higher_r_16 : 26'h0),
|
|
s3_ftb_entry_dup_1_tailSlot_lower[11:0]}
|
|
: {(_target_T_153 ? higher_plus_one_r_17 : 18'h0)
|
|
| (_target_T_154 ? higher_minus_one_r_17 : 18'h0)
|
|
| (_target_T_155 ? higher_r_17 : 18'h0),
|
|
s3_ftb_entry_dup_1_tailSlot_lower},
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88
|
|
wire _io_out_s3_full_pred_1_fallThroughErr_output =
|
|
{1'h0, s3_pc_dup_1[4:1]} >= {s3_ftb_entry_dup_1_carry, s3_ftb_entry_dup_1_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34
|
|
reg [25:0] higher_r_18; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_18; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_18; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
reg [25:0] higher_r_19; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_19; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_19; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire _target_T_180 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88
|
|
wire _target_T_181 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88
|
|
wire _target_T_182 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88
|
|
reg [17:0] higher_r_20; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [17:0] higher_plus_one_r_20; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [17:0] higher_minus_one_r_20; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire [38:0] _io_out_s3_full_pred_2_targets_1_output =
|
|
{s3_ftb_entry_dup_2_tailSlot_sharing
|
|
? {(_target_T_180 ? higher_plus_one_r_19 : 26'h0)
|
|
| (_target_T_181 ? higher_minus_one_r_19 : 26'h0)
|
|
| (_target_T_182 ? higher_r_19 : 26'h0),
|
|
s3_ftb_entry_dup_2_tailSlot_lower[11:0]}
|
|
: {(_target_T_180 ? higher_plus_one_r_20 : 18'h0)
|
|
| (_target_T_181 ? higher_minus_one_r_20 : 18'h0)
|
|
| (_target_T_182 ? higher_r_20 : 18'h0),
|
|
s3_ftb_entry_dup_2_tailSlot_lower},
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88
|
|
wire _io_out_s3_full_pred_2_fallThroughErr_output =
|
|
{1'h0, s3_pc_dup_2[4:1]} >= {s3_ftb_entry_dup_2_carry, s3_ftb_entry_dup_2_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34
|
|
reg [25:0] higher_r_21; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_21; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_21; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
reg [25:0] higher_r_22; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [25:0] higher_plus_one_r_22; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [25:0] higher_minus_one_r_22; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire _target_T_207 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:98:19, :429:88
|
|
wire _target_T_208 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:99:19, :429:88
|
|
wire _target_T_209 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, :429:88
|
|
reg [17:0] higher_r_23; // src/main/scala/xiangshan/frontend/FTB.scala:87:28
|
|
reg [17:0] higher_plus_one_r_23; // src/main/scala/xiangshan/frontend/FTB.scala:88:37
|
|
reg [17:0] higher_minus_one_r_23; // src/main/scala/xiangshan/frontend/FTB.scala:89:38
|
|
wire [38:0] _io_out_s3_full_pred_3_targets_1_output =
|
|
{s3_ftb_entry_dup_3_tailSlot_sharing
|
|
? {(_target_T_207 ? higher_plus_one_r_22 : 26'h0)
|
|
| (_target_T_208 ? higher_minus_one_r_22 : 26'h0)
|
|
| (_target_T_209 ? higher_r_22 : 26'h0),
|
|
s3_ftb_entry_dup_3_tailSlot_lower[11:0]}
|
|
: {(_target_T_207 ? higher_plus_one_r_23 : 18'h0)
|
|
| (_target_T_208 ? higher_minus_one_r_23 : 18'h0)
|
|
| (_target_T_209 ? higher_r_23 : 18'h0),
|
|
s3_ftb_entry_dup_3_tailSlot_lower},
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, :429:88
|
|
wire _io_out_s3_full_pred_3_fallThroughErr_output =
|
|
{1'h0, s3_pc_dup_3[4:1]} >= {s3_ftb_entry_dup_3_carry, s3_ftb_entry_dup_3_pftAddr}; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34
|
|
reg [2:0] io_out_last_stage_meta_r; // src/main/scala/xiangshan/frontend/FTB.scala:458:48
|
|
reg [2:0] io_out_last_stage_meta_r_1; // src/main/scala/xiangshan/frontend/FTB.scala:458:38
|
|
wire u_valid = io_update_valid & ~io_update_bits_old_entry; // src/main/scala/xiangshan/frontend/FTB.scala:474:{33,36}
|
|
wire update_now = u_valid & io_update_bits_meta[0]; // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :480:28
|
|
wire update_need_read = u_valid & ~(io_update_bits_meta[0]); // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :481:{34,37}
|
|
reg io_s1_ready_REG; // src/main/scala/xiangshan/frontend/FTB.scala:483:76
|
|
wire [38:0] _ftb_write_tag_WIRE_2 =
|
|
update_now ? io_update_bits_pc : _delay2_pc_delay_io_out; // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :492:40, utility/src/main/scala/utility/Hold.scala:97:23
|
|
reg [1:0] ftbBank_io_update_write_way_REG; // src/main/scala/xiangshan/frontend/FTB.scala:499:76
|
|
reg ftbBank_io_update_write_alloc_REG; // src/main/scala/xiangshan/frontend/FTB.scala:500:76
|
|
wire [38:0] _GEN = {3'h0, _reset_vector_delay_io_out}; // src/main/scala/xiangshan/frontend/BPU.scala:191:39, utility/src/main/scala/utility/Hold.scala:97:23
|
|
always @(posedge clock) begin
|
|
if (REG_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16
|
|
s1_pc_dup_0 <= _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39
|
|
s1_pc_dup_1 <= _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39
|
|
s1_pc_dup_2 <= _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39
|
|
s1_pc_dup_3 <= _GEN; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39
|
|
end
|
|
else begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16
|
|
if (io_s0_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s1_pc_dup_0 <= io_in_bits_s0_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
if (io_s0_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s1_pc_dup_1 <= io_in_bits_s0_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
if (io_s0_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s1_pc_dup_2 <= io_in_bits_s0_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
if (io_s0_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s1_pc_dup_3 <= io_in_bits_s0_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
end
|
|
if (io_s1_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s2_pc_dup_0 <= s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86
|
|
s2_ftb_entry_dup_0_valid <= _ftbBank_io_read_resp_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_brSlots_0_sharing <= _ftbBank_io_read_resp_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_pftAddr <= _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_isCall <= _ftbBank_io_read_resp_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_isRet <= _ftbBank_io_read_resp_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_isJalr <= _ftbBank_io_read_resp_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_last_may_be_rvi_call <=
|
|
_ftbBank_io_read_resp_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_0_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
higher_r <= s1_pc_dup_0[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28
|
|
higher_plus_one_r <= 26'(s1_pc_dup_0[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}
|
|
higher_minus_one_r <= 26'(s1_pc_dup_0[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}
|
|
higher_r_1 <= s1_pc_dup_0[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28
|
|
higher_plus_one_r_1 <= 26'(s1_pc_dup_0[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}
|
|
higher_minus_one_r_1 <= 26'(s1_pc_dup_0[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}
|
|
higher_r_2 <= s1_pc_dup_0[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28
|
|
higher_plus_one_r_2 <= 18'(s1_pc_dup_0[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}
|
|
higher_minus_one_r_2 <= 18'(s1_pc_dup_0[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}
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|
io_out_s2_full_pred_0_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23
|
|
io_out_last_stage_meta_r <=
|
|
{_ftbBank_io_read_hits_bits, io_out_last_stage_meta_e_hit}; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :431:43, :458:{48,92}
|
|
end
|
|
if (io_s1_fire_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s2_pc_dup_1 <= s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86
|
|
s2_ftb_entry_dup_1_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_1_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_1_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
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|
s2_ftb_entry_dup_1_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
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|
s2_ftb_entry_dup_1_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_1_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_1_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_1_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_1_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_1_pftAddr <= _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_1_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_1_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_1_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
higher_r_3 <= s1_pc_dup_1[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28
|
|
higher_plus_one_r_3 <= 26'(s1_pc_dup_1[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}
|
|
higher_minus_one_r_3 <= 26'(s1_pc_dup_1[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}
|
|
higher_r_4 <= s1_pc_dup_1[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28
|
|
higher_plus_one_r_4 <= 26'(s1_pc_dup_1[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}
|
|
higher_minus_one_r_4 <= 26'(s1_pc_dup_1[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}
|
|
higher_r_5 <= s1_pc_dup_1[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28
|
|
higher_plus_one_r_5 <= 18'(s1_pc_dup_1[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}
|
|
higher_minus_one_r_5 <= 18'(s1_pc_dup_1[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}
|
|
io_out_s2_full_pred_1_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23
|
|
end
|
|
if (io_s1_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s2_pc_dup_2 <= s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86
|
|
s2_ftb_entry_dup_2_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_pftAddr <= _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_isCall <= _ftbBank_io_read_resp_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_isRet <= _ftbBank_io_read_resp_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_isJalr <= _ftbBank_io_read_resp_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_last_may_be_rvi_call <=
|
|
_ftbBank_io_read_resp_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_2_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
higher_r_6 <= s1_pc_dup_2[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28
|
|
higher_plus_one_r_6 <= 26'(s1_pc_dup_2[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}
|
|
higher_minus_one_r_6 <= 26'(s1_pc_dup_2[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}
|
|
higher_r_7 <= s1_pc_dup_2[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28
|
|
higher_plus_one_r_7 <= 26'(s1_pc_dup_2[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}
|
|
higher_minus_one_r_7 <= 26'(s1_pc_dup_2[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}
|
|
higher_r_8 <= s1_pc_dup_2[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28
|
|
higher_plus_one_r_8 <= 18'(s1_pc_dup_2[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}
|
|
higher_minus_one_r_8 <= 18'(s1_pc_dup_2[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}
|
|
io_out_s2_full_pred_2_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23
|
|
end
|
|
if (io_s1_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s2_pc_dup_3 <= s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86
|
|
s2_ftb_entry_dup_3_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_3_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_3_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_3_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_3_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_3_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_3_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_3_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_3_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_3_pftAddr <= _ftbBank_io_read_resp_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_3_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_3_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
s2_ftb_entry_dup_3_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :428:55
|
|
higher_r_9 <= s1_pc_dup_3[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28
|
|
higher_plus_one_r_9 <= 26'(s1_pc_dup_3[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}
|
|
higher_minus_one_r_9 <= 26'(s1_pc_dup_3[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}
|
|
higher_r_10 <= s1_pc_dup_3[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28
|
|
higher_plus_one_r_10 <= 26'(s1_pc_dup_3[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}
|
|
higher_minus_one_r_10 <= 26'(s1_pc_dup_3[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}
|
|
higher_r_11 <= s1_pc_dup_3[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :87:28
|
|
higher_plus_one_r_11 <= 18'(s1_pc_dup_3[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :88:{37,53}
|
|
higher_minus_one_r_11 <= 18'(s1_pc_dup_3[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:85:44, :89:{38,54}
|
|
io_out_s2_full_pred_3_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; // src/main/scala/xiangshan/frontend/FTB.scala:177:36, :422:23
|
|
end
|
|
if (io_s2_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_pc_dup_0 <= s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86
|
|
s3_ftb_entry_dup_0_valid <= s2_ftb_entry_dup_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_brSlots_0_offset <= s2_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_brSlots_0_lower <= s2_ftb_entry_dup_0_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_brSlots_0_tarStat <= s2_ftb_entry_dup_0_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_brSlots_0_sharing <= s2_ftb_entry_dup_0_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_brSlots_0_valid <= s2_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_tailSlot_offset <= s2_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_tailSlot_lower <= s2_ftb_entry_dup_0_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_tailSlot_tarStat <= s2_ftb_entry_dup_0_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_tailSlot_sharing <= s2_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_tailSlot_valid <= s2_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_pftAddr <= s2_ftb_entry_dup_0_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_carry <= s2_ftb_entry_dup_0_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_isCall <= s2_ftb_entry_dup_0_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_isRet <= s2_ftb_entry_dup_0_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_isJalr <= s2_ftb_entry_dup_0_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_last_may_be_rvi_call <= s2_ftb_entry_dup_0_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_always_taken_0 <= s2_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_0_always_taken_1 <= s2_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
higher_r_12 <= s2_pc_dup_0[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28
|
|
higher_plus_one_r_12 <= 26'(s2_pc_dup_0[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}
|
|
higher_minus_one_r_12 <= 26'(s2_pc_dup_0[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}
|
|
higher_r_13 <= s2_pc_dup_0[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28
|
|
higher_plus_one_r_13 <= 26'(s2_pc_dup_0[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}
|
|
higher_minus_one_r_13 <= 26'(s2_pc_dup_0[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}
|
|
higher_r_14 <= s2_pc_dup_0[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28
|
|
higher_plus_one_r_14 <= 18'(s2_pc_dup_0[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}
|
|
higher_minus_one_r_14 <= 18'(s2_pc_dup_0[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}
|
|
io_out_last_stage_meta_r_1 <= io_out_last_stage_meta_r; // src/main/scala/xiangshan/frontend/FTB.scala:458:{38,48}
|
|
end
|
|
if (io_s2_fire_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_pc_dup_1 <= s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86
|
|
s3_ftb_entry_dup_1_brSlots_0_lower <= s2_ftb_entry_dup_1_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_1_brSlots_0_tarStat <= s2_ftb_entry_dup_1_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_1_brSlots_0_valid <= s2_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_1_tailSlot_lower <= s2_ftb_entry_dup_1_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_1_tailSlot_tarStat <= s2_ftb_entry_dup_1_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_1_tailSlot_sharing <= s2_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_1_tailSlot_valid <= s2_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_1_pftAddr <= s2_ftb_entry_dup_1_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_1_carry <= s2_ftb_entry_dup_1_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_1_always_taken_0 <= s2_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_1_always_taken_1 <= s2_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
higher_r_15 <= s2_pc_dup_1[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28
|
|
higher_plus_one_r_15 <= 26'(s2_pc_dup_1[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}
|
|
higher_minus_one_r_15 <= 26'(s2_pc_dup_1[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}
|
|
higher_r_16 <= s2_pc_dup_1[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28
|
|
higher_plus_one_r_16 <= 26'(s2_pc_dup_1[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}
|
|
higher_minus_one_r_16 <= 26'(s2_pc_dup_1[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}
|
|
higher_r_17 <= s2_pc_dup_1[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28
|
|
higher_plus_one_r_17 <= 18'(s2_pc_dup_1[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}
|
|
higher_minus_one_r_17 <= 18'(s2_pc_dup_1[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}
|
|
end
|
|
if (io_s2_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_pc_dup_2 <= s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86
|
|
s3_ftb_entry_dup_2_brSlots_0_lower <= s2_ftb_entry_dup_2_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_2_brSlots_0_tarStat <= s2_ftb_entry_dup_2_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_2_brSlots_0_valid <= s2_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_2_tailSlot_lower <= s2_ftb_entry_dup_2_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_2_tailSlot_tarStat <= s2_ftb_entry_dup_2_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_2_tailSlot_sharing <= s2_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_2_tailSlot_valid <= s2_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_2_pftAddr <= s2_ftb_entry_dup_2_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_2_carry <= s2_ftb_entry_dup_2_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_2_isCall <= s2_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_2_isRet <= s2_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_2_isJalr <= s2_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_2_always_taken_0 <= s2_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_2_always_taken_1 <= s2_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
higher_r_18 <= s2_pc_dup_2[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28
|
|
higher_plus_one_r_18 <= 26'(s2_pc_dup_2[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}
|
|
higher_minus_one_r_18 <= 26'(s2_pc_dup_2[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}
|
|
higher_r_19 <= s2_pc_dup_2[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28
|
|
higher_plus_one_r_19 <= 26'(s2_pc_dup_2[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}
|
|
higher_minus_one_r_19 <= 26'(s2_pc_dup_2[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}
|
|
higher_r_20 <= s2_pc_dup_2[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28
|
|
higher_plus_one_r_20 <= 18'(s2_pc_dup_2[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}
|
|
higher_minus_one_r_20 <= 18'(s2_pc_dup_2[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}
|
|
end
|
|
if (io_s2_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_pc_dup_3 <= s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86
|
|
s3_ftb_entry_dup_3_brSlots_0_offset <= s2_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_3_brSlots_0_lower <= s2_ftb_entry_dup_3_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_3_brSlots_0_tarStat <= s2_ftb_entry_dup_3_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_3_brSlots_0_valid <= s2_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_3_tailSlot_offset <= s2_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_3_tailSlot_lower <= s2_ftb_entry_dup_3_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_3_tailSlot_tarStat <= s2_ftb_entry_dup_3_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_3_tailSlot_sharing <= s2_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_3_tailSlot_valid <= s2_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_3_pftAddr <= s2_ftb_entry_dup_3_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_3_carry <= s2_ftb_entry_dup_3_carry; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_3_always_taken_0 <= s2_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
s3_ftb_entry_dup_3_always_taken_1 <= s2_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:428:55, :429:88
|
|
higher_r_21 <= s2_pc_dup_3[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28
|
|
higher_plus_one_r_21 <= 26'(s2_pc_dup_3[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}
|
|
higher_minus_one_r_21 <= 26'(s2_pc_dup_3[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}
|
|
higher_r_22 <= s2_pc_dup_3[38:13]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28
|
|
higher_plus_one_r_22 <= 26'(s2_pc_dup_3[38:13] + 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}
|
|
higher_minus_one_r_22 <= 26'(s2_pc_dup_3[38:13] - 26'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}
|
|
higher_r_23 <= s2_pc_dup_3[38:21]; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :87:28
|
|
higher_plus_one_r_23 <= 18'(s2_pc_dup_3[38:21] + 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :88:{37,53}
|
|
higher_minus_one_r_23 <= 18'(s2_pc_dup_3[38:21] - 18'h1); // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :89:{38,54}
|
|
end
|
|
REG <= reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:24
|
|
REG_1 <= REG & ~reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24,39,42}
|
|
io_s1_ready_REG <= update_need_read; // src/main/scala/xiangshan/frontend/FTB.scala:481:34, :483:76
|
|
ftbBank_io_update_write_way_REG <= _ftbBank_io_update_hits_bits; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :499:76
|
|
ftbBank_io_update_write_alloc_REG <= ~_ftbBank_io_update_hits_valid; // src/main/scala/xiangshan/frontend/FTB.scala:422:23, :500:{76,77}
|
|
end // always @(posedge)
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
s2_hit_dup_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49
|
|
s2_hit_dup_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49
|
|
s2_hit_dup_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49
|
|
s2_hit_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49
|
|
s3_hit_dup_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76
|
|
s3_hit_dup_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76
|
|
s3_hit_dup_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76
|
|
s3_hit_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76
|
|
end
|
|
else begin
|
|
if (io_s1_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s2_hit_dup_0 <= io_out_last_stage_meta_e_hit; // src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49
|
|
if (io_s1_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s2_hit_dup_1 <= io_out_last_stage_meta_e_hit; // src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49
|
|
if (io_s1_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s2_hit_dup_2 <= io_out_last_stage_meta_e_hit; // src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49
|
|
if (io_s1_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s2_hit_dup_3 <= io_out_last_stage_meta_e_hit; // src/main/scala/xiangshan/frontend/FTB.scala:431:43, :432:49
|
|
if (io_s2_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_hit_dup_0 <= s2_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76
|
|
if (io_s2_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_hit_dup_1 <= s2_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76
|
|
if (io_s2_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_hit_dup_2 <= s2_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76
|
|
if (io_s2_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_hit_dup_3 <= s2_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:432:49, :433:76
|
|
end
|
|
end // always @(posedge, posedge)
|
|
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
`endif // FIRRTL_BEFORE_INITIAL
|
|
logic [31:0] _RANDOM[0:84]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
initial begin // src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
`endif // INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
for (logic [6:0] i = 7'h0; i < 7'h55; i += 7'h1) begin
|
|
_RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
end // src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
s1_pc_dup_0 = {_RANDOM[7'h0], _RANDOM[7'h1][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
s1_pc_dup_1 = {_RANDOM[7'h1][31:7], _RANDOM[7'h2][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7
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s1_pc_dup_2 = {_RANDOM[7'h2][31:14], _RANDOM[7'h3][20:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7
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s1_pc_dup_3 = {_RANDOM[7'h3][31:21], _RANDOM[7'h4][27:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7
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s2_pc_dup_0 = {_RANDOM[7'h4][31:28], _RANDOM[7'h5], _RANDOM[7'h6][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7
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s2_pc_dup_1 = {_RANDOM[7'h6][31:3], _RANDOM[7'h7][9:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7
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s2_pc_dup_2 = {_RANDOM[7'h7][31:10], _RANDOM[7'h8][16:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7
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s2_pc_dup_3 = {_RANDOM[7'h8][31:17], _RANDOM[7'h9][23:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7
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s3_pc_dup_0 = {_RANDOM[7'h9][31:24], _RANDOM[7'hA][30:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7
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s3_pc_dup_1 = {_RANDOM[7'hA][31], _RANDOM[7'hB], _RANDOM[7'hC][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7
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s3_pc_dup_2 = {_RANDOM[7'hC][31:6], _RANDOM[7'hD][12:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7
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s3_pc_dup_3 = {_RANDOM[7'hD][31:13], _RANDOM[7'hE][19:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7
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REG = _RANDOM[7'hE][20]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, :190:24, src/main/scala/xiangshan/frontend/FTB.scala:284:7
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REG_1 = _RANDOM[7'hE][21]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, :190:16, src/main/scala/xiangshan/frontend/FTB.scala:284:7
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s2_ftb_entry_dup_0_valid = _RANDOM[7'hE][23]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'hE][27:24]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_brSlots_0_lower = {_RANDOM[7'hE][31:28], _RANDOM[7'hF][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'hF][9:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'hF][10]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'hF][11]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'hF][15:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_tailSlot_lower = {_RANDOM[7'hF][31:16], _RANDOM[7'h10][3:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h10][5:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h10][6]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h10][7]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_pftAddr = _RANDOM[7'h10][11:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_carry = _RANDOM[7'h10][12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_isCall = _RANDOM[7'h10][13]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_isRet = _RANDOM[7'h10][14]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_isJalr = _RANDOM[7'h10][15]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h10][16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h10][17]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h10][18]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_1_brSlots_0_offset = _RANDOM[7'h10][23:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_1_brSlots_0_lower = {_RANDOM[7'h10][31:24], _RANDOM[7'h11][3:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h11][5:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h11][7]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_1_tailSlot_offset = _RANDOM[7'h11][11:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_1_tailSlot_lower = _RANDOM[7'h11][31:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h12][1:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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|
s2_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h12][2]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h12][3]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_1_pftAddr = _RANDOM[7'h12][7:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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|
s2_ftb_entry_dup_1_carry = _RANDOM[7'h12][8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h12][13]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h12][14]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_2_brSlots_0_offset = _RANDOM[7'h12][19:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_2_brSlots_0_lower = _RANDOM[7'h12][31:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h13][1:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h13][3]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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|
s2_ftb_entry_dup_2_tailSlot_offset = _RANDOM[7'h13][7:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_2_tailSlot_lower = _RANDOM[7'h13][27:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h13][29:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h13][30]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h13][31]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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|
s2_ftb_entry_dup_2_pftAddr = _RANDOM[7'h14][3:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_2_carry = _RANDOM[7'h14][4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_2_isCall = _RANDOM[7'h14][5]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_2_isRet = _RANDOM[7'h14][6]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_2_isJalr = _RANDOM[7'h14][7]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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|
s2_ftb_entry_dup_2_last_may_be_rvi_call = _RANDOM[7'h14][8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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s2_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h14][9]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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|
s2_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h14][10]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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|
s2_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h14][15:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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|
s2_ftb_entry_dup_3_brSlots_0_lower = _RANDOM[7'h14][27:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
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|
s2_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h14][29:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
s2_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h14][31]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
s2_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h15][3:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
s2_ftb_entry_dup_3_tailSlot_lower = _RANDOM[7'h15][23:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
s2_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h15][25:24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
s2_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h15][26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
s2_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h15][27]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
s2_ftb_entry_dup_3_pftAddr = _RANDOM[7'h15][31:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
s2_ftb_entry_dup_3_carry = _RANDOM[7'h16][0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
s2_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h16][5]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
s2_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h16][6]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
s3_ftb_entry_dup_0_valid = _RANDOM[7'h16][7]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88
|
|
s3_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'h16][11:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88
|
|
s3_ftb_entry_dup_0_brSlots_0_lower = _RANDOM[7'h16][23:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88
|
|
s3_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'h16][25:24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88
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|
s3_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'h16][26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88
|
|
s3_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'h16][27]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88
|
|
s3_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'h16][31:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :429:88
|
|
s3_ftb_entry_dup_0_tailSlot_lower = _RANDOM[7'h17][19:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h17][21:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h17][22]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h17][23]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_0_pftAddr = _RANDOM[7'h17][27:24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_0_carry = _RANDOM[7'h17][28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_0_isCall = _RANDOM[7'h17][29]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_0_isRet = _RANDOM[7'h17][30]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_0_isJalr = _RANDOM[7'h17][31]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h18][0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h18][1]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h18][2]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_1_brSlots_0_lower = _RANDOM[7'h18][19:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h18][21:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h18][23]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_1_tailSlot_lower = {_RANDOM[7'h18][31:28], _RANDOM[7'h19][15:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h19][17:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h19][18]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h19][19]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_1_pftAddr = _RANDOM[7'h19][23:20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_1_carry = _RANDOM[7'h19][24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h19][29]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h19][30]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_brSlots_0_lower = _RANDOM[7'h1A][15:4]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h1A][17:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h1A][19]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_tailSlot_lower = {_RANDOM[7'h1A][31:24], _RANDOM[7'h1B][11:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h1B][13:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h1B][14]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h1B][15]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_pftAddr = _RANDOM[7'h1B][19:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_carry = _RANDOM[7'h1B][20]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_isCall = _RANDOM[7'h1B][21]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_isRet = _RANDOM[7'h1B][22]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_isJalr = _RANDOM[7'h1B][23]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h1B][25]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h1B][26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h1B][31:28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_3_brSlots_0_lower = _RANDOM[7'h1C][11:0]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h1C][13:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h1C][15]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h1C][19:16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_3_tailSlot_lower = {_RANDOM[7'h1C][31:20], _RANDOM[7'h1D][7:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h1D][9:8]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h1D][10]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h1D][11]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_3_pftAddr = _RANDOM[7'h1D][15:12]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_3_carry = _RANDOM[7'h1D][16]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h1D][21]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s3_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h1D][22]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
s2_hit_dup_0 = _RANDOM[7'h1D][23]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49
|
|
s2_hit_dup_1 = _RANDOM[7'h1D][24]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49
|
|
s2_hit_dup_2 = _RANDOM[7'h1D][25]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49
|
|
s2_hit_dup_3 = _RANDOM[7'h1D][26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :432:49
|
|
s3_hit_dup_0 = _RANDOM[7'h1D][27]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76
|
|
s3_hit_dup_1 = _RANDOM[7'h1D][28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76
|
|
s3_hit_dup_2 = _RANDOM[7'h1D][29]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76
|
|
s3_hit_dup_3 = _RANDOM[7'h1D][30]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76
|
|
higher_r = {_RANDOM[7'h1D][31], _RANDOM[7'h1E][24:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :284:7, :429:88
|
|
higher_plus_one_r = {_RANDOM[7'h1E][31:25], _RANDOM[7'h1F][18:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r = {_RANDOM[7'h1F][31:19], _RANDOM[7'h20][12:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_1 = {_RANDOM[7'h20][31:13], _RANDOM[7'h21][6:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_1 = {_RANDOM[7'h21][31:7], _RANDOM[7'h22][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_1 = _RANDOM[7'h22][26:1]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_2 = {_RANDOM[7'h22][31:27], _RANDOM[7'h23][12:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_plus_one_r_2 = _RANDOM[7'h23][30:13]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_2 = {_RANDOM[7'h23][31], _RANDOM[7'h24][16:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
io_out_s2_full_pred_0_fallThroughAddr_stashed_carry = _RANDOM[7'h24][17]; // src/main/scala/xiangshan/frontend/FTB.scala:89:38, :177:36, :284:7
|
|
higher_r_3 = {_RANDOM[7'h24][31:18], _RANDOM[7'h25][11:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_3 = {_RANDOM[7'h25][31:12], _RANDOM[7'h26][5:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_3 = _RANDOM[7'h26][31:6]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_4 = _RANDOM[7'h27][25:0]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :284:7
|
|
higher_plus_one_r_4 = {_RANDOM[7'h27][31:26], _RANDOM[7'h28][19:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_4 = {_RANDOM[7'h28][31:20], _RANDOM[7'h29][13:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_5 = _RANDOM[7'h29][31:14]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_5 = _RANDOM[7'h2A][17:0]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :284:7
|
|
higher_minus_one_r_5 = {_RANDOM[7'h2A][31:18], _RANDOM[7'h2B][3:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
io_out_s2_full_pred_1_fallThroughAddr_stashed_carry = _RANDOM[7'h2B][4]; // src/main/scala/xiangshan/frontend/FTB.scala:89:38, :177:36, :284:7
|
|
higher_r_6 = _RANDOM[7'h2B][30:5]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_6 = {_RANDOM[7'h2B][31], _RANDOM[7'h2C][24:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_minus_one_r_6 = {_RANDOM[7'h2C][31:25], _RANDOM[7'h2D][18:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_7 = {_RANDOM[7'h2D][31:19], _RANDOM[7'h2E][12:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_7 = {_RANDOM[7'h2E][31:13], _RANDOM[7'h2F][6:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_7 = {_RANDOM[7'h2F][31:7], _RANDOM[7'h30][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_8 = _RANDOM[7'h30][18:1]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_8 = {_RANDOM[7'h30][31:19], _RANDOM[7'h31][4:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_minus_one_r_8 = _RANDOM[7'h31][22:5]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
io_out_s2_full_pred_2_fallThroughAddr_stashed_carry = _RANDOM[7'h31][23]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :177:36, :284:7
|
|
higher_r_9 = {_RANDOM[7'h31][31:24], _RANDOM[7'h32][17:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_plus_one_r_9 = {_RANDOM[7'h32][31:18], _RANDOM[7'h33][11:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_9 = {_RANDOM[7'h33][31:12], _RANDOM[7'h34][5:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_10 = _RANDOM[7'h34][31:6]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_10 = _RANDOM[7'h35][25:0]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :284:7
|
|
higher_minus_one_r_10 = {_RANDOM[7'h35][31:26], _RANDOM[7'h36][19:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_11 = {_RANDOM[7'h36][31:20], _RANDOM[7'h37][5:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_11 = _RANDOM[7'h37][23:6]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_11 = {_RANDOM[7'h37][31:24], _RANDOM[7'h38][9:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
io_out_s2_full_pred_3_fallThroughAddr_stashed_carry = _RANDOM[7'h38][10]; // src/main/scala/xiangshan/frontend/FTB.scala:89:38, :177:36, :284:7
|
|
higher_r_12 = {_RANDOM[7'h38][31:11], _RANDOM[7'h39][4:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_12 = _RANDOM[7'h39][30:5]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_12 = {_RANDOM[7'h39][31], _RANDOM[7'h3A][24:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_r_13 = {_RANDOM[7'h3A][31:25], _RANDOM[7'h3B][18:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_13 = {_RANDOM[7'h3B][31:19], _RANDOM[7'h3C][12:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_13 = {_RANDOM[7'h3C][31:13], _RANDOM[7'h3D][6:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_14 = _RANDOM[7'h3D][24:7]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_14 = {_RANDOM[7'h3D][31:25], _RANDOM[7'h3E][10:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_minus_one_r_14 = _RANDOM[7'h3E][28:11]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_15 = {_RANDOM[7'h3E][31:29], _RANDOM[7'h3F][22:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_plus_one_r_15 = {_RANDOM[7'h3F][31:23], _RANDOM[7'h40][16:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_15 = {_RANDOM[7'h40][31:17], _RANDOM[7'h41][10:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_16 = {_RANDOM[7'h41][31:11], _RANDOM[7'h42][4:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_16 = _RANDOM[7'h42][30:5]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_16 = {_RANDOM[7'h42][31], _RANDOM[7'h43][24:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_r_17 = {_RANDOM[7'h43][31:25], _RANDOM[7'h44][10:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_17 = _RANDOM[7'h44][28:11]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_17 = {_RANDOM[7'h44][31:29], _RANDOM[7'h45][14:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_r_18 = {_RANDOM[7'h45][31:15], _RANDOM[7'h46][8:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_18 = {_RANDOM[7'h46][31:9], _RANDOM[7'h47][2:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_18 = _RANDOM[7'h47][28:3]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_19 = {_RANDOM[7'h47][31:29], _RANDOM[7'h48][22:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_plus_one_r_19 = {_RANDOM[7'h48][31:23], _RANDOM[7'h49][16:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_19 = {_RANDOM[7'h49][31:17], _RANDOM[7'h4A][10:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_20 = _RANDOM[7'h4A][28:11]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_20 = {_RANDOM[7'h4A][31:29], _RANDOM[7'h4B][14:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_minus_one_r_20 = {_RANDOM[7'h4B][31:15], _RANDOM[7'h4C][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_21 = _RANDOM[7'h4C][26:1]; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_21 = {_RANDOM[7'h4C][31:27], _RANDOM[7'h4D][20:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_minus_one_r_21 = {_RANDOM[7'h4D][31:21], _RANDOM[7'h4E][14:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_22 = {_RANDOM[7'h4E][31:15], _RANDOM[7'h4F][8:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :89:38, :284:7
|
|
higher_plus_one_r_22 = {_RANDOM[7'h4F][31:9], _RANDOM[7'h50][2:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_22 = _RANDOM[7'h50][28:3]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
higher_r_23 = {_RANDOM[7'h50][31:29], _RANDOM[7'h51][14:0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_plus_one_r_23 = {_RANDOM[7'h51][31:15], _RANDOM[7'h52][0]}; // src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :284:7
|
|
higher_minus_one_r_23 = _RANDOM[7'h52][18:1]; // src/main/scala/xiangshan/frontend/FTB.scala:88:37, :89:38, :284:7
|
|
io_out_last_stage_meta_r = _RANDOM[7'h54][21:19]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:48
|
|
io_out_last_stage_meta_r_1 = _RANDOM[7'h54][24:22]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:{38,48}
|
|
io_s1_ready_REG = _RANDOM[7'h54][25]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:48, :483:76
|
|
ftbBank_io_update_write_way_REG = _RANDOM[7'h54][27:26]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:48, :499:76
|
|
ftbBank_io_update_write_alloc_REG = _RANDOM[7'h54][28]; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:48, :500:76
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin // src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
s2_hit_dup_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49
|
|
s2_hit_dup_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49
|
|
s2_hit_dup_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49
|
|
s2_hit_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:432:49
|
|
s3_hit_dup_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76
|
|
s3_hit_dup_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76
|
|
s3_hit_dup_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76
|
|
s3_hit_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:433:76
|
|
end
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/FTB.scala:284:7
|
|
`endif // FIRRTL_AFTER_INITIAL
|
|
`endif // ENABLE_INITIAL_REG_
|
|
DelayN_2 reset_vector_delay ( // utility/src/main/scala/utility/Hold.scala:97:23
|
|
.clock (clock),
|
|
.io_in (io_reset_vector),
|
|
.io_out (_reset_vector_delay_io_out)
|
|
);
|
|
FTBBank ftbBank ( // src/main/scala/xiangshan/frontend/FTB.scala:422:23
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_s1_fire (io_s1_fire_0),
|
|
.io_req_pc_ready (_ftbBank_io_req_pc_ready),
|
|
.io_req_pc_valid (io_s0_fire_0),
|
|
.io_req_pc_bits (io_in_bits_s0_pc_0),
|
|
.io_read_resp_valid (_ftbBank_io_read_resp_valid),
|
|
.io_read_resp_brSlots_0_offset
|
|
(_ftbBank_io_read_resp_brSlots_0_offset),
|
|
.io_read_resp_brSlots_0_lower
|
|
(_ftbBank_io_read_resp_brSlots_0_lower),
|
|
.io_read_resp_brSlots_0_tarStat
|
|
(_ftbBank_io_read_resp_brSlots_0_tarStat),
|
|
.io_read_resp_brSlots_0_sharing
|
|
(_ftbBank_io_read_resp_brSlots_0_sharing),
|
|
.io_read_resp_brSlots_0_valid
|
|
(_ftbBank_io_read_resp_brSlots_0_valid),
|
|
.io_read_resp_tailSlot_offset
|
|
(_ftbBank_io_read_resp_tailSlot_offset),
|
|
.io_read_resp_tailSlot_lower
|
|
(_ftbBank_io_read_resp_tailSlot_lower),
|
|
.io_read_resp_tailSlot_tarStat
|
|
(_ftbBank_io_read_resp_tailSlot_tarStat),
|
|
.io_read_resp_tailSlot_sharing
|
|
(_ftbBank_io_read_resp_tailSlot_sharing),
|
|
.io_read_resp_tailSlot_valid
|
|
(_ftbBank_io_read_resp_tailSlot_valid),
|
|
.io_read_resp_pftAddr (_ftbBank_io_read_resp_pftAddr),
|
|
.io_read_resp_carry (_ftbBank_io_read_resp_carry),
|
|
.io_read_resp_isCall (_ftbBank_io_read_resp_isCall),
|
|
.io_read_resp_isRet (_ftbBank_io_read_resp_isRet),
|
|
.io_read_resp_isJalr (_ftbBank_io_read_resp_isJalr),
|
|
.io_read_resp_last_may_be_rvi_call
|
|
(_ftbBank_io_read_resp_last_may_be_rvi_call),
|
|
.io_read_resp_always_taken_0
|
|
(_ftbBank_io_read_resp_always_taken_0),
|
|
.io_read_resp_always_taken_1
|
|
(_ftbBank_io_read_resp_always_taken_1),
|
|
.io_read_hits_valid (_ftbBank_io_read_hits_valid),
|
|
.io_read_hits_bits (_ftbBank_io_read_hits_bits),
|
|
.io_u_req_pc_valid (update_need_read), // src/main/scala/xiangshan/frontend/FTB.scala:481:34
|
|
.io_u_req_pc_bits (io_update_bits_pc),
|
|
.io_update_hits_valid (_ftbBank_io_update_hits_valid),
|
|
.io_update_hits_bits (_ftbBank_io_update_hits_bits),
|
|
.io_update_access
|
|
(u_valid & ~(io_update_bits_meta[0])), // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :481:37, :501:39
|
|
.io_update_pc (_ftb_write_tag_WIRE_2), // src/main/scala/xiangshan/frontend/FTB.scala:492:40
|
|
.io_update_write_data_valid
|
|
(update_now | _write_valid_delay_io_out), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :494:32, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_valid
|
|
(update_now ? io_update_bits_ftb_entry_valid : _delay2_entry_delay_io_out_valid), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_brSlots_0_offset
|
|
(update_now
|
|
? io_update_bits_ftb_entry_brSlots_0_offset
|
|
: _delay2_entry_delay_io_out_brSlots_0_offset), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_brSlots_0_lower
|
|
(update_now
|
|
? io_update_bits_ftb_entry_brSlots_0_lower
|
|
: _delay2_entry_delay_io_out_brSlots_0_lower), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_brSlots_0_tarStat
|
|
(update_now
|
|
? io_update_bits_ftb_entry_brSlots_0_tarStat
|
|
: _delay2_entry_delay_io_out_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_brSlots_0_sharing
|
|
(update_now
|
|
? io_update_bits_ftb_entry_brSlots_0_sharing
|
|
: _delay2_entry_delay_io_out_brSlots_0_sharing), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_brSlots_0_valid
|
|
(update_now
|
|
? io_update_bits_ftb_entry_brSlots_0_valid
|
|
: _delay2_entry_delay_io_out_brSlots_0_valid), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_tailSlot_offset
|
|
(update_now
|
|
? io_update_bits_ftb_entry_tailSlot_offset
|
|
: _delay2_entry_delay_io_out_tailSlot_offset), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_tailSlot_lower
|
|
(update_now
|
|
? io_update_bits_ftb_entry_tailSlot_lower
|
|
: _delay2_entry_delay_io_out_tailSlot_lower), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_tailSlot_tarStat
|
|
(update_now
|
|
? io_update_bits_ftb_entry_tailSlot_tarStat
|
|
: _delay2_entry_delay_io_out_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_tailSlot_sharing
|
|
(update_now
|
|
? io_update_bits_ftb_entry_tailSlot_sharing
|
|
: _delay2_entry_delay_io_out_tailSlot_sharing), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_tailSlot_valid
|
|
(update_now
|
|
? io_update_bits_ftb_entry_tailSlot_valid
|
|
: _delay2_entry_delay_io_out_tailSlot_valid), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_pftAddr
|
|
(update_now
|
|
? io_update_bits_ftb_entry_pftAddr
|
|
: _delay2_entry_delay_io_out_pftAddr), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_carry
|
|
(update_now ? io_update_bits_ftb_entry_carry : _delay2_entry_delay_io_out_carry), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_isCall
|
|
(update_now ? io_update_bits_ftb_entry_isCall : _delay2_entry_delay_io_out_isCall), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_isRet
|
|
(update_now ? io_update_bits_ftb_entry_isRet : _delay2_entry_delay_io_out_isRet), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_isJalr
|
|
(update_now ? io_update_bits_ftb_entry_isJalr : _delay2_entry_delay_io_out_isJalr), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_last_may_be_rvi_call
|
|
(update_now
|
|
? io_update_bits_ftb_entry_last_may_be_rvi_call
|
|
: _delay2_entry_delay_io_out_last_may_be_rvi_call), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_always_taken_0
|
|
(update_now
|
|
? io_update_bits_ftb_entry_always_taken_0
|
|
: _delay2_entry_delay_io_out_always_taken_0), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_entry_always_taken_1
|
|
(update_now
|
|
? io_update_bits_ftb_entry_always_taken_1
|
|
: _delay2_entry_delay_io_out_always_taken_1), // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :491:25, utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_update_write_data_bits_tag (_ftb_write_tag_WIRE_2[29:10]), // src/main/scala/xiangshan/frontend/FTB.scala:492:{40,75}
|
|
.io_update_write_way
|
|
(update_now ? io_update_bits_meta[2:1] : ftbBank_io_update_write_way_REG), // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :480:28, :499:{39,76}
|
|
.io_update_write_alloc
|
|
(~update_now & ftbBank_io_update_write_alloc_REG) // src/main/scala/xiangshan/frontend/FTB.scala:480:28, :500:{39,76}
|
|
);
|
|
DelayN_4 delay2_pc_delay ( // utility/src/main/scala/utility/Hold.scala:97:23
|
|
.clock (clock),
|
|
.io_in (io_update_bits_pc),
|
|
.io_out (_delay2_pc_delay_io_out)
|
|
);
|
|
DelayN_5 delay2_entry_delay ( // utility/src/main/scala/utility/Hold.scala:97:23
|
|
.clock (clock),
|
|
.io_in_valid (io_update_bits_ftb_entry_valid),
|
|
.io_in_brSlots_0_offset (io_update_bits_ftb_entry_brSlots_0_offset),
|
|
.io_in_brSlots_0_lower (io_update_bits_ftb_entry_brSlots_0_lower),
|
|
.io_in_brSlots_0_tarStat (io_update_bits_ftb_entry_brSlots_0_tarStat),
|
|
.io_in_brSlots_0_sharing (io_update_bits_ftb_entry_brSlots_0_sharing),
|
|
.io_in_brSlots_0_valid (io_update_bits_ftb_entry_brSlots_0_valid),
|
|
.io_in_tailSlot_offset (io_update_bits_ftb_entry_tailSlot_offset),
|
|
.io_in_tailSlot_lower (io_update_bits_ftb_entry_tailSlot_lower),
|
|
.io_in_tailSlot_tarStat (io_update_bits_ftb_entry_tailSlot_tarStat),
|
|
.io_in_tailSlot_sharing (io_update_bits_ftb_entry_tailSlot_sharing),
|
|
.io_in_tailSlot_valid (io_update_bits_ftb_entry_tailSlot_valid),
|
|
.io_in_pftAddr (io_update_bits_ftb_entry_pftAddr),
|
|
.io_in_carry (io_update_bits_ftb_entry_carry),
|
|
.io_in_isCall (io_update_bits_ftb_entry_isCall),
|
|
.io_in_isRet (io_update_bits_ftb_entry_isRet),
|
|
.io_in_isJalr (io_update_bits_ftb_entry_isJalr),
|
|
.io_in_last_may_be_rvi_call (io_update_bits_ftb_entry_last_may_be_rvi_call),
|
|
.io_in_always_taken_0 (io_update_bits_ftb_entry_always_taken_0),
|
|
.io_in_always_taken_1 (io_update_bits_ftb_entry_always_taken_1),
|
|
.io_out_valid (_delay2_entry_delay_io_out_valid),
|
|
.io_out_brSlots_0_offset (_delay2_entry_delay_io_out_brSlots_0_offset),
|
|
.io_out_brSlots_0_lower (_delay2_entry_delay_io_out_brSlots_0_lower),
|
|
.io_out_brSlots_0_tarStat (_delay2_entry_delay_io_out_brSlots_0_tarStat),
|
|
.io_out_brSlots_0_sharing (_delay2_entry_delay_io_out_brSlots_0_sharing),
|
|
.io_out_brSlots_0_valid (_delay2_entry_delay_io_out_brSlots_0_valid),
|
|
.io_out_tailSlot_offset (_delay2_entry_delay_io_out_tailSlot_offset),
|
|
.io_out_tailSlot_lower (_delay2_entry_delay_io_out_tailSlot_lower),
|
|
.io_out_tailSlot_tarStat (_delay2_entry_delay_io_out_tailSlot_tarStat),
|
|
.io_out_tailSlot_sharing (_delay2_entry_delay_io_out_tailSlot_sharing),
|
|
.io_out_tailSlot_valid (_delay2_entry_delay_io_out_tailSlot_valid),
|
|
.io_out_pftAddr (_delay2_entry_delay_io_out_pftAddr),
|
|
.io_out_carry (_delay2_entry_delay_io_out_carry),
|
|
.io_out_isCall (_delay2_entry_delay_io_out_isCall),
|
|
.io_out_isRet (_delay2_entry_delay_io_out_isRet),
|
|
.io_out_isJalr (_delay2_entry_delay_io_out_isJalr),
|
|
.io_out_last_may_be_rvi_call (_delay2_entry_delay_io_out_last_may_be_rvi_call),
|
|
.io_out_always_taken_0 (_delay2_entry_delay_io_out_always_taken_0),
|
|
.io_out_always_taken_1 (_delay2_entry_delay_io_out_always_taken_1)
|
|
);
|
|
DelayN_6 write_valid_delay ( // utility/src/main/scala/utility/Hold.scala:97:23
|
|
.clock (clock),
|
|
.io_in (u_valid & ~(io_update_bits_meta[0])), // src/main/scala/xiangshan/frontend/FTB.scala:473:36, :474:33, :481:37, :494:50
|
|
.io_out (_write_valid_delay_io_out)
|
|
);
|
|
assign io_out_s2_full_pred_0_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 | s2_hit_dup_0
|
|
& s2_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}
|
|
assign io_out_s2_full_pred_0_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 | s2_hit_dup_0
|
|
& s2_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}
|
|
assign io_out_s2_full_pred_0_slot_valids_0 = s2_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_0_slot_valids_1 = s2_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_0_targets_0 =
|
|
{(s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r : 26'h0)
|
|
| (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r : 26'h0)
|
|
| (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r : 26'h0),
|
|
s2_ftb_entry_dup_0_brSlots_0_lower,
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55
|
|
assign io_out_s2_full_pred_0_targets_1 = _io_out_s2_full_pred_0_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
|
|
assign io_out_s2_full_pred_0_jalr_target = _io_out_s2_full_pred_0_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
|
|
assign io_out_s2_full_pred_0_offsets_0 = s2_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_0_offsets_1 = s2_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_0_fallThroughAddr =
|
|
{1'h0, s2_pc_dup_0[4:1]} >= {s2_ftb_entry_dup_0_carry, s2_ftb_entry_dup_0_pftAddr}
|
|
? 39'(s2_pc_dup_0 + 39'h20)
|
|
: {io_out_s2_full_pred_0_fallThroughAddr_stashed_carry
|
|
? 34'(s2_pc_dup_0[38:5] + 34'h1)
|
|
: s2_pc_dup_0[38:5],
|
|
s2_ftb_entry_dup_0_pftAddr,
|
|
1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34, :550:{27,47}
|
|
assign io_out_s2_full_pred_0_is_br_sharing =
|
|
s2_ftb_entry_dup_0_tailSlot_valid & s2_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43
|
|
assign io_out_s2_full_pred_0_hit = s2_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49
|
|
assign io_out_s2_full_pred_1_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 | s2_hit_dup_1
|
|
& s2_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}
|
|
assign io_out_s2_full_pred_1_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 | s2_hit_dup_1
|
|
& s2_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}
|
|
assign io_out_s2_full_pred_1_slot_valids_0 = s2_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_1_slot_valids_1 = s2_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_1_targets_0 =
|
|
{(s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_3 : 26'h0)
|
|
| (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_3 : 26'h0)
|
|
| (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_3 : 26'h0),
|
|
s2_ftb_entry_dup_1_brSlots_0_lower,
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55
|
|
assign io_out_s2_full_pred_1_targets_1 = _io_out_s2_full_pred_1_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
|
|
assign io_out_s2_full_pred_1_jalr_target = _io_out_s2_full_pred_1_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
|
|
assign io_out_s2_full_pred_1_offsets_0 = s2_ftb_entry_dup_1_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_1_offsets_1 = s2_ftb_entry_dup_1_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_1_fallThroughAddr =
|
|
{1'h0, s2_pc_dup_1[4:1]} >= {s2_ftb_entry_dup_1_carry, s2_ftb_entry_dup_1_pftAddr}
|
|
? 39'(s2_pc_dup_1 + 39'h20)
|
|
: {io_out_s2_full_pred_1_fallThroughAddr_stashed_carry
|
|
? 34'(s2_pc_dup_1[38:5] + 34'h1)
|
|
: s2_pc_dup_1[38:5],
|
|
s2_ftb_entry_dup_1_pftAddr,
|
|
1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34, :550:{27,47}
|
|
assign io_out_s2_full_pred_1_is_br_sharing =
|
|
s2_ftb_entry_dup_1_tailSlot_valid & s2_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43
|
|
assign io_out_s2_full_pred_1_hit = s2_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49
|
|
assign io_out_s2_full_pred_2_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 | s2_hit_dup_2
|
|
& s2_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}
|
|
assign io_out_s2_full_pred_2_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 | s2_hit_dup_2
|
|
& s2_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}
|
|
assign io_out_s2_full_pred_2_slot_valids_0 = s2_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_2_slot_valids_1 = s2_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_2_targets_0 =
|
|
{(s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_6 : 26'h0)
|
|
| (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_6 : 26'h0)
|
|
| (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_6 : 26'h0),
|
|
s2_ftb_entry_dup_2_brSlots_0_lower,
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55
|
|
assign io_out_s2_full_pred_2_targets_1 = _io_out_s2_full_pred_2_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
|
|
assign io_out_s2_full_pred_2_jalr_target = _io_out_s2_full_pred_2_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
|
|
assign io_out_s2_full_pred_2_offsets_0 = s2_ftb_entry_dup_2_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_2_offsets_1 = s2_ftb_entry_dup_2_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_2_fallThroughAddr =
|
|
{1'h0, s2_pc_dup_2[4:1]} >= {s2_ftb_entry_dup_2_carry, s2_ftb_entry_dup_2_pftAddr}
|
|
? 39'(s2_pc_dup_2 + 39'h20)
|
|
: {io_out_s2_full_pred_2_fallThroughAddr_stashed_carry
|
|
? 34'(s2_pc_dup_2[38:5] + 34'h1)
|
|
: s2_pc_dup_2[38:5],
|
|
s2_ftb_entry_dup_2_pftAddr,
|
|
1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:547:{32,48}, :548:32, :549:34, :550:{27,47}
|
|
assign io_out_s2_full_pred_2_is_jalr =
|
|
s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:540:37
|
|
assign io_out_s2_full_pred_2_is_call =
|
|
s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:541:37
|
|
assign io_out_s2_full_pred_2_is_ret =
|
|
s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:542:36
|
|
assign io_out_s2_full_pred_2_last_may_be_rvi_call =
|
|
s2_ftb_entry_dup_2_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_2_is_br_sharing =
|
|
s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43
|
|
assign io_out_s2_full_pred_2_hit = s2_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49
|
|
assign io_out_s2_full_pred_3_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 | s2_hit_dup_3
|
|
& s2_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}
|
|
assign io_out_s2_full_pred_3_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 | s2_hit_dup_3
|
|
& s2_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, :432:49, :464:{57,67}
|
|
assign io_out_s2_full_pred_3_slot_valids_0 = s2_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_3_slot_valids_1 = s2_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_3_targets_0 =
|
|
{(s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_9 : 26'h0)
|
|
| (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_9 : 26'h0)
|
|
| (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_9 : 26'h0),
|
|
s2_ftb_entry_dup_3_brSlots_0_lower,
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :428:55
|
|
assign io_out_s2_full_pred_3_targets_1 = _io_out_s2_full_pred_3_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
|
|
assign io_out_s2_full_pred_3_jalr_target = _io_out_s2_full_pred_3_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
|
|
assign io_out_s2_full_pred_3_offsets_0 = s2_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_3_offsets_1 = s2_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55
|
|
assign io_out_s2_full_pred_3_fallThroughAddr =
|
|
_io_out_s2_full_pred_3_fallThroughErr_output
|
|
? 39'(s2_pc_dup_3 + 39'h20)
|
|
: {io_out_s2_full_pred_3_fallThroughAddr_stashed_carry
|
|
? 34'(s2_pc_dup_3[38:5] + 34'h1)
|
|
: s2_pc_dup_3[38:5],
|
|
s2_ftb_entry_dup_3_pftAddr,
|
|
1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :187:86, src/main/scala/xiangshan/frontend/FTB.scala:177:36, :284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47}
|
|
assign io_out_s2_full_pred_3_fallThroughErr =
|
|
_io_out_s2_full_pred_3_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34
|
|
assign io_out_s2_full_pred_3_is_br_sharing =
|
|
s2_ftb_entry_dup_3_tailSlot_valid & s2_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :428:55, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43
|
|
assign io_out_s2_full_pred_3_hit = s2_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :432:49
|
|
assign io_out_s3_full_pred_0_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 | s3_hit_dup_0
|
|
& s3_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}
|
|
assign io_out_s3_full_pred_0_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 | s3_hit_dup_0
|
|
& s3_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}
|
|
assign io_out_s3_full_pred_0_slot_valids_0 = s3_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
assign io_out_s3_full_pred_0_slot_valids_1 = s3_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
assign io_out_s3_full_pred_0_targets_0 =
|
|
{(s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_12 : 26'h0)
|
|
| (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_12 : 26'h0)
|
|
| (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r_12 : 26'h0),
|
|
s3_ftb_entry_dup_0_brSlots_0_lower,
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88
|
|
assign io_out_s3_full_pred_0_targets_1 = _io_out_s3_full_pred_0_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
|
|
assign io_out_s3_full_pred_0_jalr_target = _io_out_s3_full_pred_0_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
|
|
assign io_out_s3_full_pred_0_fallThroughAddr =
|
|
_io_out_s3_full_pred_0_fallThroughErr_output
|
|
? 39'(s3_pc_dup_0 + 39'h20)
|
|
: {s3_ftb_entry_dup_0_carry ? 34'(s3_pc_dup_0[38:5] + 34'h1) : s3_pc_dup_0[38:5],
|
|
s3_ftb_entry_dup_0_pftAddr,
|
|
1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47}
|
|
assign io_out_s3_full_pred_0_fallThroughErr =
|
|
_io_out_s3_full_pred_0_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34
|
|
assign io_out_s3_full_pred_0_is_br_sharing =
|
|
s3_ftb_entry_dup_0_tailSlot_valid & s3_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43
|
|
assign io_out_s3_full_pred_0_hit = s3_hit_dup_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76
|
|
assign io_out_s3_full_pred_1_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 | s3_hit_dup_1
|
|
& s3_ftb_entry_dup_1_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}
|
|
assign io_out_s3_full_pred_1_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 | s3_hit_dup_1
|
|
& s3_ftb_entry_dup_1_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}
|
|
assign io_out_s3_full_pred_1_slot_valids_0 = s3_ftb_entry_dup_1_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
assign io_out_s3_full_pred_1_slot_valids_1 = s3_ftb_entry_dup_1_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
|
assign io_out_s3_full_pred_1_targets_0 =
|
|
{(s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_15 : 26'h0)
|
|
| (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_15 : 26'h0)
|
|
| (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_15 : 26'h0),
|
|
s3_ftb_entry_dup_1_brSlots_0_lower,
|
|
1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88
|
|
assign io_out_s3_full_pred_1_targets_1 = _io_out_s3_full_pred_1_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
|
|
assign io_out_s3_full_pred_1_jalr_target = _io_out_s3_full_pred_1_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
|
|
assign io_out_s3_full_pred_1_fallThroughAddr =
|
|
_io_out_s3_full_pred_1_fallThroughErr_output
|
|
? 39'(s3_pc_dup_1 + 39'h20)
|
|
: {s3_ftb_entry_dup_1_carry ? 34'(s3_pc_dup_1[38:5] + 34'h1) : s3_pc_dup_1[38:5],
|
|
s3_ftb_entry_dup_1_pftAddr,
|
|
1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47}
|
|
assign io_out_s3_full_pred_1_fallThroughErr =
|
|
_io_out_s3_full_pred_1_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34
|
|
assign io_out_s3_full_pred_1_is_br_sharing =
|
|
s3_ftb_entry_dup_1_tailSlot_valid & s3_ftb_entry_dup_1_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43
|
|
assign io_out_s3_full_pred_1_hit = s3_hit_dup_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76
|
|
assign io_out_s3_full_pred_2_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 | s3_hit_dup_2
|
|
& s3_ftb_entry_dup_2_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}
|
|
assign io_out_s3_full_pred_2_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 | s3_hit_dup_2
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& s3_ftb_entry_dup_2_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}
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assign io_out_s3_full_pred_2_slot_valids_0 = s3_ftb_entry_dup_2_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_s3_full_pred_2_slot_valids_1 = s3_ftb_entry_dup_2_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_s3_full_pred_2_targets_0 =
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{(s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_18 : 26'h0)
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| (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_18 : 26'h0)
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| (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_18 : 26'h0),
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s3_ftb_entry_dup_2_brSlots_0_lower,
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1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88
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assign io_out_s3_full_pred_2_targets_1 = _io_out_s3_full_pred_2_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
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assign io_out_s3_full_pred_2_jalr_target = _io_out_s3_full_pred_2_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
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assign io_out_s3_full_pred_2_fallThroughAddr =
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_io_out_s3_full_pred_2_fallThroughErr_output
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? 39'(s3_pc_dup_2 + 39'h20)
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: {s3_ftb_entry_dup_2_carry ? 34'(s3_pc_dup_2[38:5] + 34'h1) : s3_pc_dup_2[38:5],
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s3_ftb_entry_dup_2_pftAddr,
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1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47}
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assign io_out_s3_full_pred_2_fallThroughErr =
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_io_out_s3_full_pred_2_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34
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assign io_out_s3_full_pred_2_is_jalr =
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s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:540:37
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assign io_out_s3_full_pred_2_is_call =
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s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:541:37
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assign io_out_s3_full_pred_2_is_ret =
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s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:542:36
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assign io_out_s3_full_pred_2_is_br_sharing =
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s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43
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assign io_out_s3_full_pred_2_hit = s3_hit_dup_2; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76
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assign io_out_s3_full_pred_3_br_taken_mask_0 =
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io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 | s3_hit_dup_3
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& s3_ftb_entry_dup_3_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}
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assign io_out_s3_full_pred_3_br_taken_mask_1 =
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io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 | s3_hit_dup_3
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& s3_ftb_entry_dup_3_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, :433:76, :467:{57,67}
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assign io_out_s3_full_pred_3_slot_valids_0 = s3_ftb_entry_dup_3_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_s3_full_pred_3_slot_valids_1 = s3_ftb_entry_dup_3_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_s3_full_pred_3_targets_0 =
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{(s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_21 : 26'h0)
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| (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_21 : 26'h0)
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| (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_21 : 26'h0),
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s3_ftb_entry_dup_3_brSlots_0_lower,
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1'h0}; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:175:26, src/main/scala/xiangshan/frontend/FTB.scala:87:28, :88:37, :89:38, :96:12, :98:19, :99:19, :100:19, :284:7, :429:88
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assign io_out_s3_full_pred_3_targets_1 = _io_out_s3_full_pred_3_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
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assign io_out_s3_full_pred_3_jalr_target = _io_out_s3_full_pred_3_targets_1_output; // src/main/scala/xiangshan/frontend/FTB.scala:96:12, :109:10, :284:7
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assign io_out_s3_full_pred_3_offsets_0 = s3_ftb_entry_dup_3_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_s3_full_pred_3_offsets_1 = s3_ftb_entry_dup_3_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_s3_full_pred_3_fallThroughAddr =
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_io_out_s3_full_pred_3_fallThroughErr_output
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? 39'(s3_pc_dup_3 + 39'h20)
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: {s3_ftb_entry_dup_3_carry ? 34'(s3_pc_dup_3[38:5] + 34'h1) : s3_pc_dup_3[38:5],
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s3_ftb_entry_dup_3_pftAddr,
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1'h0}; // src/main/scala/xiangshan/frontend/BPU.scala:110:28, :111:{8,12,26}, :175:26, :188:86, src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34, :550:{27,47}
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assign io_out_s3_full_pred_3_fallThroughErr =
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_io_out_s3_full_pred_3_fallThroughErr_output; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:549:34
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assign io_out_s3_full_pred_3_is_br_sharing =
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s3_ftb_entry_dup_3_tailSlot_valid & s3_ftb_entry_dup_3_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88, src/main/scala/xiangshan/frontend/FrontendBundle.scala:544:43
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assign io_out_s3_full_pred_3_hit = s3_hit_dup_3; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :433:76
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assign io_out_last_stage_meta = {216'h0, io_out_last_stage_meta_r_1}; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :458:{26,38}
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assign io_out_last_stage_ftb_entry_valid = s3_ftb_entry_dup_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_last_stage_ftb_entry_brSlots_0_offset =
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s3_ftb_entry_dup_0_brSlots_0_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_last_stage_ftb_entry_brSlots_0_lower = s3_ftb_entry_dup_0_brSlots_0_lower; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_last_stage_ftb_entry_brSlots_0_tarStat =
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s3_ftb_entry_dup_0_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_last_stage_ftb_entry_brSlots_0_sharing =
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s3_ftb_entry_dup_0_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_last_stage_ftb_entry_brSlots_0_valid = s3_ftb_entry_dup_0_brSlots_0_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_last_stage_ftb_entry_tailSlot_offset = s3_ftb_entry_dup_0_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_last_stage_ftb_entry_tailSlot_lower = s3_ftb_entry_dup_0_tailSlot_lower; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_last_stage_ftb_entry_tailSlot_tarStat =
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s3_ftb_entry_dup_0_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
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assign io_out_last_stage_ftb_entry_tailSlot_sharing =
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s3_ftb_entry_dup_0_tailSlot_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
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assign io_out_last_stage_ftb_entry_tailSlot_valid = s3_ftb_entry_dup_0_tailSlot_valid; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_last_stage_ftb_entry_pftAddr = s3_ftb_entry_dup_0_pftAddr; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_last_stage_ftb_entry_carry = s3_ftb_entry_dup_0_carry; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_last_stage_ftb_entry_isCall = s3_ftb_entry_dup_0_isCall; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_last_stage_ftb_entry_isRet = s3_ftb_entry_dup_0_isRet; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_out_last_stage_ftb_entry_isJalr = s3_ftb_entry_dup_0_isJalr; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
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assign io_out_last_stage_ftb_entry_last_may_be_rvi_call =
|
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s3_ftb_entry_dup_0_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
|
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assign io_out_last_stage_ftb_entry_always_taken_0 = s3_ftb_entry_dup_0_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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|
assign io_out_last_stage_ftb_entry_always_taken_1 = s3_ftb_entry_dup_0_always_taken_1; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :429:88
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assign io_s1_ready = _ftbBank_io_req_pc_ready & ~update_need_read & ~io_s1_ready_REG; // src/main/scala/xiangshan/frontend/FTB.scala:284:7, :422:23, :481:34, :483:{45,65,68,76}
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endmodule
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