From 5ff250c113098ed640f31a9c5a9a4b3eb9bd47c0 Mon Sep 17 00:00:00 2001 From: Makiras <22570332+Makiras@users.noreply.github.com> Date: Wed, 14 Aug 2024 13:18:22 +0800 Subject: [PATCH] add bpu top module --- Makefile | 3 + mk/BPUTop.mk | 45 + parse_relay.sh | 33 + rtl/BPUTop.txt | 79 + rtl/BPUTop/CAMTemplate.sv | 136 + rtl/BPUTop/CAMTemplate_32.sv | 136 + rtl/BPUTop/CAMTemplate_33.sv | 184 + rtl/BPUTop/CAMTemplate_41.sv | 110 + rtl/BPUTop/CAMTemplate_43.sv | 112 + rtl/BPUTop/Composer.sv | 2426 ++ rtl/BPUTop/DelayNWithValid.sv | 107 + rtl/BPUTop/DelayNWithValid_1.sv | 271 + rtl/BPUTop/DelayN_1.sv | 112 + rtl/BPUTop/DelayN_2.sv | 102 + rtl/BPUTop/DelayN_4.sv | 91 + rtl/BPUTop/FTB.sv | 1644 + rtl/BPUTop/FTBBank.sv | 6369 ++++ rtl/BPUTop/FauFTB.sv | 4755 +++ rtl/BPUTop/FauFTBWay.sv | 187 + rtl/BPUTop/Folded1WDataModuleTemplate.sv | 146 + rtl/BPUTop/Folded1WDataModuleTemplate_2.sv | 146 + rtl/BPUTop/FoldedSRAMTemplate.sv | 224 + rtl/BPUTop/FoldedSRAMTemplate_1.sv | 100 + rtl/BPUTop/FoldedSRAMTemplate_20.sv | 180 + rtl/BPUTop/FoldedSRAMTemplate_21.sv | 90 + rtl/BPUTop/FoldedSRAMTemplate_25.sv | 155 + rtl/BPUTop/ITTage.sv | 1269 + rtl/BPUTop/ITTageTable.sv | 226 + rtl/BPUTop/ITTageTable_1.sv | 221 + rtl/BPUTop/ITTageTable_2.sv | 222 + rtl/BPUTop/ITTageTable_3.sv | 222 + rtl/BPUTop/ITTageTable_4.sv | 222 + rtl/BPUTop/Predictor.sv | 33300 +++++++++++++++++++ rtl/BPUTop/PriorityMuxModule.sv | 80 + rtl/BPUTop/PriorityMuxModule_12.sv | 450 + rtl/BPUTop/PriorityMuxModule_16.sv | 80 + rtl/BPUTop/PriorityMuxModule_20.sv | 76 + rtl/BPUTop/PriorityMuxModule_4.sv | 354 + rtl/BPUTop/PriorityMuxModule_8.sv | 94 + rtl/BPUTop/RAS.sv | 883 + rtl/BPUTop/RASStack.sv | 1934 ++ rtl/BPUTop/SCTable.sv | 244 + rtl/BPUTop/SCTable_1.sv | 250 + rtl/BPUTop/SCTable_2.sv | 248 + rtl/BPUTop/SCTable_3.sv | 248 + rtl/BPUTop/SRAMTemplate_13.sv | 443 + rtl/BPUTop/SRAMTemplate_14.sv | 248 + rtl/BPUTop/SRAMTemplate_15.sv | 165 + rtl/BPUTop/SRAMTemplate_34.sv | 229 + rtl/BPUTop/SRAMTemplate_35.sv | 196 + rtl/BPUTop/SRAMTemplate_39.sv | 149 + rtl/BPUTop/SRAMTemplate_43.sv | 171 + rtl/BPUTop/TageBTable.sv | 188 + rtl/BPUTop/TageTable.sv | 752 + rtl/BPUTop/TageTable_1.sv | 754 + rtl/BPUTop/TageTable_2.sv | 754 + rtl/BPUTop/TageTable_3.sv | 754 + rtl/BPUTop/Tage_SC.sv | 5910 ++++ rtl/BPUTop/WrBypass.sv | 281 + rtl/BPUTop/WrBypass_32.sv | 355 + rtl/BPUTop/WrBypass_33.sv | 580 + rtl/BPUTop/WrBypass_41.sv | 157 + rtl/BPUTop/WrBypass_43.sv | 157 + rtl/BPUTop/array_0_0.sv | 76 + rtl/BPUTop/array_0_0_ext.v | 49 + rtl/BPUTop/array_3.sv | 78 + rtl/BPUTop/array_3_ext.v | 52 + rtl/BPUTop/array_4.sv | 78 + rtl/BPUTop/array_4_ext.v | 48 + rtl/BPUTop/array_5.sv | 78 + rtl/BPUTop/array_5_ext.v | 52 + rtl/BPUTop/array_6.sv | 82 + rtl/BPUTop/array_6_ext.v | 57 + rtl/BPUTop/array_7.sv | 82 + rtl/BPUTop/array_7_ext.v | 53 + rtl/BPUTop/array_8.sv | 78 + rtl/BPUTop/array_8_ext.v | 52 + rtl/BPUTop/data_16x16.sv | 95 + rtl/BPUTop/data_32x16.sv | 95 + rtl/BPUTop/data_mem_0_4x2.sv | 89 + rtl/BPUTop/data_mem_0_8x3.sv | 89 + rtl/BPUTop/data_mem_16x12.sv | 97 + rtl/BPUTop/data_mem_8x4.sv | 97 + 83 files changed, 72286 insertions(+) create mode 100644 mk/BPUTop.mk create mode 100755 parse_relay.sh create mode 100644 rtl/BPUTop.txt create mode 100644 rtl/BPUTop/CAMTemplate.sv create mode 100644 rtl/BPUTop/CAMTemplate_32.sv create mode 100644 rtl/BPUTop/CAMTemplate_33.sv create mode 100644 rtl/BPUTop/CAMTemplate_41.sv create mode 100644 rtl/BPUTop/CAMTemplate_43.sv create mode 100644 rtl/BPUTop/Composer.sv create mode 100644 rtl/BPUTop/DelayNWithValid.sv create mode 100644 rtl/BPUTop/DelayNWithValid_1.sv create mode 100644 rtl/BPUTop/DelayN_1.sv create mode 100644 rtl/BPUTop/DelayN_2.sv create mode 100644 rtl/BPUTop/DelayN_4.sv create mode 100644 rtl/BPUTop/FTB.sv create mode 100644 rtl/BPUTop/FTBBank.sv create mode 100644 rtl/BPUTop/FauFTB.sv create mode 100644 rtl/BPUTop/FauFTBWay.sv create mode 100644 rtl/BPUTop/Folded1WDataModuleTemplate.sv create mode 100644 rtl/BPUTop/Folded1WDataModuleTemplate_2.sv create mode 100644 rtl/BPUTop/FoldedSRAMTemplate.sv create mode 100644 rtl/BPUTop/FoldedSRAMTemplate_1.sv create mode 100644 rtl/BPUTop/FoldedSRAMTemplate_20.sv create mode 100644 rtl/BPUTop/FoldedSRAMTemplate_21.sv create mode 100644 rtl/BPUTop/FoldedSRAMTemplate_25.sv create mode 100644 rtl/BPUTop/ITTage.sv create mode 100644 rtl/BPUTop/ITTageTable.sv create mode 100644 rtl/BPUTop/ITTageTable_1.sv create mode 100644 rtl/BPUTop/ITTageTable_2.sv create mode 100644 rtl/BPUTop/ITTageTable_3.sv create mode 100644 rtl/BPUTop/ITTageTable_4.sv create mode 100644 rtl/BPUTop/Predictor.sv create mode 100644 rtl/BPUTop/PriorityMuxModule.sv create mode 100644 rtl/BPUTop/PriorityMuxModule_12.sv create mode 100644 rtl/BPUTop/PriorityMuxModule_16.sv create mode 100644 rtl/BPUTop/PriorityMuxModule_20.sv create mode 100644 rtl/BPUTop/PriorityMuxModule_4.sv create mode 100644 rtl/BPUTop/PriorityMuxModule_8.sv create mode 100644 rtl/BPUTop/RAS.sv create mode 100644 rtl/BPUTop/RASStack.sv create mode 100644 rtl/BPUTop/SCTable.sv create mode 100644 rtl/BPUTop/SCTable_1.sv create mode 100644 rtl/BPUTop/SCTable_2.sv create mode 100644 rtl/BPUTop/SCTable_3.sv create mode 100644 rtl/BPUTop/SRAMTemplate_13.sv create mode 100644 rtl/BPUTop/SRAMTemplate_14.sv create mode 100644 rtl/BPUTop/SRAMTemplate_15.sv create mode 100644 rtl/BPUTop/SRAMTemplate_34.sv create mode 100644 rtl/BPUTop/SRAMTemplate_35.sv create mode 100644 rtl/BPUTop/SRAMTemplate_39.sv create mode 100644 rtl/BPUTop/SRAMTemplate_43.sv create mode 100644 rtl/BPUTop/TageBTable.sv create mode 100644 rtl/BPUTop/TageTable.sv create mode 100644 rtl/BPUTop/TageTable_1.sv create mode 100644 rtl/BPUTop/TageTable_2.sv create mode 100644 rtl/BPUTop/TageTable_3.sv create mode 100644 rtl/BPUTop/Tage_SC.sv create mode 100644 rtl/BPUTop/WrBypass.sv create mode 100644 rtl/BPUTop/WrBypass_32.sv create mode 100644 rtl/BPUTop/WrBypass_33.sv create mode 100644 rtl/BPUTop/WrBypass_41.sv create mode 100644 rtl/BPUTop/WrBypass_43.sv create mode 100644 rtl/BPUTop/array_0_0.sv create mode 100644 rtl/BPUTop/array_0_0_ext.v create mode 100644 rtl/BPUTop/array_3.sv create mode 100644 rtl/BPUTop/array_3_ext.v create mode 100644 rtl/BPUTop/array_4.sv create mode 100644 rtl/BPUTop/array_4_ext.v create mode 100644 rtl/BPUTop/array_5.sv create mode 100644 rtl/BPUTop/array_5_ext.v create mode 100644 rtl/BPUTop/array_6.sv create mode 100644 rtl/BPUTop/array_6_ext.v create mode 100644 rtl/BPUTop/array_7.sv create mode 100644 rtl/BPUTop/array_7_ext.v create mode 100644 rtl/BPUTop/array_8.sv create mode 100644 rtl/BPUTop/array_8_ext.v create mode 100644 rtl/BPUTop/data_16x16.sv create mode 100644 rtl/BPUTop/data_32x16.sv create mode 100644 rtl/BPUTop/data_mem_0_4x2.sv create mode 100644 rtl/BPUTop/data_mem_0_8x3.sv create mode 100644 rtl/BPUTop/data_mem_16x12.sv create mode 100644 rtl/BPUTop/data_mem_8x4.sv diff --git a/Makefile b/Makefile index e58456d..bb62056 100644 --- a/Makefile +++ b/Makefile @@ -37,6 +37,9 @@ ras: ittage: make -f ./mk/ITTAGE.mk ittage +bputop: + make -f ./mk/BPUTop.mk BPUTop + filter: cat log|grep Cannot |awk '{print $8}'| sort| uniq|tr -d "'" diff --git a/mk/BPUTop.mk b/mk/BPUTop.mk new file mode 100644 index 0000000..63e495a --- /dev/null +++ b/mk/BPUTop.mk @@ -0,0 +1,45 @@ +TOP_ENTRY := ./rtl/BPUTop/Predictor.sv +TOP_FILES := ./rtl/BPUTop.txt +TL ?= cpp + +ifneq ($(TARGET),) + TARGET := $(TARGET) +else + TARGET := out/picker_out_BPUTop +endif + +# if EXAMPLE is set, then _EXAMPLE is set to -e +ifneq ($(EXAMPLE), false) + _EXAMPLE := -e +endif +_EXAMPLE ?= +# if VERBOSE is set, then _VERBOSE is set to -v +ifneq ($(VERBOSE), false) + _VERBOSE := --verbose +endif +_VERBOSE ?= +# if WAVE is set, then _WAVEFORM is set to -w +ifneq ($(WAVE), false) + ifneq ($(WAVE), true) + _WAVEFORM := -w $(WAVE) + else + _WAVEFORM := -w BPUTop.fst + endif +endif +_WAVEFORM ?= + +BPUTop: + @echo "Building tage module with parameters: " + @echo "TL=${TL}" + @echo "TOP_ENTRY=${TOP_ENTRY}" + @echo "TOP_FILES=${TOP_FILES}" + @echo "TARGET=${TARGET}" + @echo "WAVEFORM=${_WAVEFORM}" + @echo "VERBOSE=${_VERBOSE}" + @echo "EXAMPLE=${_EXAMPLE}" + + @mkdir -p out + rm -rf ${TARGET} + picker export ${TOP_ENTRY} --fs ${TOP_FILES} --lang ${TL} -c\ + --tdir ${TARGET} ${_WAVEFORM} ${_EXAMPLE} ${_VERBOSE} + diff --git a/parse_relay.sh b/parse_relay.sh new file mode 100755 index 0000000..1485f6a --- /dev/null +++ b/parse_relay.sh @@ -0,0 +1,33 @@ +#!/bin/zsh +## 初始文件名 +filename="$1" + +# 用于存储已经处理过的文件，避免重复处理 +declare -A processed_files + +# 递归查找依赖模块的函数 +find_dependencies() { + # 查看$1是否在数组中 + if [ -n "${processed_files[$1]}" ]; then + return + fi + + # 添加文件到已处理列表 + processed_files[$1]=$1 + + # 查找文件中的依赖模块 + grep -E '^\s*[a-zA-Z0-9_]+\s+[a-zA-Z0-9_]+\s* \(' "$1" | awk '{print $1}' | uniq | while read -r module; do + # 递归查找模块的依赖 + if [ -f "${module}.sv" ]; then + find_dependencies "${module}.sv" + elif [ -f "${module}.v" ]; then + find_dependencies "${module}.v" + fi + done +} + +# 开始查找依赖 +find_dependencies "$filename" + +# 输出所有查找到的文件 +echo ${processed_files[@]} \ No newline at end of file diff --git a/rtl/BPUTop.txt b/rtl/BPUTop.txt new file mode 100644 index 0000000..11653e3 --- /dev/null +++ b/rtl/BPUTop.txt @@ -0,0 +1,79 @@ +./rtl/BPUTop/DelayN_4.sv +./rtl/BPUTop/ITTageTable_4.sv +./rtl/BPUTop/SRAMTemplate_39.sv +./rtl/BPUTop/PriorityMuxModule_4.sv +./rtl/BPUTop/array_0_0.sv +./rtl/BPUTop/data_mem_8x4.sv +./rtl/BPUTop/WrBypass_32.sv +./rtl/BPUTop/array_8.sv +./rtl/BPUTop/array_6_ext.v +./rtl/BPUTop/array_6.sv +./rtl/BPUTop/Folded1WDataModuleTemplate_2.sv +./rtl/BPUTop/array_3.sv +./rtl/BPUTop/DelayNWithValid_1.sv +./rtl/BPUTop/array_5_ext.v +./rtl/BPUTop/PriorityMuxModule_20.sv +./rtl/BPUTop/ITTage.sv +./rtl/BPUTop/WrBypass_41.sv +./rtl/BPUTop/ITTageTable_1.sv +./rtl/BPUTop/data_16x16.sv +./rtl/BPUTop/DelayN_2.sv +./rtl/BPUTop/Tage_SC.sv +./rtl/BPUTop/SRAMTemplate_15.sv +./rtl/BPUTop/data_32x16.sv +./rtl/BPUTop/DelayN_1.sv +./rtl/BPUTop/CAMTemplate_32.sv +./rtl/BPUTop/RAS.sv +./rtl/BPUTop/TageTable_2.sv +./rtl/BPUTop/data_mem_0_8x3.sv +./rtl/BPUTop/SRAMTemplate_34.sv +./rtl/BPUTop/SRAMTemplate_35.sv +./rtl/BPUTop/WrBypass_33.sv +./rtl/BPUTop/DelayNWithValid.sv +./rtl/BPUTop/PriorityMuxModule.sv +./rtl/BPUTop/PriorityMuxModule_8.sv +./rtl/BPUTop/SCTable.sv +./rtl/BPUTop/CAMTemplate.sv +./rtl/BPUTop/SCTable_1.sv +./rtl/BPUTop/FTB.sv +./rtl/BPUTop/FTBBank.sv +./rtl/BPUTop/WrBypass.sv +./rtl/BPUTop/TageTable_1.sv +./rtl/BPUTop/array_7_ext.v +./rtl/BPUTop/SRAMTemplate_14.sv +./rtl/BPUTop/FauFTBWay.sv +./rtl/BPUTop/data_mem_0_4x2.sv +./rtl/BPUTop/SRAMTemplate_43.sv +./rtl/BPUTop/RASStack.sv +./rtl/BPUTop/CAMTemplate_33.sv +./rtl/BPUTop/array_4_ext.v +./rtl/BPUTop/Predictor.sv +./rtl/BPUTop/array_4.sv +./rtl/BPUTop/SCTable_3.sv +./rtl/BPUTop/ITTageTable.sv +./rtl/BPUTop/CAMTemplate_43.sv +./rtl/BPUTop/TageTable_3.sv +./rtl/BPUTop/PriorityMuxModule_16.sv +./rtl/BPUTop/array_0_0_ext.v +./rtl/BPUTop/CAMTemplate_41.sv +./rtl/BPUTop/PriorityMuxModule_12.sv +./rtl/BPUTop/array_8_ext.v +./rtl/BPUTop/array_3_ext.v +./rtl/BPUTop/array_7.sv +./rtl/BPUTop/TageBTable.sv +./rtl/BPUTop/FoldedSRAMTemplate_1.sv +./rtl/BPUTop/FoldedSRAMTemplate_20.sv +./rtl/BPUTop/ITTageTable_2.sv +./rtl/BPUTop/WrBypass_43.sv +./rtl/BPUTop/FoldedSRAMTemplate_21.sv +./rtl/BPUTop/array_5.sv +./rtl/BPUTop/FoldedSRAMTemplate_25.sv +./rtl/BPUTop/Folded1WDataModuleTemplate.sv +./rtl/BPUTop/data_mem_16x12.sv +./rtl/BPUTop/FauFTB.sv +./rtl/BPUTop/SRAMTemplate_13.sv +./rtl/BPUTop/ITTageTable_3.sv +./rtl/BPUTop/Composer.sv +./rtl/BPUTop/FoldedSRAMTemplate.sv +./rtl/BPUTop/TageTable.sv +./rtl/BPUTop/SCTable_2.sv diff --git a/rtl/BPUTop/CAMTemplate.sv b/rtl/BPUTop/CAMTemplate.sv new file mode 100644 index 0000000..94f9218 --- /dev/null +++ b/rtl/BPUTop/CAMTemplate.sv @@ -0,0 +1,136 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module CAMTemplate( + input clock, + input [8:0] io_r_req_0_idx, + output io_r_resp_0_0, + output io_r_resp_0_1, + output io_r_resp_0_2, + output io_r_resp_0_3, + output io_r_resp_0_4, + output io_r_resp_0_5, + output io_r_resp_0_6, + output io_r_resp_0_7, + input io_w_valid, + input [8:0] io_w_bits_data_idx, + input [2:0] io_w_bits_index +); + + reg [8:0] array_0; + reg [8:0] array_1; + reg [8:0] array_2; + reg [8:0] array_3; + reg [8:0] array_4; + reg [8:0] array_5; + reg [8:0] array_6; + reg [8:0] array_7; + always @(posedge clock) begin + if (io_w_valid & io_w_bits_index == 3'h0) + array_0 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 3'h1) + array_1 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 3'h2) + array_2 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 3'h3) + array_3 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 3'h4) + array_4 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 3'h5) + array_5 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 3'h6) + array_6 <= io_w_bits_data_idx; + if (io_w_valid & (&io_w_bits_index)) + array_7 <= io_w_bits_data_idx; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; + end + array_0 = _RANDOM[2'h0][8:0]; + array_1 = _RANDOM[2'h0][17:9]; + array_2 = _RANDOM[2'h0][26:18]; + array_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][3:0]}; + array_4 = _RANDOM[2'h1][12:4]; + array_5 = _RANDOM[2'h1][21:13]; + array_6 = _RANDOM[2'h1][30:22]; + array_7 = {_RANDOM[2'h1][31], _RANDOM[2'h2][7:0]}; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_r_resp_0_0 = io_r_req_0_idx == array_0; + assign io_r_resp_0_1 = io_r_req_0_idx == array_1; + assign io_r_resp_0_2 = io_r_req_0_idx == array_2; + assign io_r_resp_0_3 = io_r_req_0_idx == array_3; + assign io_r_resp_0_4 = io_r_req_0_idx == array_4; + assign io_r_resp_0_5 = io_r_req_0_idx == array_5; + assign io_r_resp_0_6 = io_r_req_0_idx == array_6; + assign io_r_resp_0_7 = io_r_req_0_idx == array_7; +endmodule + diff --git a/rtl/BPUTop/CAMTemplate_32.sv b/rtl/BPUTop/CAMTemplate_32.sv new file mode 100644 index 0000000..1abd6e3 --- /dev/null +++ b/rtl/BPUTop/CAMTemplate_32.sv @@ -0,0 +1,136 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module CAMTemplate_32( + input clock, + input [10:0] io_r_req_0_idx, + output io_r_resp_0_0, + output io_r_resp_0_1, + output io_r_resp_0_2, + output io_r_resp_0_3, + output io_r_resp_0_4, + output io_r_resp_0_5, + output io_r_resp_0_6, + output io_r_resp_0_7, + input io_w_valid, + input [10:0] io_w_bits_data_idx, + input [2:0] io_w_bits_index +); + + reg [10:0] array_0; + reg [10:0] array_1; + reg [10:0] array_2; + reg [10:0] array_3; + reg [10:0] array_4; + reg [10:0] array_5; + reg [10:0] array_6; + reg [10:0] array_7; + always @(posedge clock) begin + if (io_w_valid & io_w_bits_index == 3'h0) + array_0 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 3'h1) + array_1 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 3'h2) + array_2 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 3'h3) + array_3 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 3'h4) + array_4 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 3'h5) + array_5 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 3'h6) + array_6 <= io_w_bits_data_idx; + if (io_w_valid & (&io_w_bits_index)) + array_7 <= io_w_bits_data_idx; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; + end + array_0 = _RANDOM[2'h0][10:0]; + array_1 = _RANDOM[2'h0][21:11]; + array_2 = {_RANDOM[2'h0][31:22], _RANDOM[2'h1][0]}; + array_3 = _RANDOM[2'h1][11:1]; + array_4 = _RANDOM[2'h1][22:12]; + array_5 = {_RANDOM[2'h1][31:23], _RANDOM[2'h2][1:0]}; + array_6 = _RANDOM[2'h2][12:2]; + array_7 = _RANDOM[2'h2][23:13]; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_r_resp_0_0 = io_r_req_0_idx == array_0; + assign io_r_resp_0_1 = io_r_req_0_idx == array_1; + assign io_r_resp_0_2 = io_r_req_0_idx == array_2; + assign io_r_resp_0_3 = io_r_req_0_idx == array_3; + assign io_r_resp_0_4 = io_r_req_0_idx == array_4; + assign io_r_resp_0_5 = io_r_req_0_idx == array_5; + assign io_r_resp_0_6 = io_r_req_0_idx == array_6; + assign io_r_resp_0_7 = io_r_req_0_idx == array_7; +endmodule + diff --git a/rtl/BPUTop/CAMTemplate_33.sv b/rtl/BPUTop/CAMTemplate_33.sv new file mode 100644 index 0000000..1b7fe54 --- /dev/null +++ b/rtl/BPUTop/CAMTemplate_33.sv @@ -0,0 +1,184 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module CAMTemplate_33( + input clock, + input [7:0] io_r_req_0_idx, + output io_r_resp_0_0, + output io_r_resp_0_1, + output io_r_resp_0_2, + output io_r_resp_0_3, + output io_r_resp_0_4, + output io_r_resp_0_5, + output io_r_resp_0_6, + output io_r_resp_0_7, + output io_r_resp_0_8, + output io_r_resp_0_9, + output io_r_resp_0_10, + output io_r_resp_0_11, + output io_r_resp_0_12, + output io_r_resp_0_13, + output io_r_resp_0_14, + output io_r_resp_0_15, + input io_w_valid, + input [7:0] io_w_bits_data_idx, + input [3:0] io_w_bits_index +); + + reg [7:0] array_0; + reg [7:0] array_1; + reg [7:0] array_2; + reg [7:0] array_3; + reg [7:0] array_4; + reg [7:0] array_5; + reg [7:0] array_6; + reg [7:0] array_7; + reg [7:0] array_8; + reg [7:0] array_9; + reg [7:0] array_10; + reg [7:0] array_11; + reg [7:0] array_12; + reg [7:0] array_13; + reg [7:0] array_14; + reg [7:0] array_15; + always @(posedge clock) begin + if (io_w_valid & io_w_bits_index == 4'h0) + array_0 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'h1) + array_1 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'h2) + array_2 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'h3) + array_3 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'h4) + array_4 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'h5) + array_5 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'h6) + array_6 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'h7) + array_7 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'h8) + array_8 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'h9) + array_9 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'hA) + array_10 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'hB) + array_11 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'hC) + array_12 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'hD) + array_13 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 4'hE) + array_14 <= io_w_bits_data_idx; + if (io_w_valid & (&io_w_bits_index)) + array_15 <= io_w_bits_data_idx; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; + end + array_0 = _RANDOM[2'h0][7:0]; + array_1 = _RANDOM[2'h0][15:8]; + array_2 = _RANDOM[2'h0][23:16]; + array_3 = _RANDOM[2'h0][31:24]; + array_4 = _RANDOM[2'h1][7:0]; + array_5 = _RANDOM[2'h1][15:8]; + array_6 = _RANDOM[2'h1][23:16]; + array_7 = _RANDOM[2'h1][31:24]; + array_8 = _RANDOM[2'h2][7:0]; + array_9 = _RANDOM[2'h2][15:8]; + array_10 = _RANDOM[2'h2][23:16]; + array_11 = _RANDOM[2'h2][31:24]; + array_12 = _RANDOM[2'h3][7:0]; + array_13 = _RANDOM[2'h3][15:8]; + array_14 = _RANDOM[2'h3][23:16]; + array_15 = _RANDOM[2'h3][31:24]; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_r_resp_0_0 = io_r_req_0_idx == array_0; + assign io_r_resp_0_1 = io_r_req_0_idx == array_1; + assign io_r_resp_0_2 = io_r_req_0_idx == array_2; + assign io_r_resp_0_3 = io_r_req_0_idx == array_3; + assign io_r_resp_0_4 = io_r_req_0_idx == array_4; + assign io_r_resp_0_5 = io_r_req_0_idx == array_5; + assign io_r_resp_0_6 = io_r_req_0_idx == array_6; + assign io_r_resp_0_7 = io_r_req_0_idx == array_7; + assign io_r_resp_0_8 = io_r_req_0_idx == array_8; + assign io_r_resp_0_9 = io_r_req_0_idx == array_9; + assign io_r_resp_0_10 = io_r_req_0_idx == array_10; + assign io_r_resp_0_11 = io_r_req_0_idx == array_11; + assign io_r_resp_0_12 = io_r_req_0_idx == array_12; + assign io_r_resp_0_13 = io_r_req_0_idx == array_13; + assign io_r_resp_0_14 = io_r_req_0_idx == array_14; + assign io_r_resp_0_15 = io_r_req_0_idx == array_15; +endmodule + diff --git a/rtl/BPUTop/CAMTemplate_41.sv b/rtl/BPUTop/CAMTemplate_41.sv new file mode 100644 index 0000000..04a965e --- /dev/null +++ b/rtl/BPUTop/CAMTemplate_41.sv @@ -0,0 +1,110 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module CAMTemplate_41( + input clock, + input [7:0] io_r_req_0_idx, + output io_r_resp_0_0, + output io_r_resp_0_1, + output io_r_resp_0_2, + output io_r_resp_0_3, + input io_w_valid, + input [7:0] io_w_bits_data_idx, + input [1:0] io_w_bits_index +); + + reg [7:0] array_0; + reg [7:0] array_1; + reg [7:0] array_2; + reg [7:0] array_3; + always @(posedge clock) begin + if (io_w_valid & io_w_bits_index == 2'h0) + array_0 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 2'h1) + array_1 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 2'h2) + array_2 <= io_w_bits_data_idx; + if (io_w_valid & (&io_w_bits_index)) + array_3 <= io_w_bits_data_idx; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + array_0 = _RANDOM[/*Zero width*/ 1'b0][7:0]; + array_1 = _RANDOM[/*Zero width*/ 1'b0][15:8]; + array_2 = _RANDOM[/*Zero width*/ 1'b0][23:16]; + array_3 = _RANDOM[/*Zero width*/ 1'b0][31:24]; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_r_resp_0_0 = io_r_req_0_idx == array_0; + assign io_r_resp_0_1 = io_r_req_0_idx == array_1; + assign io_r_resp_0_2 = io_r_req_0_idx == array_2; + assign io_r_resp_0_3 = io_r_req_0_idx == array_3; +endmodule + diff --git a/rtl/BPUTop/CAMTemplate_43.sv b/rtl/BPUTop/CAMTemplate_43.sv new file mode 100644 index 0000000..a91a3d7 --- /dev/null +++ b/rtl/BPUTop/CAMTemplate_43.sv @@ -0,0 +1,112 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module CAMTemplate_43( + input clock, + input [8:0] io_r_req_0_idx, + output io_r_resp_0_0, + output io_r_resp_0_1, + output io_r_resp_0_2, + output io_r_resp_0_3, + input io_w_valid, + input [8:0] io_w_bits_data_idx, + input [1:0] io_w_bits_index +); + + reg [8:0] array_0; + reg [8:0] array_1; + reg [8:0] array_2; + reg [8:0] array_3; + always @(posedge clock) begin + if (io_w_valid & io_w_bits_index == 2'h0) + array_0 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 2'h1) + array_1 <= io_w_bits_data_idx; + if (io_w_valid & io_w_bits_index == 2'h2) + array_2 <= io_w_bits_data_idx; + if (io_w_valid & (&io_w_bits_index)) + array_3 <= io_w_bits_data_idx; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; + end + array_0 = _RANDOM[1'h0][8:0]; + array_1 = _RANDOM[1'h0][17:9]; + array_2 = _RANDOM[1'h0][26:18]; + array_3 = {_RANDOM[1'h0][31:27], _RANDOM[1'h1][3:0]}; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_r_resp_0_0 = io_r_req_0_idx == array_0; + assign io_r_resp_0_1 = io_r_req_0_idx == array_1; + assign io_r_resp_0_2 = io_r_req_0_idx == array_2; + assign io_r_resp_0_3 = io_r_req_0_idx == array_3; +endmodule + diff --git a/rtl/BPUTop/Composer.sv b/rtl/BPUTop/Composer.sv new file mode 100644 index 0000000..5d958fb --- /dev/null +++ b/rtl/BPUTop/Composer.sv @@ -0,0 +1,2426 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module Composer( + input clock, + input reset, + input [35:0] io_reset_vector, + input [40:0] io_in_bits_s0_pc_0, + input [40:0] io_in_bits_s0_pc_1, + input [40:0] io_in_bits_s0_pc_2, + input [40:0] io_in_bits_s0_pc_3, + input [10:0] io_in_bits_folded_hist_1_hist_17_folded_hist, + input [10:0] io_in_bits_folded_hist_1_hist_16_folded_hist, + input [6:0] io_in_bits_folded_hist_1_hist_15_folded_hist, + input [7:0] io_in_bits_folded_hist_1_hist_14_folded_hist, + input [6:0] io_in_bits_folded_hist_1_hist_9_folded_hist, + input [7:0] io_in_bits_folded_hist_1_hist_8_folded_hist, + input [6:0] io_in_bits_folded_hist_1_hist_7_folded_hist, + input [6:0] io_in_bits_folded_hist_1_hist_5_folded_hist, + input [7:0] io_in_bits_folded_hist_1_hist_4_folded_hist, + input [7:0] io_in_bits_folded_hist_1_hist_3_folded_hist, + input [10:0] io_in_bits_folded_hist_1_hist_1_folded_hist, + input [7:0] io_in_bits_folded_hist_3_hist_14_folded_hist, + input [8:0] io_in_bits_folded_hist_3_hist_13_folded_hist, + input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, + input [7:0] io_in_bits_folded_hist_3_hist_11_folded_hist, + input [8:0] io_in_bits_folded_hist_3_hist_10_folded_hist, + input [8:0] io_in_bits_folded_hist_3_hist_6_folded_hist, + input [7:0] io_in_bits_folded_hist_3_hist_4_folded_hist, + input [7:0] io_in_bits_folded_hist_3_hist_3_folded_hist, + input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, + output [40:0] io_out_s1_pc_0, + output [40:0] io_out_s1_pc_1, + output [40:0] io_out_s1_pc_2, + output [40:0] io_out_s1_pc_3, + output io_out_s1_full_pred_0_br_taken_mask_0, + output io_out_s1_full_pred_0_br_taken_mask_1, + output io_out_s1_full_pred_0_slot_valids_0, + output io_out_s1_full_pred_0_slot_valids_1, + output [40:0] io_out_s1_full_pred_0_targets_0, + output [40:0] io_out_s1_full_pred_0_targets_1, + output [3:0] io_out_s1_full_pred_0_offsets_0, + output [3:0] io_out_s1_full_pred_0_offsets_1, + output [40:0] io_out_s1_full_pred_0_fallThroughAddr, + output io_out_s1_full_pred_0_is_br_sharing, + output io_out_s1_full_pred_0_hit, + output io_out_s1_full_pred_1_br_taken_mask_0, + output io_out_s1_full_pred_1_br_taken_mask_1, + output io_out_s1_full_pred_1_slot_valids_0, + output io_out_s1_full_pred_1_slot_valids_1, + output [40:0] io_out_s1_full_pred_1_targets_0, + output [40:0] io_out_s1_full_pred_1_targets_1, + output [3:0] io_out_s1_full_pred_1_offsets_0, + output [3:0] io_out_s1_full_pred_1_offsets_1, + output [40:0] io_out_s1_full_pred_1_fallThroughAddr, + output io_out_s1_full_pred_1_is_br_sharing, + output io_out_s1_full_pred_1_hit, + output io_out_s1_full_pred_2_br_taken_mask_0, + output io_out_s1_full_pred_2_br_taken_mask_1, + output io_out_s1_full_pred_2_slot_valids_0, + output io_out_s1_full_pred_2_slot_valids_1, + output [40:0] io_out_s1_full_pred_2_targets_0, + output [40:0] io_out_s1_full_pred_2_targets_1, + output [3:0] io_out_s1_full_pred_2_offsets_0, + output [3:0] io_out_s1_full_pred_2_offsets_1, + output [40:0] io_out_s1_full_pred_2_fallThroughAddr, + output io_out_s1_full_pred_2_is_br_sharing, + output io_out_s1_full_pred_2_hit, + output io_out_s1_full_pred_3_br_taken_mask_0, + output io_out_s1_full_pred_3_br_taken_mask_1, + output io_out_s1_full_pred_3_slot_valids_0, + output io_out_s1_full_pred_3_slot_valids_1, + output [40:0] io_out_s1_full_pred_3_targets_0, + output [40:0] io_out_s1_full_pred_3_targets_1, + output [3:0] io_out_s1_full_pred_3_offsets_0, + output [3:0] io_out_s1_full_pred_3_offsets_1, + output [40:0] io_out_s1_full_pred_3_fallThroughAddr, + output io_out_s1_full_pred_3_fallThroughErr, + output io_out_s1_full_pred_3_is_br_sharing, + output io_out_s1_full_pred_3_hit, + output [40:0] io_out_s2_pc_0, + output [40:0] io_out_s2_pc_1, + output [40:0] io_out_s2_pc_2, + output [40:0] io_out_s2_pc_3, + output io_out_s2_full_pred_0_br_taken_mask_0, + output io_out_s2_full_pred_0_br_taken_mask_1, + output io_out_s2_full_pred_0_slot_valids_0, + output io_out_s2_full_pred_0_slot_valids_1, + output [40:0] io_out_s2_full_pred_0_targets_0, + output [40:0] io_out_s2_full_pred_0_targets_1, + output [3:0] io_out_s2_full_pred_0_offsets_0, + output [3:0] io_out_s2_full_pred_0_offsets_1, + output [40:0] io_out_s2_full_pred_0_fallThroughAddr, + output io_out_s2_full_pred_0_is_br_sharing, + output io_out_s2_full_pred_0_hit, + output io_out_s2_full_pred_1_br_taken_mask_0, + output io_out_s2_full_pred_1_br_taken_mask_1, + output io_out_s2_full_pred_1_slot_valids_0, + output io_out_s2_full_pred_1_slot_valids_1, + output [40:0] io_out_s2_full_pred_1_targets_0, + output [40:0] io_out_s2_full_pred_1_targets_1, + output [3:0] io_out_s2_full_pred_1_offsets_0, + output [3:0] io_out_s2_full_pred_1_offsets_1, + output [40:0] io_out_s2_full_pred_1_fallThroughAddr, + output io_out_s2_full_pred_1_is_br_sharing, + output io_out_s2_full_pred_1_hit, + output io_out_s2_full_pred_2_br_taken_mask_0, + output io_out_s2_full_pred_2_br_taken_mask_1, + output io_out_s2_full_pred_2_slot_valids_0, + output io_out_s2_full_pred_2_slot_valids_1, + output [40:0] io_out_s2_full_pred_2_targets_0, + output [40:0] io_out_s2_full_pred_2_targets_1, + output [3:0] io_out_s2_full_pred_2_offsets_0, + output [3:0] io_out_s2_full_pred_2_offsets_1, + output [40:0] io_out_s2_full_pred_2_fallThroughAddr, + output io_out_s2_full_pred_2_is_br_sharing, + output io_out_s2_full_pred_2_hit, + output io_out_s2_full_pred_3_br_taken_mask_0, + output io_out_s2_full_pred_3_br_taken_mask_1, + output io_out_s2_full_pred_3_slot_valids_0, + output io_out_s2_full_pred_3_slot_valids_1, + output [40:0] io_out_s2_full_pred_3_targets_0, + output [40:0] io_out_s2_full_pred_3_targets_1, + output [3:0] io_out_s2_full_pred_3_offsets_0, + output [3:0] io_out_s2_full_pred_3_offsets_1, + output [40:0] io_out_s2_full_pred_3_fallThroughAddr, + output io_out_s2_full_pred_3_fallThroughErr, + output io_out_s2_full_pred_3_is_br_sharing, + output io_out_s2_full_pred_3_hit, + output [40:0] io_out_s3_pc_0, + output [40:0] io_out_s3_pc_1, + output [40:0] io_out_s3_pc_2, + output [40:0] io_out_s3_pc_3, + output io_out_s3_full_pred_0_br_taken_mask_0, + output io_out_s3_full_pred_0_br_taken_mask_1, + output io_out_s3_full_pred_0_slot_valids_0, + output io_out_s3_full_pred_0_slot_valids_1, + output [40:0] io_out_s3_full_pred_0_targets_0, + output [40:0] io_out_s3_full_pred_0_targets_1, + output [40:0] io_out_s3_full_pred_0_fallThroughAddr, + output io_out_s3_full_pred_0_fallThroughErr, + output io_out_s3_full_pred_0_is_br_sharing, + output io_out_s3_full_pred_0_hit, + output io_out_s3_full_pred_1_br_taken_mask_0, + output io_out_s3_full_pred_1_br_taken_mask_1, + output io_out_s3_full_pred_1_slot_valids_0, + output io_out_s3_full_pred_1_slot_valids_1, + output [40:0] io_out_s3_full_pred_1_targets_0, + output [40:0] io_out_s3_full_pred_1_targets_1, + output [40:0] io_out_s3_full_pred_1_fallThroughAddr, + output io_out_s3_full_pred_1_fallThroughErr, + output io_out_s3_full_pred_1_is_br_sharing, + output io_out_s3_full_pred_1_hit, + output io_out_s3_full_pred_2_br_taken_mask_0, + output io_out_s3_full_pred_2_br_taken_mask_1, + output io_out_s3_full_pred_2_slot_valids_0, + output io_out_s3_full_pred_2_slot_valids_1, + output [40:0] io_out_s3_full_pred_2_targets_0, + output [40:0] io_out_s3_full_pred_2_targets_1, + output [40:0] io_out_s3_full_pred_2_fallThroughAddr, + output io_out_s3_full_pred_2_fallThroughErr, + output io_out_s3_full_pred_2_is_br_sharing, + output io_out_s3_full_pred_2_hit, + output io_out_s3_full_pred_3_br_taken_mask_0, + output io_out_s3_full_pred_3_br_taken_mask_1, + output io_out_s3_full_pred_3_slot_valids_0, + output io_out_s3_full_pred_3_slot_valids_1, + output [40:0] io_out_s3_full_pred_3_targets_0, + output [40:0] io_out_s3_full_pred_3_targets_1, + output [3:0] io_out_s3_full_pred_3_offsets_0, + output [3:0] io_out_s3_full_pred_3_offsets_1, + output [40:0] io_out_s3_full_pred_3_fallThroughAddr, + output io_out_s3_full_pred_3_fallThroughErr, + output io_out_s3_full_pred_3_is_br_sharing, + output io_out_s3_full_pred_3_hit, + output [222:0] io_out_last_stage_meta, + output [3:0] io_out_last_stage_spec_info_ssp, + output [1:0] io_out_last_stage_spec_info_sctr, + output io_out_last_stage_spec_info_TOSW_flag, + output [4:0] io_out_last_stage_spec_info_TOSW_value, + output io_out_last_stage_spec_info_TOSR_flag, + output [4:0] io_out_last_stage_spec_info_TOSR_value, + output io_out_last_stage_spec_info_NOS_flag, + output [4:0] io_out_last_stage_spec_info_NOS_value, + output [40:0] io_out_last_stage_spec_info_topAddr, + output io_out_last_stage_ftb_entry_valid, + output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, + output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, + output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, + output io_out_last_stage_ftb_entry_brSlots_0_sharing, + output io_out_last_stage_ftb_entry_brSlots_0_valid, + output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, + output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, + output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, + output io_out_last_stage_ftb_entry_tailSlot_sharing, + output io_out_last_stage_ftb_entry_tailSlot_valid, + output [3:0] io_out_last_stage_ftb_entry_pftAddr, + output io_out_last_stage_ftb_entry_carry, + output io_out_last_stage_ftb_entry_isCall, + output io_out_last_stage_ftb_entry_isRet, + output io_out_last_stage_ftb_entry_isJalr, + output io_out_last_stage_ftb_entry_last_may_be_rvi_call, + output io_out_last_stage_ftb_entry_always_taken_0, + output io_out_last_stage_ftb_entry_always_taken_1, + input io_ctrl_ubtb_enable, + input io_ctrl_btb_enable, + input io_ctrl_tage_enable, + input io_ctrl_sc_enable, + input io_ctrl_ras_enable, + input io_s0_fire_0, + input io_s0_fire_1, + input io_s0_fire_2, + input io_s0_fire_3, + input io_s1_fire_0, + input io_s1_fire_1, + input io_s1_fire_2, + input io_s1_fire_3, + input io_s2_fire_0, + input io_s2_fire_1, + input io_s2_fire_2, + input io_s2_fire_3, + input io_s3_fire_2, + input io_s3_redirect_2, + output io_s1_ready, + input io_update_valid, + input [40:0] io_update_bits_pc, + input [10:0] io_update_bits_spec_info_folded_hist_hist_17_folded_hist, + input [10:0] io_update_bits_spec_info_folded_hist_hist_16_folded_hist, + input [6:0] io_update_bits_spec_info_folded_hist_hist_15_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, + input [8:0] io_update_bits_spec_info_folded_hist_hist_13_folded_hist, + input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_11_folded_hist, + input [8:0] io_update_bits_spec_info_folded_hist_hist_10_folded_hist, + input [6:0] io_update_bits_spec_info_folded_hist_hist_9_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_8_folded_hist, + input [6:0] io_update_bits_spec_info_folded_hist_hist_7_folded_hist, + input [8:0] io_update_bits_spec_info_folded_hist_hist_6_folded_hist, + input [6:0] io_update_bits_spec_info_folded_hist_hist_5_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, + input [10:0] io_update_bits_spec_info_folded_hist_hist_1_folded_hist, + input io_update_bits_ftb_entry_valid, + input [3:0] io_update_bits_ftb_entry_brSlots_0_offset, + input [11:0] io_update_bits_ftb_entry_brSlots_0_lower, + input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat, + input io_update_bits_ftb_entry_brSlots_0_sharing, + input io_update_bits_ftb_entry_brSlots_0_valid, + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, + input [19:0] io_update_bits_ftb_entry_tailSlot_lower, + input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat, + input io_update_bits_ftb_entry_tailSlot_sharing, + input io_update_bits_ftb_entry_tailSlot_valid, + input [3:0] io_update_bits_ftb_entry_pftAddr, + input io_update_bits_ftb_entry_carry, + input io_update_bits_ftb_entry_isCall, + input io_update_bits_ftb_entry_isRet, + input io_update_bits_ftb_entry_isJalr, + input io_update_bits_ftb_entry_last_may_be_rvi_call, + input io_update_bits_ftb_entry_always_taken_0, + input io_update_bits_ftb_entry_always_taken_1, + input io_update_bits_cfi_idx_valid, + input [3:0] io_update_bits_cfi_idx_bits, + input io_update_bits_br_taken_mask_0, + input io_update_bits_br_taken_mask_1, + input io_update_bits_jmp_taken, + input io_update_bits_mispred_mask_0, + input io_update_bits_mispred_mask_1, + input io_update_bits_mispred_mask_2, + input io_update_bits_old_entry, + input [222:0] io_update_bits_meta, + input [40:0] io_update_bits_full_target, + input io_redirect_valid, + input io_redirect_bits_level, + input [40:0] io_redirect_bits_cfiUpdate_pc, + input io_redirect_bits_cfiUpdate_pd_isRVC, + input io_redirect_bits_cfiUpdate_pd_isCall, + input io_redirect_bits_cfiUpdate_pd_isRet, + input [3:0] io_redirect_bits_cfiUpdate_ssp, + input [1:0] io_redirect_bits_cfiUpdate_sctr, + input io_redirect_bits_cfiUpdate_TOSW_flag, + input [4:0] io_redirect_bits_cfiUpdate_TOSW_value, + input io_redirect_bits_cfiUpdate_TOSR_flag, + input [4:0] io_redirect_bits_cfiUpdate_TOSR_value, + input io_redirect_bits_cfiUpdate_NOS_flag, + input [4:0] io_redirect_bits_cfiUpdate_NOS_value, + output [5:0] io_perf_0_value, + output [5:0] io_perf_1_value, + output [5:0] io_perf_2_value, + output [5:0] io_perf_3_value, + output [5:0] io_perf_4_value, + output [5:0] io_perf_5_value, + output [5:0] io_perf_6_value +); + + wire _ras_io_ctrl_delay_io_out_ras_enable; + wire _ftb_io_ctrl_delay_io_out_btb_enable; + wire _tage_io_ctrl_delay_io_out_tage_enable; + wire _tage_io_ctrl_delay_io_out_sc_enable; + wire _ubtb_io_ctrl_delay_io_out_ubtb_enable; + wire _ittage_io_out_s2_full_pred_0_br_taken_mask_0; + wire _ittage_io_out_s2_full_pred_0_br_taken_mask_1; + wire _ittage_io_out_s2_full_pred_0_slot_valids_0; + wire _ittage_io_out_s2_full_pred_0_slot_valids_1; + wire [40:0] _ittage_io_out_s2_full_pred_0_targets_0; + wire [40:0] _ittage_io_out_s2_full_pred_0_targets_1; + wire [40:0] _ittage_io_out_s2_full_pred_0_jalr_target; + wire [3:0] _ittage_io_out_s2_full_pred_0_offsets_0; + wire [3:0] _ittage_io_out_s2_full_pred_0_offsets_1; + wire [40:0] _ittage_io_out_s2_full_pred_0_fallThroughAddr; + wire _ittage_io_out_s2_full_pred_0_is_br_sharing; + wire _ittage_io_out_s2_full_pred_0_hit; + wire _ittage_io_out_s2_full_pred_1_br_taken_mask_0; + wire _ittage_io_out_s2_full_pred_1_br_taken_mask_1; + wire _ittage_io_out_s2_full_pred_1_slot_valids_0; + wire _ittage_io_out_s2_full_pred_1_slot_valids_1; + wire [40:0] _ittage_io_out_s2_full_pred_1_targets_0; + wire [40:0] _ittage_io_out_s2_full_pred_1_targets_1; + wire [40:0] _ittage_io_out_s2_full_pred_1_jalr_target; + wire [3:0] _ittage_io_out_s2_full_pred_1_offsets_0; + wire [3:0] _ittage_io_out_s2_full_pred_1_offsets_1; + wire [40:0] _ittage_io_out_s2_full_pred_1_fallThroughAddr; + wire _ittage_io_out_s2_full_pred_1_is_br_sharing; + wire _ittage_io_out_s2_full_pred_1_hit; + wire _ittage_io_out_s2_full_pred_2_br_taken_mask_0; + wire _ittage_io_out_s2_full_pred_2_br_taken_mask_1; + wire _ittage_io_out_s2_full_pred_2_slot_valids_0; + wire _ittage_io_out_s2_full_pred_2_slot_valids_1; + wire [40:0] _ittage_io_out_s2_full_pred_2_targets_0; + wire [40:0] _ittage_io_out_s2_full_pred_2_targets_1; + wire [40:0] _ittage_io_out_s2_full_pred_2_jalr_target; + wire [3:0] _ittage_io_out_s2_full_pred_2_offsets_0; + wire [3:0] _ittage_io_out_s2_full_pred_2_offsets_1; + wire [40:0] _ittage_io_out_s2_full_pred_2_fallThroughAddr; + wire _ittage_io_out_s2_full_pred_2_is_jalr; + wire _ittage_io_out_s2_full_pred_2_is_call; + wire _ittage_io_out_s2_full_pred_2_is_ret; + wire _ittage_io_out_s2_full_pred_2_last_may_be_rvi_call; + wire _ittage_io_out_s2_full_pred_2_is_br_sharing; + wire _ittage_io_out_s2_full_pred_2_hit; + wire _ittage_io_out_s2_full_pred_3_br_taken_mask_0; + wire _ittage_io_out_s2_full_pred_3_br_taken_mask_1; + wire _ittage_io_out_s2_full_pred_3_slot_valids_0; + wire _ittage_io_out_s2_full_pred_3_slot_valids_1; + wire [40:0] _ittage_io_out_s2_full_pred_3_targets_0; + wire [40:0] _ittage_io_out_s2_full_pred_3_targets_1; + wire [40:0] _ittage_io_out_s2_full_pred_3_jalr_target; + wire [3:0] _ittage_io_out_s2_full_pred_3_offsets_0; + wire [3:0] _ittage_io_out_s2_full_pred_3_offsets_1; + wire [40:0] _ittage_io_out_s2_full_pred_3_fallThroughAddr; + wire _ittage_io_out_s2_full_pred_3_fallThroughErr; + wire _ittage_io_out_s2_full_pred_3_is_br_sharing; + wire _ittage_io_out_s2_full_pred_3_hit; + wire _ittage_io_out_s3_full_pred_0_br_taken_mask_0; + wire _ittage_io_out_s3_full_pred_0_br_taken_mask_1; + wire _ittage_io_out_s3_full_pred_0_slot_valids_0; + wire _ittage_io_out_s3_full_pred_0_slot_valids_1; + wire [40:0] _ittage_io_out_s3_full_pred_0_targets_0; + wire [40:0] _ittage_io_out_s3_full_pred_0_targets_1; + wire [40:0] _ittage_io_out_s3_full_pred_0_jalr_target; + wire [40:0] _ittage_io_out_s3_full_pred_0_fallThroughAddr; + wire _ittage_io_out_s3_full_pred_0_fallThroughErr; + wire _ittage_io_out_s3_full_pred_0_is_br_sharing; + wire _ittage_io_out_s3_full_pred_0_hit; + wire _ittage_io_out_s3_full_pred_1_br_taken_mask_0; + wire _ittage_io_out_s3_full_pred_1_br_taken_mask_1; + wire _ittage_io_out_s3_full_pred_1_slot_valids_0; + wire _ittage_io_out_s3_full_pred_1_slot_valids_1; + wire [40:0] _ittage_io_out_s3_full_pred_1_targets_0; + wire [40:0] _ittage_io_out_s3_full_pred_1_targets_1; + wire [40:0] _ittage_io_out_s3_full_pred_1_jalr_target; + wire [40:0] _ittage_io_out_s3_full_pred_1_fallThroughAddr; + wire _ittage_io_out_s3_full_pred_1_fallThroughErr; + wire _ittage_io_out_s3_full_pred_1_is_br_sharing; + wire _ittage_io_out_s3_full_pred_1_hit; + wire _ittage_io_out_s3_full_pred_2_br_taken_mask_0; + wire _ittage_io_out_s3_full_pred_2_br_taken_mask_1; + wire _ittage_io_out_s3_full_pred_2_slot_valids_0; + wire _ittage_io_out_s3_full_pred_2_slot_valids_1; + wire [40:0] _ittage_io_out_s3_full_pred_2_targets_0; + wire [40:0] _ittage_io_out_s3_full_pred_2_targets_1; + wire [40:0] _ittage_io_out_s3_full_pred_2_jalr_target; + wire [40:0] _ittage_io_out_s3_full_pred_2_fallThroughAddr; + wire _ittage_io_out_s3_full_pred_2_fallThroughErr; + wire _ittage_io_out_s3_full_pred_2_is_jalr; + wire _ittage_io_out_s3_full_pred_2_is_call; + wire _ittage_io_out_s3_full_pred_2_is_ret; + wire _ittage_io_out_s3_full_pred_2_is_br_sharing; + wire _ittage_io_out_s3_full_pred_2_hit; + wire _ittage_io_out_s3_full_pred_3_br_taken_mask_0; + wire _ittage_io_out_s3_full_pred_3_br_taken_mask_1; + wire _ittage_io_out_s3_full_pred_3_slot_valids_0; + wire _ittage_io_out_s3_full_pred_3_slot_valids_1; + wire [40:0] _ittage_io_out_s3_full_pred_3_targets_0; + wire [40:0] _ittage_io_out_s3_full_pred_3_targets_1; + wire [40:0] _ittage_io_out_s3_full_pred_3_jalr_target; + wire [3:0] _ittage_io_out_s3_full_pred_3_offsets_0; + wire [3:0] _ittage_io_out_s3_full_pred_3_offsets_1; + wire [40:0] _ittage_io_out_s3_full_pred_3_fallThroughAddr; + wire _ittage_io_out_s3_full_pred_3_fallThroughErr; + wire _ittage_io_out_s3_full_pred_3_is_br_sharing; + wire _ittage_io_out_s3_full_pred_3_hit; + wire [222:0] _ittage_io_out_last_stage_meta; + wire _ittage_io_out_last_stage_ftb_entry_valid; + wire [3:0] _ittage_io_out_last_stage_ftb_entry_brSlots_0_offset; + wire [11:0] _ittage_io_out_last_stage_ftb_entry_brSlots_0_lower; + wire [1:0] _ittage_io_out_last_stage_ftb_entry_brSlots_0_tarStat; + wire _ittage_io_out_last_stage_ftb_entry_brSlots_0_sharing; + wire _ittage_io_out_last_stage_ftb_entry_brSlots_0_valid; + wire [3:0] _ittage_io_out_last_stage_ftb_entry_tailSlot_offset; + wire [19:0] _ittage_io_out_last_stage_ftb_entry_tailSlot_lower; + wire [1:0] _ittage_io_out_last_stage_ftb_entry_tailSlot_tarStat; + wire _ittage_io_out_last_stage_ftb_entry_tailSlot_sharing; + wire _ittage_io_out_last_stage_ftb_entry_tailSlot_valid; + wire [3:0] _ittage_io_out_last_stage_ftb_entry_pftAddr; + wire _ittage_io_out_last_stage_ftb_entry_carry; + wire _ittage_io_out_last_stage_ftb_entry_isCall; + wire _ittage_io_out_last_stage_ftb_entry_isRet; + wire _ittage_io_out_last_stage_ftb_entry_isJalr; + wire _ittage_io_out_last_stage_ftb_entry_last_may_be_rvi_call; + wire _ittage_io_out_last_stage_ftb_entry_always_taken_0; + wire _ittage_io_out_last_stage_ftb_entry_always_taken_1; + wire [222:0] _ras_io_out_last_stage_meta; + wire _tage_io_out_s2_full_pred_0_br_taken_mask_0; + wire _tage_io_out_s2_full_pred_0_br_taken_mask_1; + wire _tage_io_out_s2_full_pred_1_br_taken_mask_0; + wire _tage_io_out_s2_full_pred_1_br_taken_mask_1; + wire _tage_io_out_s2_full_pred_2_br_taken_mask_0; + wire _tage_io_out_s2_full_pred_2_br_taken_mask_1; + wire _tage_io_out_s2_full_pred_3_br_taken_mask_0; + wire _tage_io_out_s2_full_pred_3_br_taken_mask_1; + wire _tage_io_out_s3_full_pred_0_br_taken_mask_0; + wire _tage_io_out_s3_full_pred_0_br_taken_mask_1; + wire _tage_io_out_s3_full_pred_1_br_taken_mask_0; + wire _tage_io_out_s3_full_pred_1_br_taken_mask_1; + wire _tage_io_out_s3_full_pred_2_br_taken_mask_0; + wire _tage_io_out_s3_full_pred_2_br_taken_mask_1; + wire _tage_io_out_s3_full_pred_3_br_taken_mask_0; + wire _tage_io_out_s3_full_pred_3_br_taken_mask_1; + wire [222:0] _tage_io_out_last_stage_meta; + wire _tage_io_s1_ready; + wire [5:0] _tage_io_perf_0_value; + wire [5:0] _tage_io_perf_1_value; + wire [5:0] _tage_io_perf_2_value; + wire [222:0] _ubtb_io_out_last_stage_meta; + wire [5:0] _ubtb_io_perf_0_value; + wire [5:0] _ubtb_io_perf_1_value; + wire _ftb_io_out_s2_full_pred_0_br_taken_mask_0; + wire _ftb_io_out_s2_full_pred_0_br_taken_mask_1; + wire _ftb_io_out_s2_full_pred_0_slot_valids_0; + wire _ftb_io_out_s2_full_pred_0_slot_valids_1; + wire [40:0] _ftb_io_out_s2_full_pred_0_targets_0; + wire [40:0] _ftb_io_out_s2_full_pred_0_targets_1; + wire [40:0] _ftb_io_out_s2_full_pred_0_jalr_target; + wire [3:0] _ftb_io_out_s2_full_pred_0_offsets_0; + wire [3:0] _ftb_io_out_s2_full_pred_0_offsets_1; + wire [40:0] _ftb_io_out_s2_full_pred_0_fallThroughAddr; + wire _ftb_io_out_s2_full_pred_0_is_br_sharing; + wire _ftb_io_out_s2_full_pred_0_hit; + wire _ftb_io_out_s2_full_pred_1_br_taken_mask_0; + wire _ftb_io_out_s2_full_pred_1_br_taken_mask_1; + wire _ftb_io_out_s2_full_pred_1_slot_valids_0; + wire _ftb_io_out_s2_full_pred_1_slot_valids_1; + wire [40:0] _ftb_io_out_s2_full_pred_1_targets_0; + wire [40:0] _ftb_io_out_s2_full_pred_1_targets_1; + wire [40:0] _ftb_io_out_s2_full_pred_1_jalr_target; + wire [3:0] _ftb_io_out_s2_full_pred_1_offsets_0; + wire [3:0] _ftb_io_out_s2_full_pred_1_offsets_1; + wire [40:0] _ftb_io_out_s2_full_pred_1_fallThroughAddr; + wire _ftb_io_out_s2_full_pred_1_is_br_sharing; + wire _ftb_io_out_s2_full_pred_1_hit; + wire _ftb_io_out_s2_full_pred_2_br_taken_mask_0; + wire _ftb_io_out_s2_full_pred_2_br_taken_mask_1; + wire _ftb_io_out_s2_full_pred_2_slot_valids_0; + wire _ftb_io_out_s2_full_pred_2_slot_valids_1; + wire [40:0] _ftb_io_out_s2_full_pred_2_targets_0; + wire [40:0] _ftb_io_out_s2_full_pred_2_targets_1; + wire [40:0] _ftb_io_out_s2_full_pred_2_jalr_target; + wire [3:0] _ftb_io_out_s2_full_pred_2_offsets_0; + wire [3:0] _ftb_io_out_s2_full_pred_2_offsets_1; + wire [40:0] _ftb_io_out_s2_full_pred_2_fallThroughAddr; + wire _ftb_io_out_s2_full_pred_2_is_jalr; + wire _ftb_io_out_s2_full_pred_2_is_call; + wire _ftb_io_out_s2_full_pred_2_is_ret; + wire _ftb_io_out_s2_full_pred_2_last_may_be_rvi_call; + wire _ftb_io_out_s2_full_pred_2_is_br_sharing; + wire _ftb_io_out_s2_full_pred_2_hit; + wire _ftb_io_out_s2_full_pred_3_br_taken_mask_0; + wire _ftb_io_out_s2_full_pred_3_br_taken_mask_1; + wire _ftb_io_out_s2_full_pred_3_slot_valids_0; + wire _ftb_io_out_s2_full_pred_3_slot_valids_1; + wire [40:0] _ftb_io_out_s2_full_pred_3_targets_0; + wire [40:0] _ftb_io_out_s2_full_pred_3_targets_1; + wire [40:0] _ftb_io_out_s2_full_pred_3_jalr_target; + wire [3:0] _ftb_io_out_s2_full_pred_3_offsets_0; + wire [3:0] _ftb_io_out_s2_full_pred_3_offsets_1; + wire [40:0] _ftb_io_out_s2_full_pred_3_fallThroughAddr; + wire _ftb_io_out_s2_full_pred_3_fallThroughErr; + wire _ftb_io_out_s2_full_pred_3_is_br_sharing; + wire _ftb_io_out_s2_full_pred_3_hit; + wire _ftb_io_out_s3_full_pred_0_br_taken_mask_0; + wire _ftb_io_out_s3_full_pred_0_br_taken_mask_1; + wire _ftb_io_out_s3_full_pred_0_slot_valids_0; + wire _ftb_io_out_s3_full_pred_0_slot_valids_1; + wire [40:0] _ftb_io_out_s3_full_pred_0_targets_0; + wire [40:0] _ftb_io_out_s3_full_pred_0_targets_1; + wire [40:0] _ftb_io_out_s3_full_pred_0_jalr_target; + wire [40:0] _ftb_io_out_s3_full_pred_0_fallThroughAddr; + wire _ftb_io_out_s3_full_pred_0_fallThroughErr; + wire _ftb_io_out_s3_full_pred_0_is_br_sharing; + wire _ftb_io_out_s3_full_pred_0_hit; + wire _ftb_io_out_s3_full_pred_1_br_taken_mask_0; + wire _ftb_io_out_s3_full_pred_1_br_taken_mask_1; + wire _ftb_io_out_s3_full_pred_1_slot_valids_0; + wire _ftb_io_out_s3_full_pred_1_slot_valids_1; + wire [40:0] _ftb_io_out_s3_full_pred_1_targets_0; + wire [40:0] _ftb_io_out_s3_full_pred_1_targets_1; + wire [40:0] _ftb_io_out_s3_full_pred_1_jalr_target; + wire [40:0] _ftb_io_out_s3_full_pred_1_fallThroughAddr; + wire _ftb_io_out_s3_full_pred_1_fallThroughErr; + wire _ftb_io_out_s3_full_pred_1_is_br_sharing; + wire _ftb_io_out_s3_full_pred_1_hit; + wire _ftb_io_out_s3_full_pred_2_br_taken_mask_0; + wire _ftb_io_out_s3_full_pred_2_br_taken_mask_1; + wire _ftb_io_out_s3_full_pred_2_slot_valids_0; + wire _ftb_io_out_s3_full_pred_2_slot_valids_1; + wire [40:0] _ftb_io_out_s3_full_pred_2_targets_0; + wire [40:0] _ftb_io_out_s3_full_pred_2_targets_1; + wire [40:0] _ftb_io_out_s3_full_pred_2_jalr_target; + wire [40:0] _ftb_io_out_s3_full_pred_2_fallThroughAddr; + wire _ftb_io_out_s3_full_pred_2_fallThroughErr; + wire _ftb_io_out_s3_full_pred_2_is_jalr; + wire _ftb_io_out_s3_full_pred_2_is_call; + wire _ftb_io_out_s3_full_pred_2_is_ret; + wire _ftb_io_out_s3_full_pred_2_is_br_sharing; + wire _ftb_io_out_s3_full_pred_2_hit; + wire _ftb_io_out_s3_full_pred_3_br_taken_mask_0; + wire _ftb_io_out_s3_full_pred_3_br_taken_mask_1; + wire _ftb_io_out_s3_full_pred_3_slot_valids_0; + wire _ftb_io_out_s3_full_pred_3_slot_valids_1; + wire [40:0] _ftb_io_out_s3_full_pred_3_targets_0; + wire [40:0] _ftb_io_out_s3_full_pred_3_targets_1; + wire [40:0] _ftb_io_out_s3_full_pred_3_jalr_target; + wire [3:0] _ftb_io_out_s3_full_pred_3_offsets_0; + wire [3:0] _ftb_io_out_s3_full_pred_3_offsets_1; + wire [40:0] _ftb_io_out_s3_full_pred_3_fallThroughAddr; + wire _ftb_io_out_s3_full_pred_3_fallThroughErr; + wire _ftb_io_out_s3_full_pred_3_is_br_sharing; + wire _ftb_io_out_s3_full_pred_3_hit; + wire [222:0] _ftb_io_out_last_stage_meta; + wire _ftb_io_out_last_stage_ftb_entry_valid; + wire [3:0] _ftb_io_out_last_stage_ftb_entry_brSlots_0_offset; + wire [11:0] _ftb_io_out_last_stage_ftb_entry_brSlots_0_lower; + wire [1:0] _ftb_io_out_last_stage_ftb_entry_brSlots_0_tarStat; + wire _ftb_io_out_last_stage_ftb_entry_brSlots_0_sharing; + wire _ftb_io_out_last_stage_ftb_entry_brSlots_0_valid; + wire [3:0] _ftb_io_out_last_stage_ftb_entry_tailSlot_offset; + wire [19:0] _ftb_io_out_last_stage_ftb_entry_tailSlot_lower; + wire [1:0] _ftb_io_out_last_stage_ftb_entry_tailSlot_tarStat; + wire _ftb_io_out_last_stage_ftb_entry_tailSlot_sharing; + wire _ftb_io_out_last_stage_ftb_entry_tailSlot_valid; + wire [3:0] _ftb_io_out_last_stage_ftb_entry_pftAddr; + wire _ftb_io_out_last_stage_ftb_entry_carry; + wire _ftb_io_out_last_stage_ftb_entry_isCall; + wire _ftb_io_out_last_stage_ftb_entry_isRet; + wire _ftb_io_out_last_stage_ftb_entry_isJalr; + wire _ftb_io_out_last_stage_ftb_entry_last_may_be_rvi_call; + wire _ftb_io_out_last_stage_ftb_entry_always_taken_0; + wire _ftb_io_out_last_stage_ftb_entry_always_taken_1; + wire _ftb_io_s1_ready; + wire [5:0] _ftb_io_perf_0_value; + wire [5:0] _ftb_io_perf_1_value; + reg [5:0] io_perf_0_value_REG; + reg [5:0] io_perf_0_value_REG_1; + reg [5:0] io_perf_1_value_REG; + reg [5:0] io_perf_1_value_REG_1; + reg [5:0] io_perf_2_value_REG; + reg [5:0] io_perf_2_value_REG_1; + reg [5:0] io_perf_3_value_REG; + reg [5:0] io_perf_3_value_REG_1; + reg [5:0] io_perf_4_value_REG; + reg [5:0] io_perf_4_value_REG_1; + reg [5:0] io_perf_5_value_REG; + reg [5:0] io_perf_5_value_REG_1; + reg [5:0] io_perf_6_value_REG; + reg [5:0] io_perf_6_value_REG_1; + always @(posedge clock) begin + io_perf_0_value_REG <= _ubtb_io_perf_0_value; + io_perf_0_value_REG_1 <= io_perf_0_value_REG; + io_perf_1_value_REG <= _ubtb_io_perf_1_value; + io_perf_1_value_REG_1 <= io_perf_1_value_REG; + io_perf_2_value_REG <= _tage_io_perf_0_value; + io_perf_2_value_REG_1 <= io_perf_2_value_REG; + io_perf_3_value_REG <= _tage_io_perf_1_value; + io_perf_3_value_REG_1 <= io_perf_3_value_REG; + io_perf_4_value_REG <= _tage_io_perf_2_value; + io_perf_4_value_REG_1 <= io_perf_4_value_REG; + io_perf_5_value_REG <= _ftb_io_perf_0_value; + io_perf_5_value_REG_1 <= io_perf_5_value_REG; + io_perf_6_value_REG <= _ftb_io_perf_1_value; + io_perf_6_value_REG_1 <= io_perf_6_value_REG; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:18]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [4:0] i = 5'h0; i < 5'h13; i += 5'h1) begin + _RANDOM[i] = `RANDOM; + end + io_perf_0_value_REG = _RANDOM[5'hF][19:14]; + io_perf_0_value_REG_1 = _RANDOM[5'hF][25:20]; + io_perf_1_value_REG = _RANDOM[5'hF][31:26]; + io_perf_1_value_REG_1 = _RANDOM[5'h10][5:0]; + io_perf_2_value_REG = _RANDOM[5'h10][11:6]; + io_perf_2_value_REG_1 = _RANDOM[5'h10][17:12]; + io_perf_3_value_REG = _RANDOM[5'h10][23:18]; + io_perf_3_value_REG_1 = _RANDOM[5'h10][29:24]; + io_perf_4_value_REG = {_RANDOM[5'h10][31:30], _RANDOM[5'h11][3:0]}; + io_perf_4_value_REG_1 = _RANDOM[5'h11][9:4]; + io_perf_5_value_REG = _RANDOM[5'h11][15:10]; + io_perf_5_value_REG_1 = _RANDOM[5'h11][21:16]; + io_perf_6_value_REG = _RANDOM[5'h11][27:22]; + io_perf_6_value_REG_1 = {_RANDOM[5'h11][31:28], _RANDOM[5'h12][1:0]}; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FTB ftb ( + .clock (clock), + .reset (reset), + .io_reset_vector (io_reset_vector), + .io_in_bits_s0_pc_0 (io_in_bits_s0_pc_0), + .io_in_bits_s0_pc_1 (io_in_bits_s0_pc_1), + .io_in_bits_s0_pc_2 (io_in_bits_s0_pc_2), + .io_in_bits_s0_pc_3 (io_in_bits_s0_pc_3), + .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 + (_tage_io_out_s2_full_pred_0_br_taken_mask_0), + .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 + (_tage_io_out_s2_full_pred_0_br_taken_mask_1), + .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 + (_tage_io_out_s2_full_pred_1_br_taken_mask_0), + .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 + (_tage_io_out_s2_full_pred_1_br_taken_mask_1), + .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 + (_tage_io_out_s2_full_pred_2_br_taken_mask_0), + .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 + (_tage_io_out_s2_full_pred_2_br_taken_mask_1), + .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 + (_tage_io_out_s2_full_pred_3_br_taken_mask_0), + .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 + (_tage_io_out_s2_full_pred_3_br_taken_mask_1), + .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 + (_tage_io_out_s3_full_pred_0_br_taken_mask_0), + .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 + (_tage_io_out_s3_full_pred_0_br_taken_mask_1), + .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 + (_tage_io_out_s3_full_pred_1_br_taken_mask_0), + .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 + (_tage_io_out_s3_full_pred_1_br_taken_mask_1), + .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 + (_tage_io_out_s3_full_pred_2_br_taken_mask_0), + .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 + (_tage_io_out_s3_full_pred_2_br_taken_mask_1), + .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 + (_tage_io_out_s3_full_pred_3_br_taken_mask_0), + .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 + (_tage_io_out_s3_full_pred_3_br_taken_mask_1), + .io_out_s2_full_pred_0_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_0_br_taken_mask_0), + .io_out_s2_full_pred_0_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_0_br_taken_mask_1), + .io_out_s2_full_pred_0_slot_valids_0 + (_ftb_io_out_s2_full_pred_0_slot_valids_0), + .io_out_s2_full_pred_0_slot_valids_1 + (_ftb_io_out_s2_full_pred_0_slot_valids_1), + .io_out_s2_full_pred_0_targets_0 + (_ftb_io_out_s2_full_pred_0_targets_0), + .io_out_s2_full_pred_0_targets_1 + (_ftb_io_out_s2_full_pred_0_targets_1), + .io_out_s2_full_pred_0_jalr_target + (_ftb_io_out_s2_full_pred_0_jalr_target), + .io_out_s2_full_pred_0_offsets_0 + (_ftb_io_out_s2_full_pred_0_offsets_0), + .io_out_s2_full_pred_0_offsets_1 + (_ftb_io_out_s2_full_pred_0_offsets_1), + .io_out_s2_full_pred_0_fallThroughAddr + (_ftb_io_out_s2_full_pred_0_fallThroughAddr), + .io_out_s2_full_pred_0_is_br_sharing + (_ftb_io_out_s2_full_pred_0_is_br_sharing), + .io_out_s2_full_pred_0_hit (_ftb_io_out_s2_full_pred_0_hit), + .io_out_s2_full_pred_1_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_1_br_taken_mask_0), + .io_out_s2_full_pred_1_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_1_br_taken_mask_1), + .io_out_s2_full_pred_1_slot_valids_0 + (_ftb_io_out_s2_full_pred_1_slot_valids_0), + .io_out_s2_full_pred_1_slot_valids_1 + (_ftb_io_out_s2_full_pred_1_slot_valids_1), + .io_out_s2_full_pred_1_targets_0 + (_ftb_io_out_s2_full_pred_1_targets_0), + .io_out_s2_full_pred_1_targets_1 + (_ftb_io_out_s2_full_pred_1_targets_1), + .io_out_s2_full_pred_1_jalr_target + (_ftb_io_out_s2_full_pred_1_jalr_target), + .io_out_s2_full_pred_1_offsets_0 + (_ftb_io_out_s2_full_pred_1_offsets_0), + .io_out_s2_full_pred_1_offsets_1 + (_ftb_io_out_s2_full_pred_1_offsets_1), + .io_out_s2_full_pred_1_fallThroughAddr + (_ftb_io_out_s2_full_pred_1_fallThroughAddr), + .io_out_s2_full_pred_1_is_br_sharing + (_ftb_io_out_s2_full_pred_1_is_br_sharing), + .io_out_s2_full_pred_1_hit (_ftb_io_out_s2_full_pred_1_hit), + .io_out_s2_full_pred_2_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_2_br_taken_mask_0), + .io_out_s2_full_pred_2_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_2_br_taken_mask_1), + .io_out_s2_full_pred_2_slot_valids_0 + (_ftb_io_out_s2_full_pred_2_slot_valids_0), + .io_out_s2_full_pred_2_slot_valids_1 + (_ftb_io_out_s2_full_pred_2_slot_valids_1), + .io_out_s2_full_pred_2_targets_0 + (_ftb_io_out_s2_full_pred_2_targets_0), + .io_out_s2_full_pred_2_targets_1 + (_ftb_io_out_s2_full_pred_2_targets_1), + .io_out_s2_full_pred_2_jalr_target + (_ftb_io_out_s2_full_pred_2_jalr_target), + .io_out_s2_full_pred_2_offsets_0 + (_ftb_io_out_s2_full_pred_2_offsets_0), + .io_out_s2_full_pred_2_offsets_1 + (_ftb_io_out_s2_full_pred_2_offsets_1), + .io_out_s2_full_pred_2_fallThroughAddr + (_ftb_io_out_s2_full_pred_2_fallThroughAddr), + .io_out_s2_full_pred_2_is_jalr + (_ftb_io_out_s2_full_pred_2_is_jalr), + .io_out_s2_full_pred_2_is_call + (_ftb_io_out_s2_full_pred_2_is_call), + .io_out_s2_full_pred_2_is_ret + (_ftb_io_out_s2_full_pred_2_is_ret), + .io_out_s2_full_pred_2_last_may_be_rvi_call + (_ftb_io_out_s2_full_pred_2_last_may_be_rvi_call), + .io_out_s2_full_pred_2_is_br_sharing + (_ftb_io_out_s2_full_pred_2_is_br_sharing), + .io_out_s2_full_pred_2_hit (_ftb_io_out_s2_full_pred_2_hit), + .io_out_s2_full_pred_3_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_3_br_taken_mask_0), + .io_out_s2_full_pred_3_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_3_br_taken_mask_1), + .io_out_s2_full_pred_3_slot_valids_0 + (_ftb_io_out_s2_full_pred_3_slot_valids_0), + .io_out_s2_full_pred_3_slot_valids_1 + (_ftb_io_out_s2_full_pred_3_slot_valids_1), + .io_out_s2_full_pred_3_targets_0 + (_ftb_io_out_s2_full_pred_3_targets_0), + .io_out_s2_full_pred_3_targets_1 + (_ftb_io_out_s2_full_pred_3_targets_1), + .io_out_s2_full_pred_3_jalr_target + (_ftb_io_out_s2_full_pred_3_jalr_target), + .io_out_s2_full_pred_3_offsets_0 + (_ftb_io_out_s2_full_pred_3_offsets_0), + .io_out_s2_full_pred_3_offsets_1 + (_ftb_io_out_s2_full_pred_3_offsets_1), + .io_out_s2_full_pred_3_fallThroughAddr + (_ftb_io_out_s2_full_pred_3_fallThroughAddr), + .io_out_s2_full_pred_3_fallThroughErr + (_ftb_io_out_s2_full_pred_3_fallThroughErr), + .io_out_s2_full_pred_3_is_br_sharing + (_ftb_io_out_s2_full_pred_3_is_br_sharing), + .io_out_s2_full_pred_3_hit (_ftb_io_out_s2_full_pred_3_hit), + .io_out_s3_full_pred_0_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_0_br_taken_mask_0), + .io_out_s3_full_pred_0_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_0_br_taken_mask_1), + .io_out_s3_full_pred_0_slot_valids_0 + (_ftb_io_out_s3_full_pred_0_slot_valids_0), + .io_out_s3_full_pred_0_slot_valids_1 + (_ftb_io_out_s3_full_pred_0_slot_valids_1), + .io_out_s3_full_pred_0_targets_0 + (_ftb_io_out_s3_full_pred_0_targets_0), + .io_out_s3_full_pred_0_targets_1 + (_ftb_io_out_s3_full_pred_0_targets_1), + .io_out_s3_full_pred_0_jalr_target + (_ftb_io_out_s3_full_pred_0_jalr_target), + .io_out_s3_full_pred_0_fallThroughAddr + (_ftb_io_out_s3_full_pred_0_fallThroughAddr), + .io_out_s3_full_pred_0_fallThroughErr + (_ftb_io_out_s3_full_pred_0_fallThroughErr), + .io_out_s3_full_pred_0_is_br_sharing + (_ftb_io_out_s3_full_pred_0_is_br_sharing), + .io_out_s3_full_pred_0_hit (_ftb_io_out_s3_full_pred_0_hit), + .io_out_s3_full_pred_1_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_1_br_taken_mask_0), + .io_out_s3_full_pred_1_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_1_br_taken_mask_1), + .io_out_s3_full_pred_1_slot_valids_0 + (_ftb_io_out_s3_full_pred_1_slot_valids_0), + .io_out_s3_full_pred_1_slot_valids_1 + (_ftb_io_out_s3_full_pred_1_slot_valids_1), + .io_out_s3_full_pred_1_targets_0 + (_ftb_io_out_s3_full_pred_1_targets_0), + .io_out_s3_full_pred_1_targets_1 + (_ftb_io_out_s3_full_pred_1_targets_1), + .io_out_s3_full_pred_1_jalr_target + (_ftb_io_out_s3_full_pred_1_jalr_target), + .io_out_s3_full_pred_1_fallThroughAddr + (_ftb_io_out_s3_full_pred_1_fallThroughAddr), + .io_out_s3_full_pred_1_fallThroughErr + (_ftb_io_out_s3_full_pred_1_fallThroughErr), + .io_out_s3_full_pred_1_is_br_sharing + (_ftb_io_out_s3_full_pred_1_is_br_sharing), + .io_out_s3_full_pred_1_hit (_ftb_io_out_s3_full_pred_1_hit), + .io_out_s3_full_pred_2_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_2_br_taken_mask_0), + .io_out_s3_full_pred_2_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_2_br_taken_mask_1), + .io_out_s3_full_pred_2_slot_valids_0 + (_ftb_io_out_s3_full_pred_2_slot_valids_0), + .io_out_s3_full_pred_2_slot_valids_1 + (_ftb_io_out_s3_full_pred_2_slot_valids_1), + .io_out_s3_full_pred_2_targets_0 + (_ftb_io_out_s3_full_pred_2_targets_0), + .io_out_s3_full_pred_2_targets_1 + (_ftb_io_out_s3_full_pred_2_targets_1), + .io_out_s3_full_pred_2_jalr_target + (_ftb_io_out_s3_full_pred_2_jalr_target), + .io_out_s3_full_pred_2_fallThroughAddr + (_ftb_io_out_s3_full_pred_2_fallThroughAddr), + .io_out_s3_full_pred_2_fallThroughErr + (_ftb_io_out_s3_full_pred_2_fallThroughErr), + .io_out_s3_full_pred_2_is_jalr + (_ftb_io_out_s3_full_pred_2_is_jalr), + .io_out_s3_full_pred_2_is_call + (_ftb_io_out_s3_full_pred_2_is_call), + .io_out_s3_full_pred_2_is_ret + (_ftb_io_out_s3_full_pred_2_is_ret), + .io_out_s3_full_pred_2_is_br_sharing + (_ftb_io_out_s3_full_pred_2_is_br_sharing), + .io_out_s3_full_pred_2_hit (_ftb_io_out_s3_full_pred_2_hit), + .io_out_s3_full_pred_3_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_3_br_taken_mask_0), + .io_out_s3_full_pred_3_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_3_br_taken_mask_1), + .io_out_s3_full_pred_3_slot_valids_0 + (_ftb_io_out_s3_full_pred_3_slot_valids_0), + .io_out_s3_full_pred_3_slot_valids_1 + (_ftb_io_out_s3_full_pred_3_slot_valids_1), + .io_out_s3_full_pred_3_targets_0 + (_ftb_io_out_s3_full_pred_3_targets_0), + .io_out_s3_full_pred_3_targets_1 + (_ftb_io_out_s3_full_pred_3_targets_1), + .io_out_s3_full_pred_3_jalr_target + (_ftb_io_out_s3_full_pred_3_jalr_target), + .io_out_s3_full_pred_3_offsets_0 + (_ftb_io_out_s3_full_pred_3_offsets_0), + .io_out_s3_full_pred_3_offsets_1 + (_ftb_io_out_s3_full_pred_3_offsets_1), + .io_out_s3_full_pred_3_fallThroughAddr + (_ftb_io_out_s3_full_pred_3_fallThroughAddr), + .io_out_s3_full_pred_3_fallThroughErr + (_ftb_io_out_s3_full_pred_3_fallThroughErr), + .io_out_s3_full_pred_3_is_br_sharing + (_ftb_io_out_s3_full_pred_3_is_br_sharing), + .io_out_s3_full_pred_3_hit (_ftb_io_out_s3_full_pred_3_hit), + .io_out_last_stage_meta (_ftb_io_out_last_stage_meta), + .io_out_last_stage_ftb_entry_valid + (_ftb_io_out_last_stage_ftb_entry_valid), + .io_out_last_stage_ftb_entry_brSlots_0_offset + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_offset), + .io_out_last_stage_ftb_entry_brSlots_0_lower + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_lower), + .io_out_last_stage_ftb_entry_brSlots_0_tarStat + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_tarStat), + .io_out_last_stage_ftb_entry_brSlots_0_sharing + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_sharing), + .io_out_last_stage_ftb_entry_brSlots_0_valid + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_valid), + .io_out_last_stage_ftb_entry_tailSlot_offset + (_ftb_io_out_last_stage_ftb_entry_tailSlot_offset), + .io_out_last_stage_ftb_entry_tailSlot_lower + (_ftb_io_out_last_stage_ftb_entry_tailSlot_lower), + .io_out_last_stage_ftb_entry_tailSlot_tarStat + (_ftb_io_out_last_stage_ftb_entry_tailSlot_tarStat), + .io_out_last_stage_ftb_entry_tailSlot_sharing + (_ftb_io_out_last_stage_ftb_entry_tailSlot_sharing), + .io_out_last_stage_ftb_entry_tailSlot_valid + (_ftb_io_out_last_stage_ftb_entry_tailSlot_valid), + .io_out_last_stage_ftb_entry_pftAddr + (_ftb_io_out_last_stage_ftb_entry_pftAddr), + .io_out_last_stage_ftb_entry_carry + (_ftb_io_out_last_stage_ftb_entry_carry), + .io_out_last_stage_ftb_entry_isCall + (_ftb_io_out_last_stage_ftb_entry_isCall), + .io_out_last_stage_ftb_entry_isRet + (_ftb_io_out_last_stage_ftb_entry_isRet), + .io_out_last_stage_ftb_entry_isJalr + (_ftb_io_out_last_stage_ftb_entry_isJalr), + .io_out_last_stage_ftb_entry_last_may_be_rvi_call + (_ftb_io_out_last_stage_ftb_entry_last_may_be_rvi_call), + .io_out_last_stage_ftb_entry_always_taken_0 + (_ftb_io_out_last_stage_ftb_entry_always_taken_0), + .io_out_last_stage_ftb_entry_always_taken_1 + (_ftb_io_out_last_stage_ftb_entry_always_taken_1), + .io_ctrl_btb_enable + (_ftb_io_ctrl_delay_io_out_btb_enable), + .io_s0_fire_0 (io_s0_fire_0), + .io_s0_fire_1 (io_s0_fire_1), + .io_s0_fire_2 (io_s0_fire_2), + .io_s0_fire_3 (io_s0_fire_3), + .io_s1_fire_0 (io_s1_fire_0), + .io_s1_fire_1 (io_s1_fire_1), + .io_s1_fire_2 (io_s1_fire_2), + .io_s1_fire_3 (io_s1_fire_3), + .io_s2_fire_0 (io_s2_fire_0), + .io_s2_fire_1 (io_s2_fire_1), + .io_s2_fire_2 (io_s2_fire_2), + .io_s2_fire_3 (io_s2_fire_3), + .io_s1_ready (_ftb_io_s1_ready), + .io_update_valid (io_update_valid), + .io_update_bits_pc (io_update_bits_pc), + .io_update_bits_ftb_entry_valid (io_update_bits_ftb_entry_valid), + .io_update_bits_ftb_entry_brSlots_0_offset + (io_update_bits_ftb_entry_brSlots_0_offset), + .io_update_bits_ftb_entry_brSlots_0_lower + (io_update_bits_ftb_entry_brSlots_0_lower), + .io_update_bits_ftb_entry_brSlots_0_tarStat + (io_update_bits_ftb_entry_brSlots_0_tarStat), + .io_update_bits_ftb_entry_brSlots_0_sharing + (io_update_bits_ftb_entry_brSlots_0_sharing), + .io_update_bits_ftb_entry_brSlots_0_valid + (io_update_bits_ftb_entry_brSlots_0_valid), + .io_update_bits_ftb_entry_tailSlot_offset + (io_update_bits_ftb_entry_tailSlot_offset), + .io_update_bits_ftb_entry_tailSlot_lower + (io_update_bits_ftb_entry_tailSlot_lower), + .io_update_bits_ftb_entry_tailSlot_tarStat + (io_update_bits_ftb_entry_tailSlot_tarStat), + .io_update_bits_ftb_entry_tailSlot_sharing + (io_update_bits_ftb_entry_tailSlot_sharing), + .io_update_bits_ftb_entry_tailSlot_valid + (io_update_bits_ftb_entry_tailSlot_valid), + .io_update_bits_ftb_entry_pftAddr + (io_update_bits_ftb_entry_pftAddr), + .io_update_bits_ftb_entry_carry (io_update_bits_ftb_entry_carry), + .io_update_bits_ftb_entry_isCall + (io_update_bits_ftb_entry_isCall), + .io_update_bits_ftb_entry_isRet (io_update_bits_ftb_entry_isRet), + .io_update_bits_ftb_entry_isJalr + (io_update_bits_ftb_entry_isJalr), + .io_update_bits_ftb_entry_last_may_be_rvi_call + (io_update_bits_ftb_entry_last_may_be_rvi_call), + .io_update_bits_ftb_entry_always_taken_0 + (io_update_bits_ftb_entry_always_taken_0), + .io_update_bits_ftb_entry_always_taken_1 + (io_update_bits_ftb_entry_always_taken_1), + .io_update_bits_old_entry (io_update_bits_old_entry), + .io_update_bits_meta + ({126'h0, io_update_bits_meta[222:126]}), + .io_perf_0_value (_ftb_io_perf_0_value), + .io_perf_1_value (_ftb_io_perf_1_value) + ); + FauFTB ubtb ( + .clock (clock), + .reset (reset), + .io_reset_vector (io_reset_vector), + .io_in_bits_s0_pc_0 (io_in_bits_s0_pc_0), + .io_in_bits_s0_pc_1 (io_in_bits_s0_pc_1), + .io_in_bits_s0_pc_2 (io_in_bits_s0_pc_2), + .io_in_bits_s0_pc_3 (io_in_bits_s0_pc_3), + .io_out_s1_pc_0 (io_out_s1_pc_0), + .io_out_s1_pc_1 (io_out_s1_pc_1), + .io_out_s1_pc_2 (io_out_s1_pc_2), + .io_out_s1_pc_3 (io_out_s1_pc_3), + .io_out_s1_full_pred_0_br_taken_mask_0 (io_out_s1_full_pred_0_br_taken_mask_0), + .io_out_s1_full_pred_0_br_taken_mask_1 (io_out_s1_full_pred_0_br_taken_mask_1), + .io_out_s1_full_pred_0_slot_valids_0 (io_out_s1_full_pred_0_slot_valids_0), + .io_out_s1_full_pred_0_slot_valids_1 (io_out_s1_full_pred_0_slot_valids_1), + .io_out_s1_full_pred_0_targets_0 (io_out_s1_full_pred_0_targets_0), + .io_out_s1_full_pred_0_targets_1 (io_out_s1_full_pred_0_targets_1), + .io_out_s1_full_pred_0_offsets_0 (io_out_s1_full_pred_0_offsets_0), + .io_out_s1_full_pred_0_offsets_1 (io_out_s1_full_pred_0_offsets_1), + .io_out_s1_full_pred_0_fallThroughAddr (io_out_s1_full_pred_0_fallThroughAddr), + .io_out_s1_full_pred_0_is_br_sharing (io_out_s1_full_pred_0_is_br_sharing), + .io_out_s1_full_pred_0_hit (io_out_s1_full_pred_0_hit), + .io_out_s1_full_pred_1_br_taken_mask_0 (io_out_s1_full_pred_1_br_taken_mask_0), + .io_out_s1_full_pred_1_br_taken_mask_1 (io_out_s1_full_pred_1_br_taken_mask_1), + .io_out_s1_full_pred_1_slot_valids_0 (io_out_s1_full_pred_1_slot_valids_0), + .io_out_s1_full_pred_1_slot_valids_1 (io_out_s1_full_pred_1_slot_valids_1), + .io_out_s1_full_pred_1_targets_0 (io_out_s1_full_pred_1_targets_0), + .io_out_s1_full_pred_1_targets_1 (io_out_s1_full_pred_1_targets_1), + .io_out_s1_full_pred_1_offsets_0 (io_out_s1_full_pred_1_offsets_0), + .io_out_s1_full_pred_1_offsets_1 (io_out_s1_full_pred_1_offsets_1), + .io_out_s1_full_pred_1_fallThroughAddr (io_out_s1_full_pred_1_fallThroughAddr), + .io_out_s1_full_pred_1_is_br_sharing (io_out_s1_full_pred_1_is_br_sharing), + .io_out_s1_full_pred_1_hit (io_out_s1_full_pred_1_hit), + .io_out_s1_full_pred_2_br_taken_mask_0 (io_out_s1_full_pred_2_br_taken_mask_0), + .io_out_s1_full_pred_2_br_taken_mask_1 (io_out_s1_full_pred_2_br_taken_mask_1), + .io_out_s1_full_pred_2_slot_valids_0 (io_out_s1_full_pred_2_slot_valids_0), + .io_out_s1_full_pred_2_slot_valids_1 (io_out_s1_full_pred_2_slot_valids_1), + .io_out_s1_full_pred_2_targets_0 (io_out_s1_full_pred_2_targets_0), + .io_out_s1_full_pred_2_targets_1 (io_out_s1_full_pred_2_targets_1), + .io_out_s1_full_pred_2_offsets_0 (io_out_s1_full_pred_2_offsets_0), + .io_out_s1_full_pred_2_offsets_1 (io_out_s1_full_pred_2_offsets_1), + .io_out_s1_full_pred_2_fallThroughAddr (io_out_s1_full_pred_2_fallThroughAddr), + .io_out_s1_full_pred_2_is_br_sharing (io_out_s1_full_pred_2_is_br_sharing), + .io_out_s1_full_pred_2_hit (io_out_s1_full_pred_2_hit), + .io_out_s1_full_pred_3_br_taken_mask_0 (io_out_s1_full_pred_3_br_taken_mask_0), + .io_out_s1_full_pred_3_br_taken_mask_1 (io_out_s1_full_pred_3_br_taken_mask_1), + .io_out_s1_full_pred_3_slot_valids_0 (io_out_s1_full_pred_3_slot_valids_0), + .io_out_s1_full_pred_3_slot_valids_1 (io_out_s1_full_pred_3_slot_valids_1), + .io_out_s1_full_pred_3_targets_0 (io_out_s1_full_pred_3_targets_0), + .io_out_s1_full_pred_3_targets_1 (io_out_s1_full_pred_3_targets_1), + .io_out_s1_full_pred_3_offsets_0 (io_out_s1_full_pred_3_offsets_0), + .io_out_s1_full_pred_3_offsets_1 (io_out_s1_full_pred_3_offsets_1), + .io_out_s1_full_pred_3_fallThroughAddr (io_out_s1_full_pred_3_fallThroughAddr), + .io_out_s1_full_pred_3_fallThroughErr (io_out_s1_full_pred_3_fallThroughErr), + .io_out_s1_full_pred_3_is_br_sharing (io_out_s1_full_pred_3_is_br_sharing), + .io_out_s1_full_pred_3_hit (io_out_s1_full_pred_3_hit), + .io_out_last_stage_meta (_ubtb_io_out_last_stage_meta), + .io_ctrl_ubtb_enable (_ubtb_io_ctrl_delay_io_out_ubtb_enable), + .io_s0_fire_0 (io_s0_fire_0), + .io_s0_fire_1 (io_s0_fire_1), + .io_s0_fire_2 (io_s0_fire_2), + .io_s0_fire_3 (io_s0_fire_3), + .io_s1_fire_0 (io_s1_fire_0), + .io_s2_fire_0 (io_s2_fire_0), + .io_update_valid (io_update_valid), + .io_update_bits_pc (io_update_bits_pc), + .io_update_bits_ftb_entry_brSlots_0_offset + (io_update_bits_ftb_entry_brSlots_0_offset), + .io_update_bits_ftb_entry_brSlots_0_lower + (io_update_bits_ftb_entry_brSlots_0_lower), + .io_update_bits_ftb_entry_brSlots_0_tarStat + (io_update_bits_ftb_entry_brSlots_0_tarStat), + .io_update_bits_ftb_entry_brSlots_0_valid + (io_update_bits_ftb_entry_brSlots_0_valid), + .io_update_bits_ftb_entry_tailSlot_offset + (io_update_bits_ftb_entry_tailSlot_offset), + .io_update_bits_ftb_entry_tailSlot_lower (io_update_bits_ftb_entry_tailSlot_lower), + .io_update_bits_ftb_entry_tailSlot_tarStat + (io_update_bits_ftb_entry_tailSlot_tarStat), + .io_update_bits_ftb_entry_tailSlot_sharing + (io_update_bits_ftb_entry_tailSlot_sharing), + .io_update_bits_ftb_entry_tailSlot_valid (io_update_bits_ftb_entry_tailSlot_valid), + .io_update_bits_ftb_entry_pftAddr (io_update_bits_ftb_entry_pftAddr), + .io_update_bits_ftb_entry_carry (io_update_bits_ftb_entry_carry), + .io_update_bits_ftb_entry_always_taken_0 (io_update_bits_ftb_entry_always_taken_0), + .io_update_bits_ftb_entry_always_taken_1 (io_update_bits_ftb_entry_always_taken_1), + .io_update_bits_br_taken_mask_0 (io_update_bits_br_taken_mask_0), + .io_update_bits_br_taken_mask_1 (io_update_bits_br_taken_mask_1), + .io_update_bits_meta ({217'h0, io_update_bits_meta[222:217]}), + .io_perf_0_value (_ubtb_io_perf_0_value), + .io_perf_1_value (_ubtb_io_perf_1_value) + ); + Tage_SC tage ( + .clock (clock), + .reset (reset), + .io_reset_vector (io_reset_vector), + .io_in_bits_s0_pc_0 (io_in_bits_s0_pc_0), + .io_in_bits_s0_pc_1 (io_in_bits_s0_pc_1), + .io_in_bits_s0_pc_3 (io_in_bits_s0_pc_3), + .io_in_bits_folded_hist_1_hist_17_folded_hist + (io_in_bits_folded_hist_1_hist_17_folded_hist), + .io_in_bits_folded_hist_1_hist_16_folded_hist + (io_in_bits_folded_hist_1_hist_16_folded_hist), + .io_in_bits_folded_hist_1_hist_15_folded_hist + (io_in_bits_folded_hist_1_hist_15_folded_hist), + .io_in_bits_folded_hist_1_hist_14_folded_hist + (io_in_bits_folded_hist_1_hist_14_folded_hist), + .io_in_bits_folded_hist_1_hist_9_folded_hist + (io_in_bits_folded_hist_1_hist_9_folded_hist), + .io_in_bits_folded_hist_1_hist_8_folded_hist + (io_in_bits_folded_hist_1_hist_8_folded_hist), + .io_in_bits_folded_hist_1_hist_7_folded_hist + (io_in_bits_folded_hist_1_hist_7_folded_hist), + .io_in_bits_folded_hist_1_hist_5_folded_hist + (io_in_bits_folded_hist_1_hist_5_folded_hist), + .io_in_bits_folded_hist_1_hist_4_folded_hist + (io_in_bits_folded_hist_1_hist_4_folded_hist), + .io_in_bits_folded_hist_1_hist_3_folded_hist + (io_in_bits_folded_hist_1_hist_3_folded_hist), + .io_in_bits_folded_hist_1_hist_1_folded_hist + (io_in_bits_folded_hist_1_hist_1_folded_hist), + .io_in_bits_folded_hist_3_hist_12_folded_hist + (io_in_bits_folded_hist_3_hist_12_folded_hist), + .io_in_bits_folded_hist_3_hist_11_folded_hist + (io_in_bits_folded_hist_3_hist_11_folded_hist), + .io_in_bits_folded_hist_3_hist_2_folded_hist + (io_in_bits_folded_hist_3_hist_2_folded_hist), + .io_out_s2_full_pred_0_br_taken_mask_0 + (_tage_io_out_s2_full_pred_0_br_taken_mask_0), + .io_out_s2_full_pred_0_br_taken_mask_1 + (_tage_io_out_s2_full_pred_0_br_taken_mask_1), + .io_out_s2_full_pred_1_br_taken_mask_0 + (_tage_io_out_s2_full_pred_1_br_taken_mask_0), + .io_out_s2_full_pred_1_br_taken_mask_1 + (_tage_io_out_s2_full_pred_1_br_taken_mask_1), + .io_out_s2_full_pred_2_br_taken_mask_0 + (_tage_io_out_s2_full_pred_2_br_taken_mask_0), + .io_out_s2_full_pred_2_br_taken_mask_1 + (_tage_io_out_s2_full_pred_2_br_taken_mask_1), + .io_out_s2_full_pred_3_br_taken_mask_0 + (_tage_io_out_s2_full_pred_3_br_taken_mask_0), + .io_out_s2_full_pred_3_br_taken_mask_1 + (_tage_io_out_s2_full_pred_3_br_taken_mask_1), + .io_out_s3_full_pred_0_br_taken_mask_0 + (_tage_io_out_s3_full_pred_0_br_taken_mask_0), + .io_out_s3_full_pred_0_br_taken_mask_1 + (_tage_io_out_s3_full_pred_0_br_taken_mask_1), + .io_out_s3_full_pred_1_br_taken_mask_0 + (_tage_io_out_s3_full_pred_1_br_taken_mask_0), + .io_out_s3_full_pred_1_br_taken_mask_1 + (_tage_io_out_s3_full_pred_1_br_taken_mask_1), + .io_out_s3_full_pred_2_br_taken_mask_0 + (_tage_io_out_s3_full_pred_2_br_taken_mask_0), + .io_out_s3_full_pred_2_br_taken_mask_1 + (_tage_io_out_s3_full_pred_2_br_taken_mask_1), + .io_out_s3_full_pred_3_br_taken_mask_0 + (_tage_io_out_s3_full_pred_3_br_taken_mask_0), + .io_out_s3_full_pred_3_br_taken_mask_1 + (_tage_io_out_s3_full_pred_3_br_taken_mask_1), + .io_out_last_stage_meta + (_tage_io_out_last_stage_meta), + .io_ctrl_tage_enable + (_tage_io_ctrl_delay_io_out_tage_enable), + .io_ctrl_sc_enable + (_tage_io_ctrl_delay_io_out_sc_enable), + .io_s0_fire_0 (io_s0_fire_0), + .io_s0_fire_1 (io_s0_fire_1), + .io_s0_fire_3 (io_s0_fire_3), + .io_s1_fire_0 (io_s1_fire_0), + .io_s1_fire_1 (io_s1_fire_1), + .io_s1_fire_2 (io_s1_fire_2), + .io_s1_fire_3 (io_s1_fire_3), + .io_s2_fire_0 (io_s2_fire_0), + .io_s2_fire_1 (io_s2_fire_1), + .io_s2_fire_2 (io_s2_fire_2), + .io_s2_fire_3 (io_s2_fire_3), + .io_s1_ready (_tage_io_s1_ready), + .io_update_valid (io_update_valid), + .io_update_bits_pc (io_update_bits_pc), + .io_update_bits_spec_info_folded_hist_hist_17_folded_hist + (io_update_bits_spec_info_folded_hist_hist_17_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_16_folded_hist + (io_update_bits_spec_info_folded_hist_hist_16_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_15_folded_hist + (io_update_bits_spec_info_folded_hist_hist_15_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_14_folded_hist + (io_update_bits_spec_info_folded_hist_hist_14_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_12_folded_hist + (io_update_bits_spec_info_folded_hist_hist_12_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_11_folded_hist + (io_update_bits_spec_info_folded_hist_hist_11_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_9_folded_hist + (io_update_bits_spec_info_folded_hist_hist_9_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_8_folded_hist + (io_update_bits_spec_info_folded_hist_hist_8_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_7_folded_hist + (io_update_bits_spec_info_folded_hist_hist_7_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_5_folded_hist + (io_update_bits_spec_info_folded_hist_hist_5_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_4_folded_hist + (io_update_bits_spec_info_folded_hist_hist_4_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_3_folded_hist + (io_update_bits_spec_info_folded_hist_hist_3_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_2_folded_hist + (io_update_bits_spec_info_folded_hist_hist_2_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_1_folded_hist + (io_update_bits_spec_info_folded_hist_hist_1_folded_hist), + .io_update_bits_ftb_entry_brSlots_0_valid + (io_update_bits_ftb_entry_brSlots_0_valid), + .io_update_bits_ftb_entry_tailSlot_sharing + (io_update_bits_ftb_entry_tailSlot_sharing), + .io_update_bits_ftb_entry_tailSlot_valid + (io_update_bits_ftb_entry_tailSlot_valid), + .io_update_bits_ftb_entry_always_taken_0 + (io_update_bits_ftb_entry_always_taken_0), + .io_update_bits_ftb_entry_always_taken_1 + (io_update_bits_ftb_entry_always_taken_1), + .io_update_bits_br_taken_mask_0 + (io_update_bits_br_taken_mask_0), + .io_update_bits_br_taken_mask_1 + (io_update_bits_br_taken_mask_1), + .io_update_bits_mispred_mask_0 + (io_update_bits_mispred_mask_0), + .io_update_bits_mispred_mask_1 + (io_update_bits_mispred_mask_1), + .io_update_bits_meta + ({129'h0, io_update_bits_meta[222:129]}), + .io_perf_0_value (_tage_io_perf_0_value), + .io_perf_1_value (_tage_io_perf_1_value), + .io_perf_2_value (_tage_io_perf_2_value) + ); + RAS ras ( + .clock (clock), + .reset (reset), + .io_reset_vector (io_reset_vector), + .io_in_bits_s0_pc_0 (io_in_bits_s0_pc_0), + .io_in_bits_s0_pc_1 (io_in_bits_s0_pc_1), + .io_in_bits_s0_pc_2 (io_in_bits_s0_pc_2), + .io_in_bits_s0_pc_3 (io_in_bits_s0_pc_3), + .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_0_br_taken_mask_0), + .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_0_br_taken_mask_1), + .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0 + (_ittage_io_out_s2_full_pred_0_slot_valids_0), + .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1 + (_ittage_io_out_s2_full_pred_0_slot_valids_1), + .io_in_bits_resp_in_0_s2_full_pred_0_targets_0 + (_ittage_io_out_s2_full_pred_0_targets_0), + .io_in_bits_resp_in_0_s2_full_pred_0_targets_1 + (_ittage_io_out_s2_full_pred_0_targets_1), + .io_in_bits_resp_in_0_s2_full_pred_0_jalr_target + (_ittage_io_out_s2_full_pred_0_jalr_target), + .io_in_bits_resp_in_0_s2_full_pred_0_offsets_0 + (_ittage_io_out_s2_full_pred_0_offsets_0), + .io_in_bits_resp_in_0_s2_full_pred_0_offsets_1 + (_ittage_io_out_s2_full_pred_0_offsets_1), + .io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr + (_ittage_io_out_s2_full_pred_0_fallThroughAddr), + .io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing + (_ittage_io_out_s2_full_pred_0_is_br_sharing), + .io_in_bits_resp_in_0_s2_full_pred_0_hit + (_ittage_io_out_s2_full_pred_0_hit), + .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_1_br_taken_mask_0), + .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_1_br_taken_mask_1), + .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0 + (_ittage_io_out_s2_full_pred_1_slot_valids_0), + .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1 + (_ittage_io_out_s2_full_pred_1_slot_valids_1), + .io_in_bits_resp_in_0_s2_full_pred_1_targets_0 + (_ittage_io_out_s2_full_pred_1_targets_0), + .io_in_bits_resp_in_0_s2_full_pred_1_targets_1 + (_ittage_io_out_s2_full_pred_1_targets_1), + .io_in_bits_resp_in_0_s2_full_pred_1_jalr_target + (_ittage_io_out_s2_full_pred_1_jalr_target), + .io_in_bits_resp_in_0_s2_full_pred_1_offsets_0 + (_ittage_io_out_s2_full_pred_1_offsets_0), + .io_in_bits_resp_in_0_s2_full_pred_1_offsets_1 + (_ittage_io_out_s2_full_pred_1_offsets_1), + .io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr + (_ittage_io_out_s2_full_pred_1_fallThroughAddr), + .io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing + (_ittage_io_out_s2_full_pred_1_is_br_sharing), + .io_in_bits_resp_in_0_s2_full_pred_1_hit + (_ittage_io_out_s2_full_pred_1_hit), + .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_2_br_taken_mask_0), + .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_2_br_taken_mask_1), + .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0 + (_ittage_io_out_s2_full_pred_2_slot_valids_0), + .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1 + (_ittage_io_out_s2_full_pred_2_slot_valids_1), + .io_in_bits_resp_in_0_s2_full_pred_2_targets_0 + (_ittage_io_out_s2_full_pred_2_targets_0), + .io_in_bits_resp_in_0_s2_full_pred_2_targets_1 + (_ittage_io_out_s2_full_pred_2_targets_1), + .io_in_bits_resp_in_0_s2_full_pred_2_jalr_target + (_ittage_io_out_s2_full_pred_2_jalr_target), + .io_in_bits_resp_in_0_s2_full_pred_2_offsets_0 + (_ittage_io_out_s2_full_pred_2_offsets_0), + .io_in_bits_resp_in_0_s2_full_pred_2_offsets_1 + (_ittage_io_out_s2_full_pred_2_offsets_1), + .io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr + (_ittage_io_out_s2_full_pred_2_fallThroughAddr), + .io_in_bits_resp_in_0_s2_full_pred_2_is_jalr + (_ittage_io_out_s2_full_pred_2_is_jalr), + .io_in_bits_resp_in_0_s2_full_pred_2_is_call + (_ittage_io_out_s2_full_pred_2_is_call), + .io_in_bits_resp_in_0_s2_full_pred_2_is_ret + (_ittage_io_out_s2_full_pred_2_is_ret), + .io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call + (_ittage_io_out_s2_full_pred_2_last_may_be_rvi_call), + .io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing + (_ittage_io_out_s2_full_pred_2_is_br_sharing), + .io_in_bits_resp_in_0_s2_full_pred_2_hit + (_ittage_io_out_s2_full_pred_2_hit), + .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_3_br_taken_mask_0), + .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_3_br_taken_mask_1), + .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0 + (_ittage_io_out_s2_full_pred_3_slot_valids_0), + .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1 + (_ittage_io_out_s2_full_pred_3_slot_valids_1), + .io_in_bits_resp_in_0_s2_full_pred_3_targets_0 + (_ittage_io_out_s2_full_pred_3_targets_0), + .io_in_bits_resp_in_0_s2_full_pred_3_targets_1 + (_ittage_io_out_s2_full_pred_3_targets_1), + .io_in_bits_resp_in_0_s2_full_pred_3_jalr_target + (_ittage_io_out_s2_full_pred_3_jalr_target), + .io_in_bits_resp_in_0_s2_full_pred_3_offsets_0 + (_ittage_io_out_s2_full_pred_3_offsets_0), + .io_in_bits_resp_in_0_s2_full_pred_3_offsets_1 + (_ittage_io_out_s2_full_pred_3_offsets_1), + .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr + (_ittage_io_out_s2_full_pred_3_fallThroughAddr), + .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr + (_ittage_io_out_s2_full_pred_3_fallThroughErr), + .io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing + (_ittage_io_out_s2_full_pred_3_is_br_sharing), + .io_in_bits_resp_in_0_s2_full_pred_3_hit + (_ittage_io_out_s2_full_pred_3_hit), + .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_0_br_taken_mask_0), + .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_0_br_taken_mask_1), + .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0 + (_ittage_io_out_s3_full_pred_0_slot_valids_0), + .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1 + (_ittage_io_out_s3_full_pred_0_slot_valids_1), + .io_in_bits_resp_in_0_s3_full_pred_0_targets_0 + (_ittage_io_out_s3_full_pred_0_targets_0), + .io_in_bits_resp_in_0_s3_full_pred_0_targets_1 + (_ittage_io_out_s3_full_pred_0_targets_1), + .io_in_bits_resp_in_0_s3_full_pred_0_jalr_target + (_ittage_io_out_s3_full_pred_0_jalr_target), + .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr + (_ittage_io_out_s3_full_pred_0_fallThroughAddr), + .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr + (_ittage_io_out_s3_full_pred_0_fallThroughErr), + .io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing + (_ittage_io_out_s3_full_pred_0_is_br_sharing), + .io_in_bits_resp_in_0_s3_full_pred_0_hit + (_ittage_io_out_s3_full_pred_0_hit), + .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_1_br_taken_mask_0), + .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_1_br_taken_mask_1), + .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0 + (_ittage_io_out_s3_full_pred_1_slot_valids_0), + .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1 + (_ittage_io_out_s3_full_pred_1_slot_valids_1), + .io_in_bits_resp_in_0_s3_full_pred_1_targets_0 + (_ittage_io_out_s3_full_pred_1_targets_0), + .io_in_bits_resp_in_0_s3_full_pred_1_targets_1 + (_ittage_io_out_s3_full_pred_1_targets_1), + .io_in_bits_resp_in_0_s3_full_pred_1_jalr_target + (_ittage_io_out_s3_full_pred_1_jalr_target), + .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr + (_ittage_io_out_s3_full_pred_1_fallThroughAddr), + .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr + (_ittage_io_out_s3_full_pred_1_fallThroughErr), + .io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing + (_ittage_io_out_s3_full_pred_1_is_br_sharing), + .io_in_bits_resp_in_0_s3_full_pred_1_hit + (_ittage_io_out_s3_full_pred_1_hit), + .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_2_br_taken_mask_0), + .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_2_br_taken_mask_1), + .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0 + (_ittage_io_out_s3_full_pred_2_slot_valids_0), + .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1 + (_ittage_io_out_s3_full_pred_2_slot_valids_1), + .io_in_bits_resp_in_0_s3_full_pred_2_targets_0 + (_ittage_io_out_s3_full_pred_2_targets_0), + .io_in_bits_resp_in_0_s3_full_pred_2_targets_1 + (_ittage_io_out_s3_full_pred_2_targets_1), + .io_in_bits_resp_in_0_s3_full_pred_2_jalr_target + (_ittage_io_out_s3_full_pred_2_jalr_target), + .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr + (_ittage_io_out_s3_full_pred_2_fallThroughAddr), + .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr + (_ittage_io_out_s3_full_pred_2_fallThroughErr), + .io_in_bits_resp_in_0_s3_full_pred_2_is_jalr + (_ittage_io_out_s3_full_pred_2_is_jalr), + .io_in_bits_resp_in_0_s3_full_pred_2_is_call + (_ittage_io_out_s3_full_pred_2_is_call), + .io_in_bits_resp_in_0_s3_full_pred_2_is_ret + (_ittage_io_out_s3_full_pred_2_is_ret), + .io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing + (_ittage_io_out_s3_full_pred_2_is_br_sharing), + .io_in_bits_resp_in_0_s3_full_pred_2_hit + (_ittage_io_out_s3_full_pred_2_hit), + .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_3_br_taken_mask_0), + .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_3_br_taken_mask_1), + .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0 + (_ittage_io_out_s3_full_pred_3_slot_valids_0), + .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1 + (_ittage_io_out_s3_full_pred_3_slot_valids_1), + .io_in_bits_resp_in_0_s3_full_pred_3_targets_0 + (_ittage_io_out_s3_full_pred_3_targets_0), + .io_in_bits_resp_in_0_s3_full_pred_3_targets_1 + (_ittage_io_out_s3_full_pred_3_targets_1), + .io_in_bits_resp_in_0_s3_full_pred_3_jalr_target + (_ittage_io_out_s3_full_pred_3_jalr_target), + .io_in_bits_resp_in_0_s3_full_pred_3_offsets_0 + (_ittage_io_out_s3_full_pred_3_offsets_0), + .io_in_bits_resp_in_0_s3_full_pred_3_offsets_1 + (_ittage_io_out_s3_full_pred_3_offsets_1), + .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr + (_ittage_io_out_s3_full_pred_3_fallThroughAddr), + .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr + (_ittage_io_out_s3_full_pred_3_fallThroughErr), + .io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing + (_ittage_io_out_s3_full_pred_3_is_br_sharing), + .io_in_bits_resp_in_0_s3_full_pred_3_hit + (_ittage_io_out_s3_full_pred_3_hit), + .io_in_bits_resp_in_0_last_stage_ftb_entry_valid + (_ittage_io_out_last_stage_ftb_entry_valid), + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_offset), + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_lower), + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_tarStat), + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_sharing), + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_valid), + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset + (_ittage_io_out_last_stage_ftb_entry_tailSlot_offset), + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower + (_ittage_io_out_last_stage_ftb_entry_tailSlot_lower), + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat + (_ittage_io_out_last_stage_ftb_entry_tailSlot_tarStat), + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing + (_ittage_io_out_last_stage_ftb_entry_tailSlot_sharing), + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid + (_ittage_io_out_last_stage_ftb_entry_tailSlot_valid), + .io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr + (_ittage_io_out_last_stage_ftb_entry_pftAddr), + .io_in_bits_resp_in_0_last_stage_ftb_entry_carry + (_ittage_io_out_last_stage_ftb_entry_carry), + .io_in_bits_resp_in_0_last_stage_ftb_entry_isCall + (_ittage_io_out_last_stage_ftb_entry_isCall), + .io_in_bits_resp_in_0_last_stage_ftb_entry_isRet + (_ittage_io_out_last_stage_ftb_entry_isRet), + .io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr + (_ittage_io_out_last_stage_ftb_entry_isJalr), + .io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call + (_ittage_io_out_last_stage_ftb_entry_last_may_be_rvi_call), + .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0 + (_ittage_io_out_last_stage_ftb_entry_always_taken_0), + .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1 + (_ittage_io_out_last_stage_ftb_entry_always_taken_1), + .io_out_s2_pc_0 (io_out_s2_pc_0), + .io_out_s2_pc_1 (io_out_s2_pc_1), + .io_out_s2_pc_2 (io_out_s2_pc_2), + .io_out_s2_pc_3 (io_out_s2_pc_3), + .io_out_s2_full_pred_0_br_taken_mask_0 + (io_out_s2_full_pred_0_br_taken_mask_0), + .io_out_s2_full_pred_0_br_taken_mask_1 + (io_out_s2_full_pred_0_br_taken_mask_1), + .io_out_s2_full_pred_0_slot_valids_0 + (io_out_s2_full_pred_0_slot_valids_0), + .io_out_s2_full_pred_0_slot_valids_1 + (io_out_s2_full_pred_0_slot_valids_1), + .io_out_s2_full_pred_0_targets_0 + (io_out_s2_full_pred_0_targets_0), + .io_out_s2_full_pred_0_targets_1 + (io_out_s2_full_pred_0_targets_1), + .io_out_s2_full_pred_0_offsets_0 + (io_out_s2_full_pred_0_offsets_0), + .io_out_s2_full_pred_0_offsets_1 + (io_out_s2_full_pred_0_offsets_1), + .io_out_s2_full_pred_0_fallThroughAddr + (io_out_s2_full_pred_0_fallThroughAddr), + .io_out_s2_full_pred_0_is_br_sharing + (io_out_s2_full_pred_0_is_br_sharing), + .io_out_s2_full_pred_0_hit + (io_out_s2_full_pred_0_hit), + .io_out_s2_full_pred_1_br_taken_mask_0 + (io_out_s2_full_pred_1_br_taken_mask_0), + .io_out_s2_full_pred_1_br_taken_mask_1 + (io_out_s2_full_pred_1_br_taken_mask_1), + .io_out_s2_full_pred_1_slot_valids_0 + (io_out_s2_full_pred_1_slot_valids_0), + .io_out_s2_full_pred_1_slot_valids_1 + (io_out_s2_full_pred_1_slot_valids_1), + .io_out_s2_full_pred_1_targets_0 + (io_out_s2_full_pred_1_targets_0), + .io_out_s2_full_pred_1_targets_1 + (io_out_s2_full_pred_1_targets_1), + .io_out_s2_full_pred_1_offsets_0 + (io_out_s2_full_pred_1_offsets_0), + .io_out_s2_full_pred_1_offsets_1 + (io_out_s2_full_pred_1_offsets_1), + .io_out_s2_full_pred_1_fallThroughAddr + (io_out_s2_full_pred_1_fallThroughAddr), + .io_out_s2_full_pred_1_is_br_sharing + (io_out_s2_full_pred_1_is_br_sharing), + .io_out_s2_full_pred_1_hit + (io_out_s2_full_pred_1_hit), + .io_out_s2_full_pred_2_br_taken_mask_0 + (io_out_s2_full_pred_2_br_taken_mask_0), + .io_out_s2_full_pred_2_br_taken_mask_1 + (io_out_s2_full_pred_2_br_taken_mask_1), + .io_out_s2_full_pred_2_slot_valids_0 + (io_out_s2_full_pred_2_slot_valids_0), + .io_out_s2_full_pred_2_slot_valids_1 + (io_out_s2_full_pred_2_slot_valids_1), + .io_out_s2_full_pred_2_targets_0 + (io_out_s2_full_pred_2_targets_0), + .io_out_s2_full_pred_2_targets_1 + (io_out_s2_full_pred_2_targets_1), + .io_out_s2_full_pred_2_offsets_0 + (io_out_s2_full_pred_2_offsets_0), + .io_out_s2_full_pred_2_offsets_1 + (io_out_s2_full_pred_2_offsets_1), + .io_out_s2_full_pred_2_fallThroughAddr + (io_out_s2_full_pred_2_fallThroughAddr), + .io_out_s2_full_pred_2_is_br_sharing + (io_out_s2_full_pred_2_is_br_sharing), + .io_out_s2_full_pred_2_hit + (io_out_s2_full_pred_2_hit), + .io_out_s2_full_pred_3_br_taken_mask_0 + (io_out_s2_full_pred_3_br_taken_mask_0), + .io_out_s2_full_pred_3_br_taken_mask_1 + (io_out_s2_full_pred_3_br_taken_mask_1), + .io_out_s2_full_pred_3_slot_valids_0 + (io_out_s2_full_pred_3_slot_valids_0), + .io_out_s2_full_pred_3_slot_valids_1 + (io_out_s2_full_pred_3_slot_valids_1), + .io_out_s2_full_pred_3_targets_0 + (io_out_s2_full_pred_3_targets_0), + .io_out_s2_full_pred_3_targets_1 + (io_out_s2_full_pred_3_targets_1), + .io_out_s2_full_pred_3_offsets_0 + (io_out_s2_full_pred_3_offsets_0), + .io_out_s2_full_pred_3_offsets_1 + (io_out_s2_full_pred_3_offsets_1), + .io_out_s2_full_pred_3_fallThroughAddr + (io_out_s2_full_pred_3_fallThroughAddr), + .io_out_s2_full_pred_3_fallThroughErr + (io_out_s2_full_pred_3_fallThroughErr), + .io_out_s2_full_pred_3_is_br_sharing + (io_out_s2_full_pred_3_is_br_sharing), + .io_out_s2_full_pred_3_hit + (io_out_s2_full_pred_3_hit), + .io_out_s3_pc_0 (io_out_s3_pc_0), + .io_out_s3_pc_1 (io_out_s3_pc_1), + .io_out_s3_pc_2 (io_out_s3_pc_2), + .io_out_s3_pc_3 (io_out_s3_pc_3), + .io_out_s3_full_pred_0_br_taken_mask_0 + (io_out_s3_full_pred_0_br_taken_mask_0), + .io_out_s3_full_pred_0_br_taken_mask_1 + (io_out_s3_full_pred_0_br_taken_mask_1), + .io_out_s3_full_pred_0_slot_valids_0 + (io_out_s3_full_pred_0_slot_valids_0), + .io_out_s3_full_pred_0_slot_valids_1 + (io_out_s3_full_pred_0_slot_valids_1), + .io_out_s3_full_pred_0_targets_0 + (io_out_s3_full_pred_0_targets_0), + .io_out_s3_full_pred_0_targets_1 + (io_out_s3_full_pred_0_targets_1), + .io_out_s3_full_pred_0_fallThroughAddr + (io_out_s3_full_pred_0_fallThroughAddr), + .io_out_s3_full_pred_0_fallThroughErr + (io_out_s3_full_pred_0_fallThroughErr), + .io_out_s3_full_pred_0_is_br_sharing + (io_out_s3_full_pred_0_is_br_sharing), + .io_out_s3_full_pred_0_hit + (io_out_s3_full_pred_0_hit), + .io_out_s3_full_pred_1_br_taken_mask_0 + (io_out_s3_full_pred_1_br_taken_mask_0), + .io_out_s3_full_pred_1_br_taken_mask_1 + (io_out_s3_full_pred_1_br_taken_mask_1), + .io_out_s3_full_pred_1_slot_valids_0 + (io_out_s3_full_pred_1_slot_valids_0), + .io_out_s3_full_pred_1_slot_valids_1 + (io_out_s3_full_pred_1_slot_valids_1), + .io_out_s3_full_pred_1_targets_0 + (io_out_s3_full_pred_1_targets_0), + .io_out_s3_full_pred_1_targets_1 + (io_out_s3_full_pred_1_targets_1), + .io_out_s3_full_pred_1_fallThroughAddr + (io_out_s3_full_pred_1_fallThroughAddr), + .io_out_s3_full_pred_1_fallThroughErr + (io_out_s3_full_pred_1_fallThroughErr), + .io_out_s3_full_pred_1_is_br_sharing + (io_out_s3_full_pred_1_is_br_sharing), + .io_out_s3_full_pred_1_hit + (io_out_s3_full_pred_1_hit), + .io_out_s3_full_pred_2_br_taken_mask_0 + (io_out_s3_full_pred_2_br_taken_mask_0), + .io_out_s3_full_pred_2_br_taken_mask_1 + (io_out_s3_full_pred_2_br_taken_mask_1), + .io_out_s3_full_pred_2_slot_valids_0 + (io_out_s3_full_pred_2_slot_valids_0), + .io_out_s3_full_pred_2_slot_valids_1 + (io_out_s3_full_pred_2_slot_valids_1), + .io_out_s3_full_pred_2_targets_0 + (io_out_s3_full_pred_2_targets_0), + .io_out_s3_full_pred_2_targets_1 + (io_out_s3_full_pred_2_targets_1), + .io_out_s3_full_pred_2_fallThroughAddr + (io_out_s3_full_pred_2_fallThroughAddr), + .io_out_s3_full_pred_2_fallThroughErr + (io_out_s3_full_pred_2_fallThroughErr), + .io_out_s3_full_pred_2_is_br_sharing + (io_out_s3_full_pred_2_is_br_sharing), + .io_out_s3_full_pred_2_hit + (io_out_s3_full_pred_2_hit), + .io_out_s3_full_pred_3_br_taken_mask_0 + (io_out_s3_full_pred_3_br_taken_mask_0), + .io_out_s3_full_pred_3_br_taken_mask_1 + (io_out_s3_full_pred_3_br_taken_mask_1), + .io_out_s3_full_pred_3_slot_valids_0 + (io_out_s3_full_pred_3_slot_valids_0), + .io_out_s3_full_pred_3_slot_valids_1 + (io_out_s3_full_pred_3_slot_valids_1), + .io_out_s3_full_pred_3_targets_0 + (io_out_s3_full_pred_3_targets_0), + .io_out_s3_full_pred_3_targets_1 + (io_out_s3_full_pred_3_targets_1), + .io_out_s3_full_pred_3_offsets_0 + (io_out_s3_full_pred_3_offsets_0), + .io_out_s3_full_pred_3_offsets_1 + (io_out_s3_full_pred_3_offsets_1), + .io_out_s3_full_pred_3_fallThroughAddr + (io_out_s3_full_pred_3_fallThroughAddr), + .io_out_s3_full_pred_3_fallThroughErr + (io_out_s3_full_pred_3_fallThroughErr), + .io_out_s3_full_pred_3_is_br_sharing + (io_out_s3_full_pred_3_is_br_sharing), + .io_out_s3_full_pred_3_hit + (io_out_s3_full_pred_3_hit), + .io_out_last_stage_meta + (_ras_io_out_last_stage_meta), + .io_out_last_stage_spec_info_ssp + (io_out_last_stage_spec_info_ssp), + .io_out_last_stage_spec_info_sctr + (io_out_last_stage_spec_info_sctr), + .io_out_last_stage_spec_info_TOSW_flag + (io_out_last_stage_spec_info_TOSW_flag), + .io_out_last_stage_spec_info_TOSW_value + (io_out_last_stage_spec_info_TOSW_value), + .io_out_last_stage_spec_info_TOSR_flag + (io_out_last_stage_spec_info_TOSR_flag), + .io_out_last_stage_spec_info_TOSR_value + (io_out_last_stage_spec_info_TOSR_value), + .io_out_last_stage_spec_info_NOS_flag + (io_out_last_stage_spec_info_NOS_flag), + .io_out_last_stage_spec_info_NOS_value + (io_out_last_stage_spec_info_NOS_value), + .io_out_last_stage_spec_info_topAddr + (io_out_last_stage_spec_info_topAddr), + .io_out_last_stage_ftb_entry_valid + (io_out_last_stage_ftb_entry_valid), + .io_out_last_stage_ftb_entry_brSlots_0_offset + (io_out_last_stage_ftb_entry_brSlots_0_offset), + .io_out_last_stage_ftb_entry_brSlots_0_lower + (io_out_last_stage_ftb_entry_brSlots_0_lower), + .io_out_last_stage_ftb_entry_brSlots_0_tarStat + (io_out_last_stage_ftb_entry_brSlots_0_tarStat), + .io_out_last_stage_ftb_entry_brSlots_0_sharing + (io_out_last_stage_ftb_entry_brSlots_0_sharing), + .io_out_last_stage_ftb_entry_brSlots_0_valid + (io_out_last_stage_ftb_entry_brSlots_0_valid), + .io_out_last_stage_ftb_entry_tailSlot_offset + (io_out_last_stage_ftb_entry_tailSlot_offset), + .io_out_last_stage_ftb_entry_tailSlot_lower + (io_out_last_stage_ftb_entry_tailSlot_lower), + .io_out_last_stage_ftb_entry_tailSlot_tarStat + (io_out_last_stage_ftb_entry_tailSlot_tarStat), + .io_out_last_stage_ftb_entry_tailSlot_sharing + (io_out_last_stage_ftb_entry_tailSlot_sharing), + .io_out_last_stage_ftb_entry_tailSlot_valid + (io_out_last_stage_ftb_entry_tailSlot_valid), + .io_out_last_stage_ftb_entry_pftAddr + (io_out_last_stage_ftb_entry_pftAddr), + .io_out_last_stage_ftb_entry_carry + (io_out_last_stage_ftb_entry_carry), + .io_out_last_stage_ftb_entry_isCall + (io_out_last_stage_ftb_entry_isCall), + .io_out_last_stage_ftb_entry_isRet + (io_out_last_stage_ftb_entry_isRet), + .io_out_last_stage_ftb_entry_isJalr + (io_out_last_stage_ftb_entry_isJalr), + .io_out_last_stage_ftb_entry_last_may_be_rvi_call + (io_out_last_stage_ftb_entry_last_may_be_rvi_call), + .io_out_last_stage_ftb_entry_always_taken_0 + (io_out_last_stage_ftb_entry_always_taken_0), + .io_out_last_stage_ftb_entry_always_taken_1 + (io_out_last_stage_ftb_entry_always_taken_1), + .io_ctrl_ras_enable + (_ras_io_ctrl_delay_io_out_ras_enable), + .io_s0_fire_0 (io_s0_fire_0), + .io_s0_fire_1 (io_s0_fire_1), + .io_s0_fire_2 (io_s0_fire_2), + .io_s0_fire_3 (io_s0_fire_3), + .io_s1_fire_0 (io_s1_fire_0), + .io_s1_fire_1 (io_s1_fire_1), + .io_s1_fire_2 (io_s1_fire_2), + .io_s1_fire_3 (io_s1_fire_3), + .io_s2_fire_0 (io_s2_fire_0), + .io_s2_fire_1 (io_s2_fire_1), + .io_s2_fire_2 (io_s2_fire_2), + .io_s2_fire_3 (io_s2_fire_3), + .io_s3_fire_2 (io_s3_fire_2), + .io_s3_redirect_2 (io_s3_redirect_2), + .io_update_valid (io_update_valid), + .io_update_bits_ftb_entry_tailSlot_offset + (io_update_bits_ftb_entry_tailSlot_offset), + .io_update_bits_ftb_entry_tailSlot_valid + (io_update_bits_ftb_entry_tailSlot_valid), + .io_update_bits_ftb_entry_isCall + (io_update_bits_ftb_entry_isCall), + .io_update_bits_ftb_entry_isRet + (io_update_bits_ftb_entry_isRet), + .io_update_bits_cfi_idx_valid + (io_update_bits_cfi_idx_valid), + .io_update_bits_cfi_idx_bits + (io_update_bits_cfi_idx_bits), + .io_update_bits_jmp_taken + (io_update_bits_jmp_taken), + .io_update_bits_meta (io_update_bits_meta), + .io_redirect_valid (io_redirect_valid), + .io_redirect_bits_level + (io_redirect_bits_level), + .io_redirect_bits_cfiUpdate_pc + (io_redirect_bits_cfiUpdate_pc), + .io_redirect_bits_cfiUpdate_pd_isRVC + (io_redirect_bits_cfiUpdate_pd_isRVC), + .io_redirect_bits_cfiUpdate_pd_isCall + (io_redirect_bits_cfiUpdate_pd_isCall), + .io_redirect_bits_cfiUpdate_pd_isRet + (io_redirect_bits_cfiUpdate_pd_isRet), + .io_redirect_bits_cfiUpdate_ssp + (io_redirect_bits_cfiUpdate_ssp), + .io_redirect_bits_cfiUpdate_sctr + (io_redirect_bits_cfiUpdate_sctr), + .io_redirect_bits_cfiUpdate_TOSW_flag + (io_redirect_bits_cfiUpdate_TOSW_flag), + .io_redirect_bits_cfiUpdate_TOSW_value + (io_redirect_bits_cfiUpdate_TOSW_value), + .io_redirect_bits_cfiUpdate_TOSR_flag + (io_redirect_bits_cfiUpdate_TOSR_flag), + .io_redirect_bits_cfiUpdate_TOSR_value + (io_redirect_bits_cfiUpdate_TOSR_value), + .io_redirect_bits_cfiUpdate_NOS_flag + (io_redirect_bits_cfiUpdate_NOS_flag), + .io_redirect_bits_cfiUpdate_NOS_value + (io_redirect_bits_cfiUpdate_NOS_value) + ); + ITTage ittage ( + .clock (clock), + .reset (reset), + .io_in_bits_s0_pc_3 (io_in_bits_s0_pc_3), + .io_in_bits_folded_hist_3_hist_14_folded_hist + (io_in_bits_folded_hist_3_hist_14_folded_hist), + .io_in_bits_folded_hist_3_hist_13_folded_hist + (io_in_bits_folded_hist_3_hist_13_folded_hist), + .io_in_bits_folded_hist_3_hist_12_folded_hist + (io_in_bits_folded_hist_3_hist_12_folded_hist), + .io_in_bits_folded_hist_3_hist_10_folded_hist + (io_in_bits_folded_hist_3_hist_10_folded_hist), + .io_in_bits_folded_hist_3_hist_6_folded_hist + (io_in_bits_folded_hist_3_hist_6_folded_hist), + .io_in_bits_folded_hist_3_hist_4_folded_hist + (io_in_bits_folded_hist_3_hist_4_folded_hist), + .io_in_bits_folded_hist_3_hist_3_folded_hist + (io_in_bits_folded_hist_3_hist_3_folded_hist), + .io_in_bits_folded_hist_3_hist_2_folded_hist + (io_in_bits_folded_hist_3_hist_2_folded_hist), + .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_0_br_taken_mask_0), + .io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_0_br_taken_mask_1), + .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0 + (_ftb_io_out_s2_full_pred_0_slot_valids_0), + .io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1 + (_ftb_io_out_s2_full_pred_0_slot_valids_1), + .io_in_bits_resp_in_0_s2_full_pred_0_targets_0 + (_ftb_io_out_s2_full_pred_0_targets_0), + .io_in_bits_resp_in_0_s2_full_pred_0_targets_1 + (_ftb_io_out_s2_full_pred_0_targets_1), + .io_in_bits_resp_in_0_s2_full_pred_0_jalr_target + (_ftb_io_out_s2_full_pred_0_jalr_target), + .io_in_bits_resp_in_0_s2_full_pred_0_offsets_0 + (_ftb_io_out_s2_full_pred_0_offsets_0), + .io_in_bits_resp_in_0_s2_full_pred_0_offsets_1 + (_ftb_io_out_s2_full_pred_0_offsets_1), + .io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr + (_ftb_io_out_s2_full_pred_0_fallThroughAddr), + .io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing + (_ftb_io_out_s2_full_pred_0_is_br_sharing), + .io_in_bits_resp_in_0_s2_full_pred_0_hit + (_ftb_io_out_s2_full_pred_0_hit), + .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_1_br_taken_mask_0), + .io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_1_br_taken_mask_1), + .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0 + (_ftb_io_out_s2_full_pred_1_slot_valids_0), + .io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1 + (_ftb_io_out_s2_full_pred_1_slot_valids_1), + .io_in_bits_resp_in_0_s2_full_pred_1_targets_0 + (_ftb_io_out_s2_full_pred_1_targets_0), + .io_in_bits_resp_in_0_s2_full_pred_1_targets_1 + (_ftb_io_out_s2_full_pred_1_targets_1), + .io_in_bits_resp_in_0_s2_full_pred_1_jalr_target + (_ftb_io_out_s2_full_pred_1_jalr_target), + .io_in_bits_resp_in_0_s2_full_pred_1_offsets_0 + (_ftb_io_out_s2_full_pred_1_offsets_0), + .io_in_bits_resp_in_0_s2_full_pred_1_offsets_1 + (_ftb_io_out_s2_full_pred_1_offsets_1), + .io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr + (_ftb_io_out_s2_full_pred_1_fallThroughAddr), + .io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing + (_ftb_io_out_s2_full_pred_1_is_br_sharing), + .io_in_bits_resp_in_0_s2_full_pred_1_hit + (_ftb_io_out_s2_full_pred_1_hit), + .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_2_br_taken_mask_0), + .io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_2_br_taken_mask_1), + .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0 + (_ftb_io_out_s2_full_pred_2_slot_valids_0), + .io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1 + (_ftb_io_out_s2_full_pred_2_slot_valids_1), + .io_in_bits_resp_in_0_s2_full_pred_2_targets_0 + (_ftb_io_out_s2_full_pred_2_targets_0), + .io_in_bits_resp_in_0_s2_full_pred_2_targets_1 + (_ftb_io_out_s2_full_pred_2_targets_1), + .io_in_bits_resp_in_0_s2_full_pred_2_jalr_target + (_ftb_io_out_s2_full_pred_2_jalr_target), + .io_in_bits_resp_in_0_s2_full_pred_2_offsets_0 + (_ftb_io_out_s2_full_pred_2_offsets_0), + .io_in_bits_resp_in_0_s2_full_pred_2_offsets_1 + (_ftb_io_out_s2_full_pred_2_offsets_1), + .io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr + (_ftb_io_out_s2_full_pred_2_fallThroughAddr), + .io_in_bits_resp_in_0_s2_full_pred_2_is_jalr + (_ftb_io_out_s2_full_pred_2_is_jalr), + .io_in_bits_resp_in_0_s2_full_pred_2_is_call + (_ftb_io_out_s2_full_pred_2_is_call), + .io_in_bits_resp_in_0_s2_full_pred_2_is_ret + (_ftb_io_out_s2_full_pred_2_is_ret), + .io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call + (_ftb_io_out_s2_full_pred_2_last_may_be_rvi_call), + .io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing + (_ftb_io_out_s2_full_pred_2_is_br_sharing), + .io_in_bits_resp_in_0_s2_full_pred_2_hit + (_ftb_io_out_s2_full_pred_2_hit), + .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 + (_ftb_io_out_s2_full_pred_3_br_taken_mask_0), + .io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 + (_ftb_io_out_s2_full_pred_3_br_taken_mask_1), + .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0 + (_ftb_io_out_s2_full_pred_3_slot_valids_0), + .io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1 + (_ftb_io_out_s2_full_pred_3_slot_valids_1), + .io_in_bits_resp_in_0_s2_full_pred_3_targets_0 + (_ftb_io_out_s2_full_pred_3_targets_0), + .io_in_bits_resp_in_0_s2_full_pred_3_targets_1 + (_ftb_io_out_s2_full_pred_3_targets_1), + .io_in_bits_resp_in_0_s2_full_pred_3_jalr_target + (_ftb_io_out_s2_full_pred_3_jalr_target), + .io_in_bits_resp_in_0_s2_full_pred_3_offsets_0 + (_ftb_io_out_s2_full_pred_3_offsets_0), + .io_in_bits_resp_in_0_s2_full_pred_3_offsets_1 + (_ftb_io_out_s2_full_pred_3_offsets_1), + .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr + (_ftb_io_out_s2_full_pred_3_fallThroughAddr), + .io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr + (_ftb_io_out_s2_full_pred_3_fallThroughErr), + .io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing + (_ftb_io_out_s2_full_pred_3_is_br_sharing), + .io_in_bits_resp_in_0_s2_full_pred_3_hit + (_ftb_io_out_s2_full_pred_3_hit), + .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_0_br_taken_mask_0), + .io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_0_br_taken_mask_1), + .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0 + (_ftb_io_out_s3_full_pred_0_slot_valids_0), + .io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1 + (_ftb_io_out_s3_full_pred_0_slot_valids_1), + .io_in_bits_resp_in_0_s3_full_pred_0_targets_0 + (_ftb_io_out_s3_full_pred_0_targets_0), + .io_in_bits_resp_in_0_s3_full_pred_0_targets_1 + (_ftb_io_out_s3_full_pred_0_targets_1), + .io_in_bits_resp_in_0_s3_full_pred_0_jalr_target + (_ftb_io_out_s3_full_pred_0_jalr_target), + .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr + (_ftb_io_out_s3_full_pred_0_fallThroughAddr), + .io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr + (_ftb_io_out_s3_full_pred_0_fallThroughErr), + .io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing + (_ftb_io_out_s3_full_pred_0_is_br_sharing), + .io_in_bits_resp_in_0_s3_full_pred_0_hit + (_ftb_io_out_s3_full_pred_0_hit), + .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_1_br_taken_mask_0), + .io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_1_br_taken_mask_1), + .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0 + (_ftb_io_out_s3_full_pred_1_slot_valids_0), + .io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1 + (_ftb_io_out_s3_full_pred_1_slot_valids_1), + .io_in_bits_resp_in_0_s3_full_pred_1_targets_0 + (_ftb_io_out_s3_full_pred_1_targets_0), + .io_in_bits_resp_in_0_s3_full_pred_1_targets_1 + (_ftb_io_out_s3_full_pred_1_targets_1), + .io_in_bits_resp_in_0_s3_full_pred_1_jalr_target + (_ftb_io_out_s3_full_pred_1_jalr_target), + .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr + (_ftb_io_out_s3_full_pred_1_fallThroughAddr), + .io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr + (_ftb_io_out_s3_full_pred_1_fallThroughErr), + .io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing + (_ftb_io_out_s3_full_pred_1_is_br_sharing), + .io_in_bits_resp_in_0_s3_full_pred_1_hit + (_ftb_io_out_s3_full_pred_1_hit), + .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_2_br_taken_mask_0), + .io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_2_br_taken_mask_1), + .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0 + (_ftb_io_out_s3_full_pred_2_slot_valids_0), + .io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1 + (_ftb_io_out_s3_full_pred_2_slot_valids_1), + .io_in_bits_resp_in_0_s3_full_pred_2_targets_0 + (_ftb_io_out_s3_full_pred_2_targets_0), + .io_in_bits_resp_in_0_s3_full_pred_2_targets_1 + (_ftb_io_out_s3_full_pred_2_targets_1), + .io_in_bits_resp_in_0_s3_full_pred_2_jalr_target + (_ftb_io_out_s3_full_pred_2_jalr_target), + .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr + (_ftb_io_out_s3_full_pred_2_fallThroughAddr), + .io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr + (_ftb_io_out_s3_full_pred_2_fallThroughErr), + .io_in_bits_resp_in_0_s3_full_pred_2_is_jalr + (_ftb_io_out_s3_full_pred_2_is_jalr), + .io_in_bits_resp_in_0_s3_full_pred_2_is_call + (_ftb_io_out_s3_full_pred_2_is_call), + .io_in_bits_resp_in_0_s3_full_pred_2_is_ret + (_ftb_io_out_s3_full_pred_2_is_ret), + .io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing + (_ftb_io_out_s3_full_pred_2_is_br_sharing), + .io_in_bits_resp_in_0_s3_full_pred_2_hit + (_ftb_io_out_s3_full_pred_2_hit), + .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 + (_ftb_io_out_s3_full_pred_3_br_taken_mask_0), + .io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 + (_ftb_io_out_s3_full_pred_3_br_taken_mask_1), + .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0 + (_ftb_io_out_s3_full_pred_3_slot_valids_0), + .io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1 + (_ftb_io_out_s3_full_pred_3_slot_valids_1), + .io_in_bits_resp_in_0_s3_full_pred_3_targets_0 + (_ftb_io_out_s3_full_pred_3_targets_0), + .io_in_bits_resp_in_0_s3_full_pred_3_targets_1 + (_ftb_io_out_s3_full_pred_3_targets_1), + .io_in_bits_resp_in_0_s3_full_pred_3_jalr_target + (_ftb_io_out_s3_full_pred_3_jalr_target), + .io_in_bits_resp_in_0_s3_full_pred_3_offsets_0 + (_ftb_io_out_s3_full_pred_3_offsets_0), + .io_in_bits_resp_in_0_s3_full_pred_3_offsets_1 + (_ftb_io_out_s3_full_pred_3_offsets_1), + .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr + (_ftb_io_out_s3_full_pred_3_fallThroughAddr), + .io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr + (_ftb_io_out_s3_full_pred_3_fallThroughErr), + .io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing + (_ftb_io_out_s3_full_pred_3_is_br_sharing), + .io_in_bits_resp_in_0_s3_full_pred_3_hit + (_ftb_io_out_s3_full_pred_3_hit), + .io_in_bits_resp_in_0_last_stage_ftb_entry_valid + (_ftb_io_out_last_stage_ftb_entry_valid), + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_offset), + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_lower), + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_tarStat), + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_sharing), + .io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid + (_ftb_io_out_last_stage_ftb_entry_brSlots_0_valid), + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset + (_ftb_io_out_last_stage_ftb_entry_tailSlot_offset), + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower + (_ftb_io_out_last_stage_ftb_entry_tailSlot_lower), + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat + (_ftb_io_out_last_stage_ftb_entry_tailSlot_tarStat), + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing + (_ftb_io_out_last_stage_ftb_entry_tailSlot_sharing), + .io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid + (_ftb_io_out_last_stage_ftb_entry_tailSlot_valid), + .io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr + (_ftb_io_out_last_stage_ftb_entry_pftAddr), + .io_in_bits_resp_in_0_last_stage_ftb_entry_carry + (_ftb_io_out_last_stage_ftb_entry_carry), + .io_in_bits_resp_in_0_last_stage_ftb_entry_isCall + (_ftb_io_out_last_stage_ftb_entry_isCall), + .io_in_bits_resp_in_0_last_stage_ftb_entry_isRet + (_ftb_io_out_last_stage_ftb_entry_isRet), + .io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr + (_ftb_io_out_last_stage_ftb_entry_isJalr), + .io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call + (_ftb_io_out_last_stage_ftb_entry_last_may_be_rvi_call), + .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0 + (_ftb_io_out_last_stage_ftb_entry_always_taken_0), + .io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1 + (_ftb_io_out_last_stage_ftb_entry_always_taken_1), + .io_out_s2_full_pred_0_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_0_br_taken_mask_0), + .io_out_s2_full_pred_0_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_0_br_taken_mask_1), + .io_out_s2_full_pred_0_slot_valids_0 + (_ittage_io_out_s2_full_pred_0_slot_valids_0), + .io_out_s2_full_pred_0_slot_valids_1 + (_ittage_io_out_s2_full_pred_0_slot_valids_1), + .io_out_s2_full_pred_0_targets_0 + (_ittage_io_out_s2_full_pred_0_targets_0), + .io_out_s2_full_pred_0_targets_1 + (_ittage_io_out_s2_full_pred_0_targets_1), + .io_out_s2_full_pred_0_jalr_target + (_ittage_io_out_s2_full_pred_0_jalr_target), + .io_out_s2_full_pred_0_offsets_0 + (_ittage_io_out_s2_full_pred_0_offsets_0), + .io_out_s2_full_pred_0_offsets_1 + (_ittage_io_out_s2_full_pred_0_offsets_1), + .io_out_s2_full_pred_0_fallThroughAddr + (_ittage_io_out_s2_full_pred_0_fallThroughAddr), + .io_out_s2_full_pred_0_is_br_sharing + (_ittage_io_out_s2_full_pred_0_is_br_sharing), + .io_out_s2_full_pred_0_hit + (_ittage_io_out_s2_full_pred_0_hit), + .io_out_s2_full_pred_1_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_1_br_taken_mask_0), + .io_out_s2_full_pred_1_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_1_br_taken_mask_1), + .io_out_s2_full_pred_1_slot_valids_0 + (_ittage_io_out_s2_full_pred_1_slot_valids_0), + .io_out_s2_full_pred_1_slot_valids_1 + (_ittage_io_out_s2_full_pred_1_slot_valids_1), + .io_out_s2_full_pred_1_targets_0 + (_ittage_io_out_s2_full_pred_1_targets_0), + .io_out_s2_full_pred_1_targets_1 + (_ittage_io_out_s2_full_pred_1_targets_1), + .io_out_s2_full_pred_1_jalr_target + (_ittage_io_out_s2_full_pred_1_jalr_target), + .io_out_s2_full_pred_1_offsets_0 + (_ittage_io_out_s2_full_pred_1_offsets_0), + .io_out_s2_full_pred_1_offsets_1 + (_ittage_io_out_s2_full_pred_1_offsets_1), + .io_out_s2_full_pred_1_fallThroughAddr + (_ittage_io_out_s2_full_pred_1_fallThroughAddr), + .io_out_s2_full_pred_1_is_br_sharing + (_ittage_io_out_s2_full_pred_1_is_br_sharing), + .io_out_s2_full_pred_1_hit + (_ittage_io_out_s2_full_pred_1_hit), + .io_out_s2_full_pred_2_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_2_br_taken_mask_0), + .io_out_s2_full_pred_2_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_2_br_taken_mask_1), + .io_out_s2_full_pred_2_slot_valids_0 + (_ittage_io_out_s2_full_pred_2_slot_valids_0), + .io_out_s2_full_pred_2_slot_valids_1 + (_ittage_io_out_s2_full_pred_2_slot_valids_1), + .io_out_s2_full_pred_2_targets_0 + (_ittage_io_out_s2_full_pred_2_targets_0), + .io_out_s2_full_pred_2_targets_1 + (_ittage_io_out_s2_full_pred_2_targets_1), + .io_out_s2_full_pred_2_jalr_target + (_ittage_io_out_s2_full_pred_2_jalr_target), + .io_out_s2_full_pred_2_offsets_0 + (_ittage_io_out_s2_full_pred_2_offsets_0), + .io_out_s2_full_pred_2_offsets_1 + (_ittage_io_out_s2_full_pred_2_offsets_1), + .io_out_s2_full_pred_2_fallThroughAddr + (_ittage_io_out_s2_full_pred_2_fallThroughAddr), + .io_out_s2_full_pred_2_is_jalr + (_ittage_io_out_s2_full_pred_2_is_jalr), + .io_out_s2_full_pred_2_is_call + (_ittage_io_out_s2_full_pred_2_is_call), + .io_out_s2_full_pred_2_is_ret + (_ittage_io_out_s2_full_pred_2_is_ret), + .io_out_s2_full_pred_2_last_may_be_rvi_call + (_ittage_io_out_s2_full_pred_2_last_may_be_rvi_call), + .io_out_s2_full_pred_2_is_br_sharing + (_ittage_io_out_s2_full_pred_2_is_br_sharing), + .io_out_s2_full_pred_2_hit + (_ittage_io_out_s2_full_pred_2_hit), + .io_out_s2_full_pred_3_br_taken_mask_0 + (_ittage_io_out_s2_full_pred_3_br_taken_mask_0), + .io_out_s2_full_pred_3_br_taken_mask_1 + (_ittage_io_out_s2_full_pred_3_br_taken_mask_1), + .io_out_s2_full_pred_3_slot_valids_0 + (_ittage_io_out_s2_full_pred_3_slot_valids_0), + .io_out_s2_full_pred_3_slot_valids_1 + (_ittage_io_out_s2_full_pred_3_slot_valids_1), + .io_out_s2_full_pred_3_targets_0 + (_ittage_io_out_s2_full_pred_3_targets_0), + .io_out_s2_full_pred_3_targets_1 + (_ittage_io_out_s2_full_pred_3_targets_1), + .io_out_s2_full_pred_3_jalr_target + (_ittage_io_out_s2_full_pred_3_jalr_target), + .io_out_s2_full_pred_3_offsets_0 + (_ittage_io_out_s2_full_pred_3_offsets_0), + .io_out_s2_full_pred_3_offsets_1 + (_ittage_io_out_s2_full_pred_3_offsets_1), + .io_out_s2_full_pred_3_fallThroughAddr + (_ittage_io_out_s2_full_pred_3_fallThroughAddr), + .io_out_s2_full_pred_3_fallThroughErr + (_ittage_io_out_s2_full_pred_3_fallThroughErr), + .io_out_s2_full_pred_3_is_br_sharing + (_ittage_io_out_s2_full_pred_3_is_br_sharing), + .io_out_s2_full_pred_3_hit + (_ittage_io_out_s2_full_pred_3_hit), + .io_out_s3_full_pred_0_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_0_br_taken_mask_0), + .io_out_s3_full_pred_0_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_0_br_taken_mask_1), + .io_out_s3_full_pred_0_slot_valids_0 + (_ittage_io_out_s3_full_pred_0_slot_valids_0), + .io_out_s3_full_pred_0_slot_valids_1 + (_ittage_io_out_s3_full_pred_0_slot_valids_1), + .io_out_s3_full_pred_0_targets_0 + (_ittage_io_out_s3_full_pred_0_targets_0), + .io_out_s3_full_pred_0_targets_1 + (_ittage_io_out_s3_full_pred_0_targets_1), + .io_out_s3_full_pred_0_jalr_target + (_ittage_io_out_s3_full_pred_0_jalr_target), + .io_out_s3_full_pred_0_fallThroughAddr + (_ittage_io_out_s3_full_pred_0_fallThroughAddr), + .io_out_s3_full_pred_0_fallThroughErr + (_ittage_io_out_s3_full_pred_0_fallThroughErr), + .io_out_s3_full_pred_0_is_br_sharing + (_ittage_io_out_s3_full_pred_0_is_br_sharing), + .io_out_s3_full_pred_0_hit + (_ittage_io_out_s3_full_pred_0_hit), + .io_out_s3_full_pred_1_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_1_br_taken_mask_0), + .io_out_s3_full_pred_1_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_1_br_taken_mask_1), + .io_out_s3_full_pred_1_slot_valids_0 + (_ittage_io_out_s3_full_pred_1_slot_valids_0), + .io_out_s3_full_pred_1_slot_valids_1 + (_ittage_io_out_s3_full_pred_1_slot_valids_1), + .io_out_s3_full_pred_1_targets_0 + (_ittage_io_out_s3_full_pred_1_targets_0), + .io_out_s3_full_pred_1_targets_1 + (_ittage_io_out_s3_full_pred_1_targets_1), + .io_out_s3_full_pred_1_jalr_target + (_ittage_io_out_s3_full_pred_1_jalr_target), + .io_out_s3_full_pred_1_fallThroughAddr + (_ittage_io_out_s3_full_pred_1_fallThroughAddr), + .io_out_s3_full_pred_1_fallThroughErr + (_ittage_io_out_s3_full_pred_1_fallThroughErr), + .io_out_s3_full_pred_1_is_br_sharing + (_ittage_io_out_s3_full_pred_1_is_br_sharing), + .io_out_s3_full_pred_1_hit + (_ittage_io_out_s3_full_pred_1_hit), + .io_out_s3_full_pred_2_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_2_br_taken_mask_0), + .io_out_s3_full_pred_2_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_2_br_taken_mask_1), + .io_out_s3_full_pred_2_slot_valids_0 + (_ittage_io_out_s3_full_pred_2_slot_valids_0), + .io_out_s3_full_pred_2_slot_valids_1 + (_ittage_io_out_s3_full_pred_2_slot_valids_1), + .io_out_s3_full_pred_2_targets_0 + (_ittage_io_out_s3_full_pred_2_targets_0), + .io_out_s3_full_pred_2_targets_1 + (_ittage_io_out_s3_full_pred_2_targets_1), + .io_out_s3_full_pred_2_jalr_target + (_ittage_io_out_s3_full_pred_2_jalr_target), + .io_out_s3_full_pred_2_fallThroughAddr + (_ittage_io_out_s3_full_pred_2_fallThroughAddr), + .io_out_s3_full_pred_2_fallThroughErr + (_ittage_io_out_s3_full_pred_2_fallThroughErr), + .io_out_s3_full_pred_2_is_jalr + (_ittage_io_out_s3_full_pred_2_is_jalr), + .io_out_s3_full_pred_2_is_call + (_ittage_io_out_s3_full_pred_2_is_call), + .io_out_s3_full_pred_2_is_ret + (_ittage_io_out_s3_full_pred_2_is_ret), + .io_out_s3_full_pred_2_is_br_sharing + (_ittage_io_out_s3_full_pred_2_is_br_sharing), + .io_out_s3_full_pred_2_hit + (_ittage_io_out_s3_full_pred_2_hit), + .io_out_s3_full_pred_3_br_taken_mask_0 + (_ittage_io_out_s3_full_pred_3_br_taken_mask_0), + .io_out_s3_full_pred_3_br_taken_mask_1 + (_ittage_io_out_s3_full_pred_3_br_taken_mask_1), + .io_out_s3_full_pred_3_slot_valids_0 + (_ittage_io_out_s3_full_pred_3_slot_valids_0), + .io_out_s3_full_pred_3_slot_valids_1 + (_ittage_io_out_s3_full_pred_3_slot_valids_1), + .io_out_s3_full_pred_3_targets_0 + (_ittage_io_out_s3_full_pred_3_targets_0), + .io_out_s3_full_pred_3_targets_1 + (_ittage_io_out_s3_full_pred_3_targets_1), + .io_out_s3_full_pred_3_jalr_target + (_ittage_io_out_s3_full_pred_3_jalr_target), + .io_out_s3_full_pred_3_offsets_0 + (_ittage_io_out_s3_full_pred_3_offsets_0), + .io_out_s3_full_pred_3_offsets_1 + (_ittage_io_out_s3_full_pred_3_offsets_1), + .io_out_s3_full_pred_3_fallThroughAddr + (_ittage_io_out_s3_full_pred_3_fallThroughAddr), + .io_out_s3_full_pred_3_fallThroughErr + (_ittage_io_out_s3_full_pred_3_fallThroughErr), + .io_out_s3_full_pred_3_is_br_sharing + (_ittage_io_out_s3_full_pred_3_is_br_sharing), + .io_out_s3_full_pred_3_hit + (_ittage_io_out_s3_full_pred_3_hit), + .io_out_last_stage_meta + (_ittage_io_out_last_stage_meta), + .io_out_last_stage_ftb_entry_valid + (_ittage_io_out_last_stage_ftb_entry_valid), + .io_out_last_stage_ftb_entry_brSlots_0_offset + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_offset), + .io_out_last_stage_ftb_entry_brSlots_0_lower + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_lower), + .io_out_last_stage_ftb_entry_brSlots_0_tarStat + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_tarStat), + .io_out_last_stage_ftb_entry_brSlots_0_sharing + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_sharing), + .io_out_last_stage_ftb_entry_brSlots_0_valid + (_ittage_io_out_last_stage_ftb_entry_brSlots_0_valid), + .io_out_last_stage_ftb_entry_tailSlot_offset + (_ittage_io_out_last_stage_ftb_entry_tailSlot_offset), + .io_out_last_stage_ftb_entry_tailSlot_lower + (_ittage_io_out_last_stage_ftb_entry_tailSlot_lower), + .io_out_last_stage_ftb_entry_tailSlot_tarStat + (_ittage_io_out_last_stage_ftb_entry_tailSlot_tarStat), + .io_out_last_stage_ftb_entry_tailSlot_sharing + (_ittage_io_out_last_stage_ftb_entry_tailSlot_sharing), + .io_out_last_stage_ftb_entry_tailSlot_valid + (_ittage_io_out_last_stage_ftb_entry_tailSlot_valid), + .io_out_last_stage_ftb_entry_pftAddr + (_ittage_io_out_last_stage_ftb_entry_pftAddr), + .io_out_last_stage_ftb_entry_carry + (_ittage_io_out_last_stage_ftb_entry_carry), + .io_out_last_stage_ftb_entry_isCall + (_ittage_io_out_last_stage_ftb_entry_isCall), + .io_out_last_stage_ftb_entry_isRet + (_ittage_io_out_last_stage_ftb_entry_isRet), + .io_out_last_stage_ftb_entry_isJalr + (_ittage_io_out_last_stage_ftb_entry_isJalr), + .io_out_last_stage_ftb_entry_last_may_be_rvi_call + (_ittage_io_out_last_stage_ftb_entry_last_may_be_rvi_call), + .io_out_last_stage_ftb_entry_always_taken_0 + (_ittage_io_out_last_stage_ftb_entry_always_taken_0), + .io_out_last_stage_ftb_entry_always_taken_1 + (_ittage_io_out_last_stage_ftb_entry_always_taken_1), + .io_s0_fire_3 (io_s0_fire_3), + .io_s1_fire_3 (io_s1_fire_3), + .io_s2_fire_0 (io_s2_fire_0), + .io_s2_fire_1 (io_s2_fire_1), + .io_s2_fire_2 (io_s2_fire_2), + .io_s2_fire_3 (io_s2_fire_3), + .io_update_valid (io_update_valid), + .io_update_bits_pc (io_update_bits_pc), + .io_update_bits_spec_info_folded_hist_hist_14_folded_hist + (io_update_bits_spec_info_folded_hist_hist_14_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_13_folded_hist + (io_update_bits_spec_info_folded_hist_hist_13_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_12_folded_hist + (io_update_bits_spec_info_folded_hist_hist_12_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_10_folded_hist + (io_update_bits_spec_info_folded_hist_hist_10_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_6_folded_hist + (io_update_bits_spec_info_folded_hist_hist_6_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_4_folded_hist + (io_update_bits_spec_info_folded_hist_hist_4_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_3_folded_hist + (io_update_bits_spec_info_folded_hist_hist_3_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_2_folded_hist + (io_update_bits_spec_info_folded_hist_hist_2_folded_hist), + .io_update_bits_ftb_entry_tailSlot_offset + (io_update_bits_ftb_entry_tailSlot_offset), + .io_update_bits_ftb_entry_tailSlot_sharing + (io_update_bits_ftb_entry_tailSlot_sharing), + .io_update_bits_ftb_entry_tailSlot_valid + (io_update_bits_ftb_entry_tailSlot_valid), + .io_update_bits_ftb_entry_isRet + (io_update_bits_ftb_entry_isRet), + .io_update_bits_ftb_entry_isJalr + (io_update_bits_ftb_entry_isJalr), + .io_update_bits_cfi_idx_valid + (io_update_bits_cfi_idx_valid), + .io_update_bits_cfi_idx_bits + (io_update_bits_cfi_idx_bits), + .io_update_bits_jmp_taken + (io_update_bits_jmp_taken), + .io_update_bits_mispred_mask_2 + (io_update_bits_mispred_mask_2), + .io_update_bits_meta + ({25'h0, io_update_bits_meta[222:25]}), + .io_update_bits_full_target + (io_update_bits_full_target) + ); + DelayN_1 ubtb_io_ctrl_delay ( + .clock (clock), + .io_in_ubtb_enable (io_ctrl_ubtb_enable), + .io_in_btb_enable (io_ctrl_btb_enable), + .io_in_tage_enable (io_ctrl_tage_enable), + .io_in_sc_enable (io_ctrl_sc_enable), + .io_in_ras_enable (io_ctrl_ras_enable), + .io_out_ubtb_enable (_ubtb_io_ctrl_delay_io_out_ubtb_enable), + .io_out_btb_enable (/* unused */), + .io_out_tage_enable (/* unused */), + .io_out_sc_enable (/* unused */), + .io_out_ras_enable (/* unused */) + ); + DelayN_1 tage_io_ctrl_delay ( + .clock (clock), + .io_in_ubtb_enable (io_ctrl_ubtb_enable), + .io_in_btb_enable (io_ctrl_btb_enable), + .io_in_tage_enable (io_ctrl_tage_enable), + .io_in_sc_enable (io_ctrl_sc_enable), + .io_in_ras_enable (io_ctrl_ras_enable), + .io_out_ubtb_enable (/* unused */), + .io_out_btb_enable (/* unused */), + .io_out_tage_enable (_tage_io_ctrl_delay_io_out_tage_enable), + .io_out_sc_enable (_tage_io_ctrl_delay_io_out_sc_enable), + .io_out_ras_enable (/* unused */) + ); + DelayN_1 ftb_io_ctrl_delay ( + .clock (clock), + .io_in_ubtb_enable (io_ctrl_ubtb_enable), + .io_in_btb_enable (io_ctrl_btb_enable), + .io_in_tage_enable (io_ctrl_tage_enable), + .io_in_sc_enable (io_ctrl_sc_enable), + .io_in_ras_enable (io_ctrl_ras_enable), + .io_out_ubtb_enable (/* unused */), + .io_out_btb_enable (_ftb_io_ctrl_delay_io_out_btb_enable), + .io_out_tage_enable (/* unused */), + .io_out_sc_enable (/* unused */), + .io_out_ras_enable (/* unused */) + ); + DelayN_1 ras_io_ctrl_delay ( + .clock (clock), + .io_in_ubtb_enable (io_ctrl_ubtb_enable), + .io_in_btb_enable (io_ctrl_btb_enable), + .io_in_tage_enable (io_ctrl_tage_enable), + .io_in_sc_enable (io_ctrl_sc_enable), + .io_in_ras_enable (io_ctrl_ras_enable), + .io_out_ubtb_enable (/* unused */), + .io_out_btb_enable (/* unused */), + .io_out_tage_enable (/* unused */), + .io_out_sc_enable (/* unused */), + .io_out_ras_enable (_ras_io_ctrl_delay_io_out_ras_enable) + ); + assign io_out_last_stage_meta = + {_ubtb_io_out_last_stage_meta[5:0], + _tage_io_out_last_stage_meta[87:0], + _ftb_io_out_last_stage_meta[2:0], + _ittage_io_out_last_stage_meta[100:0], + _ras_io_out_last_stage_meta[24:0]}; + assign io_s1_ready = _tage_io_s1_ready & _ftb_io_s1_ready; + assign io_perf_0_value = io_perf_0_value_REG_1; + assign io_perf_1_value = io_perf_1_value_REG_1; + assign io_perf_2_value = io_perf_2_value_REG_1; + assign io_perf_3_value = io_perf_3_value_REG_1; + assign io_perf_4_value = io_perf_4_value_REG_1; + assign io_perf_5_value = io_perf_5_value_REG_1; + assign io_perf_6_value = io_perf_6_value_REG_1; +endmodule + diff --git a/rtl/BPUTop/DelayNWithValid.sv b/rtl/BPUTop/DelayNWithValid.sv new file mode 100644 index 0000000..0d55008 --- /dev/null +++ b/rtl/BPUTop/DelayNWithValid.sv @@ -0,0 +1,107 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module DelayNWithValid( + input clock, + input reset, + input [40:0] io_in_bits, + input io_in_valid, + output [40:0] io_out_bits +); + + reg valid_REG; + reg [40:0] data; + reg [40:0] res_bits; + always @(posedge clock or posedge reset) begin + if (reset) + valid_REG <= 1'h0; + else + valid_REG <= io_in_valid; + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_in_valid) + data <= io_in_bits; + if (valid_REG) + res_bits <= data; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; + end + valid_REG = _RANDOM[2'h0][0]; + data = {_RANDOM[2'h0][31:1], _RANDOM[2'h1][9:0]}; + res_bits = {_RANDOM[2'h1][31:11], _RANDOM[2'h2][19:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) + valid_REG = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_out_bits = res_bits; +endmodule + diff --git a/rtl/BPUTop/DelayNWithValid_1.sv b/rtl/BPUTop/DelayNWithValid_1.sv new file mode 100644 index 0000000..59184ce --- /dev/null +++ b/rtl/BPUTop/DelayNWithValid_1.sv @@ -0,0 +1,271 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module DelayNWithValid_1( + input clock, + input reset, + input io_in_bits_valid, + input [3:0] io_in_bits_brSlots_0_offset, + input [11:0] io_in_bits_brSlots_0_lower, + input [1:0] io_in_bits_brSlots_0_tarStat, + input io_in_bits_brSlots_0_sharing, + input io_in_bits_brSlots_0_valid, + input [3:0] io_in_bits_tailSlot_offset, + input [19:0] io_in_bits_tailSlot_lower, + input [1:0] io_in_bits_tailSlot_tarStat, + input io_in_bits_tailSlot_sharing, + input io_in_bits_tailSlot_valid, + input [3:0] io_in_bits_pftAddr, + input io_in_bits_carry, + input io_in_bits_isCall, + input io_in_bits_isRet, + input io_in_bits_isJalr, + input io_in_bits_last_may_be_rvi_call, + input io_in_bits_always_taken_0, + input io_in_bits_always_taken_1, + input io_in_valid, + output io_out_bits_valid, + output [3:0] io_out_bits_brSlots_0_offset, + output [11:0] io_out_bits_brSlots_0_lower, + output [1:0] io_out_bits_brSlots_0_tarStat, + output io_out_bits_brSlots_0_sharing, + output io_out_bits_brSlots_0_valid, + output [3:0] io_out_bits_tailSlot_offset, + output [19:0] io_out_bits_tailSlot_lower, + output [1:0] io_out_bits_tailSlot_tarStat, + output io_out_bits_tailSlot_sharing, + output io_out_bits_tailSlot_valid, + output [3:0] io_out_bits_pftAddr, + output io_out_bits_carry, + output io_out_bits_isCall, + output io_out_bits_isRet, + output io_out_bits_isJalr, + output io_out_bits_last_may_be_rvi_call, + output io_out_bits_always_taken_0, + output io_out_bits_always_taken_1 +); + + reg valid_REG; + reg data_valid; + reg [3:0] data_brSlots_0_offset; + reg [11:0] data_brSlots_0_lower; + reg [1:0] data_brSlots_0_tarStat; + reg data_brSlots_0_sharing; + reg data_brSlots_0_valid; + reg [3:0] data_tailSlot_offset; + reg [19:0] data_tailSlot_lower; + reg [1:0] data_tailSlot_tarStat; + reg data_tailSlot_sharing; + reg data_tailSlot_valid; + reg [3:0] data_pftAddr; + reg data_carry; + reg data_isCall; + reg data_isRet; + reg data_isJalr; + reg data_last_may_be_rvi_call; + reg data_always_taken_0; + reg data_always_taken_1; + reg res_bits_valid; + reg [3:0] res_bits_brSlots_0_offset; + reg [11:0] res_bits_brSlots_0_lower; + reg [1:0] res_bits_brSlots_0_tarStat; + reg res_bits_brSlots_0_sharing; + reg res_bits_brSlots_0_valid; + reg [3:0] res_bits_tailSlot_offset; + reg [19:0] res_bits_tailSlot_lower; + reg [1:0] res_bits_tailSlot_tarStat; + reg res_bits_tailSlot_sharing; + reg res_bits_tailSlot_valid; + reg [3:0] res_bits_pftAddr; + reg res_bits_carry; + reg res_bits_isCall; + reg res_bits_isRet; + reg res_bits_isJalr; + reg res_bits_last_may_be_rvi_call; + reg res_bits_always_taken_0; + reg res_bits_always_taken_1; + always @(posedge clock or posedge reset) begin + if (reset) + valid_REG <= 1'h0; + else + valid_REG <= io_in_valid; + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_in_valid) begin + data_valid <= io_in_bits_valid; + data_brSlots_0_offset <= io_in_bits_brSlots_0_offset; + data_brSlots_0_lower <= io_in_bits_brSlots_0_lower; + data_brSlots_0_tarStat <= io_in_bits_brSlots_0_tarStat; + data_brSlots_0_sharing <= io_in_bits_brSlots_0_sharing; + data_brSlots_0_valid <= io_in_bits_brSlots_0_valid; + data_tailSlot_offset <= io_in_bits_tailSlot_offset; + data_tailSlot_lower <= io_in_bits_tailSlot_lower; + data_tailSlot_tarStat <= io_in_bits_tailSlot_tarStat; + data_tailSlot_sharing <= io_in_bits_tailSlot_sharing; + data_tailSlot_valid <= io_in_bits_tailSlot_valid; + data_pftAddr <= io_in_bits_pftAddr; + data_carry <= io_in_bits_carry; + data_isCall <= io_in_bits_isCall; + data_isRet <= io_in_bits_isRet; + data_isJalr <= io_in_bits_isJalr; + data_last_may_be_rvi_call <= io_in_bits_last_may_be_rvi_call; + data_always_taken_0 <= io_in_bits_always_taken_0; + data_always_taken_1 <= io_in_bits_always_taken_1; + end + if (valid_REG) begin + res_bits_valid <= data_valid; + res_bits_brSlots_0_offset <= data_brSlots_0_offset; + res_bits_brSlots_0_lower <= data_brSlots_0_lower; + res_bits_brSlots_0_tarStat <= data_brSlots_0_tarStat; + res_bits_brSlots_0_sharing <= data_brSlots_0_sharing; + res_bits_brSlots_0_valid <= data_brSlots_0_valid; + res_bits_tailSlot_offset <= data_tailSlot_offset; + res_bits_tailSlot_lower <= data_tailSlot_lower; + res_bits_tailSlot_tarStat <= data_tailSlot_tarStat; + res_bits_tailSlot_sharing <= data_tailSlot_sharing; + res_bits_tailSlot_valid <= data_tailSlot_valid; + res_bits_pftAddr <= data_pftAddr; + res_bits_carry <= data_carry; + res_bits_isCall <= data_isCall; + res_bits_isRet <= data_isRet; + res_bits_isJalr <= data_isJalr; + res_bits_last_may_be_rvi_call <= data_last_may_be_rvi_call; + res_bits_always_taken_0 <= data_always_taken_0; + res_bits_always_taken_1 <= data_always_taken_1; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; + end + valid_REG = _RANDOM[2'h0][0]; + data_valid = _RANDOM[2'h0][1]; + data_brSlots_0_offset = _RANDOM[2'h0][5:2]; + data_brSlots_0_lower = _RANDOM[2'h0][17:6]; + data_brSlots_0_tarStat = _RANDOM[2'h0][19:18]; + data_brSlots_0_sharing = _RANDOM[2'h0][20]; + data_brSlots_0_valid = _RANDOM[2'h0][21]; + data_tailSlot_offset = _RANDOM[2'h0][25:22]; + data_tailSlot_lower = {_RANDOM[2'h0][31:26], _RANDOM[2'h1][13:0]}; + data_tailSlot_tarStat = _RANDOM[2'h1][15:14]; + data_tailSlot_sharing = _RANDOM[2'h1][16]; + data_tailSlot_valid = _RANDOM[2'h1][17]; + data_pftAddr = _RANDOM[2'h1][21:18]; + data_carry = _RANDOM[2'h1][22]; + data_isCall = _RANDOM[2'h1][23]; + data_isRet = _RANDOM[2'h1][24]; + data_isJalr = _RANDOM[2'h1][25]; + data_last_may_be_rvi_call = _RANDOM[2'h1][26]; + data_always_taken_0 = _RANDOM[2'h1][27]; + data_always_taken_1 = _RANDOM[2'h1][28]; + res_bits_valid = _RANDOM[2'h1][30]; + res_bits_brSlots_0_offset = {_RANDOM[2'h1][31], _RANDOM[2'h2][2:0]}; + res_bits_brSlots_0_lower = _RANDOM[2'h2][14:3]; + res_bits_brSlots_0_tarStat = _RANDOM[2'h2][16:15]; + res_bits_brSlots_0_sharing = _RANDOM[2'h2][17]; + res_bits_brSlots_0_valid = _RANDOM[2'h2][18]; + res_bits_tailSlot_offset = _RANDOM[2'h2][22:19]; + res_bits_tailSlot_lower = {_RANDOM[2'h2][31:23], _RANDOM[2'h3][10:0]}; + res_bits_tailSlot_tarStat = _RANDOM[2'h3][12:11]; + res_bits_tailSlot_sharing = _RANDOM[2'h3][13]; + res_bits_tailSlot_valid = _RANDOM[2'h3][14]; + res_bits_pftAddr = _RANDOM[2'h3][18:15]; + res_bits_carry = _RANDOM[2'h3][19]; + res_bits_isCall = _RANDOM[2'h3][20]; + res_bits_isRet = _RANDOM[2'h3][21]; + res_bits_isJalr = _RANDOM[2'h3][22]; + res_bits_last_may_be_rvi_call = _RANDOM[2'h3][23]; + res_bits_always_taken_0 = _RANDOM[2'h3][24]; + res_bits_always_taken_1 = _RANDOM[2'h3][25]; + `endif // RANDOMIZE_REG_INIT + if (reset) + valid_REG = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_out_bits_valid = res_bits_valid; + assign io_out_bits_brSlots_0_offset = res_bits_brSlots_0_offset; + assign io_out_bits_brSlots_0_lower = res_bits_brSlots_0_lower; + assign io_out_bits_brSlots_0_tarStat = res_bits_brSlots_0_tarStat; + assign io_out_bits_brSlots_0_sharing = res_bits_brSlots_0_sharing; + assign io_out_bits_brSlots_0_valid = res_bits_brSlots_0_valid; + assign io_out_bits_tailSlot_offset = res_bits_tailSlot_offset; + assign io_out_bits_tailSlot_lower = res_bits_tailSlot_lower; + assign io_out_bits_tailSlot_tarStat = res_bits_tailSlot_tarStat; + assign io_out_bits_tailSlot_sharing = res_bits_tailSlot_sharing; + assign io_out_bits_tailSlot_valid = res_bits_tailSlot_valid; + assign io_out_bits_pftAddr = res_bits_pftAddr; + assign io_out_bits_carry = res_bits_carry; + assign io_out_bits_isCall = res_bits_isCall; + assign io_out_bits_isRet = res_bits_isRet; + assign io_out_bits_isJalr = res_bits_isJalr; + assign io_out_bits_last_may_be_rvi_call = res_bits_last_may_be_rvi_call; + assign io_out_bits_always_taken_0 = res_bits_always_taken_0; + assign io_out_bits_always_taken_1 = res_bits_always_taken_1; +endmodule + diff --git a/rtl/BPUTop/DelayN_1.sv b/rtl/BPUTop/DelayN_1.sv new file mode 100644 index 0000000..d213a55 --- /dev/null +++ b/rtl/BPUTop/DelayN_1.sv @@ -0,0 +1,112 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module DelayN_1( + input clock, + input io_in_ubtb_enable, + input io_in_btb_enable, + input io_in_tage_enable, + input io_in_sc_enable, + input io_in_ras_enable, + output io_out_ubtb_enable, + output io_out_btb_enable, + output io_out_tage_enable, + output io_out_sc_enable, + output io_out_ras_enable +); + + reg REG_ubtb_enable; + reg REG_btb_enable; + reg REG_tage_enable; + reg REG_sc_enable; + reg REG_ras_enable; + always @(posedge clock) begin + REG_ubtb_enable <= io_in_ubtb_enable; + REG_btb_enable <= io_in_btb_enable; + REG_tage_enable <= io_in_tage_enable; + REG_sc_enable <= io_in_sc_enable; + REG_ras_enable <= io_in_ras_enable; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + REG_ubtb_enable = _RANDOM[/*Zero width*/ 1'b0][0]; + REG_btb_enable = _RANDOM[/*Zero width*/ 1'b0][1]; + REG_tage_enable = _RANDOM[/*Zero width*/ 1'b0][3]; + REG_sc_enable = _RANDOM[/*Zero width*/ 1'b0][4]; + REG_ras_enable = _RANDOM[/*Zero width*/ 1'b0][5]; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_out_ubtb_enable = REG_ubtb_enable; + assign io_out_btb_enable = REG_btb_enable; + assign io_out_tage_enable = REG_tage_enable; + assign io_out_sc_enable = REG_sc_enable; + assign io_out_ras_enable = REG_ras_enable; +endmodule + diff --git a/rtl/BPUTop/DelayN_2.sv b/rtl/BPUTop/DelayN_2.sv new file mode 100644 index 0000000..19d1710 --- /dev/null +++ b/rtl/BPUTop/DelayN_2.sv @@ -0,0 +1,102 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module DelayN_2( + input clock, + input [35:0] io_in, + output [35:0] io_out +); + + reg [35:0] REG; + reg [35:0] REG_1; + reg [35:0] REG_2; + reg [35:0] REG_3; + reg [35:0] REG_4; + always @(posedge clock) begin + REG <= io_in; + REG_1 <= REG; + REG_2 <= REG_1; + REG_3 <= REG_2; + REG_4 <= REG_3; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:5]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin + _RANDOM[i] = `RANDOM; + end + REG = {_RANDOM[3'h0], _RANDOM[3'h1][3:0]}; + REG_1 = {_RANDOM[3'h1][31:4], _RANDOM[3'h2][7:0]}; + REG_2 = {_RANDOM[3'h2][31:8], _RANDOM[3'h3][11:0]}; + REG_3 = {_RANDOM[3'h3][31:12], _RANDOM[3'h4][15:0]}; + REG_4 = {_RANDOM[3'h4][31:16], _RANDOM[3'h5][19:0]}; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_out = REG_4; +endmodule + diff --git a/rtl/BPUTop/DelayN_4.sv b/rtl/BPUTop/DelayN_4.sv new file mode 100644 index 0000000..22811fb --- /dev/null +++ b/rtl/BPUTop/DelayN_4.sv @@ -0,0 +1,91 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module DelayN_4( + input clock, + input io_in, + output io_out +); + + reg REG; + reg REG_1; + always @(posedge clock) begin + REG <= io_in; + REG_1 <= REG; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + REG = _RANDOM[/*Zero width*/ 1'b0][0]; + REG_1 = _RANDOM[/*Zero width*/ 1'b0][1]; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_out = REG_1; +endmodule + diff --git a/rtl/BPUTop/FTB.sv b/rtl/BPUTop/FTB.sv new file mode 100644 index 0000000..1774c6c --- /dev/null +++ b/rtl/BPUTop/FTB.sv @@ -0,0 +1,1644 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FTB( + input clock, + input reset, + input [35:0] io_reset_vector, + input [40:0] io_in_bits_s0_pc_0, + input [40:0] io_in_bits_s0_pc_1, + input [40:0] io_in_bits_s0_pc_2, + input [40:0] io_in_bits_s0_pc_3, + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, + output io_out_s2_full_pred_0_br_taken_mask_0, + output io_out_s2_full_pred_0_br_taken_mask_1, + output io_out_s2_full_pred_0_slot_valids_0, + output io_out_s2_full_pred_0_slot_valids_1, + output [40:0] io_out_s2_full_pred_0_targets_0, + output [40:0] io_out_s2_full_pred_0_targets_1, + output [40:0] io_out_s2_full_pred_0_jalr_target, + output [3:0] io_out_s2_full_pred_0_offsets_0, + output [3:0] io_out_s2_full_pred_0_offsets_1, + output [40:0] io_out_s2_full_pred_0_fallThroughAddr, + output io_out_s2_full_pred_0_is_br_sharing, + output io_out_s2_full_pred_0_hit, + output io_out_s2_full_pred_1_br_taken_mask_0, + output io_out_s2_full_pred_1_br_taken_mask_1, + output io_out_s2_full_pred_1_slot_valids_0, + output io_out_s2_full_pred_1_slot_valids_1, + output [40:0] io_out_s2_full_pred_1_targets_0, + output [40:0] io_out_s2_full_pred_1_targets_1, + output [40:0] io_out_s2_full_pred_1_jalr_target, + output [3:0] io_out_s2_full_pred_1_offsets_0, + output [3:0] io_out_s2_full_pred_1_offsets_1, + output [40:0] io_out_s2_full_pred_1_fallThroughAddr, + output io_out_s2_full_pred_1_is_br_sharing, + output io_out_s2_full_pred_1_hit, + output io_out_s2_full_pred_2_br_taken_mask_0, + output io_out_s2_full_pred_2_br_taken_mask_1, + output io_out_s2_full_pred_2_slot_valids_0, + output io_out_s2_full_pred_2_slot_valids_1, + output [40:0] io_out_s2_full_pred_2_targets_0, + output [40:0] io_out_s2_full_pred_2_targets_1, + output [40:0] io_out_s2_full_pred_2_jalr_target, + output [3:0] io_out_s2_full_pred_2_offsets_0, + output [3:0] io_out_s2_full_pred_2_offsets_1, + output [40:0] io_out_s2_full_pred_2_fallThroughAddr, + output io_out_s2_full_pred_2_is_jalr, + output io_out_s2_full_pred_2_is_call, + output io_out_s2_full_pred_2_is_ret, + output io_out_s2_full_pred_2_last_may_be_rvi_call, + output io_out_s2_full_pred_2_is_br_sharing, + output io_out_s2_full_pred_2_hit, + output io_out_s2_full_pred_3_br_taken_mask_0, + output io_out_s2_full_pred_3_br_taken_mask_1, + output io_out_s2_full_pred_3_slot_valids_0, + output io_out_s2_full_pred_3_slot_valids_1, + output [40:0] io_out_s2_full_pred_3_targets_0, + output [40:0] io_out_s2_full_pred_3_targets_1, + output [40:0] io_out_s2_full_pred_3_jalr_target, + output [3:0] io_out_s2_full_pred_3_offsets_0, + output [3:0] io_out_s2_full_pred_3_offsets_1, + output [40:0] io_out_s2_full_pred_3_fallThroughAddr, + output io_out_s2_full_pred_3_fallThroughErr, + output io_out_s2_full_pred_3_is_br_sharing, + output io_out_s2_full_pred_3_hit, + output io_out_s3_full_pred_0_br_taken_mask_0, + output io_out_s3_full_pred_0_br_taken_mask_1, + output io_out_s3_full_pred_0_slot_valids_0, + output io_out_s3_full_pred_0_slot_valids_1, + output [40:0] io_out_s3_full_pred_0_targets_0, + output [40:0] io_out_s3_full_pred_0_targets_1, + output [40:0] io_out_s3_full_pred_0_jalr_target, + output [40:0] io_out_s3_full_pred_0_fallThroughAddr, + output io_out_s3_full_pred_0_fallThroughErr, + output io_out_s3_full_pred_0_is_br_sharing, + output io_out_s3_full_pred_0_hit, + output io_out_s3_full_pred_1_br_taken_mask_0, + output io_out_s3_full_pred_1_br_taken_mask_1, + output io_out_s3_full_pred_1_slot_valids_0, + output io_out_s3_full_pred_1_slot_valids_1, + output [40:0] io_out_s3_full_pred_1_targets_0, + output [40:0] io_out_s3_full_pred_1_targets_1, + output [40:0] io_out_s3_full_pred_1_jalr_target, + output [40:0] io_out_s3_full_pred_1_fallThroughAddr, + output io_out_s3_full_pred_1_fallThroughErr, + output io_out_s3_full_pred_1_is_br_sharing, + output io_out_s3_full_pred_1_hit, + output io_out_s3_full_pred_2_br_taken_mask_0, + output io_out_s3_full_pred_2_br_taken_mask_1, + output io_out_s3_full_pred_2_slot_valids_0, + output io_out_s3_full_pred_2_slot_valids_1, + output [40:0] io_out_s3_full_pred_2_targets_0, + output [40:0] io_out_s3_full_pred_2_targets_1, + output [40:0] io_out_s3_full_pred_2_jalr_target, + output [40:0] io_out_s3_full_pred_2_fallThroughAddr, + output io_out_s3_full_pred_2_fallThroughErr, + output io_out_s3_full_pred_2_is_jalr, + output io_out_s3_full_pred_2_is_call, + output io_out_s3_full_pred_2_is_ret, + output io_out_s3_full_pred_2_is_br_sharing, + output io_out_s3_full_pred_2_hit, + output io_out_s3_full_pred_3_br_taken_mask_0, + output io_out_s3_full_pred_3_br_taken_mask_1, + output io_out_s3_full_pred_3_slot_valids_0, + output io_out_s3_full_pred_3_slot_valids_1, + output [40:0] io_out_s3_full_pred_3_targets_0, + output [40:0] io_out_s3_full_pred_3_targets_1, + output [40:0] io_out_s3_full_pred_3_jalr_target, + output [3:0] io_out_s3_full_pred_3_offsets_0, + output [3:0] io_out_s3_full_pred_3_offsets_1, + output [40:0] io_out_s3_full_pred_3_fallThroughAddr, + output io_out_s3_full_pred_3_fallThroughErr, + output io_out_s3_full_pred_3_is_br_sharing, + output io_out_s3_full_pred_3_hit, + output [222:0] io_out_last_stage_meta, + output io_out_last_stage_ftb_entry_valid, + output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, + output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, + output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, + output io_out_last_stage_ftb_entry_brSlots_0_sharing, + output io_out_last_stage_ftb_entry_brSlots_0_valid, + output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, + output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, + output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, + output io_out_last_stage_ftb_entry_tailSlot_sharing, + output io_out_last_stage_ftb_entry_tailSlot_valid, + output [3:0] io_out_last_stage_ftb_entry_pftAddr, + output io_out_last_stage_ftb_entry_carry, + output io_out_last_stage_ftb_entry_isCall, + output io_out_last_stage_ftb_entry_isRet, + output io_out_last_stage_ftb_entry_isJalr, + output io_out_last_stage_ftb_entry_last_may_be_rvi_call, + output io_out_last_stage_ftb_entry_always_taken_0, + output io_out_last_stage_ftb_entry_always_taken_1, + input io_ctrl_btb_enable, + input io_s0_fire_0, + input io_s0_fire_1, + input io_s0_fire_2, + input io_s0_fire_3, + input io_s1_fire_0, + input io_s1_fire_1, + input io_s1_fire_2, + input io_s1_fire_3, + input io_s2_fire_0, + input io_s2_fire_1, + input io_s2_fire_2, + input io_s2_fire_3, + output io_s1_ready, + input io_update_valid, + input [40:0] io_update_bits_pc, + input io_update_bits_ftb_entry_valid, + input [3:0] io_update_bits_ftb_entry_brSlots_0_offset, + input [11:0] io_update_bits_ftb_entry_brSlots_0_lower, + input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat, + input io_update_bits_ftb_entry_brSlots_0_sharing, + input io_update_bits_ftb_entry_brSlots_0_valid, + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, + input [19:0] io_update_bits_ftb_entry_tailSlot_lower, + input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat, + input io_update_bits_ftb_entry_tailSlot_sharing, + input io_update_bits_ftb_entry_tailSlot_valid, + input [3:0] io_update_bits_ftb_entry_pftAddr, + input io_update_bits_ftb_entry_carry, + input io_update_bits_ftb_entry_isCall, + input io_update_bits_ftb_entry_isRet, + input io_update_bits_ftb_entry_isJalr, + input io_update_bits_ftb_entry_last_may_be_rvi_call, + input io_update_bits_ftb_entry_always_taken_0, + input io_update_bits_ftb_entry_always_taken_1, + input io_update_bits_old_entry, + input [222:0] io_update_bits_meta, + output [5:0] io_perf_0_value, + output [5:0] io_perf_1_value +); + + wire _write_valid_delay_io_out; + wire _delay2_entry_pipMod_io_out_bits_valid; + wire [3:0] _delay2_entry_pipMod_io_out_bits_brSlots_0_offset; + wire [11:0] _delay2_entry_pipMod_io_out_bits_brSlots_0_lower; + wire [1:0] _delay2_entry_pipMod_io_out_bits_brSlots_0_tarStat; + wire _delay2_entry_pipMod_io_out_bits_brSlots_0_sharing; + wire _delay2_entry_pipMod_io_out_bits_brSlots_0_valid; + wire [3:0] _delay2_entry_pipMod_io_out_bits_tailSlot_offset; + wire [19:0] _delay2_entry_pipMod_io_out_bits_tailSlot_lower; + wire [1:0] _delay2_entry_pipMod_io_out_bits_tailSlot_tarStat; + wire _delay2_entry_pipMod_io_out_bits_tailSlot_sharing; + wire _delay2_entry_pipMod_io_out_bits_tailSlot_valid; + wire [3:0] _delay2_entry_pipMod_io_out_bits_pftAddr; + wire _delay2_entry_pipMod_io_out_bits_carry; + wire _delay2_entry_pipMod_io_out_bits_isCall; + wire _delay2_entry_pipMod_io_out_bits_isRet; + wire _delay2_entry_pipMod_io_out_bits_isJalr; + wire _delay2_entry_pipMod_io_out_bits_last_may_be_rvi_call; + wire _delay2_entry_pipMod_io_out_bits_always_taken_0; + wire _delay2_entry_pipMod_io_out_bits_always_taken_1; + wire [40:0] _delay2_pc_pipMod_io_out_bits; + wire _ftbBank_io_req_pc_ready; + wire _ftbBank_io_read_resp_valid; + wire [3:0] _ftbBank_io_read_resp_brSlots_0_offset; + wire [11:0] _ftbBank_io_read_resp_brSlots_0_lower; + wire [1:0] _ftbBank_io_read_resp_brSlots_0_tarStat; + wire _ftbBank_io_read_resp_brSlots_0_sharing; + wire _ftbBank_io_read_resp_brSlots_0_valid; + wire [3:0] _ftbBank_io_read_resp_tailSlot_offset; + wire [19:0] _ftbBank_io_read_resp_tailSlot_lower; + wire [1:0] _ftbBank_io_read_resp_tailSlot_tarStat; + wire _ftbBank_io_read_resp_tailSlot_sharing; + wire _ftbBank_io_read_resp_tailSlot_valid; + wire [3:0] _ftbBank_io_read_resp_pftAddr; + wire _ftbBank_io_read_resp_carry; + wire _ftbBank_io_read_resp_isCall; + wire _ftbBank_io_read_resp_isRet; + wire _ftbBank_io_read_resp_isJalr; + wire _ftbBank_io_read_resp_last_may_be_rvi_call; + wire _ftbBank_io_read_resp_always_taken_0; + wire _ftbBank_io_read_resp_always_taken_1; + wire _ftbBank_io_read_hits_valid; + wire [1:0] _ftbBank_io_read_hits_bits; + wire _ftbBank_io_update_hits_valid; + wire [1:0] _ftbBank_io_update_hits_bits; + wire [35:0] _reset_vector_delay_io_out; + reg [40:0] s1_pc_dup_0; + reg [40:0] s1_pc_dup_1; + reg [40:0] s1_pc_dup_2; + reg [40:0] s1_pc_dup_3; + reg [40:0] s2_pc_dup_0; + reg [40:0] s2_pc_dup_1; + reg [40:0] s2_pc_dup_2; + reg [40:0] s2_pc_dup_3; + reg [40:0] s3_pc_dup_0; + reg [40:0] s3_pc_dup_1; + reg [40:0] s3_pc_dup_2; + reg [40:0] s3_pc_dup_3; + reg REG; + reg REG_1; + reg s2_ftb_entry_dup_0_valid; + reg [3:0] s2_ftb_entry_dup_0_brSlots_0_offset; + reg [11:0] s2_ftb_entry_dup_0_brSlots_0_lower; + reg [1:0] s2_ftb_entry_dup_0_brSlots_0_tarStat; + reg s2_ftb_entry_dup_0_brSlots_0_sharing; + reg s2_ftb_entry_dup_0_brSlots_0_valid; + reg [3:0] s2_ftb_entry_dup_0_tailSlot_offset; + reg [19:0] s2_ftb_entry_dup_0_tailSlot_lower; + reg [1:0] s2_ftb_entry_dup_0_tailSlot_tarStat; + reg s2_ftb_entry_dup_0_tailSlot_sharing; + reg s2_ftb_entry_dup_0_tailSlot_valid; + reg [3:0] s2_ftb_entry_dup_0_pftAddr; + reg s2_ftb_entry_dup_0_carry; + reg s2_ftb_entry_dup_0_isCall; + reg s2_ftb_entry_dup_0_isRet; + reg s2_ftb_entry_dup_0_isJalr; + reg s2_ftb_entry_dup_0_last_may_be_rvi_call; + reg s2_ftb_entry_dup_0_always_taken_0; + reg s2_ftb_entry_dup_0_always_taken_1; + reg [3:0] s2_ftb_entry_dup_1_brSlots_0_offset; + reg [11:0] s2_ftb_entry_dup_1_brSlots_0_lower; + reg [1:0] s2_ftb_entry_dup_1_brSlots_0_tarStat; + reg s2_ftb_entry_dup_1_brSlots_0_valid; + reg [3:0] s2_ftb_entry_dup_1_tailSlot_offset; + reg [19:0] s2_ftb_entry_dup_1_tailSlot_lower; + reg [1:0] s2_ftb_entry_dup_1_tailSlot_tarStat; + reg s2_ftb_entry_dup_1_tailSlot_sharing; + reg s2_ftb_entry_dup_1_tailSlot_valid; + reg [3:0] s2_ftb_entry_dup_1_pftAddr; + reg s2_ftb_entry_dup_1_carry; + reg s2_ftb_entry_dup_1_always_taken_0; + reg s2_ftb_entry_dup_1_always_taken_1; + reg [3:0] s2_ftb_entry_dup_2_brSlots_0_offset; + reg [11:0] s2_ftb_entry_dup_2_brSlots_0_lower; + reg [1:0] s2_ftb_entry_dup_2_brSlots_0_tarStat; + reg s2_ftb_entry_dup_2_brSlots_0_valid; + reg [3:0] s2_ftb_entry_dup_2_tailSlot_offset; + reg [19:0] s2_ftb_entry_dup_2_tailSlot_lower; + reg [1:0] s2_ftb_entry_dup_2_tailSlot_tarStat; + reg s2_ftb_entry_dup_2_tailSlot_sharing; + reg s2_ftb_entry_dup_2_tailSlot_valid; + reg [3:0] s2_ftb_entry_dup_2_pftAddr; + reg s2_ftb_entry_dup_2_carry; + reg s2_ftb_entry_dup_2_isCall; + reg s2_ftb_entry_dup_2_isRet; + reg s2_ftb_entry_dup_2_isJalr; + reg s2_ftb_entry_dup_2_last_may_be_rvi_call; + reg s2_ftb_entry_dup_2_always_taken_0; + reg s2_ftb_entry_dup_2_always_taken_1; + reg [3:0] s2_ftb_entry_dup_3_brSlots_0_offset; + reg [11:0] s2_ftb_entry_dup_3_brSlots_0_lower; + reg [1:0] s2_ftb_entry_dup_3_brSlots_0_tarStat; + reg s2_ftb_entry_dup_3_brSlots_0_valid; + reg [3:0] s2_ftb_entry_dup_3_tailSlot_offset; + reg [19:0] s2_ftb_entry_dup_3_tailSlot_lower; + reg [1:0] s2_ftb_entry_dup_3_tailSlot_tarStat; + reg s2_ftb_entry_dup_3_tailSlot_sharing; + reg s2_ftb_entry_dup_3_tailSlot_valid; + reg [3:0] s2_ftb_entry_dup_3_pftAddr; + reg s2_ftb_entry_dup_3_carry; + reg s2_ftb_entry_dup_3_always_taken_0; + reg s2_ftb_entry_dup_3_always_taken_1; + reg s3_ftb_entry_dup_0_valid; + reg [3:0] s3_ftb_entry_dup_0_brSlots_0_offset; + reg [11:0] s3_ftb_entry_dup_0_brSlots_0_lower; + reg [1:0] s3_ftb_entry_dup_0_brSlots_0_tarStat; + reg s3_ftb_entry_dup_0_brSlots_0_sharing; + reg s3_ftb_entry_dup_0_brSlots_0_valid; + reg [3:0] s3_ftb_entry_dup_0_tailSlot_offset; + reg [19:0] s3_ftb_entry_dup_0_tailSlot_lower; + reg [1:0] s3_ftb_entry_dup_0_tailSlot_tarStat; + reg s3_ftb_entry_dup_0_tailSlot_sharing; + reg s3_ftb_entry_dup_0_tailSlot_valid; + reg [3:0] s3_ftb_entry_dup_0_pftAddr; + reg s3_ftb_entry_dup_0_carry; + reg s3_ftb_entry_dup_0_isCall; + reg s3_ftb_entry_dup_0_isRet; + reg s3_ftb_entry_dup_0_isJalr; + reg s3_ftb_entry_dup_0_last_may_be_rvi_call; + reg s3_ftb_entry_dup_0_always_taken_0; + reg s3_ftb_entry_dup_0_always_taken_1; + reg [11:0] s3_ftb_entry_dup_1_brSlots_0_lower; + reg [1:0] s3_ftb_entry_dup_1_brSlots_0_tarStat; + reg s3_ftb_entry_dup_1_brSlots_0_valid; + reg [19:0] s3_ftb_entry_dup_1_tailSlot_lower; + reg [1:0] s3_ftb_entry_dup_1_tailSlot_tarStat; + reg s3_ftb_entry_dup_1_tailSlot_sharing; + reg s3_ftb_entry_dup_1_tailSlot_valid; + reg [3:0] s3_ftb_entry_dup_1_pftAddr; + reg s3_ftb_entry_dup_1_carry; + reg s3_ftb_entry_dup_1_always_taken_0; + reg s3_ftb_entry_dup_1_always_taken_1; + reg [11:0] s3_ftb_entry_dup_2_brSlots_0_lower; + reg [1:0] s3_ftb_entry_dup_2_brSlots_0_tarStat; + reg s3_ftb_entry_dup_2_brSlots_0_valid; + reg [19:0] s3_ftb_entry_dup_2_tailSlot_lower; + reg [1:0] s3_ftb_entry_dup_2_tailSlot_tarStat; + reg s3_ftb_entry_dup_2_tailSlot_sharing; + reg s3_ftb_entry_dup_2_tailSlot_valid; + reg [3:0] s3_ftb_entry_dup_2_pftAddr; + reg s3_ftb_entry_dup_2_carry; + reg s3_ftb_entry_dup_2_isCall; + reg s3_ftb_entry_dup_2_isRet; + reg s3_ftb_entry_dup_2_isJalr; + reg s3_ftb_entry_dup_2_always_taken_0; + reg s3_ftb_entry_dup_2_always_taken_1; + reg [3:0] s3_ftb_entry_dup_3_brSlots_0_offset; + reg [11:0] s3_ftb_entry_dup_3_brSlots_0_lower; + reg [1:0] s3_ftb_entry_dup_3_brSlots_0_tarStat; + reg s3_ftb_entry_dup_3_brSlots_0_valid; + reg [3:0] s3_ftb_entry_dup_3_tailSlot_offset; + reg [19:0] s3_ftb_entry_dup_3_tailSlot_lower; + reg [1:0] s3_ftb_entry_dup_3_tailSlot_tarStat; + reg s3_ftb_entry_dup_3_tailSlot_sharing; + reg s3_ftb_entry_dup_3_tailSlot_valid; + reg [3:0] s3_ftb_entry_dup_3_pftAddr; + reg s3_ftb_entry_dup_3_carry; + reg s3_ftb_entry_dup_3_always_taken_0; + reg s3_ftb_entry_dup_3_always_taken_1; + wire s1_hit = _ftbBank_io_read_hits_valid & io_ctrl_btb_enable; + reg s2_hit_dup_0; + reg s2_hit_dup_1; + reg s2_hit_dup_2; + reg s2_hit_dup_3; + reg s3_hit_dup_0; + reg s3_hit_dup_1; + reg s3_hit_dup_2; + reg s3_hit_dup_3; + reg [27:0] higher_r; + reg [27:0] higher_plus_one_r; + reg [27:0] higher_minus_one_r; + reg [27:0] higher_r_1; + reg [27:0] higher_plus_one_r_1; + reg [27:0] higher_minus_one_r_1; + wire _target_T_18 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h1; + wire _target_T_19 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h2; + wire _target_T_20 = s2_ftb_entry_dup_0_tailSlot_tarStat == 2'h0; + reg [19:0] higher_r_2; + reg [19:0] higher_plus_one_r_2; + reg [19:0] higher_minus_one_r_2; + wire [40:0] io_out_s2_full_pred_0_targets_1_0 = + {s2_ftb_entry_dup_0_tailSlot_sharing + ? {(_target_T_18 ? higher_plus_one_r_1 : 28'h0) + | (_target_T_19 ? higher_minus_one_r_1 : 28'h0) + | (_target_T_20 ? higher_r_1 : 28'h0), + s2_ftb_entry_dup_0_tailSlot_lower[11:0]} + : {(_target_T_18 ? higher_plus_one_r_2 : 20'h0) + | (_target_T_19 ? higher_minus_one_r_2 : 20'h0) + | (_target_T_20 ? higher_r_2 : 20'h0), + s2_ftb_entry_dup_0_tailSlot_lower}, + 1'h0}; + reg io_out_s2_full_pred_0_fallThroughAddr_stashed_carry; + reg [27:0] higher_r_3; + reg [27:0] higher_plus_one_r_3; + reg [27:0] higher_minus_one_r_3; + reg [27:0] higher_r_4; + reg [27:0] higher_plus_one_r_4; + reg [27:0] higher_minus_one_r_4; + wire _target_T_45 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h1; + wire _target_T_46 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h2; + wire _target_T_47 = s2_ftb_entry_dup_1_tailSlot_tarStat == 2'h0; + reg [19:0] higher_r_5; + reg [19:0] higher_plus_one_r_5; + reg [19:0] higher_minus_one_r_5; + wire [40:0] io_out_s2_full_pred_1_targets_1_0 = + {s2_ftb_entry_dup_1_tailSlot_sharing + ? {(_target_T_45 ? higher_plus_one_r_4 : 28'h0) + | (_target_T_46 ? higher_minus_one_r_4 : 28'h0) + | (_target_T_47 ? higher_r_4 : 28'h0), + s2_ftb_entry_dup_1_tailSlot_lower[11:0]} + : {(_target_T_45 ? higher_plus_one_r_5 : 20'h0) + | (_target_T_46 ? higher_minus_one_r_5 : 20'h0) + | (_target_T_47 ? higher_r_5 : 20'h0), + s2_ftb_entry_dup_1_tailSlot_lower}, + 1'h0}; + reg io_out_s2_full_pred_1_fallThroughAddr_stashed_carry; + reg [27:0] higher_r_6; + reg [27:0] higher_plus_one_r_6; + reg [27:0] higher_minus_one_r_6; + reg [27:0] higher_r_7; + reg [27:0] higher_plus_one_r_7; + reg [27:0] higher_minus_one_r_7; + wire _target_T_72 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h1; + wire _target_T_73 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h2; + wire _target_T_74 = s2_ftb_entry_dup_2_tailSlot_tarStat == 2'h0; + reg [19:0] higher_r_8; + reg [19:0] higher_plus_one_r_8; + reg [19:0] higher_minus_one_r_8; + wire [40:0] io_out_s2_full_pred_2_targets_1_0 = + {s2_ftb_entry_dup_2_tailSlot_sharing + ? {(_target_T_72 ? higher_plus_one_r_7 : 28'h0) + | (_target_T_73 ? higher_minus_one_r_7 : 28'h0) + | (_target_T_74 ? higher_r_7 : 28'h0), + s2_ftb_entry_dup_2_tailSlot_lower[11:0]} + : {(_target_T_72 ? higher_plus_one_r_8 : 20'h0) + | (_target_T_73 ? higher_minus_one_r_8 : 20'h0) + | (_target_T_74 ? higher_r_8 : 20'h0), + s2_ftb_entry_dup_2_tailSlot_lower}, + 1'h0}; + reg io_out_s2_full_pred_2_fallThroughAddr_stashed_carry; + reg [27:0] higher_r_9; + reg [27:0] higher_plus_one_r_9; + reg [27:0] higher_minus_one_r_9; + reg [27:0] higher_r_10; + reg [27:0] higher_plus_one_r_10; + reg [27:0] higher_minus_one_r_10; + wire _target_T_99 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h1; + wire _target_T_100 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h2; + wire _target_T_101 = s2_ftb_entry_dup_3_tailSlot_tarStat == 2'h0; + reg [19:0] higher_r_11; + reg [19:0] higher_plus_one_r_11; + reg [19:0] higher_minus_one_r_11; + wire [40:0] io_out_s2_full_pred_3_targets_1_0 = + {s2_ftb_entry_dup_3_tailSlot_sharing + ? {(_target_T_99 ? higher_plus_one_r_10 : 28'h0) + | (_target_T_100 ? higher_minus_one_r_10 : 28'h0) + | (_target_T_101 ? higher_r_10 : 28'h0), + s2_ftb_entry_dup_3_tailSlot_lower[11:0]} + : {(_target_T_99 ? higher_plus_one_r_11 : 20'h0) + | (_target_T_100 ? higher_minus_one_r_11 : 20'h0) + | (_target_T_101 ? higher_r_11 : 20'h0), + s2_ftb_entry_dup_3_tailSlot_lower}, + 1'h0}; + wire io_out_s2_full_pred_3_fallThroughErr_0 = + {1'h0, s2_pc_dup_3[4:1]} >= {s2_ftb_entry_dup_3_carry, s2_ftb_entry_dup_3_pftAddr}; + reg io_out_s2_full_pred_3_fallThroughAddr_stashed_carry; + reg [27:0] higher_r_12; + reg [27:0] higher_plus_one_r_12; + reg [27:0] higher_minus_one_r_12; + reg [27:0] higher_r_13; + reg [27:0] higher_plus_one_r_13; + reg [27:0] higher_minus_one_r_13; + wire _target_T_126 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h1; + wire _target_T_127 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h2; + wire _target_T_128 = s3_ftb_entry_dup_0_tailSlot_tarStat == 2'h0; + reg [19:0] higher_r_14; + reg [19:0] higher_plus_one_r_14; + reg [19:0] higher_minus_one_r_14; + wire [40:0] io_out_s3_full_pred_0_targets_1_0 = + {s3_ftb_entry_dup_0_tailSlot_sharing + ? {(_target_T_126 ? higher_plus_one_r_13 : 28'h0) + | (_target_T_127 ? higher_minus_one_r_13 : 28'h0) + | (_target_T_128 ? higher_r_13 : 28'h0), + s3_ftb_entry_dup_0_tailSlot_lower[11:0]} + : {(_target_T_126 ? higher_plus_one_r_14 : 20'h0) + | (_target_T_127 ? higher_minus_one_r_14 : 20'h0) + | (_target_T_128 ? higher_r_14 : 20'h0), + s3_ftb_entry_dup_0_tailSlot_lower}, + 1'h0}; + wire io_out_s3_full_pred_0_fallThroughErr_0 = + {1'h0, s3_pc_dup_0[4:1]} >= {s3_ftb_entry_dup_0_carry, s3_ftb_entry_dup_0_pftAddr}; + reg [27:0] higher_r_15; + reg [27:0] higher_plus_one_r_15; + reg [27:0] higher_minus_one_r_15; + reg [27:0] higher_r_16; + reg [27:0] higher_plus_one_r_16; + reg [27:0] higher_minus_one_r_16; + wire _target_T_153 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h1; + wire _target_T_154 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h2; + wire _target_T_155 = s3_ftb_entry_dup_1_tailSlot_tarStat == 2'h0; + reg [19:0] higher_r_17; + reg [19:0] higher_plus_one_r_17; + reg [19:0] higher_minus_one_r_17; + wire [40:0] io_out_s3_full_pred_1_targets_1_0 = + {s3_ftb_entry_dup_1_tailSlot_sharing + ? {(_target_T_153 ? higher_plus_one_r_16 : 28'h0) + | (_target_T_154 ? higher_minus_one_r_16 : 28'h0) + | (_target_T_155 ? higher_r_16 : 28'h0), + s3_ftb_entry_dup_1_tailSlot_lower[11:0]} + : {(_target_T_153 ? higher_plus_one_r_17 : 20'h0) + | (_target_T_154 ? higher_minus_one_r_17 : 20'h0) + | (_target_T_155 ? higher_r_17 : 20'h0), + s3_ftb_entry_dup_1_tailSlot_lower}, + 1'h0}; + wire io_out_s3_full_pred_1_fallThroughErr_0 = + {1'h0, s3_pc_dup_1[4:1]} >= {s3_ftb_entry_dup_1_carry, s3_ftb_entry_dup_1_pftAddr}; + reg [27:0] higher_r_18; + reg [27:0] higher_plus_one_r_18; + reg [27:0] higher_minus_one_r_18; + reg [27:0] higher_r_19; + reg [27:0] higher_plus_one_r_19; + reg [27:0] higher_minus_one_r_19; + wire _target_T_180 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h1; + wire _target_T_181 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h2; + wire _target_T_182 = s3_ftb_entry_dup_2_tailSlot_tarStat == 2'h0; + reg [19:0] higher_r_20; + reg [19:0] higher_plus_one_r_20; + reg [19:0] higher_minus_one_r_20; + wire [40:0] io_out_s3_full_pred_2_targets_1_0 = + {s3_ftb_entry_dup_2_tailSlot_sharing + ? {(_target_T_180 ? higher_plus_one_r_19 : 28'h0) + | (_target_T_181 ? higher_minus_one_r_19 : 28'h0) + | (_target_T_182 ? higher_r_19 : 28'h0), + s3_ftb_entry_dup_2_tailSlot_lower[11:0]} + : {(_target_T_180 ? higher_plus_one_r_20 : 20'h0) + | (_target_T_181 ? higher_minus_one_r_20 : 20'h0) + | (_target_T_182 ? higher_r_20 : 20'h0), + s3_ftb_entry_dup_2_tailSlot_lower}, + 1'h0}; + wire io_out_s3_full_pred_2_fallThroughErr_0 = + {1'h0, s3_pc_dup_2[4:1]} >= {s3_ftb_entry_dup_2_carry, s3_ftb_entry_dup_2_pftAddr}; + reg [27:0] higher_r_21; + reg [27:0] higher_plus_one_r_21; + reg [27:0] higher_minus_one_r_21; + reg [27:0] higher_r_22; + reg [27:0] higher_plus_one_r_22; + reg [27:0] higher_minus_one_r_22; + wire _target_T_207 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h1; + wire _target_T_208 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h2; + wire _target_T_209 = s3_ftb_entry_dup_3_tailSlot_tarStat == 2'h0; + reg [19:0] higher_r_23; + reg [19:0] higher_plus_one_r_23; + reg [19:0] higher_minus_one_r_23; + wire [40:0] io_out_s3_full_pred_3_targets_1_0 = + {s3_ftb_entry_dup_3_tailSlot_sharing + ? {(_target_T_207 ? higher_plus_one_r_22 : 28'h0) + | (_target_T_208 ? higher_minus_one_r_22 : 28'h0) + | (_target_T_209 ? higher_r_22 : 28'h0), + s3_ftb_entry_dup_3_tailSlot_lower[11:0]} + : {(_target_T_207 ? higher_plus_one_r_23 : 20'h0) + | (_target_T_208 ? higher_minus_one_r_23 : 20'h0) + | (_target_T_209 ? higher_r_23 : 20'h0), + s3_ftb_entry_dup_3_tailSlot_lower}, + 1'h0}; + wire io_out_s3_full_pred_3_fallThroughErr_0 = + {1'h0, s3_pc_dup_3[4:1]} >= {s3_ftb_entry_dup_3_carry, s3_ftb_entry_dup_3_pftAddr}; + reg [2:0] io_out_last_stage_meta_r; + reg [2:0] io_out_last_stage_meta_r_1; + wire u_valid = io_update_valid & ~io_update_bits_old_entry; + wire update_now = u_valid & io_update_bits_meta[0]; + wire update_need_read = u_valid & ~(io_update_bits_meta[0]); + reg io_s1_ready_REG; + wire [40:0] _ftbBank_io_update_pc_T = + update_now ? io_update_bits_pc : _delay2_pc_pipMod_io_out_bits; + reg [1:0] ftbBank_io_update_write_way_REG; + reg ftbBank_io_update_write_alloc_REG; + reg io_perf_0_value_REG; + reg io_perf_0_value_REG_1; + reg io_perf_1_value_REG; + reg io_perf_1_value_REG_1; + wire [40:0] _GEN = {5'h0, _reset_vector_delay_io_out}; + always @(posedge clock) begin + if (REG_1) begin + s1_pc_dup_0 <= _GEN; + s1_pc_dup_1 <= _GEN; + s1_pc_dup_2 <= _GEN; + s1_pc_dup_3 <= _GEN; + end + else begin + if (io_s0_fire_0) + s1_pc_dup_0 <= io_in_bits_s0_pc_0; + if (io_s0_fire_1) + s1_pc_dup_1 <= io_in_bits_s0_pc_1; + if (io_s0_fire_2) + s1_pc_dup_2 <= io_in_bits_s0_pc_2; + if (io_s0_fire_3) + s1_pc_dup_3 <= io_in_bits_s0_pc_3; + end + if (io_s1_fire_0) begin + s2_pc_dup_0 <= s1_pc_dup_0; + s2_ftb_entry_dup_0_valid <= _ftbBank_io_read_resp_valid; + s2_ftb_entry_dup_0_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; + s2_ftb_entry_dup_0_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; + s2_ftb_entry_dup_0_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; + s2_ftb_entry_dup_0_brSlots_0_sharing <= _ftbBank_io_read_resp_brSlots_0_sharing; + s2_ftb_entry_dup_0_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; + s2_ftb_entry_dup_0_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; + s2_ftb_entry_dup_0_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; + s2_ftb_entry_dup_0_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; + s2_ftb_entry_dup_0_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; + s2_ftb_entry_dup_0_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; + s2_ftb_entry_dup_0_pftAddr <= _ftbBank_io_read_resp_pftAddr; + s2_ftb_entry_dup_0_carry <= _ftbBank_io_read_resp_carry; + s2_ftb_entry_dup_0_isCall <= _ftbBank_io_read_resp_isCall; + s2_ftb_entry_dup_0_isRet <= _ftbBank_io_read_resp_isRet; + s2_ftb_entry_dup_0_isJalr <= _ftbBank_io_read_resp_isJalr; + s2_ftb_entry_dup_0_last_may_be_rvi_call <= + _ftbBank_io_read_resp_last_may_be_rvi_call; + s2_ftb_entry_dup_0_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; + s2_ftb_entry_dup_0_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; + higher_r <= s1_pc_dup_0[40:13]; + higher_plus_one_r <= 28'(s1_pc_dup_0[40:13] + 28'h1); + higher_minus_one_r <= 28'(s1_pc_dup_0[40:13] - 28'h1); + higher_r_1 <= s1_pc_dup_0[40:13]; + higher_plus_one_r_1 <= 28'(s1_pc_dup_0[40:13] + 28'h1); + higher_minus_one_r_1 <= 28'(s1_pc_dup_0[40:13] - 28'h1); + higher_r_2 <= s1_pc_dup_0[40:21]; + higher_plus_one_r_2 <= 20'(s1_pc_dup_0[40:21] + 20'h1); + higher_minus_one_r_2 <= 20'(s1_pc_dup_0[40:21] - 20'h1); + io_out_s2_full_pred_0_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; + io_out_last_stage_meta_r <= {_ftbBank_io_read_hits_bits, s1_hit}; + end + if (io_s1_fire_1) begin + s2_pc_dup_1 <= s1_pc_dup_1; + s2_ftb_entry_dup_1_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; + s2_ftb_entry_dup_1_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; + s2_ftb_entry_dup_1_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; + s2_ftb_entry_dup_1_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; + s2_ftb_entry_dup_1_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; + s2_ftb_entry_dup_1_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; + s2_ftb_entry_dup_1_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; + s2_ftb_entry_dup_1_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; + s2_ftb_entry_dup_1_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; + s2_ftb_entry_dup_1_pftAddr <= _ftbBank_io_read_resp_pftAddr; + s2_ftb_entry_dup_1_carry <= _ftbBank_io_read_resp_carry; + s2_ftb_entry_dup_1_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; + s2_ftb_entry_dup_1_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; + higher_r_3 <= s1_pc_dup_1[40:13]; + higher_plus_one_r_3 <= 28'(s1_pc_dup_1[40:13] + 28'h1); + higher_minus_one_r_3 <= 28'(s1_pc_dup_1[40:13] - 28'h1); + higher_r_4 <= s1_pc_dup_1[40:13]; + higher_plus_one_r_4 <= 28'(s1_pc_dup_1[40:13] + 28'h1); + higher_minus_one_r_4 <= 28'(s1_pc_dup_1[40:13] - 28'h1); + higher_r_5 <= s1_pc_dup_1[40:21]; + higher_plus_one_r_5 <= 20'(s1_pc_dup_1[40:21] + 20'h1); + higher_minus_one_r_5 <= 20'(s1_pc_dup_1[40:21] - 20'h1); + io_out_s2_full_pred_1_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; + end + if (io_s1_fire_2) begin + s2_pc_dup_2 <= s1_pc_dup_2; + s2_ftb_entry_dup_2_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; + s2_ftb_entry_dup_2_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; + s2_ftb_entry_dup_2_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; + s2_ftb_entry_dup_2_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; + s2_ftb_entry_dup_2_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; + s2_ftb_entry_dup_2_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; + s2_ftb_entry_dup_2_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; + s2_ftb_entry_dup_2_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; + s2_ftb_entry_dup_2_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; + s2_ftb_entry_dup_2_pftAddr <= _ftbBank_io_read_resp_pftAddr; + s2_ftb_entry_dup_2_carry <= _ftbBank_io_read_resp_carry; + s2_ftb_entry_dup_2_isCall <= _ftbBank_io_read_resp_isCall; + s2_ftb_entry_dup_2_isRet <= _ftbBank_io_read_resp_isRet; + s2_ftb_entry_dup_2_isJalr <= _ftbBank_io_read_resp_isJalr; + s2_ftb_entry_dup_2_last_may_be_rvi_call <= + _ftbBank_io_read_resp_last_may_be_rvi_call; + s2_ftb_entry_dup_2_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; + s2_ftb_entry_dup_2_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; + higher_r_6 <= s1_pc_dup_2[40:13]; + higher_plus_one_r_6 <= 28'(s1_pc_dup_2[40:13] + 28'h1); + higher_minus_one_r_6 <= 28'(s1_pc_dup_2[40:13] - 28'h1); + higher_r_7 <= s1_pc_dup_2[40:13]; + higher_plus_one_r_7 <= 28'(s1_pc_dup_2[40:13] + 28'h1); + higher_minus_one_r_7 <= 28'(s1_pc_dup_2[40:13] - 28'h1); + higher_r_8 <= s1_pc_dup_2[40:21]; + higher_plus_one_r_8 <= 20'(s1_pc_dup_2[40:21] + 20'h1); + higher_minus_one_r_8 <= 20'(s1_pc_dup_2[40:21] - 20'h1); + io_out_s2_full_pred_2_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; + end + if (io_s1_fire_3) begin + s2_pc_dup_3 <= s1_pc_dup_3; + s2_ftb_entry_dup_3_brSlots_0_offset <= _ftbBank_io_read_resp_brSlots_0_offset; + s2_ftb_entry_dup_3_brSlots_0_lower <= _ftbBank_io_read_resp_brSlots_0_lower; + s2_ftb_entry_dup_3_brSlots_0_tarStat <= _ftbBank_io_read_resp_brSlots_0_tarStat; + s2_ftb_entry_dup_3_brSlots_0_valid <= _ftbBank_io_read_resp_brSlots_0_valid; + s2_ftb_entry_dup_3_tailSlot_offset <= _ftbBank_io_read_resp_tailSlot_offset; + s2_ftb_entry_dup_3_tailSlot_lower <= _ftbBank_io_read_resp_tailSlot_lower; + s2_ftb_entry_dup_3_tailSlot_tarStat <= _ftbBank_io_read_resp_tailSlot_tarStat; + s2_ftb_entry_dup_3_tailSlot_sharing <= _ftbBank_io_read_resp_tailSlot_sharing; + s2_ftb_entry_dup_3_tailSlot_valid <= _ftbBank_io_read_resp_tailSlot_valid; + s2_ftb_entry_dup_3_pftAddr <= _ftbBank_io_read_resp_pftAddr; + s2_ftb_entry_dup_3_carry <= _ftbBank_io_read_resp_carry; + s2_ftb_entry_dup_3_always_taken_0 <= _ftbBank_io_read_resp_always_taken_0; + s2_ftb_entry_dup_3_always_taken_1 <= _ftbBank_io_read_resp_always_taken_1; + higher_r_9 <= s1_pc_dup_3[40:13]; + higher_plus_one_r_9 <= 28'(s1_pc_dup_3[40:13] + 28'h1); + higher_minus_one_r_9 <= 28'(s1_pc_dup_3[40:13] - 28'h1); + higher_r_10 <= s1_pc_dup_3[40:13]; + higher_plus_one_r_10 <= 28'(s1_pc_dup_3[40:13] + 28'h1); + higher_minus_one_r_10 <= 28'(s1_pc_dup_3[40:13] - 28'h1); + higher_r_11 <= s1_pc_dup_3[40:21]; + higher_plus_one_r_11 <= 20'(s1_pc_dup_3[40:21] + 20'h1); + higher_minus_one_r_11 <= 20'(s1_pc_dup_3[40:21] - 20'h1); + io_out_s2_full_pred_3_fallThroughAddr_stashed_carry <= _ftbBank_io_read_resp_carry; + end + if (io_s2_fire_0) begin + s3_pc_dup_0 <= s2_pc_dup_0; + s3_ftb_entry_dup_0_valid <= s2_ftb_entry_dup_0_valid; + s3_ftb_entry_dup_0_brSlots_0_offset <= s2_ftb_entry_dup_0_brSlots_0_offset; + s3_ftb_entry_dup_0_brSlots_0_lower <= s2_ftb_entry_dup_0_brSlots_0_lower; + s3_ftb_entry_dup_0_brSlots_0_tarStat <= s2_ftb_entry_dup_0_brSlots_0_tarStat; + s3_ftb_entry_dup_0_brSlots_0_sharing <= s2_ftb_entry_dup_0_brSlots_0_sharing; + s3_ftb_entry_dup_0_brSlots_0_valid <= s2_ftb_entry_dup_0_brSlots_0_valid; + s3_ftb_entry_dup_0_tailSlot_offset <= s2_ftb_entry_dup_0_tailSlot_offset; + s3_ftb_entry_dup_0_tailSlot_lower <= s2_ftb_entry_dup_0_tailSlot_lower; + s3_ftb_entry_dup_0_tailSlot_tarStat <= s2_ftb_entry_dup_0_tailSlot_tarStat; + s3_ftb_entry_dup_0_tailSlot_sharing <= s2_ftb_entry_dup_0_tailSlot_sharing; + s3_ftb_entry_dup_0_tailSlot_valid <= s2_ftb_entry_dup_0_tailSlot_valid; + s3_ftb_entry_dup_0_pftAddr <= s2_ftb_entry_dup_0_pftAddr; + s3_ftb_entry_dup_0_carry <= s2_ftb_entry_dup_0_carry; + s3_ftb_entry_dup_0_isCall <= s2_ftb_entry_dup_0_isCall; + s3_ftb_entry_dup_0_isRet <= s2_ftb_entry_dup_0_isRet; + s3_ftb_entry_dup_0_isJalr <= s2_ftb_entry_dup_0_isJalr; + s3_ftb_entry_dup_0_last_may_be_rvi_call <= s2_ftb_entry_dup_0_last_may_be_rvi_call; + s3_ftb_entry_dup_0_always_taken_0 <= s2_ftb_entry_dup_0_always_taken_0; + s3_ftb_entry_dup_0_always_taken_1 <= s2_ftb_entry_dup_0_always_taken_1; + higher_r_12 <= s2_pc_dup_0[40:13]; + higher_plus_one_r_12 <= 28'(s2_pc_dup_0[40:13] + 28'h1); + higher_minus_one_r_12 <= 28'(s2_pc_dup_0[40:13] - 28'h1); + higher_r_13 <= s2_pc_dup_0[40:13]; + higher_plus_one_r_13 <= 28'(s2_pc_dup_0[40:13] + 28'h1); + higher_minus_one_r_13 <= 28'(s2_pc_dup_0[40:13] - 28'h1); + higher_r_14 <= s2_pc_dup_0[40:21]; + higher_plus_one_r_14 <= 20'(s2_pc_dup_0[40:21] + 20'h1); + higher_minus_one_r_14 <= 20'(s2_pc_dup_0[40:21] - 20'h1); + io_out_last_stage_meta_r_1 <= io_out_last_stage_meta_r; + end + if (io_s2_fire_1) begin + s3_pc_dup_1 <= s2_pc_dup_1; + s3_ftb_entry_dup_1_brSlots_0_lower <= s2_ftb_entry_dup_1_brSlots_0_lower; + s3_ftb_entry_dup_1_brSlots_0_tarStat <= s2_ftb_entry_dup_1_brSlots_0_tarStat; + s3_ftb_entry_dup_1_brSlots_0_valid <= s2_ftb_entry_dup_1_brSlots_0_valid; + s3_ftb_entry_dup_1_tailSlot_lower <= s2_ftb_entry_dup_1_tailSlot_lower; + s3_ftb_entry_dup_1_tailSlot_tarStat <= s2_ftb_entry_dup_1_tailSlot_tarStat; + s3_ftb_entry_dup_1_tailSlot_sharing <= s2_ftb_entry_dup_1_tailSlot_sharing; + s3_ftb_entry_dup_1_tailSlot_valid <= s2_ftb_entry_dup_1_tailSlot_valid; + s3_ftb_entry_dup_1_pftAddr <= s2_ftb_entry_dup_1_pftAddr; + s3_ftb_entry_dup_1_carry <= s2_ftb_entry_dup_1_carry; + s3_ftb_entry_dup_1_always_taken_0 <= s2_ftb_entry_dup_1_always_taken_0; + s3_ftb_entry_dup_1_always_taken_1 <= s2_ftb_entry_dup_1_always_taken_1; + higher_r_15 <= s2_pc_dup_1[40:13]; + higher_plus_one_r_15 <= 28'(s2_pc_dup_1[40:13] + 28'h1); + higher_minus_one_r_15 <= 28'(s2_pc_dup_1[40:13] - 28'h1); + higher_r_16 <= s2_pc_dup_1[40:13]; + higher_plus_one_r_16 <= 28'(s2_pc_dup_1[40:13] + 28'h1); + higher_minus_one_r_16 <= 28'(s2_pc_dup_1[40:13] - 28'h1); + higher_r_17 <= s2_pc_dup_1[40:21]; + higher_plus_one_r_17 <= 20'(s2_pc_dup_1[40:21] + 20'h1); + higher_minus_one_r_17 <= 20'(s2_pc_dup_1[40:21] - 20'h1); + end + if (io_s2_fire_2) begin + s3_pc_dup_2 <= s2_pc_dup_2; + s3_ftb_entry_dup_2_brSlots_0_lower <= s2_ftb_entry_dup_2_brSlots_0_lower; + s3_ftb_entry_dup_2_brSlots_0_tarStat <= s2_ftb_entry_dup_2_brSlots_0_tarStat; + s3_ftb_entry_dup_2_brSlots_0_valid <= s2_ftb_entry_dup_2_brSlots_0_valid; + s3_ftb_entry_dup_2_tailSlot_lower <= s2_ftb_entry_dup_2_tailSlot_lower; + s3_ftb_entry_dup_2_tailSlot_tarStat <= s2_ftb_entry_dup_2_tailSlot_tarStat; + s3_ftb_entry_dup_2_tailSlot_sharing <= s2_ftb_entry_dup_2_tailSlot_sharing; + s3_ftb_entry_dup_2_tailSlot_valid <= s2_ftb_entry_dup_2_tailSlot_valid; + s3_ftb_entry_dup_2_pftAddr <= s2_ftb_entry_dup_2_pftAddr; + s3_ftb_entry_dup_2_carry <= s2_ftb_entry_dup_2_carry; + s3_ftb_entry_dup_2_isCall <= s2_ftb_entry_dup_2_isCall; + s3_ftb_entry_dup_2_isRet <= s2_ftb_entry_dup_2_isRet; + s3_ftb_entry_dup_2_isJalr <= s2_ftb_entry_dup_2_isJalr; + s3_ftb_entry_dup_2_always_taken_0 <= s2_ftb_entry_dup_2_always_taken_0; + s3_ftb_entry_dup_2_always_taken_1 <= s2_ftb_entry_dup_2_always_taken_1; + higher_r_18 <= s2_pc_dup_2[40:13]; + higher_plus_one_r_18 <= 28'(s2_pc_dup_2[40:13] + 28'h1); + higher_minus_one_r_18 <= 28'(s2_pc_dup_2[40:13] - 28'h1); + higher_r_19 <= s2_pc_dup_2[40:13]; + higher_plus_one_r_19 <= 28'(s2_pc_dup_2[40:13] + 28'h1); + higher_minus_one_r_19 <= 28'(s2_pc_dup_2[40:13] - 28'h1); + higher_r_20 <= s2_pc_dup_2[40:21]; + higher_plus_one_r_20 <= 20'(s2_pc_dup_2[40:21] + 20'h1); + higher_minus_one_r_20 <= 20'(s2_pc_dup_2[40:21] - 20'h1); + end + if (io_s2_fire_3) begin + s3_pc_dup_3 <= s2_pc_dup_3; + s3_ftb_entry_dup_3_brSlots_0_offset <= s2_ftb_entry_dup_3_brSlots_0_offset; + s3_ftb_entry_dup_3_brSlots_0_lower <= s2_ftb_entry_dup_3_brSlots_0_lower; + s3_ftb_entry_dup_3_brSlots_0_tarStat <= s2_ftb_entry_dup_3_brSlots_0_tarStat; + s3_ftb_entry_dup_3_brSlots_0_valid <= s2_ftb_entry_dup_3_brSlots_0_valid; + s3_ftb_entry_dup_3_tailSlot_offset <= s2_ftb_entry_dup_3_tailSlot_offset; + s3_ftb_entry_dup_3_tailSlot_lower <= s2_ftb_entry_dup_3_tailSlot_lower; + s3_ftb_entry_dup_3_tailSlot_tarStat <= s2_ftb_entry_dup_3_tailSlot_tarStat; + s3_ftb_entry_dup_3_tailSlot_sharing <= s2_ftb_entry_dup_3_tailSlot_sharing; + s3_ftb_entry_dup_3_tailSlot_valid <= s2_ftb_entry_dup_3_tailSlot_valid; + s3_ftb_entry_dup_3_pftAddr <= s2_ftb_entry_dup_3_pftAddr; + s3_ftb_entry_dup_3_carry <= s2_ftb_entry_dup_3_carry; + s3_ftb_entry_dup_3_always_taken_0 <= s2_ftb_entry_dup_3_always_taken_0; + s3_ftb_entry_dup_3_always_taken_1 <= s2_ftb_entry_dup_3_always_taken_1; + higher_r_21 <= s2_pc_dup_3[40:13]; + higher_plus_one_r_21 <= 28'(s2_pc_dup_3[40:13] + 28'h1); + higher_minus_one_r_21 <= 28'(s2_pc_dup_3[40:13] - 28'h1); + higher_r_22 <= s2_pc_dup_3[40:13]; + higher_plus_one_r_22 <= 28'(s2_pc_dup_3[40:13] + 28'h1); + higher_minus_one_r_22 <= 28'(s2_pc_dup_3[40:13] - 28'h1); + higher_r_23 <= s2_pc_dup_3[40:21]; + higher_plus_one_r_23 <= 20'(s2_pc_dup_3[40:21] + 20'h1); + higher_minus_one_r_23 <= 20'(s2_pc_dup_3[40:21] - 20'h1); + end + REG <= reset; + REG_1 <= REG & ~reset; + io_s1_ready_REG <= update_need_read; + ftbBank_io_update_write_way_REG <= _ftbBank_io_update_hits_bits; + ftbBank_io_update_write_alloc_REG <= ~_ftbBank_io_update_hits_valid; + io_perf_0_value_REG <= io_update_valid & io_update_bits_meta[0]; + io_perf_0_value_REG_1 <= io_perf_0_value_REG; + io_perf_1_value_REG <= io_update_valid & ~(io_update_bits_meta[0]); + io_perf_1_value_REG_1 <= io_perf_1_value_REG; + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) begin + s2_hit_dup_0 <= 1'h0; + s2_hit_dup_1 <= 1'h0; + s2_hit_dup_2 <= 1'h0; + s2_hit_dup_3 <= 1'h0; + s3_hit_dup_0 <= 1'h0; + s3_hit_dup_1 <= 1'h0; + s3_hit_dup_2 <= 1'h0; + s3_hit_dup_3 <= 1'h0; + end + else begin + if (io_s1_fire_0) + s2_hit_dup_0 <= s1_hit; + if (io_s1_fire_1) + s2_hit_dup_1 <= s1_hit; + if (io_s1_fire_2) + s2_hit_dup_2 <= s1_hit; + if (io_s1_fire_3) + s2_hit_dup_3 <= s1_hit; + if (io_s2_fire_0) + s3_hit_dup_0 <= s2_hit_dup_0; + if (io_s2_fire_1) + s3_hit_dup_1 <= s2_hit_dup_1; + if (io_s2_fire_2) + s3_hit_dup_2 <= s2_hit_dup_2; + if (io_s2_fire_3) + s3_hit_dup_3 <= s2_hit_dup_3; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:90]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [6:0] i = 7'h0; i < 7'h5B; i += 7'h1) begin + _RANDOM[i] = `RANDOM; + end + s1_pc_dup_0 = {_RANDOM[7'h0], _RANDOM[7'h1][8:0]}; + s1_pc_dup_1 = {_RANDOM[7'h1][31:9], _RANDOM[7'h2][17:0]}; + s1_pc_dup_2 = {_RANDOM[7'h2][31:18], _RANDOM[7'h3][26:0]}; + s1_pc_dup_3 = {_RANDOM[7'h3][31:27], _RANDOM[7'h4], _RANDOM[7'h5][3:0]}; + s2_pc_dup_0 = {_RANDOM[7'h5][31:4], _RANDOM[7'h6][12:0]}; + s2_pc_dup_1 = {_RANDOM[7'h6][31:13], _RANDOM[7'h7][21:0]}; + s2_pc_dup_2 = {_RANDOM[7'h7][31:22], _RANDOM[7'h8][30:0]}; + s2_pc_dup_3 = {_RANDOM[7'h8][31], _RANDOM[7'h9], _RANDOM[7'hA][7:0]}; + s3_pc_dup_0 = {_RANDOM[7'hA][31:8], _RANDOM[7'hB][16:0]}; + s3_pc_dup_1 = {_RANDOM[7'hB][31:17], _RANDOM[7'hC][25:0]}; + s3_pc_dup_2 = {_RANDOM[7'hC][31:26], _RANDOM[7'hD], _RANDOM[7'hE][2:0]}; + s3_pc_dup_3 = {_RANDOM[7'hE][31:3], _RANDOM[7'hF][11:0]}; + REG = _RANDOM[7'hF][12]; + REG_1 = _RANDOM[7'hF][13]; + s2_ftb_entry_dup_0_valid = _RANDOM[7'hF][15]; + s2_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'hF][19:16]; + s2_ftb_entry_dup_0_brSlots_0_lower = _RANDOM[7'hF][31:20]; + s2_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'h10][1:0]; + s2_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'h10][2]; + s2_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'h10][3]; + s2_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'h10][7:4]; + s2_ftb_entry_dup_0_tailSlot_lower = _RANDOM[7'h10][27:8]; + s2_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h10][29:28]; + s2_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h10][30]; + s2_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h10][31]; + s2_ftb_entry_dup_0_pftAddr = _RANDOM[7'h11][3:0]; + s2_ftb_entry_dup_0_carry = _RANDOM[7'h11][4]; + s2_ftb_entry_dup_0_isCall = _RANDOM[7'h11][5]; + s2_ftb_entry_dup_0_isRet = _RANDOM[7'h11][6]; + s2_ftb_entry_dup_0_isJalr = _RANDOM[7'h11][7]; + s2_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h11][8]; + s2_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h11][9]; + s2_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h11][10]; + s2_ftb_entry_dup_1_brSlots_0_offset = _RANDOM[7'h11][15:12]; + s2_ftb_entry_dup_1_brSlots_0_lower = _RANDOM[7'h11][27:16]; + s2_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h11][29:28]; + s2_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h11][31]; + s2_ftb_entry_dup_1_tailSlot_offset = _RANDOM[7'h12][3:0]; + s2_ftb_entry_dup_1_tailSlot_lower = _RANDOM[7'h12][23:4]; + s2_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h12][25:24]; + s2_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h12][26]; + s2_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h12][27]; + s2_ftb_entry_dup_1_pftAddr = _RANDOM[7'h12][31:28]; + s2_ftb_entry_dup_1_carry = _RANDOM[7'h13][0]; + s2_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h13][5]; + s2_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h13][6]; + s2_ftb_entry_dup_2_brSlots_0_offset = _RANDOM[7'h13][11:8]; + s2_ftb_entry_dup_2_brSlots_0_lower = _RANDOM[7'h13][23:12]; + s2_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h13][25:24]; + s2_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h13][27]; + s2_ftb_entry_dup_2_tailSlot_offset = _RANDOM[7'h13][31:28]; + s2_ftb_entry_dup_2_tailSlot_lower = _RANDOM[7'h14][19:0]; + s2_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h14][21:20]; + s2_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h14][22]; + s2_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h14][23]; + s2_ftb_entry_dup_2_pftAddr = _RANDOM[7'h14][27:24]; + s2_ftb_entry_dup_2_carry = _RANDOM[7'h14][28]; + s2_ftb_entry_dup_2_isCall = _RANDOM[7'h14][29]; + s2_ftb_entry_dup_2_isRet = _RANDOM[7'h14][30]; + s2_ftb_entry_dup_2_isJalr = _RANDOM[7'h14][31]; + s2_ftb_entry_dup_2_last_may_be_rvi_call = _RANDOM[7'h15][0]; + s2_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h15][1]; + s2_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h15][2]; + s2_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h15][7:4]; + s2_ftb_entry_dup_3_brSlots_0_lower = _RANDOM[7'h15][19:8]; + s2_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h15][21:20]; + s2_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h15][23]; + s2_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h15][27:24]; + s2_ftb_entry_dup_3_tailSlot_lower = {_RANDOM[7'h15][31:28], _RANDOM[7'h16][15:0]}; + s2_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h16][17:16]; + s2_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h16][18]; + s2_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h16][19]; + s2_ftb_entry_dup_3_pftAddr = _RANDOM[7'h16][23:20]; + s2_ftb_entry_dup_3_carry = _RANDOM[7'h16][24]; + s2_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h16][29]; + s2_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h16][30]; + s3_ftb_entry_dup_0_valid = _RANDOM[7'h16][31]; + s3_ftb_entry_dup_0_brSlots_0_offset = _RANDOM[7'h17][3:0]; + s3_ftb_entry_dup_0_brSlots_0_lower = _RANDOM[7'h17][15:4]; + s3_ftb_entry_dup_0_brSlots_0_tarStat = _RANDOM[7'h17][17:16]; + s3_ftb_entry_dup_0_brSlots_0_sharing = _RANDOM[7'h17][18]; + s3_ftb_entry_dup_0_brSlots_0_valid = _RANDOM[7'h17][19]; + s3_ftb_entry_dup_0_tailSlot_offset = _RANDOM[7'h17][23:20]; + s3_ftb_entry_dup_0_tailSlot_lower = {_RANDOM[7'h17][31:24], _RANDOM[7'h18][11:0]}; + s3_ftb_entry_dup_0_tailSlot_tarStat = _RANDOM[7'h18][13:12]; + s3_ftb_entry_dup_0_tailSlot_sharing = _RANDOM[7'h18][14]; + s3_ftb_entry_dup_0_tailSlot_valid = _RANDOM[7'h18][15]; + s3_ftb_entry_dup_0_pftAddr = _RANDOM[7'h18][19:16]; + s3_ftb_entry_dup_0_carry = _RANDOM[7'h18][20]; + s3_ftb_entry_dup_0_isCall = _RANDOM[7'h18][21]; + s3_ftb_entry_dup_0_isRet = _RANDOM[7'h18][22]; + s3_ftb_entry_dup_0_isJalr = _RANDOM[7'h18][23]; + s3_ftb_entry_dup_0_last_may_be_rvi_call = _RANDOM[7'h18][24]; + s3_ftb_entry_dup_0_always_taken_0 = _RANDOM[7'h18][25]; + s3_ftb_entry_dup_0_always_taken_1 = _RANDOM[7'h18][26]; + s3_ftb_entry_dup_1_brSlots_0_lower = _RANDOM[7'h19][11:0]; + s3_ftb_entry_dup_1_brSlots_0_tarStat = _RANDOM[7'h19][13:12]; + s3_ftb_entry_dup_1_brSlots_0_valid = _RANDOM[7'h19][15]; + s3_ftb_entry_dup_1_tailSlot_lower = {_RANDOM[7'h19][31:20], _RANDOM[7'h1A][7:0]}; + s3_ftb_entry_dup_1_tailSlot_tarStat = _RANDOM[7'h1A][9:8]; + s3_ftb_entry_dup_1_tailSlot_sharing = _RANDOM[7'h1A][10]; + s3_ftb_entry_dup_1_tailSlot_valid = _RANDOM[7'h1A][11]; + s3_ftb_entry_dup_1_pftAddr = _RANDOM[7'h1A][15:12]; + s3_ftb_entry_dup_1_carry = _RANDOM[7'h1A][16]; + s3_ftb_entry_dup_1_always_taken_0 = _RANDOM[7'h1A][21]; + s3_ftb_entry_dup_1_always_taken_1 = _RANDOM[7'h1A][22]; + s3_ftb_entry_dup_2_brSlots_0_lower = {_RANDOM[7'h1A][31:28], _RANDOM[7'h1B][7:0]}; + s3_ftb_entry_dup_2_brSlots_0_tarStat = _RANDOM[7'h1B][9:8]; + s3_ftb_entry_dup_2_brSlots_0_valid = _RANDOM[7'h1B][11]; + s3_ftb_entry_dup_2_tailSlot_lower = {_RANDOM[7'h1B][31:16], _RANDOM[7'h1C][3:0]}; + s3_ftb_entry_dup_2_tailSlot_tarStat = _RANDOM[7'h1C][5:4]; + s3_ftb_entry_dup_2_tailSlot_sharing = _RANDOM[7'h1C][6]; + s3_ftb_entry_dup_2_tailSlot_valid = _RANDOM[7'h1C][7]; + s3_ftb_entry_dup_2_pftAddr = _RANDOM[7'h1C][11:8]; + s3_ftb_entry_dup_2_carry = _RANDOM[7'h1C][12]; + s3_ftb_entry_dup_2_isCall = _RANDOM[7'h1C][13]; + s3_ftb_entry_dup_2_isRet = _RANDOM[7'h1C][14]; + s3_ftb_entry_dup_2_isJalr = _RANDOM[7'h1C][15]; + s3_ftb_entry_dup_2_always_taken_0 = _RANDOM[7'h1C][17]; + s3_ftb_entry_dup_2_always_taken_1 = _RANDOM[7'h1C][18]; + s3_ftb_entry_dup_3_brSlots_0_offset = _RANDOM[7'h1C][23:20]; + s3_ftb_entry_dup_3_brSlots_0_lower = {_RANDOM[7'h1C][31:24], _RANDOM[7'h1D][3:0]}; + s3_ftb_entry_dup_3_brSlots_0_tarStat = _RANDOM[7'h1D][5:4]; + s3_ftb_entry_dup_3_brSlots_0_valid = _RANDOM[7'h1D][7]; + s3_ftb_entry_dup_3_tailSlot_offset = _RANDOM[7'h1D][11:8]; + s3_ftb_entry_dup_3_tailSlot_lower = _RANDOM[7'h1D][31:12]; + s3_ftb_entry_dup_3_tailSlot_tarStat = _RANDOM[7'h1E][1:0]; + s3_ftb_entry_dup_3_tailSlot_sharing = _RANDOM[7'h1E][2]; + s3_ftb_entry_dup_3_tailSlot_valid = _RANDOM[7'h1E][3]; + s3_ftb_entry_dup_3_pftAddr = _RANDOM[7'h1E][7:4]; + s3_ftb_entry_dup_3_carry = _RANDOM[7'h1E][8]; + s3_ftb_entry_dup_3_always_taken_0 = _RANDOM[7'h1E][13]; + s3_ftb_entry_dup_3_always_taken_1 = _RANDOM[7'h1E][14]; + s2_hit_dup_0 = _RANDOM[7'h1E][15]; + s2_hit_dup_1 = _RANDOM[7'h1E][16]; + s2_hit_dup_2 = _RANDOM[7'h1E][17]; + s2_hit_dup_3 = _RANDOM[7'h1E][18]; + s3_hit_dup_0 = _RANDOM[7'h1E][19]; + s3_hit_dup_1 = _RANDOM[7'h1E][20]; + s3_hit_dup_2 = _RANDOM[7'h1E][21]; + s3_hit_dup_3 = _RANDOM[7'h1E][22]; + higher_r = {_RANDOM[7'h1E][31:23], _RANDOM[7'h1F][18:0]}; + higher_plus_one_r = {_RANDOM[7'h1F][31:19], _RANDOM[7'h20][14:0]}; + higher_minus_one_r = {_RANDOM[7'h20][31:15], _RANDOM[7'h21][10:0]}; + higher_r_1 = {_RANDOM[7'h21][31:11], _RANDOM[7'h22][6:0]}; + higher_plus_one_r_1 = {_RANDOM[7'h22][31:7], _RANDOM[7'h23][2:0]}; + higher_minus_one_r_1 = _RANDOM[7'h23][30:3]; + higher_r_2 = {_RANDOM[7'h23][31], _RANDOM[7'h24][18:0]}; + higher_plus_one_r_2 = {_RANDOM[7'h24][31:19], _RANDOM[7'h25][6:0]}; + higher_minus_one_r_2 = _RANDOM[7'h25][26:7]; + io_out_s2_full_pred_0_fallThroughAddr_stashed_carry = _RANDOM[7'h25][27]; + higher_r_3 = {_RANDOM[7'h25][31:28], _RANDOM[7'h26][23:0]}; + higher_plus_one_r_3 = {_RANDOM[7'h26][31:24], _RANDOM[7'h27][19:0]}; + higher_minus_one_r_3 = {_RANDOM[7'h27][31:20], _RANDOM[7'h28][15:0]}; + higher_r_4 = {_RANDOM[7'h28][31:16], _RANDOM[7'h29][11:0]}; + higher_plus_one_r_4 = {_RANDOM[7'h29][31:12], _RANDOM[7'h2A][7:0]}; + higher_minus_one_r_4 = {_RANDOM[7'h2A][31:8], _RANDOM[7'h2B][3:0]}; + higher_r_5 = _RANDOM[7'h2B][23:4]; + higher_plus_one_r_5 = {_RANDOM[7'h2B][31:24], _RANDOM[7'h2C][11:0]}; + higher_minus_one_r_5 = _RANDOM[7'h2C][31:12]; + io_out_s2_full_pred_1_fallThroughAddr_stashed_carry = _RANDOM[7'h2D][0]; + higher_r_6 = _RANDOM[7'h2D][28:1]; + higher_plus_one_r_6 = {_RANDOM[7'h2D][31:29], _RANDOM[7'h2E][24:0]}; + higher_minus_one_r_6 = {_RANDOM[7'h2E][31:25], _RANDOM[7'h2F][20:0]}; + higher_r_7 = {_RANDOM[7'h2F][31:21], _RANDOM[7'h30][16:0]}; + higher_plus_one_r_7 = {_RANDOM[7'h30][31:17], _RANDOM[7'h31][12:0]}; + higher_minus_one_r_7 = {_RANDOM[7'h31][31:13], _RANDOM[7'h32][8:0]}; + higher_r_8 = _RANDOM[7'h32][28:9]; + higher_plus_one_r_8 = {_RANDOM[7'h32][31:29], _RANDOM[7'h33][16:0]}; + higher_minus_one_r_8 = {_RANDOM[7'h33][31:17], _RANDOM[7'h34][4:0]}; + io_out_s2_full_pred_2_fallThroughAddr_stashed_carry = _RANDOM[7'h34][5]; + higher_r_9 = {_RANDOM[7'h34][31:6], _RANDOM[7'h35][1:0]}; + higher_plus_one_r_9 = _RANDOM[7'h35][29:2]; + higher_minus_one_r_9 = {_RANDOM[7'h35][31:30], _RANDOM[7'h36][25:0]}; + higher_r_10 = {_RANDOM[7'h36][31:26], _RANDOM[7'h37][21:0]}; + higher_plus_one_r_10 = {_RANDOM[7'h37][31:22], _RANDOM[7'h38][17:0]}; + higher_minus_one_r_10 = {_RANDOM[7'h38][31:18], _RANDOM[7'h39][13:0]}; + higher_r_11 = {_RANDOM[7'h39][31:14], _RANDOM[7'h3A][1:0]}; + higher_plus_one_r_11 = _RANDOM[7'h3A][21:2]; + higher_minus_one_r_11 = {_RANDOM[7'h3A][31:22], _RANDOM[7'h3B][9:0]}; + io_out_s2_full_pred_3_fallThroughAddr_stashed_carry = _RANDOM[7'h3B][10]; + higher_r_12 = {_RANDOM[7'h3B][31:11], _RANDOM[7'h3C][6:0]}; + higher_plus_one_r_12 = {_RANDOM[7'h3C][31:7], _RANDOM[7'h3D][2:0]}; + higher_minus_one_r_12 = _RANDOM[7'h3D][30:3]; + higher_r_13 = {_RANDOM[7'h3D][31], _RANDOM[7'h3E][26:0]}; + higher_plus_one_r_13 = {_RANDOM[7'h3E][31:27], _RANDOM[7'h3F][22:0]}; + higher_minus_one_r_13 = {_RANDOM[7'h3F][31:23], _RANDOM[7'h40][18:0]}; + higher_r_14 = {_RANDOM[7'h40][31:19], _RANDOM[7'h41][6:0]}; + higher_plus_one_r_14 = _RANDOM[7'h41][26:7]; + higher_minus_one_r_14 = {_RANDOM[7'h41][31:27], _RANDOM[7'h42][14:0]}; + higher_r_15 = {_RANDOM[7'h42][31:15], _RANDOM[7'h43][10:0]}; + higher_plus_one_r_15 = {_RANDOM[7'h43][31:11], _RANDOM[7'h44][6:0]}; + higher_minus_one_r_15 = {_RANDOM[7'h44][31:7], _RANDOM[7'h45][2:0]}; + higher_r_16 = _RANDOM[7'h45][30:3]; + higher_plus_one_r_16 = {_RANDOM[7'h45][31], _RANDOM[7'h46][26:0]}; + higher_minus_one_r_16 = {_RANDOM[7'h46][31:27], _RANDOM[7'h47][22:0]}; + higher_r_17 = {_RANDOM[7'h47][31:23], _RANDOM[7'h48][10:0]}; + higher_plus_one_r_17 = _RANDOM[7'h48][30:11]; + higher_minus_one_r_17 = {_RANDOM[7'h48][31], _RANDOM[7'h49][18:0]}; + higher_r_18 = {_RANDOM[7'h49][31:19], _RANDOM[7'h4A][14:0]}; + higher_plus_one_r_18 = {_RANDOM[7'h4A][31:15], _RANDOM[7'h4B][10:0]}; + higher_minus_one_r_18 = {_RANDOM[7'h4B][31:11], _RANDOM[7'h4C][6:0]}; + higher_r_19 = {_RANDOM[7'h4C][31:7], _RANDOM[7'h4D][2:0]}; + higher_plus_one_r_19 = _RANDOM[7'h4D][30:3]; + higher_minus_one_r_19 = {_RANDOM[7'h4D][31], _RANDOM[7'h4E][26:0]}; + higher_r_20 = {_RANDOM[7'h4E][31:27], _RANDOM[7'h4F][14:0]}; + higher_plus_one_r_20 = {_RANDOM[7'h4F][31:15], _RANDOM[7'h50][2:0]}; + higher_minus_one_r_20 = _RANDOM[7'h50][22:3]; + higher_r_21 = {_RANDOM[7'h50][31:23], _RANDOM[7'h51][18:0]}; + higher_plus_one_r_21 = {_RANDOM[7'h51][31:19], _RANDOM[7'h52][14:0]}; + higher_minus_one_r_21 = {_RANDOM[7'h52][31:15], _RANDOM[7'h53][10:0]}; + higher_r_22 = {_RANDOM[7'h53][31:11], _RANDOM[7'h54][6:0]}; + higher_plus_one_r_22 = {_RANDOM[7'h54][31:7], _RANDOM[7'h55][2:0]}; + higher_minus_one_r_22 = _RANDOM[7'h55][30:3]; + higher_r_23 = {_RANDOM[7'h55][31], _RANDOM[7'h56][18:0]}; + higher_plus_one_r_23 = {_RANDOM[7'h56][31:19], _RANDOM[7'h57][6:0]}; + higher_minus_one_r_23 = _RANDOM[7'h57][26:7]; + io_out_last_stage_meta_r = _RANDOM[7'h59][29:27]; + io_out_last_stage_meta_r_1 = {_RANDOM[7'h59][31:30], _RANDOM[7'h5A][0]}; + io_s1_ready_REG = _RANDOM[7'h5A][1]; + ftbBank_io_update_write_way_REG = _RANDOM[7'h5A][3:2]; + ftbBank_io_update_write_alloc_REG = _RANDOM[7'h5A][4]; + io_perf_0_value_REG = _RANDOM[7'h5A][7]; + io_perf_0_value_REG_1 = _RANDOM[7'h5A][8]; + io_perf_1_value_REG = _RANDOM[7'h5A][9]; + io_perf_1_value_REG_1 = _RANDOM[7'h5A][10]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + s2_hit_dup_0 = 1'h0; + s2_hit_dup_1 = 1'h0; + s2_hit_dup_2 = 1'h0; + s2_hit_dup_3 = 1'h0; + s3_hit_dup_0 = 1'h0; + s3_hit_dup_1 = 1'h0; + s3_hit_dup_2 = 1'h0; + s3_hit_dup_3 = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + DelayN_2 reset_vector_delay ( + .clock (clock), + .io_in (io_reset_vector), + .io_out (_reset_vector_delay_io_out) + ); + FTBBank ftbBank ( + .clock (clock), + .reset (reset), + .io_s1_fire (io_s1_fire_0), + .io_req_pc_ready (_ftbBank_io_req_pc_ready), + .io_req_pc_valid (io_s0_fire_0), + .io_req_pc_bits (io_in_bits_s0_pc_0), + .io_read_resp_valid (_ftbBank_io_read_resp_valid), + .io_read_resp_brSlots_0_offset + (_ftbBank_io_read_resp_brSlots_0_offset), + .io_read_resp_brSlots_0_lower + (_ftbBank_io_read_resp_brSlots_0_lower), + .io_read_resp_brSlots_0_tarStat + (_ftbBank_io_read_resp_brSlots_0_tarStat), + .io_read_resp_brSlots_0_sharing + (_ftbBank_io_read_resp_brSlots_0_sharing), + .io_read_resp_brSlots_0_valid + (_ftbBank_io_read_resp_brSlots_0_valid), + .io_read_resp_tailSlot_offset + (_ftbBank_io_read_resp_tailSlot_offset), + .io_read_resp_tailSlot_lower + (_ftbBank_io_read_resp_tailSlot_lower), + .io_read_resp_tailSlot_tarStat + (_ftbBank_io_read_resp_tailSlot_tarStat), + .io_read_resp_tailSlot_sharing + (_ftbBank_io_read_resp_tailSlot_sharing), + .io_read_resp_tailSlot_valid + (_ftbBank_io_read_resp_tailSlot_valid), + .io_read_resp_pftAddr (_ftbBank_io_read_resp_pftAddr), + .io_read_resp_carry (_ftbBank_io_read_resp_carry), + .io_read_resp_isCall (_ftbBank_io_read_resp_isCall), + .io_read_resp_isRet (_ftbBank_io_read_resp_isRet), + .io_read_resp_isJalr (_ftbBank_io_read_resp_isJalr), + .io_read_resp_last_may_be_rvi_call + (_ftbBank_io_read_resp_last_may_be_rvi_call), + .io_read_resp_always_taken_0 + (_ftbBank_io_read_resp_always_taken_0), + .io_read_resp_always_taken_1 + (_ftbBank_io_read_resp_always_taken_1), + .io_read_hits_valid (_ftbBank_io_read_hits_valid), + .io_read_hits_bits (_ftbBank_io_read_hits_bits), + .io_u_req_pc_valid (update_need_read), + .io_u_req_pc_bits (io_update_bits_pc), + .io_update_hits_valid (_ftbBank_io_update_hits_valid), + .io_update_hits_bits (_ftbBank_io_update_hits_bits), + .io_update_access + (u_valid & ~(io_update_bits_meta[0])), + .io_update_pc (_ftbBank_io_update_pc_T), + .io_update_write_data_valid + (update_now | _write_valid_delay_io_out), + .io_update_write_data_bits_entry_valid + (update_now + ? io_update_bits_ftb_entry_valid + : _delay2_entry_pipMod_io_out_bits_valid), + .io_update_write_data_bits_entry_brSlots_0_offset + (update_now + ? io_update_bits_ftb_entry_brSlots_0_offset + : _delay2_entry_pipMod_io_out_bits_brSlots_0_offset), + .io_update_write_data_bits_entry_brSlots_0_lower + (update_now + ? io_update_bits_ftb_entry_brSlots_0_lower + : _delay2_entry_pipMod_io_out_bits_brSlots_0_lower), + .io_update_write_data_bits_entry_brSlots_0_tarStat + (update_now + ? io_update_bits_ftb_entry_brSlots_0_tarStat + : _delay2_entry_pipMod_io_out_bits_brSlots_0_tarStat), + .io_update_write_data_bits_entry_brSlots_0_sharing + (update_now + ? io_update_bits_ftb_entry_brSlots_0_sharing + : _delay2_entry_pipMod_io_out_bits_brSlots_0_sharing), + .io_update_write_data_bits_entry_brSlots_0_valid + (update_now + ? io_update_bits_ftb_entry_brSlots_0_valid + : _delay2_entry_pipMod_io_out_bits_brSlots_0_valid), + .io_update_write_data_bits_entry_tailSlot_offset + (update_now + ? io_update_bits_ftb_entry_tailSlot_offset + : _delay2_entry_pipMod_io_out_bits_tailSlot_offset), + .io_update_write_data_bits_entry_tailSlot_lower + (update_now + ? io_update_bits_ftb_entry_tailSlot_lower + : _delay2_entry_pipMod_io_out_bits_tailSlot_lower), + .io_update_write_data_bits_entry_tailSlot_tarStat + (update_now + ? io_update_bits_ftb_entry_tailSlot_tarStat + : _delay2_entry_pipMod_io_out_bits_tailSlot_tarStat), + .io_update_write_data_bits_entry_tailSlot_sharing + (update_now + ? io_update_bits_ftb_entry_tailSlot_sharing + : _delay2_entry_pipMod_io_out_bits_tailSlot_sharing), + .io_update_write_data_bits_entry_tailSlot_valid + (update_now + ? io_update_bits_ftb_entry_tailSlot_valid + : _delay2_entry_pipMod_io_out_bits_tailSlot_valid), + .io_update_write_data_bits_entry_pftAddr + (update_now + ? io_update_bits_ftb_entry_pftAddr + : _delay2_entry_pipMod_io_out_bits_pftAddr), + .io_update_write_data_bits_entry_carry + (update_now + ? io_update_bits_ftb_entry_carry + : _delay2_entry_pipMod_io_out_bits_carry), + .io_update_write_data_bits_entry_isCall + (update_now + ? io_update_bits_ftb_entry_isCall + : _delay2_entry_pipMod_io_out_bits_isCall), + .io_update_write_data_bits_entry_isRet + (update_now + ? io_update_bits_ftb_entry_isRet + : _delay2_entry_pipMod_io_out_bits_isRet), + .io_update_write_data_bits_entry_isJalr + (update_now + ? io_update_bits_ftb_entry_isJalr + : _delay2_entry_pipMod_io_out_bits_isJalr), + .io_update_write_data_bits_entry_last_may_be_rvi_call + (update_now + ? io_update_bits_ftb_entry_last_may_be_rvi_call + : _delay2_entry_pipMod_io_out_bits_last_may_be_rvi_call), + .io_update_write_data_bits_entry_always_taken_0 + (update_now + ? io_update_bits_ftb_entry_always_taken_0 + : _delay2_entry_pipMod_io_out_bits_always_taken_0), + .io_update_write_data_bits_entry_always_taken_1 + (update_now + ? io_update_bits_ftb_entry_always_taken_1 + : _delay2_entry_pipMod_io_out_bits_always_taken_1), + .io_update_write_data_bits_tag + (_ftbBank_io_update_pc_T[29:10]), + .io_update_write_way + (update_now ? io_update_bits_meta[2:1] : ftbBank_io_update_write_way_REG), + .io_update_write_alloc + (~update_now & ftbBank_io_update_write_alloc_REG) + ); + DelayNWithValid delay2_pc_pipMod ( + .clock (clock), + .reset (reset), + .io_in_bits (io_update_bits_pc), + .io_in_valid (u_valid), + .io_out_bits (_delay2_pc_pipMod_io_out_bits) + ); + DelayNWithValid_1 delay2_entry_pipMod ( + .clock (clock), + .reset (reset), + .io_in_bits_valid (io_update_bits_ftb_entry_valid), + .io_in_bits_brSlots_0_offset (io_update_bits_ftb_entry_brSlots_0_offset), + .io_in_bits_brSlots_0_lower (io_update_bits_ftb_entry_brSlots_0_lower), + .io_in_bits_brSlots_0_tarStat (io_update_bits_ftb_entry_brSlots_0_tarStat), + .io_in_bits_brSlots_0_sharing (io_update_bits_ftb_entry_brSlots_0_sharing), + .io_in_bits_brSlots_0_valid (io_update_bits_ftb_entry_brSlots_0_valid), + .io_in_bits_tailSlot_offset (io_update_bits_ftb_entry_tailSlot_offset), + .io_in_bits_tailSlot_lower (io_update_bits_ftb_entry_tailSlot_lower), + .io_in_bits_tailSlot_tarStat (io_update_bits_ftb_entry_tailSlot_tarStat), + .io_in_bits_tailSlot_sharing (io_update_bits_ftb_entry_tailSlot_sharing), + .io_in_bits_tailSlot_valid (io_update_bits_ftb_entry_tailSlot_valid), + .io_in_bits_pftAddr (io_update_bits_ftb_entry_pftAddr), + .io_in_bits_carry (io_update_bits_ftb_entry_carry), + .io_in_bits_isCall (io_update_bits_ftb_entry_isCall), + .io_in_bits_isRet (io_update_bits_ftb_entry_isRet), + .io_in_bits_isJalr (io_update_bits_ftb_entry_isJalr), + .io_in_bits_last_may_be_rvi_call (io_update_bits_ftb_entry_last_may_be_rvi_call), + .io_in_bits_always_taken_0 (io_update_bits_ftb_entry_always_taken_0), + .io_in_bits_always_taken_1 (io_update_bits_ftb_entry_always_taken_1), + .io_in_valid (u_valid), + .io_out_bits_valid (_delay2_entry_pipMod_io_out_bits_valid), + .io_out_bits_brSlots_0_offset (_delay2_entry_pipMod_io_out_bits_brSlots_0_offset), + .io_out_bits_brSlots_0_lower (_delay2_entry_pipMod_io_out_bits_brSlots_0_lower), + .io_out_bits_brSlots_0_tarStat + (_delay2_entry_pipMod_io_out_bits_brSlots_0_tarStat), + .io_out_bits_brSlots_0_sharing + (_delay2_entry_pipMod_io_out_bits_brSlots_0_sharing), + .io_out_bits_brSlots_0_valid (_delay2_entry_pipMod_io_out_bits_brSlots_0_valid), + .io_out_bits_tailSlot_offset (_delay2_entry_pipMod_io_out_bits_tailSlot_offset), + .io_out_bits_tailSlot_lower (_delay2_entry_pipMod_io_out_bits_tailSlot_lower), + .io_out_bits_tailSlot_tarStat (_delay2_entry_pipMod_io_out_bits_tailSlot_tarStat), + .io_out_bits_tailSlot_sharing (_delay2_entry_pipMod_io_out_bits_tailSlot_sharing), + .io_out_bits_tailSlot_valid (_delay2_entry_pipMod_io_out_bits_tailSlot_valid), + .io_out_bits_pftAddr (_delay2_entry_pipMod_io_out_bits_pftAddr), + .io_out_bits_carry (_delay2_entry_pipMod_io_out_bits_carry), + .io_out_bits_isCall (_delay2_entry_pipMod_io_out_bits_isCall), + .io_out_bits_isRet (_delay2_entry_pipMod_io_out_bits_isRet), + .io_out_bits_isJalr (_delay2_entry_pipMod_io_out_bits_isJalr), + .io_out_bits_last_may_be_rvi_call + (_delay2_entry_pipMod_io_out_bits_last_may_be_rvi_call), + .io_out_bits_always_taken_0 (_delay2_entry_pipMod_io_out_bits_always_taken_0), + .io_out_bits_always_taken_1 (_delay2_entry_pipMod_io_out_bits_always_taken_1) + ); + DelayN_4 write_valid_delay ( + .clock (clock), + .io_in (u_valid & ~(io_update_bits_meta[0])), + .io_out (_write_valid_delay_io_out) + ); + assign io_out_s2_full_pred_0_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0 | s2_hit_dup_0 + & s2_ftb_entry_dup_0_always_taken_0; + assign io_out_s2_full_pred_0_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1 | s2_hit_dup_0 + & s2_ftb_entry_dup_0_always_taken_1; + assign io_out_s2_full_pred_0_slot_valids_0 = s2_ftb_entry_dup_0_brSlots_0_valid; + assign io_out_s2_full_pred_0_slot_valids_1 = s2_ftb_entry_dup_0_tailSlot_valid; + assign io_out_s2_full_pred_0_targets_0 = + {(s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r : 28'h0) + | (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r : 28'h0) + | (s2_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r : 28'h0), + s2_ftb_entry_dup_0_brSlots_0_lower, + 1'h0}; + assign io_out_s2_full_pred_0_targets_1 = io_out_s2_full_pred_0_targets_1_0; + assign io_out_s2_full_pred_0_jalr_target = io_out_s2_full_pred_0_targets_1_0; + assign io_out_s2_full_pred_0_offsets_0 = s2_ftb_entry_dup_0_brSlots_0_offset; + assign io_out_s2_full_pred_0_offsets_1 = s2_ftb_entry_dup_0_tailSlot_offset; + assign io_out_s2_full_pred_0_fallThroughAddr = + {1'h0, s2_pc_dup_0[4:1]} >= {s2_ftb_entry_dup_0_carry, s2_ftb_entry_dup_0_pftAddr} + ? 41'(s2_pc_dup_0 + 41'h20) + : {io_out_s2_full_pred_0_fallThroughAddr_stashed_carry + ? 36'(s2_pc_dup_0[40:5] + 36'h1) + : s2_pc_dup_0[40:5], + s2_ftb_entry_dup_0_pftAddr, + 1'h0}; + assign io_out_s2_full_pred_0_is_br_sharing = + s2_ftb_entry_dup_0_tailSlot_valid & s2_ftb_entry_dup_0_tailSlot_sharing; + assign io_out_s2_full_pred_0_hit = s2_hit_dup_0; + assign io_out_s2_full_pred_1_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0 | s2_hit_dup_1 + & s2_ftb_entry_dup_1_always_taken_0; + assign io_out_s2_full_pred_1_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1 | s2_hit_dup_1 + & s2_ftb_entry_dup_1_always_taken_1; + assign io_out_s2_full_pred_1_slot_valids_0 = s2_ftb_entry_dup_1_brSlots_0_valid; + assign io_out_s2_full_pred_1_slot_valids_1 = s2_ftb_entry_dup_1_tailSlot_valid; + assign io_out_s2_full_pred_1_targets_0 = + {(s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_3 : 28'h0) + | (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_3 : 28'h0) + | (s2_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_3 : 28'h0), + s2_ftb_entry_dup_1_brSlots_0_lower, + 1'h0}; + assign io_out_s2_full_pred_1_targets_1 = io_out_s2_full_pred_1_targets_1_0; + assign io_out_s2_full_pred_1_jalr_target = io_out_s2_full_pred_1_targets_1_0; + assign io_out_s2_full_pred_1_offsets_0 = s2_ftb_entry_dup_1_brSlots_0_offset; + assign io_out_s2_full_pred_1_offsets_1 = s2_ftb_entry_dup_1_tailSlot_offset; + assign io_out_s2_full_pred_1_fallThroughAddr = + {1'h0, s2_pc_dup_1[4:1]} >= {s2_ftb_entry_dup_1_carry, s2_ftb_entry_dup_1_pftAddr} + ? 41'(s2_pc_dup_1 + 41'h20) + : {io_out_s2_full_pred_1_fallThroughAddr_stashed_carry + ? 36'(s2_pc_dup_1[40:5] + 36'h1) + : s2_pc_dup_1[40:5], + s2_ftb_entry_dup_1_pftAddr, + 1'h0}; + assign io_out_s2_full_pred_1_is_br_sharing = + s2_ftb_entry_dup_1_tailSlot_valid & s2_ftb_entry_dup_1_tailSlot_sharing; + assign io_out_s2_full_pred_1_hit = s2_hit_dup_1; + assign io_out_s2_full_pred_2_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0 | s2_hit_dup_2 + & s2_ftb_entry_dup_2_always_taken_0; + assign io_out_s2_full_pred_2_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1 | s2_hit_dup_2 + & s2_ftb_entry_dup_2_always_taken_1; + assign io_out_s2_full_pred_2_slot_valids_0 = s2_ftb_entry_dup_2_brSlots_0_valid; + assign io_out_s2_full_pred_2_slot_valids_1 = s2_ftb_entry_dup_2_tailSlot_valid; + assign io_out_s2_full_pred_2_targets_0 = + {(s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_6 : 28'h0) + | (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_6 : 28'h0) + | (s2_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_6 : 28'h0), + s2_ftb_entry_dup_2_brSlots_0_lower, + 1'h0}; + assign io_out_s2_full_pred_2_targets_1 = io_out_s2_full_pred_2_targets_1_0; + assign io_out_s2_full_pred_2_jalr_target = io_out_s2_full_pred_2_targets_1_0; + assign io_out_s2_full_pred_2_offsets_0 = s2_ftb_entry_dup_2_brSlots_0_offset; + assign io_out_s2_full_pred_2_offsets_1 = s2_ftb_entry_dup_2_tailSlot_offset; + assign io_out_s2_full_pred_2_fallThroughAddr = + {1'h0, s2_pc_dup_2[4:1]} >= {s2_ftb_entry_dup_2_carry, s2_ftb_entry_dup_2_pftAddr} + ? 41'(s2_pc_dup_2 + 41'h20) + : {io_out_s2_full_pred_2_fallThroughAddr_stashed_carry + ? 36'(s2_pc_dup_2[40:5] + 36'h1) + : s2_pc_dup_2[40:5], + s2_ftb_entry_dup_2_pftAddr, + 1'h0}; + assign io_out_s2_full_pred_2_is_jalr = + s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isJalr; + assign io_out_s2_full_pred_2_is_call = + s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isCall; + assign io_out_s2_full_pred_2_is_ret = + s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_isRet; + assign io_out_s2_full_pred_2_last_may_be_rvi_call = + s2_ftb_entry_dup_2_last_may_be_rvi_call; + assign io_out_s2_full_pred_2_is_br_sharing = + s2_ftb_entry_dup_2_tailSlot_valid & s2_ftb_entry_dup_2_tailSlot_sharing; + assign io_out_s2_full_pred_2_hit = s2_hit_dup_2; + assign io_out_s2_full_pred_3_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0 | s2_hit_dup_3 + & s2_ftb_entry_dup_3_always_taken_0; + assign io_out_s2_full_pred_3_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1 | s2_hit_dup_3 + & s2_ftb_entry_dup_3_always_taken_1; + assign io_out_s2_full_pred_3_slot_valids_0 = s2_ftb_entry_dup_3_brSlots_0_valid; + assign io_out_s2_full_pred_3_slot_valids_1 = s2_ftb_entry_dup_3_tailSlot_valid; + assign io_out_s2_full_pred_3_targets_0 = + {(s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_9 : 28'h0) + | (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_9 : 28'h0) + | (s2_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_9 : 28'h0), + s2_ftb_entry_dup_3_brSlots_0_lower, + 1'h0}; + assign io_out_s2_full_pred_3_targets_1 = io_out_s2_full_pred_3_targets_1_0; + assign io_out_s2_full_pred_3_jalr_target = io_out_s2_full_pred_3_targets_1_0; + assign io_out_s2_full_pred_3_offsets_0 = s2_ftb_entry_dup_3_brSlots_0_offset; + assign io_out_s2_full_pred_3_offsets_1 = s2_ftb_entry_dup_3_tailSlot_offset; + assign io_out_s2_full_pred_3_fallThroughAddr = + io_out_s2_full_pred_3_fallThroughErr_0 + ? 41'(s2_pc_dup_3 + 41'h20) + : {io_out_s2_full_pred_3_fallThroughAddr_stashed_carry + ? 36'(s2_pc_dup_3[40:5] + 36'h1) + : s2_pc_dup_3[40:5], + s2_ftb_entry_dup_3_pftAddr, + 1'h0}; + assign io_out_s2_full_pred_3_fallThroughErr = io_out_s2_full_pred_3_fallThroughErr_0; + assign io_out_s2_full_pred_3_is_br_sharing = + s2_ftb_entry_dup_3_tailSlot_valid & s2_ftb_entry_dup_3_tailSlot_sharing; + assign io_out_s2_full_pred_3_hit = s2_hit_dup_3; + assign io_out_s3_full_pred_0_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0 | s3_hit_dup_0 + & s3_ftb_entry_dup_0_always_taken_0; + assign io_out_s3_full_pred_0_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1 | s3_hit_dup_0 + & s3_ftb_entry_dup_0_always_taken_1; + assign io_out_s3_full_pred_0_slot_valids_0 = s3_ftb_entry_dup_0_brSlots_0_valid; + assign io_out_s3_full_pred_0_slot_valids_1 = s3_ftb_entry_dup_0_tailSlot_valid; + assign io_out_s3_full_pred_0_targets_0 = + {(s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_12 : 28'h0) + | (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_12 : 28'h0) + | (s3_ftb_entry_dup_0_brSlots_0_tarStat == 2'h0 ? higher_r_12 : 28'h0), + s3_ftb_entry_dup_0_brSlots_0_lower, + 1'h0}; + assign io_out_s3_full_pred_0_targets_1 = io_out_s3_full_pred_0_targets_1_0; + assign io_out_s3_full_pred_0_jalr_target = io_out_s3_full_pred_0_targets_1_0; + assign io_out_s3_full_pred_0_fallThroughAddr = + io_out_s3_full_pred_0_fallThroughErr_0 + ? 41'(s3_pc_dup_0 + 41'h20) + : {s3_ftb_entry_dup_0_carry ? 36'(s3_pc_dup_0[40:5] + 36'h1) : s3_pc_dup_0[40:5], + s3_ftb_entry_dup_0_pftAddr, + 1'h0}; + assign io_out_s3_full_pred_0_fallThroughErr = io_out_s3_full_pred_0_fallThroughErr_0; + assign io_out_s3_full_pred_0_is_br_sharing = + s3_ftb_entry_dup_0_tailSlot_valid & s3_ftb_entry_dup_0_tailSlot_sharing; + assign io_out_s3_full_pred_0_hit = s3_hit_dup_0; + assign io_out_s3_full_pred_1_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0 | s3_hit_dup_1 + & s3_ftb_entry_dup_1_always_taken_0; + assign io_out_s3_full_pred_1_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1 | s3_hit_dup_1 + & s3_ftb_entry_dup_1_always_taken_1; + assign io_out_s3_full_pred_1_slot_valids_0 = s3_ftb_entry_dup_1_brSlots_0_valid; + assign io_out_s3_full_pred_1_slot_valids_1 = s3_ftb_entry_dup_1_tailSlot_valid; + assign io_out_s3_full_pred_1_targets_0 = + {(s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_15 : 28'h0) + | (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_15 : 28'h0) + | (s3_ftb_entry_dup_1_brSlots_0_tarStat == 2'h0 ? higher_r_15 : 28'h0), + s3_ftb_entry_dup_1_brSlots_0_lower, + 1'h0}; + assign io_out_s3_full_pred_1_targets_1 = io_out_s3_full_pred_1_targets_1_0; + assign io_out_s3_full_pred_1_jalr_target = io_out_s3_full_pred_1_targets_1_0; + assign io_out_s3_full_pred_1_fallThroughAddr = + io_out_s3_full_pred_1_fallThroughErr_0 + ? 41'(s3_pc_dup_1 + 41'h20) + : {s3_ftb_entry_dup_1_carry ? 36'(s3_pc_dup_1[40:5] + 36'h1) : s3_pc_dup_1[40:5], + s3_ftb_entry_dup_1_pftAddr, + 1'h0}; + assign io_out_s3_full_pred_1_fallThroughErr = io_out_s3_full_pred_1_fallThroughErr_0; + assign io_out_s3_full_pred_1_is_br_sharing = + s3_ftb_entry_dup_1_tailSlot_valid & s3_ftb_entry_dup_1_tailSlot_sharing; + assign io_out_s3_full_pred_1_hit = s3_hit_dup_1; + assign io_out_s3_full_pred_2_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0 | s3_hit_dup_2 + & s3_ftb_entry_dup_2_always_taken_0; + assign io_out_s3_full_pred_2_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1 | s3_hit_dup_2 + & s3_ftb_entry_dup_2_always_taken_1; + assign io_out_s3_full_pred_2_slot_valids_0 = s3_ftb_entry_dup_2_brSlots_0_valid; + assign io_out_s3_full_pred_2_slot_valids_1 = s3_ftb_entry_dup_2_tailSlot_valid; + assign io_out_s3_full_pred_2_targets_0 = + {(s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_18 : 28'h0) + | (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_18 : 28'h0) + | (s3_ftb_entry_dup_2_brSlots_0_tarStat == 2'h0 ? higher_r_18 : 28'h0), + s3_ftb_entry_dup_2_brSlots_0_lower, + 1'h0}; + assign io_out_s3_full_pred_2_targets_1 = io_out_s3_full_pred_2_targets_1_0; + assign io_out_s3_full_pred_2_jalr_target = io_out_s3_full_pred_2_targets_1_0; + assign io_out_s3_full_pred_2_fallThroughAddr = + io_out_s3_full_pred_2_fallThroughErr_0 + ? 41'(s3_pc_dup_2 + 41'h20) + : {s3_ftb_entry_dup_2_carry ? 36'(s3_pc_dup_2[40:5] + 36'h1) : s3_pc_dup_2[40:5], + s3_ftb_entry_dup_2_pftAddr, + 1'h0}; + assign io_out_s3_full_pred_2_fallThroughErr = io_out_s3_full_pred_2_fallThroughErr_0; + assign io_out_s3_full_pred_2_is_jalr = + s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isJalr; + assign io_out_s3_full_pred_2_is_call = + s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isCall; + assign io_out_s3_full_pred_2_is_ret = + s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_isRet; + assign io_out_s3_full_pred_2_is_br_sharing = + s3_ftb_entry_dup_2_tailSlot_valid & s3_ftb_entry_dup_2_tailSlot_sharing; + assign io_out_s3_full_pred_2_hit = s3_hit_dup_2; + assign io_out_s3_full_pred_3_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0 | s3_hit_dup_3 + & s3_ftb_entry_dup_3_always_taken_0; + assign io_out_s3_full_pred_3_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1 | s3_hit_dup_3 + & s3_ftb_entry_dup_3_always_taken_1; + assign io_out_s3_full_pred_3_slot_valids_0 = s3_ftb_entry_dup_3_brSlots_0_valid; + assign io_out_s3_full_pred_3_slot_valids_1 = s3_ftb_entry_dup_3_tailSlot_valid; + assign io_out_s3_full_pred_3_targets_0 = + {(s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h1 ? higher_plus_one_r_21 : 28'h0) + | (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h2 ? higher_minus_one_r_21 : 28'h0) + | (s3_ftb_entry_dup_3_brSlots_0_tarStat == 2'h0 ? higher_r_21 : 28'h0), + s3_ftb_entry_dup_3_brSlots_0_lower, + 1'h0}; + assign io_out_s3_full_pred_3_targets_1 = io_out_s3_full_pred_3_targets_1_0; + assign io_out_s3_full_pred_3_jalr_target = io_out_s3_full_pred_3_targets_1_0; + assign io_out_s3_full_pred_3_offsets_0 = s3_ftb_entry_dup_3_brSlots_0_offset; + assign io_out_s3_full_pred_3_offsets_1 = s3_ftb_entry_dup_3_tailSlot_offset; + assign io_out_s3_full_pred_3_fallThroughAddr = + io_out_s3_full_pred_3_fallThroughErr_0 + ? 41'(s3_pc_dup_3 + 41'h20) + : {s3_ftb_entry_dup_3_carry ? 36'(s3_pc_dup_3[40:5] + 36'h1) : s3_pc_dup_3[40:5], + s3_ftb_entry_dup_3_pftAddr, + 1'h0}; + assign io_out_s3_full_pred_3_fallThroughErr = io_out_s3_full_pred_3_fallThroughErr_0; + assign io_out_s3_full_pred_3_is_br_sharing = + s3_ftb_entry_dup_3_tailSlot_valid & s3_ftb_entry_dup_3_tailSlot_sharing; + assign io_out_s3_full_pred_3_hit = s3_hit_dup_3; + assign io_out_last_stage_meta = {220'h0, io_out_last_stage_meta_r_1}; + assign io_out_last_stage_ftb_entry_valid = s3_ftb_entry_dup_0_valid; + assign io_out_last_stage_ftb_entry_brSlots_0_offset = + s3_ftb_entry_dup_0_brSlots_0_offset; + assign io_out_last_stage_ftb_entry_brSlots_0_lower = s3_ftb_entry_dup_0_brSlots_0_lower; + assign io_out_last_stage_ftb_entry_brSlots_0_tarStat = + s3_ftb_entry_dup_0_brSlots_0_tarStat; + assign io_out_last_stage_ftb_entry_brSlots_0_sharing = + s3_ftb_entry_dup_0_brSlots_0_sharing; + assign io_out_last_stage_ftb_entry_brSlots_0_valid = s3_ftb_entry_dup_0_brSlots_0_valid; + assign io_out_last_stage_ftb_entry_tailSlot_offset = s3_ftb_entry_dup_0_tailSlot_offset; + assign io_out_last_stage_ftb_entry_tailSlot_lower = s3_ftb_entry_dup_0_tailSlot_lower; + assign io_out_last_stage_ftb_entry_tailSlot_tarStat = + s3_ftb_entry_dup_0_tailSlot_tarStat; + assign io_out_last_stage_ftb_entry_tailSlot_sharing = + s3_ftb_entry_dup_0_tailSlot_sharing; + assign io_out_last_stage_ftb_entry_tailSlot_valid = s3_ftb_entry_dup_0_tailSlot_valid; + assign io_out_last_stage_ftb_entry_pftAddr = s3_ftb_entry_dup_0_pftAddr; + assign io_out_last_stage_ftb_entry_carry = s3_ftb_entry_dup_0_carry; + assign io_out_last_stage_ftb_entry_isCall = s3_ftb_entry_dup_0_isCall; + assign io_out_last_stage_ftb_entry_isRet = s3_ftb_entry_dup_0_isRet; + assign io_out_last_stage_ftb_entry_isJalr = s3_ftb_entry_dup_0_isJalr; + assign io_out_last_stage_ftb_entry_last_may_be_rvi_call = + s3_ftb_entry_dup_0_last_may_be_rvi_call; + assign io_out_last_stage_ftb_entry_always_taken_0 = s3_ftb_entry_dup_0_always_taken_0; + assign io_out_last_stage_ftb_entry_always_taken_1 = s3_ftb_entry_dup_0_always_taken_1; + assign io_s1_ready = _ftbBank_io_req_pc_ready & ~update_need_read & ~io_s1_ready_REG; + assign io_perf_0_value = {5'h0, io_perf_0_value_REG_1}; + assign io_perf_1_value = {5'h0, io_perf_1_value_REG_1}; +endmodule + diff --git a/rtl/BPUTop/FTBBank.sv b/rtl/BPUTop/FTBBank.sv new file mode 100644 index 0000000..8d657da --- /dev/null +++ b/rtl/BPUTop/FTBBank.sv @@ -0,0 +1,6369 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FTBBank( + input clock, + input reset, + input io_s1_fire, + output io_req_pc_ready, + input io_req_pc_valid, + input [40:0] io_req_pc_bits, + output io_read_resp_valid, + output [3:0] io_read_resp_brSlots_0_offset, + output [11:0] io_read_resp_brSlots_0_lower, + output [1:0] io_read_resp_brSlots_0_tarStat, + output io_read_resp_brSlots_0_sharing, + output io_read_resp_brSlots_0_valid, + output [3:0] io_read_resp_tailSlot_offset, + output [19:0] io_read_resp_tailSlot_lower, + output [1:0] io_read_resp_tailSlot_tarStat, + output io_read_resp_tailSlot_sharing, + output io_read_resp_tailSlot_valid, + output [3:0] io_read_resp_pftAddr, + output io_read_resp_carry, + output io_read_resp_isCall, + output io_read_resp_isRet, + output io_read_resp_isJalr, + output io_read_resp_last_may_be_rvi_call, + output io_read_resp_always_taken_0, + output io_read_resp_always_taken_1, + output io_read_hits_valid, + output [1:0] io_read_hits_bits, + input io_u_req_pc_valid, + input [40:0] io_u_req_pc_bits, + output io_update_hits_valid, + output [1:0] io_update_hits_bits, + input io_update_access, + input [40:0] io_update_pc, + input io_update_write_data_valid, + input io_update_write_data_bits_entry_valid, + input [3:0] io_update_write_data_bits_entry_brSlots_0_offset, + input [11:0] io_update_write_data_bits_entry_brSlots_0_lower, + input [1:0] io_update_write_data_bits_entry_brSlots_0_tarStat, + input io_update_write_data_bits_entry_brSlots_0_sharing, + input io_update_write_data_bits_entry_brSlots_0_valid, + input [3:0] io_update_write_data_bits_entry_tailSlot_offset, + input [19:0] io_update_write_data_bits_entry_tailSlot_lower, + input [1:0] io_update_write_data_bits_entry_tailSlot_tarStat, + input io_update_write_data_bits_entry_tailSlot_sharing, + input io_update_write_data_bits_entry_tailSlot_valid, + input [3:0] io_update_write_data_bits_entry_pftAddr, + input io_update_write_data_bits_entry_carry, + input io_update_write_data_bits_entry_isCall, + input io_update_write_data_bits_entry_isRet, + input io_update_write_data_bits_entry_isJalr, + input io_update_write_data_bits_entry_last_may_be_rvi_call, + input io_update_write_data_bits_entry_always_taken_0, + input io_update_write_data_bits_entry_always_taken_1, + input [19:0] io_update_write_data_bits_tag, + input [1:0] io_update_write_way, + input io_update_write_alloc +); + + wire _ftb_io_r_resp_data_0_entry_valid; + wire [3:0] _ftb_io_r_resp_data_0_entry_brSlots_0_offset; + wire [11:0] _ftb_io_r_resp_data_0_entry_brSlots_0_lower; + wire [1:0] _ftb_io_r_resp_data_0_entry_brSlots_0_tarStat; + wire _ftb_io_r_resp_data_0_entry_brSlots_0_sharing; + wire _ftb_io_r_resp_data_0_entry_brSlots_0_valid; + wire [3:0] _ftb_io_r_resp_data_0_entry_tailSlot_offset; + wire [19:0] _ftb_io_r_resp_data_0_entry_tailSlot_lower; + wire [1:0] _ftb_io_r_resp_data_0_entry_tailSlot_tarStat; + wire _ftb_io_r_resp_data_0_entry_tailSlot_sharing; + wire _ftb_io_r_resp_data_0_entry_tailSlot_valid; + wire [3:0] _ftb_io_r_resp_data_0_entry_pftAddr; + wire _ftb_io_r_resp_data_0_entry_carry; + wire _ftb_io_r_resp_data_0_entry_isCall; + wire _ftb_io_r_resp_data_0_entry_isRet; + wire _ftb_io_r_resp_data_0_entry_isJalr; + wire _ftb_io_r_resp_data_0_entry_last_may_be_rvi_call; + wire _ftb_io_r_resp_data_0_entry_always_taken_0; + wire _ftb_io_r_resp_data_0_entry_always_taken_1; + wire [19:0] _ftb_io_r_resp_data_0_tag; + wire _ftb_io_r_resp_data_1_entry_valid; + wire [3:0] _ftb_io_r_resp_data_1_entry_brSlots_0_offset; + wire [11:0] _ftb_io_r_resp_data_1_entry_brSlots_0_lower; + wire [1:0] _ftb_io_r_resp_data_1_entry_brSlots_0_tarStat; + wire _ftb_io_r_resp_data_1_entry_brSlots_0_sharing; + wire _ftb_io_r_resp_data_1_entry_brSlots_0_valid; + wire [3:0] _ftb_io_r_resp_data_1_entry_tailSlot_offset; + wire [19:0] _ftb_io_r_resp_data_1_entry_tailSlot_lower; + wire [1:0] _ftb_io_r_resp_data_1_entry_tailSlot_tarStat; + wire _ftb_io_r_resp_data_1_entry_tailSlot_sharing; + wire _ftb_io_r_resp_data_1_entry_tailSlot_valid; + wire [3:0] _ftb_io_r_resp_data_1_entry_pftAddr; + wire _ftb_io_r_resp_data_1_entry_carry; + wire _ftb_io_r_resp_data_1_entry_isCall; + wire _ftb_io_r_resp_data_1_entry_isRet; + wire _ftb_io_r_resp_data_1_entry_isJalr; + wire _ftb_io_r_resp_data_1_entry_last_may_be_rvi_call; + wire _ftb_io_r_resp_data_1_entry_always_taken_0; + wire _ftb_io_r_resp_data_1_entry_always_taken_1; + wire [19:0] _ftb_io_r_resp_data_1_tag; + wire _ftb_io_r_resp_data_2_entry_valid; + wire [3:0] _ftb_io_r_resp_data_2_entry_brSlots_0_offset; + wire [11:0] _ftb_io_r_resp_data_2_entry_brSlots_0_lower; + wire [1:0] _ftb_io_r_resp_data_2_entry_brSlots_0_tarStat; + wire _ftb_io_r_resp_data_2_entry_brSlots_0_sharing; + wire _ftb_io_r_resp_data_2_entry_brSlots_0_valid; + wire [3:0] _ftb_io_r_resp_data_2_entry_tailSlot_offset; + wire [19:0] _ftb_io_r_resp_data_2_entry_tailSlot_lower; + wire [1:0] _ftb_io_r_resp_data_2_entry_tailSlot_tarStat; + wire _ftb_io_r_resp_data_2_entry_tailSlot_sharing; + wire _ftb_io_r_resp_data_2_entry_tailSlot_valid; + wire [3:0] _ftb_io_r_resp_data_2_entry_pftAddr; + wire _ftb_io_r_resp_data_2_entry_carry; + wire _ftb_io_r_resp_data_2_entry_isCall; + wire _ftb_io_r_resp_data_2_entry_isRet; + wire _ftb_io_r_resp_data_2_entry_isJalr; + wire _ftb_io_r_resp_data_2_entry_last_may_be_rvi_call; + wire _ftb_io_r_resp_data_2_entry_always_taken_0; + wire _ftb_io_r_resp_data_2_entry_always_taken_1; + wire [19:0] _ftb_io_r_resp_data_2_tag; + wire _ftb_io_r_resp_data_3_entry_valid; + wire [3:0] _ftb_io_r_resp_data_3_entry_brSlots_0_offset; + wire [11:0] _ftb_io_r_resp_data_3_entry_brSlots_0_lower; + wire [1:0] _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat; + wire _ftb_io_r_resp_data_3_entry_brSlots_0_sharing; + wire _ftb_io_r_resp_data_3_entry_brSlots_0_valid; + wire [3:0] _ftb_io_r_resp_data_3_entry_tailSlot_offset; + wire [19:0] _ftb_io_r_resp_data_3_entry_tailSlot_lower; + wire [1:0] _ftb_io_r_resp_data_3_entry_tailSlot_tarStat; + wire _ftb_io_r_resp_data_3_entry_tailSlot_sharing; + wire _ftb_io_r_resp_data_3_entry_tailSlot_valid; + wire [3:0] _ftb_io_r_resp_data_3_entry_pftAddr; + wire _ftb_io_r_resp_data_3_entry_carry; + wire _ftb_io_r_resp_data_3_entry_isCall; + wire _ftb_io_r_resp_data_3_entry_isRet; + wire _ftb_io_r_resp_data_3_entry_isJalr; + wire _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call; + wire _ftb_io_r_resp_data_3_entry_always_taken_0; + wire _ftb_io_r_resp_data_3_entry_always_taken_1; + wire [19:0] _ftb_io_r_resp_data_3_tag; + reg pred_rdata_REG; + reg pred_rdata_hold_data_0_entry_valid; + reg [3:0] pred_rdata_hold_data_0_entry_brSlots_0_offset; + reg [11:0] pred_rdata_hold_data_0_entry_brSlots_0_lower; + reg [1:0] pred_rdata_hold_data_0_entry_brSlots_0_tarStat; + reg pred_rdata_hold_data_0_entry_brSlots_0_sharing; + reg pred_rdata_hold_data_0_entry_brSlots_0_valid; + reg [3:0] pred_rdata_hold_data_0_entry_tailSlot_offset; + reg [19:0] pred_rdata_hold_data_0_entry_tailSlot_lower; + reg [1:0] pred_rdata_hold_data_0_entry_tailSlot_tarStat; + reg pred_rdata_hold_data_0_entry_tailSlot_sharing; + reg pred_rdata_hold_data_0_entry_tailSlot_valid; + reg [3:0] pred_rdata_hold_data_0_entry_pftAddr; + reg pred_rdata_hold_data_0_entry_carry; + reg pred_rdata_hold_data_0_entry_isCall; + reg pred_rdata_hold_data_0_entry_isRet; + reg pred_rdata_hold_data_0_entry_isJalr; + reg pred_rdata_hold_data_0_entry_last_may_be_rvi_call; + reg pred_rdata_hold_data_0_entry_always_taken_0; + reg pred_rdata_hold_data_0_entry_always_taken_1; + reg [19:0] pred_rdata_hold_data_0_tag; + reg pred_rdata_hold_data_1_entry_valid; + reg [3:0] pred_rdata_hold_data_1_entry_brSlots_0_offset; + reg [11:0] pred_rdata_hold_data_1_entry_brSlots_0_lower; + reg [1:0] pred_rdata_hold_data_1_entry_brSlots_0_tarStat; + reg pred_rdata_hold_data_1_entry_brSlots_0_sharing; + reg pred_rdata_hold_data_1_entry_brSlots_0_valid; + reg [3:0] pred_rdata_hold_data_1_entry_tailSlot_offset; + reg [19:0] pred_rdata_hold_data_1_entry_tailSlot_lower; + reg [1:0] pred_rdata_hold_data_1_entry_tailSlot_tarStat; + reg pred_rdata_hold_data_1_entry_tailSlot_sharing; + reg pred_rdata_hold_data_1_entry_tailSlot_valid; + reg [3:0] pred_rdata_hold_data_1_entry_pftAddr; + reg pred_rdata_hold_data_1_entry_carry; + reg pred_rdata_hold_data_1_entry_isCall; + reg pred_rdata_hold_data_1_entry_isRet; + reg pred_rdata_hold_data_1_entry_isJalr; + reg pred_rdata_hold_data_1_entry_last_may_be_rvi_call; + reg pred_rdata_hold_data_1_entry_always_taken_0; + reg pred_rdata_hold_data_1_entry_always_taken_1; + reg [19:0] pred_rdata_hold_data_1_tag; + reg pred_rdata_hold_data_2_entry_valid; + reg [3:0] pred_rdata_hold_data_2_entry_brSlots_0_offset; + reg [11:0] pred_rdata_hold_data_2_entry_brSlots_0_lower; + reg [1:0] pred_rdata_hold_data_2_entry_brSlots_0_tarStat; + reg pred_rdata_hold_data_2_entry_brSlots_0_sharing; + reg pred_rdata_hold_data_2_entry_brSlots_0_valid; + reg [3:0] pred_rdata_hold_data_2_entry_tailSlot_offset; + reg [19:0] pred_rdata_hold_data_2_entry_tailSlot_lower; + reg [1:0] pred_rdata_hold_data_2_entry_tailSlot_tarStat; + reg pred_rdata_hold_data_2_entry_tailSlot_sharing; + reg pred_rdata_hold_data_2_entry_tailSlot_valid; + reg [3:0] pred_rdata_hold_data_2_entry_pftAddr; + reg pred_rdata_hold_data_2_entry_carry; + reg pred_rdata_hold_data_2_entry_isCall; + reg pred_rdata_hold_data_2_entry_isRet; + reg pred_rdata_hold_data_2_entry_isJalr; + reg pred_rdata_hold_data_2_entry_last_may_be_rvi_call; + reg pred_rdata_hold_data_2_entry_always_taken_0; + reg pred_rdata_hold_data_2_entry_always_taken_1; + reg [19:0] pred_rdata_hold_data_2_tag; + reg pred_rdata_hold_data_3_entry_valid; + reg [3:0] pred_rdata_hold_data_3_entry_brSlots_0_offset; + reg [11:0] pred_rdata_hold_data_3_entry_brSlots_0_lower; + reg [1:0] pred_rdata_hold_data_3_entry_brSlots_0_tarStat; + reg pred_rdata_hold_data_3_entry_brSlots_0_sharing; + reg pred_rdata_hold_data_3_entry_brSlots_0_valid; + reg [3:0] pred_rdata_hold_data_3_entry_tailSlot_offset; + reg [19:0] pred_rdata_hold_data_3_entry_tailSlot_lower; + reg [1:0] pred_rdata_hold_data_3_entry_tailSlot_tarStat; + reg pred_rdata_hold_data_3_entry_tailSlot_sharing; + reg pred_rdata_hold_data_3_entry_tailSlot_valid; + reg [3:0] pred_rdata_hold_data_3_entry_pftAddr; + reg pred_rdata_hold_data_3_entry_carry; + reg pred_rdata_hold_data_3_entry_isCall; + reg pred_rdata_hold_data_3_entry_isRet; + reg pred_rdata_hold_data_3_entry_isJalr; + reg pred_rdata_hold_data_3_entry_last_may_be_rvi_call; + reg pred_rdata_hold_data_3_entry_always_taken_0; + reg pred_rdata_hold_data_3_entry_always_taken_1; + reg [19:0] pred_rdata_hold_data_3_tag; + wire pred_rdata_0_entry_valid = + pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_valid + : pred_rdata_hold_data_0_entry_valid; + wire pred_rdata_1_entry_valid = + pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_valid + : pred_rdata_hold_data_1_entry_valid; + wire pred_rdata_2_entry_valid = + pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_valid + : pred_rdata_hold_data_2_entry_valid; + wire pred_rdata_3_entry_valid = + pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_valid + : pred_rdata_hold_data_3_entry_valid; + reg [19:0] req_tag; + reg [8:0] req_idx; + reg [19:0] u_req_tag; + wire total_hits_0 = + (pred_rdata_REG ? _ftb_io_r_resp_data_0_tag : pred_rdata_hold_data_0_tag) == req_tag + & pred_rdata_0_entry_valid & io_s1_fire; + wire total_hits_1 = + (pred_rdata_REG ? _ftb_io_r_resp_data_1_tag : pred_rdata_hold_data_1_tag) == req_tag + & pred_rdata_1_entry_valid & io_s1_fire; + wire total_hits_2 = + (pred_rdata_REG ? _ftb_io_r_resp_data_2_tag : pred_rdata_hold_data_2_tag) == req_tag + & pred_rdata_2_entry_valid & io_s1_fire; + wire total_hits_3 = + (pred_rdata_REG ? _ftb_io_r_resp_data_3_tag : pred_rdata_hold_data_3_tag) == req_tag + & pred_rdata_3_entry_valid & io_s1_fire; + wire hit = total_hits_0 | total_hits_1 | total_hits_2 | total_hits_3; + wire [1:0] hit_way = + {|{total_hits_3, total_hits_2}, total_hits_3 | total_hits_1}; + reg u_total_hits_REG; + reg u_total_hits_REG_1; + wire u_total_hits_1 = + _ftb_io_r_resp_data_1_tag == u_req_tag & _ftb_io_r_resp_data_1_entry_valid + & u_total_hits_REG_1; + reg u_total_hits_REG_2; + wire u_total_hits_2 = + _ftb_io_r_resp_data_2_tag == u_req_tag & _ftb_io_r_resp_data_2_entry_valid + & u_total_hits_REG_2; + reg u_total_hits_REG_3; + wire u_total_hits_3 = + _ftb_io_r_resp_data_3_tag == u_req_tag & _ftb_io_r_resp_data_3_entry_valid + & u_total_hits_REG_3; + reg [2:0] state_vec_0; + reg [2:0] state_vec_1; + reg [2:0] state_vec_2; + reg [2:0] state_vec_3; + reg [2:0] state_vec_4; + reg [2:0] state_vec_5; + reg [2:0] state_vec_6; + reg [2:0] state_vec_7; + reg [2:0] state_vec_8; + reg [2:0] state_vec_9; + reg [2:0] state_vec_10; + reg [2:0] state_vec_11; + reg [2:0] state_vec_12; + reg [2:0] state_vec_13; + reg [2:0] state_vec_14; + reg [2:0] state_vec_15; + reg [2:0] state_vec_16; + reg [2:0] state_vec_17; + reg [2:0] state_vec_18; + reg [2:0] state_vec_19; + reg [2:0] state_vec_20; + reg [2:0] state_vec_21; + reg [2:0] state_vec_22; + reg [2:0] state_vec_23; + reg [2:0] state_vec_24; + reg [2:0] state_vec_25; + reg [2:0] state_vec_26; + reg [2:0] state_vec_27; + reg [2:0] state_vec_28; + reg [2:0] state_vec_29; + reg [2:0] state_vec_30; + reg [2:0] state_vec_31; + reg [2:0] state_vec_32; + reg [2:0] state_vec_33; + reg [2:0] state_vec_34; + reg [2:0] state_vec_35; + reg [2:0] state_vec_36; + reg [2:0] state_vec_37; + reg [2:0] state_vec_38; + reg [2:0] state_vec_39; + reg [2:0] state_vec_40; + reg [2:0] state_vec_41; + reg [2:0] state_vec_42; + reg [2:0] state_vec_43; + reg [2:0] state_vec_44; + reg [2:0] state_vec_45; + reg [2:0] state_vec_46; + reg [2:0] state_vec_47; + reg [2:0] state_vec_48; + reg [2:0] state_vec_49; + reg [2:0] state_vec_50; + reg [2:0] state_vec_51; + reg [2:0] state_vec_52; + reg [2:0] state_vec_53; + reg [2:0] state_vec_54; + reg [2:0] state_vec_55; + reg [2:0] state_vec_56; + reg [2:0] state_vec_57; + reg [2:0] state_vec_58; + reg [2:0] state_vec_59; + reg [2:0] state_vec_60; + reg [2:0] state_vec_61; + reg [2:0] state_vec_62; + reg [2:0] state_vec_63; + reg [2:0] state_vec_64; + reg [2:0] state_vec_65; + reg [2:0] state_vec_66; + reg [2:0] state_vec_67; + reg [2:0] state_vec_68; + reg [2:0] state_vec_69; + reg [2:0] state_vec_70; + reg [2:0] state_vec_71; + reg [2:0] state_vec_72; + reg [2:0] state_vec_73; + reg [2:0] state_vec_74; + reg [2:0] state_vec_75; + reg [2:0] state_vec_76; + reg [2:0] state_vec_77; + reg [2:0] state_vec_78; + reg [2:0] state_vec_79; + reg [2:0] state_vec_80; + reg [2:0] state_vec_81; + reg [2:0] state_vec_82; + reg [2:0] state_vec_83; + reg [2:0] state_vec_84; + reg [2:0] state_vec_85; + reg [2:0] state_vec_86; + reg [2:0] state_vec_87; + reg [2:0] state_vec_88; + reg [2:0] state_vec_89; + reg [2:0] state_vec_90; + reg [2:0] state_vec_91; + reg [2:0] state_vec_92; + reg [2:0] state_vec_93; + reg [2:0] state_vec_94; + reg [2:0] state_vec_95; + reg [2:0] state_vec_96; + reg [2:0] state_vec_97; + reg [2:0] state_vec_98; + reg [2:0] state_vec_99; + reg [2:0] state_vec_100; + reg [2:0] state_vec_101; + reg [2:0] state_vec_102; + reg [2:0] state_vec_103; + reg [2:0] state_vec_104; + reg [2:0] state_vec_105; + reg [2:0] state_vec_106; + reg [2:0] state_vec_107; + reg [2:0] state_vec_108; + reg [2:0] state_vec_109; + reg [2:0] state_vec_110; + reg [2:0] state_vec_111; + reg [2:0] state_vec_112; + reg [2:0] state_vec_113; + reg [2:0] state_vec_114; + reg [2:0] state_vec_115; + reg [2:0] state_vec_116; + reg [2:0] state_vec_117; + reg [2:0] state_vec_118; + reg [2:0] state_vec_119; + reg [2:0] state_vec_120; + reg [2:0] state_vec_121; + reg [2:0] state_vec_122; + reg [2:0] state_vec_123; + reg [2:0] state_vec_124; + reg [2:0] state_vec_125; + reg [2:0] state_vec_126; + reg [2:0] state_vec_127; + reg [2:0] state_vec_128; + reg [2:0] state_vec_129; + reg [2:0] state_vec_130; + reg [2:0] state_vec_131; + reg [2:0] state_vec_132; + reg [2:0] state_vec_133; + reg [2:0] state_vec_134; + reg [2:0] state_vec_135; + reg [2:0] state_vec_136; + reg [2:0] state_vec_137; + reg [2:0] state_vec_138; + reg [2:0] state_vec_139; + reg [2:0] state_vec_140; + reg [2:0] state_vec_141; + reg [2:0] state_vec_142; + reg [2:0] state_vec_143; + reg [2:0] state_vec_144; + reg [2:0] state_vec_145; + reg [2:0] state_vec_146; + reg [2:0] state_vec_147; + reg [2:0] state_vec_148; + reg [2:0] state_vec_149; + reg [2:0] state_vec_150; + reg [2:0] state_vec_151; + reg [2:0] state_vec_152; + reg [2:0] state_vec_153; + reg [2:0] state_vec_154; + reg [2:0] state_vec_155; + reg [2:0] state_vec_156; + reg [2:0] state_vec_157; + reg [2:0] state_vec_158; + reg [2:0] state_vec_159; + reg [2:0] state_vec_160; + reg [2:0] state_vec_161; + reg [2:0] state_vec_162; + reg [2:0] state_vec_163; + reg [2:0] state_vec_164; + reg [2:0] state_vec_165; + reg [2:0] state_vec_166; + reg [2:0] state_vec_167; + reg [2:0] state_vec_168; + reg [2:0] state_vec_169; + reg [2:0] state_vec_170; + reg [2:0] state_vec_171; + reg [2:0] state_vec_172; + reg [2:0] state_vec_173; + reg [2:0] state_vec_174; + reg [2:0] state_vec_175; + reg [2:0] state_vec_176; + reg [2:0] state_vec_177; + reg [2:0] state_vec_178; + reg [2:0] state_vec_179; + reg [2:0] state_vec_180; + reg [2:0] state_vec_181; + reg [2:0] state_vec_182; + reg [2:0] state_vec_183; + reg [2:0] state_vec_184; + reg [2:0] state_vec_185; + reg [2:0] state_vec_186; + reg [2:0] state_vec_187; + reg [2:0] state_vec_188; + reg [2:0] state_vec_189; + reg [2:0] state_vec_190; + reg [2:0] state_vec_191; + reg [2:0] state_vec_192; + reg [2:0] state_vec_193; + reg [2:0] state_vec_194; + reg [2:0] state_vec_195; + reg [2:0] state_vec_196; + reg [2:0] state_vec_197; + reg [2:0] state_vec_198; + reg [2:0] state_vec_199; + reg [2:0] state_vec_200; + reg [2:0] state_vec_201; + reg [2:0] state_vec_202; + reg [2:0] state_vec_203; + reg [2:0] state_vec_204; + reg [2:0] state_vec_205; + reg [2:0] state_vec_206; + reg [2:0] state_vec_207; + reg [2:0] state_vec_208; + reg [2:0] state_vec_209; + reg [2:0] state_vec_210; + reg [2:0] state_vec_211; + reg [2:0] state_vec_212; + reg [2:0] state_vec_213; + reg [2:0] state_vec_214; + reg [2:0] state_vec_215; + reg [2:0] state_vec_216; + reg [2:0] state_vec_217; + reg [2:0] state_vec_218; + reg [2:0] state_vec_219; + reg [2:0] state_vec_220; + reg [2:0] state_vec_221; + reg [2:0] state_vec_222; + reg [2:0] state_vec_223; + reg [2:0] state_vec_224; + reg [2:0] state_vec_225; + reg [2:0] state_vec_226; + reg [2:0] state_vec_227; + reg [2:0] state_vec_228; + reg [2:0] state_vec_229; + reg [2:0] state_vec_230; + reg [2:0] state_vec_231; + reg [2:0] state_vec_232; + reg [2:0] state_vec_233; + reg [2:0] state_vec_234; + reg [2:0] state_vec_235; + reg [2:0] state_vec_236; + reg [2:0] state_vec_237; + reg [2:0] state_vec_238; + reg [2:0] state_vec_239; + reg [2:0] state_vec_240; + reg [2:0] state_vec_241; + reg [2:0] state_vec_242; + reg [2:0] state_vec_243; + reg [2:0] state_vec_244; + reg [2:0] state_vec_245; + reg [2:0] state_vec_246; + reg [2:0] state_vec_247; + reg [2:0] state_vec_248; + reg [2:0] state_vec_249; + reg [2:0] state_vec_250; + reg [2:0] state_vec_251; + reg [2:0] state_vec_252; + reg [2:0] state_vec_253; + reg [2:0] state_vec_254; + reg [2:0] state_vec_255; + reg [2:0] state_vec_256; + reg [2:0] state_vec_257; + reg [2:0] state_vec_258; + reg [2:0] state_vec_259; + reg [2:0] state_vec_260; + reg [2:0] state_vec_261; + reg [2:0] state_vec_262; + reg [2:0] state_vec_263; + reg [2:0] state_vec_264; + reg [2:0] state_vec_265; + reg [2:0] state_vec_266; + reg [2:0] state_vec_267; + reg [2:0] state_vec_268; + reg [2:0] state_vec_269; + reg [2:0] state_vec_270; + reg [2:0] state_vec_271; + reg [2:0] state_vec_272; + reg [2:0] state_vec_273; + reg [2:0] state_vec_274; + reg [2:0] state_vec_275; + reg [2:0] state_vec_276; + reg [2:0] state_vec_277; + reg [2:0] state_vec_278; + reg [2:0] state_vec_279; + reg [2:0] state_vec_280; + reg [2:0] state_vec_281; + reg [2:0] state_vec_282; + reg [2:0] state_vec_283; + reg [2:0] state_vec_284; + reg [2:0] state_vec_285; + reg [2:0] state_vec_286; + reg [2:0] state_vec_287; + reg [2:0] state_vec_288; + reg [2:0] state_vec_289; + reg [2:0] state_vec_290; + reg [2:0] state_vec_291; + reg [2:0] state_vec_292; + reg [2:0] state_vec_293; + reg [2:0] state_vec_294; + reg [2:0] state_vec_295; + reg [2:0] state_vec_296; + reg [2:0] state_vec_297; + reg [2:0] state_vec_298; + reg [2:0] state_vec_299; + reg [2:0] state_vec_300; + reg [2:0] state_vec_301; + reg [2:0] state_vec_302; + reg [2:0] state_vec_303; + reg [2:0] state_vec_304; + reg [2:0] state_vec_305; + reg [2:0] state_vec_306; + reg [2:0] state_vec_307; + reg [2:0] state_vec_308; + reg [2:0] state_vec_309; + reg [2:0] state_vec_310; + reg [2:0] state_vec_311; + reg [2:0] state_vec_312; + reg [2:0] state_vec_313; + reg [2:0] state_vec_314; + reg [2:0] state_vec_315; + reg [2:0] state_vec_316; + reg [2:0] state_vec_317; + reg [2:0] state_vec_318; + reg [2:0] state_vec_319; + reg [2:0] state_vec_320; + reg [2:0] state_vec_321; + reg [2:0] state_vec_322; + reg [2:0] state_vec_323; + reg [2:0] state_vec_324; + reg [2:0] state_vec_325; + reg [2:0] state_vec_326; + reg [2:0] state_vec_327; + reg [2:0] state_vec_328; + reg [2:0] state_vec_329; + reg [2:0] state_vec_330; + reg [2:0] state_vec_331; + reg [2:0] state_vec_332; + reg [2:0] state_vec_333; + reg [2:0] state_vec_334; + reg [2:0] state_vec_335; + reg [2:0] state_vec_336; + reg [2:0] state_vec_337; + reg [2:0] state_vec_338; + reg [2:0] state_vec_339; + reg [2:0] state_vec_340; + reg [2:0] state_vec_341; + reg [2:0] state_vec_342; + reg [2:0] state_vec_343; + reg [2:0] state_vec_344; + reg [2:0] state_vec_345; + reg [2:0] state_vec_346; + reg [2:0] state_vec_347; + reg [2:0] state_vec_348; + reg [2:0] state_vec_349; + reg [2:0] state_vec_350; + reg [2:0] state_vec_351; + reg [2:0] state_vec_352; + reg [2:0] state_vec_353; + reg [2:0] state_vec_354; + reg [2:0] state_vec_355; + reg [2:0] state_vec_356; + reg [2:0] state_vec_357; + reg [2:0] state_vec_358; + reg [2:0] state_vec_359; + reg [2:0] state_vec_360; + reg [2:0] state_vec_361; + reg [2:0] state_vec_362; + reg [2:0] state_vec_363; + reg [2:0] state_vec_364; + reg [2:0] state_vec_365; + reg [2:0] state_vec_366; + reg [2:0] state_vec_367; + reg [2:0] state_vec_368; + reg [2:0] state_vec_369; + reg [2:0] state_vec_370; + reg [2:0] state_vec_371; + reg [2:0] state_vec_372; + reg [2:0] state_vec_373; + reg [2:0] state_vec_374; + reg [2:0] state_vec_375; + reg [2:0] state_vec_376; + reg [2:0] state_vec_377; + reg [2:0] state_vec_378; + reg [2:0] state_vec_379; + reg [2:0] state_vec_380; + reg [2:0] state_vec_381; + reg [2:0] state_vec_382; + reg [2:0] state_vec_383; + reg [2:0] state_vec_384; + reg [2:0] state_vec_385; + reg [2:0] state_vec_386; + reg [2:0] state_vec_387; + reg [2:0] state_vec_388; + reg [2:0] state_vec_389; + reg [2:0] state_vec_390; + reg [2:0] state_vec_391; + reg [2:0] state_vec_392; + reg [2:0] state_vec_393; + reg [2:0] state_vec_394; + reg [2:0] state_vec_395; + reg [2:0] state_vec_396; + reg [2:0] state_vec_397; + reg [2:0] state_vec_398; + reg [2:0] state_vec_399; + reg [2:0] state_vec_400; + reg [2:0] state_vec_401; + reg [2:0] state_vec_402; + reg [2:0] state_vec_403; + reg [2:0] state_vec_404; + reg [2:0] state_vec_405; + reg [2:0] state_vec_406; + reg [2:0] state_vec_407; + reg [2:0] state_vec_408; + reg [2:0] state_vec_409; + reg [2:0] state_vec_410; + reg [2:0] state_vec_411; + reg [2:0] state_vec_412; + reg [2:0] state_vec_413; + reg [2:0] state_vec_414; + reg [2:0] state_vec_415; + reg [2:0] state_vec_416; + reg [2:0] state_vec_417; + reg [2:0] state_vec_418; + reg [2:0] state_vec_419; + reg [2:0] state_vec_420; + reg [2:0] state_vec_421; + reg [2:0] state_vec_422; + reg [2:0] state_vec_423; + reg [2:0] state_vec_424; + reg [2:0] state_vec_425; + reg [2:0] state_vec_426; + reg [2:0] state_vec_427; + reg [2:0] state_vec_428; + reg [2:0] state_vec_429; + reg [2:0] state_vec_430; + reg [2:0] state_vec_431; + reg [2:0] state_vec_432; + reg [2:0] state_vec_433; + reg [2:0] state_vec_434; + reg [2:0] state_vec_435; + reg [2:0] state_vec_436; + reg [2:0] state_vec_437; + reg [2:0] state_vec_438; + reg [2:0] state_vec_439; + reg [2:0] state_vec_440; + reg [2:0] state_vec_441; + reg [2:0] state_vec_442; + reg [2:0] state_vec_443; + reg [2:0] state_vec_444; + reg [2:0] state_vec_445; + reg [2:0] state_vec_446; + reg [2:0] state_vec_447; + reg [2:0] state_vec_448; + reg [2:0] state_vec_449; + reg [2:0] state_vec_450; + reg [2:0] state_vec_451; + reg [2:0] state_vec_452; + reg [2:0] state_vec_453; + reg [2:0] state_vec_454; + reg [2:0] state_vec_455; + reg [2:0] state_vec_456; + reg [2:0] state_vec_457; + reg [2:0] state_vec_458; + reg [2:0] state_vec_459; + reg [2:0] state_vec_460; + reg [2:0] state_vec_461; + reg [2:0] state_vec_462; + reg [2:0] state_vec_463; + reg [2:0] state_vec_464; + reg [2:0] state_vec_465; + reg [2:0] state_vec_466; + reg [2:0] state_vec_467; + reg [2:0] state_vec_468; + reg [2:0] state_vec_469; + reg [2:0] state_vec_470; + reg [2:0] state_vec_471; + reg [2:0] state_vec_472; + reg [2:0] state_vec_473; + reg [2:0] state_vec_474; + reg [2:0] state_vec_475; + reg [2:0] state_vec_476; + reg [2:0] state_vec_477; + reg [2:0] state_vec_478; + reg [2:0] state_vec_479; + reg [2:0] state_vec_480; + reg [2:0] state_vec_481; + reg [2:0] state_vec_482; + reg [2:0] state_vec_483; + reg [2:0] state_vec_484; + reg [2:0] state_vec_485; + reg [2:0] state_vec_486; + reg [2:0] state_vec_487; + reg [2:0] state_vec_488; + reg [2:0] state_vec_489; + reg [2:0] state_vec_490; + reg [2:0] state_vec_491; + reg [2:0] state_vec_492; + reg [2:0] state_vec_493; + reg [2:0] state_vec_494; + reg [2:0] state_vec_495; + reg [2:0] state_vec_496; + reg [2:0] state_vec_497; + reg [2:0] state_vec_498; + reg [2:0] state_vec_499; + reg [2:0] state_vec_500; + reg [2:0] state_vec_501; + reg [2:0] state_vec_502; + reg [2:0] state_vec_503; + reg [2:0] state_vec_504; + reg [2:0] state_vec_505; + reg [2:0] state_vec_506; + reg [2:0] state_vec_507; + reg [2:0] state_vec_508; + reg [2:0] state_vec_509; + reg [2:0] state_vec_510; + reg [2:0] state_vec_511; + reg [8:0] touch_set_0_REG; + reg touch_way_0_valid_REG; + reg [1:0] touch_way_0_bits_REG; + reg allocWriteWay_REG_0; + reg allocWriteWay_REG_1; + reg allocWriteWay_REG_2; + reg allocWriteWay_REG_3; + wire [511:0][2:0] _GEN = + {{state_vec_511}, + {state_vec_510}, + {state_vec_509}, + {state_vec_508}, + {state_vec_507}, + {state_vec_506}, + {state_vec_505}, + {state_vec_504}, + {state_vec_503}, + {state_vec_502}, + {state_vec_501}, + {state_vec_500}, + {state_vec_499}, + {state_vec_498}, + {state_vec_497}, + {state_vec_496}, + {state_vec_495}, + {state_vec_494}, + {state_vec_493}, + {state_vec_492}, + {state_vec_491}, + {state_vec_490}, + {state_vec_489}, + {state_vec_488}, + {state_vec_487}, + {state_vec_486}, + {state_vec_485}, + {state_vec_484}, + {state_vec_483}, + {state_vec_482}, + {state_vec_481}, + {state_vec_480}, + {state_vec_479}, + {state_vec_478}, + {state_vec_477}, + {state_vec_476}, + {state_vec_475}, + {state_vec_474}, + {state_vec_473}, + {state_vec_472}, + {state_vec_471}, + {state_vec_470}, + {state_vec_469}, + {state_vec_468}, + {state_vec_467}, + {state_vec_466}, + {state_vec_465}, + {state_vec_464}, + {state_vec_463}, + {state_vec_462}, + {state_vec_461}, + {state_vec_460}, + {state_vec_459}, + {state_vec_458}, + {state_vec_457}, + {state_vec_456}, + {state_vec_455}, + {state_vec_454}, + {state_vec_453}, + {state_vec_452}, + {state_vec_451}, + {state_vec_450}, + {state_vec_449}, + {state_vec_448}, + {state_vec_447}, + {state_vec_446}, + {state_vec_445}, + {state_vec_444}, + {state_vec_443}, + {state_vec_442}, + {state_vec_441}, + {state_vec_440}, + {state_vec_439}, + {state_vec_438}, + {state_vec_437}, + {state_vec_436}, + {state_vec_435}, + {state_vec_434}, + {state_vec_433}, + {state_vec_432}, + {state_vec_431}, + {state_vec_430}, + {state_vec_429}, + {state_vec_428}, + {state_vec_427}, + {state_vec_426}, + {state_vec_425}, + {state_vec_424}, + {state_vec_423}, + {state_vec_422}, + {state_vec_421}, + {state_vec_420}, + {state_vec_419}, + {state_vec_418}, + {state_vec_417}, + {state_vec_416}, + {state_vec_415}, + {state_vec_414}, + {state_vec_413}, + {state_vec_412}, + {state_vec_411}, + {state_vec_410}, + {state_vec_409}, + {state_vec_408}, + {state_vec_407}, + {state_vec_406}, + {state_vec_405}, + {state_vec_404}, + {state_vec_403}, + {state_vec_402}, + {state_vec_401}, + {state_vec_400}, + {state_vec_399}, + {state_vec_398}, + {state_vec_397}, + {state_vec_396}, + {state_vec_395}, + {state_vec_394}, + {state_vec_393}, + {state_vec_392}, + {state_vec_391}, + {state_vec_390}, + {state_vec_389}, + {state_vec_388}, + {state_vec_387}, + {state_vec_386}, + {state_vec_385}, + {state_vec_384}, + {state_vec_383}, + {state_vec_382}, + {state_vec_381}, + {state_vec_380}, + {state_vec_379}, + {state_vec_378}, + {state_vec_377}, + {state_vec_376}, + {state_vec_375}, + {state_vec_374}, + {state_vec_373}, + {state_vec_372}, + {state_vec_371}, + {state_vec_370}, + {state_vec_369}, + {state_vec_368}, + {state_vec_367}, + {state_vec_366}, + {state_vec_365}, + {state_vec_364}, + {state_vec_363}, + {state_vec_362}, + {state_vec_361}, + {state_vec_360}, + {state_vec_359}, + {state_vec_358}, + {state_vec_357}, + {state_vec_356}, + {state_vec_355}, + {state_vec_354}, + {state_vec_353}, + {state_vec_352}, + {state_vec_351}, + {state_vec_350}, + {state_vec_349}, + {state_vec_348}, + {state_vec_347}, + {state_vec_346}, + {state_vec_345}, + {state_vec_344}, + {state_vec_343}, + {state_vec_342}, + {state_vec_341}, + {state_vec_340}, + {state_vec_339}, + {state_vec_338}, + {state_vec_337}, + {state_vec_336}, + {state_vec_335}, + {state_vec_334}, + {state_vec_333}, + {state_vec_332}, + {state_vec_331}, + {state_vec_330}, + {state_vec_329}, + {state_vec_328}, + {state_vec_327}, + {state_vec_326}, + {state_vec_325}, + {state_vec_324}, + {state_vec_323}, + {state_vec_322}, + {state_vec_321}, + {state_vec_320}, + {state_vec_319}, + {state_vec_318}, + {state_vec_317}, + {state_vec_316}, + {state_vec_315}, + {state_vec_314}, + {state_vec_313}, + {state_vec_312}, + {state_vec_311}, + {state_vec_310}, + {state_vec_309}, + {state_vec_308}, + {state_vec_307}, + {state_vec_306}, + {state_vec_305}, + {state_vec_304}, + {state_vec_303}, + {state_vec_302}, + {state_vec_301}, + {state_vec_300}, + {state_vec_299}, + {state_vec_298}, + {state_vec_297}, + {state_vec_296}, + {state_vec_295}, + {state_vec_294}, + {state_vec_293}, + {state_vec_292}, + {state_vec_291}, + {state_vec_290}, + {state_vec_289}, + {state_vec_288}, + {state_vec_287}, + {state_vec_286}, + {state_vec_285}, + {state_vec_284}, + {state_vec_283}, + {state_vec_282}, + {state_vec_281}, + {state_vec_280}, + {state_vec_279}, + {state_vec_278}, + {state_vec_277}, + {state_vec_276}, + {state_vec_275}, + {state_vec_274}, + {state_vec_273}, + {state_vec_272}, + {state_vec_271}, + {state_vec_270}, + {state_vec_269}, + {state_vec_268}, + {state_vec_267}, + {state_vec_266}, + {state_vec_265}, + {state_vec_264}, + {state_vec_263}, + {state_vec_262}, + {state_vec_261}, + {state_vec_260}, + {state_vec_259}, + {state_vec_258}, + {state_vec_257}, + {state_vec_256}, + {state_vec_255}, + {state_vec_254}, + {state_vec_253}, + {state_vec_252}, + {state_vec_251}, + {state_vec_250}, + {state_vec_249}, + {state_vec_248}, + {state_vec_247}, + {state_vec_246}, + {state_vec_245}, + {state_vec_244}, + {state_vec_243}, + {state_vec_242}, + {state_vec_241}, + {state_vec_240}, + {state_vec_239}, + {state_vec_238}, + {state_vec_237}, + {state_vec_236}, + {state_vec_235}, + {state_vec_234}, + {state_vec_233}, + {state_vec_232}, + {state_vec_231}, + {state_vec_230}, + {state_vec_229}, + {state_vec_228}, + {state_vec_227}, + {state_vec_226}, + {state_vec_225}, + {state_vec_224}, + {state_vec_223}, + {state_vec_222}, + {state_vec_221}, + {state_vec_220}, + {state_vec_219}, + {state_vec_218}, + {state_vec_217}, + {state_vec_216}, + {state_vec_215}, + {state_vec_214}, + {state_vec_213}, + {state_vec_212}, + {state_vec_211}, + {state_vec_210}, + {state_vec_209}, + {state_vec_208}, + {state_vec_207}, + {state_vec_206}, + {state_vec_205}, + {state_vec_204}, + {state_vec_203}, + {state_vec_202}, + {state_vec_201}, + {state_vec_200}, + {state_vec_199}, + {state_vec_198}, + {state_vec_197}, + {state_vec_196}, + {state_vec_195}, + {state_vec_194}, + {state_vec_193}, + {state_vec_192}, + {state_vec_191}, + {state_vec_190}, + {state_vec_189}, + {state_vec_188}, + {state_vec_187}, + {state_vec_186}, + {state_vec_185}, + {state_vec_184}, + {state_vec_183}, + {state_vec_182}, + {state_vec_181}, + {state_vec_180}, + {state_vec_179}, + {state_vec_178}, + {state_vec_177}, + {state_vec_176}, + {state_vec_175}, + {state_vec_174}, + {state_vec_173}, + {state_vec_172}, + {state_vec_171}, + {state_vec_170}, + {state_vec_169}, + {state_vec_168}, + {state_vec_167}, + {state_vec_166}, + {state_vec_165}, + {state_vec_164}, + {state_vec_163}, + {state_vec_162}, + {state_vec_161}, + {state_vec_160}, + {state_vec_159}, + {state_vec_158}, + {state_vec_157}, + {state_vec_156}, + {state_vec_155}, + {state_vec_154}, + {state_vec_153}, + {state_vec_152}, + {state_vec_151}, + {state_vec_150}, + {state_vec_149}, + {state_vec_148}, + {state_vec_147}, + {state_vec_146}, + {state_vec_145}, + {state_vec_144}, + {state_vec_143}, + {state_vec_142}, + {state_vec_141}, + {state_vec_140}, + {state_vec_139}, + {state_vec_138}, + {state_vec_137}, + {state_vec_136}, + {state_vec_135}, + {state_vec_134}, + {state_vec_133}, + {state_vec_132}, + {state_vec_131}, + {state_vec_130}, + {state_vec_129}, + {state_vec_128}, + {state_vec_127}, + {state_vec_126}, + {state_vec_125}, + {state_vec_124}, + {state_vec_123}, + {state_vec_122}, + {state_vec_121}, + {state_vec_120}, + {state_vec_119}, + {state_vec_118}, + {state_vec_117}, + {state_vec_116}, + {state_vec_115}, + {state_vec_114}, + {state_vec_113}, + {state_vec_112}, + {state_vec_111}, + {state_vec_110}, + {state_vec_109}, + {state_vec_108}, + {state_vec_107}, + {state_vec_106}, + {state_vec_105}, + {state_vec_104}, + {state_vec_103}, + {state_vec_102}, + {state_vec_101}, + {state_vec_100}, + {state_vec_99}, + {state_vec_98}, + {state_vec_97}, + {state_vec_96}, + {state_vec_95}, + {state_vec_94}, + {state_vec_93}, + {state_vec_92}, + {state_vec_91}, + {state_vec_90}, + {state_vec_89}, + {state_vec_88}, + {state_vec_87}, + {state_vec_86}, + {state_vec_85}, + {state_vec_84}, + {state_vec_83}, + {state_vec_82}, + {state_vec_81}, + {state_vec_80}, + {state_vec_79}, + {state_vec_78}, + {state_vec_77}, + {state_vec_76}, + {state_vec_75}, + {state_vec_74}, + {state_vec_73}, + {state_vec_72}, + {state_vec_71}, + {state_vec_70}, + {state_vec_69}, + {state_vec_68}, + {state_vec_67}, + {state_vec_66}, + {state_vec_65}, + {state_vec_64}, + {state_vec_63}, + {state_vec_62}, + {state_vec_61}, + {state_vec_60}, + {state_vec_59}, + {state_vec_58}, + {state_vec_57}, + {state_vec_56}, + {state_vec_55}, + {state_vec_54}, + {state_vec_53}, + {state_vec_52}, + {state_vec_51}, + {state_vec_50}, + {state_vec_49}, + {state_vec_48}, + {state_vec_47}, + {state_vec_46}, + {state_vec_45}, + {state_vec_44}, + {state_vec_43}, + {state_vec_42}, + {state_vec_41}, + {state_vec_40}, + {state_vec_39}, + {state_vec_38}, + {state_vec_37}, + {state_vec_36}, + {state_vec_35}, + {state_vec_34}, + {state_vec_33}, + {state_vec_32}, + {state_vec_31}, + {state_vec_30}, + {state_vec_29}, + {state_vec_28}, + {state_vec_27}, + {state_vec_26}, + {state_vec_25}, + {state_vec_24}, + {state_vec_23}, + {state_vec_22}, + {state_vec_21}, + {state_vec_20}, + {state_vec_19}, + {state_vec_18}, + {state_vec_17}, + {state_vec_16}, + {state_vec_15}, + {state_vec_14}, + {state_vec_13}, + {state_vec_12}, + {state_vec_11}, + {state_vec_10}, + {state_vec_9}, + {state_vec_8}, + {state_vec_7}, + {state_vec_6}, + {state_vec_5}, + {state_vec_4}, + {state_vec_3}, + {state_vec_2}, + {state_vec_1}, + {state_vec_0}}; + wire [2:0] _GEN_0 = _GEN[io_update_pc[9:1]]; + wire [2:0] _allocWriteWay_w_T_4 = + ~{allocWriteWay_REG_2, allocWriteWay_REG_1, allocWriteWay_REG_0}; + wire [1:0] u_way = + io_update_write_alloc + ? ((&{allocWriteWay_REG_3, + allocWriteWay_REG_2, + allocWriteWay_REG_1, + allocWriteWay_REG_0}) + ? {_GEN_0[2], _GEN_0[2] ? _GEN_0[1] : _GEN_0[0]} + : _allocWriteWay_w_T_4[0] + ? 2'h0 + : _allocWriteWay_w_T_4[1] ? 2'h1 : {1'h1, ~(_allocWriteWay_w_T_4[2])}) + : io_update_write_way; + always @(posedge clock) begin + pred_rdata_REG <= io_req_pc_valid & ~io_update_access; + if (pred_rdata_REG) begin + pred_rdata_hold_data_0_entry_valid <= _ftb_io_r_resp_data_0_entry_valid; + pred_rdata_hold_data_0_entry_brSlots_0_offset <= + _ftb_io_r_resp_data_0_entry_brSlots_0_offset; + pred_rdata_hold_data_0_entry_brSlots_0_lower <= + _ftb_io_r_resp_data_0_entry_brSlots_0_lower; + pred_rdata_hold_data_0_entry_brSlots_0_tarStat <= + _ftb_io_r_resp_data_0_entry_brSlots_0_tarStat; + pred_rdata_hold_data_0_entry_brSlots_0_sharing <= + _ftb_io_r_resp_data_0_entry_brSlots_0_sharing; + pred_rdata_hold_data_0_entry_brSlots_0_valid <= + _ftb_io_r_resp_data_0_entry_brSlots_0_valid; + pred_rdata_hold_data_0_entry_tailSlot_offset <= + _ftb_io_r_resp_data_0_entry_tailSlot_offset; + pred_rdata_hold_data_0_entry_tailSlot_lower <= + _ftb_io_r_resp_data_0_entry_tailSlot_lower; + pred_rdata_hold_data_0_entry_tailSlot_tarStat <= + _ftb_io_r_resp_data_0_entry_tailSlot_tarStat; + pred_rdata_hold_data_0_entry_tailSlot_sharing <= + _ftb_io_r_resp_data_0_entry_tailSlot_sharing; + pred_rdata_hold_data_0_entry_tailSlot_valid <= + _ftb_io_r_resp_data_0_entry_tailSlot_valid; + pred_rdata_hold_data_0_entry_pftAddr <= _ftb_io_r_resp_data_0_entry_pftAddr; + pred_rdata_hold_data_0_entry_carry <= _ftb_io_r_resp_data_0_entry_carry; + pred_rdata_hold_data_0_entry_isCall <= _ftb_io_r_resp_data_0_entry_isCall; + pred_rdata_hold_data_0_entry_isRet <= _ftb_io_r_resp_data_0_entry_isRet; + pred_rdata_hold_data_0_entry_isJalr <= _ftb_io_r_resp_data_0_entry_isJalr; + pred_rdata_hold_data_0_entry_last_may_be_rvi_call <= + _ftb_io_r_resp_data_0_entry_last_may_be_rvi_call; + pred_rdata_hold_data_0_entry_always_taken_0 <= + _ftb_io_r_resp_data_0_entry_always_taken_0; + pred_rdata_hold_data_0_entry_always_taken_1 <= + _ftb_io_r_resp_data_0_entry_always_taken_1; + pred_rdata_hold_data_0_tag <= _ftb_io_r_resp_data_0_tag; + pred_rdata_hold_data_1_entry_valid <= _ftb_io_r_resp_data_1_entry_valid; + pred_rdata_hold_data_1_entry_brSlots_0_offset <= + _ftb_io_r_resp_data_1_entry_brSlots_0_offset; + pred_rdata_hold_data_1_entry_brSlots_0_lower <= + _ftb_io_r_resp_data_1_entry_brSlots_0_lower; + pred_rdata_hold_data_1_entry_brSlots_0_tarStat <= + _ftb_io_r_resp_data_1_entry_brSlots_0_tarStat; + pred_rdata_hold_data_1_entry_brSlots_0_sharing <= + _ftb_io_r_resp_data_1_entry_brSlots_0_sharing; + pred_rdata_hold_data_1_entry_brSlots_0_valid <= + _ftb_io_r_resp_data_1_entry_brSlots_0_valid; + pred_rdata_hold_data_1_entry_tailSlot_offset <= + _ftb_io_r_resp_data_1_entry_tailSlot_offset; + pred_rdata_hold_data_1_entry_tailSlot_lower <= + _ftb_io_r_resp_data_1_entry_tailSlot_lower; + pred_rdata_hold_data_1_entry_tailSlot_tarStat <= + _ftb_io_r_resp_data_1_entry_tailSlot_tarStat; + pred_rdata_hold_data_1_entry_tailSlot_sharing <= + _ftb_io_r_resp_data_1_entry_tailSlot_sharing; + pred_rdata_hold_data_1_entry_tailSlot_valid <= + _ftb_io_r_resp_data_1_entry_tailSlot_valid; + pred_rdata_hold_data_1_entry_pftAddr <= _ftb_io_r_resp_data_1_entry_pftAddr; + pred_rdata_hold_data_1_entry_carry <= _ftb_io_r_resp_data_1_entry_carry; + pred_rdata_hold_data_1_entry_isCall <= _ftb_io_r_resp_data_1_entry_isCall; + pred_rdata_hold_data_1_entry_isRet <= _ftb_io_r_resp_data_1_entry_isRet; + pred_rdata_hold_data_1_entry_isJalr <= _ftb_io_r_resp_data_1_entry_isJalr; + pred_rdata_hold_data_1_entry_last_may_be_rvi_call <= + _ftb_io_r_resp_data_1_entry_last_may_be_rvi_call; + pred_rdata_hold_data_1_entry_always_taken_0 <= + _ftb_io_r_resp_data_1_entry_always_taken_0; + pred_rdata_hold_data_1_entry_always_taken_1 <= + _ftb_io_r_resp_data_1_entry_always_taken_1; + pred_rdata_hold_data_1_tag <= _ftb_io_r_resp_data_1_tag; + pred_rdata_hold_data_2_entry_valid <= _ftb_io_r_resp_data_2_entry_valid; + pred_rdata_hold_data_2_entry_brSlots_0_offset <= + _ftb_io_r_resp_data_2_entry_brSlots_0_offset; + pred_rdata_hold_data_2_entry_brSlots_0_lower <= + _ftb_io_r_resp_data_2_entry_brSlots_0_lower; + pred_rdata_hold_data_2_entry_brSlots_0_tarStat <= + _ftb_io_r_resp_data_2_entry_brSlots_0_tarStat; + pred_rdata_hold_data_2_entry_brSlots_0_sharing <= + _ftb_io_r_resp_data_2_entry_brSlots_0_sharing; + pred_rdata_hold_data_2_entry_brSlots_0_valid <= + _ftb_io_r_resp_data_2_entry_brSlots_0_valid; + pred_rdata_hold_data_2_entry_tailSlot_offset <= + _ftb_io_r_resp_data_2_entry_tailSlot_offset; + pred_rdata_hold_data_2_entry_tailSlot_lower <= + _ftb_io_r_resp_data_2_entry_tailSlot_lower; + pred_rdata_hold_data_2_entry_tailSlot_tarStat <= + _ftb_io_r_resp_data_2_entry_tailSlot_tarStat; + pred_rdata_hold_data_2_entry_tailSlot_sharing <= + _ftb_io_r_resp_data_2_entry_tailSlot_sharing; + pred_rdata_hold_data_2_entry_tailSlot_valid <= + _ftb_io_r_resp_data_2_entry_tailSlot_valid; + pred_rdata_hold_data_2_entry_pftAddr <= _ftb_io_r_resp_data_2_entry_pftAddr; + pred_rdata_hold_data_2_entry_carry <= _ftb_io_r_resp_data_2_entry_carry; + pred_rdata_hold_data_2_entry_isCall <= _ftb_io_r_resp_data_2_entry_isCall; + pred_rdata_hold_data_2_entry_isRet <= _ftb_io_r_resp_data_2_entry_isRet; + pred_rdata_hold_data_2_entry_isJalr <= _ftb_io_r_resp_data_2_entry_isJalr; + pred_rdata_hold_data_2_entry_last_may_be_rvi_call <= + _ftb_io_r_resp_data_2_entry_last_may_be_rvi_call; + pred_rdata_hold_data_2_entry_always_taken_0 <= + _ftb_io_r_resp_data_2_entry_always_taken_0; + pred_rdata_hold_data_2_entry_always_taken_1 <= + _ftb_io_r_resp_data_2_entry_always_taken_1; + pred_rdata_hold_data_2_tag <= _ftb_io_r_resp_data_2_tag; + pred_rdata_hold_data_3_entry_valid <= _ftb_io_r_resp_data_3_entry_valid; + pred_rdata_hold_data_3_entry_brSlots_0_offset <= + _ftb_io_r_resp_data_3_entry_brSlots_0_offset; + pred_rdata_hold_data_3_entry_brSlots_0_lower <= + _ftb_io_r_resp_data_3_entry_brSlots_0_lower; + pred_rdata_hold_data_3_entry_brSlots_0_tarStat <= + _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat; + pred_rdata_hold_data_3_entry_brSlots_0_sharing <= + _ftb_io_r_resp_data_3_entry_brSlots_0_sharing; + pred_rdata_hold_data_3_entry_brSlots_0_valid <= + _ftb_io_r_resp_data_3_entry_brSlots_0_valid; + pred_rdata_hold_data_3_entry_tailSlot_offset <= + _ftb_io_r_resp_data_3_entry_tailSlot_offset; + pred_rdata_hold_data_3_entry_tailSlot_lower <= + _ftb_io_r_resp_data_3_entry_tailSlot_lower; + pred_rdata_hold_data_3_entry_tailSlot_tarStat <= + _ftb_io_r_resp_data_3_entry_tailSlot_tarStat; + pred_rdata_hold_data_3_entry_tailSlot_sharing <= + _ftb_io_r_resp_data_3_entry_tailSlot_sharing; + pred_rdata_hold_data_3_entry_tailSlot_valid <= + _ftb_io_r_resp_data_3_entry_tailSlot_valid; + pred_rdata_hold_data_3_entry_pftAddr <= _ftb_io_r_resp_data_3_entry_pftAddr; + pred_rdata_hold_data_3_entry_carry <= _ftb_io_r_resp_data_3_entry_carry; + pred_rdata_hold_data_3_entry_isCall <= _ftb_io_r_resp_data_3_entry_isCall; + pred_rdata_hold_data_3_entry_isRet <= _ftb_io_r_resp_data_3_entry_isRet; + pred_rdata_hold_data_3_entry_isJalr <= _ftb_io_r_resp_data_3_entry_isJalr; + pred_rdata_hold_data_3_entry_last_may_be_rvi_call <= + _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call; + pred_rdata_hold_data_3_entry_always_taken_0 <= + _ftb_io_r_resp_data_3_entry_always_taken_0; + pred_rdata_hold_data_3_entry_always_taken_1 <= + _ftb_io_r_resp_data_3_entry_always_taken_1; + pred_rdata_hold_data_3_tag <= _ftb_io_r_resp_data_3_tag; + end + if (io_req_pc_valid) begin + req_tag <= io_req_pc_bits[29:10]; + req_idx <= io_req_pc_bits[9:1]; + end + if (io_u_req_pc_valid) + u_req_tag <= io_u_req_pc_bits[29:10]; + u_total_hits_REG <= io_update_access; + u_total_hits_REG_1 <= io_update_access; + u_total_hits_REG_2 <= io_update_access; + u_total_hits_REG_3 <= io_update_access; + touch_set_0_REG <= req_idx; + touch_way_0_valid_REG <= hit; + touch_way_0_bits_REG <= hit_way; + allocWriteWay_REG_0 <= _ftb_io_r_resp_data_0_entry_valid; + allocWriteWay_REG_1 <= _ftb_io_r_resp_data_1_entry_valid; + allocWriteWay_REG_2 <= _ftb_io_r_resp_data_2_entry_valid; + allocWriteWay_REG_3 <= _ftb_io_r_resp_data_3_entry_valid; + end // always @(posedge) + wire [8:0] touch_set_0 = + io_update_write_data_valid ? io_update_pc[9:1] : touch_set_0_REG; + wire touch_way_0_valid = + io_update_write_data_valid | touch_way_0_valid_REG; + wire [1:0] touch_way_0_bits = + io_update_write_data_valid ? u_way : touch_way_0_bits_REG; + always @(posedge clock or posedge reset) begin + if (reset) begin + state_vec_0 <= 3'h0; + state_vec_1 <= 3'h0; + state_vec_2 <= 3'h0; + state_vec_3 <= 3'h0; + state_vec_4 <= 3'h0; + state_vec_5 <= 3'h0; + state_vec_6 <= 3'h0; + state_vec_7 <= 3'h0; + state_vec_8 <= 3'h0; + state_vec_9 <= 3'h0; + state_vec_10 <= 3'h0; + state_vec_11 <= 3'h0; + state_vec_12 <= 3'h0; + state_vec_13 <= 3'h0; + state_vec_14 <= 3'h0; + state_vec_15 <= 3'h0; + state_vec_16 <= 3'h0; + state_vec_17 <= 3'h0; + state_vec_18 <= 3'h0; + state_vec_19 <= 3'h0; + state_vec_20 <= 3'h0; + state_vec_21 <= 3'h0; + state_vec_22 <= 3'h0; + state_vec_23 <= 3'h0; + state_vec_24 <= 3'h0; + state_vec_25 <= 3'h0; + state_vec_26 <= 3'h0; + state_vec_27 <= 3'h0; + state_vec_28 <= 3'h0; + state_vec_29 <= 3'h0; + state_vec_30 <= 3'h0; + state_vec_31 <= 3'h0; + state_vec_32 <= 3'h0; + state_vec_33 <= 3'h0; + state_vec_34 <= 3'h0; + state_vec_35 <= 3'h0; + state_vec_36 <= 3'h0; + state_vec_37 <= 3'h0; + state_vec_38 <= 3'h0; + state_vec_39 <= 3'h0; + state_vec_40 <= 3'h0; + state_vec_41 <= 3'h0; + state_vec_42 <= 3'h0; + state_vec_43 <= 3'h0; + state_vec_44 <= 3'h0; + state_vec_45 <= 3'h0; + state_vec_46 <= 3'h0; + state_vec_47 <= 3'h0; + state_vec_48 <= 3'h0; + state_vec_49 <= 3'h0; + state_vec_50 <= 3'h0; + state_vec_51 <= 3'h0; + state_vec_52 <= 3'h0; + state_vec_53 <= 3'h0; + state_vec_54 <= 3'h0; + state_vec_55 <= 3'h0; + state_vec_56 <= 3'h0; + state_vec_57 <= 3'h0; + state_vec_58 <= 3'h0; + state_vec_59 <= 3'h0; + state_vec_60 <= 3'h0; + state_vec_61 <= 3'h0; + state_vec_62 <= 3'h0; + state_vec_63 <= 3'h0; + state_vec_64 <= 3'h0; + state_vec_65 <= 3'h0; + state_vec_66 <= 3'h0; + state_vec_67 <= 3'h0; + state_vec_68 <= 3'h0; + state_vec_69 <= 3'h0; + state_vec_70 <= 3'h0; + state_vec_71 <= 3'h0; + state_vec_72 <= 3'h0; + state_vec_73 <= 3'h0; + state_vec_74 <= 3'h0; + state_vec_75 <= 3'h0; + state_vec_76 <= 3'h0; + state_vec_77 <= 3'h0; + state_vec_78 <= 3'h0; + state_vec_79 <= 3'h0; + state_vec_80 <= 3'h0; + state_vec_81 <= 3'h0; + state_vec_82 <= 3'h0; + state_vec_83 <= 3'h0; + state_vec_84 <= 3'h0; + state_vec_85 <= 3'h0; + state_vec_86 <= 3'h0; + state_vec_87 <= 3'h0; + state_vec_88 <= 3'h0; + state_vec_89 <= 3'h0; + state_vec_90 <= 3'h0; + state_vec_91 <= 3'h0; + state_vec_92 <= 3'h0; + state_vec_93 <= 3'h0; + state_vec_94 <= 3'h0; + state_vec_95 <= 3'h0; + state_vec_96 <= 3'h0; + state_vec_97 <= 3'h0; + state_vec_98 <= 3'h0; + state_vec_99 <= 3'h0; + state_vec_100 <= 3'h0; + state_vec_101 <= 3'h0; + state_vec_102 <= 3'h0; + state_vec_103 <= 3'h0; + state_vec_104 <= 3'h0; + state_vec_105 <= 3'h0; + state_vec_106 <= 3'h0; + state_vec_107 <= 3'h0; + state_vec_108 <= 3'h0; + state_vec_109 <= 3'h0; + state_vec_110 <= 3'h0; + state_vec_111 <= 3'h0; + state_vec_112 <= 3'h0; + state_vec_113 <= 3'h0; + state_vec_114 <= 3'h0; + state_vec_115 <= 3'h0; + state_vec_116 <= 3'h0; + state_vec_117 <= 3'h0; + state_vec_118 <= 3'h0; + state_vec_119 <= 3'h0; + state_vec_120 <= 3'h0; + state_vec_121 <= 3'h0; + state_vec_122 <= 3'h0; + state_vec_123 <= 3'h0; + state_vec_124 <= 3'h0; + state_vec_125 <= 3'h0; + state_vec_126 <= 3'h0; + state_vec_127 <= 3'h0; + state_vec_128 <= 3'h0; + state_vec_129 <= 3'h0; + state_vec_130 <= 3'h0; + state_vec_131 <= 3'h0; + state_vec_132 <= 3'h0; + state_vec_133 <= 3'h0; + state_vec_134 <= 3'h0; + state_vec_135 <= 3'h0; + state_vec_136 <= 3'h0; + state_vec_137 <= 3'h0; + state_vec_138 <= 3'h0; + state_vec_139 <= 3'h0; + state_vec_140 <= 3'h0; + state_vec_141 <= 3'h0; + state_vec_142 <= 3'h0; + state_vec_143 <= 3'h0; + state_vec_144 <= 3'h0; + state_vec_145 <= 3'h0; + state_vec_146 <= 3'h0; + state_vec_147 <= 3'h0; + state_vec_148 <= 3'h0; + state_vec_149 <= 3'h0; + state_vec_150 <= 3'h0; + state_vec_151 <= 3'h0; + state_vec_152 <= 3'h0; + state_vec_153 <= 3'h0; + state_vec_154 <= 3'h0; + state_vec_155 <= 3'h0; + state_vec_156 <= 3'h0; + state_vec_157 <= 3'h0; + state_vec_158 <= 3'h0; + state_vec_159 <= 3'h0; + state_vec_160 <= 3'h0; + state_vec_161 <= 3'h0; + state_vec_162 <= 3'h0; + state_vec_163 <= 3'h0; + state_vec_164 <= 3'h0; + state_vec_165 <= 3'h0; + state_vec_166 <= 3'h0; + state_vec_167 <= 3'h0; + state_vec_168 <= 3'h0; + state_vec_169 <= 3'h0; + state_vec_170 <= 3'h0; + state_vec_171 <= 3'h0; + state_vec_172 <= 3'h0; + state_vec_173 <= 3'h0; + state_vec_174 <= 3'h0; + state_vec_175 <= 3'h0; + state_vec_176 <= 3'h0; + state_vec_177 <= 3'h0; + state_vec_178 <= 3'h0; + state_vec_179 <= 3'h0; + state_vec_180 <= 3'h0; + state_vec_181 <= 3'h0; + state_vec_182 <= 3'h0; + state_vec_183 <= 3'h0; + state_vec_184 <= 3'h0; + state_vec_185 <= 3'h0; + state_vec_186 <= 3'h0; + state_vec_187 <= 3'h0; + state_vec_188 <= 3'h0; + state_vec_189 <= 3'h0; + state_vec_190 <= 3'h0; + state_vec_191 <= 3'h0; + state_vec_192 <= 3'h0; + state_vec_193 <= 3'h0; + state_vec_194 <= 3'h0; + state_vec_195 <= 3'h0; + state_vec_196 <= 3'h0; + state_vec_197 <= 3'h0; + state_vec_198 <= 3'h0; + state_vec_199 <= 3'h0; + state_vec_200 <= 3'h0; + state_vec_201 <= 3'h0; + state_vec_202 <= 3'h0; + state_vec_203 <= 3'h0; + state_vec_204 <= 3'h0; + state_vec_205 <= 3'h0; + state_vec_206 <= 3'h0; + state_vec_207 <= 3'h0; + state_vec_208 <= 3'h0; + state_vec_209 <= 3'h0; + state_vec_210 <= 3'h0; + state_vec_211 <= 3'h0; + state_vec_212 <= 3'h0; + state_vec_213 <= 3'h0; + state_vec_214 <= 3'h0; + state_vec_215 <= 3'h0; + state_vec_216 <= 3'h0; + state_vec_217 <= 3'h0; + state_vec_218 <= 3'h0; + state_vec_219 <= 3'h0; + state_vec_220 <= 3'h0; + state_vec_221 <= 3'h0; + state_vec_222 <= 3'h0; + state_vec_223 <= 3'h0; + state_vec_224 <= 3'h0; + state_vec_225 <= 3'h0; + state_vec_226 <= 3'h0; + state_vec_227 <= 3'h0; + state_vec_228 <= 3'h0; + state_vec_229 <= 3'h0; + state_vec_230 <= 3'h0; + state_vec_231 <= 3'h0; + state_vec_232 <= 3'h0; + state_vec_233 <= 3'h0; + state_vec_234 <= 3'h0; + state_vec_235 <= 3'h0; + state_vec_236 <= 3'h0; + state_vec_237 <= 3'h0; + state_vec_238 <= 3'h0; + state_vec_239 <= 3'h0; + state_vec_240 <= 3'h0; + state_vec_241 <= 3'h0; + state_vec_242 <= 3'h0; + state_vec_243 <= 3'h0; + state_vec_244 <= 3'h0; + state_vec_245 <= 3'h0; + state_vec_246 <= 3'h0; + state_vec_247 <= 3'h0; + state_vec_248 <= 3'h0; + state_vec_249 <= 3'h0; + state_vec_250 <= 3'h0; + state_vec_251 <= 3'h0; + state_vec_252 <= 3'h0; + state_vec_253 <= 3'h0; + state_vec_254 <= 3'h0; + state_vec_255 <= 3'h0; + state_vec_256 <= 3'h0; + state_vec_257 <= 3'h0; + state_vec_258 <= 3'h0; + state_vec_259 <= 3'h0; + state_vec_260 <= 3'h0; + state_vec_261 <= 3'h0; + state_vec_262 <= 3'h0; + state_vec_263 <= 3'h0; + state_vec_264 <= 3'h0; + state_vec_265 <= 3'h0; + state_vec_266 <= 3'h0; + state_vec_267 <= 3'h0; + state_vec_268 <= 3'h0; + state_vec_269 <= 3'h0; + state_vec_270 <= 3'h0; + state_vec_271 <= 3'h0; + state_vec_272 <= 3'h0; + state_vec_273 <= 3'h0; + state_vec_274 <= 3'h0; + state_vec_275 <= 3'h0; + state_vec_276 <= 3'h0; + state_vec_277 <= 3'h0; + state_vec_278 <= 3'h0; + state_vec_279 <= 3'h0; + state_vec_280 <= 3'h0; + state_vec_281 <= 3'h0; + state_vec_282 <= 3'h0; + state_vec_283 <= 3'h0; + state_vec_284 <= 3'h0; + state_vec_285 <= 3'h0; + state_vec_286 <= 3'h0; + state_vec_287 <= 3'h0; + state_vec_288 <= 3'h0; + state_vec_289 <= 3'h0; + state_vec_290 <= 3'h0; + state_vec_291 <= 3'h0; + state_vec_292 <= 3'h0; + state_vec_293 <= 3'h0; + state_vec_294 <= 3'h0; + state_vec_295 <= 3'h0; + state_vec_296 <= 3'h0; + state_vec_297 <= 3'h0; + state_vec_298 <= 3'h0; + state_vec_299 <= 3'h0; + state_vec_300 <= 3'h0; + state_vec_301 <= 3'h0; + state_vec_302 <= 3'h0; + state_vec_303 <= 3'h0; + state_vec_304 <= 3'h0; + state_vec_305 <= 3'h0; + state_vec_306 <= 3'h0; + state_vec_307 <= 3'h0; + state_vec_308 <= 3'h0; + state_vec_309 <= 3'h0; + state_vec_310 <= 3'h0; + state_vec_311 <= 3'h0; + state_vec_312 <= 3'h0; + state_vec_313 <= 3'h0; + state_vec_314 <= 3'h0; + state_vec_315 <= 3'h0; + state_vec_316 <= 3'h0; + state_vec_317 <= 3'h0; + state_vec_318 <= 3'h0; + state_vec_319 <= 3'h0; + state_vec_320 <= 3'h0; + state_vec_321 <= 3'h0; + state_vec_322 <= 3'h0; + state_vec_323 <= 3'h0; + state_vec_324 <= 3'h0; + state_vec_325 <= 3'h0; + state_vec_326 <= 3'h0; + state_vec_327 <= 3'h0; + state_vec_328 <= 3'h0; + state_vec_329 <= 3'h0; + state_vec_330 <= 3'h0; + state_vec_331 <= 3'h0; + state_vec_332 <= 3'h0; + state_vec_333 <= 3'h0; + state_vec_334 <= 3'h0; + state_vec_335 <= 3'h0; + state_vec_336 <= 3'h0; + state_vec_337 <= 3'h0; + state_vec_338 <= 3'h0; + state_vec_339 <= 3'h0; + state_vec_340 <= 3'h0; + state_vec_341 <= 3'h0; + state_vec_342 <= 3'h0; + state_vec_343 <= 3'h0; + state_vec_344 <= 3'h0; + state_vec_345 <= 3'h0; + state_vec_346 <= 3'h0; + state_vec_347 <= 3'h0; + state_vec_348 <= 3'h0; + state_vec_349 <= 3'h0; + state_vec_350 <= 3'h0; + state_vec_351 <= 3'h0; + state_vec_352 <= 3'h0; + state_vec_353 <= 3'h0; + state_vec_354 <= 3'h0; + state_vec_355 <= 3'h0; + state_vec_356 <= 3'h0; + state_vec_357 <= 3'h0; + state_vec_358 <= 3'h0; + state_vec_359 <= 3'h0; + state_vec_360 <= 3'h0; + state_vec_361 <= 3'h0; + state_vec_362 <= 3'h0; + state_vec_363 <= 3'h0; + state_vec_364 <= 3'h0; + state_vec_365 <= 3'h0; + state_vec_366 <= 3'h0; + state_vec_367 <= 3'h0; + state_vec_368 <= 3'h0; + state_vec_369 <= 3'h0; + state_vec_370 <= 3'h0; + state_vec_371 <= 3'h0; + state_vec_372 <= 3'h0; + state_vec_373 <= 3'h0; + state_vec_374 <= 3'h0; + state_vec_375 <= 3'h0; + state_vec_376 <= 3'h0; + state_vec_377 <= 3'h0; + state_vec_378 <= 3'h0; + state_vec_379 <= 3'h0; + state_vec_380 <= 3'h0; + state_vec_381 <= 3'h0; + state_vec_382 <= 3'h0; + state_vec_383 <= 3'h0; + state_vec_384 <= 3'h0; + state_vec_385 <= 3'h0; + state_vec_386 <= 3'h0; + state_vec_387 <= 3'h0; + state_vec_388 <= 3'h0; + state_vec_389 <= 3'h0; + state_vec_390 <= 3'h0; + state_vec_391 <= 3'h0; + state_vec_392 <= 3'h0; + state_vec_393 <= 3'h0; + state_vec_394 <= 3'h0; + state_vec_395 <= 3'h0; + state_vec_396 <= 3'h0; + state_vec_397 <= 3'h0; + state_vec_398 <= 3'h0; + state_vec_399 <= 3'h0; + state_vec_400 <= 3'h0; + state_vec_401 <= 3'h0; + state_vec_402 <= 3'h0; + state_vec_403 <= 3'h0; + state_vec_404 <= 3'h0; + state_vec_405 <= 3'h0; + state_vec_406 <= 3'h0; + state_vec_407 <= 3'h0; + state_vec_408 <= 3'h0; + state_vec_409 <= 3'h0; + state_vec_410 <= 3'h0; + state_vec_411 <= 3'h0; + state_vec_412 <= 3'h0; + state_vec_413 <= 3'h0; + state_vec_414 <= 3'h0; + state_vec_415 <= 3'h0; + state_vec_416 <= 3'h0; + state_vec_417 <= 3'h0; + state_vec_418 <= 3'h0; + state_vec_419 <= 3'h0; + state_vec_420 <= 3'h0; + state_vec_421 <= 3'h0; + state_vec_422 <= 3'h0; + state_vec_423 <= 3'h0; + state_vec_424 <= 3'h0; + state_vec_425 <= 3'h0; + state_vec_426 <= 3'h0; + state_vec_427 <= 3'h0; + state_vec_428 <= 3'h0; + state_vec_429 <= 3'h0; + state_vec_430 <= 3'h0; + state_vec_431 <= 3'h0; + state_vec_432 <= 3'h0; + state_vec_433 <= 3'h0; + state_vec_434 <= 3'h0; + state_vec_435 <= 3'h0; + state_vec_436 <= 3'h0; + state_vec_437 <= 3'h0; + state_vec_438 <= 3'h0; + state_vec_439 <= 3'h0; + state_vec_440 <= 3'h0; + state_vec_441 <= 3'h0; + state_vec_442 <= 3'h0; + state_vec_443 <= 3'h0; + state_vec_444 <= 3'h0; + state_vec_445 <= 3'h0; + state_vec_446 <= 3'h0; + state_vec_447 <= 3'h0; + state_vec_448 <= 3'h0; + state_vec_449 <= 3'h0; + state_vec_450 <= 3'h0; + state_vec_451 <= 3'h0; + state_vec_452 <= 3'h0; + state_vec_453 <= 3'h0; + state_vec_454 <= 3'h0; + state_vec_455 <= 3'h0; + state_vec_456 <= 3'h0; + state_vec_457 <= 3'h0; + state_vec_458 <= 3'h0; + state_vec_459 <= 3'h0; + state_vec_460 <= 3'h0; + state_vec_461 <= 3'h0; + state_vec_462 <= 3'h0; + state_vec_463 <= 3'h0; + state_vec_464 <= 3'h0; + state_vec_465 <= 3'h0; + state_vec_466 <= 3'h0; + state_vec_467 <= 3'h0; + state_vec_468 <= 3'h0; + state_vec_469 <= 3'h0; + state_vec_470 <= 3'h0; + state_vec_471 <= 3'h0; + state_vec_472 <= 3'h0; + state_vec_473 <= 3'h0; + state_vec_474 <= 3'h0; + state_vec_475 <= 3'h0; + state_vec_476 <= 3'h0; + state_vec_477 <= 3'h0; + state_vec_478 <= 3'h0; + state_vec_479 <= 3'h0; + state_vec_480 <= 3'h0; + state_vec_481 <= 3'h0; + state_vec_482 <= 3'h0; + state_vec_483 <= 3'h0; + state_vec_484 <= 3'h0; + state_vec_485 <= 3'h0; + state_vec_486 <= 3'h0; + state_vec_487 <= 3'h0; + state_vec_488 <= 3'h0; + state_vec_489 <= 3'h0; + state_vec_490 <= 3'h0; + state_vec_491 <= 3'h0; + state_vec_492 <= 3'h0; + state_vec_493 <= 3'h0; + state_vec_494 <= 3'h0; + state_vec_495 <= 3'h0; + state_vec_496 <= 3'h0; + state_vec_497 <= 3'h0; + state_vec_498 <= 3'h0; + state_vec_499 <= 3'h0; + state_vec_500 <= 3'h0; + state_vec_501 <= 3'h0; + state_vec_502 <= 3'h0; + state_vec_503 <= 3'h0; + state_vec_504 <= 3'h0; + state_vec_505 <= 3'h0; + state_vec_506 <= 3'h0; + state_vec_507 <= 3'h0; + state_vec_508 <= 3'h0; + state_vec_509 <= 3'h0; + state_vec_510 <= 3'h0; + state_vec_511 <= 3'h0; + end + else begin + if (touch_way_0_valid & touch_set_0 == 9'h0) + state_vec_0 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_0[1], + touch_way_0_bits[1] ? state_vec_0[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1) + state_vec_1 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_1[1], + touch_way_0_bits[1] ? state_vec_1[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h2) + state_vec_2 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_2[1], + touch_way_0_bits[1] ? state_vec_2[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h3) + state_vec_3 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_3[1], + touch_way_0_bits[1] ? state_vec_3[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h4) + state_vec_4 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_4[1], + touch_way_0_bits[1] ? state_vec_4[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h5) + state_vec_5 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_5[1], + touch_way_0_bits[1] ? state_vec_5[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h6) + state_vec_6 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_6[1], + touch_way_0_bits[1] ? state_vec_6[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h7) + state_vec_7 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_7[1], + touch_way_0_bits[1] ? state_vec_7[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h8) + state_vec_8 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_8[1], + touch_way_0_bits[1] ? state_vec_8[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h9) + state_vec_9 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_9[1], + touch_way_0_bits[1] ? state_vec_9[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hA) + state_vec_10 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_10[1], + touch_way_0_bits[1] ? state_vec_10[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hB) + state_vec_11 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_11[1], + touch_way_0_bits[1] ? state_vec_11[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hC) + state_vec_12 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_12[1], + touch_way_0_bits[1] ? state_vec_12[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hD) + state_vec_13 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_13[1], + touch_way_0_bits[1] ? state_vec_13[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hE) + state_vec_14 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_14[1], + touch_way_0_bits[1] ? state_vec_14[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hF) + state_vec_15 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_15[1], + touch_way_0_bits[1] ? state_vec_15[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h10) + state_vec_16 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_16[1], + touch_way_0_bits[1] ? state_vec_16[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h11) + state_vec_17 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_17[1], + touch_way_0_bits[1] ? state_vec_17[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h12) + state_vec_18 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_18[1], + touch_way_0_bits[1] ? state_vec_18[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h13) + state_vec_19 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_19[1], + touch_way_0_bits[1] ? state_vec_19[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h14) + state_vec_20 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_20[1], + touch_way_0_bits[1] ? state_vec_20[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h15) + state_vec_21 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_21[1], + touch_way_0_bits[1] ? state_vec_21[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h16) + state_vec_22 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_22[1], + touch_way_0_bits[1] ? state_vec_22[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h17) + state_vec_23 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_23[1], + touch_way_0_bits[1] ? state_vec_23[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h18) + state_vec_24 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_24[1], + touch_way_0_bits[1] ? state_vec_24[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h19) + state_vec_25 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_25[1], + touch_way_0_bits[1] ? state_vec_25[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1A) + state_vec_26 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_26[1], + touch_way_0_bits[1] ? state_vec_26[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1B) + state_vec_27 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_27[1], + touch_way_0_bits[1] ? state_vec_27[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1C) + state_vec_28 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_28[1], + touch_way_0_bits[1] ? state_vec_28[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1D) + state_vec_29 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_29[1], + touch_way_0_bits[1] ? state_vec_29[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1E) + state_vec_30 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_30[1], + touch_way_0_bits[1] ? state_vec_30[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1F) + state_vec_31 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_31[1], + touch_way_0_bits[1] ? state_vec_31[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h20) + state_vec_32 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_32[1], + touch_way_0_bits[1] ? state_vec_32[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h21) + state_vec_33 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_33[1], + touch_way_0_bits[1] ? state_vec_33[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h22) + state_vec_34 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_34[1], + touch_way_0_bits[1] ? state_vec_34[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h23) + state_vec_35 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_35[1], + touch_way_0_bits[1] ? state_vec_35[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h24) + state_vec_36 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_36[1], + touch_way_0_bits[1] ? state_vec_36[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h25) + state_vec_37 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_37[1], + touch_way_0_bits[1] ? state_vec_37[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h26) + state_vec_38 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_38[1], + touch_way_0_bits[1] ? state_vec_38[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h27) + state_vec_39 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_39[1], + touch_way_0_bits[1] ? state_vec_39[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h28) + state_vec_40 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_40[1], + touch_way_0_bits[1] ? state_vec_40[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h29) + state_vec_41 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_41[1], + touch_way_0_bits[1] ? state_vec_41[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h2A) + state_vec_42 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_42[1], + touch_way_0_bits[1] ? state_vec_42[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h2B) + state_vec_43 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_43[1], + touch_way_0_bits[1] ? state_vec_43[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h2C) + state_vec_44 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_44[1], + touch_way_0_bits[1] ? state_vec_44[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h2D) + state_vec_45 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_45[1], + touch_way_0_bits[1] ? state_vec_45[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h2E) + state_vec_46 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_46[1], + touch_way_0_bits[1] ? state_vec_46[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h2F) + state_vec_47 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_47[1], + touch_way_0_bits[1] ? state_vec_47[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h30) + state_vec_48 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_48[1], + touch_way_0_bits[1] ? state_vec_48[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h31) + state_vec_49 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_49[1], + touch_way_0_bits[1] ? state_vec_49[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h32) + state_vec_50 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_50[1], + touch_way_0_bits[1] ? state_vec_50[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h33) + state_vec_51 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_51[1], + touch_way_0_bits[1] ? state_vec_51[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h34) + state_vec_52 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_52[1], + touch_way_0_bits[1] ? state_vec_52[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h35) + state_vec_53 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_53[1], + touch_way_0_bits[1] ? state_vec_53[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h36) + state_vec_54 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_54[1], + touch_way_0_bits[1] ? state_vec_54[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h37) + state_vec_55 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_55[1], + touch_way_0_bits[1] ? state_vec_55[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h38) + state_vec_56 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_56[1], + touch_way_0_bits[1] ? state_vec_56[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h39) + state_vec_57 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_57[1], + touch_way_0_bits[1] ? state_vec_57[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h3A) + state_vec_58 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_58[1], + touch_way_0_bits[1] ? state_vec_58[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h3B) + state_vec_59 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_59[1], + touch_way_0_bits[1] ? state_vec_59[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h3C) + state_vec_60 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_60[1], + touch_way_0_bits[1] ? state_vec_60[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h3D) + state_vec_61 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_61[1], + touch_way_0_bits[1] ? state_vec_61[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h3E) + state_vec_62 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_62[1], + touch_way_0_bits[1] ? state_vec_62[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h3F) + state_vec_63 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_63[1], + touch_way_0_bits[1] ? state_vec_63[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h40) + state_vec_64 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_64[1], + touch_way_0_bits[1] ? state_vec_64[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h41) + state_vec_65 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_65[1], + touch_way_0_bits[1] ? state_vec_65[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h42) + state_vec_66 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_66[1], + touch_way_0_bits[1] ? state_vec_66[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h43) + state_vec_67 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_67[1], + touch_way_0_bits[1] ? state_vec_67[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h44) + state_vec_68 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_68[1], + touch_way_0_bits[1] ? state_vec_68[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h45) + state_vec_69 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_69[1], + touch_way_0_bits[1] ? state_vec_69[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h46) + state_vec_70 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_70[1], + touch_way_0_bits[1] ? state_vec_70[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h47) + state_vec_71 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_71[1], + touch_way_0_bits[1] ? state_vec_71[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h48) + state_vec_72 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_72[1], + touch_way_0_bits[1] ? state_vec_72[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h49) + state_vec_73 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_73[1], + touch_way_0_bits[1] ? state_vec_73[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h4A) + state_vec_74 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_74[1], + touch_way_0_bits[1] ? state_vec_74[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h4B) + state_vec_75 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_75[1], + touch_way_0_bits[1] ? state_vec_75[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h4C) + state_vec_76 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_76[1], + touch_way_0_bits[1] ? state_vec_76[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h4D) + state_vec_77 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_77[1], + touch_way_0_bits[1] ? state_vec_77[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h4E) + state_vec_78 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_78[1], + touch_way_0_bits[1] ? state_vec_78[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h4F) + state_vec_79 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_79[1], + touch_way_0_bits[1] ? state_vec_79[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h50) + state_vec_80 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_80[1], + touch_way_0_bits[1] ? state_vec_80[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h51) + state_vec_81 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_81[1], + touch_way_0_bits[1] ? state_vec_81[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h52) + state_vec_82 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_82[1], + touch_way_0_bits[1] ? state_vec_82[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h53) + state_vec_83 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_83[1], + touch_way_0_bits[1] ? state_vec_83[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h54) + state_vec_84 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_84[1], + touch_way_0_bits[1] ? state_vec_84[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h55) + state_vec_85 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_85[1], + touch_way_0_bits[1] ? state_vec_85[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h56) + state_vec_86 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_86[1], + touch_way_0_bits[1] ? state_vec_86[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h57) + state_vec_87 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_87[1], + touch_way_0_bits[1] ? state_vec_87[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h58) + state_vec_88 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_88[1], + touch_way_0_bits[1] ? state_vec_88[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h59) + state_vec_89 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_89[1], + touch_way_0_bits[1] ? state_vec_89[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h5A) + state_vec_90 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_90[1], + touch_way_0_bits[1] ? state_vec_90[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h5B) + state_vec_91 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_91[1], + touch_way_0_bits[1] ? state_vec_91[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h5C) + state_vec_92 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_92[1], + touch_way_0_bits[1] ? state_vec_92[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h5D) + state_vec_93 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_93[1], + touch_way_0_bits[1] ? state_vec_93[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h5E) + state_vec_94 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_94[1], + touch_way_0_bits[1] ? state_vec_94[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h5F) + state_vec_95 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_95[1], + touch_way_0_bits[1] ? state_vec_95[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h60) + state_vec_96 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_96[1], + touch_way_0_bits[1] ? state_vec_96[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h61) + state_vec_97 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_97[1], + touch_way_0_bits[1] ? state_vec_97[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h62) + state_vec_98 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_98[1], + touch_way_0_bits[1] ? state_vec_98[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h63) + state_vec_99 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_99[1], + touch_way_0_bits[1] ? state_vec_99[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h64) + state_vec_100 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_100[1], + touch_way_0_bits[1] ? state_vec_100[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h65) + state_vec_101 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_101[1], + touch_way_0_bits[1] ? state_vec_101[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h66) + state_vec_102 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_102[1], + touch_way_0_bits[1] ? state_vec_102[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h67) + state_vec_103 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_103[1], + touch_way_0_bits[1] ? state_vec_103[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h68) + state_vec_104 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_104[1], + touch_way_0_bits[1] ? state_vec_104[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h69) + state_vec_105 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_105[1], + touch_way_0_bits[1] ? state_vec_105[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h6A) + state_vec_106 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_106[1], + touch_way_0_bits[1] ? state_vec_106[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h6B) + state_vec_107 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_107[1], + touch_way_0_bits[1] ? state_vec_107[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h6C) + state_vec_108 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_108[1], + touch_way_0_bits[1] ? state_vec_108[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h6D) + state_vec_109 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_109[1], + touch_way_0_bits[1] ? state_vec_109[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h6E) + state_vec_110 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_110[1], + touch_way_0_bits[1] ? state_vec_110[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h6F) + state_vec_111 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_111[1], + touch_way_0_bits[1] ? state_vec_111[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h70) + state_vec_112 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_112[1], + touch_way_0_bits[1] ? state_vec_112[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h71) + state_vec_113 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_113[1], + touch_way_0_bits[1] ? state_vec_113[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h72) + state_vec_114 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_114[1], + touch_way_0_bits[1] ? state_vec_114[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h73) + state_vec_115 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_115[1], + touch_way_0_bits[1] ? state_vec_115[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h74) + state_vec_116 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_116[1], + touch_way_0_bits[1] ? state_vec_116[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h75) + state_vec_117 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_117[1], + touch_way_0_bits[1] ? state_vec_117[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h76) + state_vec_118 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_118[1], + touch_way_0_bits[1] ? state_vec_118[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h77) + state_vec_119 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_119[1], + touch_way_0_bits[1] ? state_vec_119[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h78) + state_vec_120 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_120[1], + touch_way_0_bits[1] ? state_vec_120[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h79) + state_vec_121 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_121[1], + touch_way_0_bits[1] ? state_vec_121[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h7A) + state_vec_122 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_122[1], + touch_way_0_bits[1] ? state_vec_122[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h7B) + state_vec_123 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_123[1], + touch_way_0_bits[1] ? state_vec_123[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h7C) + state_vec_124 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_124[1], + touch_way_0_bits[1] ? state_vec_124[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h7D) + state_vec_125 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_125[1], + touch_way_0_bits[1] ? state_vec_125[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h7E) + state_vec_126 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_126[1], + touch_way_0_bits[1] ? state_vec_126[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h7F) + state_vec_127 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_127[1], + touch_way_0_bits[1] ? state_vec_127[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h80) + state_vec_128 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_128[1], + touch_way_0_bits[1] ? state_vec_128[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h81) + state_vec_129 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_129[1], + touch_way_0_bits[1] ? state_vec_129[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h82) + state_vec_130 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_130[1], + touch_way_0_bits[1] ? state_vec_130[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h83) + state_vec_131 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_131[1], + touch_way_0_bits[1] ? state_vec_131[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h84) + state_vec_132 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_132[1], + touch_way_0_bits[1] ? state_vec_132[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h85) + state_vec_133 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_133[1], + touch_way_0_bits[1] ? state_vec_133[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h86) + state_vec_134 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_134[1], + touch_way_0_bits[1] ? state_vec_134[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h87) + state_vec_135 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_135[1], + touch_way_0_bits[1] ? state_vec_135[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h88) + state_vec_136 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_136[1], + touch_way_0_bits[1] ? state_vec_136[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h89) + state_vec_137 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_137[1], + touch_way_0_bits[1] ? state_vec_137[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h8A) + state_vec_138 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_138[1], + touch_way_0_bits[1] ? state_vec_138[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h8B) + state_vec_139 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_139[1], + touch_way_0_bits[1] ? state_vec_139[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h8C) + state_vec_140 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_140[1], + touch_way_0_bits[1] ? state_vec_140[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h8D) + state_vec_141 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_141[1], + touch_way_0_bits[1] ? state_vec_141[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h8E) + state_vec_142 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_142[1], + touch_way_0_bits[1] ? state_vec_142[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h8F) + state_vec_143 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_143[1], + touch_way_0_bits[1] ? state_vec_143[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h90) + state_vec_144 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_144[1], + touch_way_0_bits[1] ? state_vec_144[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h91) + state_vec_145 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_145[1], + touch_way_0_bits[1] ? state_vec_145[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h92) + state_vec_146 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_146[1], + touch_way_0_bits[1] ? state_vec_146[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h93) + state_vec_147 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_147[1], + touch_way_0_bits[1] ? state_vec_147[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h94) + state_vec_148 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_148[1], + touch_way_0_bits[1] ? state_vec_148[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h95) + state_vec_149 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_149[1], + touch_way_0_bits[1] ? state_vec_149[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h96) + state_vec_150 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_150[1], + touch_way_0_bits[1] ? state_vec_150[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h97) + state_vec_151 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_151[1], + touch_way_0_bits[1] ? state_vec_151[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h98) + state_vec_152 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_152[1], + touch_way_0_bits[1] ? state_vec_152[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h99) + state_vec_153 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_153[1], + touch_way_0_bits[1] ? state_vec_153[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h9A) + state_vec_154 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_154[1], + touch_way_0_bits[1] ? state_vec_154[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h9B) + state_vec_155 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_155[1], + touch_way_0_bits[1] ? state_vec_155[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h9C) + state_vec_156 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_156[1], + touch_way_0_bits[1] ? state_vec_156[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h9D) + state_vec_157 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_157[1], + touch_way_0_bits[1] ? state_vec_157[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h9E) + state_vec_158 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_158[1], + touch_way_0_bits[1] ? state_vec_158[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h9F) + state_vec_159 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_159[1], + touch_way_0_bits[1] ? state_vec_159[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hA0) + state_vec_160 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_160[1], + touch_way_0_bits[1] ? state_vec_160[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hA1) + state_vec_161 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_161[1], + touch_way_0_bits[1] ? state_vec_161[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hA2) + state_vec_162 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_162[1], + touch_way_0_bits[1] ? state_vec_162[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hA3) + state_vec_163 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_163[1], + touch_way_0_bits[1] ? state_vec_163[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hA4) + state_vec_164 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_164[1], + touch_way_0_bits[1] ? state_vec_164[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hA5) + state_vec_165 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_165[1], + touch_way_0_bits[1] ? state_vec_165[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hA6) + state_vec_166 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_166[1], + touch_way_0_bits[1] ? state_vec_166[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hA7) + state_vec_167 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_167[1], + touch_way_0_bits[1] ? state_vec_167[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hA8) + state_vec_168 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_168[1], + touch_way_0_bits[1] ? state_vec_168[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hA9) + state_vec_169 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_169[1], + touch_way_0_bits[1] ? state_vec_169[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hAA) + state_vec_170 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_170[1], + touch_way_0_bits[1] ? state_vec_170[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hAB) + state_vec_171 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_171[1], + touch_way_0_bits[1] ? state_vec_171[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hAC) + state_vec_172 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_172[1], + touch_way_0_bits[1] ? state_vec_172[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hAD) + state_vec_173 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_173[1], + touch_way_0_bits[1] ? state_vec_173[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hAE) + state_vec_174 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_174[1], + touch_way_0_bits[1] ? state_vec_174[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hAF) + state_vec_175 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_175[1], + touch_way_0_bits[1] ? state_vec_175[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hB0) + state_vec_176 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_176[1], + touch_way_0_bits[1] ? state_vec_176[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hB1) + state_vec_177 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_177[1], + touch_way_0_bits[1] ? state_vec_177[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hB2) + state_vec_178 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_178[1], + touch_way_0_bits[1] ? state_vec_178[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hB3) + state_vec_179 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_179[1], + touch_way_0_bits[1] ? state_vec_179[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hB4) + state_vec_180 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_180[1], + touch_way_0_bits[1] ? state_vec_180[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hB5) + state_vec_181 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_181[1], + touch_way_0_bits[1] ? state_vec_181[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hB6) + state_vec_182 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_182[1], + touch_way_0_bits[1] ? state_vec_182[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hB7) + state_vec_183 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_183[1], + touch_way_0_bits[1] ? state_vec_183[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hB8) + state_vec_184 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_184[1], + touch_way_0_bits[1] ? state_vec_184[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hB9) + state_vec_185 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_185[1], + touch_way_0_bits[1] ? state_vec_185[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hBA) + state_vec_186 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_186[1], + touch_way_0_bits[1] ? state_vec_186[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hBB) + state_vec_187 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_187[1], + touch_way_0_bits[1] ? state_vec_187[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hBC) + state_vec_188 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_188[1], + touch_way_0_bits[1] ? state_vec_188[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hBD) + state_vec_189 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_189[1], + touch_way_0_bits[1] ? state_vec_189[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hBE) + state_vec_190 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_190[1], + touch_way_0_bits[1] ? state_vec_190[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hBF) + state_vec_191 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_191[1], + touch_way_0_bits[1] ? state_vec_191[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hC0) + state_vec_192 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_192[1], + touch_way_0_bits[1] ? state_vec_192[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hC1) + state_vec_193 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_193[1], + touch_way_0_bits[1] ? state_vec_193[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hC2) + state_vec_194 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_194[1], + touch_way_0_bits[1] ? state_vec_194[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hC3) + state_vec_195 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_195[1], + touch_way_0_bits[1] ? state_vec_195[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hC4) + state_vec_196 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_196[1], + touch_way_0_bits[1] ? state_vec_196[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hC5) + state_vec_197 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_197[1], + touch_way_0_bits[1] ? state_vec_197[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hC6) + state_vec_198 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_198[1], + touch_way_0_bits[1] ? state_vec_198[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hC7) + state_vec_199 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_199[1], + touch_way_0_bits[1] ? state_vec_199[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hC8) + state_vec_200 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_200[1], + touch_way_0_bits[1] ? state_vec_200[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hC9) + state_vec_201 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_201[1], + touch_way_0_bits[1] ? state_vec_201[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hCA) + state_vec_202 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_202[1], + touch_way_0_bits[1] ? state_vec_202[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hCB) + state_vec_203 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_203[1], + touch_way_0_bits[1] ? state_vec_203[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hCC) + state_vec_204 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_204[1], + touch_way_0_bits[1] ? state_vec_204[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hCD) + state_vec_205 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_205[1], + touch_way_0_bits[1] ? state_vec_205[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hCE) + state_vec_206 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_206[1], + touch_way_0_bits[1] ? state_vec_206[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hCF) + state_vec_207 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_207[1], + touch_way_0_bits[1] ? state_vec_207[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hD0) + state_vec_208 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_208[1], + touch_way_0_bits[1] ? state_vec_208[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hD1) + state_vec_209 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_209[1], + touch_way_0_bits[1] ? state_vec_209[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hD2) + state_vec_210 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_210[1], + touch_way_0_bits[1] ? state_vec_210[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hD3) + state_vec_211 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_211[1], + touch_way_0_bits[1] ? state_vec_211[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hD4) + state_vec_212 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_212[1], + touch_way_0_bits[1] ? state_vec_212[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hD5) + state_vec_213 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_213[1], + touch_way_0_bits[1] ? state_vec_213[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hD6) + state_vec_214 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_214[1], + touch_way_0_bits[1] ? state_vec_214[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hD7) + state_vec_215 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_215[1], + touch_way_0_bits[1] ? state_vec_215[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hD8) + state_vec_216 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_216[1], + touch_way_0_bits[1] ? state_vec_216[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hD9) + state_vec_217 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_217[1], + touch_way_0_bits[1] ? state_vec_217[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hDA) + state_vec_218 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_218[1], + touch_way_0_bits[1] ? state_vec_218[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hDB) + state_vec_219 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_219[1], + touch_way_0_bits[1] ? state_vec_219[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hDC) + state_vec_220 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_220[1], + touch_way_0_bits[1] ? state_vec_220[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hDD) + state_vec_221 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_221[1], + touch_way_0_bits[1] ? state_vec_221[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hDE) + state_vec_222 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_222[1], + touch_way_0_bits[1] ? state_vec_222[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hDF) + state_vec_223 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_223[1], + touch_way_0_bits[1] ? state_vec_223[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hE0) + state_vec_224 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_224[1], + touch_way_0_bits[1] ? state_vec_224[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hE1) + state_vec_225 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_225[1], + touch_way_0_bits[1] ? state_vec_225[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hE2) + state_vec_226 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_226[1], + touch_way_0_bits[1] ? state_vec_226[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hE3) + state_vec_227 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_227[1], + touch_way_0_bits[1] ? state_vec_227[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hE4) + state_vec_228 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_228[1], + touch_way_0_bits[1] ? state_vec_228[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hE5) + state_vec_229 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_229[1], + touch_way_0_bits[1] ? state_vec_229[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hE6) + state_vec_230 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_230[1], + touch_way_0_bits[1] ? state_vec_230[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hE7) + state_vec_231 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_231[1], + touch_way_0_bits[1] ? state_vec_231[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hE8) + state_vec_232 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_232[1], + touch_way_0_bits[1] ? state_vec_232[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hE9) + state_vec_233 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_233[1], + touch_way_0_bits[1] ? state_vec_233[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hEA) + state_vec_234 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_234[1], + touch_way_0_bits[1] ? state_vec_234[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hEB) + state_vec_235 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_235[1], + touch_way_0_bits[1] ? state_vec_235[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hEC) + state_vec_236 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_236[1], + touch_way_0_bits[1] ? state_vec_236[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hED) + state_vec_237 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_237[1], + touch_way_0_bits[1] ? state_vec_237[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hEE) + state_vec_238 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_238[1], + touch_way_0_bits[1] ? state_vec_238[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hEF) + state_vec_239 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_239[1], + touch_way_0_bits[1] ? state_vec_239[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hF0) + state_vec_240 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_240[1], + touch_way_0_bits[1] ? state_vec_240[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hF1) + state_vec_241 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_241[1], + touch_way_0_bits[1] ? state_vec_241[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hF2) + state_vec_242 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_242[1], + touch_way_0_bits[1] ? state_vec_242[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hF3) + state_vec_243 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_243[1], + touch_way_0_bits[1] ? state_vec_243[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hF4) + state_vec_244 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_244[1], + touch_way_0_bits[1] ? state_vec_244[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hF5) + state_vec_245 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_245[1], + touch_way_0_bits[1] ? state_vec_245[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hF6) + state_vec_246 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_246[1], + touch_way_0_bits[1] ? state_vec_246[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hF7) + state_vec_247 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_247[1], + touch_way_0_bits[1] ? state_vec_247[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hF8) + state_vec_248 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_248[1], + touch_way_0_bits[1] ? state_vec_248[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hF9) + state_vec_249 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_249[1], + touch_way_0_bits[1] ? state_vec_249[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hFA) + state_vec_250 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_250[1], + touch_way_0_bits[1] ? state_vec_250[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hFB) + state_vec_251 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_251[1], + touch_way_0_bits[1] ? state_vec_251[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hFC) + state_vec_252 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_252[1], + touch_way_0_bits[1] ? state_vec_252[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hFD) + state_vec_253 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_253[1], + touch_way_0_bits[1] ? state_vec_253[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hFE) + state_vec_254 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_254[1], + touch_way_0_bits[1] ? state_vec_254[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'hFF) + state_vec_255 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_255[1], + touch_way_0_bits[1] ? state_vec_255[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h100) + state_vec_256 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_256[1], + touch_way_0_bits[1] ? state_vec_256[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h101) + state_vec_257 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_257[1], + touch_way_0_bits[1] ? state_vec_257[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h102) + state_vec_258 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_258[1], + touch_way_0_bits[1] ? state_vec_258[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h103) + state_vec_259 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_259[1], + touch_way_0_bits[1] ? state_vec_259[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h104) + state_vec_260 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_260[1], + touch_way_0_bits[1] ? state_vec_260[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h105) + state_vec_261 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_261[1], + touch_way_0_bits[1] ? state_vec_261[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h106) + state_vec_262 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_262[1], + touch_way_0_bits[1] ? state_vec_262[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h107) + state_vec_263 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_263[1], + touch_way_0_bits[1] ? state_vec_263[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h108) + state_vec_264 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_264[1], + touch_way_0_bits[1] ? state_vec_264[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h109) + state_vec_265 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_265[1], + touch_way_0_bits[1] ? state_vec_265[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h10A) + state_vec_266 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_266[1], + touch_way_0_bits[1] ? state_vec_266[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h10B) + state_vec_267 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_267[1], + touch_way_0_bits[1] ? state_vec_267[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h10C) + state_vec_268 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_268[1], + touch_way_0_bits[1] ? state_vec_268[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h10D) + state_vec_269 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_269[1], + touch_way_0_bits[1] ? state_vec_269[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h10E) + state_vec_270 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_270[1], + touch_way_0_bits[1] ? state_vec_270[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h10F) + state_vec_271 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_271[1], + touch_way_0_bits[1] ? state_vec_271[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h110) + state_vec_272 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_272[1], + touch_way_0_bits[1] ? state_vec_272[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h111) + state_vec_273 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_273[1], + touch_way_0_bits[1] ? state_vec_273[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h112) + state_vec_274 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_274[1], + touch_way_0_bits[1] ? state_vec_274[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h113) + state_vec_275 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_275[1], + touch_way_0_bits[1] ? state_vec_275[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h114) + state_vec_276 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_276[1], + touch_way_0_bits[1] ? state_vec_276[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h115) + state_vec_277 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_277[1], + touch_way_0_bits[1] ? state_vec_277[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h116) + state_vec_278 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_278[1], + touch_way_0_bits[1] ? state_vec_278[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h117) + state_vec_279 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_279[1], + touch_way_0_bits[1] ? state_vec_279[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h118) + state_vec_280 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_280[1], + touch_way_0_bits[1] ? state_vec_280[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h119) + state_vec_281 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_281[1], + touch_way_0_bits[1] ? state_vec_281[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h11A) + state_vec_282 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_282[1], + touch_way_0_bits[1] ? state_vec_282[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h11B) + state_vec_283 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_283[1], + touch_way_0_bits[1] ? state_vec_283[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h11C) + state_vec_284 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_284[1], + touch_way_0_bits[1] ? state_vec_284[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h11D) + state_vec_285 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_285[1], + touch_way_0_bits[1] ? state_vec_285[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h11E) + state_vec_286 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_286[1], + touch_way_0_bits[1] ? state_vec_286[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h11F) + state_vec_287 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_287[1], + touch_way_0_bits[1] ? state_vec_287[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h120) + state_vec_288 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_288[1], + touch_way_0_bits[1] ? state_vec_288[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h121) + state_vec_289 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_289[1], + touch_way_0_bits[1] ? state_vec_289[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h122) + state_vec_290 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_290[1], + touch_way_0_bits[1] ? state_vec_290[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h123) + state_vec_291 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_291[1], + touch_way_0_bits[1] ? state_vec_291[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h124) + state_vec_292 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_292[1], + touch_way_0_bits[1] ? state_vec_292[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h125) + state_vec_293 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_293[1], + touch_way_0_bits[1] ? state_vec_293[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h126) + state_vec_294 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_294[1], + touch_way_0_bits[1] ? state_vec_294[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h127) + state_vec_295 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_295[1], + touch_way_0_bits[1] ? state_vec_295[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h128) + state_vec_296 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_296[1], + touch_way_0_bits[1] ? state_vec_296[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h129) + state_vec_297 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_297[1], + touch_way_0_bits[1] ? state_vec_297[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h12A) + state_vec_298 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_298[1], + touch_way_0_bits[1] ? state_vec_298[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h12B) + state_vec_299 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_299[1], + touch_way_0_bits[1] ? state_vec_299[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h12C) + state_vec_300 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_300[1], + touch_way_0_bits[1] ? state_vec_300[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h12D) + state_vec_301 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_301[1], + touch_way_0_bits[1] ? state_vec_301[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h12E) + state_vec_302 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_302[1], + touch_way_0_bits[1] ? state_vec_302[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h12F) + state_vec_303 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_303[1], + touch_way_0_bits[1] ? state_vec_303[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h130) + state_vec_304 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_304[1], + touch_way_0_bits[1] ? state_vec_304[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h131) + state_vec_305 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_305[1], + touch_way_0_bits[1] ? state_vec_305[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h132) + state_vec_306 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_306[1], + touch_way_0_bits[1] ? state_vec_306[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h133) + state_vec_307 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_307[1], + touch_way_0_bits[1] ? state_vec_307[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h134) + state_vec_308 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_308[1], + touch_way_0_bits[1] ? state_vec_308[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h135) + state_vec_309 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_309[1], + touch_way_0_bits[1] ? state_vec_309[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h136) + state_vec_310 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_310[1], + touch_way_0_bits[1] ? state_vec_310[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h137) + state_vec_311 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_311[1], + touch_way_0_bits[1] ? state_vec_311[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h138) + state_vec_312 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_312[1], + touch_way_0_bits[1] ? state_vec_312[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h139) + state_vec_313 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_313[1], + touch_way_0_bits[1] ? state_vec_313[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h13A) + state_vec_314 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_314[1], + touch_way_0_bits[1] ? state_vec_314[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h13B) + state_vec_315 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_315[1], + touch_way_0_bits[1] ? state_vec_315[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h13C) + state_vec_316 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_316[1], + touch_way_0_bits[1] ? state_vec_316[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h13D) + state_vec_317 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_317[1], + touch_way_0_bits[1] ? state_vec_317[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h13E) + state_vec_318 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_318[1], + touch_way_0_bits[1] ? state_vec_318[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h13F) + state_vec_319 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_319[1], + touch_way_0_bits[1] ? state_vec_319[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h140) + state_vec_320 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_320[1], + touch_way_0_bits[1] ? state_vec_320[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h141) + state_vec_321 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_321[1], + touch_way_0_bits[1] ? state_vec_321[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h142) + state_vec_322 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_322[1], + touch_way_0_bits[1] ? state_vec_322[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h143) + state_vec_323 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_323[1], + touch_way_0_bits[1] ? state_vec_323[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h144) + state_vec_324 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_324[1], + touch_way_0_bits[1] ? state_vec_324[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h145) + state_vec_325 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_325[1], + touch_way_0_bits[1] ? state_vec_325[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h146) + state_vec_326 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_326[1], + touch_way_0_bits[1] ? state_vec_326[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h147) + state_vec_327 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_327[1], + touch_way_0_bits[1] ? state_vec_327[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h148) + state_vec_328 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_328[1], + touch_way_0_bits[1] ? state_vec_328[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h149) + state_vec_329 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_329[1], + touch_way_0_bits[1] ? state_vec_329[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h14A) + state_vec_330 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_330[1], + touch_way_0_bits[1] ? state_vec_330[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h14B) + state_vec_331 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_331[1], + touch_way_0_bits[1] ? state_vec_331[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h14C) + state_vec_332 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_332[1], + touch_way_0_bits[1] ? state_vec_332[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h14D) + state_vec_333 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_333[1], + touch_way_0_bits[1] ? state_vec_333[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h14E) + state_vec_334 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_334[1], + touch_way_0_bits[1] ? state_vec_334[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h14F) + state_vec_335 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_335[1], + touch_way_0_bits[1] ? state_vec_335[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h150) + state_vec_336 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_336[1], + touch_way_0_bits[1] ? state_vec_336[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h151) + state_vec_337 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_337[1], + touch_way_0_bits[1] ? state_vec_337[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h152) + state_vec_338 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_338[1], + touch_way_0_bits[1] ? state_vec_338[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h153) + state_vec_339 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_339[1], + touch_way_0_bits[1] ? state_vec_339[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h154) + state_vec_340 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_340[1], + touch_way_0_bits[1] ? state_vec_340[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h155) + state_vec_341 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_341[1], + touch_way_0_bits[1] ? state_vec_341[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h156) + state_vec_342 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_342[1], + touch_way_0_bits[1] ? state_vec_342[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h157) + state_vec_343 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_343[1], + touch_way_0_bits[1] ? state_vec_343[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h158) + state_vec_344 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_344[1], + touch_way_0_bits[1] ? state_vec_344[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h159) + state_vec_345 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_345[1], + touch_way_0_bits[1] ? state_vec_345[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h15A) + state_vec_346 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_346[1], + touch_way_0_bits[1] ? state_vec_346[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h15B) + state_vec_347 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_347[1], + touch_way_0_bits[1] ? state_vec_347[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h15C) + state_vec_348 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_348[1], + touch_way_0_bits[1] ? state_vec_348[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h15D) + state_vec_349 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_349[1], + touch_way_0_bits[1] ? state_vec_349[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h15E) + state_vec_350 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_350[1], + touch_way_0_bits[1] ? state_vec_350[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h15F) + state_vec_351 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_351[1], + touch_way_0_bits[1] ? state_vec_351[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h160) + state_vec_352 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_352[1], + touch_way_0_bits[1] ? state_vec_352[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h161) + state_vec_353 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_353[1], + touch_way_0_bits[1] ? state_vec_353[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h162) + state_vec_354 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_354[1], + touch_way_0_bits[1] ? state_vec_354[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h163) + state_vec_355 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_355[1], + touch_way_0_bits[1] ? state_vec_355[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h164) + state_vec_356 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_356[1], + touch_way_0_bits[1] ? state_vec_356[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h165) + state_vec_357 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_357[1], + touch_way_0_bits[1] ? state_vec_357[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h166) + state_vec_358 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_358[1], + touch_way_0_bits[1] ? state_vec_358[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h167) + state_vec_359 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_359[1], + touch_way_0_bits[1] ? state_vec_359[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h168) + state_vec_360 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_360[1], + touch_way_0_bits[1] ? state_vec_360[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h169) + state_vec_361 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_361[1], + touch_way_0_bits[1] ? state_vec_361[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h16A) + state_vec_362 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_362[1], + touch_way_0_bits[1] ? state_vec_362[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h16B) + state_vec_363 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_363[1], + touch_way_0_bits[1] ? state_vec_363[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h16C) + state_vec_364 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_364[1], + touch_way_0_bits[1] ? state_vec_364[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h16D) + state_vec_365 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_365[1], + touch_way_0_bits[1] ? state_vec_365[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h16E) + state_vec_366 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_366[1], + touch_way_0_bits[1] ? state_vec_366[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h16F) + state_vec_367 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_367[1], + touch_way_0_bits[1] ? state_vec_367[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h170) + state_vec_368 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_368[1], + touch_way_0_bits[1] ? state_vec_368[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h171) + state_vec_369 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_369[1], + touch_way_0_bits[1] ? state_vec_369[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h172) + state_vec_370 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_370[1], + touch_way_0_bits[1] ? state_vec_370[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h173) + state_vec_371 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_371[1], + touch_way_0_bits[1] ? state_vec_371[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h174) + state_vec_372 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_372[1], + touch_way_0_bits[1] ? state_vec_372[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h175) + state_vec_373 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_373[1], + touch_way_0_bits[1] ? state_vec_373[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h176) + state_vec_374 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_374[1], + touch_way_0_bits[1] ? state_vec_374[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h177) + state_vec_375 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_375[1], + touch_way_0_bits[1] ? state_vec_375[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h178) + state_vec_376 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_376[1], + touch_way_0_bits[1] ? state_vec_376[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h179) + state_vec_377 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_377[1], + touch_way_0_bits[1] ? state_vec_377[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h17A) + state_vec_378 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_378[1], + touch_way_0_bits[1] ? state_vec_378[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h17B) + state_vec_379 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_379[1], + touch_way_0_bits[1] ? state_vec_379[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h17C) + state_vec_380 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_380[1], + touch_way_0_bits[1] ? state_vec_380[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h17D) + state_vec_381 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_381[1], + touch_way_0_bits[1] ? state_vec_381[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h17E) + state_vec_382 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_382[1], + touch_way_0_bits[1] ? state_vec_382[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h17F) + state_vec_383 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_383[1], + touch_way_0_bits[1] ? state_vec_383[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h180) + state_vec_384 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_384[1], + touch_way_0_bits[1] ? state_vec_384[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h181) + state_vec_385 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_385[1], + touch_way_0_bits[1] ? state_vec_385[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h182) + state_vec_386 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_386[1], + touch_way_0_bits[1] ? state_vec_386[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h183) + state_vec_387 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_387[1], + touch_way_0_bits[1] ? state_vec_387[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h184) + state_vec_388 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_388[1], + touch_way_0_bits[1] ? state_vec_388[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h185) + state_vec_389 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_389[1], + touch_way_0_bits[1] ? state_vec_389[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h186) + state_vec_390 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_390[1], + touch_way_0_bits[1] ? state_vec_390[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h187) + state_vec_391 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_391[1], + touch_way_0_bits[1] ? state_vec_391[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h188) + state_vec_392 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_392[1], + touch_way_0_bits[1] ? state_vec_392[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h189) + state_vec_393 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_393[1], + touch_way_0_bits[1] ? state_vec_393[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h18A) + state_vec_394 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_394[1], + touch_way_0_bits[1] ? state_vec_394[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h18B) + state_vec_395 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_395[1], + touch_way_0_bits[1] ? state_vec_395[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h18C) + state_vec_396 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_396[1], + touch_way_0_bits[1] ? state_vec_396[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h18D) + state_vec_397 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_397[1], + touch_way_0_bits[1] ? state_vec_397[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h18E) + state_vec_398 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_398[1], + touch_way_0_bits[1] ? state_vec_398[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h18F) + state_vec_399 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_399[1], + touch_way_0_bits[1] ? state_vec_399[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h190) + state_vec_400 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_400[1], + touch_way_0_bits[1] ? state_vec_400[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h191) + state_vec_401 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_401[1], + touch_way_0_bits[1] ? state_vec_401[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h192) + state_vec_402 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_402[1], + touch_way_0_bits[1] ? state_vec_402[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h193) + state_vec_403 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_403[1], + touch_way_0_bits[1] ? state_vec_403[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h194) + state_vec_404 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_404[1], + touch_way_0_bits[1] ? state_vec_404[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h195) + state_vec_405 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_405[1], + touch_way_0_bits[1] ? state_vec_405[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h196) + state_vec_406 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_406[1], + touch_way_0_bits[1] ? state_vec_406[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h197) + state_vec_407 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_407[1], + touch_way_0_bits[1] ? state_vec_407[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h198) + state_vec_408 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_408[1], + touch_way_0_bits[1] ? state_vec_408[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h199) + state_vec_409 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_409[1], + touch_way_0_bits[1] ? state_vec_409[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h19A) + state_vec_410 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_410[1], + touch_way_0_bits[1] ? state_vec_410[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h19B) + state_vec_411 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_411[1], + touch_way_0_bits[1] ? state_vec_411[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h19C) + state_vec_412 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_412[1], + touch_way_0_bits[1] ? state_vec_412[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h19D) + state_vec_413 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_413[1], + touch_way_0_bits[1] ? state_vec_413[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h19E) + state_vec_414 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_414[1], + touch_way_0_bits[1] ? state_vec_414[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h19F) + state_vec_415 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_415[1], + touch_way_0_bits[1] ? state_vec_415[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1A0) + state_vec_416 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_416[1], + touch_way_0_bits[1] ? state_vec_416[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1A1) + state_vec_417 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_417[1], + touch_way_0_bits[1] ? state_vec_417[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1A2) + state_vec_418 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_418[1], + touch_way_0_bits[1] ? state_vec_418[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1A3) + state_vec_419 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_419[1], + touch_way_0_bits[1] ? state_vec_419[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1A4) + state_vec_420 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_420[1], + touch_way_0_bits[1] ? state_vec_420[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1A5) + state_vec_421 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_421[1], + touch_way_0_bits[1] ? state_vec_421[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1A6) + state_vec_422 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_422[1], + touch_way_0_bits[1] ? state_vec_422[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1A7) + state_vec_423 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_423[1], + touch_way_0_bits[1] ? state_vec_423[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1A8) + state_vec_424 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_424[1], + touch_way_0_bits[1] ? state_vec_424[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1A9) + state_vec_425 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_425[1], + touch_way_0_bits[1] ? state_vec_425[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1AA) + state_vec_426 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_426[1], + touch_way_0_bits[1] ? state_vec_426[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1AB) + state_vec_427 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_427[1], + touch_way_0_bits[1] ? state_vec_427[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1AC) + state_vec_428 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_428[1], + touch_way_0_bits[1] ? state_vec_428[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1AD) + state_vec_429 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_429[1], + touch_way_0_bits[1] ? state_vec_429[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1AE) + state_vec_430 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_430[1], + touch_way_0_bits[1] ? state_vec_430[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1AF) + state_vec_431 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_431[1], + touch_way_0_bits[1] ? state_vec_431[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1B0) + state_vec_432 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_432[1], + touch_way_0_bits[1] ? state_vec_432[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1B1) + state_vec_433 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_433[1], + touch_way_0_bits[1] ? state_vec_433[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1B2) + state_vec_434 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_434[1], + touch_way_0_bits[1] ? state_vec_434[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1B3) + state_vec_435 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_435[1], + touch_way_0_bits[1] ? state_vec_435[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1B4) + state_vec_436 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_436[1], + touch_way_0_bits[1] ? state_vec_436[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1B5) + state_vec_437 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_437[1], + touch_way_0_bits[1] ? state_vec_437[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1B6) + state_vec_438 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_438[1], + touch_way_0_bits[1] ? state_vec_438[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1B7) + state_vec_439 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_439[1], + touch_way_0_bits[1] ? state_vec_439[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1B8) + state_vec_440 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_440[1], + touch_way_0_bits[1] ? state_vec_440[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1B9) + state_vec_441 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_441[1], + touch_way_0_bits[1] ? state_vec_441[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1BA) + state_vec_442 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_442[1], + touch_way_0_bits[1] ? state_vec_442[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1BB) + state_vec_443 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_443[1], + touch_way_0_bits[1] ? state_vec_443[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1BC) + state_vec_444 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_444[1], + touch_way_0_bits[1] ? state_vec_444[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1BD) + state_vec_445 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_445[1], + touch_way_0_bits[1] ? state_vec_445[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1BE) + state_vec_446 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_446[1], + touch_way_0_bits[1] ? state_vec_446[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1BF) + state_vec_447 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_447[1], + touch_way_0_bits[1] ? state_vec_447[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1C0) + state_vec_448 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_448[1], + touch_way_0_bits[1] ? state_vec_448[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1C1) + state_vec_449 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_449[1], + touch_way_0_bits[1] ? state_vec_449[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1C2) + state_vec_450 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_450[1], + touch_way_0_bits[1] ? state_vec_450[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1C3) + state_vec_451 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_451[1], + touch_way_0_bits[1] ? state_vec_451[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1C4) + state_vec_452 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_452[1], + touch_way_0_bits[1] ? state_vec_452[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1C5) + state_vec_453 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_453[1], + touch_way_0_bits[1] ? state_vec_453[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1C6) + state_vec_454 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_454[1], + touch_way_0_bits[1] ? state_vec_454[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1C7) + state_vec_455 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_455[1], + touch_way_0_bits[1] ? state_vec_455[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1C8) + state_vec_456 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_456[1], + touch_way_0_bits[1] ? state_vec_456[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1C9) + state_vec_457 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_457[1], + touch_way_0_bits[1] ? state_vec_457[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1CA) + state_vec_458 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_458[1], + touch_way_0_bits[1] ? state_vec_458[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1CB) + state_vec_459 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_459[1], + touch_way_0_bits[1] ? state_vec_459[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1CC) + state_vec_460 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_460[1], + touch_way_0_bits[1] ? state_vec_460[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1CD) + state_vec_461 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_461[1], + touch_way_0_bits[1] ? state_vec_461[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1CE) + state_vec_462 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_462[1], + touch_way_0_bits[1] ? state_vec_462[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1CF) + state_vec_463 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_463[1], + touch_way_0_bits[1] ? state_vec_463[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1D0) + state_vec_464 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_464[1], + touch_way_0_bits[1] ? state_vec_464[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1D1) + state_vec_465 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_465[1], + touch_way_0_bits[1] ? state_vec_465[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1D2) + state_vec_466 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_466[1], + touch_way_0_bits[1] ? state_vec_466[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1D3) + state_vec_467 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_467[1], + touch_way_0_bits[1] ? state_vec_467[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1D4) + state_vec_468 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_468[1], + touch_way_0_bits[1] ? state_vec_468[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1D5) + state_vec_469 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_469[1], + touch_way_0_bits[1] ? state_vec_469[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1D6) + state_vec_470 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_470[1], + touch_way_0_bits[1] ? state_vec_470[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1D7) + state_vec_471 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_471[1], + touch_way_0_bits[1] ? state_vec_471[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1D8) + state_vec_472 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_472[1], + touch_way_0_bits[1] ? state_vec_472[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1D9) + state_vec_473 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_473[1], + touch_way_0_bits[1] ? state_vec_473[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1DA) + state_vec_474 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_474[1], + touch_way_0_bits[1] ? state_vec_474[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1DB) + state_vec_475 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_475[1], + touch_way_0_bits[1] ? state_vec_475[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1DC) + state_vec_476 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_476[1], + touch_way_0_bits[1] ? state_vec_476[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1DD) + state_vec_477 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_477[1], + touch_way_0_bits[1] ? state_vec_477[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1DE) + state_vec_478 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_478[1], + touch_way_0_bits[1] ? state_vec_478[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1DF) + state_vec_479 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_479[1], + touch_way_0_bits[1] ? state_vec_479[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1E0) + state_vec_480 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_480[1], + touch_way_0_bits[1] ? state_vec_480[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1E1) + state_vec_481 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_481[1], + touch_way_0_bits[1] ? state_vec_481[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1E2) + state_vec_482 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_482[1], + touch_way_0_bits[1] ? state_vec_482[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1E3) + state_vec_483 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_483[1], + touch_way_0_bits[1] ? state_vec_483[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1E4) + state_vec_484 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_484[1], + touch_way_0_bits[1] ? state_vec_484[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1E5) + state_vec_485 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_485[1], + touch_way_0_bits[1] ? state_vec_485[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1E6) + state_vec_486 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_486[1], + touch_way_0_bits[1] ? state_vec_486[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1E7) + state_vec_487 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_487[1], + touch_way_0_bits[1] ? state_vec_487[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1E8) + state_vec_488 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_488[1], + touch_way_0_bits[1] ? state_vec_488[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1E9) + state_vec_489 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_489[1], + touch_way_0_bits[1] ? state_vec_489[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1EA) + state_vec_490 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_490[1], + touch_way_0_bits[1] ? state_vec_490[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1EB) + state_vec_491 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_491[1], + touch_way_0_bits[1] ? state_vec_491[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1EC) + state_vec_492 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_492[1], + touch_way_0_bits[1] ? state_vec_492[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1ED) + state_vec_493 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_493[1], + touch_way_0_bits[1] ? state_vec_493[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1EE) + state_vec_494 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_494[1], + touch_way_0_bits[1] ? state_vec_494[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1EF) + state_vec_495 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_495[1], + touch_way_0_bits[1] ? state_vec_495[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1F0) + state_vec_496 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_496[1], + touch_way_0_bits[1] ? state_vec_496[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1F1) + state_vec_497 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_497[1], + touch_way_0_bits[1] ? state_vec_497[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1F2) + state_vec_498 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_498[1], + touch_way_0_bits[1] ? state_vec_498[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1F3) + state_vec_499 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_499[1], + touch_way_0_bits[1] ? state_vec_499[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1F4) + state_vec_500 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_500[1], + touch_way_0_bits[1] ? state_vec_500[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1F5) + state_vec_501 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_501[1], + touch_way_0_bits[1] ? state_vec_501[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1F6) + state_vec_502 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_502[1], + touch_way_0_bits[1] ? state_vec_502[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1F7) + state_vec_503 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_503[1], + touch_way_0_bits[1] ? state_vec_503[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1F8) + state_vec_504 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_504[1], + touch_way_0_bits[1] ? state_vec_504[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1F9) + state_vec_505 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_505[1], + touch_way_0_bits[1] ? state_vec_505[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1FA) + state_vec_506 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_506[1], + touch_way_0_bits[1] ? state_vec_506[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1FB) + state_vec_507 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_507[1], + touch_way_0_bits[1] ? state_vec_507[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1FC) + state_vec_508 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_508[1], + touch_way_0_bits[1] ? state_vec_508[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1FD) + state_vec_509 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_509[1], + touch_way_0_bits[1] ? state_vec_509[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & touch_set_0 == 9'h1FE) + state_vec_510 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_510[1], + touch_way_0_bits[1] ? state_vec_510[0] : ~(touch_way_0_bits[0])}; + if (touch_way_0_valid & (&touch_set_0)) + state_vec_511 <= + {~(touch_way_0_bits[1]), + touch_way_0_bits[1] ? ~(touch_way_0_bits[0]) : state_vec_511[1], + touch_way_0_bits[1] ? state_vec_511[0] : ~(touch_way_0_bits[0])}; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:60]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [5:0] i = 6'h0; i < 6'h3D; i += 6'h1) begin + _RANDOM[i] = `RANDOM; + end + pred_rdata_REG = _RANDOM[6'h0][0]; + pred_rdata_hold_data_0_entry_valid = _RANDOM[6'h0][1]; + pred_rdata_hold_data_0_entry_brSlots_0_offset = _RANDOM[6'h0][5:2]; + pred_rdata_hold_data_0_entry_brSlots_0_lower = _RANDOM[6'h0][17:6]; + pred_rdata_hold_data_0_entry_brSlots_0_tarStat = _RANDOM[6'h0][19:18]; + pred_rdata_hold_data_0_entry_brSlots_0_sharing = _RANDOM[6'h0][20]; + pred_rdata_hold_data_0_entry_brSlots_0_valid = _RANDOM[6'h0][21]; + pred_rdata_hold_data_0_entry_tailSlot_offset = _RANDOM[6'h0][25:22]; + pred_rdata_hold_data_0_entry_tailSlot_lower = + {_RANDOM[6'h0][31:26], _RANDOM[6'h1][13:0]}; + pred_rdata_hold_data_0_entry_tailSlot_tarStat = _RANDOM[6'h1][15:14]; + pred_rdata_hold_data_0_entry_tailSlot_sharing = _RANDOM[6'h1][16]; + pred_rdata_hold_data_0_entry_tailSlot_valid = _RANDOM[6'h1][17]; + pred_rdata_hold_data_0_entry_pftAddr = _RANDOM[6'h1][21:18]; + pred_rdata_hold_data_0_entry_carry = _RANDOM[6'h1][22]; + pred_rdata_hold_data_0_entry_isCall = _RANDOM[6'h1][23]; + pred_rdata_hold_data_0_entry_isRet = _RANDOM[6'h1][24]; + pred_rdata_hold_data_0_entry_isJalr = _RANDOM[6'h1][25]; + pred_rdata_hold_data_0_entry_last_may_be_rvi_call = _RANDOM[6'h1][26]; + pred_rdata_hold_data_0_entry_always_taken_0 = _RANDOM[6'h1][27]; + pred_rdata_hold_data_0_entry_always_taken_1 = _RANDOM[6'h1][28]; + pred_rdata_hold_data_0_tag = {_RANDOM[6'h1][31:29], _RANDOM[6'h2][16:0]}; + pred_rdata_hold_data_1_entry_valid = _RANDOM[6'h2][17]; + pred_rdata_hold_data_1_entry_brSlots_0_offset = _RANDOM[6'h2][21:18]; + pred_rdata_hold_data_1_entry_brSlots_0_lower = + {_RANDOM[6'h2][31:22], _RANDOM[6'h3][1:0]}; + pred_rdata_hold_data_1_entry_brSlots_0_tarStat = _RANDOM[6'h3][3:2]; + pred_rdata_hold_data_1_entry_brSlots_0_sharing = _RANDOM[6'h3][4]; + pred_rdata_hold_data_1_entry_brSlots_0_valid = _RANDOM[6'h3][5]; + pred_rdata_hold_data_1_entry_tailSlot_offset = _RANDOM[6'h3][9:6]; + pred_rdata_hold_data_1_entry_tailSlot_lower = _RANDOM[6'h3][29:10]; + pred_rdata_hold_data_1_entry_tailSlot_tarStat = _RANDOM[6'h3][31:30]; + pred_rdata_hold_data_1_entry_tailSlot_sharing = _RANDOM[6'h4][0]; + pred_rdata_hold_data_1_entry_tailSlot_valid = _RANDOM[6'h4][1]; + pred_rdata_hold_data_1_entry_pftAddr = _RANDOM[6'h4][5:2]; + pred_rdata_hold_data_1_entry_carry = _RANDOM[6'h4][6]; + pred_rdata_hold_data_1_entry_isCall = _RANDOM[6'h4][7]; + pred_rdata_hold_data_1_entry_isRet = _RANDOM[6'h4][8]; + pred_rdata_hold_data_1_entry_isJalr = _RANDOM[6'h4][9]; + pred_rdata_hold_data_1_entry_last_may_be_rvi_call = _RANDOM[6'h4][10]; + pred_rdata_hold_data_1_entry_always_taken_0 = _RANDOM[6'h4][11]; + pred_rdata_hold_data_1_entry_always_taken_1 = _RANDOM[6'h4][12]; + pred_rdata_hold_data_1_tag = {_RANDOM[6'h4][31:13], _RANDOM[6'h5][0]}; + pred_rdata_hold_data_2_entry_valid = _RANDOM[6'h5][1]; + pred_rdata_hold_data_2_entry_brSlots_0_offset = _RANDOM[6'h5][5:2]; + pred_rdata_hold_data_2_entry_brSlots_0_lower = _RANDOM[6'h5][17:6]; + pred_rdata_hold_data_2_entry_brSlots_0_tarStat = _RANDOM[6'h5][19:18]; + pred_rdata_hold_data_2_entry_brSlots_0_sharing = _RANDOM[6'h5][20]; + pred_rdata_hold_data_2_entry_brSlots_0_valid = _RANDOM[6'h5][21]; + pred_rdata_hold_data_2_entry_tailSlot_offset = _RANDOM[6'h5][25:22]; + pred_rdata_hold_data_2_entry_tailSlot_lower = + {_RANDOM[6'h5][31:26], _RANDOM[6'h6][13:0]}; + pred_rdata_hold_data_2_entry_tailSlot_tarStat = _RANDOM[6'h6][15:14]; + pred_rdata_hold_data_2_entry_tailSlot_sharing = _RANDOM[6'h6][16]; + pred_rdata_hold_data_2_entry_tailSlot_valid = _RANDOM[6'h6][17]; + pred_rdata_hold_data_2_entry_pftAddr = _RANDOM[6'h6][21:18]; + pred_rdata_hold_data_2_entry_carry = _RANDOM[6'h6][22]; + pred_rdata_hold_data_2_entry_isCall = _RANDOM[6'h6][23]; + pred_rdata_hold_data_2_entry_isRet = _RANDOM[6'h6][24]; + pred_rdata_hold_data_2_entry_isJalr = _RANDOM[6'h6][25]; + pred_rdata_hold_data_2_entry_last_may_be_rvi_call = _RANDOM[6'h6][26]; + pred_rdata_hold_data_2_entry_always_taken_0 = _RANDOM[6'h6][27]; + pred_rdata_hold_data_2_entry_always_taken_1 = _RANDOM[6'h6][28]; + pred_rdata_hold_data_2_tag = {_RANDOM[6'h6][31:29], _RANDOM[6'h7][16:0]}; + pred_rdata_hold_data_3_entry_valid = _RANDOM[6'h7][17]; + pred_rdata_hold_data_3_entry_brSlots_0_offset = _RANDOM[6'h7][21:18]; + pred_rdata_hold_data_3_entry_brSlots_0_lower = + {_RANDOM[6'h7][31:22], _RANDOM[6'h8][1:0]}; + pred_rdata_hold_data_3_entry_brSlots_0_tarStat = _RANDOM[6'h8][3:2]; + pred_rdata_hold_data_3_entry_brSlots_0_sharing = _RANDOM[6'h8][4]; + pred_rdata_hold_data_3_entry_brSlots_0_valid = _RANDOM[6'h8][5]; + pred_rdata_hold_data_3_entry_tailSlot_offset = _RANDOM[6'h8][9:6]; + pred_rdata_hold_data_3_entry_tailSlot_lower = _RANDOM[6'h8][29:10]; + pred_rdata_hold_data_3_entry_tailSlot_tarStat = _RANDOM[6'h8][31:30]; + pred_rdata_hold_data_3_entry_tailSlot_sharing = _RANDOM[6'h9][0]; + pred_rdata_hold_data_3_entry_tailSlot_valid = _RANDOM[6'h9][1]; + pred_rdata_hold_data_3_entry_pftAddr = _RANDOM[6'h9][5:2]; + pred_rdata_hold_data_3_entry_carry = _RANDOM[6'h9][6]; + pred_rdata_hold_data_3_entry_isCall = _RANDOM[6'h9][7]; + pred_rdata_hold_data_3_entry_isRet = _RANDOM[6'h9][8]; + pred_rdata_hold_data_3_entry_isJalr = _RANDOM[6'h9][9]; + pred_rdata_hold_data_3_entry_last_may_be_rvi_call = _RANDOM[6'h9][10]; + pred_rdata_hold_data_3_entry_always_taken_0 = _RANDOM[6'h9][11]; + pred_rdata_hold_data_3_entry_always_taken_1 = _RANDOM[6'h9][12]; + pred_rdata_hold_data_3_tag = {_RANDOM[6'h9][31:13], _RANDOM[6'hA][0]}; + req_tag = _RANDOM[6'hA][20:1]; + req_idx = _RANDOM[6'hA][29:21]; + u_req_tag = {_RANDOM[6'hA][31:30], _RANDOM[6'hB][17:0]}; + u_total_hits_REG = _RANDOM[6'hB][18]; + u_total_hits_REG_1 = _RANDOM[6'hB][19]; + u_total_hits_REG_2 = _RANDOM[6'hB][20]; + u_total_hits_REG_3 = _RANDOM[6'hB][21]; + state_vec_0 = _RANDOM[6'hB][27:25]; + state_vec_1 = _RANDOM[6'hB][30:28]; + state_vec_2 = {_RANDOM[6'hB][31], _RANDOM[6'hC][1:0]}; + state_vec_3 = _RANDOM[6'hC][4:2]; + state_vec_4 = _RANDOM[6'hC][7:5]; + state_vec_5 = _RANDOM[6'hC][10:8]; + state_vec_6 = _RANDOM[6'hC][13:11]; + state_vec_7 = _RANDOM[6'hC][16:14]; + state_vec_8 = _RANDOM[6'hC][19:17]; + state_vec_9 = _RANDOM[6'hC][22:20]; + state_vec_10 = _RANDOM[6'hC][25:23]; + state_vec_11 = _RANDOM[6'hC][28:26]; + state_vec_12 = _RANDOM[6'hC][31:29]; + state_vec_13 = _RANDOM[6'hD][2:0]; + state_vec_14 = _RANDOM[6'hD][5:3]; + state_vec_15 = _RANDOM[6'hD][8:6]; + state_vec_16 = _RANDOM[6'hD][11:9]; + state_vec_17 = _RANDOM[6'hD][14:12]; + state_vec_18 = _RANDOM[6'hD][17:15]; + state_vec_19 = _RANDOM[6'hD][20:18]; + state_vec_20 = _RANDOM[6'hD][23:21]; + state_vec_21 = _RANDOM[6'hD][26:24]; + state_vec_22 = _RANDOM[6'hD][29:27]; + state_vec_23 = {_RANDOM[6'hD][31:30], _RANDOM[6'hE][0]}; + state_vec_24 = _RANDOM[6'hE][3:1]; + state_vec_25 = _RANDOM[6'hE][6:4]; + state_vec_26 = _RANDOM[6'hE][9:7]; + state_vec_27 = _RANDOM[6'hE][12:10]; + state_vec_28 = _RANDOM[6'hE][15:13]; + state_vec_29 = _RANDOM[6'hE][18:16]; + state_vec_30 = _RANDOM[6'hE][21:19]; + state_vec_31 = _RANDOM[6'hE][24:22]; + state_vec_32 = _RANDOM[6'hE][27:25]; + state_vec_33 = _RANDOM[6'hE][30:28]; + state_vec_34 = {_RANDOM[6'hE][31], _RANDOM[6'hF][1:0]}; + state_vec_35 = _RANDOM[6'hF][4:2]; + state_vec_36 = _RANDOM[6'hF][7:5]; + state_vec_37 = _RANDOM[6'hF][10:8]; + state_vec_38 = _RANDOM[6'hF][13:11]; + state_vec_39 = _RANDOM[6'hF][16:14]; + state_vec_40 = _RANDOM[6'hF][19:17]; + state_vec_41 = _RANDOM[6'hF][22:20]; + state_vec_42 = _RANDOM[6'hF][25:23]; + state_vec_43 = _RANDOM[6'hF][28:26]; + state_vec_44 = _RANDOM[6'hF][31:29]; + state_vec_45 = _RANDOM[6'h10][2:0]; + state_vec_46 = _RANDOM[6'h10][5:3]; + state_vec_47 = _RANDOM[6'h10][8:6]; + state_vec_48 = _RANDOM[6'h10][11:9]; + state_vec_49 = _RANDOM[6'h10][14:12]; + state_vec_50 = _RANDOM[6'h10][17:15]; + state_vec_51 = _RANDOM[6'h10][20:18]; + state_vec_52 = _RANDOM[6'h10][23:21]; + state_vec_53 = _RANDOM[6'h10][26:24]; + state_vec_54 = _RANDOM[6'h10][29:27]; + state_vec_55 = {_RANDOM[6'h10][31:30], _RANDOM[6'h11][0]}; + state_vec_56 = _RANDOM[6'h11][3:1]; + state_vec_57 = _RANDOM[6'h11][6:4]; + state_vec_58 = _RANDOM[6'h11][9:7]; + state_vec_59 = _RANDOM[6'h11][12:10]; + state_vec_60 = _RANDOM[6'h11][15:13]; + state_vec_61 = _RANDOM[6'h11][18:16]; + state_vec_62 = _RANDOM[6'h11][21:19]; + state_vec_63 = _RANDOM[6'h11][24:22]; + state_vec_64 = _RANDOM[6'h11][27:25]; + state_vec_65 = _RANDOM[6'h11][30:28]; + state_vec_66 = {_RANDOM[6'h11][31], _RANDOM[6'h12][1:0]}; + state_vec_67 = _RANDOM[6'h12][4:2]; + state_vec_68 = _RANDOM[6'h12][7:5]; + state_vec_69 = _RANDOM[6'h12][10:8]; + state_vec_70 = _RANDOM[6'h12][13:11]; + state_vec_71 = _RANDOM[6'h12][16:14]; + state_vec_72 = _RANDOM[6'h12][19:17]; + state_vec_73 = _RANDOM[6'h12][22:20]; + state_vec_74 = _RANDOM[6'h12][25:23]; + state_vec_75 = _RANDOM[6'h12][28:26]; + state_vec_76 = _RANDOM[6'h12][31:29]; + state_vec_77 = _RANDOM[6'h13][2:0]; + state_vec_78 = _RANDOM[6'h13][5:3]; + state_vec_79 = _RANDOM[6'h13][8:6]; + state_vec_80 = _RANDOM[6'h13][11:9]; + state_vec_81 = _RANDOM[6'h13][14:12]; + state_vec_82 = _RANDOM[6'h13][17:15]; + state_vec_83 = _RANDOM[6'h13][20:18]; + state_vec_84 = _RANDOM[6'h13][23:21]; + state_vec_85 = _RANDOM[6'h13][26:24]; + state_vec_86 = _RANDOM[6'h13][29:27]; + state_vec_87 = {_RANDOM[6'h13][31:30], _RANDOM[6'h14][0]}; + state_vec_88 = _RANDOM[6'h14][3:1]; + state_vec_89 = _RANDOM[6'h14][6:4]; + state_vec_90 = _RANDOM[6'h14][9:7]; + state_vec_91 = _RANDOM[6'h14][12:10]; + state_vec_92 = _RANDOM[6'h14][15:13]; + state_vec_93 = _RANDOM[6'h14][18:16]; + state_vec_94 = _RANDOM[6'h14][21:19]; + state_vec_95 = _RANDOM[6'h14][24:22]; + state_vec_96 = _RANDOM[6'h14][27:25]; + state_vec_97 = _RANDOM[6'h14][30:28]; + state_vec_98 = {_RANDOM[6'h14][31], _RANDOM[6'h15][1:0]}; + state_vec_99 = _RANDOM[6'h15][4:2]; + state_vec_100 = _RANDOM[6'h15][7:5]; + state_vec_101 = _RANDOM[6'h15][10:8]; + state_vec_102 = _RANDOM[6'h15][13:11]; + state_vec_103 = _RANDOM[6'h15][16:14]; + state_vec_104 = _RANDOM[6'h15][19:17]; + state_vec_105 = _RANDOM[6'h15][22:20]; + state_vec_106 = _RANDOM[6'h15][25:23]; + state_vec_107 = _RANDOM[6'h15][28:26]; + state_vec_108 = _RANDOM[6'h15][31:29]; + state_vec_109 = _RANDOM[6'h16][2:0]; + state_vec_110 = _RANDOM[6'h16][5:3]; + state_vec_111 = _RANDOM[6'h16][8:6]; + state_vec_112 = _RANDOM[6'h16][11:9]; + state_vec_113 = _RANDOM[6'h16][14:12]; + state_vec_114 = _RANDOM[6'h16][17:15]; + state_vec_115 = _RANDOM[6'h16][20:18]; + state_vec_116 = _RANDOM[6'h16][23:21]; + state_vec_117 = _RANDOM[6'h16][26:24]; + state_vec_118 = _RANDOM[6'h16][29:27]; + state_vec_119 = {_RANDOM[6'h16][31:30], _RANDOM[6'h17][0]}; + state_vec_120 = _RANDOM[6'h17][3:1]; + state_vec_121 = _RANDOM[6'h17][6:4]; + state_vec_122 = _RANDOM[6'h17][9:7]; + state_vec_123 = _RANDOM[6'h17][12:10]; + state_vec_124 = _RANDOM[6'h17][15:13]; + state_vec_125 = _RANDOM[6'h17][18:16]; + state_vec_126 = _RANDOM[6'h17][21:19]; + state_vec_127 = _RANDOM[6'h17][24:22]; + state_vec_128 = _RANDOM[6'h17][27:25]; + state_vec_129 = _RANDOM[6'h17][30:28]; + state_vec_130 = {_RANDOM[6'h17][31], _RANDOM[6'h18][1:0]}; + state_vec_131 = _RANDOM[6'h18][4:2]; + state_vec_132 = _RANDOM[6'h18][7:5]; + state_vec_133 = _RANDOM[6'h18][10:8]; + state_vec_134 = _RANDOM[6'h18][13:11]; + state_vec_135 = _RANDOM[6'h18][16:14]; + state_vec_136 = _RANDOM[6'h18][19:17]; + state_vec_137 = _RANDOM[6'h18][22:20]; + state_vec_138 = _RANDOM[6'h18][25:23]; + state_vec_139 = _RANDOM[6'h18][28:26]; + state_vec_140 = _RANDOM[6'h18][31:29]; + state_vec_141 = _RANDOM[6'h19][2:0]; + state_vec_142 = _RANDOM[6'h19][5:3]; + state_vec_143 = _RANDOM[6'h19][8:6]; + state_vec_144 = _RANDOM[6'h19][11:9]; + state_vec_145 = _RANDOM[6'h19][14:12]; + state_vec_146 = _RANDOM[6'h19][17:15]; + state_vec_147 = _RANDOM[6'h19][20:18]; + state_vec_148 = _RANDOM[6'h19][23:21]; + state_vec_149 = _RANDOM[6'h19][26:24]; + state_vec_150 = _RANDOM[6'h19][29:27]; + state_vec_151 = {_RANDOM[6'h19][31:30], _RANDOM[6'h1A][0]}; + state_vec_152 = _RANDOM[6'h1A][3:1]; + state_vec_153 = _RANDOM[6'h1A][6:4]; + state_vec_154 = _RANDOM[6'h1A][9:7]; + state_vec_155 = _RANDOM[6'h1A][12:10]; + state_vec_156 = _RANDOM[6'h1A][15:13]; + state_vec_157 = _RANDOM[6'h1A][18:16]; + state_vec_158 = _RANDOM[6'h1A][21:19]; + state_vec_159 = _RANDOM[6'h1A][24:22]; + state_vec_160 = _RANDOM[6'h1A][27:25]; + state_vec_161 = _RANDOM[6'h1A][30:28]; + state_vec_162 = {_RANDOM[6'h1A][31], _RANDOM[6'h1B][1:0]}; + state_vec_163 = _RANDOM[6'h1B][4:2]; + state_vec_164 = _RANDOM[6'h1B][7:5]; + state_vec_165 = _RANDOM[6'h1B][10:8]; + state_vec_166 = _RANDOM[6'h1B][13:11]; + state_vec_167 = _RANDOM[6'h1B][16:14]; + state_vec_168 = _RANDOM[6'h1B][19:17]; + state_vec_169 = _RANDOM[6'h1B][22:20]; + state_vec_170 = _RANDOM[6'h1B][25:23]; + state_vec_171 = _RANDOM[6'h1B][28:26]; + state_vec_172 = _RANDOM[6'h1B][31:29]; + state_vec_173 = _RANDOM[6'h1C][2:0]; + state_vec_174 = _RANDOM[6'h1C][5:3]; + state_vec_175 = _RANDOM[6'h1C][8:6]; + state_vec_176 = _RANDOM[6'h1C][11:9]; + state_vec_177 = _RANDOM[6'h1C][14:12]; + state_vec_178 = _RANDOM[6'h1C][17:15]; + state_vec_179 = _RANDOM[6'h1C][20:18]; + state_vec_180 = _RANDOM[6'h1C][23:21]; + state_vec_181 = _RANDOM[6'h1C][26:24]; + state_vec_182 = _RANDOM[6'h1C][29:27]; + state_vec_183 = {_RANDOM[6'h1C][31:30], _RANDOM[6'h1D][0]}; + state_vec_184 = _RANDOM[6'h1D][3:1]; + state_vec_185 = _RANDOM[6'h1D][6:4]; + state_vec_186 = _RANDOM[6'h1D][9:7]; + state_vec_187 = _RANDOM[6'h1D][12:10]; + state_vec_188 = _RANDOM[6'h1D][15:13]; + state_vec_189 = _RANDOM[6'h1D][18:16]; + state_vec_190 = _RANDOM[6'h1D][21:19]; + state_vec_191 = _RANDOM[6'h1D][24:22]; + state_vec_192 = _RANDOM[6'h1D][27:25]; + state_vec_193 = _RANDOM[6'h1D][30:28]; + state_vec_194 = {_RANDOM[6'h1D][31], _RANDOM[6'h1E][1:0]}; + state_vec_195 = _RANDOM[6'h1E][4:2]; + state_vec_196 = _RANDOM[6'h1E][7:5]; + state_vec_197 = _RANDOM[6'h1E][10:8]; + state_vec_198 = _RANDOM[6'h1E][13:11]; + state_vec_199 = _RANDOM[6'h1E][16:14]; + state_vec_200 = _RANDOM[6'h1E][19:17]; + state_vec_201 = _RANDOM[6'h1E][22:20]; + state_vec_202 = _RANDOM[6'h1E][25:23]; + state_vec_203 = _RANDOM[6'h1E][28:26]; + state_vec_204 = _RANDOM[6'h1E][31:29]; + state_vec_205 = _RANDOM[6'h1F][2:0]; + state_vec_206 = _RANDOM[6'h1F][5:3]; + state_vec_207 = _RANDOM[6'h1F][8:6]; + state_vec_208 = _RANDOM[6'h1F][11:9]; + state_vec_209 = _RANDOM[6'h1F][14:12]; + state_vec_210 = _RANDOM[6'h1F][17:15]; + state_vec_211 = _RANDOM[6'h1F][20:18]; + state_vec_212 = _RANDOM[6'h1F][23:21]; + state_vec_213 = _RANDOM[6'h1F][26:24]; + state_vec_214 = _RANDOM[6'h1F][29:27]; + state_vec_215 = {_RANDOM[6'h1F][31:30], _RANDOM[6'h20][0]}; + state_vec_216 = _RANDOM[6'h20][3:1]; + state_vec_217 = _RANDOM[6'h20][6:4]; + state_vec_218 = _RANDOM[6'h20][9:7]; + state_vec_219 = _RANDOM[6'h20][12:10]; + state_vec_220 = _RANDOM[6'h20][15:13]; + state_vec_221 = _RANDOM[6'h20][18:16]; + state_vec_222 = _RANDOM[6'h20][21:19]; + state_vec_223 = _RANDOM[6'h20][24:22]; + state_vec_224 = _RANDOM[6'h20][27:25]; + state_vec_225 = _RANDOM[6'h20][30:28]; + state_vec_226 = {_RANDOM[6'h20][31], _RANDOM[6'h21][1:0]}; + state_vec_227 = _RANDOM[6'h21][4:2]; + state_vec_228 = _RANDOM[6'h21][7:5]; + state_vec_229 = _RANDOM[6'h21][10:8]; + state_vec_230 = _RANDOM[6'h21][13:11]; + state_vec_231 = _RANDOM[6'h21][16:14]; + state_vec_232 = _RANDOM[6'h21][19:17]; + state_vec_233 = _RANDOM[6'h21][22:20]; + state_vec_234 = _RANDOM[6'h21][25:23]; + state_vec_235 = _RANDOM[6'h21][28:26]; + state_vec_236 = _RANDOM[6'h21][31:29]; + state_vec_237 = _RANDOM[6'h22][2:0]; + state_vec_238 = _RANDOM[6'h22][5:3]; + state_vec_239 = _RANDOM[6'h22][8:6]; + state_vec_240 = _RANDOM[6'h22][11:9]; + state_vec_241 = _RANDOM[6'h22][14:12]; + state_vec_242 = _RANDOM[6'h22][17:15]; + state_vec_243 = _RANDOM[6'h22][20:18]; + state_vec_244 = _RANDOM[6'h22][23:21]; + state_vec_245 = _RANDOM[6'h22][26:24]; + state_vec_246 = _RANDOM[6'h22][29:27]; + state_vec_247 = {_RANDOM[6'h22][31:30], _RANDOM[6'h23][0]}; + state_vec_248 = _RANDOM[6'h23][3:1]; + state_vec_249 = _RANDOM[6'h23][6:4]; + state_vec_250 = _RANDOM[6'h23][9:7]; + state_vec_251 = _RANDOM[6'h23][12:10]; + state_vec_252 = _RANDOM[6'h23][15:13]; + state_vec_253 = _RANDOM[6'h23][18:16]; + state_vec_254 = _RANDOM[6'h23][21:19]; + state_vec_255 = _RANDOM[6'h23][24:22]; + state_vec_256 = _RANDOM[6'h23][27:25]; + state_vec_257 = _RANDOM[6'h23][30:28]; + state_vec_258 = {_RANDOM[6'h23][31], _RANDOM[6'h24][1:0]}; + state_vec_259 = _RANDOM[6'h24][4:2]; + state_vec_260 = _RANDOM[6'h24][7:5]; + state_vec_261 = _RANDOM[6'h24][10:8]; + state_vec_262 = _RANDOM[6'h24][13:11]; + state_vec_263 = _RANDOM[6'h24][16:14]; + state_vec_264 = _RANDOM[6'h24][19:17]; + state_vec_265 = _RANDOM[6'h24][22:20]; + state_vec_266 = _RANDOM[6'h24][25:23]; + state_vec_267 = _RANDOM[6'h24][28:26]; + state_vec_268 = _RANDOM[6'h24][31:29]; + state_vec_269 = _RANDOM[6'h25][2:0]; + state_vec_270 = _RANDOM[6'h25][5:3]; + state_vec_271 = _RANDOM[6'h25][8:6]; + state_vec_272 = _RANDOM[6'h25][11:9]; + state_vec_273 = _RANDOM[6'h25][14:12]; + state_vec_274 = _RANDOM[6'h25][17:15]; + state_vec_275 = _RANDOM[6'h25][20:18]; + state_vec_276 = _RANDOM[6'h25][23:21]; + state_vec_277 = _RANDOM[6'h25][26:24]; + state_vec_278 = _RANDOM[6'h25][29:27]; + state_vec_279 = {_RANDOM[6'h25][31:30], _RANDOM[6'h26][0]}; + state_vec_280 = _RANDOM[6'h26][3:1]; + state_vec_281 = _RANDOM[6'h26][6:4]; + state_vec_282 = _RANDOM[6'h26][9:7]; + state_vec_283 = _RANDOM[6'h26][12:10]; + state_vec_284 = _RANDOM[6'h26][15:13]; + state_vec_285 = _RANDOM[6'h26][18:16]; + state_vec_286 = _RANDOM[6'h26][21:19]; + state_vec_287 = _RANDOM[6'h26][24:22]; + state_vec_288 = _RANDOM[6'h26][27:25]; + state_vec_289 = _RANDOM[6'h26][30:28]; + state_vec_290 = {_RANDOM[6'h26][31], _RANDOM[6'h27][1:0]}; + state_vec_291 = _RANDOM[6'h27][4:2]; + state_vec_292 = _RANDOM[6'h27][7:5]; + state_vec_293 = _RANDOM[6'h27][10:8]; + state_vec_294 = _RANDOM[6'h27][13:11]; + state_vec_295 = _RANDOM[6'h27][16:14]; + state_vec_296 = _RANDOM[6'h27][19:17]; + state_vec_297 = _RANDOM[6'h27][22:20]; + state_vec_298 = _RANDOM[6'h27][25:23]; + state_vec_299 = _RANDOM[6'h27][28:26]; + state_vec_300 = _RANDOM[6'h27][31:29]; + state_vec_301 = _RANDOM[6'h28][2:0]; + state_vec_302 = _RANDOM[6'h28][5:3]; + state_vec_303 = _RANDOM[6'h28][8:6]; + state_vec_304 = _RANDOM[6'h28][11:9]; + state_vec_305 = _RANDOM[6'h28][14:12]; + state_vec_306 = _RANDOM[6'h28][17:15]; + state_vec_307 = _RANDOM[6'h28][20:18]; + state_vec_308 = _RANDOM[6'h28][23:21]; + state_vec_309 = _RANDOM[6'h28][26:24]; + state_vec_310 = _RANDOM[6'h28][29:27]; + state_vec_311 = {_RANDOM[6'h28][31:30], _RANDOM[6'h29][0]}; + state_vec_312 = _RANDOM[6'h29][3:1]; + state_vec_313 = _RANDOM[6'h29][6:4]; + state_vec_314 = _RANDOM[6'h29][9:7]; + state_vec_315 = _RANDOM[6'h29][12:10]; + state_vec_316 = _RANDOM[6'h29][15:13]; + state_vec_317 = _RANDOM[6'h29][18:16]; + state_vec_318 = _RANDOM[6'h29][21:19]; + state_vec_319 = _RANDOM[6'h29][24:22]; + state_vec_320 = _RANDOM[6'h29][27:25]; + state_vec_321 = _RANDOM[6'h29][30:28]; + state_vec_322 = {_RANDOM[6'h29][31], _RANDOM[6'h2A][1:0]}; + state_vec_323 = _RANDOM[6'h2A][4:2]; + state_vec_324 = _RANDOM[6'h2A][7:5]; + state_vec_325 = _RANDOM[6'h2A][10:8]; + state_vec_326 = _RANDOM[6'h2A][13:11]; + state_vec_327 = _RANDOM[6'h2A][16:14]; + state_vec_328 = _RANDOM[6'h2A][19:17]; + state_vec_329 = _RANDOM[6'h2A][22:20]; + state_vec_330 = _RANDOM[6'h2A][25:23]; + state_vec_331 = _RANDOM[6'h2A][28:26]; + state_vec_332 = _RANDOM[6'h2A][31:29]; + state_vec_333 = _RANDOM[6'h2B][2:0]; + state_vec_334 = _RANDOM[6'h2B][5:3]; + state_vec_335 = _RANDOM[6'h2B][8:6]; + state_vec_336 = _RANDOM[6'h2B][11:9]; + state_vec_337 = _RANDOM[6'h2B][14:12]; + state_vec_338 = _RANDOM[6'h2B][17:15]; + state_vec_339 = _RANDOM[6'h2B][20:18]; + state_vec_340 = _RANDOM[6'h2B][23:21]; + state_vec_341 = _RANDOM[6'h2B][26:24]; + state_vec_342 = _RANDOM[6'h2B][29:27]; + state_vec_343 = {_RANDOM[6'h2B][31:30], _RANDOM[6'h2C][0]}; + state_vec_344 = _RANDOM[6'h2C][3:1]; + state_vec_345 = _RANDOM[6'h2C][6:4]; + state_vec_346 = _RANDOM[6'h2C][9:7]; + state_vec_347 = _RANDOM[6'h2C][12:10]; + state_vec_348 = _RANDOM[6'h2C][15:13]; + state_vec_349 = _RANDOM[6'h2C][18:16]; + state_vec_350 = _RANDOM[6'h2C][21:19]; + state_vec_351 = _RANDOM[6'h2C][24:22]; + state_vec_352 = _RANDOM[6'h2C][27:25]; + state_vec_353 = _RANDOM[6'h2C][30:28]; + state_vec_354 = {_RANDOM[6'h2C][31], _RANDOM[6'h2D][1:0]}; + state_vec_355 = _RANDOM[6'h2D][4:2]; + state_vec_356 = _RANDOM[6'h2D][7:5]; + state_vec_357 = _RANDOM[6'h2D][10:8]; + state_vec_358 = _RANDOM[6'h2D][13:11]; + state_vec_359 = _RANDOM[6'h2D][16:14]; + state_vec_360 = _RANDOM[6'h2D][19:17]; + state_vec_361 = _RANDOM[6'h2D][22:20]; + state_vec_362 = _RANDOM[6'h2D][25:23]; + state_vec_363 = _RANDOM[6'h2D][28:26]; + state_vec_364 = _RANDOM[6'h2D][31:29]; + state_vec_365 = _RANDOM[6'h2E][2:0]; + state_vec_366 = _RANDOM[6'h2E][5:3]; + state_vec_367 = _RANDOM[6'h2E][8:6]; + state_vec_368 = _RANDOM[6'h2E][11:9]; + state_vec_369 = _RANDOM[6'h2E][14:12]; + state_vec_370 = _RANDOM[6'h2E][17:15]; + state_vec_371 = _RANDOM[6'h2E][20:18]; + state_vec_372 = _RANDOM[6'h2E][23:21]; + state_vec_373 = _RANDOM[6'h2E][26:24]; + state_vec_374 = _RANDOM[6'h2E][29:27]; + state_vec_375 = {_RANDOM[6'h2E][31:30], _RANDOM[6'h2F][0]}; + state_vec_376 = _RANDOM[6'h2F][3:1]; + state_vec_377 = _RANDOM[6'h2F][6:4]; + state_vec_378 = _RANDOM[6'h2F][9:7]; + state_vec_379 = _RANDOM[6'h2F][12:10]; + state_vec_380 = _RANDOM[6'h2F][15:13]; + state_vec_381 = _RANDOM[6'h2F][18:16]; + state_vec_382 = _RANDOM[6'h2F][21:19]; + state_vec_383 = _RANDOM[6'h2F][24:22]; + state_vec_384 = _RANDOM[6'h2F][27:25]; + state_vec_385 = _RANDOM[6'h2F][30:28]; + state_vec_386 = {_RANDOM[6'h2F][31], _RANDOM[6'h30][1:0]}; + state_vec_387 = _RANDOM[6'h30][4:2]; + state_vec_388 = _RANDOM[6'h30][7:5]; + state_vec_389 = _RANDOM[6'h30][10:8]; + state_vec_390 = _RANDOM[6'h30][13:11]; + state_vec_391 = _RANDOM[6'h30][16:14]; + state_vec_392 = _RANDOM[6'h30][19:17]; + state_vec_393 = _RANDOM[6'h30][22:20]; + state_vec_394 = _RANDOM[6'h30][25:23]; + state_vec_395 = _RANDOM[6'h30][28:26]; + state_vec_396 = _RANDOM[6'h30][31:29]; + state_vec_397 = _RANDOM[6'h31][2:0]; + state_vec_398 = _RANDOM[6'h31][5:3]; + state_vec_399 = _RANDOM[6'h31][8:6]; + state_vec_400 = _RANDOM[6'h31][11:9]; + state_vec_401 = _RANDOM[6'h31][14:12]; + state_vec_402 = _RANDOM[6'h31][17:15]; + state_vec_403 = _RANDOM[6'h31][20:18]; + state_vec_404 = _RANDOM[6'h31][23:21]; + state_vec_405 = _RANDOM[6'h31][26:24]; + state_vec_406 = _RANDOM[6'h31][29:27]; + state_vec_407 = {_RANDOM[6'h31][31:30], _RANDOM[6'h32][0]}; + state_vec_408 = _RANDOM[6'h32][3:1]; + state_vec_409 = _RANDOM[6'h32][6:4]; + state_vec_410 = _RANDOM[6'h32][9:7]; + state_vec_411 = _RANDOM[6'h32][12:10]; + state_vec_412 = _RANDOM[6'h32][15:13]; + state_vec_413 = _RANDOM[6'h32][18:16]; + state_vec_414 = _RANDOM[6'h32][21:19]; + state_vec_415 = _RANDOM[6'h32][24:22]; + state_vec_416 = _RANDOM[6'h32][27:25]; + state_vec_417 = _RANDOM[6'h32][30:28]; + state_vec_418 = {_RANDOM[6'h32][31], _RANDOM[6'h33][1:0]}; + state_vec_419 = _RANDOM[6'h33][4:2]; + state_vec_420 = _RANDOM[6'h33][7:5]; + state_vec_421 = _RANDOM[6'h33][10:8]; + state_vec_422 = _RANDOM[6'h33][13:11]; + state_vec_423 = _RANDOM[6'h33][16:14]; + state_vec_424 = _RANDOM[6'h33][19:17]; + state_vec_425 = _RANDOM[6'h33][22:20]; + state_vec_426 = _RANDOM[6'h33][25:23]; + state_vec_427 = _RANDOM[6'h33][28:26]; + state_vec_428 = _RANDOM[6'h33][31:29]; + state_vec_429 = _RANDOM[6'h34][2:0]; + state_vec_430 = _RANDOM[6'h34][5:3]; + state_vec_431 = _RANDOM[6'h34][8:6]; + state_vec_432 = _RANDOM[6'h34][11:9]; + state_vec_433 = _RANDOM[6'h34][14:12]; + state_vec_434 = _RANDOM[6'h34][17:15]; + state_vec_435 = _RANDOM[6'h34][20:18]; + state_vec_436 = _RANDOM[6'h34][23:21]; + state_vec_437 = _RANDOM[6'h34][26:24]; + state_vec_438 = _RANDOM[6'h34][29:27]; + state_vec_439 = {_RANDOM[6'h34][31:30], _RANDOM[6'h35][0]}; + state_vec_440 = _RANDOM[6'h35][3:1]; + state_vec_441 = _RANDOM[6'h35][6:4]; + state_vec_442 = _RANDOM[6'h35][9:7]; + state_vec_443 = _RANDOM[6'h35][12:10]; + state_vec_444 = _RANDOM[6'h35][15:13]; + state_vec_445 = _RANDOM[6'h35][18:16]; + state_vec_446 = _RANDOM[6'h35][21:19]; + state_vec_447 = _RANDOM[6'h35][24:22]; + state_vec_448 = _RANDOM[6'h35][27:25]; + state_vec_449 = _RANDOM[6'h35][30:28]; + state_vec_450 = {_RANDOM[6'h35][31], _RANDOM[6'h36][1:0]}; + state_vec_451 = _RANDOM[6'h36][4:2]; + state_vec_452 = _RANDOM[6'h36][7:5]; + state_vec_453 = _RANDOM[6'h36][10:8]; + state_vec_454 = _RANDOM[6'h36][13:11]; + state_vec_455 = _RANDOM[6'h36][16:14]; + state_vec_456 = _RANDOM[6'h36][19:17]; + state_vec_457 = _RANDOM[6'h36][22:20]; + state_vec_458 = _RANDOM[6'h36][25:23]; + state_vec_459 = _RANDOM[6'h36][28:26]; + state_vec_460 = _RANDOM[6'h36][31:29]; + state_vec_461 = _RANDOM[6'h37][2:0]; + state_vec_462 = _RANDOM[6'h37][5:3]; + state_vec_463 = _RANDOM[6'h37][8:6]; + state_vec_464 = _RANDOM[6'h37][11:9]; + state_vec_465 = _RANDOM[6'h37][14:12]; + state_vec_466 = _RANDOM[6'h37][17:15]; + state_vec_467 = _RANDOM[6'h37][20:18]; + state_vec_468 = _RANDOM[6'h37][23:21]; + state_vec_469 = _RANDOM[6'h37][26:24]; + state_vec_470 = _RANDOM[6'h37][29:27]; + state_vec_471 = {_RANDOM[6'h37][31:30], _RANDOM[6'h38][0]}; + state_vec_472 = _RANDOM[6'h38][3:1]; + state_vec_473 = _RANDOM[6'h38][6:4]; + state_vec_474 = _RANDOM[6'h38][9:7]; + state_vec_475 = _RANDOM[6'h38][12:10]; + state_vec_476 = _RANDOM[6'h38][15:13]; + state_vec_477 = _RANDOM[6'h38][18:16]; + state_vec_478 = _RANDOM[6'h38][21:19]; + state_vec_479 = _RANDOM[6'h38][24:22]; + state_vec_480 = _RANDOM[6'h38][27:25]; + state_vec_481 = _RANDOM[6'h38][30:28]; + state_vec_482 = {_RANDOM[6'h38][31], _RANDOM[6'h39][1:0]}; + state_vec_483 = _RANDOM[6'h39][4:2]; + state_vec_484 = _RANDOM[6'h39][7:5]; + state_vec_485 = _RANDOM[6'h39][10:8]; + state_vec_486 = _RANDOM[6'h39][13:11]; + state_vec_487 = _RANDOM[6'h39][16:14]; + state_vec_488 = _RANDOM[6'h39][19:17]; + state_vec_489 = _RANDOM[6'h39][22:20]; + state_vec_490 = _RANDOM[6'h39][25:23]; + state_vec_491 = _RANDOM[6'h39][28:26]; + state_vec_492 = _RANDOM[6'h39][31:29]; + state_vec_493 = _RANDOM[6'h3A][2:0]; + state_vec_494 = _RANDOM[6'h3A][5:3]; + state_vec_495 = _RANDOM[6'h3A][8:6]; + state_vec_496 = _RANDOM[6'h3A][11:9]; + state_vec_497 = _RANDOM[6'h3A][14:12]; + state_vec_498 = _RANDOM[6'h3A][17:15]; + state_vec_499 = _RANDOM[6'h3A][20:18]; + state_vec_500 = _RANDOM[6'h3A][23:21]; + state_vec_501 = _RANDOM[6'h3A][26:24]; + state_vec_502 = _RANDOM[6'h3A][29:27]; + state_vec_503 = {_RANDOM[6'h3A][31:30], _RANDOM[6'h3B][0]}; + state_vec_504 = _RANDOM[6'h3B][3:1]; + state_vec_505 = _RANDOM[6'h3B][6:4]; + state_vec_506 = _RANDOM[6'h3B][9:7]; + state_vec_507 = _RANDOM[6'h3B][12:10]; + state_vec_508 = _RANDOM[6'h3B][15:13]; + state_vec_509 = _RANDOM[6'h3B][18:16]; + state_vec_510 = _RANDOM[6'h3B][21:19]; + state_vec_511 = _RANDOM[6'h3B][24:22]; + touch_set_0_REG = {_RANDOM[6'h3B][31:25], _RANDOM[6'h3C][1:0]}; + touch_way_0_valid_REG = _RANDOM[6'h3C][2]; + touch_way_0_bits_REG = _RANDOM[6'h3C][4:3]; + allocWriteWay_REG_0 = _RANDOM[6'h3C][5]; + allocWriteWay_REG_1 = _RANDOM[6'h3C][6]; + allocWriteWay_REG_2 = _RANDOM[6'h3C][7]; + allocWriteWay_REG_3 = _RANDOM[6'h3C][8]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + state_vec_0 = 3'h0; + state_vec_1 = 3'h0; + state_vec_2 = 3'h0; + state_vec_3 = 3'h0; + state_vec_4 = 3'h0; + state_vec_5 = 3'h0; + state_vec_6 = 3'h0; + state_vec_7 = 3'h0; + state_vec_8 = 3'h0; + state_vec_9 = 3'h0; + state_vec_10 = 3'h0; + state_vec_11 = 3'h0; + state_vec_12 = 3'h0; + state_vec_13 = 3'h0; + state_vec_14 = 3'h0; + state_vec_15 = 3'h0; + state_vec_16 = 3'h0; + state_vec_17 = 3'h0; + state_vec_18 = 3'h0; + state_vec_19 = 3'h0; + state_vec_20 = 3'h0; + state_vec_21 = 3'h0; + state_vec_22 = 3'h0; + state_vec_23 = 3'h0; + state_vec_24 = 3'h0; + state_vec_25 = 3'h0; + state_vec_26 = 3'h0; + state_vec_27 = 3'h0; + state_vec_28 = 3'h0; + state_vec_29 = 3'h0; + state_vec_30 = 3'h0; + state_vec_31 = 3'h0; + state_vec_32 = 3'h0; + state_vec_33 = 3'h0; + state_vec_34 = 3'h0; + state_vec_35 = 3'h0; + state_vec_36 = 3'h0; + state_vec_37 = 3'h0; + state_vec_38 = 3'h0; + state_vec_39 = 3'h0; + state_vec_40 = 3'h0; + state_vec_41 = 3'h0; + state_vec_42 = 3'h0; + state_vec_43 = 3'h0; + state_vec_44 = 3'h0; + state_vec_45 = 3'h0; + state_vec_46 = 3'h0; + state_vec_47 = 3'h0; + state_vec_48 = 3'h0; + state_vec_49 = 3'h0; + state_vec_50 = 3'h0; + state_vec_51 = 3'h0; + state_vec_52 = 3'h0; + state_vec_53 = 3'h0; + state_vec_54 = 3'h0; + state_vec_55 = 3'h0; + state_vec_56 = 3'h0; + state_vec_57 = 3'h0; + state_vec_58 = 3'h0; + state_vec_59 = 3'h0; + state_vec_60 = 3'h0; + state_vec_61 = 3'h0; + state_vec_62 = 3'h0; + state_vec_63 = 3'h0; + state_vec_64 = 3'h0; + state_vec_65 = 3'h0; + state_vec_66 = 3'h0; + state_vec_67 = 3'h0; + state_vec_68 = 3'h0; + state_vec_69 = 3'h0; + state_vec_70 = 3'h0; + state_vec_71 = 3'h0; + state_vec_72 = 3'h0; + state_vec_73 = 3'h0; + state_vec_74 = 3'h0; + state_vec_75 = 3'h0; + state_vec_76 = 3'h0; + state_vec_77 = 3'h0; + state_vec_78 = 3'h0; + state_vec_79 = 3'h0; + state_vec_80 = 3'h0; + state_vec_81 = 3'h0; + state_vec_82 = 3'h0; + state_vec_83 = 3'h0; + state_vec_84 = 3'h0; + state_vec_85 = 3'h0; + state_vec_86 = 3'h0; + state_vec_87 = 3'h0; + state_vec_88 = 3'h0; + state_vec_89 = 3'h0; + state_vec_90 = 3'h0; + state_vec_91 = 3'h0; + state_vec_92 = 3'h0; + state_vec_93 = 3'h0; + state_vec_94 = 3'h0; + state_vec_95 = 3'h0; + state_vec_96 = 3'h0; + state_vec_97 = 3'h0; + state_vec_98 = 3'h0; + state_vec_99 = 3'h0; + state_vec_100 = 3'h0; + state_vec_101 = 3'h0; + state_vec_102 = 3'h0; + state_vec_103 = 3'h0; + state_vec_104 = 3'h0; + state_vec_105 = 3'h0; + state_vec_106 = 3'h0; + state_vec_107 = 3'h0; + state_vec_108 = 3'h0; + state_vec_109 = 3'h0; + state_vec_110 = 3'h0; + state_vec_111 = 3'h0; + state_vec_112 = 3'h0; + state_vec_113 = 3'h0; + state_vec_114 = 3'h0; + state_vec_115 = 3'h0; + state_vec_116 = 3'h0; + state_vec_117 = 3'h0; + state_vec_118 = 3'h0; + state_vec_119 = 3'h0; + state_vec_120 = 3'h0; + state_vec_121 = 3'h0; + state_vec_122 = 3'h0; + state_vec_123 = 3'h0; + state_vec_124 = 3'h0; + state_vec_125 = 3'h0; + state_vec_126 = 3'h0; + state_vec_127 = 3'h0; + state_vec_128 = 3'h0; + state_vec_129 = 3'h0; + state_vec_130 = 3'h0; + state_vec_131 = 3'h0; + state_vec_132 = 3'h0; + state_vec_133 = 3'h0; + state_vec_134 = 3'h0; + state_vec_135 = 3'h0; + state_vec_136 = 3'h0; + state_vec_137 = 3'h0; + state_vec_138 = 3'h0; + state_vec_139 = 3'h0; + state_vec_140 = 3'h0; + state_vec_141 = 3'h0; + state_vec_142 = 3'h0; + state_vec_143 = 3'h0; + state_vec_144 = 3'h0; + state_vec_145 = 3'h0; + state_vec_146 = 3'h0; + state_vec_147 = 3'h0; + state_vec_148 = 3'h0; + state_vec_149 = 3'h0; + state_vec_150 = 3'h0; + state_vec_151 = 3'h0; + state_vec_152 = 3'h0; + state_vec_153 = 3'h0; + state_vec_154 = 3'h0; + state_vec_155 = 3'h0; + state_vec_156 = 3'h0; + state_vec_157 = 3'h0; + state_vec_158 = 3'h0; + state_vec_159 = 3'h0; + state_vec_160 = 3'h0; + state_vec_161 = 3'h0; + state_vec_162 = 3'h0; + state_vec_163 = 3'h0; + state_vec_164 = 3'h0; + state_vec_165 = 3'h0; + state_vec_166 = 3'h0; + state_vec_167 = 3'h0; + state_vec_168 = 3'h0; + state_vec_169 = 3'h0; + state_vec_170 = 3'h0; + state_vec_171 = 3'h0; + state_vec_172 = 3'h0; + state_vec_173 = 3'h0; + state_vec_174 = 3'h0; + state_vec_175 = 3'h0; + state_vec_176 = 3'h0; + state_vec_177 = 3'h0; + state_vec_178 = 3'h0; + state_vec_179 = 3'h0; + state_vec_180 = 3'h0; + state_vec_181 = 3'h0; + state_vec_182 = 3'h0; + state_vec_183 = 3'h0; + state_vec_184 = 3'h0; + state_vec_185 = 3'h0; + state_vec_186 = 3'h0; + state_vec_187 = 3'h0; + state_vec_188 = 3'h0; + state_vec_189 = 3'h0; + state_vec_190 = 3'h0; + state_vec_191 = 3'h0; + state_vec_192 = 3'h0; + state_vec_193 = 3'h0; + state_vec_194 = 3'h0; + state_vec_195 = 3'h0; + state_vec_196 = 3'h0; + state_vec_197 = 3'h0; + state_vec_198 = 3'h0; + state_vec_199 = 3'h0; + state_vec_200 = 3'h0; + state_vec_201 = 3'h0; + state_vec_202 = 3'h0; + state_vec_203 = 3'h0; + state_vec_204 = 3'h0; + state_vec_205 = 3'h0; + state_vec_206 = 3'h0; + state_vec_207 = 3'h0; + state_vec_208 = 3'h0; + state_vec_209 = 3'h0; + state_vec_210 = 3'h0; + state_vec_211 = 3'h0; + state_vec_212 = 3'h0; + state_vec_213 = 3'h0; + state_vec_214 = 3'h0; + state_vec_215 = 3'h0; + state_vec_216 = 3'h0; + state_vec_217 = 3'h0; + state_vec_218 = 3'h0; + state_vec_219 = 3'h0; + state_vec_220 = 3'h0; + state_vec_221 = 3'h0; + state_vec_222 = 3'h0; + state_vec_223 = 3'h0; + state_vec_224 = 3'h0; + state_vec_225 = 3'h0; + state_vec_226 = 3'h0; + state_vec_227 = 3'h0; + state_vec_228 = 3'h0; + state_vec_229 = 3'h0; + state_vec_230 = 3'h0; + state_vec_231 = 3'h0; + state_vec_232 = 3'h0; + state_vec_233 = 3'h0; + state_vec_234 = 3'h0; + state_vec_235 = 3'h0; + state_vec_236 = 3'h0; + state_vec_237 = 3'h0; + state_vec_238 = 3'h0; + state_vec_239 = 3'h0; + state_vec_240 = 3'h0; + state_vec_241 = 3'h0; + state_vec_242 = 3'h0; + state_vec_243 = 3'h0; + state_vec_244 = 3'h0; + state_vec_245 = 3'h0; + state_vec_246 = 3'h0; + state_vec_247 = 3'h0; + state_vec_248 = 3'h0; + state_vec_249 = 3'h0; + state_vec_250 = 3'h0; + state_vec_251 = 3'h0; + state_vec_252 = 3'h0; + state_vec_253 = 3'h0; + state_vec_254 = 3'h0; + state_vec_255 = 3'h0; + state_vec_256 = 3'h0; + state_vec_257 = 3'h0; + state_vec_258 = 3'h0; + state_vec_259 = 3'h0; + state_vec_260 = 3'h0; + state_vec_261 = 3'h0; + state_vec_262 = 3'h0; + state_vec_263 = 3'h0; + state_vec_264 = 3'h0; + state_vec_265 = 3'h0; + state_vec_266 = 3'h0; + state_vec_267 = 3'h0; + state_vec_268 = 3'h0; + state_vec_269 = 3'h0; + state_vec_270 = 3'h0; + state_vec_271 = 3'h0; + state_vec_272 = 3'h0; + state_vec_273 = 3'h0; + state_vec_274 = 3'h0; + state_vec_275 = 3'h0; + state_vec_276 = 3'h0; + state_vec_277 = 3'h0; + state_vec_278 = 3'h0; + state_vec_279 = 3'h0; + state_vec_280 = 3'h0; + state_vec_281 = 3'h0; + state_vec_282 = 3'h0; + state_vec_283 = 3'h0; + state_vec_284 = 3'h0; + state_vec_285 = 3'h0; + state_vec_286 = 3'h0; + state_vec_287 = 3'h0; + state_vec_288 = 3'h0; + state_vec_289 = 3'h0; + state_vec_290 = 3'h0; + state_vec_291 = 3'h0; + state_vec_292 = 3'h0; + state_vec_293 = 3'h0; + state_vec_294 = 3'h0; + state_vec_295 = 3'h0; + state_vec_296 = 3'h0; + state_vec_297 = 3'h0; + state_vec_298 = 3'h0; + state_vec_299 = 3'h0; + state_vec_300 = 3'h0; + state_vec_301 = 3'h0; + state_vec_302 = 3'h0; + state_vec_303 = 3'h0; + state_vec_304 = 3'h0; + state_vec_305 = 3'h0; + state_vec_306 = 3'h0; + state_vec_307 = 3'h0; + state_vec_308 = 3'h0; + state_vec_309 = 3'h0; + state_vec_310 = 3'h0; + state_vec_311 = 3'h0; + state_vec_312 = 3'h0; + state_vec_313 = 3'h0; + state_vec_314 = 3'h0; + state_vec_315 = 3'h0; + state_vec_316 = 3'h0; + state_vec_317 = 3'h0; + state_vec_318 = 3'h0; + state_vec_319 = 3'h0; + state_vec_320 = 3'h0; + state_vec_321 = 3'h0; + state_vec_322 = 3'h0; + state_vec_323 = 3'h0; + state_vec_324 = 3'h0; + state_vec_325 = 3'h0; + state_vec_326 = 3'h0; + state_vec_327 = 3'h0; + state_vec_328 = 3'h0; + state_vec_329 = 3'h0; + state_vec_330 = 3'h0; + state_vec_331 = 3'h0; + state_vec_332 = 3'h0; + state_vec_333 = 3'h0; + state_vec_334 = 3'h0; + state_vec_335 = 3'h0; + state_vec_336 = 3'h0; + state_vec_337 = 3'h0; + state_vec_338 = 3'h0; + state_vec_339 = 3'h0; + state_vec_340 = 3'h0; + state_vec_341 = 3'h0; + state_vec_342 = 3'h0; + state_vec_343 = 3'h0; + state_vec_344 = 3'h0; + state_vec_345 = 3'h0; + state_vec_346 = 3'h0; + state_vec_347 = 3'h0; + state_vec_348 = 3'h0; + state_vec_349 = 3'h0; + state_vec_350 = 3'h0; + state_vec_351 = 3'h0; + state_vec_352 = 3'h0; + state_vec_353 = 3'h0; + state_vec_354 = 3'h0; + state_vec_355 = 3'h0; + state_vec_356 = 3'h0; + state_vec_357 = 3'h0; + state_vec_358 = 3'h0; + state_vec_359 = 3'h0; + state_vec_360 = 3'h0; + state_vec_361 = 3'h0; + state_vec_362 = 3'h0; + state_vec_363 = 3'h0; + state_vec_364 = 3'h0; + state_vec_365 = 3'h0; + state_vec_366 = 3'h0; + state_vec_367 = 3'h0; + state_vec_368 = 3'h0; + state_vec_369 = 3'h0; + state_vec_370 = 3'h0; + state_vec_371 = 3'h0; + state_vec_372 = 3'h0; + state_vec_373 = 3'h0; + state_vec_374 = 3'h0; + state_vec_375 = 3'h0; + state_vec_376 = 3'h0; + state_vec_377 = 3'h0; + state_vec_378 = 3'h0; + state_vec_379 = 3'h0; + state_vec_380 = 3'h0; + state_vec_381 = 3'h0; + state_vec_382 = 3'h0; + state_vec_383 = 3'h0; + state_vec_384 = 3'h0; + state_vec_385 = 3'h0; + state_vec_386 = 3'h0; + state_vec_387 = 3'h0; + state_vec_388 = 3'h0; + state_vec_389 = 3'h0; + state_vec_390 = 3'h0; + state_vec_391 = 3'h0; + state_vec_392 = 3'h0; + state_vec_393 = 3'h0; + state_vec_394 = 3'h0; + state_vec_395 = 3'h0; + state_vec_396 = 3'h0; + state_vec_397 = 3'h0; + state_vec_398 = 3'h0; + state_vec_399 = 3'h0; + state_vec_400 = 3'h0; + state_vec_401 = 3'h0; + state_vec_402 = 3'h0; + state_vec_403 = 3'h0; + state_vec_404 = 3'h0; + state_vec_405 = 3'h0; + state_vec_406 = 3'h0; + state_vec_407 = 3'h0; + state_vec_408 = 3'h0; + state_vec_409 = 3'h0; + state_vec_410 = 3'h0; + state_vec_411 = 3'h0; + state_vec_412 = 3'h0; + state_vec_413 = 3'h0; + state_vec_414 = 3'h0; + state_vec_415 = 3'h0; + state_vec_416 = 3'h0; + state_vec_417 = 3'h0; + state_vec_418 = 3'h0; + state_vec_419 = 3'h0; + state_vec_420 = 3'h0; + state_vec_421 = 3'h0; + state_vec_422 = 3'h0; + state_vec_423 = 3'h0; + state_vec_424 = 3'h0; + state_vec_425 = 3'h0; + state_vec_426 = 3'h0; + state_vec_427 = 3'h0; + state_vec_428 = 3'h0; + state_vec_429 = 3'h0; + state_vec_430 = 3'h0; + state_vec_431 = 3'h0; + state_vec_432 = 3'h0; + state_vec_433 = 3'h0; + state_vec_434 = 3'h0; + state_vec_435 = 3'h0; + state_vec_436 = 3'h0; + state_vec_437 = 3'h0; + state_vec_438 = 3'h0; + state_vec_439 = 3'h0; + state_vec_440 = 3'h0; + state_vec_441 = 3'h0; + state_vec_442 = 3'h0; + state_vec_443 = 3'h0; + state_vec_444 = 3'h0; + state_vec_445 = 3'h0; + state_vec_446 = 3'h0; + state_vec_447 = 3'h0; + state_vec_448 = 3'h0; + state_vec_449 = 3'h0; + state_vec_450 = 3'h0; + state_vec_451 = 3'h0; + state_vec_452 = 3'h0; + state_vec_453 = 3'h0; + state_vec_454 = 3'h0; + state_vec_455 = 3'h0; + state_vec_456 = 3'h0; + state_vec_457 = 3'h0; + state_vec_458 = 3'h0; + state_vec_459 = 3'h0; + state_vec_460 = 3'h0; + state_vec_461 = 3'h0; + state_vec_462 = 3'h0; + state_vec_463 = 3'h0; + state_vec_464 = 3'h0; + state_vec_465 = 3'h0; + state_vec_466 = 3'h0; + state_vec_467 = 3'h0; + state_vec_468 = 3'h0; + state_vec_469 = 3'h0; + state_vec_470 = 3'h0; + state_vec_471 = 3'h0; + state_vec_472 = 3'h0; + state_vec_473 = 3'h0; + state_vec_474 = 3'h0; + state_vec_475 = 3'h0; + state_vec_476 = 3'h0; + state_vec_477 = 3'h0; + state_vec_478 = 3'h0; + state_vec_479 = 3'h0; + state_vec_480 = 3'h0; + state_vec_481 = 3'h0; + state_vec_482 = 3'h0; + state_vec_483 = 3'h0; + state_vec_484 = 3'h0; + state_vec_485 = 3'h0; + state_vec_486 = 3'h0; + state_vec_487 = 3'h0; + state_vec_488 = 3'h0; + state_vec_489 = 3'h0; + state_vec_490 = 3'h0; + state_vec_491 = 3'h0; + state_vec_492 = 3'h0; + state_vec_493 = 3'h0; + state_vec_494 = 3'h0; + state_vec_495 = 3'h0; + state_vec_496 = 3'h0; + state_vec_497 = 3'h0; + state_vec_498 = 3'h0; + state_vec_499 = 3'h0; + state_vec_500 = 3'h0; + state_vec_501 = 3'h0; + state_vec_502 = 3'h0; + state_vec_503 = 3'h0; + state_vec_504 = 3'h0; + state_vec_505 = 3'h0; + state_vec_506 = 3'h0; + state_vec_507 = 3'h0; + state_vec_508 = 3'h0; + state_vec_509 = 3'h0; + state_vec_510 = 3'h0; + state_vec_511 = 3'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_13 ftb ( + .clock (clock), + .reset (reset), + .io_r_req_ready (io_req_pc_ready), + .io_r_req_valid + (io_req_pc_valid | io_u_req_pc_valid), + .io_r_req_bits_setIdx + (io_u_req_pc_valid ? io_u_req_pc_bits[9:1] : io_req_pc_bits[9:1]), + .io_r_resp_data_0_entry_valid (_ftb_io_r_resp_data_0_entry_valid), + .io_r_resp_data_0_entry_brSlots_0_offset + (_ftb_io_r_resp_data_0_entry_brSlots_0_offset), + .io_r_resp_data_0_entry_brSlots_0_lower + (_ftb_io_r_resp_data_0_entry_brSlots_0_lower), + .io_r_resp_data_0_entry_brSlots_0_tarStat + (_ftb_io_r_resp_data_0_entry_brSlots_0_tarStat), + .io_r_resp_data_0_entry_brSlots_0_sharing + (_ftb_io_r_resp_data_0_entry_brSlots_0_sharing), + .io_r_resp_data_0_entry_brSlots_0_valid + (_ftb_io_r_resp_data_0_entry_brSlots_0_valid), + .io_r_resp_data_0_entry_tailSlot_offset + (_ftb_io_r_resp_data_0_entry_tailSlot_offset), + .io_r_resp_data_0_entry_tailSlot_lower + (_ftb_io_r_resp_data_0_entry_tailSlot_lower), + .io_r_resp_data_0_entry_tailSlot_tarStat + (_ftb_io_r_resp_data_0_entry_tailSlot_tarStat), + .io_r_resp_data_0_entry_tailSlot_sharing + (_ftb_io_r_resp_data_0_entry_tailSlot_sharing), + .io_r_resp_data_0_entry_tailSlot_valid + (_ftb_io_r_resp_data_0_entry_tailSlot_valid), + .io_r_resp_data_0_entry_pftAddr + (_ftb_io_r_resp_data_0_entry_pftAddr), + .io_r_resp_data_0_entry_carry (_ftb_io_r_resp_data_0_entry_carry), + .io_r_resp_data_0_entry_isCall (_ftb_io_r_resp_data_0_entry_isCall), + .io_r_resp_data_0_entry_isRet (_ftb_io_r_resp_data_0_entry_isRet), + .io_r_resp_data_0_entry_isJalr (_ftb_io_r_resp_data_0_entry_isJalr), + .io_r_resp_data_0_entry_last_may_be_rvi_call + (_ftb_io_r_resp_data_0_entry_last_may_be_rvi_call), + .io_r_resp_data_0_entry_always_taken_0 + (_ftb_io_r_resp_data_0_entry_always_taken_0), + .io_r_resp_data_0_entry_always_taken_1 + (_ftb_io_r_resp_data_0_entry_always_taken_1), + .io_r_resp_data_0_tag (_ftb_io_r_resp_data_0_tag), + .io_r_resp_data_1_entry_valid (_ftb_io_r_resp_data_1_entry_valid), + .io_r_resp_data_1_entry_brSlots_0_offset + (_ftb_io_r_resp_data_1_entry_brSlots_0_offset), + .io_r_resp_data_1_entry_brSlots_0_lower + (_ftb_io_r_resp_data_1_entry_brSlots_0_lower), + .io_r_resp_data_1_entry_brSlots_0_tarStat + (_ftb_io_r_resp_data_1_entry_brSlots_0_tarStat), + .io_r_resp_data_1_entry_brSlots_0_sharing + (_ftb_io_r_resp_data_1_entry_brSlots_0_sharing), + .io_r_resp_data_1_entry_brSlots_0_valid + (_ftb_io_r_resp_data_1_entry_brSlots_0_valid), + .io_r_resp_data_1_entry_tailSlot_offset + (_ftb_io_r_resp_data_1_entry_tailSlot_offset), + .io_r_resp_data_1_entry_tailSlot_lower + (_ftb_io_r_resp_data_1_entry_tailSlot_lower), + .io_r_resp_data_1_entry_tailSlot_tarStat + (_ftb_io_r_resp_data_1_entry_tailSlot_tarStat), + .io_r_resp_data_1_entry_tailSlot_sharing + (_ftb_io_r_resp_data_1_entry_tailSlot_sharing), + .io_r_resp_data_1_entry_tailSlot_valid + (_ftb_io_r_resp_data_1_entry_tailSlot_valid), + .io_r_resp_data_1_entry_pftAddr + (_ftb_io_r_resp_data_1_entry_pftAddr), + .io_r_resp_data_1_entry_carry (_ftb_io_r_resp_data_1_entry_carry), + .io_r_resp_data_1_entry_isCall (_ftb_io_r_resp_data_1_entry_isCall), + .io_r_resp_data_1_entry_isRet (_ftb_io_r_resp_data_1_entry_isRet), + .io_r_resp_data_1_entry_isJalr (_ftb_io_r_resp_data_1_entry_isJalr), + .io_r_resp_data_1_entry_last_may_be_rvi_call + (_ftb_io_r_resp_data_1_entry_last_may_be_rvi_call), + .io_r_resp_data_1_entry_always_taken_0 + (_ftb_io_r_resp_data_1_entry_always_taken_0), + .io_r_resp_data_1_entry_always_taken_1 + (_ftb_io_r_resp_data_1_entry_always_taken_1), + .io_r_resp_data_1_tag (_ftb_io_r_resp_data_1_tag), + .io_r_resp_data_2_entry_valid (_ftb_io_r_resp_data_2_entry_valid), + .io_r_resp_data_2_entry_brSlots_0_offset + (_ftb_io_r_resp_data_2_entry_brSlots_0_offset), + .io_r_resp_data_2_entry_brSlots_0_lower + (_ftb_io_r_resp_data_2_entry_brSlots_0_lower), + .io_r_resp_data_2_entry_brSlots_0_tarStat + (_ftb_io_r_resp_data_2_entry_brSlots_0_tarStat), + .io_r_resp_data_2_entry_brSlots_0_sharing + (_ftb_io_r_resp_data_2_entry_brSlots_0_sharing), + .io_r_resp_data_2_entry_brSlots_0_valid + (_ftb_io_r_resp_data_2_entry_brSlots_0_valid), + .io_r_resp_data_2_entry_tailSlot_offset + (_ftb_io_r_resp_data_2_entry_tailSlot_offset), + .io_r_resp_data_2_entry_tailSlot_lower + (_ftb_io_r_resp_data_2_entry_tailSlot_lower), + .io_r_resp_data_2_entry_tailSlot_tarStat + (_ftb_io_r_resp_data_2_entry_tailSlot_tarStat), + .io_r_resp_data_2_entry_tailSlot_sharing + (_ftb_io_r_resp_data_2_entry_tailSlot_sharing), + .io_r_resp_data_2_entry_tailSlot_valid + (_ftb_io_r_resp_data_2_entry_tailSlot_valid), + .io_r_resp_data_2_entry_pftAddr + (_ftb_io_r_resp_data_2_entry_pftAddr), + .io_r_resp_data_2_entry_carry (_ftb_io_r_resp_data_2_entry_carry), + .io_r_resp_data_2_entry_isCall (_ftb_io_r_resp_data_2_entry_isCall), + .io_r_resp_data_2_entry_isRet (_ftb_io_r_resp_data_2_entry_isRet), + .io_r_resp_data_2_entry_isJalr (_ftb_io_r_resp_data_2_entry_isJalr), + .io_r_resp_data_2_entry_last_may_be_rvi_call + (_ftb_io_r_resp_data_2_entry_last_may_be_rvi_call), + .io_r_resp_data_2_entry_always_taken_0 + (_ftb_io_r_resp_data_2_entry_always_taken_0), + .io_r_resp_data_2_entry_always_taken_1 + (_ftb_io_r_resp_data_2_entry_always_taken_1), + .io_r_resp_data_2_tag (_ftb_io_r_resp_data_2_tag), + .io_r_resp_data_3_entry_valid (_ftb_io_r_resp_data_3_entry_valid), + .io_r_resp_data_3_entry_brSlots_0_offset + (_ftb_io_r_resp_data_3_entry_brSlots_0_offset), + .io_r_resp_data_3_entry_brSlots_0_lower + (_ftb_io_r_resp_data_3_entry_brSlots_0_lower), + .io_r_resp_data_3_entry_brSlots_0_tarStat + (_ftb_io_r_resp_data_3_entry_brSlots_0_tarStat), + .io_r_resp_data_3_entry_brSlots_0_sharing + (_ftb_io_r_resp_data_3_entry_brSlots_0_sharing), + .io_r_resp_data_3_entry_brSlots_0_valid + (_ftb_io_r_resp_data_3_entry_brSlots_0_valid), + .io_r_resp_data_3_entry_tailSlot_offset + (_ftb_io_r_resp_data_3_entry_tailSlot_offset), + .io_r_resp_data_3_entry_tailSlot_lower + (_ftb_io_r_resp_data_3_entry_tailSlot_lower), + .io_r_resp_data_3_entry_tailSlot_tarStat + (_ftb_io_r_resp_data_3_entry_tailSlot_tarStat), + .io_r_resp_data_3_entry_tailSlot_sharing + (_ftb_io_r_resp_data_3_entry_tailSlot_sharing), + .io_r_resp_data_3_entry_tailSlot_valid + (_ftb_io_r_resp_data_3_entry_tailSlot_valid), + .io_r_resp_data_3_entry_pftAddr + (_ftb_io_r_resp_data_3_entry_pftAddr), + .io_r_resp_data_3_entry_carry (_ftb_io_r_resp_data_3_entry_carry), + .io_r_resp_data_3_entry_isCall (_ftb_io_r_resp_data_3_entry_isCall), + .io_r_resp_data_3_entry_isRet (_ftb_io_r_resp_data_3_entry_isRet), + .io_r_resp_data_3_entry_isJalr (_ftb_io_r_resp_data_3_entry_isJalr), + .io_r_resp_data_3_entry_last_may_be_rvi_call + (_ftb_io_r_resp_data_3_entry_last_may_be_rvi_call), + .io_r_resp_data_3_entry_always_taken_0 + (_ftb_io_r_resp_data_3_entry_always_taken_0), + .io_r_resp_data_3_entry_always_taken_1 + (_ftb_io_r_resp_data_3_entry_always_taken_1), + .io_r_resp_data_3_tag (_ftb_io_r_resp_data_3_tag), + .io_w_req_valid (io_update_write_data_valid), + .io_w_req_bits_setIdx (io_update_pc[9:1]), + .io_w_req_bits_data_0_entry_valid + (io_update_write_data_bits_entry_valid), + .io_w_req_bits_data_0_entry_brSlots_0_offset + (io_update_write_data_bits_entry_brSlots_0_offset), + .io_w_req_bits_data_0_entry_brSlots_0_lower + (io_update_write_data_bits_entry_brSlots_0_lower), + .io_w_req_bits_data_0_entry_brSlots_0_tarStat + (io_update_write_data_bits_entry_brSlots_0_tarStat), + .io_w_req_bits_data_0_entry_brSlots_0_sharing + (io_update_write_data_bits_entry_brSlots_0_sharing), + .io_w_req_bits_data_0_entry_brSlots_0_valid + (io_update_write_data_bits_entry_brSlots_0_valid), + .io_w_req_bits_data_0_entry_tailSlot_offset + (io_update_write_data_bits_entry_tailSlot_offset), + .io_w_req_bits_data_0_entry_tailSlot_lower + (io_update_write_data_bits_entry_tailSlot_lower), + .io_w_req_bits_data_0_entry_tailSlot_tarStat + (io_update_write_data_bits_entry_tailSlot_tarStat), + .io_w_req_bits_data_0_entry_tailSlot_sharing + (io_update_write_data_bits_entry_tailSlot_sharing), + .io_w_req_bits_data_0_entry_tailSlot_valid + (io_update_write_data_bits_entry_tailSlot_valid), + .io_w_req_bits_data_0_entry_pftAddr + (io_update_write_data_bits_entry_pftAddr), + .io_w_req_bits_data_0_entry_carry + (io_update_write_data_bits_entry_carry), + .io_w_req_bits_data_0_entry_isCall + (io_update_write_data_bits_entry_isCall), + .io_w_req_bits_data_0_entry_isRet + (io_update_write_data_bits_entry_isRet), + .io_w_req_bits_data_0_entry_isJalr + (io_update_write_data_bits_entry_isJalr), + .io_w_req_bits_data_0_entry_last_may_be_rvi_call + (io_update_write_data_bits_entry_last_may_be_rvi_call), + .io_w_req_bits_data_0_entry_always_taken_0 + (io_update_write_data_bits_entry_always_taken_0), + .io_w_req_bits_data_0_entry_always_taken_1 + (io_update_write_data_bits_entry_always_taken_1), + .io_w_req_bits_data_0_tag (io_update_write_data_bits_tag), + .io_w_req_bits_data_1_entry_valid + (io_update_write_data_bits_entry_valid), + .io_w_req_bits_data_1_entry_brSlots_0_offset + (io_update_write_data_bits_entry_brSlots_0_offset), + .io_w_req_bits_data_1_entry_brSlots_0_lower + (io_update_write_data_bits_entry_brSlots_0_lower), + .io_w_req_bits_data_1_entry_brSlots_0_tarStat + (io_update_write_data_bits_entry_brSlots_0_tarStat), + .io_w_req_bits_data_1_entry_brSlots_0_sharing + (io_update_write_data_bits_entry_brSlots_0_sharing), + .io_w_req_bits_data_1_entry_brSlots_0_valid + (io_update_write_data_bits_entry_brSlots_0_valid), + .io_w_req_bits_data_1_entry_tailSlot_offset + (io_update_write_data_bits_entry_tailSlot_offset), + .io_w_req_bits_data_1_entry_tailSlot_lower + (io_update_write_data_bits_entry_tailSlot_lower), + .io_w_req_bits_data_1_entry_tailSlot_tarStat + (io_update_write_data_bits_entry_tailSlot_tarStat), + .io_w_req_bits_data_1_entry_tailSlot_sharing + (io_update_write_data_bits_entry_tailSlot_sharing), + .io_w_req_bits_data_1_entry_tailSlot_valid + (io_update_write_data_bits_entry_tailSlot_valid), + .io_w_req_bits_data_1_entry_pftAddr + (io_update_write_data_bits_entry_pftAddr), + .io_w_req_bits_data_1_entry_carry + (io_update_write_data_bits_entry_carry), + .io_w_req_bits_data_1_entry_isCall + (io_update_write_data_bits_entry_isCall), + .io_w_req_bits_data_1_entry_isRet + (io_update_write_data_bits_entry_isRet), + .io_w_req_bits_data_1_entry_isJalr + (io_update_write_data_bits_entry_isJalr), + .io_w_req_bits_data_1_entry_last_may_be_rvi_call + (io_update_write_data_bits_entry_last_may_be_rvi_call), + .io_w_req_bits_data_1_entry_always_taken_0 + (io_update_write_data_bits_entry_always_taken_0), + .io_w_req_bits_data_1_entry_always_taken_1 + (io_update_write_data_bits_entry_always_taken_1), + .io_w_req_bits_data_1_tag (io_update_write_data_bits_tag), + .io_w_req_bits_data_2_entry_valid + (io_update_write_data_bits_entry_valid), + .io_w_req_bits_data_2_entry_brSlots_0_offset + (io_update_write_data_bits_entry_brSlots_0_offset), + .io_w_req_bits_data_2_entry_brSlots_0_lower + (io_update_write_data_bits_entry_brSlots_0_lower), + .io_w_req_bits_data_2_entry_brSlots_0_tarStat + (io_update_write_data_bits_entry_brSlots_0_tarStat), + .io_w_req_bits_data_2_entry_brSlots_0_sharing + (io_update_write_data_bits_entry_brSlots_0_sharing), + .io_w_req_bits_data_2_entry_brSlots_0_valid + (io_update_write_data_bits_entry_brSlots_0_valid), + .io_w_req_bits_data_2_entry_tailSlot_offset + (io_update_write_data_bits_entry_tailSlot_offset), + .io_w_req_bits_data_2_entry_tailSlot_lower + (io_update_write_data_bits_entry_tailSlot_lower), + .io_w_req_bits_data_2_entry_tailSlot_tarStat + (io_update_write_data_bits_entry_tailSlot_tarStat), + .io_w_req_bits_data_2_entry_tailSlot_sharing + (io_update_write_data_bits_entry_tailSlot_sharing), + .io_w_req_bits_data_2_entry_tailSlot_valid + (io_update_write_data_bits_entry_tailSlot_valid), + .io_w_req_bits_data_2_entry_pftAddr + (io_update_write_data_bits_entry_pftAddr), + .io_w_req_bits_data_2_entry_carry + (io_update_write_data_bits_entry_carry), + .io_w_req_bits_data_2_entry_isCall + (io_update_write_data_bits_entry_isCall), + .io_w_req_bits_data_2_entry_isRet + (io_update_write_data_bits_entry_isRet), + .io_w_req_bits_data_2_entry_isJalr + (io_update_write_data_bits_entry_isJalr), + .io_w_req_bits_data_2_entry_last_may_be_rvi_call + (io_update_write_data_bits_entry_last_may_be_rvi_call), + .io_w_req_bits_data_2_entry_always_taken_0 + (io_update_write_data_bits_entry_always_taken_0), + .io_w_req_bits_data_2_entry_always_taken_1 + (io_update_write_data_bits_entry_always_taken_1), + .io_w_req_bits_data_2_tag (io_update_write_data_bits_tag), + .io_w_req_bits_data_3_entry_valid + (io_update_write_data_bits_entry_valid), + .io_w_req_bits_data_3_entry_brSlots_0_offset + (io_update_write_data_bits_entry_brSlots_0_offset), + .io_w_req_bits_data_3_entry_brSlots_0_lower + (io_update_write_data_bits_entry_brSlots_0_lower), + .io_w_req_bits_data_3_entry_brSlots_0_tarStat + (io_update_write_data_bits_entry_brSlots_0_tarStat), + .io_w_req_bits_data_3_entry_brSlots_0_sharing + (io_update_write_data_bits_entry_brSlots_0_sharing), + .io_w_req_bits_data_3_entry_brSlots_0_valid + (io_update_write_data_bits_entry_brSlots_0_valid), + .io_w_req_bits_data_3_entry_tailSlot_offset + (io_update_write_data_bits_entry_tailSlot_offset), + .io_w_req_bits_data_3_entry_tailSlot_lower + (io_update_write_data_bits_entry_tailSlot_lower), + .io_w_req_bits_data_3_entry_tailSlot_tarStat + (io_update_write_data_bits_entry_tailSlot_tarStat), + .io_w_req_bits_data_3_entry_tailSlot_sharing + (io_update_write_data_bits_entry_tailSlot_sharing), + .io_w_req_bits_data_3_entry_tailSlot_valid + (io_update_write_data_bits_entry_tailSlot_valid), + .io_w_req_bits_data_3_entry_pftAddr + (io_update_write_data_bits_entry_pftAddr), + .io_w_req_bits_data_3_entry_carry + (io_update_write_data_bits_entry_carry), + .io_w_req_bits_data_3_entry_isCall + (io_update_write_data_bits_entry_isCall), + .io_w_req_bits_data_3_entry_isRet + (io_update_write_data_bits_entry_isRet), + .io_w_req_bits_data_3_entry_isJalr + (io_update_write_data_bits_entry_isJalr), + .io_w_req_bits_data_3_entry_last_may_be_rvi_call + (io_update_write_data_bits_entry_last_may_be_rvi_call), + .io_w_req_bits_data_3_entry_always_taken_0 + (io_update_write_data_bits_entry_always_taken_0), + .io_w_req_bits_data_3_entry_always_taken_1 + (io_update_write_data_bits_entry_always_taken_1), + .io_w_req_bits_data_3_tag (io_update_write_data_bits_tag), + .io_w_req_bits_waymask (4'h1 << u_way) + ); + assign io_read_resp_valid = + total_hits_0 & pred_rdata_0_entry_valid | total_hits_1 & pred_rdata_1_entry_valid + | total_hits_2 & pred_rdata_2_entry_valid | total_hits_3 & pred_rdata_3_entry_valid; + assign io_read_resp_brSlots_0_offset = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_brSlots_0_offset + : pred_rdata_hold_data_0_entry_brSlots_0_offset) + : 4'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_brSlots_0_offset + : pred_rdata_hold_data_1_entry_brSlots_0_offset) + : 4'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_brSlots_0_offset + : pred_rdata_hold_data_2_entry_brSlots_0_offset) + : 4'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_brSlots_0_offset + : pred_rdata_hold_data_3_entry_brSlots_0_offset) + : 4'h0); + assign io_read_resp_brSlots_0_lower = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_brSlots_0_lower + : pred_rdata_hold_data_0_entry_brSlots_0_lower) + : 12'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_brSlots_0_lower + : pred_rdata_hold_data_1_entry_brSlots_0_lower) + : 12'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_brSlots_0_lower + : pred_rdata_hold_data_2_entry_brSlots_0_lower) + : 12'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_brSlots_0_lower + : pred_rdata_hold_data_3_entry_brSlots_0_lower) + : 12'h0); + assign io_read_resp_brSlots_0_tarStat = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_brSlots_0_tarStat + : pred_rdata_hold_data_0_entry_brSlots_0_tarStat) + : 2'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_brSlots_0_tarStat + : pred_rdata_hold_data_1_entry_brSlots_0_tarStat) + : 2'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_brSlots_0_tarStat + : pred_rdata_hold_data_2_entry_brSlots_0_tarStat) + : 2'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_brSlots_0_tarStat + : pred_rdata_hold_data_3_entry_brSlots_0_tarStat) + : 2'h0); + assign io_read_resp_brSlots_0_sharing = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_brSlots_0_sharing + : pred_rdata_hold_data_0_entry_brSlots_0_sharing) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_brSlots_0_sharing + : pred_rdata_hold_data_1_entry_brSlots_0_sharing) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_brSlots_0_sharing + : pred_rdata_hold_data_2_entry_brSlots_0_sharing) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_brSlots_0_sharing + : pred_rdata_hold_data_3_entry_brSlots_0_sharing); + assign io_read_resp_brSlots_0_valid = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_brSlots_0_valid + : pred_rdata_hold_data_0_entry_brSlots_0_valid) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_brSlots_0_valid + : pred_rdata_hold_data_1_entry_brSlots_0_valid) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_brSlots_0_valid + : pred_rdata_hold_data_2_entry_brSlots_0_valid) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_brSlots_0_valid + : pred_rdata_hold_data_3_entry_brSlots_0_valid); + assign io_read_resp_tailSlot_offset = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_tailSlot_offset + : pred_rdata_hold_data_0_entry_tailSlot_offset) + : 4'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_tailSlot_offset + : pred_rdata_hold_data_1_entry_tailSlot_offset) + : 4'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_tailSlot_offset + : pred_rdata_hold_data_2_entry_tailSlot_offset) + : 4'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_tailSlot_offset + : pred_rdata_hold_data_3_entry_tailSlot_offset) + : 4'h0); + assign io_read_resp_tailSlot_lower = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_tailSlot_lower + : pred_rdata_hold_data_0_entry_tailSlot_lower) + : 20'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_tailSlot_lower + : pred_rdata_hold_data_1_entry_tailSlot_lower) + : 20'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_tailSlot_lower + : pred_rdata_hold_data_2_entry_tailSlot_lower) + : 20'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_tailSlot_lower + : pred_rdata_hold_data_3_entry_tailSlot_lower) + : 20'h0); + assign io_read_resp_tailSlot_tarStat = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_tailSlot_tarStat + : pred_rdata_hold_data_0_entry_tailSlot_tarStat) + : 2'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_tailSlot_tarStat + : pred_rdata_hold_data_1_entry_tailSlot_tarStat) + : 2'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_tailSlot_tarStat + : pred_rdata_hold_data_2_entry_tailSlot_tarStat) + : 2'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_tailSlot_tarStat + : pred_rdata_hold_data_3_entry_tailSlot_tarStat) + : 2'h0); + assign io_read_resp_tailSlot_sharing = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_tailSlot_sharing + : pred_rdata_hold_data_0_entry_tailSlot_sharing) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_tailSlot_sharing + : pred_rdata_hold_data_1_entry_tailSlot_sharing) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_tailSlot_sharing + : pred_rdata_hold_data_2_entry_tailSlot_sharing) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_tailSlot_sharing + : pred_rdata_hold_data_3_entry_tailSlot_sharing); + assign io_read_resp_tailSlot_valid = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_tailSlot_valid + : pred_rdata_hold_data_0_entry_tailSlot_valid) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_tailSlot_valid + : pred_rdata_hold_data_1_entry_tailSlot_valid) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_tailSlot_valid + : pred_rdata_hold_data_2_entry_tailSlot_valid) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_tailSlot_valid + : pred_rdata_hold_data_3_entry_tailSlot_valid); + assign io_read_resp_pftAddr = + (total_hits_0 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_pftAddr + : pred_rdata_hold_data_0_entry_pftAddr) + : 4'h0) + | (total_hits_1 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_pftAddr + : pred_rdata_hold_data_1_entry_pftAddr) + : 4'h0) + | (total_hits_2 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_pftAddr + : pred_rdata_hold_data_2_entry_pftAddr) + : 4'h0) + | (total_hits_3 + ? (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_pftAddr + : pred_rdata_hold_data_3_entry_pftAddr) + : 4'h0); + assign io_read_resp_carry = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_carry + : pred_rdata_hold_data_0_entry_carry) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_carry + : pred_rdata_hold_data_1_entry_carry) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_carry + : pred_rdata_hold_data_2_entry_carry) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_carry + : pred_rdata_hold_data_3_entry_carry); + assign io_read_resp_isCall = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_isCall + : pred_rdata_hold_data_0_entry_isCall) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_isCall + : pred_rdata_hold_data_1_entry_isCall) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_isCall + : pred_rdata_hold_data_2_entry_isCall) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_isCall + : pred_rdata_hold_data_3_entry_isCall); + assign io_read_resp_isRet = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_isRet + : pred_rdata_hold_data_0_entry_isRet) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_isRet + : pred_rdata_hold_data_1_entry_isRet) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_isRet + : pred_rdata_hold_data_2_entry_isRet) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_isRet + : pred_rdata_hold_data_3_entry_isRet); + assign io_read_resp_isJalr = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_isJalr + : pred_rdata_hold_data_0_entry_isJalr) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_isJalr + : pred_rdata_hold_data_1_entry_isJalr) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_isJalr + : pred_rdata_hold_data_2_entry_isJalr) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_isJalr + : pred_rdata_hold_data_3_entry_isJalr); + assign io_read_resp_last_may_be_rvi_call = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_last_may_be_rvi_call + : pred_rdata_hold_data_0_entry_last_may_be_rvi_call) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_last_may_be_rvi_call + : pred_rdata_hold_data_1_entry_last_may_be_rvi_call) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_last_may_be_rvi_call + : pred_rdata_hold_data_2_entry_last_may_be_rvi_call) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_last_may_be_rvi_call + : pred_rdata_hold_data_3_entry_last_may_be_rvi_call); + assign io_read_resp_always_taken_0 = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_always_taken_0 + : pred_rdata_hold_data_0_entry_always_taken_0) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_always_taken_0 + : pred_rdata_hold_data_1_entry_always_taken_0) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_always_taken_0 + : pred_rdata_hold_data_2_entry_always_taken_0) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_always_taken_0 + : pred_rdata_hold_data_3_entry_always_taken_0); + assign io_read_resp_always_taken_1 = + total_hits_0 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_0_entry_always_taken_1 + : pred_rdata_hold_data_0_entry_always_taken_1) | total_hits_1 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_1_entry_always_taken_1 + : pred_rdata_hold_data_1_entry_always_taken_1) | total_hits_2 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_2_entry_always_taken_1 + : pred_rdata_hold_data_2_entry_always_taken_1) | total_hits_3 + & (pred_rdata_REG + ? _ftb_io_r_resp_data_3_entry_always_taken_1 + : pred_rdata_hold_data_3_entry_always_taken_1); + assign io_read_hits_valid = hit; + assign io_read_hits_bits = hit_way; + assign io_update_hits_valid = + _ftb_io_r_resp_data_0_tag == u_req_tag & _ftb_io_r_resp_data_0_entry_valid + & u_total_hits_REG | u_total_hits_1 | u_total_hits_2 | u_total_hits_3; + assign io_update_hits_bits = + {|{u_total_hits_3, u_total_hits_2}, u_total_hits_3 | u_total_hits_1}; +endmodule + diff --git a/rtl/BPUTop/FauFTB.sv b/rtl/BPUTop/FauFTB.sv new file mode 100644 index 0000000..b7f27c5 --- /dev/null +++ b/rtl/BPUTop/FauFTB.sv @@ -0,0 +1,4755 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FauFTB( + input clock, + input reset, + input [35:0] io_reset_vector, + input [40:0] io_in_bits_s0_pc_0, + input [40:0] io_in_bits_s0_pc_1, + input [40:0] io_in_bits_s0_pc_2, + input [40:0] io_in_bits_s0_pc_3, + output [40:0] io_out_s1_pc_0, + output [40:0] io_out_s1_pc_1, + output [40:0] io_out_s1_pc_2, + output [40:0] io_out_s1_pc_3, + output io_out_s1_full_pred_0_br_taken_mask_0, + output io_out_s1_full_pred_0_br_taken_mask_1, + output io_out_s1_full_pred_0_slot_valids_0, + output io_out_s1_full_pred_0_slot_valids_1, + output [40:0] io_out_s1_full_pred_0_targets_0, + output [40:0] io_out_s1_full_pred_0_targets_1, + output [3:0] io_out_s1_full_pred_0_offsets_0, + output [3:0] io_out_s1_full_pred_0_offsets_1, + output [40:0] io_out_s1_full_pred_0_fallThroughAddr, + output io_out_s1_full_pred_0_is_br_sharing, + output io_out_s1_full_pred_0_hit, + output io_out_s1_full_pred_1_br_taken_mask_0, + output io_out_s1_full_pred_1_br_taken_mask_1, + output io_out_s1_full_pred_1_slot_valids_0, + output io_out_s1_full_pred_1_slot_valids_1, + output [40:0] io_out_s1_full_pred_1_targets_0, + output [40:0] io_out_s1_full_pred_1_targets_1, + output [3:0] io_out_s1_full_pred_1_offsets_0, + output [3:0] io_out_s1_full_pred_1_offsets_1, + output [40:0] io_out_s1_full_pred_1_fallThroughAddr, + output io_out_s1_full_pred_1_is_br_sharing, + output io_out_s1_full_pred_1_hit, + output io_out_s1_full_pred_2_br_taken_mask_0, + output io_out_s1_full_pred_2_br_taken_mask_1, + output io_out_s1_full_pred_2_slot_valids_0, + output io_out_s1_full_pred_2_slot_valids_1, + output [40:0] io_out_s1_full_pred_2_targets_0, + output [40:0] io_out_s1_full_pred_2_targets_1, + output [3:0] io_out_s1_full_pred_2_offsets_0, + output [3:0] io_out_s1_full_pred_2_offsets_1, + output [40:0] io_out_s1_full_pred_2_fallThroughAddr, + output io_out_s1_full_pred_2_is_br_sharing, + output io_out_s1_full_pred_2_hit, + output io_out_s1_full_pred_3_br_taken_mask_0, + output io_out_s1_full_pred_3_br_taken_mask_1, + output io_out_s1_full_pred_3_slot_valids_0, + output io_out_s1_full_pred_3_slot_valids_1, + output [40:0] io_out_s1_full_pred_3_targets_0, + output [40:0] io_out_s1_full_pred_3_targets_1, + output [3:0] io_out_s1_full_pred_3_offsets_0, + output [3:0] io_out_s1_full_pred_3_offsets_1, + output [40:0] io_out_s1_full_pred_3_fallThroughAddr, + output io_out_s1_full_pred_3_fallThroughErr, + output io_out_s1_full_pred_3_is_br_sharing, + output io_out_s1_full_pred_3_hit, + output [222:0] io_out_last_stage_meta, + input io_ctrl_ubtb_enable, + input io_s0_fire_0, + input io_s0_fire_1, + input io_s0_fire_2, + input io_s0_fire_3, + input io_s1_fire_0, + input io_s2_fire_0, + input io_update_valid, + input [40:0] io_update_bits_pc, + input [3:0] io_update_bits_ftb_entry_brSlots_0_offset, + input [11:0] io_update_bits_ftb_entry_brSlots_0_lower, + input [1:0] io_update_bits_ftb_entry_brSlots_0_tarStat, + input io_update_bits_ftb_entry_brSlots_0_valid, + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, + input [19:0] io_update_bits_ftb_entry_tailSlot_lower, + input [1:0] io_update_bits_ftb_entry_tailSlot_tarStat, + input io_update_bits_ftb_entry_tailSlot_sharing, + input io_update_bits_ftb_entry_tailSlot_valid, + input [3:0] io_update_bits_ftb_entry_pftAddr, + input io_update_bits_ftb_entry_carry, + input io_update_bits_ftb_entry_always_taken_0, + input io_update_bits_ftb_entry_always_taken_1, + input io_update_bits_br_taken_mask_0, + input io_update_bits_br_taken_mask_1, + input [222:0] io_update_bits_meta, + output [5:0] io_perf_0_value, + output [5:0] io_perf_1_value +); + + reg [4:0] resp_meta_pred_way_r_1; + reg resp_meta_hit_r_1; + wire [3:0] _ways_31_io_resp_brSlots_0_offset; + wire [11:0] _ways_31_io_resp_brSlots_0_lower; + wire [1:0] _ways_31_io_resp_brSlots_0_tarStat; + wire _ways_31_io_resp_brSlots_0_valid; + wire [3:0] _ways_31_io_resp_tailSlot_offset; + wire [19:0] _ways_31_io_resp_tailSlot_lower; + wire [1:0] _ways_31_io_resp_tailSlot_tarStat; + wire _ways_31_io_resp_tailSlot_sharing; + wire _ways_31_io_resp_tailSlot_valid; + wire [3:0] _ways_31_io_resp_pftAddr; + wire _ways_31_io_resp_carry; + wire _ways_31_io_resp_always_taken_0; + wire _ways_31_io_resp_always_taken_1; + wire _ways_31_io_resp_hit; + wire _ways_31_io_update_hit; + wire [3:0] _ways_30_io_resp_brSlots_0_offset; + wire [11:0] _ways_30_io_resp_brSlots_0_lower; + wire [1:0] _ways_30_io_resp_brSlots_0_tarStat; + wire _ways_30_io_resp_brSlots_0_valid; + wire [3:0] _ways_30_io_resp_tailSlot_offset; + wire [19:0] _ways_30_io_resp_tailSlot_lower; + wire [1:0] _ways_30_io_resp_tailSlot_tarStat; + wire _ways_30_io_resp_tailSlot_sharing; + wire _ways_30_io_resp_tailSlot_valid; + wire [3:0] _ways_30_io_resp_pftAddr; + wire _ways_30_io_resp_carry; + wire _ways_30_io_resp_always_taken_0; + wire _ways_30_io_resp_always_taken_1; + wire _ways_30_io_resp_hit; + wire _ways_30_io_update_hit; + wire [3:0] _ways_29_io_resp_brSlots_0_offset; + wire [11:0] _ways_29_io_resp_brSlots_0_lower; + wire [1:0] _ways_29_io_resp_brSlots_0_tarStat; + wire _ways_29_io_resp_brSlots_0_valid; + wire [3:0] _ways_29_io_resp_tailSlot_offset; + wire [19:0] _ways_29_io_resp_tailSlot_lower; + wire [1:0] _ways_29_io_resp_tailSlot_tarStat; + wire _ways_29_io_resp_tailSlot_sharing; + wire _ways_29_io_resp_tailSlot_valid; + wire [3:0] _ways_29_io_resp_pftAddr; + wire _ways_29_io_resp_carry; + wire _ways_29_io_resp_always_taken_0; + wire _ways_29_io_resp_always_taken_1; + wire _ways_29_io_resp_hit; + wire _ways_29_io_update_hit; + wire [3:0] _ways_28_io_resp_brSlots_0_offset; + wire [11:0] _ways_28_io_resp_brSlots_0_lower; + wire [1:0] _ways_28_io_resp_brSlots_0_tarStat; + wire _ways_28_io_resp_brSlots_0_valid; + wire [3:0] _ways_28_io_resp_tailSlot_offset; + wire [19:0] _ways_28_io_resp_tailSlot_lower; + wire [1:0] _ways_28_io_resp_tailSlot_tarStat; + wire _ways_28_io_resp_tailSlot_sharing; + wire _ways_28_io_resp_tailSlot_valid; + wire [3:0] _ways_28_io_resp_pftAddr; + wire _ways_28_io_resp_carry; + wire _ways_28_io_resp_always_taken_0; + wire _ways_28_io_resp_always_taken_1; + wire _ways_28_io_resp_hit; + wire _ways_28_io_update_hit; + wire [3:0] _ways_27_io_resp_brSlots_0_offset; + wire [11:0] _ways_27_io_resp_brSlots_0_lower; + wire [1:0] _ways_27_io_resp_brSlots_0_tarStat; + wire _ways_27_io_resp_brSlots_0_valid; + wire [3:0] _ways_27_io_resp_tailSlot_offset; + wire [19:0] _ways_27_io_resp_tailSlot_lower; + wire [1:0] _ways_27_io_resp_tailSlot_tarStat; + wire _ways_27_io_resp_tailSlot_sharing; + wire _ways_27_io_resp_tailSlot_valid; + wire [3:0] _ways_27_io_resp_pftAddr; + wire _ways_27_io_resp_carry; + wire _ways_27_io_resp_always_taken_0; + wire _ways_27_io_resp_always_taken_1; + wire _ways_27_io_resp_hit; + wire _ways_27_io_update_hit; + wire [3:0] _ways_26_io_resp_brSlots_0_offset; + wire [11:0] _ways_26_io_resp_brSlots_0_lower; + wire [1:0] _ways_26_io_resp_brSlots_0_tarStat; + wire _ways_26_io_resp_brSlots_0_valid; + wire [3:0] _ways_26_io_resp_tailSlot_offset; + wire [19:0] _ways_26_io_resp_tailSlot_lower; + wire [1:0] _ways_26_io_resp_tailSlot_tarStat; + wire _ways_26_io_resp_tailSlot_sharing; + wire _ways_26_io_resp_tailSlot_valid; + wire [3:0] _ways_26_io_resp_pftAddr; + wire _ways_26_io_resp_carry; + wire _ways_26_io_resp_always_taken_0; + wire _ways_26_io_resp_always_taken_1; + wire _ways_26_io_resp_hit; + wire _ways_26_io_update_hit; + wire [3:0] _ways_25_io_resp_brSlots_0_offset; + wire [11:0] _ways_25_io_resp_brSlots_0_lower; + wire [1:0] _ways_25_io_resp_brSlots_0_tarStat; + wire _ways_25_io_resp_brSlots_0_valid; + wire [3:0] _ways_25_io_resp_tailSlot_offset; + wire [19:0] _ways_25_io_resp_tailSlot_lower; + wire [1:0] _ways_25_io_resp_tailSlot_tarStat; + wire _ways_25_io_resp_tailSlot_sharing; + wire _ways_25_io_resp_tailSlot_valid; + wire [3:0] _ways_25_io_resp_pftAddr; + wire _ways_25_io_resp_carry; + wire _ways_25_io_resp_always_taken_0; + wire _ways_25_io_resp_always_taken_1; + wire _ways_25_io_resp_hit; + wire _ways_25_io_update_hit; + wire [3:0] _ways_24_io_resp_brSlots_0_offset; + wire [11:0] _ways_24_io_resp_brSlots_0_lower; + wire [1:0] _ways_24_io_resp_brSlots_0_tarStat; + wire _ways_24_io_resp_brSlots_0_valid; + wire [3:0] _ways_24_io_resp_tailSlot_offset; + wire [19:0] _ways_24_io_resp_tailSlot_lower; + wire [1:0] _ways_24_io_resp_tailSlot_tarStat; + wire _ways_24_io_resp_tailSlot_sharing; + wire _ways_24_io_resp_tailSlot_valid; + wire [3:0] _ways_24_io_resp_pftAddr; + wire _ways_24_io_resp_carry; + wire _ways_24_io_resp_always_taken_0; + wire _ways_24_io_resp_always_taken_1; + wire _ways_24_io_resp_hit; + wire _ways_24_io_update_hit; + wire [3:0] _ways_23_io_resp_brSlots_0_offset; + wire [11:0] _ways_23_io_resp_brSlots_0_lower; + wire [1:0] _ways_23_io_resp_brSlots_0_tarStat; + wire _ways_23_io_resp_brSlots_0_valid; + wire [3:0] _ways_23_io_resp_tailSlot_offset; + wire [19:0] _ways_23_io_resp_tailSlot_lower; + wire [1:0] _ways_23_io_resp_tailSlot_tarStat; + wire _ways_23_io_resp_tailSlot_sharing; + wire _ways_23_io_resp_tailSlot_valid; + wire [3:0] _ways_23_io_resp_pftAddr; + wire _ways_23_io_resp_carry; + wire _ways_23_io_resp_always_taken_0; + wire _ways_23_io_resp_always_taken_1; + wire _ways_23_io_resp_hit; + wire _ways_23_io_update_hit; + wire [3:0] _ways_22_io_resp_brSlots_0_offset; + wire [11:0] _ways_22_io_resp_brSlots_0_lower; + wire [1:0] _ways_22_io_resp_brSlots_0_tarStat; + wire _ways_22_io_resp_brSlots_0_valid; + wire [3:0] _ways_22_io_resp_tailSlot_offset; + wire [19:0] _ways_22_io_resp_tailSlot_lower; + wire [1:0] _ways_22_io_resp_tailSlot_tarStat; + wire _ways_22_io_resp_tailSlot_sharing; + wire _ways_22_io_resp_tailSlot_valid; + wire [3:0] _ways_22_io_resp_pftAddr; + wire _ways_22_io_resp_carry; + wire _ways_22_io_resp_always_taken_0; + wire _ways_22_io_resp_always_taken_1; + wire _ways_22_io_resp_hit; + wire _ways_22_io_update_hit; + wire [3:0] _ways_21_io_resp_brSlots_0_offset; + wire [11:0] _ways_21_io_resp_brSlots_0_lower; + wire [1:0] _ways_21_io_resp_brSlots_0_tarStat; + wire _ways_21_io_resp_brSlots_0_valid; + wire [3:0] _ways_21_io_resp_tailSlot_offset; + wire [19:0] _ways_21_io_resp_tailSlot_lower; + wire [1:0] _ways_21_io_resp_tailSlot_tarStat; + wire _ways_21_io_resp_tailSlot_sharing; + wire _ways_21_io_resp_tailSlot_valid; + wire [3:0] _ways_21_io_resp_pftAddr; + wire _ways_21_io_resp_carry; + wire _ways_21_io_resp_always_taken_0; + wire _ways_21_io_resp_always_taken_1; + wire _ways_21_io_resp_hit; + wire _ways_21_io_update_hit; + wire [3:0] _ways_20_io_resp_brSlots_0_offset; + wire [11:0] _ways_20_io_resp_brSlots_0_lower; + wire [1:0] _ways_20_io_resp_brSlots_0_tarStat; + wire _ways_20_io_resp_brSlots_0_valid; + wire [3:0] _ways_20_io_resp_tailSlot_offset; + wire [19:0] _ways_20_io_resp_tailSlot_lower; + wire [1:0] _ways_20_io_resp_tailSlot_tarStat; + wire _ways_20_io_resp_tailSlot_sharing; + wire _ways_20_io_resp_tailSlot_valid; + wire [3:0] _ways_20_io_resp_pftAddr; + wire _ways_20_io_resp_carry; + wire _ways_20_io_resp_always_taken_0; + wire _ways_20_io_resp_always_taken_1; + wire _ways_20_io_resp_hit; + wire _ways_20_io_update_hit; + wire [3:0] _ways_19_io_resp_brSlots_0_offset; + wire [11:0] _ways_19_io_resp_brSlots_0_lower; + wire [1:0] _ways_19_io_resp_brSlots_0_tarStat; + wire _ways_19_io_resp_brSlots_0_valid; + wire [3:0] _ways_19_io_resp_tailSlot_offset; + wire [19:0] _ways_19_io_resp_tailSlot_lower; + wire [1:0] _ways_19_io_resp_tailSlot_tarStat; + wire _ways_19_io_resp_tailSlot_sharing; + wire _ways_19_io_resp_tailSlot_valid; + wire [3:0] _ways_19_io_resp_pftAddr; + wire _ways_19_io_resp_carry; + wire _ways_19_io_resp_always_taken_0; + wire _ways_19_io_resp_always_taken_1; + wire _ways_19_io_resp_hit; + wire _ways_19_io_update_hit; + wire [3:0] _ways_18_io_resp_brSlots_0_offset; + wire [11:0] _ways_18_io_resp_brSlots_0_lower; + wire [1:0] _ways_18_io_resp_brSlots_0_tarStat; + wire _ways_18_io_resp_brSlots_0_valid; + wire [3:0] _ways_18_io_resp_tailSlot_offset; + wire [19:0] _ways_18_io_resp_tailSlot_lower; + wire [1:0] _ways_18_io_resp_tailSlot_tarStat; + wire _ways_18_io_resp_tailSlot_sharing; + wire _ways_18_io_resp_tailSlot_valid; + wire [3:0] _ways_18_io_resp_pftAddr; + wire _ways_18_io_resp_carry; + wire _ways_18_io_resp_always_taken_0; + wire _ways_18_io_resp_always_taken_1; + wire _ways_18_io_resp_hit; + wire _ways_18_io_update_hit; + wire [3:0] _ways_17_io_resp_brSlots_0_offset; + wire [11:0] _ways_17_io_resp_brSlots_0_lower; + wire [1:0] _ways_17_io_resp_brSlots_0_tarStat; + wire _ways_17_io_resp_brSlots_0_valid; + wire [3:0] _ways_17_io_resp_tailSlot_offset; + wire [19:0] _ways_17_io_resp_tailSlot_lower; + wire [1:0] _ways_17_io_resp_tailSlot_tarStat; + wire _ways_17_io_resp_tailSlot_sharing; + wire _ways_17_io_resp_tailSlot_valid; + wire [3:0] _ways_17_io_resp_pftAddr; + wire _ways_17_io_resp_carry; + wire _ways_17_io_resp_always_taken_0; + wire _ways_17_io_resp_always_taken_1; + wire _ways_17_io_resp_hit; + wire _ways_17_io_update_hit; + wire [3:0] _ways_16_io_resp_brSlots_0_offset; + wire [11:0] _ways_16_io_resp_brSlots_0_lower; + wire [1:0] _ways_16_io_resp_brSlots_0_tarStat; + wire _ways_16_io_resp_brSlots_0_valid; + wire [3:0] _ways_16_io_resp_tailSlot_offset; + wire [19:0] _ways_16_io_resp_tailSlot_lower; + wire [1:0] _ways_16_io_resp_tailSlot_tarStat; + wire _ways_16_io_resp_tailSlot_sharing; + wire _ways_16_io_resp_tailSlot_valid; + wire [3:0] _ways_16_io_resp_pftAddr; + wire _ways_16_io_resp_carry; + wire _ways_16_io_resp_always_taken_0; + wire _ways_16_io_resp_always_taken_1; + wire _ways_16_io_resp_hit; + wire _ways_16_io_update_hit; + wire [3:0] _ways_15_io_resp_brSlots_0_offset; + wire [11:0] _ways_15_io_resp_brSlots_0_lower; + wire [1:0] _ways_15_io_resp_brSlots_0_tarStat; + wire _ways_15_io_resp_brSlots_0_valid; + wire [3:0] _ways_15_io_resp_tailSlot_offset; + wire [19:0] _ways_15_io_resp_tailSlot_lower; + wire [1:0] _ways_15_io_resp_tailSlot_tarStat; + wire _ways_15_io_resp_tailSlot_sharing; + wire _ways_15_io_resp_tailSlot_valid; + wire [3:0] _ways_15_io_resp_pftAddr; + wire _ways_15_io_resp_carry; + wire _ways_15_io_resp_always_taken_0; + wire _ways_15_io_resp_always_taken_1; + wire _ways_15_io_resp_hit; + wire _ways_15_io_update_hit; + wire [3:0] _ways_14_io_resp_brSlots_0_offset; + wire [11:0] _ways_14_io_resp_brSlots_0_lower; + wire [1:0] _ways_14_io_resp_brSlots_0_tarStat; + wire _ways_14_io_resp_brSlots_0_valid; + wire [3:0] _ways_14_io_resp_tailSlot_offset; + wire [19:0] _ways_14_io_resp_tailSlot_lower; + wire [1:0] _ways_14_io_resp_tailSlot_tarStat; + wire _ways_14_io_resp_tailSlot_sharing; + wire _ways_14_io_resp_tailSlot_valid; + wire [3:0] _ways_14_io_resp_pftAddr; + wire _ways_14_io_resp_carry; + wire _ways_14_io_resp_always_taken_0; + wire _ways_14_io_resp_always_taken_1; + wire _ways_14_io_resp_hit; + wire _ways_14_io_update_hit; + wire [3:0] _ways_13_io_resp_brSlots_0_offset; + wire [11:0] _ways_13_io_resp_brSlots_0_lower; + wire [1:0] _ways_13_io_resp_brSlots_0_tarStat; + wire _ways_13_io_resp_brSlots_0_valid; + wire [3:0] _ways_13_io_resp_tailSlot_offset; + wire [19:0] _ways_13_io_resp_tailSlot_lower; + wire [1:0] _ways_13_io_resp_tailSlot_tarStat; + wire _ways_13_io_resp_tailSlot_sharing; + wire _ways_13_io_resp_tailSlot_valid; + wire [3:0] _ways_13_io_resp_pftAddr; + wire _ways_13_io_resp_carry; + wire _ways_13_io_resp_always_taken_0; + wire _ways_13_io_resp_always_taken_1; + wire _ways_13_io_resp_hit; + wire _ways_13_io_update_hit; + wire [3:0] _ways_12_io_resp_brSlots_0_offset; + wire [11:0] _ways_12_io_resp_brSlots_0_lower; + wire [1:0] _ways_12_io_resp_brSlots_0_tarStat; + wire _ways_12_io_resp_brSlots_0_valid; + wire [3:0] _ways_12_io_resp_tailSlot_offset; + wire [19:0] _ways_12_io_resp_tailSlot_lower; + wire [1:0] _ways_12_io_resp_tailSlot_tarStat; + wire _ways_12_io_resp_tailSlot_sharing; + wire _ways_12_io_resp_tailSlot_valid; + wire [3:0] _ways_12_io_resp_pftAddr; + wire _ways_12_io_resp_carry; + wire _ways_12_io_resp_always_taken_0; + wire _ways_12_io_resp_always_taken_1; + wire _ways_12_io_resp_hit; + wire _ways_12_io_update_hit; + wire [3:0] _ways_11_io_resp_brSlots_0_offset; + wire [11:0] _ways_11_io_resp_brSlots_0_lower; + wire [1:0] _ways_11_io_resp_brSlots_0_tarStat; + wire _ways_11_io_resp_brSlots_0_valid; + wire [3:0] _ways_11_io_resp_tailSlot_offset; + wire [19:0] _ways_11_io_resp_tailSlot_lower; + wire [1:0] _ways_11_io_resp_tailSlot_tarStat; + wire _ways_11_io_resp_tailSlot_sharing; + wire _ways_11_io_resp_tailSlot_valid; + wire [3:0] _ways_11_io_resp_pftAddr; + wire _ways_11_io_resp_carry; + wire _ways_11_io_resp_always_taken_0; + wire _ways_11_io_resp_always_taken_1; + wire _ways_11_io_resp_hit; + wire _ways_11_io_update_hit; + wire [3:0] _ways_10_io_resp_brSlots_0_offset; + wire [11:0] _ways_10_io_resp_brSlots_0_lower; + wire [1:0] _ways_10_io_resp_brSlots_0_tarStat; + wire _ways_10_io_resp_brSlots_0_valid; + wire [3:0] _ways_10_io_resp_tailSlot_offset; + wire [19:0] _ways_10_io_resp_tailSlot_lower; + wire [1:0] _ways_10_io_resp_tailSlot_tarStat; + wire _ways_10_io_resp_tailSlot_sharing; + wire _ways_10_io_resp_tailSlot_valid; + wire [3:0] _ways_10_io_resp_pftAddr; + wire _ways_10_io_resp_carry; + wire _ways_10_io_resp_always_taken_0; + wire _ways_10_io_resp_always_taken_1; + wire _ways_10_io_resp_hit; + wire _ways_10_io_update_hit; + wire [3:0] _ways_9_io_resp_brSlots_0_offset; + wire [11:0] _ways_9_io_resp_brSlots_0_lower; + wire [1:0] _ways_9_io_resp_brSlots_0_tarStat; + wire _ways_9_io_resp_brSlots_0_valid; + wire [3:0] _ways_9_io_resp_tailSlot_offset; + wire [19:0] _ways_9_io_resp_tailSlot_lower; + wire [1:0] _ways_9_io_resp_tailSlot_tarStat; + wire _ways_9_io_resp_tailSlot_sharing; + wire _ways_9_io_resp_tailSlot_valid; + wire [3:0] _ways_9_io_resp_pftAddr; + wire _ways_9_io_resp_carry; + wire _ways_9_io_resp_always_taken_0; + wire _ways_9_io_resp_always_taken_1; + wire _ways_9_io_resp_hit; + wire _ways_9_io_update_hit; + wire [3:0] _ways_8_io_resp_brSlots_0_offset; + wire [11:0] _ways_8_io_resp_brSlots_0_lower; + wire [1:0] _ways_8_io_resp_brSlots_0_tarStat; + wire _ways_8_io_resp_brSlots_0_valid; + wire [3:0] _ways_8_io_resp_tailSlot_offset; + wire [19:0] _ways_8_io_resp_tailSlot_lower; + wire [1:0] _ways_8_io_resp_tailSlot_tarStat; + wire _ways_8_io_resp_tailSlot_sharing; + wire _ways_8_io_resp_tailSlot_valid; + wire [3:0] _ways_8_io_resp_pftAddr; + wire _ways_8_io_resp_carry; + wire _ways_8_io_resp_always_taken_0; + wire _ways_8_io_resp_always_taken_1; + wire _ways_8_io_resp_hit; + wire _ways_8_io_update_hit; + wire [3:0] _ways_7_io_resp_brSlots_0_offset; + wire [11:0] _ways_7_io_resp_brSlots_0_lower; + wire [1:0] _ways_7_io_resp_brSlots_0_tarStat; + wire _ways_7_io_resp_brSlots_0_valid; + wire [3:0] _ways_7_io_resp_tailSlot_offset; + wire [19:0] _ways_7_io_resp_tailSlot_lower; + wire [1:0] _ways_7_io_resp_tailSlot_tarStat; + wire _ways_7_io_resp_tailSlot_sharing; + wire _ways_7_io_resp_tailSlot_valid; + wire [3:0] _ways_7_io_resp_pftAddr; + wire _ways_7_io_resp_carry; + wire _ways_7_io_resp_always_taken_0; + wire _ways_7_io_resp_always_taken_1; + wire _ways_7_io_resp_hit; + wire _ways_7_io_update_hit; + wire [3:0] _ways_6_io_resp_brSlots_0_offset; + wire [11:0] _ways_6_io_resp_brSlots_0_lower; + wire [1:0] _ways_6_io_resp_brSlots_0_tarStat; + wire _ways_6_io_resp_brSlots_0_valid; + wire [3:0] _ways_6_io_resp_tailSlot_offset; + wire [19:0] _ways_6_io_resp_tailSlot_lower; + wire [1:0] _ways_6_io_resp_tailSlot_tarStat; + wire _ways_6_io_resp_tailSlot_sharing; + wire _ways_6_io_resp_tailSlot_valid; + wire [3:0] _ways_6_io_resp_pftAddr; + wire _ways_6_io_resp_carry; + wire _ways_6_io_resp_always_taken_0; + wire _ways_6_io_resp_always_taken_1; + wire _ways_6_io_resp_hit; + wire _ways_6_io_update_hit; + wire [3:0] _ways_5_io_resp_brSlots_0_offset; + wire [11:0] _ways_5_io_resp_brSlots_0_lower; + wire [1:0] _ways_5_io_resp_brSlots_0_tarStat; + wire _ways_5_io_resp_brSlots_0_valid; + wire [3:0] _ways_5_io_resp_tailSlot_offset; + wire [19:0] _ways_5_io_resp_tailSlot_lower; + wire [1:0] _ways_5_io_resp_tailSlot_tarStat; + wire _ways_5_io_resp_tailSlot_sharing; + wire _ways_5_io_resp_tailSlot_valid; + wire [3:0] _ways_5_io_resp_pftAddr; + wire _ways_5_io_resp_carry; + wire _ways_5_io_resp_always_taken_0; + wire _ways_5_io_resp_always_taken_1; + wire _ways_5_io_resp_hit; + wire _ways_5_io_update_hit; + wire [3:0] _ways_4_io_resp_brSlots_0_offset; + wire [11:0] _ways_4_io_resp_brSlots_0_lower; + wire [1:0] _ways_4_io_resp_brSlots_0_tarStat; + wire _ways_4_io_resp_brSlots_0_valid; + wire [3:0] _ways_4_io_resp_tailSlot_offset; + wire [19:0] _ways_4_io_resp_tailSlot_lower; + wire [1:0] _ways_4_io_resp_tailSlot_tarStat; + wire _ways_4_io_resp_tailSlot_sharing; + wire _ways_4_io_resp_tailSlot_valid; + wire [3:0] _ways_4_io_resp_pftAddr; + wire _ways_4_io_resp_carry; + wire _ways_4_io_resp_always_taken_0; + wire _ways_4_io_resp_always_taken_1; + wire _ways_4_io_resp_hit; + wire _ways_4_io_update_hit; + wire [3:0] _ways_3_io_resp_brSlots_0_offset; + wire [11:0] _ways_3_io_resp_brSlots_0_lower; + wire [1:0] _ways_3_io_resp_brSlots_0_tarStat; + wire _ways_3_io_resp_brSlots_0_valid; + wire [3:0] _ways_3_io_resp_tailSlot_offset; + wire [19:0] _ways_3_io_resp_tailSlot_lower; + wire [1:0] _ways_3_io_resp_tailSlot_tarStat; + wire _ways_3_io_resp_tailSlot_sharing; + wire _ways_3_io_resp_tailSlot_valid; + wire [3:0] _ways_3_io_resp_pftAddr; + wire _ways_3_io_resp_carry; + wire _ways_3_io_resp_always_taken_0; + wire _ways_3_io_resp_always_taken_1; + wire _ways_3_io_resp_hit; + wire _ways_3_io_update_hit; + wire [3:0] _ways_2_io_resp_brSlots_0_offset; + wire [11:0] _ways_2_io_resp_brSlots_0_lower; + wire [1:0] _ways_2_io_resp_brSlots_0_tarStat; + wire _ways_2_io_resp_brSlots_0_valid; + wire [3:0] _ways_2_io_resp_tailSlot_offset; + wire [19:0] _ways_2_io_resp_tailSlot_lower; + wire [1:0] _ways_2_io_resp_tailSlot_tarStat; + wire _ways_2_io_resp_tailSlot_sharing; + wire _ways_2_io_resp_tailSlot_valid; + wire [3:0] _ways_2_io_resp_pftAddr; + wire _ways_2_io_resp_carry; + wire _ways_2_io_resp_always_taken_0; + wire _ways_2_io_resp_always_taken_1; + wire _ways_2_io_resp_hit; + wire _ways_2_io_update_hit; + wire [3:0] _ways_1_io_resp_brSlots_0_offset; + wire [11:0] _ways_1_io_resp_brSlots_0_lower; + wire [1:0] _ways_1_io_resp_brSlots_0_tarStat; + wire _ways_1_io_resp_brSlots_0_valid; + wire [3:0] _ways_1_io_resp_tailSlot_offset; + wire [19:0] _ways_1_io_resp_tailSlot_lower; + wire [1:0] _ways_1_io_resp_tailSlot_tarStat; + wire _ways_1_io_resp_tailSlot_sharing; + wire _ways_1_io_resp_tailSlot_valid; + wire [3:0] _ways_1_io_resp_pftAddr; + wire _ways_1_io_resp_carry; + wire _ways_1_io_resp_always_taken_0; + wire _ways_1_io_resp_always_taken_1; + wire _ways_1_io_resp_hit; + wire _ways_1_io_update_hit; + wire [3:0] _ways_0_io_resp_brSlots_0_offset; + wire [11:0] _ways_0_io_resp_brSlots_0_lower; + wire [1:0] _ways_0_io_resp_brSlots_0_tarStat; + wire _ways_0_io_resp_brSlots_0_valid; + wire [3:0] _ways_0_io_resp_tailSlot_offset; + wire [19:0] _ways_0_io_resp_tailSlot_lower; + wire [1:0] _ways_0_io_resp_tailSlot_tarStat; + wire _ways_0_io_resp_tailSlot_sharing; + wire _ways_0_io_resp_tailSlot_valid; + wire [3:0] _ways_0_io_resp_pftAddr; + wire _ways_0_io_resp_carry; + wire _ways_0_io_resp_always_taken_0; + wire _ways_0_io_resp_always_taken_1; + wire _ways_0_io_resp_hit; + wire _ways_0_io_update_hit; + wire [35:0] _reset_vector_delay_io_out; + reg [40:0] s1_pc_dup_0; + reg [40:0] s1_pc_dup_1; + reg [40:0] s1_pc_dup_2; + reg [40:0] s1_pc_dup_3; + reg REG; + reg REG_1; + reg [1:0] ctrs_0_0; + reg [1:0] ctrs_0_1; + reg [1:0] ctrs_1_0; + reg [1:0] ctrs_1_1; + reg [1:0] ctrs_2_0; + reg [1:0] ctrs_2_1; + reg [1:0] ctrs_3_0; + reg [1:0] ctrs_3_1; + reg [1:0] ctrs_4_0; + reg [1:0] ctrs_4_1; + reg [1:0] ctrs_5_0; + reg [1:0] ctrs_5_1; + reg [1:0] ctrs_6_0; + reg [1:0] ctrs_6_1; + reg [1:0] ctrs_7_0; + reg [1:0] ctrs_7_1; + reg [1:0] ctrs_8_0; + reg [1:0] ctrs_8_1; + reg [1:0] ctrs_9_0; + reg [1:0] ctrs_9_1; + reg [1:0] ctrs_10_0; + reg [1:0] ctrs_10_1; + reg [1:0] ctrs_11_0; + reg [1:0] ctrs_11_1; + reg [1:0] ctrs_12_0; + reg [1:0] ctrs_12_1; + reg [1:0] ctrs_13_0; + reg [1:0] ctrs_13_1; + reg [1:0] ctrs_14_0; + reg [1:0] ctrs_14_1; + reg [1:0] ctrs_15_0; + reg [1:0] ctrs_15_1; + reg [1:0] ctrs_16_0; + reg [1:0] ctrs_16_1; + reg [1:0] ctrs_17_0; + reg [1:0] ctrs_17_1; + reg [1:0] ctrs_18_0; + reg [1:0] ctrs_18_1; + reg [1:0] ctrs_19_0; + reg [1:0] ctrs_19_1; + reg [1:0] ctrs_20_0; + reg [1:0] ctrs_20_1; + reg [1:0] ctrs_21_0; + reg [1:0] ctrs_21_1; + reg [1:0] ctrs_22_0; + reg [1:0] ctrs_22_1; + reg [1:0] ctrs_23_0; + reg [1:0] ctrs_23_1; + reg [1:0] ctrs_24_0; + reg [1:0] ctrs_24_1; + reg [1:0] ctrs_25_0; + reg [1:0] ctrs_25_1; + reg [1:0] ctrs_26_0; + reg [1:0] ctrs_26_1; + reg [1:0] ctrs_27_0; + reg [1:0] ctrs_27_1; + reg [1:0] ctrs_28_0; + reg [1:0] ctrs_28_1; + reg [1:0] ctrs_29_0; + reg [1:0] ctrs_29_1; + reg [1:0] ctrs_30_0; + reg [1:0] ctrs_30_1; + reg [1:0] ctrs_31_0; + reg [1:0] ctrs_31_1; + reg [30:0] state_reg; + wire [31:0] s1_hit_oh = + {_ways_31_io_resp_hit, + _ways_30_io_resp_hit, + _ways_29_io_resp_hit, + _ways_28_io_resp_hit, + _ways_27_io_resp_hit, + _ways_26_io_resp_hit, + _ways_25_io_resp_hit, + _ways_24_io_resp_hit, + _ways_23_io_resp_hit, + _ways_22_io_resp_hit, + _ways_21_io_resp_hit, + _ways_20_io_resp_hit, + _ways_19_io_resp_hit, + _ways_18_io_resp_hit, + _ways_17_io_resp_hit, + _ways_16_io_resp_hit, + _ways_15_io_resp_hit, + _ways_14_io_resp_hit, + _ways_13_io_resp_hit, + _ways_12_io_resp_hit, + _ways_11_io_resp_hit, + _ways_10_io_resp_hit, + _ways_9_io_resp_hit, + _ways_8_io_resp_hit, + _ways_7_io_resp_hit, + _ways_6_io_resp_hit, + _ways_5_io_resp_hit, + _ways_4_io_resp_hit, + _ways_3_io_resp_hit, + _ways_2_io_resp_hit, + _ways_1_io_resp_hit, + _ways_0_io_resp_hit}; + wire _target_T_18 = _ways_0_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_19 = _ways_0_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_20 = _ways_0_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_0_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_0_io_resp_carry, _ways_0_io_resp_pftAddr}; + wire [40:0] _s1_possible_full_preds_31_fallThroughAddr_T = 41'(s1_pc_dup_0 + 41'h20); + wire _target_T_45 = _ways_1_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_46 = _ways_1_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_47 = _ways_1_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_1_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_1_io_resp_carry, _ways_1_io_resp_pftAddr}; + wire _target_T_72 = _ways_2_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_73 = _ways_2_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_74 = _ways_2_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_2_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_2_io_resp_carry, _ways_2_io_resp_pftAddr}; + wire _target_T_99 = _ways_3_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_100 = _ways_3_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_101 = _ways_3_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_3_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_3_io_resp_carry, _ways_3_io_resp_pftAddr}; + wire _target_T_126 = _ways_4_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_127 = _ways_4_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_128 = _ways_4_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_4_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_4_io_resp_carry, _ways_4_io_resp_pftAddr}; + wire _target_T_153 = _ways_5_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_154 = _ways_5_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_155 = _ways_5_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_5_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_5_io_resp_carry, _ways_5_io_resp_pftAddr}; + wire _target_T_180 = _ways_6_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_181 = _ways_6_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_182 = _ways_6_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_6_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_6_io_resp_carry, _ways_6_io_resp_pftAddr}; + wire _target_T_207 = _ways_7_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_208 = _ways_7_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_209 = _ways_7_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_7_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_7_io_resp_carry, _ways_7_io_resp_pftAddr}; + wire _target_T_234 = _ways_8_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_235 = _ways_8_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_236 = _ways_8_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_8_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_8_io_resp_carry, _ways_8_io_resp_pftAddr}; + wire _target_T_261 = _ways_9_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_262 = _ways_9_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_263 = _ways_9_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_9_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_9_io_resp_carry, _ways_9_io_resp_pftAddr}; + wire _target_T_288 = _ways_10_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_289 = _ways_10_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_290 = _ways_10_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_10_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_10_io_resp_carry, _ways_10_io_resp_pftAddr}; + wire _target_T_315 = _ways_11_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_316 = _ways_11_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_317 = _ways_11_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_11_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_11_io_resp_carry, _ways_11_io_resp_pftAddr}; + wire _target_T_342 = _ways_12_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_343 = _ways_12_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_344 = _ways_12_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_12_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_12_io_resp_carry, _ways_12_io_resp_pftAddr}; + wire _target_T_369 = _ways_13_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_370 = _ways_13_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_371 = _ways_13_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_13_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_13_io_resp_carry, _ways_13_io_resp_pftAddr}; + wire _target_T_396 = _ways_14_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_397 = _ways_14_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_398 = _ways_14_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_14_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_14_io_resp_carry, _ways_14_io_resp_pftAddr}; + wire _target_T_423 = _ways_15_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_424 = _ways_15_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_425 = _ways_15_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_15_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_15_io_resp_carry, _ways_15_io_resp_pftAddr}; + wire _target_T_450 = _ways_16_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_451 = _ways_16_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_452 = _ways_16_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_16_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_16_io_resp_carry, _ways_16_io_resp_pftAddr}; + wire _target_T_477 = _ways_17_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_478 = _ways_17_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_479 = _ways_17_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_17_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_17_io_resp_carry, _ways_17_io_resp_pftAddr}; + wire _target_T_504 = _ways_18_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_505 = _ways_18_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_506 = _ways_18_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_18_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_18_io_resp_carry, _ways_18_io_resp_pftAddr}; + wire _target_T_531 = _ways_19_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_532 = _ways_19_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_533 = _ways_19_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_19_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_19_io_resp_carry, _ways_19_io_resp_pftAddr}; + wire _target_T_558 = _ways_20_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_559 = _ways_20_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_560 = _ways_20_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_20_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_20_io_resp_carry, _ways_20_io_resp_pftAddr}; + wire _target_T_585 = _ways_21_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_586 = _ways_21_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_587 = _ways_21_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_21_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_21_io_resp_carry, _ways_21_io_resp_pftAddr}; + wire _target_T_612 = _ways_22_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_613 = _ways_22_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_614 = _ways_22_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_22_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_22_io_resp_carry, _ways_22_io_resp_pftAddr}; + wire _target_T_639 = _ways_23_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_640 = _ways_23_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_641 = _ways_23_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_23_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_23_io_resp_carry, _ways_23_io_resp_pftAddr}; + wire _target_T_666 = _ways_24_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_667 = _ways_24_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_668 = _ways_24_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_24_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_24_io_resp_carry, _ways_24_io_resp_pftAddr}; + wire _target_T_693 = _ways_25_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_694 = _ways_25_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_695 = _ways_25_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_25_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_25_io_resp_carry, _ways_25_io_resp_pftAddr}; + wire _target_T_720 = _ways_26_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_721 = _ways_26_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_722 = _ways_26_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_26_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_26_io_resp_carry, _ways_26_io_resp_pftAddr}; + wire _target_T_747 = _ways_27_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_748 = _ways_27_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_749 = _ways_27_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_27_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_27_io_resp_carry, _ways_27_io_resp_pftAddr}; + wire _target_T_774 = _ways_28_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_775 = _ways_28_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_776 = _ways_28_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_28_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_28_io_resp_carry, _ways_28_io_resp_pftAddr}; + wire _target_T_801 = _ways_29_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_802 = _ways_29_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_803 = _ways_29_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_29_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_29_io_resp_carry, _ways_29_io_resp_pftAddr}; + wire _target_T_828 = _ways_30_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_829 = _ways_30_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_830 = _ways_30_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_30_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_30_io_resp_carry, _ways_30_io_resp_pftAddr}; + wire _target_T_855 = _ways_31_io_resp_tailSlot_tarStat == 2'h1; + wire _target_T_856 = _ways_31_io_resp_tailSlot_tarStat == 2'h2; + wire _target_T_857 = _ways_31_io_resp_tailSlot_tarStat == 2'h0; + wire s1_possible_full_preds_31_fallThroughErr = + {1'h0, s1_pc_dup_0[4:1]} >= {_ways_31_io_resp_carry, _ways_31_io_resp_pftAddr}; + wire _s1_hit_full_pred_T_157 = + _ways_0_io_resp_hit & _ways_0_io_resp_tailSlot_valid + & _ways_0_io_resp_tailSlot_sharing | _ways_1_io_resp_hit + & _ways_1_io_resp_tailSlot_valid & _ways_1_io_resp_tailSlot_sharing + | _ways_2_io_resp_hit & _ways_2_io_resp_tailSlot_valid + & _ways_2_io_resp_tailSlot_sharing | _ways_3_io_resp_hit + & _ways_3_io_resp_tailSlot_valid & _ways_3_io_resp_tailSlot_sharing + | _ways_4_io_resp_hit & _ways_4_io_resp_tailSlot_valid + & _ways_4_io_resp_tailSlot_sharing | _ways_5_io_resp_hit + & _ways_5_io_resp_tailSlot_valid & _ways_5_io_resp_tailSlot_sharing + | _ways_6_io_resp_hit & _ways_6_io_resp_tailSlot_valid + & _ways_6_io_resp_tailSlot_sharing | _ways_7_io_resp_hit + & _ways_7_io_resp_tailSlot_valid & _ways_7_io_resp_tailSlot_sharing + | _ways_8_io_resp_hit & _ways_8_io_resp_tailSlot_valid + & _ways_8_io_resp_tailSlot_sharing | _ways_9_io_resp_hit + & _ways_9_io_resp_tailSlot_valid & _ways_9_io_resp_tailSlot_sharing + | _ways_10_io_resp_hit & _ways_10_io_resp_tailSlot_valid + & _ways_10_io_resp_tailSlot_sharing | _ways_11_io_resp_hit + & _ways_11_io_resp_tailSlot_valid & _ways_11_io_resp_tailSlot_sharing + | _ways_12_io_resp_hit & _ways_12_io_resp_tailSlot_valid + & _ways_12_io_resp_tailSlot_sharing | _ways_13_io_resp_hit + & _ways_13_io_resp_tailSlot_valid & _ways_13_io_resp_tailSlot_sharing + | _ways_14_io_resp_hit & _ways_14_io_resp_tailSlot_valid + & _ways_14_io_resp_tailSlot_sharing | _ways_15_io_resp_hit + & _ways_15_io_resp_tailSlot_valid & _ways_15_io_resp_tailSlot_sharing + | _ways_16_io_resp_hit & _ways_16_io_resp_tailSlot_valid + & _ways_16_io_resp_tailSlot_sharing | _ways_17_io_resp_hit + & _ways_17_io_resp_tailSlot_valid & _ways_17_io_resp_tailSlot_sharing + | _ways_18_io_resp_hit & _ways_18_io_resp_tailSlot_valid + & _ways_18_io_resp_tailSlot_sharing | _ways_19_io_resp_hit + & _ways_19_io_resp_tailSlot_valid & _ways_19_io_resp_tailSlot_sharing + | _ways_20_io_resp_hit & _ways_20_io_resp_tailSlot_valid + & _ways_20_io_resp_tailSlot_sharing | _ways_21_io_resp_hit + & _ways_21_io_resp_tailSlot_valid & _ways_21_io_resp_tailSlot_sharing + | _ways_22_io_resp_hit & _ways_22_io_resp_tailSlot_valid + & _ways_22_io_resp_tailSlot_sharing | _ways_23_io_resp_hit + & _ways_23_io_resp_tailSlot_valid & _ways_23_io_resp_tailSlot_sharing + | _ways_24_io_resp_hit & _ways_24_io_resp_tailSlot_valid + & _ways_24_io_resp_tailSlot_sharing | _ways_25_io_resp_hit + & _ways_25_io_resp_tailSlot_valid & _ways_25_io_resp_tailSlot_sharing + | _ways_26_io_resp_hit & _ways_26_io_resp_tailSlot_valid + & _ways_26_io_resp_tailSlot_sharing | _ways_27_io_resp_hit + & _ways_27_io_resp_tailSlot_valid & _ways_27_io_resp_tailSlot_sharing + | _ways_28_io_resp_hit & _ways_28_io_resp_tailSlot_valid + & _ways_28_io_resp_tailSlot_sharing | _ways_29_io_resp_hit + & _ways_29_io_resp_tailSlot_valid & _ways_29_io_resp_tailSlot_sharing + | _ways_30_io_resp_hit & _ways_30_io_resp_tailSlot_valid + & _ways_30_io_resp_tailSlot_sharing | _ways_31_io_resp_hit + & _ways_31_io_resp_tailSlot_valid & _ways_31_io_resp_tailSlot_sharing; + wire [40:0] _s1_hit_full_pred_T_598 = + (_ways_0_io_resp_hit + ? (s1_possible_full_preds_0_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_0_io_resp_carry ? 36'(s1_pc_dup_0[40:5] + 36'h1) : s1_pc_dup_0[40:5], + _ways_0_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_1_io_resp_hit + ? (s1_possible_full_preds_1_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_1_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_1_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_2_io_resp_hit + ? (s1_possible_full_preds_2_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_2_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_2_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_3_io_resp_hit + ? (s1_possible_full_preds_3_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_3_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_3_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_4_io_resp_hit + ? (s1_possible_full_preds_4_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_4_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_4_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_5_io_resp_hit + ? (s1_possible_full_preds_5_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_5_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_5_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_6_io_resp_hit + ? (s1_possible_full_preds_6_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_6_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_6_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_7_io_resp_hit + ? (s1_possible_full_preds_7_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_7_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_7_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_8_io_resp_hit + ? (s1_possible_full_preds_8_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_8_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_8_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_9_io_resp_hit + ? (s1_possible_full_preds_9_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_9_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_9_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_10_io_resp_hit + ? (s1_possible_full_preds_10_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_10_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_10_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_11_io_resp_hit + ? (s1_possible_full_preds_11_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_11_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_11_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_12_io_resp_hit + ? (s1_possible_full_preds_12_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_12_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_12_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_13_io_resp_hit + ? (s1_possible_full_preds_13_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_13_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_13_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_14_io_resp_hit + ? (s1_possible_full_preds_14_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_14_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_14_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_15_io_resp_hit + ? (s1_possible_full_preds_15_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_15_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_15_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_16_io_resp_hit + ? (s1_possible_full_preds_16_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_16_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_16_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_17_io_resp_hit + ? (s1_possible_full_preds_17_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_17_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_17_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_18_io_resp_hit + ? (s1_possible_full_preds_18_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_18_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_18_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_19_io_resp_hit + ? (s1_possible_full_preds_19_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_19_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_19_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_20_io_resp_hit + ? (s1_possible_full_preds_20_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_20_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_20_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_21_io_resp_hit + ? (s1_possible_full_preds_21_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_21_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_21_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_22_io_resp_hit + ? (s1_possible_full_preds_22_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_22_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_22_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_23_io_resp_hit + ? (s1_possible_full_preds_23_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_23_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_23_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_24_io_resp_hit + ? (s1_possible_full_preds_24_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_24_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_24_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_25_io_resp_hit + ? (s1_possible_full_preds_25_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_25_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_25_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_26_io_resp_hit + ? (s1_possible_full_preds_26_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_26_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_26_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_27_io_resp_hit + ? (s1_possible_full_preds_27_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_27_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_27_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_28_io_resp_hit + ? (s1_possible_full_preds_28_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_28_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_28_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_29_io_resp_hit + ? (s1_possible_full_preds_29_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_29_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_29_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_30_io_resp_hit + ? (s1_possible_full_preds_30_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_30_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_30_io_resp_pftAddr, + 1'h0}) + : 41'h0) + | (_ways_31_io_resp_hit + ? (s1_possible_full_preds_31_fallThroughErr + ? _s1_possible_full_preds_31_fallThroughAddr_T + : {_ways_31_io_resp_carry + ? 36'(s1_pc_dup_0[40:5] + 36'h1) + : s1_pc_dup_0[40:5], + _ways_31_io_resp_pftAddr, + 1'h0}) + : 41'h0); + wire [3:0] _s1_hit_full_pred_T_661 = + (_ways_0_io_resp_hit ? _ways_0_io_resp_brSlots_0_offset : 4'h0) + | (_ways_1_io_resp_hit ? _ways_1_io_resp_brSlots_0_offset : 4'h0) + | (_ways_2_io_resp_hit ? _ways_2_io_resp_brSlots_0_offset : 4'h0) + | (_ways_3_io_resp_hit ? _ways_3_io_resp_brSlots_0_offset : 4'h0) + | (_ways_4_io_resp_hit ? _ways_4_io_resp_brSlots_0_offset : 4'h0) + | (_ways_5_io_resp_hit ? _ways_5_io_resp_brSlots_0_offset : 4'h0) + | (_ways_6_io_resp_hit ? _ways_6_io_resp_brSlots_0_offset : 4'h0) + | (_ways_7_io_resp_hit ? _ways_7_io_resp_brSlots_0_offset : 4'h0) + | (_ways_8_io_resp_hit ? _ways_8_io_resp_brSlots_0_offset : 4'h0) + | (_ways_9_io_resp_hit ? _ways_9_io_resp_brSlots_0_offset : 4'h0) + | (_ways_10_io_resp_hit ? _ways_10_io_resp_brSlots_0_offset : 4'h0) + | (_ways_11_io_resp_hit ? _ways_11_io_resp_brSlots_0_offset : 4'h0) + | (_ways_12_io_resp_hit ? _ways_12_io_resp_brSlots_0_offset : 4'h0) + | (_ways_13_io_resp_hit ? _ways_13_io_resp_brSlots_0_offset : 4'h0) + | (_ways_14_io_resp_hit ? _ways_14_io_resp_brSlots_0_offset : 4'h0) + | (_ways_15_io_resp_hit ? _ways_15_io_resp_brSlots_0_offset : 4'h0) + | (_ways_16_io_resp_hit ? _ways_16_io_resp_brSlots_0_offset : 4'h0) + | (_ways_17_io_resp_hit ? _ways_17_io_resp_brSlots_0_offset : 4'h0) + | (_ways_18_io_resp_hit ? _ways_18_io_resp_brSlots_0_offset : 4'h0) + | (_ways_19_io_resp_hit ? _ways_19_io_resp_brSlots_0_offset : 4'h0) + | (_ways_20_io_resp_hit ? _ways_20_io_resp_brSlots_0_offset : 4'h0) + | (_ways_21_io_resp_hit ? _ways_21_io_resp_brSlots_0_offset : 4'h0) + | (_ways_22_io_resp_hit ? _ways_22_io_resp_brSlots_0_offset : 4'h0) + | (_ways_23_io_resp_hit ? _ways_23_io_resp_brSlots_0_offset : 4'h0) + | (_ways_24_io_resp_hit ? _ways_24_io_resp_brSlots_0_offset : 4'h0) + | (_ways_25_io_resp_hit ? _ways_25_io_resp_brSlots_0_offset : 4'h0) + | (_ways_26_io_resp_hit ? _ways_26_io_resp_brSlots_0_offset : 4'h0) + | (_ways_27_io_resp_hit ? _ways_27_io_resp_brSlots_0_offset : 4'h0) + | (_ways_28_io_resp_hit ? _ways_28_io_resp_brSlots_0_offset : 4'h0) + | (_ways_29_io_resp_hit ? _ways_29_io_resp_brSlots_0_offset : 4'h0) + | (_ways_30_io_resp_hit ? _ways_30_io_resp_brSlots_0_offset : 4'h0) + | (_ways_31_io_resp_hit ? _ways_31_io_resp_brSlots_0_offset : 4'h0); + wire [3:0] _s1_hit_full_pred_T_724 = + (_ways_0_io_resp_hit ? _ways_0_io_resp_tailSlot_offset : 4'h0) + | (_ways_1_io_resp_hit ? _ways_1_io_resp_tailSlot_offset : 4'h0) + | (_ways_2_io_resp_hit ? _ways_2_io_resp_tailSlot_offset : 4'h0) + | (_ways_3_io_resp_hit ? _ways_3_io_resp_tailSlot_offset : 4'h0) + | (_ways_4_io_resp_hit ? _ways_4_io_resp_tailSlot_offset : 4'h0) + | (_ways_5_io_resp_hit ? _ways_5_io_resp_tailSlot_offset : 4'h0) + | (_ways_6_io_resp_hit ? _ways_6_io_resp_tailSlot_offset : 4'h0) + | (_ways_7_io_resp_hit ? _ways_7_io_resp_tailSlot_offset : 4'h0) + | (_ways_8_io_resp_hit ? _ways_8_io_resp_tailSlot_offset : 4'h0) + | (_ways_9_io_resp_hit ? _ways_9_io_resp_tailSlot_offset : 4'h0) + | (_ways_10_io_resp_hit ? _ways_10_io_resp_tailSlot_offset : 4'h0) + | (_ways_11_io_resp_hit ? _ways_11_io_resp_tailSlot_offset : 4'h0) + | (_ways_12_io_resp_hit ? _ways_12_io_resp_tailSlot_offset : 4'h0) + | (_ways_13_io_resp_hit ? _ways_13_io_resp_tailSlot_offset : 4'h0) + | (_ways_14_io_resp_hit ? _ways_14_io_resp_tailSlot_offset : 4'h0) + | (_ways_15_io_resp_hit ? _ways_15_io_resp_tailSlot_offset : 4'h0) + | (_ways_16_io_resp_hit ? _ways_16_io_resp_tailSlot_offset : 4'h0) + | (_ways_17_io_resp_hit ? _ways_17_io_resp_tailSlot_offset : 4'h0) + | (_ways_18_io_resp_hit ? _ways_18_io_resp_tailSlot_offset : 4'h0) + | (_ways_19_io_resp_hit ? _ways_19_io_resp_tailSlot_offset : 4'h0) + | (_ways_20_io_resp_hit ? _ways_20_io_resp_tailSlot_offset : 4'h0) + | (_ways_21_io_resp_hit ? _ways_21_io_resp_tailSlot_offset : 4'h0) + | (_ways_22_io_resp_hit ? _ways_22_io_resp_tailSlot_offset : 4'h0) + | (_ways_23_io_resp_hit ? _ways_23_io_resp_tailSlot_offset : 4'h0) + | (_ways_24_io_resp_hit ? _ways_24_io_resp_tailSlot_offset : 4'h0) + | (_ways_25_io_resp_hit ? _ways_25_io_resp_tailSlot_offset : 4'h0) + | (_ways_26_io_resp_hit ? _ways_26_io_resp_tailSlot_offset : 4'h0) + | (_ways_27_io_resp_hit ? _ways_27_io_resp_tailSlot_offset : 4'h0) + | (_ways_28_io_resp_hit ? _ways_28_io_resp_tailSlot_offset : 4'h0) + | (_ways_29_io_resp_hit ? _ways_29_io_resp_tailSlot_offset : 4'h0) + | (_ways_30_io_resp_hit ? _ways_30_io_resp_tailSlot_offset : 4'h0) + | (_ways_31_io_resp_hit ? _ways_31_io_resp_tailSlot_offset : 4'h0); + wire [40:0] _GEN = + (_ways_0_io_resp_hit + ? {(_ways_0_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_0_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_0_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_0_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_1_io_resp_hit + ? {(_ways_1_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_1_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_1_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_1_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_2_io_resp_hit + ? {(_ways_2_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_2_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_2_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_2_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_3_io_resp_hit + ? {(_ways_3_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_3_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_3_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_3_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_4_io_resp_hit + ? {(_ways_4_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_4_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_4_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_4_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_5_io_resp_hit + ? {(_ways_5_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_5_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_5_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_5_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_6_io_resp_hit + ? {(_ways_6_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_6_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_6_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_6_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_7_io_resp_hit + ? {(_ways_7_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_7_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_7_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_7_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_8_io_resp_hit + ? {(_ways_8_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_8_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_8_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_8_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_9_io_resp_hit + ? {(_ways_9_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_9_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_9_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_9_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_10_io_resp_hit + ? {(_ways_10_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_10_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_10_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_10_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_11_io_resp_hit + ? {(_ways_11_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_11_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_11_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_11_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_12_io_resp_hit + ? {(_ways_12_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_12_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_12_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_12_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_13_io_resp_hit + ? {(_ways_13_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_13_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_13_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_13_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_14_io_resp_hit + ? {(_ways_14_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_14_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_14_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_14_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_15_io_resp_hit + ? {(_ways_15_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_15_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_15_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_15_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0); + wire [40:0] _GEN_0 = + (_ways_16_io_resp_hit + ? {(_ways_16_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_16_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_16_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_16_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_17_io_resp_hit + ? {(_ways_17_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_17_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_17_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_17_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_18_io_resp_hit + ? {(_ways_18_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_18_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_18_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_18_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_19_io_resp_hit + ? {(_ways_19_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_19_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_19_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_19_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_20_io_resp_hit + ? {(_ways_20_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_20_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_20_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_20_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_21_io_resp_hit + ? {(_ways_21_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_21_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_21_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_21_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_22_io_resp_hit + ? {(_ways_22_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_22_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_22_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_22_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_23_io_resp_hit + ? {(_ways_23_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_23_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_23_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_23_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_24_io_resp_hit + ? {(_ways_24_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_24_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_24_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_24_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_25_io_resp_hit + ? {(_ways_25_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_25_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_25_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_25_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_26_io_resp_hit + ? {(_ways_26_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_26_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_26_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_26_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_27_io_resp_hit + ? {(_ways_27_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_27_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_27_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_27_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_28_io_resp_hit + ? {(_ways_28_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_28_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_28_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_28_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_29_io_resp_hit + ? {(_ways_29_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_29_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_29_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_29_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_30_io_resp_hit + ? {(_ways_30_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_30_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_30_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_30_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0) + | (_ways_31_io_resp_hit + ? {(_ways_31_io_resp_brSlots_0_tarStat == 2'h1 + ? 28'(s1_pc_dup_0[40:13] + 28'h1) + : 28'h0) + | (_ways_31_io_resp_brSlots_0_tarStat == 2'h2 + ? 28'(s1_pc_dup_0[40:13] - 28'h1) + : 28'h0) + | (_ways_31_io_resp_brSlots_0_tarStat == 2'h0 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_31_io_resp_brSlots_0_lower, + 1'h0} + : 41'h0); + wire [40:0] _s1_hit_full_pred_T_850 = _GEN | _GEN_0; + wire [40:0] _GEN_1 = + (_ways_0_io_resp_hit + ? {_ways_0_io_resp_tailSlot_sharing + ? {(_target_T_18 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_19 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_20 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_0_io_resp_tailSlot_lower[11:0]} + : {(_target_T_18 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_19 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_20 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_0_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_1_io_resp_hit + ? {_ways_1_io_resp_tailSlot_sharing + ? {(_target_T_45 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_46 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_47 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_1_io_resp_tailSlot_lower[11:0]} + : {(_target_T_45 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_46 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_47 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_1_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_2_io_resp_hit + ? {_ways_2_io_resp_tailSlot_sharing + ? {(_target_T_72 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_73 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_74 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_2_io_resp_tailSlot_lower[11:0]} + : {(_target_T_72 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_73 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_74 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_2_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_3_io_resp_hit + ? {_ways_3_io_resp_tailSlot_sharing + ? {(_target_T_99 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_100 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_101 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_3_io_resp_tailSlot_lower[11:0]} + : {(_target_T_99 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_100 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_101 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_3_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_4_io_resp_hit + ? {_ways_4_io_resp_tailSlot_sharing + ? {(_target_T_126 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_127 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_128 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_4_io_resp_tailSlot_lower[11:0]} + : {(_target_T_126 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_127 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_128 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_4_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_5_io_resp_hit + ? {_ways_5_io_resp_tailSlot_sharing + ? {(_target_T_153 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_154 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_155 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_5_io_resp_tailSlot_lower[11:0]} + : {(_target_T_153 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_154 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_155 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_5_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_6_io_resp_hit + ? {_ways_6_io_resp_tailSlot_sharing + ? {(_target_T_180 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_181 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_182 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_6_io_resp_tailSlot_lower[11:0]} + : {(_target_T_180 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_181 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_182 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_6_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_7_io_resp_hit + ? {_ways_7_io_resp_tailSlot_sharing + ? {(_target_T_207 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_208 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_209 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_7_io_resp_tailSlot_lower[11:0]} + : {(_target_T_207 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_208 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_209 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_7_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_8_io_resp_hit + ? {_ways_8_io_resp_tailSlot_sharing + ? {(_target_T_234 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_235 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_236 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_8_io_resp_tailSlot_lower[11:0]} + : {(_target_T_234 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_235 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_236 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_8_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_9_io_resp_hit + ? {_ways_9_io_resp_tailSlot_sharing + ? {(_target_T_261 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_262 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_263 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_9_io_resp_tailSlot_lower[11:0]} + : {(_target_T_261 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_262 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_263 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_9_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_10_io_resp_hit + ? {_ways_10_io_resp_tailSlot_sharing + ? {(_target_T_288 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_289 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_290 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_10_io_resp_tailSlot_lower[11:0]} + : {(_target_T_288 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_289 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_290 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_10_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_11_io_resp_hit + ? {_ways_11_io_resp_tailSlot_sharing + ? {(_target_T_315 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_316 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_317 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_11_io_resp_tailSlot_lower[11:0]} + : {(_target_T_315 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_316 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_317 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_11_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_12_io_resp_hit + ? {_ways_12_io_resp_tailSlot_sharing + ? {(_target_T_342 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_343 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_344 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_12_io_resp_tailSlot_lower[11:0]} + : {(_target_T_342 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_343 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_344 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_12_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_13_io_resp_hit + ? {_ways_13_io_resp_tailSlot_sharing + ? {(_target_T_369 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_370 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_371 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_13_io_resp_tailSlot_lower[11:0]} + : {(_target_T_369 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_370 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_371 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_13_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_14_io_resp_hit + ? {_ways_14_io_resp_tailSlot_sharing + ? {(_target_T_396 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_397 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_398 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_14_io_resp_tailSlot_lower[11:0]} + : {(_target_T_396 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_397 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_398 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_14_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_15_io_resp_hit + ? {_ways_15_io_resp_tailSlot_sharing + ? {(_target_T_423 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_424 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_425 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_15_io_resp_tailSlot_lower[11:0]} + : {(_target_T_423 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_424 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_425 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_15_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0); + wire [40:0] _GEN_2 = + (_ways_16_io_resp_hit + ? {_ways_16_io_resp_tailSlot_sharing + ? {(_target_T_450 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_451 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_452 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_16_io_resp_tailSlot_lower[11:0]} + : {(_target_T_450 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_451 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_452 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_16_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_17_io_resp_hit + ? {_ways_17_io_resp_tailSlot_sharing + ? {(_target_T_477 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_478 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_479 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_17_io_resp_tailSlot_lower[11:0]} + : {(_target_T_477 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_478 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_479 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_17_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_18_io_resp_hit + ? {_ways_18_io_resp_tailSlot_sharing + ? {(_target_T_504 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_505 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_506 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_18_io_resp_tailSlot_lower[11:0]} + : {(_target_T_504 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_505 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_506 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_18_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_19_io_resp_hit + ? {_ways_19_io_resp_tailSlot_sharing + ? {(_target_T_531 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_532 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_533 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_19_io_resp_tailSlot_lower[11:0]} + : {(_target_T_531 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_532 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_533 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_19_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_20_io_resp_hit + ? {_ways_20_io_resp_tailSlot_sharing + ? {(_target_T_558 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_559 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_560 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_20_io_resp_tailSlot_lower[11:0]} + : {(_target_T_558 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_559 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_560 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_20_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_21_io_resp_hit + ? {_ways_21_io_resp_tailSlot_sharing + ? {(_target_T_585 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_586 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_587 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_21_io_resp_tailSlot_lower[11:0]} + : {(_target_T_585 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_586 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_587 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_21_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_22_io_resp_hit + ? {_ways_22_io_resp_tailSlot_sharing + ? {(_target_T_612 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_613 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_614 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_22_io_resp_tailSlot_lower[11:0]} + : {(_target_T_612 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_613 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_614 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_22_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_23_io_resp_hit + ? {_ways_23_io_resp_tailSlot_sharing + ? {(_target_T_639 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_640 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_641 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_23_io_resp_tailSlot_lower[11:0]} + : {(_target_T_639 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_640 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_641 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_23_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_24_io_resp_hit + ? {_ways_24_io_resp_tailSlot_sharing + ? {(_target_T_666 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_667 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_668 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_24_io_resp_tailSlot_lower[11:0]} + : {(_target_T_666 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_667 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_668 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_24_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_25_io_resp_hit + ? {_ways_25_io_resp_tailSlot_sharing + ? {(_target_T_693 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_694 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_695 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_25_io_resp_tailSlot_lower[11:0]} + : {(_target_T_693 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_694 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_695 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_25_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_26_io_resp_hit + ? {_ways_26_io_resp_tailSlot_sharing + ? {(_target_T_720 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_721 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_722 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_26_io_resp_tailSlot_lower[11:0]} + : {(_target_T_720 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_721 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_722 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_26_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_27_io_resp_hit + ? {_ways_27_io_resp_tailSlot_sharing + ? {(_target_T_747 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_748 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_749 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_27_io_resp_tailSlot_lower[11:0]} + : {(_target_T_747 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_748 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_749 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_27_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_28_io_resp_hit + ? {_ways_28_io_resp_tailSlot_sharing + ? {(_target_T_774 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_775 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_776 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_28_io_resp_tailSlot_lower[11:0]} + : {(_target_T_774 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_775 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_776 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_28_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_29_io_resp_hit + ? {_ways_29_io_resp_tailSlot_sharing + ? {(_target_T_801 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_802 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_803 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_29_io_resp_tailSlot_lower[11:0]} + : {(_target_T_801 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_802 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_803 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_29_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_30_io_resp_hit + ? {_ways_30_io_resp_tailSlot_sharing + ? {(_target_T_828 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_829 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_830 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_30_io_resp_tailSlot_lower[11:0]} + : {(_target_T_828 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_829 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_830 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_30_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0) + | (_ways_31_io_resp_hit + ? {_ways_31_io_resp_tailSlot_sharing + ? {(_target_T_855 ? 28'(s1_pc_dup_0[40:13] + 28'h1) : 28'h0) + | (_target_T_856 ? 28'(s1_pc_dup_0[40:13] - 28'h1) : 28'h0) + | (_target_T_857 ? s1_pc_dup_0[40:13] : 28'h0), + _ways_31_io_resp_tailSlot_lower[11:0]} + : {(_target_T_855 ? 20'(s1_pc_dup_0[40:21] + 20'h1) : 20'h0) + | (_target_T_856 ? 20'(s1_pc_dup_0[40:21] - 20'h1) : 20'h0) + | (_target_T_857 ? s1_pc_dup_0[40:21] : 20'h0), + _ways_31_io_resp_tailSlot_lower}, + 1'h0} + : 41'h0); + wire [40:0] _s1_hit_full_pred_T_913 = _GEN_1 | _GEN_2; + wire _s1_hit_full_pred_T_976 = + _ways_0_io_resp_hit & _ways_0_io_resp_brSlots_0_valid | _ways_1_io_resp_hit + & _ways_1_io_resp_brSlots_0_valid | _ways_2_io_resp_hit + & _ways_2_io_resp_brSlots_0_valid | _ways_3_io_resp_hit + & _ways_3_io_resp_brSlots_0_valid | _ways_4_io_resp_hit + & _ways_4_io_resp_brSlots_0_valid | _ways_5_io_resp_hit + & _ways_5_io_resp_brSlots_0_valid | _ways_6_io_resp_hit + & _ways_6_io_resp_brSlots_0_valid | _ways_7_io_resp_hit + & _ways_7_io_resp_brSlots_0_valid | _ways_8_io_resp_hit + & _ways_8_io_resp_brSlots_0_valid | _ways_9_io_resp_hit + & _ways_9_io_resp_brSlots_0_valid | _ways_10_io_resp_hit + & _ways_10_io_resp_brSlots_0_valid | _ways_11_io_resp_hit + & _ways_11_io_resp_brSlots_0_valid | _ways_12_io_resp_hit + & _ways_12_io_resp_brSlots_0_valid | _ways_13_io_resp_hit + & _ways_13_io_resp_brSlots_0_valid | _ways_14_io_resp_hit + & _ways_14_io_resp_brSlots_0_valid | _ways_15_io_resp_hit + & _ways_15_io_resp_brSlots_0_valid | _ways_16_io_resp_hit + & _ways_16_io_resp_brSlots_0_valid | _ways_17_io_resp_hit + & _ways_17_io_resp_brSlots_0_valid | _ways_18_io_resp_hit + & _ways_18_io_resp_brSlots_0_valid | _ways_19_io_resp_hit + & _ways_19_io_resp_brSlots_0_valid | _ways_20_io_resp_hit + & _ways_20_io_resp_brSlots_0_valid | _ways_21_io_resp_hit + & _ways_21_io_resp_brSlots_0_valid | _ways_22_io_resp_hit + & _ways_22_io_resp_brSlots_0_valid | _ways_23_io_resp_hit + & _ways_23_io_resp_brSlots_0_valid | _ways_24_io_resp_hit + & _ways_24_io_resp_brSlots_0_valid | _ways_25_io_resp_hit + & _ways_25_io_resp_brSlots_0_valid | _ways_26_io_resp_hit + & _ways_26_io_resp_brSlots_0_valid | _ways_27_io_resp_hit + & _ways_27_io_resp_brSlots_0_valid | _ways_28_io_resp_hit + & _ways_28_io_resp_brSlots_0_valid | _ways_29_io_resp_hit + & _ways_29_io_resp_brSlots_0_valid | _ways_30_io_resp_hit + & _ways_30_io_resp_brSlots_0_valid | _ways_31_io_resp_hit + & _ways_31_io_resp_brSlots_0_valid; + wire _s1_hit_full_pred_T_1039 = + _ways_0_io_resp_hit & _ways_0_io_resp_tailSlot_valid | _ways_1_io_resp_hit + & _ways_1_io_resp_tailSlot_valid | _ways_2_io_resp_hit + & _ways_2_io_resp_tailSlot_valid | _ways_3_io_resp_hit + & _ways_3_io_resp_tailSlot_valid | _ways_4_io_resp_hit + & _ways_4_io_resp_tailSlot_valid | _ways_5_io_resp_hit + & _ways_5_io_resp_tailSlot_valid | _ways_6_io_resp_hit + & _ways_6_io_resp_tailSlot_valid | _ways_7_io_resp_hit + & _ways_7_io_resp_tailSlot_valid | _ways_8_io_resp_hit + & _ways_8_io_resp_tailSlot_valid | _ways_9_io_resp_hit + & _ways_9_io_resp_tailSlot_valid | _ways_10_io_resp_hit + & _ways_10_io_resp_tailSlot_valid | _ways_11_io_resp_hit + & _ways_11_io_resp_tailSlot_valid | _ways_12_io_resp_hit + & _ways_12_io_resp_tailSlot_valid | _ways_13_io_resp_hit + & _ways_13_io_resp_tailSlot_valid | _ways_14_io_resp_hit + & _ways_14_io_resp_tailSlot_valid | _ways_15_io_resp_hit + & _ways_15_io_resp_tailSlot_valid | _ways_16_io_resp_hit + & _ways_16_io_resp_tailSlot_valid | _ways_17_io_resp_hit + & _ways_17_io_resp_tailSlot_valid | _ways_18_io_resp_hit + & _ways_18_io_resp_tailSlot_valid | _ways_19_io_resp_hit + & _ways_19_io_resp_tailSlot_valid | _ways_20_io_resp_hit + & _ways_20_io_resp_tailSlot_valid | _ways_21_io_resp_hit + & _ways_21_io_resp_tailSlot_valid | _ways_22_io_resp_hit + & _ways_22_io_resp_tailSlot_valid | _ways_23_io_resp_hit + & _ways_23_io_resp_tailSlot_valid | _ways_24_io_resp_hit + & _ways_24_io_resp_tailSlot_valid | _ways_25_io_resp_hit + & _ways_25_io_resp_tailSlot_valid | _ways_26_io_resp_hit + & _ways_26_io_resp_tailSlot_valid | _ways_27_io_resp_hit + & _ways_27_io_resp_tailSlot_valid | _ways_28_io_resp_hit + & _ways_28_io_resp_tailSlot_valid | _ways_29_io_resp_hit + & _ways_29_io_resp_tailSlot_valid | _ways_30_io_resp_hit + & _ways_30_io_resp_tailSlot_valid | _ways_31_io_resp_hit + & _ways_31_io_resp_tailSlot_valid; + wire _s1_hit_full_pred_T_1102 = + _ways_0_io_resp_hit & (ctrs_0_0[1] | _ways_0_io_resp_always_taken_0) + | _ways_1_io_resp_hit & (ctrs_1_0[1] | _ways_1_io_resp_always_taken_0) + | _ways_2_io_resp_hit & (ctrs_2_0[1] | _ways_2_io_resp_always_taken_0) + | _ways_3_io_resp_hit & (ctrs_3_0[1] | _ways_3_io_resp_always_taken_0) + | _ways_4_io_resp_hit & (ctrs_4_0[1] | _ways_4_io_resp_always_taken_0) + | _ways_5_io_resp_hit & (ctrs_5_0[1] | _ways_5_io_resp_always_taken_0) + | _ways_6_io_resp_hit & (ctrs_6_0[1] | _ways_6_io_resp_always_taken_0) + | _ways_7_io_resp_hit & (ctrs_7_0[1] | _ways_7_io_resp_always_taken_0) + | _ways_8_io_resp_hit & (ctrs_8_0[1] | _ways_8_io_resp_always_taken_0) + | _ways_9_io_resp_hit & (ctrs_9_0[1] | _ways_9_io_resp_always_taken_0) + | _ways_10_io_resp_hit & (ctrs_10_0[1] | _ways_10_io_resp_always_taken_0) + | _ways_11_io_resp_hit & (ctrs_11_0[1] | _ways_11_io_resp_always_taken_0) + | _ways_12_io_resp_hit & (ctrs_12_0[1] | _ways_12_io_resp_always_taken_0) + | _ways_13_io_resp_hit & (ctrs_13_0[1] | _ways_13_io_resp_always_taken_0) + | _ways_14_io_resp_hit & (ctrs_14_0[1] | _ways_14_io_resp_always_taken_0) + | _ways_15_io_resp_hit & (ctrs_15_0[1] | _ways_15_io_resp_always_taken_0) + | _ways_16_io_resp_hit & (ctrs_16_0[1] | _ways_16_io_resp_always_taken_0) + | _ways_17_io_resp_hit & (ctrs_17_0[1] | _ways_17_io_resp_always_taken_0) + | _ways_18_io_resp_hit & (ctrs_18_0[1] | _ways_18_io_resp_always_taken_0) + | _ways_19_io_resp_hit & (ctrs_19_0[1] | _ways_19_io_resp_always_taken_0) + | _ways_20_io_resp_hit & (ctrs_20_0[1] | _ways_20_io_resp_always_taken_0) + | _ways_21_io_resp_hit & (ctrs_21_0[1] | _ways_21_io_resp_always_taken_0) + | _ways_22_io_resp_hit & (ctrs_22_0[1] | _ways_22_io_resp_always_taken_0) + | _ways_23_io_resp_hit & (ctrs_23_0[1] | _ways_23_io_resp_always_taken_0) + | _ways_24_io_resp_hit & (ctrs_24_0[1] | _ways_24_io_resp_always_taken_0) + | _ways_25_io_resp_hit & (ctrs_25_0[1] | _ways_25_io_resp_always_taken_0) + | _ways_26_io_resp_hit & (ctrs_26_0[1] | _ways_26_io_resp_always_taken_0) + | _ways_27_io_resp_hit & (ctrs_27_0[1] | _ways_27_io_resp_always_taken_0) + | _ways_28_io_resp_hit & (ctrs_28_0[1] | _ways_28_io_resp_always_taken_0) + | _ways_29_io_resp_hit & (ctrs_29_0[1] | _ways_29_io_resp_always_taken_0) + | _ways_30_io_resp_hit & (ctrs_30_0[1] | _ways_30_io_resp_always_taken_0) + | _ways_31_io_resp_hit & (ctrs_31_0[1] | _ways_31_io_resp_always_taken_0); + wire _s1_hit_full_pred_T_1165 = + _ways_0_io_resp_hit & (ctrs_0_1[1] | _ways_0_io_resp_always_taken_1) + | _ways_1_io_resp_hit & (ctrs_1_1[1] | _ways_1_io_resp_always_taken_1) + | _ways_2_io_resp_hit & (ctrs_2_1[1] | _ways_2_io_resp_always_taken_1) + | _ways_3_io_resp_hit & (ctrs_3_1[1] | _ways_3_io_resp_always_taken_1) + | _ways_4_io_resp_hit & (ctrs_4_1[1] | _ways_4_io_resp_always_taken_1) + | _ways_5_io_resp_hit & (ctrs_5_1[1] | _ways_5_io_resp_always_taken_1) + | _ways_6_io_resp_hit & (ctrs_6_1[1] | _ways_6_io_resp_always_taken_1) + | _ways_7_io_resp_hit & (ctrs_7_1[1] | _ways_7_io_resp_always_taken_1) + | _ways_8_io_resp_hit & (ctrs_8_1[1] | _ways_8_io_resp_always_taken_1) + | _ways_9_io_resp_hit & (ctrs_9_1[1] | _ways_9_io_resp_always_taken_1) + | _ways_10_io_resp_hit & (ctrs_10_1[1] | _ways_10_io_resp_always_taken_1) + | _ways_11_io_resp_hit & (ctrs_11_1[1] | _ways_11_io_resp_always_taken_1) + | _ways_12_io_resp_hit & (ctrs_12_1[1] | _ways_12_io_resp_always_taken_1) + | _ways_13_io_resp_hit & (ctrs_13_1[1] | _ways_13_io_resp_always_taken_1) + | _ways_14_io_resp_hit & (ctrs_14_1[1] | _ways_14_io_resp_always_taken_1) + | _ways_15_io_resp_hit & (ctrs_15_1[1] | _ways_15_io_resp_always_taken_1) + | _ways_16_io_resp_hit & (ctrs_16_1[1] | _ways_16_io_resp_always_taken_1) + | _ways_17_io_resp_hit & (ctrs_17_1[1] | _ways_17_io_resp_always_taken_1) + | _ways_18_io_resp_hit & (ctrs_18_1[1] | _ways_18_io_resp_always_taken_1) + | _ways_19_io_resp_hit & (ctrs_19_1[1] | _ways_19_io_resp_always_taken_1) + | _ways_20_io_resp_hit & (ctrs_20_1[1] | _ways_20_io_resp_always_taken_1) + | _ways_21_io_resp_hit & (ctrs_21_1[1] | _ways_21_io_resp_always_taken_1) + | _ways_22_io_resp_hit & (ctrs_22_1[1] | _ways_22_io_resp_always_taken_1) + | _ways_23_io_resp_hit & (ctrs_23_1[1] | _ways_23_io_resp_always_taken_1) + | _ways_24_io_resp_hit & (ctrs_24_1[1] | _ways_24_io_resp_always_taken_1) + | _ways_25_io_resp_hit & (ctrs_25_1[1] | _ways_25_io_resp_always_taken_1) + | _ways_26_io_resp_hit & (ctrs_26_1[1] | _ways_26_io_resp_always_taken_1) + | _ways_27_io_resp_hit & (ctrs_27_1[1] | _ways_27_io_resp_always_taken_1) + | _ways_28_io_resp_hit & (ctrs_28_1[1] | _ways_28_io_resp_always_taken_1) + | _ways_29_io_resp_hit & (ctrs_29_1[1] | _ways_29_io_resp_always_taken_1) + | _ways_30_io_resp_hit & (ctrs_30_1[1] | _ways_30_io_resp_always_taken_1) + | _ways_31_io_resp_hit & (ctrs_31_1[1] | _ways_31_io_resp_always_taken_1); + reg fauftb_enable; + wire io_out_s1_full_pred_3_hit_0 = (|s1_hit_oh) & fauftb_enable; + reg resp_meta_hit_r; + reg [4:0] resp_meta_pred_way_r; + reg replacer_touch_ways_0_valid_REG; + reg [4:0] replacer_touch_ways_0_bits_r; + reg u_s1_valid; + reg [15:0] u_s1_tag; + reg [31:0] u_s1_hit_oh; + reg u_s1_hit; + wire [31:0] u_s1_write_way_oh = + u_s1_hit + ? u_s1_hit_oh + : 32'h1 + << {27'h0, + state_reg[30], + state_reg[30] + ? {state_reg[29], + state_reg[29] + ? {state_reg[28], + state_reg[28] + ? {state_reg[27], state_reg[27] ? state_reg[26] : state_reg[25]} + : {state_reg[24], state_reg[24] ? state_reg[23] : state_reg[22]}} + : {state_reg[21], + state_reg[21] + ? {state_reg[20], state_reg[20] ? state_reg[19] : state_reg[18]} + : {state_reg[17], state_reg[17] ? state_reg[16] : state_reg[15]}}} + : {state_reg[14], + state_reg[14] + ? {state_reg[13], + state_reg[13] + ? {state_reg[12], state_reg[12] ? state_reg[11] : state_reg[10]} + : {state_reg[9], state_reg[9] ? state_reg[8] : state_reg[7]}} + : {state_reg[6], + state_reg[6] + ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]} + : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}}}; + reg [3:0] u_s1_ftb_entry_brSlots_0_offset; + reg [11:0] u_s1_ftb_entry_brSlots_0_lower; + reg [1:0] u_s1_ftb_entry_brSlots_0_tarStat; + reg u_s1_ftb_entry_brSlots_0_valid; + reg [3:0] u_s1_ftb_entry_tailSlot_offset; + reg [19:0] u_s1_ftb_entry_tailSlot_lower; + reg [1:0] u_s1_ftb_entry_tailSlot_tarStat; + reg u_s1_ftb_entry_tailSlot_sharing; + reg u_s1_ftb_entry_tailSlot_valid; + reg [3:0] u_s1_ftb_entry_pftAddr; + reg u_s1_ftb_entry_carry; + reg u_s1_ftb_entry_always_taken_0; + reg u_s1_ftb_entry_always_taken_1; + wire u_s1_ways_write_valid_0 = u_s1_write_way_oh[0] & u_s1_valid; + wire u_s1_ways_write_valid_1 = u_s1_write_way_oh[1] & u_s1_valid; + wire u_s1_ways_write_valid_2 = u_s1_write_way_oh[2] & u_s1_valid; + wire u_s1_ways_write_valid_3 = u_s1_write_way_oh[3] & u_s1_valid; + wire u_s1_ways_write_valid_4 = u_s1_write_way_oh[4] & u_s1_valid; + wire u_s1_ways_write_valid_5 = u_s1_write_way_oh[5] & u_s1_valid; + wire u_s1_ways_write_valid_6 = u_s1_write_way_oh[6] & u_s1_valid; + wire u_s1_ways_write_valid_7 = u_s1_write_way_oh[7] & u_s1_valid; + wire u_s1_ways_write_valid_8 = u_s1_write_way_oh[8] & u_s1_valid; + wire u_s1_ways_write_valid_9 = u_s1_write_way_oh[9] & u_s1_valid; + wire u_s1_ways_write_valid_10 = u_s1_write_way_oh[10] & u_s1_valid; + wire u_s1_ways_write_valid_11 = u_s1_write_way_oh[11] & u_s1_valid; + wire u_s1_ways_write_valid_12 = u_s1_write_way_oh[12] & u_s1_valid; + wire u_s1_ways_write_valid_13 = u_s1_write_way_oh[13] & u_s1_valid; + wire u_s1_ways_write_valid_14 = u_s1_write_way_oh[14] & u_s1_valid; + wire u_s1_ways_write_valid_15 = u_s1_write_way_oh[15] & u_s1_valid; + wire u_s1_ways_write_valid_16 = u_s1_write_way_oh[16] & u_s1_valid; + wire u_s1_ways_write_valid_17 = u_s1_write_way_oh[17] & u_s1_valid; + wire u_s1_ways_write_valid_18 = u_s1_write_way_oh[18] & u_s1_valid; + wire u_s1_ways_write_valid_19 = u_s1_write_way_oh[19] & u_s1_valid; + wire u_s1_ways_write_valid_20 = u_s1_write_way_oh[20] & u_s1_valid; + wire u_s1_ways_write_valid_21 = u_s1_write_way_oh[21] & u_s1_valid; + wire u_s1_ways_write_valid_22 = u_s1_write_way_oh[22] & u_s1_valid; + wire u_s1_ways_write_valid_23 = u_s1_write_way_oh[23] & u_s1_valid; + wire u_s1_ways_write_valid_24 = u_s1_write_way_oh[24] & u_s1_valid; + wire u_s1_ways_write_valid_25 = u_s1_write_way_oh[25] & u_s1_valid; + wire u_s1_ways_write_valid_26 = u_s1_write_way_oh[26] & u_s1_valid; + wire u_s1_ways_write_valid_27 = u_s1_write_way_oh[27] & u_s1_valid; + wire u_s1_ways_write_valid_28 = u_s1_write_way_oh[28] & u_s1_valid; + wire u_s1_ways_write_valid_29 = u_s1_write_way_oh[29] & u_s1_valid; + wire u_s1_ways_write_valid_30 = u_s1_write_way_oh[30] & u_s1_valid; + wire u_s1_ways_write_valid_31 = u_s1_write_way_oh[31] & u_s1_valid; + reg u_s1_br_update_valids_0; + reg u_s1_br_update_valids_1; + reg u_s1_br_takens_0; + reg u_s1_br_takens_1; + reg io_perf_0_value_REG; + reg io_perf_0_value_REG_1; + reg io_perf_1_value_REG; + reg io_perf_1_value_REG_1; + wire [40:0] _GEN_3 = {5'h0, _reset_vector_delay_io_out}; + wire [31:0] u_s0_hit_oh = + {_ways_31_io_update_hit, + _ways_30_io_update_hit, + _ways_29_io_update_hit, + _ways_28_io_update_hit, + _ways_27_io_update_hit, + _ways_26_io_update_hit, + _ways_25_io_update_hit, + _ways_24_io_update_hit, + _ways_23_io_update_hit, + _ways_22_io_update_hit, + _ways_21_io_update_hit, + _ways_20_io_update_hit, + _ways_19_io_update_hit, + _ways_18_io_update_hit, + _ways_17_io_update_hit, + _ways_16_io_update_hit, + _ways_15_io_update_hit, + _ways_14_io_update_hit, + _ways_13_io_update_hit, + _ways_12_io_update_hit, + _ways_11_io_update_hit, + _ways_10_io_update_hit, + _ways_9_io_update_hit, + _ways_8_io_update_hit, + _ways_7_io_update_hit, + _ways_6_io_update_hit, + _ways_5_io_update_hit, + _ways_4_io_update_hit, + _ways_3_io_update_hit, + _ways_2_io_update_hit, + _ways_1_io_update_hit, + _ways_0_io_update_hit}; + wire [14:0] _s1_hit_way_T_1 = + {_ways_31_io_resp_hit, + _ways_30_io_resp_hit, + _ways_29_io_resp_hit, + _ways_28_io_resp_hit, + _ways_27_io_resp_hit, + _ways_26_io_resp_hit, + _ways_25_io_resp_hit, + _ways_24_io_resp_hit, + _ways_23_io_resp_hit, + _ways_22_io_resp_hit, + _ways_21_io_resp_hit, + _ways_20_io_resp_hit, + _ways_19_io_resp_hit, + _ways_18_io_resp_hit, + _ways_17_io_resp_hit} + | {_ways_15_io_resp_hit, + _ways_14_io_resp_hit, + _ways_13_io_resp_hit, + _ways_12_io_resp_hit, + _ways_11_io_resp_hit, + _ways_10_io_resp_hit, + _ways_9_io_resp_hit, + _ways_8_io_resp_hit, + _ways_7_io_resp_hit, + _ways_6_io_resp_hit, + _ways_5_io_resp_hit, + _ways_4_io_resp_hit, + _ways_3_io_resp_hit, + _ways_2_io_resp_hit, + _ways_1_io_resp_hit}; + wire [6:0] _s1_hit_way_T_3 = _s1_hit_way_T_1[14:8] | _s1_hit_way_T_1[6:0]; + wire [2:0] _s1_hit_way_T_5 = _s1_hit_way_T_3[6:4] | _s1_hit_way_T_3[2:0]; + wire [4:0] s1_hit_way = + {|{_ways_31_io_resp_hit, + _ways_30_io_resp_hit, + _ways_29_io_resp_hit, + _ways_28_io_resp_hit, + _ways_27_io_resp_hit, + _ways_26_io_resp_hit, + _ways_25_io_resp_hit, + _ways_24_io_resp_hit, + _ways_23_io_resp_hit, + _ways_22_io_resp_hit, + _ways_21_io_resp_hit, + _ways_20_io_resp_hit, + _ways_19_io_resp_hit, + _ways_18_io_resp_hit, + _ways_17_io_resp_hit, + _ways_16_io_resp_hit}, + |(_s1_hit_way_T_1[14:7]), + |(_s1_hit_way_T_3[6:3]), + |(_s1_hit_way_T_5[2:1]), + _s1_hit_way_T_5[2] | _s1_hit_way_T_5[0]}; + always @(posedge clock) begin + if (REG_1) begin + s1_pc_dup_0 <= _GEN_3; + s1_pc_dup_1 <= _GEN_3; + s1_pc_dup_2 <= _GEN_3; + s1_pc_dup_3 <= _GEN_3; + end + else begin + if (io_s0_fire_0) + s1_pc_dup_0 <= io_in_bits_s0_pc_0; + if (io_s0_fire_1) + s1_pc_dup_1 <= io_in_bits_s0_pc_1; + if (io_s0_fire_2) + s1_pc_dup_2 <= io_in_bits_s0_pc_2; + if (io_s0_fire_3) + s1_pc_dup_3 <= io_in_bits_s0_pc_3; + end + REG <= reset; + REG_1 <= REG & ~reset; + fauftb_enable <= io_ctrl_ubtb_enable; + if (io_s1_fire_0) begin + resp_meta_hit_r <= |s1_hit_oh; + resp_meta_pred_way_r <= s1_hit_way; + end + if (io_s2_fire_0) begin + resp_meta_hit_r_1 <= resp_meta_hit_r; + resp_meta_pred_way_r_1 <= resp_meta_pred_way_r; + end + replacer_touch_ways_0_valid_REG <= io_s1_fire_0 & (|s1_hit_oh); + if (io_s1_fire_0 & (|s1_hit_oh)) + replacer_touch_ways_0_bits_r <= s1_hit_way; + u_s1_valid <= io_update_valid; + if (io_update_valid) begin + u_s1_tag <= io_update_bits_pc[16:1]; + u_s1_hit_oh <= u_s0_hit_oh; + u_s1_hit <= |u_s0_hit_oh; + u_s1_ftb_entry_brSlots_0_offset <= io_update_bits_ftb_entry_brSlots_0_offset; + u_s1_ftb_entry_brSlots_0_lower <= io_update_bits_ftb_entry_brSlots_0_lower; + u_s1_ftb_entry_brSlots_0_tarStat <= io_update_bits_ftb_entry_brSlots_0_tarStat; + u_s1_ftb_entry_brSlots_0_valid <= io_update_bits_ftb_entry_brSlots_0_valid; + u_s1_ftb_entry_tailSlot_offset <= io_update_bits_ftb_entry_tailSlot_offset; + u_s1_ftb_entry_tailSlot_lower <= io_update_bits_ftb_entry_tailSlot_lower; + u_s1_ftb_entry_tailSlot_tarStat <= io_update_bits_ftb_entry_tailSlot_tarStat; + u_s1_ftb_entry_tailSlot_sharing <= io_update_bits_ftb_entry_tailSlot_sharing; + u_s1_ftb_entry_tailSlot_valid <= io_update_bits_ftb_entry_tailSlot_valid; + u_s1_ftb_entry_pftAddr <= io_update_bits_ftb_entry_pftAddr; + u_s1_ftb_entry_carry <= io_update_bits_ftb_entry_carry; + u_s1_ftb_entry_always_taken_0 <= io_update_bits_ftb_entry_always_taken_0; + u_s1_ftb_entry_always_taken_1 <= io_update_bits_ftb_entry_always_taken_1; + u_s1_br_update_valids_0 <= + io_update_bits_ftb_entry_brSlots_0_valid & io_update_valid + & ~io_update_bits_ftb_entry_always_taken_0; + u_s1_br_update_valids_1 <= + io_update_bits_ftb_entry_tailSlot_valid + & io_update_bits_ftb_entry_tailSlot_sharing & io_update_valid + & ~io_update_bits_ftb_entry_always_taken_1 & ~io_update_bits_br_taken_mask_0; + u_s1_br_takens_0 <= io_update_bits_br_taken_mask_0; + u_s1_br_takens_1 <= io_update_bits_br_taken_mask_1; + end + io_perf_0_value_REG <= io_update_valid & io_update_bits_meta[0]; + io_perf_0_value_REG_1 <= io_perf_0_value_REG; + io_perf_1_value_REG <= io_update_valid & ~(io_update_bits_meta[0]); + io_perf_1_value_REG_1 <= io_perf_1_value_REG; + end // always @(posedge) + wire [14:0] _replacer_touch_ways_1_bits_T_1 = + u_s1_write_way_oh[31:17] | u_s1_write_way_oh[15:1]; + wire [6:0] _replacer_touch_ways_1_bits_T_3 = + _replacer_touch_ways_1_bits_T_1[14:8] | _replacer_touch_ways_1_bits_T_1[6:0]; + wire [2:0] _replacer_touch_ways_1_bits_T_5 = + _replacer_touch_ways_1_bits_T_3[6:4] | _replacer_touch_ways_1_bits_T_3[2:0]; + wire _replacer_touch_ways_1_bits_T_7 = + _replacer_touch_ways_1_bits_T_5[2] | _replacer_touch_ways_1_bits_T_5[0]; + wire [14:0] _state_reg_T_52 = + replacer_touch_ways_0_bits_r[4] + ? {~(replacer_touch_ways_0_bits_r[3]), + replacer_touch_ways_0_bits_r[3] + ? {~(replacer_touch_ways_0_bits_r[2]), + replacer_touch_ways_0_bits_r[2] + ? {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[26], + replacer_touch_ways_0_bits_r[1] + ? state_reg[25] + : ~(replacer_touch_ways_0_bits_r[0])} + : state_reg[27:25], + replacer_touch_ways_0_bits_r[2] + ? state_reg[24:22] + : {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[23], + replacer_touch_ways_0_bits_r[1] + ? state_reg[22] + : ~(replacer_touch_ways_0_bits_r[0])}} + : state_reg[28:22], + replacer_touch_ways_0_bits_r[3] + ? state_reg[21:15] + : {~(replacer_touch_ways_0_bits_r[2]), + replacer_touch_ways_0_bits_r[2] + ? {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[19], + replacer_touch_ways_0_bits_r[1] + ? state_reg[18] + : ~(replacer_touch_ways_0_bits_r[0])} + : state_reg[20:18], + replacer_touch_ways_0_bits_r[2] + ? state_reg[17:15] + : {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[16], + replacer_touch_ways_0_bits_r[1] + ? state_reg[15] + : ~(replacer_touch_ways_0_bits_r[0])}}} + : state_reg[29:15]; + wire [14:0] _state_reg_T_105 = + replacer_touch_ways_0_bits_r[4] + ? state_reg[14:0] + : {~(replacer_touch_ways_0_bits_r[3]), + replacer_touch_ways_0_bits_r[3] + ? {~(replacer_touch_ways_0_bits_r[2]), + replacer_touch_ways_0_bits_r[2] + ? {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[11], + replacer_touch_ways_0_bits_r[1] + ? state_reg[10] + : ~(replacer_touch_ways_0_bits_r[0])} + : state_reg[12:10], + replacer_touch_ways_0_bits_r[2] + ? state_reg[9:7] + : {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[8], + replacer_touch_ways_0_bits_r[1] + ? state_reg[7] + : ~(replacer_touch_ways_0_bits_r[0])}} + : state_reg[13:7], + replacer_touch_ways_0_bits_r[3] + ? state_reg[6:0] + : {~(replacer_touch_ways_0_bits_r[2]), + replacer_touch_ways_0_bits_r[2] + ? {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[4], + replacer_touch_ways_0_bits_r[1] + ? state_reg[3] + : ~(replacer_touch_ways_0_bits_r[0])} + : state_reg[5:3], + replacer_touch_ways_0_bits_r[2] + ? state_reg[2:0] + : {~(replacer_touch_ways_0_bits_r[1]), + replacer_touch_ways_0_bits_r[1] + ? ~(replacer_touch_ways_0_bits_r[0]) + : state_reg[1], + replacer_touch_ways_0_bits_r[1] + ? state_reg[0] + : ~(replacer_touch_ways_0_bits_r[0])}}}; + wire [29:0] _state_reg_T_107 = + replacer_touch_ways_0_valid_REG + ? {_state_reg_T_52, _state_reg_T_105} + : state_reg[29:0]; + always @(posedge clock or posedge reset) begin + if (reset) begin + ctrs_0_0 <= 2'h2; + ctrs_0_1 <= 2'h2; + ctrs_1_0 <= 2'h2; + ctrs_1_1 <= 2'h2; + ctrs_2_0 <= 2'h2; + ctrs_2_1 <= 2'h2; + ctrs_3_0 <= 2'h2; + ctrs_3_1 <= 2'h2; + ctrs_4_0 <= 2'h2; + ctrs_4_1 <= 2'h2; + ctrs_5_0 <= 2'h2; + ctrs_5_1 <= 2'h2; + ctrs_6_0 <= 2'h2; + ctrs_6_1 <= 2'h2; + ctrs_7_0 <= 2'h2; + ctrs_7_1 <= 2'h2; + ctrs_8_0 <= 2'h2; + ctrs_8_1 <= 2'h2; + ctrs_9_0 <= 2'h2; + ctrs_9_1 <= 2'h2; + ctrs_10_0 <= 2'h2; + ctrs_10_1 <= 2'h2; + ctrs_11_0 <= 2'h2; + ctrs_11_1 <= 2'h2; + ctrs_12_0 <= 2'h2; + ctrs_12_1 <= 2'h2; + ctrs_13_0 <= 2'h2; + ctrs_13_1 <= 2'h2; + ctrs_14_0 <= 2'h2; + ctrs_14_1 <= 2'h2; + ctrs_15_0 <= 2'h2; + ctrs_15_1 <= 2'h2; + ctrs_16_0 <= 2'h2; + ctrs_16_1 <= 2'h2; + ctrs_17_0 <= 2'h2; + ctrs_17_1 <= 2'h2; + ctrs_18_0 <= 2'h2; + ctrs_18_1 <= 2'h2; + ctrs_19_0 <= 2'h2; + ctrs_19_1 <= 2'h2; + ctrs_20_0 <= 2'h2; + ctrs_20_1 <= 2'h2; + ctrs_21_0 <= 2'h2; + ctrs_21_1 <= 2'h2; + ctrs_22_0 <= 2'h2; + ctrs_22_1 <= 2'h2; + ctrs_23_0 <= 2'h2; + ctrs_23_1 <= 2'h2; + ctrs_24_0 <= 2'h2; + ctrs_24_1 <= 2'h2; + ctrs_25_0 <= 2'h2; + ctrs_25_1 <= 2'h2; + ctrs_26_0 <= 2'h2; + ctrs_26_1 <= 2'h2; + ctrs_27_0 <= 2'h2; + ctrs_27_1 <= 2'h2; + ctrs_28_0 <= 2'h2; + ctrs_28_1 <= 2'h2; + ctrs_29_0 <= 2'h2; + ctrs_29_1 <= 2'h2; + ctrs_30_0 <= 2'h2; + ctrs_30_1 <= 2'h2; + ctrs_31_0 <= 2'h2; + ctrs_31_1 <= 2'h2; + state_reg <= 31'h0; + end + else begin + if (u_s1_ways_write_valid_0 & u_s1_br_update_valids_0) begin + if ((&ctrs_0_0) & u_s1_br_takens_0) + ctrs_0_0 <= 2'h3; + else if (ctrs_0_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_0_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_0_0 <= 2'(ctrs_0_0 + 2'h1); + else + ctrs_0_0 <= 2'(ctrs_0_0 - 2'h1); + end + if (u_s1_ways_write_valid_0 & u_s1_br_update_valids_1) begin + if ((&ctrs_0_1) & u_s1_br_takens_1) + ctrs_0_1 <= 2'h3; + else if (ctrs_0_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_0_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_0_1 <= 2'(ctrs_0_1 + 2'h1); + else + ctrs_0_1 <= 2'(ctrs_0_1 - 2'h1); + end + if (u_s1_ways_write_valid_1 & u_s1_br_update_valids_0) begin + if ((&ctrs_1_0) & u_s1_br_takens_0) + ctrs_1_0 <= 2'h3; + else if (ctrs_1_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_1_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_1_0 <= 2'(ctrs_1_0 + 2'h1); + else + ctrs_1_0 <= 2'(ctrs_1_0 - 2'h1); + end + if (u_s1_ways_write_valid_1 & u_s1_br_update_valids_1) begin + if ((&ctrs_1_1) & u_s1_br_takens_1) + ctrs_1_1 <= 2'h3; + else if (ctrs_1_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_1_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_1_1 <= 2'(ctrs_1_1 + 2'h1); + else + ctrs_1_1 <= 2'(ctrs_1_1 - 2'h1); + end + if (u_s1_ways_write_valid_2 & u_s1_br_update_valids_0) begin + if ((&ctrs_2_0) & u_s1_br_takens_0) + ctrs_2_0 <= 2'h3; + else if (ctrs_2_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_2_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_2_0 <= 2'(ctrs_2_0 + 2'h1); + else + ctrs_2_0 <= 2'(ctrs_2_0 - 2'h1); + end + if (u_s1_ways_write_valid_2 & u_s1_br_update_valids_1) begin + if ((&ctrs_2_1) & u_s1_br_takens_1) + ctrs_2_1 <= 2'h3; + else if (ctrs_2_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_2_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_2_1 <= 2'(ctrs_2_1 + 2'h1); + else + ctrs_2_1 <= 2'(ctrs_2_1 - 2'h1); + end + if (u_s1_ways_write_valid_3 & u_s1_br_update_valids_0) begin + if ((&ctrs_3_0) & u_s1_br_takens_0) + ctrs_3_0 <= 2'h3; + else if (ctrs_3_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_3_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_3_0 <= 2'(ctrs_3_0 + 2'h1); + else + ctrs_3_0 <= 2'(ctrs_3_0 - 2'h1); + end + if (u_s1_ways_write_valid_3 & u_s1_br_update_valids_1) begin + if ((&ctrs_3_1) & u_s1_br_takens_1) + ctrs_3_1 <= 2'h3; + else if (ctrs_3_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_3_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_3_1 <= 2'(ctrs_3_1 + 2'h1); + else + ctrs_3_1 <= 2'(ctrs_3_1 - 2'h1); + end + if (u_s1_ways_write_valid_4 & u_s1_br_update_valids_0) begin + if ((&ctrs_4_0) & u_s1_br_takens_0) + ctrs_4_0 <= 2'h3; + else if (ctrs_4_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_4_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_4_0 <= 2'(ctrs_4_0 + 2'h1); + else + ctrs_4_0 <= 2'(ctrs_4_0 - 2'h1); + end + if (u_s1_ways_write_valid_4 & u_s1_br_update_valids_1) begin + if ((&ctrs_4_1) & u_s1_br_takens_1) + ctrs_4_1 <= 2'h3; + else if (ctrs_4_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_4_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_4_1 <= 2'(ctrs_4_1 + 2'h1); + else + ctrs_4_1 <= 2'(ctrs_4_1 - 2'h1); + end + if (u_s1_ways_write_valid_5 & u_s1_br_update_valids_0) begin + if ((&ctrs_5_0) & u_s1_br_takens_0) + ctrs_5_0 <= 2'h3; + else if (ctrs_5_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_5_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_5_0 <= 2'(ctrs_5_0 + 2'h1); + else + ctrs_5_0 <= 2'(ctrs_5_0 - 2'h1); + end + if (u_s1_ways_write_valid_5 & u_s1_br_update_valids_1) begin + if ((&ctrs_5_1) & u_s1_br_takens_1) + ctrs_5_1 <= 2'h3; + else if (ctrs_5_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_5_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_5_1 <= 2'(ctrs_5_1 + 2'h1); + else + ctrs_5_1 <= 2'(ctrs_5_1 - 2'h1); + end + if (u_s1_ways_write_valid_6 & u_s1_br_update_valids_0) begin + if ((&ctrs_6_0) & u_s1_br_takens_0) + ctrs_6_0 <= 2'h3; + else if (ctrs_6_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_6_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_6_0 <= 2'(ctrs_6_0 + 2'h1); + else + ctrs_6_0 <= 2'(ctrs_6_0 - 2'h1); + end + if (u_s1_ways_write_valid_6 & u_s1_br_update_valids_1) begin + if ((&ctrs_6_1) & u_s1_br_takens_1) + ctrs_6_1 <= 2'h3; + else if (ctrs_6_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_6_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_6_1 <= 2'(ctrs_6_1 + 2'h1); + else + ctrs_6_1 <= 2'(ctrs_6_1 - 2'h1); + end + if (u_s1_ways_write_valid_7 & u_s1_br_update_valids_0) begin + if ((&ctrs_7_0) & u_s1_br_takens_0) + ctrs_7_0 <= 2'h3; + else if (ctrs_7_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_7_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_7_0 <= 2'(ctrs_7_0 + 2'h1); + else + ctrs_7_0 <= 2'(ctrs_7_0 - 2'h1); + end + if (u_s1_ways_write_valid_7 & u_s1_br_update_valids_1) begin + if ((&ctrs_7_1) & u_s1_br_takens_1) + ctrs_7_1 <= 2'h3; + else if (ctrs_7_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_7_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_7_1 <= 2'(ctrs_7_1 + 2'h1); + else + ctrs_7_1 <= 2'(ctrs_7_1 - 2'h1); + end + if (u_s1_ways_write_valid_8 & u_s1_br_update_valids_0) begin + if ((&ctrs_8_0) & u_s1_br_takens_0) + ctrs_8_0 <= 2'h3; + else if (ctrs_8_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_8_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_8_0 <= 2'(ctrs_8_0 + 2'h1); + else + ctrs_8_0 <= 2'(ctrs_8_0 - 2'h1); + end + if (u_s1_ways_write_valid_8 & u_s1_br_update_valids_1) begin + if ((&ctrs_8_1) & u_s1_br_takens_1) + ctrs_8_1 <= 2'h3; + else if (ctrs_8_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_8_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_8_1 <= 2'(ctrs_8_1 + 2'h1); + else + ctrs_8_1 <= 2'(ctrs_8_1 - 2'h1); + end + if (u_s1_ways_write_valid_9 & u_s1_br_update_valids_0) begin + if ((&ctrs_9_0) & u_s1_br_takens_0) + ctrs_9_0 <= 2'h3; + else if (ctrs_9_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_9_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_9_0 <= 2'(ctrs_9_0 + 2'h1); + else + ctrs_9_0 <= 2'(ctrs_9_0 - 2'h1); + end + if (u_s1_ways_write_valid_9 & u_s1_br_update_valids_1) begin + if ((&ctrs_9_1) & u_s1_br_takens_1) + ctrs_9_1 <= 2'h3; + else if (ctrs_9_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_9_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_9_1 <= 2'(ctrs_9_1 + 2'h1); + else + ctrs_9_1 <= 2'(ctrs_9_1 - 2'h1); + end + if (u_s1_ways_write_valid_10 & u_s1_br_update_valids_0) begin + if ((&ctrs_10_0) & u_s1_br_takens_0) + ctrs_10_0 <= 2'h3; + else if (ctrs_10_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_10_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_10_0 <= 2'(ctrs_10_0 + 2'h1); + else + ctrs_10_0 <= 2'(ctrs_10_0 - 2'h1); + end + if (u_s1_ways_write_valid_10 & u_s1_br_update_valids_1) begin + if ((&ctrs_10_1) & u_s1_br_takens_1) + ctrs_10_1 <= 2'h3; + else if (ctrs_10_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_10_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_10_1 <= 2'(ctrs_10_1 + 2'h1); + else + ctrs_10_1 <= 2'(ctrs_10_1 - 2'h1); + end + if (u_s1_ways_write_valid_11 & u_s1_br_update_valids_0) begin + if ((&ctrs_11_0) & u_s1_br_takens_0) + ctrs_11_0 <= 2'h3; + else if (ctrs_11_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_11_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_11_0 <= 2'(ctrs_11_0 + 2'h1); + else + ctrs_11_0 <= 2'(ctrs_11_0 - 2'h1); + end + if (u_s1_ways_write_valid_11 & u_s1_br_update_valids_1) begin + if ((&ctrs_11_1) & u_s1_br_takens_1) + ctrs_11_1 <= 2'h3; + else if (ctrs_11_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_11_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_11_1 <= 2'(ctrs_11_1 + 2'h1); + else + ctrs_11_1 <= 2'(ctrs_11_1 - 2'h1); + end + if (u_s1_ways_write_valid_12 & u_s1_br_update_valids_0) begin + if ((&ctrs_12_0) & u_s1_br_takens_0) + ctrs_12_0 <= 2'h3; + else if (ctrs_12_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_12_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_12_0 <= 2'(ctrs_12_0 + 2'h1); + else + ctrs_12_0 <= 2'(ctrs_12_0 - 2'h1); + end + if (u_s1_ways_write_valid_12 & u_s1_br_update_valids_1) begin + if ((&ctrs_12_1) & u_s1_br_takens_1) + ctrs_12_1 <= 2'h3; + else if (ctrs_12_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_12_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_12_1 <= 2'(ctrs_12_1 + 2'h1); + else + ctrs_12_1 <= 2'(ctrs_12_1 - 2'h1); + end + if (u_s1_ways_write_valid_13 & u_s1_br_update_valids_0) begin + if ((&ctrs_13_0) & u_s1_br_takens_0) + ctrs_13_0 <= 2'h3; + else if (ctrs_13_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_13_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_13_0 <= 2'(ctrs_13_0 + 2'h1); + else + ctrs_13_0 <= 2'(ctrs_13_0 - 2'h1); + end + if (u_s1_ways_write_valid_13 & u_s1_br_update_valids_1) begin + if ((&ctrs_13_1) & u_s1_br_takens_1) + ctrs_13_1 <= 2'h3; + else if (ctrs_13_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_13_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_13_1 <= 2'(ctrs_13_1 + 2'h1); + else + ctrs_13_1 <= 2'(ctrs_13_1 - 2'h1); + end + if (u_s1_ways_write_valid_14 & u_s1_br_update_valids_0) begin + if ((&ctrs_14_0) & u_s1_br_takens_0) + ctrs_14_0 <= 2'h3; + else if (ctrs_14_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_14_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_14_0 <= 2'(ctrs_14_0 + 2'h1); + else + ctrs_14_0 <= 2'(ctrs_14_0 - 2'h1); + end + if (u_s1_ways_write_valid_14 & u_s1_br_update_valids_1) begin + if ((&ctrs_14_1) & u_s1_br_takens_1) + ctrs_14_1 <= 2'h3; + else if (ctrs_14_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_14_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_14_1 <= 2'(ctrs_14_1 + 2'h1); + else + ctrs_14_1 <= 2'(ctrs_14_1 - 2'h1); + end + if (u_s1_ways_write_valid_15 & u_s1_br_update_valids_0) begin + if ((&ctrs_15_0) & u_s1_br_takens_0) + ctrs_15_0 <= 2'h3; + else if (ctrs_15_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_15_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_15_0 <= 2'(ctrs_15_0 + 2'h1); + else + ctrs_15_0 <= 2'(ctrs_15_0 - 2'h1); + end + if (u_s1_ways_write_valid_15 & u_s1_br_update_valids_1) begin + if ((&ctrs_15_1) & u_s1_br_takens_1) + ctrs_15_1 <= 2'h3; + else if (ctrs_15_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_15_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_15_1 <= 2'(ctrs_15_1 + 2'h1); + else + ctrs_15_1 <= 2'(ctrs_15_1 - 2'h1); + end + if (u_s1_ways_write_valid_16 & u_s1_br_update_valids_0) begin + if ((&ctrs_16_0) & u_s1_br_takens_0) + ctrs_16_0 <= 2'h3; + else if (ctrs_16_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_16_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_16_0 <= 2'(ctrs_16_0 + 2'h1); + else + ctrs_16_0 <= 2'(ctrs_16_0 - 2'h1); + end + if (u_s1_ways_write_valid_16 & u_s1_br_update_valids_1) begin + if ((&ctrs_16_1) & u_s1_br_takens_1) + ctrs_16_1 <= 2'h3; + else if (ctrs_16_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_16_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_16_1 <= 2'(ctrs_16_1 + 2'h1); + else + ctrs_16_1 <= 2'(ctrs_16_1 - 2'h1); + end + if (u_s1_ways_write_valid_17 & u_s1_br_update_valids_0) begin + if ((&ctrs_17_0) & u_s1_br_takens_0) + ctrs_17_0 <= 2'h3; + else if (ctrs_17_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_17_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_17_0 <= 2'(ctrs_17_0 + 2'h1); + else + ctrs_17_0 <= 2'(ctrs_17_0 - 2'h1); + end + if (u_s1_ways_write_valid_17 & u_s1_br_update_valids_1) begin + if ((&ctrs_17_1) & u_s1_br_takens_1) + ctrs_17_1 <= 2'h3; + else if (ctrs_17_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_17_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_17_1 <= 2'(ctrs_17_1 + 2'h1); + else + ctrs_17_1 <= 2'(ctrs_17_1 - 2'h1); + end + if (u_s1_ways_write_valid_18 & u_s1_br_update_valids_0) begin + if ((&ctrs_18_0) & u_s1_br_takens_0) + ctrs_18_0 <= 2'h3; + else if (ctrs_18_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_18_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_18_0 <= 2'(ctrs_18_0 + 2'h1); + else + ctrs_18_0 <= 2'(ctrs_18_0 - 2'h1); + end + if (u_s1_ways_write_valid_18 & u_s1_br_update_valids_1) begin + if ((&ctrs_18_1) & u_s1_br_takens_1) + ctrs_18_1 <= 2'h3; + else if (ctrs_18_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_18_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_18_1 <= 2'(ctrs_18_1 + 2'h1); + else + ctrs_18_1 <= 2'(ctrs_18_1 - 2'h1); + end + if (u_s1_ways_write_valid_19 & u_s1_br_update_valids_0) begin + if ((&ctrs_19_0) & u_s1_br_takens_0) + ctrs_19_0 <= 2'h3; + else if (ctrs_19_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_19_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_19_0 <= 2'(ctrs_19_0 + 2'h1); + else + ctrs_19_0 <= 2'(ctrs_19_0 - 2'h1); + end + if (u_s1_ways_write_valid_19 & u_s1_br_update_valids_1) begin + if ((&ctrs_19_1) & u_s1_br_takens_1) + ctrs_19_1 <= 2'h3; + else if (ctrs_19_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_19_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_19_1 <= 2'(ctrs_19_1 + 2'h1); + else + ctrs_19_1 <= 2'(ctrs_19_1 - 2'h1); + end + if (u_s1_ways_write_valid_20 & u_s1_br_update_valids_0) begin + if ((&ctrs_20_0) & u_s1_br_takens_0) + ctrs_20_0 <= 2'h3; + else if (ctrs_20_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_20_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_20_0 <= 2'(ctrs_20_0 + 2'h1); + else + ctrs_20_0 <= 2'(ctrs_20_0 - 2'h1); + end + if (u_s1_ways_write_valid_20 & u_s1_br_update_valids_1) begin + if ((&ctrs_20_1) & u_s1_br_takens_1) + ctrs_20_1 <= 2'h3; + else if (ctrs_20_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_20_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_20_1 <= 2'(ctrs_20_1 + 2'h1); + else + ctrs_20_1 <= 2'(ctrs_20_1 - 2'h1); + end + if (u_s1_ways_write_valid_21 & u_s1_br_update_valids_0) begin + if ((&ctrs_21_0) & u_s1_br_takens_0) + ctrs_21_0 <= 2'h3; + else if (ctrs_21_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_21_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_21_0 <= 2'(ctrs_21_0 + 2'h1); + else + ctrs_21_0 <= 2'(ctrs_21_0 - 2'h1); + end + if (u_s1_ways_write_valid_21 & u_s1_br_update_valids_1) begin + if ((&ctrs_21_1) & u_s1_br_takens_1) + ctrs_21_1 <= 2'h3; + else if (ctrs_21_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_21_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_21_1 <= 2'(ctrs_21_1 + 2'h1); + else + ctrs_21_1 <= 2'(ctrs_21_1 - 2'h1); + end + if (u_s1_ways_write_valid_22 & u_s1_br_update_valids_0) begin + if ((&ctrs_22_0) & u_s1_br_takens_0) + ctrs_22_0 <= 2'h3; + else if (ctrs_22_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_22_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_22_0 <= 2'(ctrs_22_0 + 2'h1); + else + ctrs_22_0 <= 2'(ctrs_22_0 - 2'h1); + end + if (u_s1_ways_write_valid_22 & u_s1_br_update_valids_1) begin + if ((&ctrs_22_1) & u_s1_br_takens_1) + ctrs_22_1 <= 2'h3; + else if (ctrs_22_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_22_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_22_1 <= 2'(ctrs_22_1 + 2'h1); + else + ctrs_22_1 <= 2'(ctrs_22_1 - 2'h1); + end + if (u_s1_ways_write_valid_23 & u_s1_br_update_valids_0) begin + if ((&ctrs_23_0) & u_s1_br_takens_0) + ctrs_23_0 <= 2'h3; + else if (ctrs_23_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_23_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_23_0 <= 2'(ctrs_23_0 + 2'h1); + else + ctrs_23_0 <= 2'(ctrs_23_0 - 2'h1); + end + if (u_s1_ways_write_valid_23 & u_s1_br_update_valids_1) begin + if ((&ctrs_23_1) & u_s1_br_takens_1) + ctrs_23_1 <= 2'h3; + else if (ctrs_23_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_23_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_23_1 <= 2'(ctrs_23_1 + 2'h1); + else + ctrs_23_1 <= 2'(ctrs_23_1 - 2'h1); + end + if (u_s1_ways_write_valid_24 & u_s1_br_update_valids_0) begin + if ((&ctrs_24_0) & u_s1_br_takens_0) + ctrs_24_0 <= 2'h3; + else if (ctrs_24_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_24_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_24_0 <= 2'(ctrs_24_0 + 2'h1); + else + ctrs_24_0 <= 2'(ctrs_24_0 - 2'h1); + end + if (u_s1_ways_write_valid_24 & u_s1_br_update_valids_1) begin + if ((&ctrs_24_1) & u_s1_br_takens_1) + ctrs_24_1 <= 2'h3; + else if (ctrs_24_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_24_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_24_1 <= 2'(ctrs_24_1 + 2'h1); + else + ctrs_24_1 <= 2'(ctrs_24_1 - 2'h1); + end + if (u_s1_ways_write_valid_25 & u_s1_br_update_valids_0) begin + if ((&ctrs_25_0) & u_s1_br_takens_0) + ctrs_25_0 <= 2'h3; + else if (ctrs_25_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_25_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_25_0 <= 2'(ctrs_25_0 + 2'h1); + else + ctrs_25_0 <= 2'(ctrs_25_0 - 2'h1); + end + if (u_s1_ways_write_valid_25 & u_s1_br_update_valids_1) begin + if ((&ctrs_25_1) & u_s1_br_takens_1) + ctrs_25_1 <= 2'h3; + else if (ctrs_25_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_25_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_25_1 <= 2'(ctrs_25_1 + 2'h1); + else + ctrs_25_1 <= 2'(ctrs_25_1 - 2'h1); + end + if (u_s1_ways_write_valid_26 & u_s1_br_update_valids_0) begin + if ((&ctrs_26_0) & u_s1_br_takens_0) + ctrs_26_0 <= 2'h3; + else if (ctrs_26_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_26_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_26_0 <= 2'(ctrs_26_0 + 2'h1); + else + ctrs_26_0 <= 2'(ctrs_26_0 - 2'h1); + end + if (u_s1_ways_write_valid_26 & u_s1_br_update_valids_1) begin + if ((&ctrs_26_1) & u_s1_br_takens_1) + ctrs_26_1 <= 2'h3; + else if (ctrs_26_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_26_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_26_1 <= 2'(ctrs_26_1 + 2'h1); + else + ctrs_26_1 <= 2'(ctrs_26_1 - 2'h1); + end + if (u_s1_ways_write_valid_27 & u_s1_br_update_valids_0) begin + if ((&ctrs_27_0) & u_s1_br_takens_0) + ctrs_27_0 <= 2'h3; + else if (ctrs_27_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_27_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_27_0 <= 2'(ctrs_27_0 + 2'h1); + else + ctrs_27_0 <= 2'(ctrs_27_0 - 2'h1); + end + if (u_s1_ways_write_valid_27 & u_s1_br_update_valids_1) begin + if ((&ctrs_27_1) & u_s1_br_takens_1) + ctrs_27_1 <= 2'h3; + else if (ctrs_27_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_27_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_27_1 <= 2'(ctrs_27_1 + 2'h1); + else + ctrs_27_1 <= 2'(ctrs_27_1 - 2'h1); + end + if (u_s1_ways_write_valid_28 & u_s1_br_update_valids_0) begin + if ((&ctrs_28_0) & u_s1_br_takens_0) + ctrs_28_0 <= 2'h3; + else if (ctrs_28_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_28_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_28_0 <= 2'(ctrs_28_0 + 2'h1); + else + ctrs_28_0 <= 2'(ctrs_28_0 - 2'h1); + end + if (u_s1_ways_write_valid_28 & u_s1_br_update_valids_1) begin + if ((&ctrs_28_1) & u_s1_br_takens_1) + ctrs_28_1 <= 2'h3; + else if (ctrs_28_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_28_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_28_1 <= 2'(ctrs_28_1 + 2'h1); + else + ctrs_28_1 <= 2'(ctrs_28_1 - 2'h1); + end + if (u_s1_ways_write_valid_29 & u_s1_br_update_valids_0) begin + if ((&ctrs_29_0) & u_s1_br_takens_0) + ctrs_29_0 <= 2'h3; + else if (ctrs_29_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_29_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_29_0 <= 2'(ctrs_29_0 + 2'h1); + else + ctrs_29_0 <= 2'(ctrs_29_0 - 2'h1); + end + if (u_s1_ways_write_valid_29 & u_s1_br_update_valids_1) begin + if ((&ctrs_29_1) & u_s1_br_takens_1) + ctrs_29_1 <= 2'h3; + else if (ctrs_29_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_29_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_29_1 <= 2'(ctrs_29_1 + 2'h1); + else + ctrs_29_1 <= 2'(ctrs_29_1 - 2'h1); + end + if (u_s1_ways_write_valid_30 & u_s1_br_update_valids_0) begin + if ((&ctrs_30_0) & u_s1_br_takens_0) + ctrs_30_0 <= 2'h3; + else if (ctrs_30_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_30_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_30_0 <= 2'(ctrs_30_0 + 2'h1); + else + ctrs_30_0 <= 2'(ctrs_30_0 - 2'h1); + end + if (u_s1_ways_write_valid_30 & u_s1_br_update_valids_1) begin + if ((&ctrs_30_1) & u_s1_br_takens_1) + ctrs_30_1 <= 2'h3; + else if (ctrs_30_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_30_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_30_1 <= 2'(ctrs_30_1 + 2'h1); + else + ctrs_30_1 <= 2'(ctrs_30_1 - 2'h1); + end + if (u_s1_ways_write_valid_31 & u_s1_br_update_valids_0) begin + if ((&ctrs_31_0) & u_s1_br_takens_0) + ctrs_31_0 <= 2'h3; + else if (ctrs_31_0 == 2'h0 & ~u_s1_br_takens_0) + ctrs_31_0 <= 2'h0; + else if (u_s1_br_takens_0) + ctrs_31_0 <= 2'(ctrs_31_0 + 2'h1); + else + ctrs_31_0 <= 2'(ctrs_31_0 - 2'h1); + end + if (u_s1_ways_write_valid_31 & u_s1_br_update_valids_1) begin + if ((&ctrs_31_1) & u_s1_br_takens_1) + ctrs_31_1 <= 2'h3; + else if (ctrs_31_1 == 2'h0 & ~u_s1_br_takens_1) + ctrs_31_1 <= 2'h0; + else if (u_s1_br_takens_1) + ctrs_31_1 <= 2'(ctrs_31_1 + 2'h1); + else + ctrs_31_1 <= 2'(ctrs_31_1 - 2'h1); + end + if (replacer_touch_ways_0_valid_REG | u_s1_valid) begin + if (u_s1_valid) + state_reg <= + {~(|(u_s1_write_way_oh[31:16])), + (|(u_s1_write_way_oh[31:16])) + ? {~(|(_replacer_touch_ways_1_bits_T_1[14:7])), + (|(_replacer_touch_ways_1_bits_T_1[14:7])) + ? {~(|(_replacer_touch_ways_1_bits_T_3[6:3])), + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[26], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[25] + : ~_replacer_touch_ways_1_bits_T_7} + : _state_reg_T_107[27:25], + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? _state_reg_T_107[24:22] + : {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[23], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[22] + : ~_replacer_touch_ways_1_bits_T_7}} + : _state_reg_T_107[28:22], + (|(_replacer_touch_ways_1_bits_T_1[14:7])) + ? _state_reg_T_107[21:15] + : {~(|(_replacer_touch_ways_1_bits_T_3[6:3])), + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[19], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[18] + : ~_replacer_touch_ways_1_bits_T_7} + : _state_reg_T_107[20:18], + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? _state_reg_T_107[17:15] + : {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[16], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[15] + : ~_replacer_touch_ways_1_bits_T_7}}} + : _state_reg_T_107[29:15], + (|(u_s1_write_way_oh[31:16])) + ? _state_reg_T_107[14:0] + : {~(|(_replacer_touch_ways_1_bits_T_1[14:7])), + (|(_replacer_touch_ways_1_bits_T_1[14:7])) + ? {~(|(_replacer_touch_ways_1_bits_T_3[6:3])), + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[11], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[10] + : ~_replacer_touch_ways_1_bits_T_7} + : _state_reg_T_107[12:10], + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? _state_reg_T_107[9:7] + : {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[8], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[7] + : ~_replacer_touch_ways_1_bits_T_7}} + : _state_reg_T_107[13:7], + (|(_replacer_touch_ways_1_bits_T_1[14:7])) + ? _state_reg_T_107[6:0] + : {~(|(_replacer_touch_ways_1_bits_T_3[6:3])), + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[4], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[3] + : ~_replacer_touch_ways_1_bits_T_7} + : _state_reg_T_107[5:3], + (|(_replacer_touch_ways_1_bits_T_3[6:3])) + ? _state_reg_T_107[2:0] + : {~(|(_replacer_touch_ways_1_bits_T_5[2:1])), + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? ~_replacer_touch_ways_1_bits_T_7 + : _state_reg_T_107[1], + (|(_replacer_touch_ways_1_bits_T_5[2:1])) + ? _state_reg_T_107[0] + : ~_replacer_touch_ways_1_bits_T_7}}}}; + else if (replacer_touch_ways_0_valid_REG) + state_reg <= + {~(replacer_touch_ways_0_bits_r[4]), _state_reg_T_52, _state_reg_T_105}; + end + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:24]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [4:0] i = 5'h0; i < 5'h19; i += 5'h1) begin + _RANDOM[i] = `RANDOM; + end + s1_pc_dup_0 = {_RANDOM[5'h0], _RANDOM[5'h1][8:0]}; + s1_pc_dup_1 = {_RANDOM[5'h1][31:9], _RANDOM[5'h2][17:0]}; + s1_pc_dup_2 = {_RANDOM[5'h2][31:18], _RANDOM[5'h3][26:0]}; + s1_pc_dup_3 = {_RANDOM[5'h3][31:27], _RANDOM[5'h4], _RANDOM[5'h5][3:0]}; + REG = _RANDOM[5'hF][12]; + REG_1 = _RANDOM[5'hF][13]; + ctrs_0_0 = _RANDOM[5'hF][15:14]; + ctrs_0_1 = _RANDOM[5'hF][17:16]; + ctrs_1_0 = _RANDOM[5'hF][19:18]; + ctrs_1_1 = _RANDOM[5'hF][21:20]; + ctrs_2_0 = _RANDOM[5'hF][23:22]; + ctrs_2_1 = _RANDOM[5'hF][25:24]; + ctrs_3_0 = _RANDOM[5'hF][27:26]; + ctrs_3_1 = _RANDOM[5'hF][29:28]; + ctrs_4_0 = _RANDOM[5'hF][31:30]; + ctrs_4_1 = _RANDOM[5'h10][1:0]; + ctrs_5_0 = _RANDOM[5'h10][3:2]; + ctrs_5_1 = _RANDOM[5'h10][5:4]; + ctrs_6_0 = _RANDOM[5'h10][7:6]; + ctrs_6_1 = _RANDOM[5'h10][9:8]; + ctrs_7_0 = _RANDOM[5'h10][11:10]; + ctrs_7_1 = _RANDOM[5'h10][13:12]; + ctrs_8_0 = _RANDOM[5'h10][15:14]; + ctrs_8_1 = _RANDOM[5'h10][17:16]; + ctrs_9_0 = _RANDOM[5'h10][19:18]; + ctrs_9_1 = _RANDOM[5'h10][21:20]; + ctrs_10_0 = _RANDOM[5'h10][23:22]; + ctrs_10_1 = _RANDOM[5'h10][25:24]; + ctrs_11_0 = _RANDOM[5'h10][27:26]; + ctrs_11_1 = _RANDOM[5'h10][29:28]; + ctrs_12_0 = _RANDOM[5'h10][31:30]; + ctrs_12_1 = _RANDOM[5'h11][1:0]; + ctrs_13_0 = _RANDOM[5'h11][3:2]; + ctrs_13_1 = _RANDOM[5'h11][5:4]; + ctrs_14_0 = _RANDOM[5'h11][7:6]; + ctrs_14_1 = _RANDOM[5'h11][9:8]; + ctrs_15_0 = _RANDOM[5'h11][11:10]; + ctrs_15_1 = _RANDOM[5'h11][13:12]; + ctrs_16_0 = _RANDOM[5'h11][15:14]; + ctrs_16_1 = _RANDOM[5'h11][17:16]; + ctrs_17_0 = _RANDOM[5'h11][19:18]; + ctrs_17_1 = _RANDOM[5'h11][21:20]; + ctrs_18_0 = _RANDOM[5'h11][23:22]; + ctrs_18_1 = _RANDOM[5'h11][25:24]; + ctrs_19_0 = _RANDOM[5'h11][27:26]; + ctrs_19_1 = _RANDOM[5'h11][29:28]; + ctrs_20_0 = _RANDOM[5'h11][31:30]; + ctrs_20_1 = _RANDOM[5'h12][1:0]; + ctrs_21_0 = _RANDOM[5'h12][3:2]; + ctrs_21_1 = _RANDOM[5'h12][5:4]; + ctrs_22_0 = _RANDOM[5'h12][7:6]; + ctrs_22_1 = _RANDOM[5'h12][9:8]; + ctrs_23_0 = _RANDOM[5'h12][11:10]; + ctrs_23_1 = _RANDOM[5'h12][13:12]; + ctrs_24_0 = _RANDOM[5'h12][15:14]; + ctrs_24_1 = _RANDOM[5'h12][17:16]; + ctrs_25_0 = _RANDOM[5'h12][19:18]; + ctrs_25_1 = _RANDOM[5'h12][21:20]; + ctrs_26_0 = _RANDOM[5'h12][23:22]; + ctrs_26_1 = _RANDOM[5'h12][25:24]; + ctrs_27_0 = _RANDOM[5'h12][27:26]; + ctrs_27_1 = _RANDOM[5'h12][29:28]; + ctrs_28_0 = _RANDOM[5'h12][31:30]; + ctrs_28_1 = _RANDOM[5'h13][1:0]; + ctrs_29_0 = _RANDOM[5'h13][3:2]; + ctrs_29_1 = _RANDOM[5'h13][5:4]; + ctrs_30_0 = _RANDOM[5'h13][7:6]; + ctrs_30_1 = _RANDOM[5'h13][9:8]; + ctrs_31_0 = _RANDOM[5'h13][11:10]; + ctrs_31_1 = _RANDOM[5'h13][13:12]; + state_reg = {_RANDOM[5'h13][31:14], _RANDOM[5'h14][12:0]}; + fauftb_enable = _RANDOM[5'h14][13]; + resp_meta_hit_r = _RANDOM[5'h14][14]; + resp_meta_hit_r_1 = _RANDOM[5'h14][15]; + resp_meta_pred_way_r = _RANDOM[5'h14][20:16]; + resp_meta_pred_way_r_1 = _RANDOM[5'h14][25:21]; + replacer_touch_ways_0_valid_REG = _RANDOM[5'h14][26]; + replacer_touch_ways_0_bits_r = _RANDOM[5'h14][31:27]; + u_s1_valid = _RANDOM[5'h15][0]; + u_s1_tag = _RANDOM[5'h15][16:1]; + u_s1_hit_oh = {_RANDOM[5'h15][31:17], _RANDOM[5'h16][16:0]}; + u_s1_hit = _RANDOM[5'h16][17]; + u_s1_ftb_entry_brSlots_0_offset = _RANDOM[5'h16][22:19]; + u_s1_ftb_entry_brSlots_0_lower = {_RANDOM[5'h16][31:23], _RANDOM[5'h17][2:0]}; + u_s1_ftb_entry_brSlots_0_tarStat = _RANDOM[5'h17][4:3]; + u_s1_ftb_entry_brSlots_0_valid = _RANDOM[5'h17][6]; + u_s1_ftb_entry_tailSlot_offset = _RANDOM[5'h17][10:7]; + u_s1_ftb_entry_tailSlot_lower = _RANDOM[5'h17][30:11]; + u_s1_ftb_entry_tailSlot_tarStat = {_RANDOM[5'h17][31], _RANDOM[5'h18][0]}; + u_s1_ftb_entry_tailSlot_sharing = _RANDOM[5'h18][1]; + u_s1_ftb_entry_tailSlot_valid = _RANDOM[5'h18][2]; + u_s1_ftb_entry_pftAddr = _RANDOM[5'h18][6:3]; + u_s1_ftb_entry_carry = _RANDOM[5'h18][7]; + u_s1_ftb_entry_always_taken_0 = _RANDOM[5'h18][12]; + u_s1_ftb_entry_always_taken_1 = _RANDOM[5'h18][13]; + u_s1_br_update_valids_0 = _RANDOM[5'h18][14]; + u_s1_br_update_valids_1 = _RANDOM[5'h18][15]; + u_s1_br_takens_0 = _RANDOM[5'h18][16]; + u_s1_br_takens_1 = _RANDOM[5'h18][17]; + io_perf_0_value_REG = _RANDOM[5'h18][19]; + io_perf_0_value_REG_1 = _RANDOM[5'h18][20]; + io_perf_1_value_REG = _RANDOM[5'h18][21]; + io_perf_1_value_REG_1 = _RANDOM[5'h18][22]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + ctrs_0_0 = 2'h2; + ctrs_0_1 = 2'h2; + ctrs_1_0 = 2'h2; + ctrs_1_1 = 2'h2; + ctrs_2_0 = 2'h2; + ctrs_2_1 = 2'h2; + ctrs_3_0 = 2'h2; + ctrs_3_1 = 2'h2; + ctrs_4_0 = 2'h2; + ctrs_4_1 = 2'h2; + ctrs_5_0 = 2'h2; + ctrs_5_1 = 2'h2; + ctrs_6_0 = 2'h2; + ctrs_6_1 = 2'h2; + ctrs_7_0 = 2'h2; + ctrs_7_1 = 2'h2; + ctrs_8_0 = 2'h2; + ctrs_8_1 = 2'h2; + ctrs_9_0 = 2'h2; + ctrs_9_1 = 2'h2; + ctrs_10_0 = 2'h2; + ctrs_10_1 = 2'h2; + ctrs_11_0 = 2'h2; + ctrs_11_1 = 2'h2; + ctrs_12_0 = 2'h2; + ctrs_12_1 = 2'h2; + ctrs_13_0 = 2'h2; + ctrs_13_1 = 2'h2; + ctrs_14_0 = 2'h2; + ctrs_14_1 = 2'h2; + ctrs_15_0 = 2'h2; + ctrs_15_1 = 2'h2; + ctrs_16_0 = 2'h2; + ctrs_16_1 = 2'h2; + ctrs_17_0 = 2'h2; + ctrs_17_1 = 2'h2; + ctrs_18_0 = 2'h2; + ctrs_18_1 = 2'h2; + ctrs_19_0 = 2'h2; + ctrs_19_1 = 2'h2; + ctrs_20_0 = 2'h2; + ctrs_20_1 = 2'h2; + ctrs_21_0 = 2'h2; + ctrs_21_1 = 2'h2; + ctrs_22_0 = 2'h2; + ctrs_22_1 = 2'h2; + ctrs_23_0 = 2'h2; + ctrs_23_1 = 2'h2; + ctrs_24_0 = 2'h2; + ctrs_24_1 = 2'h2; + ctrs_25_0 = 2'h2; + ctrs_25_1 = 2'h2; + ctrs_26_0 = 2'h2; + ctrs_26_1 = 2'h2; + ctrs_27_0 = 2'h2; + ctrs_27_1 = 2'h2; + ctrs_28_0 = 2'h2; + ctrs_28_1 = 2'h2; + ctrs_29_0 = 2'h2; + ctrs_29_1 = 2'h2; + ctrs_30_0 = 2'h2; + ctrs_30_1 = 2'h2; + ctrs_31_0 = 2'h2; + ctrs_31_1 = 2'h2; + state_reg = 31'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + DelayN_2 reset_vector_delay ( + .clock (clock), + .io_in (io_reset_vector), + .io_out (_reset_vector_delay_io_out) + ); + FauFTBWay ways_0 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_0_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_0_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_0_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_0_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_0_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_0_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_0_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_0_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_0_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_0_io_resp_pftAddr), + .io_resp_carry (_ways_0_io_resp_carry), + .io_resp_always_taken_0 (_ways_0_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_0_io_resp_always_taken_1), + .io_resp_hit (_ways_0_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_0_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_0), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_1 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_1_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_1_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_1_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_1_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_1_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_1_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_1_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_1_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_1_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_1_io_resp_pftAddr), + .io_resp_carry (_ways_1_io_resp_carry), + .io_resp_always_taken_0 (_ways_1_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_1_io_resp_always_taken_1), + .io_resp_hit (_ways_1_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_1_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_1), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_2 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_2_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_2_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_2_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_2_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_2_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_2_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_2_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_2_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_2_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_2_io_resp_pftAddr), + .io_resp_carry (_ways_2_io_resp_carry), + .io_resp_always_taken_0 (_ways_2_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_2_io_resp_always_taken_1), + .io_resp_hit (_ways_2_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_2_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_2), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_3 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_3_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_3_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_3_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_3_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_3_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_3_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_3_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_3_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_3_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_3_io_resp_pftAddr), + .io_resp_carry (_ways_3_io_resp_carry), + .io_resp_always_taken_0 (_ways_3_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_3_io_resp_always_taken_1), + .io_resp_hit (_ways_3_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_3_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_3), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_4 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_4_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_4_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_4_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_4_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_4_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_4_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_4_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_4_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_4_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_4_io_resp_pftAddr), + .io_resp_carry (_ways_4_io_resp_carry), + .io_resp_always_taken_0 (_ways_4_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_4_io_resp_always_taken_1), + .io_resp_hit (_ways_4_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_4_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_4), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_5 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_5_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_5_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_5_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_5_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_5_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_5_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_5_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_5_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_5_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_5_io_resp_pftAddr), + .io_resp_carry (_ways_5_io_resp_carry), + .io_resp_always_taken_0 (_ways_5_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_5_io_resp_always_taken_1), + .io_resp_hit (_ways_5_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_5_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_5), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_6 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_6_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_6_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_6_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_6_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_6_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_6_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_6_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_6_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_6_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_6_io_resp_pftAddr), + .io_resp_carry (_ways_6_io_resp_carry), + .io_resp_always_taken_0 (_ways_6_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_6_io_resp_always_taken_1), + .io_resp_hit (_ways_6_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_6_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_6), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_7 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_7_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_7_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_7_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_7_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_7_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_7_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_7_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_7_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_7_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_7_io_resp_pftAddr), + .io_resp_carry (_ways_7_io_resp_carry), + .io_resp_always_taken_0 (_ways_7_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_7_io_resp_always_taken_1), + .io_resp_hit (_ways_7_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_7_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_7), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_8 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_8_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_8_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_8_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_8_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_8_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_8_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_8_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_8_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_8_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_8_io_resp_pftAddr), + .io_resp_carry (_ways_8_io_resp_carry), + .io_resp_always_taken_0 (_ways_8_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_8_io_resp_always_taken_1), + .io_resp_hit (_ways_8_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_8_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_8), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_9 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_9_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_9_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_9_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_9_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_9_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_9_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_9_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_9_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_9_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_9_io_resp_pftAddr), + .io_resp_carry (_ways_9_io_resp_carry), + .io_resp_always_taken_0 (_ways_9_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_9_io_resp_always_taken_1), + .io_resp_hit (_ways_9_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_9_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_9), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_10 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_10_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_10_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_10_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_10_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_10_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_10_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_10_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_10_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_10_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_10_io_resp_pftAddr), + .io_resp_carry (_ways_10_io_resp_carry), + .io_resp_always_taken_0 (_ways_10_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_10_io_resp_always_taken_1), + .io_resp_hit (_ways_10_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_10_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_10), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_11 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_11_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_11_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_11_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_11_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_11_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_11_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_11_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_11_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_11_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_11_io_resp_pftAddr), + .io_resp_carry (_ways_11_io_resp_carry), + .io_resp_always_taken_0 (_ways_11_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_11_io_resp_always_taken_1), + .io_resp_hit (_ways_11_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_11_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_11), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_12 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_12_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_12_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_12_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_12_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_12_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_12_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_12_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_12_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_12_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_12_io_resp_pftAddr), + .io_resp_carry (_ways_12_io_resp_carry), + .io_resp_always_taken_0 (_ways_12_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_12_io_resp_always_taken_1), + .io_resp_hit (_ways_12_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_12_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_12), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_13 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_13_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_13_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_13_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_13_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_13_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_13_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_13_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_13_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_13_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_13_io_resp_pftAddr), + .io_resp_carry (_ways_13_io_resp_carry), + .io_resp_always_taken_0 (_ways_13_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_13_io_resp_always_taken_1), + .io_resp_hit (_ways_13_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_13_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_13), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_14 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_14_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_14_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_14_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_14_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_14_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_14_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_14_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_14_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_14_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_14_io_resp_pftAddr), + .io_resp_carry (_ways_14_io_resp_carry), + .io_resp_always_taken_0 (_ways_14_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_14_io_resp_always_taken_1), + .io_resp_hit (_ways_14_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_14_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_14), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_15 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_15_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_15_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_15_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_15_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_15_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_15_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_15_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_15_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_15_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_15_io_resp_pftAddr), + .io_resp_carry (_ways_15_io_resp_carry), + .io_resp_always_taken_0 (_ways_15_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_15_io_resp_always_taken_1), + .io_resp_hit (_ways_15_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_15_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_15), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_16 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_16_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_16_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_16_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_16_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_16_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_16_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_16_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_16_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_16_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_16_io_resp_pftAddr), + .io_resp_carry (_ways_16_io_resp_carry), + .io_resp_always_taken_0 (_ways_16_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_16_io_resp_always_taken_1), + .io_resp_hit (_ways_16_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_16_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_16), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_17 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_17_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_17_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_17_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_17_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_17_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_17_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_17_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_17_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_17_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_17_io_resp_pftAddr), + .io_resp_carry (_ways_17_io_resp_carry), + .io_resp_always_taken_0 (_ways_17_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_17_io_resp_always_taken_1), + .io_resp_hit (_ways_17_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_17_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_17), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_18 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_18_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_18_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_18_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_18_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_18_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_18_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_18_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_18_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_18_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_18_io_resp_pftAddr), + .io_resp_carry (_ways_18_io_resp_carry), + .io_resp_always_taken_0 (_ways_18_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_18_io_resp_always_taken_1), + .io_resp_hit (_ways_18_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_18_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_18), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_19 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_19_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_19_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_19_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_19_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_19_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_19_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_19_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_19_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_19_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_19_io_resp_pftAddr), + .io_resp_carry (_ways_19_io_resp_carry), + .io_resp_always_taken_0 (_ways_19_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_19_io_resp_always_taken_1), + .io_resp_hit (_ways_19_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_19_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_19), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_20 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_20_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_20_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_20_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_20_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_20_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_20_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_20_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_20_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_20_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_20_io_resp_pftAddr), + .io_resp_carry (_ways_20_io_resp_carry), + .io_resp_always_taken_0 (_ways_20_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_20_io_resp_always_taken_1), + .io_resp_hit (_ways_20_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_20_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_20), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_21 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_21_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_21_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_21_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_21_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_21_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_21_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_21_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_21_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_21_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_21_io_resp_pftAddr), + .io_resp_carry (_ways_21_io_resp_carry), + .io_resp_always_taken_0 (_ways_21_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_21_io_resp_always_taken_1), + .io_resp_hit (_ways_21_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_21_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_21), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_22 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_22_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_22_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_22_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_22_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_22_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_22_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_22_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_22_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_22_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_22_io_resp_pftAddr), + .io_resp_carry (_ways_22_io_resp_carry), + .io_resp_always_taken_0 (_ways_22_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_22_io_resp_always_taken_1), + .io_resp_hit (_ways_22_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_22_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_22), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_23 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_23_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_23_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_23_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_23_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_23_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_23_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_23_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_23_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_23_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_23_io_resp_pftAddr), + .io_resp_carry (_ways_23_io_resp_carry), + .io_resp_always_taken_0 (_ways_23_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_23_io_resp_always_taken_1), + .io_resp_hit (_ways_23_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_23_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_23), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_24 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_24_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_24_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_24_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_24_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_24_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_24_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_24_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_24_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_24_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_24_io_resp_pftAddr), + .io_resp_carry (_ways_24_io_resp_carry), + .io_resp_always_taken_0 (_ways_24_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_24_io_resp_always_taken_1), + .io_resp_hit (_ways_24_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_24_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_24), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_25 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_25_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_25_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_25_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_25_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_25_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_25_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_25_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_25_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_25_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_25_io_resp_pftAddr), + .io_resp_carry (_ways_25_io_resp_carry), + .io_resp_always_taken_0 (_ways_25_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_25_io_resp_always_taken_1), + .io_resp_hit (_ways_25_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_25_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_25), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_26 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_26_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_26_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_26_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_26_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_26_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_26_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_26_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_26_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_26_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_26_io_resp_pftAddr), + .io_resp_carry (_ways_26_io_resp_carry), + .io_resp_always_taken_0 (_ways_26_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_26_io_resp_always_taken_1), + .io_resp_hit (_ways_26_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_26_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_26), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_27 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_27_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_27_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_27_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_27_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_27_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_27_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_27_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_27_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_27_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_27_io_resp_pftAddr), + .io_resp_carry (_ways_27_io_resp_carry), + .io_resp_always_taken_0 (_ways_27_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_27_io_resp_always_taken_1), + .io_resp_hit (_ways_27_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_27_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_27), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_28 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_28_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_28_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_28_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_28_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_28_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_28_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_28_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_28_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_28_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_28_io_resp_pftAddr), + .io_resp_carry (_ways_28_io_resp_carry), + .io_resp_always_taken_0 (_ways_28_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_28_io_resp_always_taken_1), + .io_resp_hit (_ways_28_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_28_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_28), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_29 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_29_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_29_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_29_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_29_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_29_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_29_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_29_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_29_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_29_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_29_io_resp_pftAddr), + .io_resp_carry (_ways_29_io_resp_carry), + .io_resp_always_taken_0 (_ways_29_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_29_io_resp_always_taken_1), + .io_resp_hit (_ways_29_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_29_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_29), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_30 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_30_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_30_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_30_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_30_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_30_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_30_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_30_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_30_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_30_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_30_io_resp_pftAddr), + .io_resp_carry (_ways_30_io_resp_carry), + .io_resp_always_taken_0 (_ways_30_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_30_io_resp_always_taken_1), + .io_resp_hit (_ways_30_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_30_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_30), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + FauFTBWay ways_31 ( + .clock (clock), + .reset (reset), + .io_req_tag (s1_pc_dup_0[16:1]), + .io_resp_brSlots_0_offset (_ways_31_io_resp_brSlots_0_offset), + .io_resp_brSlots_0_lower (_ways_31_io_resp_brSlots_0_lower), + .io_resp_brSlots_0_tarStat (_ways_31_io_resp_brSlots_0_tarStat), + .io_resp_brSlots_0_valid (_ways_31_io_resp_brSlots_0_valid), + .io_resp_tailSlot_offset (_ways_31_io_resp_tailSlot_offset), + .io_resp_tailSlot_lower (_ways_31_io_resp_tailSlot_lower), + .io_resp_tailSlot_tarStat (_ways_31_io_resp_tailSlot_tarStat), + .io_resp_tailSlot_sharing (_ways_31_io_resp_tailSlot_sharing), + .io_resp_tailSlot_valid (_ways_31_io_resp_tailSlot_valid), + .io_resp_pftAddr (_ways_31_io_resp_pftAddr), + .io_resp_carry (_ways_31_io_resp_carry), + .io_resp_always_taken_0 (_ways_31_io_resp_always_taken_0), + .io_resp_always_taken_1 (_ways_31_io_resp_always_taken_1), + .io_resp_hit (_ways_31_io_resp_hit), + .io_update_req_tag (io_update_bits_pc[16:1]), + .io_update_hit (_ways_31_io_update_hit), + .io_write_valid (u_s1_ways_write_valid_31), + .io_write_entry_brSlots_0_offset (u_s1_ftb_entry_brSlots_0_offset), + .io_write_entry_brSlots_0_lower (u_s1_ftb_entry_brSlots_0_lower), + .io_write_entry_brSlots_0_tarStat (u_s1_ftb_entry_brSlots_0_tarStat), + .io_write_entry_brSlots_0_valid (u_s1_ftb_entry_brSlots_0_valid), + .io_write_entry_tailSlot_offset (u_s1_ftb_entry_tailSlot_offset), + .io_write_entry_tailSlot_lower (u_s1_ftb_entry_tailSlot_lower), + .io_write_entry_tailSlot_tarStat (u_s1_ftb_entry_tailSlot_tarStat), + .io_write_entry_tailSlot_sharing (u_s1_ftb_entry_tailSlot_sharing), + .io_write_entry_tailSlot_valid (u_s1_ftb_entry_tailSlot_valid), + .io_write_entry_pftAddr (u_s1_ftb_entry_pftAddr), + .io_write_entry_carry (u_s1_ftb_entry_carry), + .io_write_entry_always_taken_0 (u_s1_ftb_entry_always_taken_0), + .io_write_entry_always_taken_1 (u_s1_ftb_entry_always_taken_1), + .io_write_tag (u_s1_tag) + ); + assign io_out_s1_pc_0 = s1_pc_dup_0; + assign io_out_s1_pc_1 = s1_pc_dup_1; + assign io_out_s1_pc_2 = s1_pc_dup_2; + assign io_out_s1_pc_3 = s1_pc_dup_3; + assign io_out_s1_full_pred_0_br_taken_mask_0 = _s1_hit_full_pred_T_1102; + assign io_out_s1_full_pred_0_br_taken_mask_1 = _s1_hit_full_pred_T_1165; + assign io_out_s1_full_pred_0_slot_valids_0 = _s1_hit_full_pred_T_976; + assign io_out_s1_full_pred_0_slot_valids_1 = _s1_hit_full_pred_T_1039; + assign io_out_s1_full_pred_0_targets_0 = _s1_hit_full_pred_T_850; + assign io_out_s1_full_pred_0_targets_1 = _s1_hit_full_pred_T_913; + assign io_out_s1_full_pred_0_offsets_0 = _s1_hit_full_pred_T_661; + assign io_out_s1_full_pred_0_offsets_1 = _s1_hit_full_pred_T_724; + assign io_out_s1_full_pred_0_fallThroughAddr = _s1_hit_full_pred_T_598; + assign io_out_s1_full_pred_0_is_br_sharing = _s1_hit_full_pred_T_157; + assign io_out_s1_full_pred_0_hit = io_out_s1_full_pred_3_hit_0; + assign io_out_s1_full_pred_1_br_taken_mask_0 = _s1_hit_full_pred_T_1102; + assign io_out_s1_full_pred_1_br_taken_mask_1 = _s1_hit_full_pred_T_1165; + assign io_out_s1_full_pred_1_slot_valids_0 = _s1_hit_full_pred_T_976; + assign io_out_s1_full_pred_1_slot_valids_1 = _s1_hit_full_pred_T_1039; + assign io_out_s1_full_pred_1_targets_0 = _s1_hit_full_pred_T_850; + assign io_out_s1_full_pred_1_targets_1 = _s1_hit_full_pred_T_913; + assign io_out_s1_full_pred_1_offsets_0 = _s1_hit_full_pred_T_661; + assign io_out_s1_full_pred_1_offsets_1 = _s1_hit_full_pred_T_724; + assign io_out_s1_full_pred_1_fallThroughAddr = _s1_hit_full_pred_T_598; + assign io_out_s1_full_pred_1_is_br_sharing = _s1_hit_full_pred_T_157; + assign io_out_s1_full_pred_1_hit = io_out_s1_full_pred_3_hit_0; + assign io_out_s1_full_pred_2_br_taken_mask_0 = _s1_hit_full_pred_T_1102; + assign io_out_s1_full_pred_2_br_taken_mask_1 = _s1_hit_full_pred_T_1165; + assign io_out_s1_full_pred_2_slot_valids_0 = _s1_hit_full_pred_T_976; + assign io_out_s1_full_pred_2_slot_valids_1 = _s1_hit_full_pred_T_1039; + assign io_out_s1_full_pred_2_targets_0 = _s1_hit_full_pred_T_850; + assign io_out_s1_full_pred_2_targets_1 = _s1_hit_full_pred_T_913; + assign io_out_s1_full_pred_2_offsets_0 = _s1_hit_full_pred_T_661; + assign io_out_s1_full_pred_2_offsets_1 = _s1_hit_full_pred_T_724; + assign io_out_s1_full_pred_2_fallThroughAddr = _s1_hit_full_pred_T_598; + assign io_out_s1_full_pred_2_is_br_sharing = _s1_hit_full_pred_T_157; + assign io_out_s1_full_pred_2_hit = io_out_s1_full_pred_3_hit_0; + assign io_out_s1_full_pred_3_br_taken_mask_0 = _s1_hit_full_pred_T_1102; + assign io_out_s1_full_pred_3_br_taken_mask_1 = _s1_hit_full_pred_T_1165; + assign io_out_s1_full_pred_3_slot_valids_0 = _s1_hit_full_pred_T_976; + assign io_out_s1_full_pred_3_slot_valids_1 = _s1_hit_full_pred_T_1039; + assign io_out_s1_full_pred_3_targets_0 = _s1_hit_full_pred_T_850; + assign io_out_s1_full_pred_3_targets_1 = _s1_hit_full_pred_T_913; + assign io_out_s1_full_pred_3_offsets_0 = _s1_hit_full_pred_T_661; + assign io_out_s1_full_pred_3_offsets_1 = _s1_hit_full_pred_T_724; + assign io_out_s1_full_pred_3_fallThroughAddr = _s1_hit_full_pred_T_598; + assign io_out_s1_full_pred_3_fallThroughErr = + _ways_0_io_resp_hit & s1_possible_full_preds_0_fallThroughErr | _ways_1_io_resp_hit + & s1_possible_full_preds_1_fallThroughErr | _ways_2_io_resp_hit + & s1_possible_full_preds_2_fallThroughErr | _ways_3_io_resp_hit + & s1_possible_full_preds_3_fallThroughErr | _ways_4_io_resp_hit + & s1_possible_full_preds_4_fallThroughErr | _ways_5_io_resp_hit + & s1_possible_full_preds_5_fallThroughErr | _ways_6_io_resp_hit + & s1_possible_full_preds_6_fallThroughErr | _ways_7_io_resp_hit + & s1_possible_full_preds_7_fallThroughErr | _ways_8_io_resp_hit + & s1_possible_full_preds_8_fallThroughErr | _ways_9_io_resp_hit + & s1_possible_full_preds_9_fallThroughErr | _ways_10_io_resp_hit + & s1_possible_full_preds_10_fallThroughErr | _ways_11_io_resp_hit + & s1_possible_full_preds_11_fallThroughErr | _ways_12_io_resp_hit + & s1_possible_full_preds_12_fallThroughErr | _ways_13_io_resp_hit + & s1_possible_full_preds_13_fallThroughErr | _ways_14_io_resp_hit + & s1_possible_full_preds_14_fallThroughErr | _ways_15_io_resp_hit + & s1_possible_full_preds_15_fallThroughErr | _ways_16_io_resp_hit + & s1_possible_full_preds_16_fallThroughErr | _ways_17_io_resp_hit + & s1_possible_full_preds_17_fallThroughErr | _ways_18_io_resp_hit + & s1_possible_full_preds_18_fallThroughErr | _ways_19_io_resp_hit + & s1_possible_full_preds_19_fallThroughErr | _ways_20_io_resp_hit + & s1_possible_full_preds_20_fallThroughErr | _ways_21_io_resp_hit + & s1_possible_full_preds_21_fallThroughErr | _ways_22_io_resp_hit + & s1_possible_full_preds_22_fallThroughErr | _ways_23_io_resp_hit + & s1_possible_full_preds_23_fallThroughErr | _ways_24_io_resp_hit + & s1_possible_full_preds_24_fallThroughErr | _ways_25_io_resp_hit + & s1_possible_full_preds_25_fallThroughErr | _ways_26_io_resp_hit + & s1_possible_full_preds_26_fallThroughErr | _ways_27_io_resp_hit + & s1_possible_full_preds_27_fallThroughErr | _ways_28_io_resp_hit + & s1_possible_full_preds_28_fallThroughErr | _ways_29_io_resp_hit + & s1_possible_full_preds_29_fallThroughErr | _ways_30_io_resp_hit + & s1_possible_full_preds_30_fallThroughErr | _ways_31_io_resp_hit + & s1_possible_full_preds_31_fallThroughErr; + assign io_out_s1_full_pred_3_is_br_sharing = _s1_hit_full_pred_T_157; + assign io_out_s1_full_pred_3_hit = io_out_s1_full_pred_3_hit_0; + assign io_out_last_stage_meta = {217'h0, resp_meta_pred_way_r_1, resp_meta_hit_r_1}; + assign io_perf_0_value = {5'h0, io_perf_0_value_REG_1}; + assign io_perf_1_value = {5'h0, io_perf_1_value_REG_1}; +endmodule + diff --git a/rtl/BPUTop/FauFTBWay.sv b/rtl/BPUTop/FauFTBWay.sv new file mode 100644 index 0000000..4d2174e --- /dev/null +++ b/rtl/BPUTop/FauFTBWay.sv @@ -0,0 +1,187 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FauFTBWay( + input clock, + input reset, + input [15:0] io_req_tag, + output [3:0] io_resp_brSlots_0_offset, + output [11:0] io_resp_brSlots_0_lower, + output [1:0] io_resp_brSlots_0_tarStat, + output io_resp_brSlots_0_valid, + output [3:0] io_resp_tailSlot_offset, + output [19:0] io_resp_tailSlot_lower, + output [1:0] io_resp_tailSlot_tarStat, + output io_resp_tailSlot_sharing, + output io_resp_tailSlot_valid, + output [3:0] io_resp_pftAddr, + output io_resp_carry, + output io_resp_always_taken_0, + output io_resp_always_taken_1, + output io_resp_hit, + input [15:0] io_update_req_tag, + output io_update_hit, + input io_write_valid, + input [3:0] io_write_entry_brSlots_0_offset, + input [11:0] io_write_entry_brSlots_0_lower, + input [1:0] io_write_entry_brSlots_0_tarStat, + input io_write_entry_brSlots_0_valid, + input [3:0] io_write_entry_tailSlot_offset, + input [19:0] io_write_entry_tailSlot_lower, + input [1:0] io_write_entry_tailSlot_tarStat, + input io_write_entry_tailSlot_sharing, + input io_write_entry_tailSlot_valid, + input [3:0] io_write_entry_pftAddr, + input io_write_entry_carry, + input io_write_entry_always_taken_0, + input io_write_entry_always_taken_1, + input [15:0] io_write_tag +); + + reg [3:0] data_brSlots_0_offset; + reg [11:0] data_brSlots_0_lower; + reg [1:0] data_brSlots_0_tarStat; + reg data_brSlots_0_valid; + reg [3:0] data_tailSlot_offset; + reg [19:0] data_tailSlot_lower; + reg [1:0] data_tailSlot_tarStat; + reg data_tailSlot_sharing; + reg data_tailSlot_valid; + reg [3:0] data_pftAddr; + reg data_carry; + reg data_always_taken_0; + reg data_always_taken_1; + reg [15:0] tag; + reg valid; + always @(posedge clock) begin + if (io_write_valid) begin + data_brSlots_0_offset <= io_write_entry_brSlots_0_offset; + data_brSlots_0_lower <= io_write_entry_brSlots_0_lower; + data_brSlots_0_tarStat <= io_write_entry_brSlots_0_tarStat; + data_brSlots_0_valid <= io_write_entry_brSlots_0_valid; + data_tailSlot_offset <= io_write_entry_tailSlot_offset; + data_tailSlot_lower <= io_write_entry_tailSlot_lower; + data_tailSlot_tarStat <= io_write_entry_tailSlot_tarStat; + data_tailSlot_sharing <= io_write_entry_tailSlot_sharing; + data_tailSlot_valid <= io_write_entry_tailSlot_valid; + data_pftAddr <= io_write_entry_pftAddr; + data_carry <= io_write_entry_carry; + data_always_taken_0 <= io_write_entry_always_taken_0; + data_always_taken_1 <= io_write_entry_always_taken_1; + tag <= io_write_tag; + end + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) + valid <= 1'h0; + else + valid <= io_write_valid & ~valid | valid; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; + end + data_brSlots_0_offset = _RANDOM[2'h0][4:1]; + data_brSlots_0_lower = _RANDOM[2'h0][16:5]; + data_brSlots_0_tarStat = _RANDOM[2'h0][18:17]; + data_brSlots_0_valid = _RANDOM[2'h0][20]; + data_tailSlot_offset = _RANDOM[2'h0][24:21]; + data_tailSlot_lower = {_RANDOM[2'h0][31:25], _RANDOM[2'h1][12:0]}; + data_tailSlot_tarStat = _RANDOM[2'h1][14:13]; + data_tailSlot_sharing = _RANDOM[2'h1][15]; + data_tailSlot_valid = _RANDOM[2'h1][16]; + data_pftAddr = _RANDOM[2'h1][20:17]; + data_carry = _RANDOM[2'h1][21]; + data_always_taken_0 = _RANDOM[2'h1][26]; + data_always_taken_1 = _RANDOM[2'h1][27]; + tag = {_RANDOM[2'h1][31:28], _RANDOM[2'h2][11:0]}; + valid = _RANDOM[2'h2][12]; + `endif // RANDOMIZE_REG_INIT + if (reset) + valid = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_resp_brSlots_0_offset = data_brSlots_0_offset; + assign io_resp_brSlots_0_lower = data_brSlots_0_lower; + assign io_resp_brSlots_0_tarStat = data_brSlots_0_tarStat; + assign io_resp_brSlots_0_valid = data_brSlots_0_valid; + assign io_resp_tailSlot_offset = data_tailSlot_offset; + assign io_resp_tailSlot_lower = data_tailSlot_lower; + assign io_resp_tailSlot_tarStat = data_tailSlot_tarStat; + assign io_resp_tailSlot_sharing = data_tailSlot_sharing; + assign io_resp_tailSlot_valid = data_tailSlot_valid; + assign io_resp_pftAddr = data_pftAddr; + assign io_resp_carry = data_carry; + assign io_resp_always_taken_0 = data_always_taken_0; + assign io_resp_always_taken_1 = data_always_taken_1; + assign io_resp_hit = tag == io_req_tag & valid; + assign io_update_hit = + tag == io_update_req_tag & valid | io_write_tag == io_update_req_tag & io_write_valid; +endmodule + diff --git a/rtl/BPUTop/Folded1WDataModuleTemplate.sv b/rtl/BPUTop/Folded1WDataModuleTemplate.sv new file mode 100644 index 0000000..7dc5280 --- /dev/null +++ b/rtl/BPUTop/Folded1WDataModuleTemplate.sv @@ -0,0 +1,146 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module Folded1WDataModuleTemplate( + input clock, + input reset, + input io_ren_0, + input [7:0] io_raddr_0, + output io_rdata_0, + input io_wen, + input [7:0] io_waddr, + input io_wdata, + input io_resetEn +); + + wire [15:0] _data_ext_R0_data; + reg doing_reset; + reg [3:0] resetRow; + reg [7:0] raddr_0; + wire [15:0] _GEN = + {{_data_ext_R0_data[15]}, + {_data_ext_R0_data[14]}, + {_data_ext_R0_data[13]}, + {_data_ext_R0_data[12]}, + {_data_ext_R0_data[11]}, + {_data_ext_R0_data[10]}, + {_data_ext_R0_data[9]}, + {_data_ext_R0_data[8]}, + {_data_ext_R0_data[7]}, + {_data_ext_R0_data[6]}, + {_data_ext_R0_data[5]}, + {_data_ext_R0_data[4]}, + {_data_ext_R0_data[3]}, + {_data_ext_R0_data[2]}, + {_data_ext_R0_data[1]}, + {_data_ext_R0_data[0]}}; + always @(posedge clock or posedge reset) begin + if (reset) begin + doing_reset <= 1'h1; + resetRow <= 4'h0; + end + else begin + doing_reset <= resetRow != 4'hF & (io_resetEn | doing_reset); + if (doing_reset) + resetRow <= 4'(resetRow + 4'h1); + end + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_ren_0) + raddr_0 <= io_raddr_0; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; + resetRow = _RANDOM[/*Zero width*/ 1'b0][4:1]; + raddr_0 = _RANDOM[/*Zero width*/ 1'b0][12:5]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + doing_reset = 1'h1; + resetRow = 4'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + data_16x16 data_ext ( + .R0_addr (raddr_0[7:4]), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_data_ext_R0_data), + .W0_addr (io_waddr[7:4]), + .W0_en (~doing_reset & io_wen), + .W0_clk (clock), + .W0_data ({16{io_wdata}}), + .W1_addr (resetRow), + .W1_en (doing_reset), + .W1_clk (clock), + .W1_data (16'h0) + ); + assign io_rdata_0 = ~doing_reset & _GEN[raddr_0[3:0]]; +endmodule + diff --git a/rtl/BPUTop/Folded1WDataModuleTemplate_2.sv b/rtl/BPUTop/Folded1WDataModuleTemplate_2.sv new file mode 100644 index 0000000..1c7abf7 --- /dev/null +++ b/rtl/BPUTop/Folded1WDataModuleTemplate_2.sv @@ -0,0 +1,146 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module Folded1WDataModuleTemplate_2( + input clock, + input reset, + input io_ren_0, + input [8:0] io_raddr_0, + output io_rdata_0, + input io_wen, + input [8:0] io_waddr, + input io_wdata, + input io_resetEn +); + + wire [15:0] _data_ext_R0_data; + reg doing_reset; + reg [4:0] resetRow; + reg [8:0] raddr_0; + wire [15:0] _GEN = + {{_data_ext_R0_data[15]}, + {_data_ext_R0_data[14]}, + {_data_ext_R0_data[13]}, + {_data_ext_R0_data[12]}, + {_data_ext_R0_data[11]}, + {_data_ext_R0_data[10]}, + {_data_ext_R0_data[9]}, + {_data_ext_R0_data[8]}, + {_data_ext_R0_data[7]}, + {_data_ext_R0_data[6]}, + {_data_ext_R0_data[5]}, + {_data_ext_R0_data[4]}, + {_data_ext_R0_data[3]}, + {_data_ext_R0_data[2]}, + {_data_ext_R0_data[1]}, + {_data_ext_R0_data[0]}}; + always @(posedge clock or posedge reset) begin + if (reset) begin + doing_reset <= 1'h1; + resetRow <= 5'h0; + end + else begin + doing_reset <= resetRow != 5'h1F & (io_resetEn | doing_reset); + if (doing_reset) + resetRow <= 5'(resetRow + 5'h1); + end + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_ren_0) + raddr_0 <= io_raddr_0; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; + resetRow = _RANDOM[/*Zero width*/ 1'b0][5:1]; + raddr_0 = _RANDOM[/*Zero width*/ 1'b0][14:6]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + doing_reset = 1'h1; + resetRow = 5'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + data_32x16 data_ext ( + .R0_addr (raddr_0[8:4]), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_data_ext_R0_data), + .W0_addr (io_waddr[8:4]), + .W0_en (~doing_reset & io_wen), + .W0_clk (clock), + .W0_data ({16{io_wdata}}), + .W1_addr (resetRow), + .W1_en (doing_reset), + .W1_clk (clock), + .W1_data (16'h0) + ); + assign io_rdata_0 = ~doing_reset & _GEN[raddr_0[3:0]]; +endmodule + diff --git a/rtl/BPUTop/FoldedSRAMTemplate.sv b/rtl/BPUTop/FoldedSRAMTemplate.sv new file mode 100644 index 0000000..3c29c57 --- /dev/null +++ b/rtl/BPUTop/FoldedSRAMTemplate.sv @@ -0,0 +1,224 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FoldedSRAMTemplate( + input clock, + input reset, + output io_r_req_ready, + input io_r_req_valid, + input [10:0] io_r_req_bits_setIdx, + output io_r_resp_data_0, + output io_r_resp_data_1, + input io_w_req_valid, + input [10:0] io_w_req_bits_setIdx, + input io_w_req_bits_data_0, + input io_w_req_bits_data_1, + input [1:0] io_w_req_bits_waymask, + input extra_reset +); + + wire _array_io_r_resp_data_0; + wire _array_io_r_resp_data_1; + wire _array_io_r_resp_data_2; + wire _array_io_r_resp_data_3; + wire _array_io_r_resp_data_4; + wire _array_io_r_resp_data_5; + wire _array_io_r_resp_data_6; + wire _array_io_r_resp_data_7; + wire _array_io_r_resp_data_8; + wire _array_io_r_resp_data_9; + wire _array_io_r_resp_data_10; + wire _array_io_r_resp_data_11; + wire _array_io_r_resp_data_12; + wire _array_io_r_resp_data_13; + wire _array_io_r_resp_data_14; + wire _array_io_r_resp_data_15; + reg [2:0] ridx; + reg holdRidx_last_r; + reg [2:0] holdRidx_hold_data; + wire [2:0] holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data; + reg holdRidx_last_r_1; + reg [2:0] holdRidx_hold_data_1; + wire [2:0] holdRidx_1 = holdRidx_last_r_1 ? ridx : holdRidx_hold_data_1; + wire _wmask_T_3 = io_w_req_bits_setIdx[2:0] == 3'h0; + wire _wmask_T_9 = io_w_req_bits_setIdx[2:0] == 3'h1; + wire _wmask_T_15 = io_w_req_bits_setIdx[2:0] == 3'h2; + wire _wmask_T_21 = io_w_req_bits_setIdx[2:0] == 3'h3; + wire _wmask_T_27 = io_w_req_bits_setIdx[2:0] == 3'h4; + wire _wmask_T_33 = io_w_req_bits_setIdx[2:0] == 3'h5; + wire _wmask_T_39 = io_w_req_bits_setIdx[2:0] == 3'h6; + always @(posedge clock) begin + if (io_r_req_valid) + ridx <= io_r_req_bits_setIdx[2:0]; + if (holdRidx_last_r) + holdRidx_hold_data <= ridx; + if (holdRidx_last_r_1) + holdRidx_hold_data_1 <= ridx; + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) begin + holdRidx_last_r <= 1'h0; + holdRidx_last_r_1 <= 1'h0; + end + else begin + if (io_r_req_valid | holdRidx_last_r) + holdRidx_last_r <= io_r_req_valid; + if (io_r_req_valid | holdRidx_last_r_1) + holdRidx_last_r_1 <= io_r_req_valid; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + ridx = _RANDOM[/*Zero width*/ 1'b0][2:0]; + holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][3]; + holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][6:4]; + holdRidx_last_r_1 = _RANDOM[/*Zero width*/ 1'b0][7]; + holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][10:8]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + holdRidx_last_r = 1'h0; + holdRidx_last_r_1 = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_14 array ( + .clock (clock), + .reset (reset), + .io_r_req_ready (io_r_req_ready), + .io_r_req_valid (io_r_req_valid), + .io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:3]), + .io_r_resp_data_0 (_array_io_r_resp_data_0), + .io_r_resp_data_1 (_array_io_r_resp_data_1), + .io_r_resp_data_2 (_array_io_r_resp_data_2), + .io_r_resp_data_3 (_array_io_r_resp_data_3), + .io_r_resp_data_4 (_array_io_r_resp_data_4), + .io_r_resp_data_5 (_array_io_r_resp_data_5), + .io_r_resp_data_6 (_array_io_r_resp_data_6), + .io_r_resp_data_7 (_array_io_r_resp_data_7), + .io_r_resp_data_8 (_array_io_r_resp_data_8), + .io_r_resp_data_9 (_array_io_r_resp_data_9), + .io_r_resp_data_10 (_array_io_r_resp_data_10), + .io_r_resp_data_11 (_array_io_r_resp_data_11), + .io_r_resp_data_12 (_array_io_r_resp_data_12), + .io_r_resp_data_13 (_array_io_r_resp_data_13), + .io_r_resp_data_14 (_array_io_r_resp_data_14), + .io_r_resp_data_15 (_array_io_r_resp_data_15), + .io_w_req_valid (io_w_req_valid), + .io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:3]), + .io_w_req_bits_data_0 (io_w_req_bits_data_0), + .io_w_req_bits_data_1 (io_w_req_bits_data_1), + .io_w_req_bits_data_2 (io_w_req_bits_data_0), + .io_w_req_bits_data_3 (io_w_req_bits_data_1), + .io_w_req_bits_data_4 (io_w_req_bits_data_0), + .io_w_req_bits_data_5 (io_w_req_bits_data_1), + .io_w_req_bits_data_6 (io_w_req_bits_data_0), + .io_w_req_bits_data_7 (io_w_req_bits_data_1), + .io_w_req_bits_data_8 (io_w_req_bits_data_0), + .io_w_req_bits_data_9 (io_w_req_bits_data_1), + .io_w_req_bits_data_10 (io_w_req_bits_data_0), + .io_w_req_bits_data_11 (io_w_req_bits_data_1), + .io_w_req_bits_data_12 (io_w_req_bits_data_0), + .io_w_req_bits_data_13 (io_w_req_bits_data_1), + .io_w_req_bits_data_14 (io_w_req_bits_data_0), + .io_w_req_bits_data_15 (io_w_req_bits_data_1), + .io_w_req_bits_waymask + ({(&(io_w_req_bits_setIdx[2:0])) & io_w_req_bits_waymask[1], + (&(io_w_req_bits_setIdx[2:0])) & io_w_req_bits_waymask[0], + _wmask_T_39 & io_w_req_bits_waymask[1], + _wmask_T_39 & io_w_req_bits_waymask[0], + _wmask_T_33 & io_w_req_bits_waymask[1], + _wmask_T_33 & io_w_req_bits_waymask[0], + _wmask_T_27 & io_w_req_bits_waymask[1], + _wmask_T_27 & io_w_req_bits_waymask[0], + _wmask_T_21 & io_w_req_bits_waymask[1], + _wmask_T_21 & io_w_req_bits_waymask[0], + _wmask_T_15 & io_w_req_bits_waymask[1], + _wmask_T_15 & io_w_req_bits_waymask[0], + _wmask_T_9 & io_w_req_bits_waymask[1], + _wmask_T_9 & io_w_req_bits_waymask[0], + _wmask_T_3 & io_w_req_bits_waymask[1], + _wmask_T_3 & io_w_req_bits_waymask[0]}), + .extra_reset (extra_reset) + ); + assign io_r_resp_data_0 = + holdRidx == 3'h0 & _array_io_r_resp_data_0 | holdRidx == 3'h1 + & _array_io_r_resp_data_2 | holdRidx == 3'h2 & _array_io_r_resp_data_4 + | holdRidx == 3'h3 & _array_io_r_resp_data_6 | holdRidx == 3'h4 + & _array_io_r_resp_data_8 | holdRidx == 3'h5 & _array_io_r_resp_data_10 + | holdRidx == 3'h6 & _array_io_r_resp_data_12 | (&holdRidx) + & _array_io_r_resp_data_14; + assign io_r_resp_data_1 = + holdRidx_1 == 3'h0 & _array_io_r_resp_data_1 | holdRidx_1 == 3'h1 + & _array_io_r_resp_data_3 | holdRidx_1 == 3'h2 & _array_io_r_resp_data_5 + | holdRidx_1 == 3'h3 & _array_io_r_resp_data_7 | holdRidx_1 == 3'h4 + & _array_io_r_resp_data_9 | holdRidx_1 == 3'h5 & _array_io_r_resp_data_11 + | holdRidx_1 == 3'h6 & _array_io_r_resp_data_13 | (&holdRidx_1) + & _array_io_r_resp_data_15; +endmodule + diff --git a/rtl/BPUTop/FoldedSRAMTemplate_1.sv b/rtl/BPUTop/FoldedSRAMTemplate_1.sv new file mode 100644 index 0000000..4e5dc0f --- /dev/null +++ b/rtl/BPUTop/FoldedSRAMTemplate_1.sv @@ -0,0 +1,100 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FoldedSRAMTemplate_1( + input clock, + input reset, + output io_r_req_ready, + input io_r_req_valid, + input [8:0] io_r_req_bits_setIdx, + output io_r_resp_data_0_valid, + output [7:0] io_r_resp_data_0_tag, + output [2:0] io_r_resp_data_0_ctr, + output io_r_resp_data_1_valid, + output [7:0] io_r_resp_data_1_tag, + output [2:0] io_r_resp_data_1_ctr, + input io_w_req_valid, + input [8:0] io_w_req_bits_setIdx, + input [7:0] io_w_req_bits_data_0_tag, + input [2:0] io_w_req_bits_data_0_ctr, + input [7:0] io_w_req_bits_data_1_tag, + input [2:0] io_w_req_bits_data_1_ctr, + input [1:0] io_w_req_bits_waymask +); + + SRAMTemplate_15 array ( + .clock (clock), + .reset (reset), + .io_r_req_ready (io_r_req_ready), + .io_r_req_valid (io_r_req_valid), + .io_r_req_bits_setIdx (io_r_req_bits_setIdx), + .io_r_resp_data_0_valid (io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (io_r_resp_data_1_ctr), + .io_w_req_valid (io_w_req_valid), + .io_w_req_bits_setIdx (io_w_req_bits_setIdx), + .io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag), + .io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr), + .io_w_req_bits_data_1_tag (io_w_req_bits_data_1_tag), + .io_w_req_bits_data_1_ctr (io_w_req_bits_data_1_ctr), + .io_w_req_bits_waymask (io_w_req_bits_waymask) + ); +endmodule + diff --git a/rtl/BPUTop/FoldedSRAMTemplate_20.sv b/rtl/BPUTop/FoldedSRAMTemplate_20.sv new file mode 100644 index 0000000..f5e60cb --- /dev/null +++ b/rtl/BPUTop/FoldedSRAMTemplate_20.sv @@ -0,0 +1,180 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FoldedSRAMTemplate_20( + input clock, + input reset, + input io_r_req_valid, + input [10:0] io_r_req_bits_setIdx, + output [1:0] io_r_resp_data_0, + output [1:0] io_r_resp_data_1, + input io_w_req_valid, + input [10:0] io_w_req_bits_setIdx, + input [1:0] io_w_req_bits_data_0, + input [1:0] io_w_req_bits_data_1, + input [1:0] io_w_req_bits_waymask +); + + wire [1:0] _array_io_r_resp_data_0; + wire [1:0] _array_io_r_resp_data_1; + wire [1:0] _array_io_r_resp_data_2; + wire [1:0] _array_io_r_resp_data_3; + wire [1:0] _array_io_r_resp_data_4; + wire [1:0] _array_io_r_resp_data_5; + wire [1:0] _array_io_r_resp_data_6; + wire [1:0] _array_io_r_resp_data_7; + reg [1:0] ridx; + reg holdRidx_last_r; + reg [1:0] holdRidx_hold_data; + wire [1:0] holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data; + reg holdRidx_last_r_1; + reg [1:0] holdRidx_hold_data_1; + wire [1:0] holdRidx_1 = holdRidx_last_r_1 ? ridx : holdRidx_hold_data_1; + wire _wmask_T_3 = io_w_req_bits_setIdx[1:0] == 2'h0; + wire _wmask_T_9 = io_w_req_bits_setIdx[1:0] == 2'h1; + wire _wmask_T_15 = io_w_req_bits_setIdx[1:0] == 2'h2; + always @(posedge clock) begin + if (io_r_req_valid) + ridx <= io_r_req_bits_setIdx[1:0]; + if (holdRidx_last_r) + holdRidx_hold_data <= ridx; + if (holdRidx_last_r_1) + holdRidx_hold_data_1 <= ridx; + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) begin + holdRidx_last_r <= 1'h0; + holdRidx_last_r_1 <= 1'h0; + end + else begin + if (io_r_req_valid | holdRidx_last_r) + holdRidx_last_r <= io_r_req_valid; + if (io_r_req_valid | holdRidx_last_r_1) + holdRidx_last_r_1 <= io_r_req_valid; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + ridx = _RANDOM[/*Zero width*/ 1'b0][1:0]; + holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][2]; + holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][4:3]; + holdRidx_last_r_1 = _RANDOM[/*Zero width*/ 1'b0][5]; + holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][7:6]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + holdRidx_last_r = 1'h0; + holdRidx_last_r_1 = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_34 array ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_r_req_valid), + .io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:2]), + .io_r_resp_data_0 (_array_io_r_resp_data_0), + .io_r_resp_data_1 (_array_io_r_resp_data_1), + .io_r_resp_data_2 (_array_io_r_resp_data_2), + .io_r_resp_data_3 (_array_io_r_resp_data_3), + .io_r_resp_data_4 (_array_io_r_resp_data_4), + .io_r_resp_data_5 (_array_io_r_resp_data_5), + .io_r_resp_data_6 (_array_io_r_resp_data_6), + .io_r_resp_data_7 (_array_io_r_resp_data_7), + .io_w_req_valid (io_w_req_valid), + .io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:2]), + .io_w_req_bits_data_0 (io_w_req_bits_data_0), + .io_w_req_bits_data_1 (io_w_req_bits_data_1), + .io_w_req_bits_data_2 (io_w_req_bits_data_0), + .io_w_req_bits_data_3 (io_w_req_bits_data_1), + .io_w_req_bits_data_4 (io_w_req_bits_data_0), + .io_w_req_bits_data_5 (io_w_req_bits_data_1), + .io_w_req_bits_data_6 (io_w_req_bits_data_0), + .io_w_req_bits_data_7 (io_w_req_bits_data_1), + .io_w_req_bits_waymask + ({(&(io_w_req_bits_setIdx[1:0])) & io_w_req_bits_waymask[1], + (&(io_w_req_bits_setIdx[1:0])) & io_w_req_bits_waymask[0], + _wmask_T_15 & io_w_req_bits_waymask[1], + _wmask_T_15 & io_w_req_bits_waymask[0], + _wmask_T_9 & io_w_req_bits_waymask[1], + _wmask_T_9 & io_w_req_bits_waymask[0], + _wmask_T_3 & io_w_req_bits_waymask[1], + _wmask_T_3 & io_w_req_bits_waymask[0]}) + ); + assign io_r_resp_data_0 = + (holdRidx == 2'h0 ? _array_io_r_resp_data_0 : 2'h0) + | (holdRidx == 2'h1 ? _array_io_r_resp_data_2 : 2'h0) + | (holdRidx == 2'h2 ? _array_io_r_resp_data_4 : 2'h0) + | ((&holdRidx) ? _array_io_r_resp_data_6 : 2'h0); + assign io_r_resp_data_1 = + (holdRidx_1 == 2'h0 ? _array_io_r_resp_data_1 : 2'h0) + | (holdRidx_1 == 2'h1 ? _array_io_r_resp_data_3 : 2'h0) + | (holdRidx_1 == 2'h2 ? _array_io_r_resp_data_5 : 2'h0) + | ((&holdRidx_1) ? _array_io_r_resp_data_7 : 2'h0); +endmodule + diff --git a/rtl/BPUTop/FoldedSRAMTemplate_21.sv b/rtl/BPUTop/FoldedSRAMTemplate_21.sv new file mode 100644 index 0000000..24574e9 --- /dev/null +++ b/rtl/BPUTop/FoldedSRAMTemplate_21.sv @@ -0,0 +1,90 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FoldedSRAMTemplate_21( + input clock, + input reset, + input io_r_req_valid, + input [6:0] io_r_req_bits_setIdx, + output io_r_resp_data_0_valid, + output [8:0] io_r_resp_data_0_tag, + output [1:0] io_r_resp_data_0_ctr, + output [40:0] io_r_resp_data_0_target, + input io_w_req_valid, + input [6:0] io_w_req_bits_setIdx, + input [8:0] io_w_req_bits_data_0_tag, + input [1:0] io_w_req_bits_data_0_ctr, + input [40:0] io_w_req_bits_data_0_target +); + + SRAMTemplate_39 array ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_r_req_valid), + .io_r_req_bits_setIdx (io_r_req_bits_setIdx), + .io_r_resp_data_0_valid (io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (io_r_resp_data_0_target), + .io_w_req_valid (io_w_req_valid), + .io_w_req_bits_setIdx (io_w_req_bits_setIdx), + .io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag), + .io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr), + .io_w_req_bits_data_0_target (io_w_req_bits_data_0_target) + ); +endmodule + diff --git a/rtl/BPUTop/FoldedSRAMTemplate_25.sv b/rtl/BPUTop/FoldedSRAMTemplate_25.sv new file mode 100644 index 0000000..69b32f0 --- /dev/null +++ b/rtl/BPUTop/FoldedSRAMTemplate_25.sv @@ -0,0 +1,155 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module FoldedSRAMTemplate_25( + input clock, + input reset, + input io_r_req_valid, + input [7:0] io_r_req_bits_setIdx, + output io_r_resp_data_0_valid, + output [8:0] io_r_resp_data_0_tag, + output [1:0] io_r_resp_data_0_ctr, + output [40:0] io_r_resp_data_0_target, + input io_w_req_valid, + input [7:0] io_w_req_bits_setIdx, + input [8:0] io_w_req_bits_data_0_tag, + input [1:0] io_w_req_bits_data_0_ctr, + input [40:0] io_w_req_bits_data_0_target +); + + wire _array_io_r_resp_data_0_valid; + wire [8:0] _array_io_r_resp_data_0_tag; + wire [1:0] _array_io_r_resp_data_0_ctr; + wire [40:0] _array_io_r_resp_data_0_target; + wire _array_io_r_resp_data_1_valid; + wire [8:0] _array_io_r_resp_data_1_tag; + wire [1:0] _array_io_r_resp_data_1_ctr; + wire [40:0] _array_io_r_resp_data_1_target; + reg ridx; + reg holdRidx_last_r; + reg holdRidx_hold_data; + wire holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data; + always @(posedge clock) begin + if (io_r_req_valid) + ridx <= io_r_req_bits_setIdx[0]; + if (holdRidx_last_r) + holdRidx_hold_data <= ridx; + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) + holdRidx_last_r <= 1'h0; + else if (io_r_req_valid | holdRidx_last_r) + holdRidx_last_r <= io_r_req_valid; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + ridx = _RANDOM[/*Zero width*/ 1'b0][0]; + holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][1]; + holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][2]; + `endif // RANDOMIZE_REG_INIT + if (reset) + holdRidx_last_r = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_43 array ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_r_req_valid), + .io_r_req_bits_setIdx (io_r_req_bits_setIdx[7:1]), + .io_r_resp_data_0_valid (_array_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_array_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_array_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_array_io_r_resp_data_0_target), + .io_r_resp_data_1_valid (_array_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_array_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_array_io_r_resp_data_1_ctr), + .io_r_resp_data_1_target (_array_io_r_resp_data_1_target), + .io_w_req_valid (io_w_req_valid), + .io_w_req_bits_setIdx (io_w_req_bits_setIdx[7:1]), + .io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag), + .io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr), + .io_w_req_bits_data_0_target (io_w_req_bits_data_0_target), + .io_w_req_bits_data_1_tag (io_w_req_bits_data_0_tag), + .io_w_req_bits_data_1_ctr (io_w_req_bits_data_0_ctr), + .io_w_req_bits_data_1_target (io_w_req_bits_data_0_target), + .io_w_req_bits_waymask (2'h1 << io_w_req_bits_setIdx[0]) + ); + assign io_r_resp_data_0_valid = + ~holdRidx & _array_io_r_resp_data_0_valid | holdRidx & _array_io_r_resp_data_1_valid; + assign io_r_resp_data_0_tag = + (holdRidx ? 9'h0 : _array_io_r_resp_data_0_tag) + | (holdRidx ? _array_io_r_resp_data_1_tag : 9'h0); + assign io_r_resp_data_0_ctr = + (holdRidx ? 2'h0 : _array_io_r_resp_data_0_ctr) + | (holdRidx ? _array_io_r_resp_data_1_ctr : 2'h0); + assign io_r_resp_data_0_target = + (holdRidx ? 41'h0 : _array_io_r_resp_data_0_target) + | (holdRidx ? _array_io_r_resp_data_1_target : 41'h0); +endmodule + diff --git a/rtl/BPUTop/ITTage.sv b/rtl/BPUTop/ITTage.sv new file mode 100644 index 0000000..44b8fe7 --- /dev/null +++ b/rtl/BPUTop/ITTage.sv @@ -0,0 +1,1269 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module ITTage( + input clock, + input reset, + input [40:0] io_in_bits_s0_pc_3, + input [7:0] io_in_bits_folded_hist_3_hist_14_folded_hist, + input [8:0] io_in_bits_folded_hist_3_hist_13_folded_hist, + input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, + input [8:0] io_in_bits_folded_hist_3_hist_10_folded_hist, + input [8:0] io_in_bits_folded_hist_3_hist_6_folded_hist, + input [7:0] io_in_bits_folded_hist_3_hist_4_folded_hist, + input [7:0] io_in_bits_folded_hist_3_hist_3_folded_hist, + input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, + input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0, + input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_0, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_jalr_target, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_0, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr, + input io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing, + input io_in_bits_resp_in_0_s2_full_pred_0_hit, + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, + input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0, + input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_0, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_jalr_target, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_0, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr, + input io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing, + input io_in_bits_resp_in_0_s2_full_pred_1_hit, + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, + input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0, + input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_0, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_jalr_target, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_0, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr, + input io_in_bits_resp_in_0_s2_full_pred_2_is_jalr, + input io_in_bits_resp_in_0_s2_full_pred_2_is_call, + input io_in_bits_resp_in_0_s2_full_pred_2_is_ret, + input io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, + input io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing, + input io_in_bits_resp_in_0_s2_full_pred_2_hit, + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, + input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0, + input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_0, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_jalr_target, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_0, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr, + input io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr, + input io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing, + input io_in_bits_resp_in_0_s2_full_pred_3_hit, + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, + input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0, + input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_0, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_jalr_target, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr, + input io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr, + input io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing, + input io_in_bits_resp_in_0_s3_full_pred_0_hit, + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, + input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0, + input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_0, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_jalr_target, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr, + input io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr, + input io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing, + input io_in_bits_resp_in_0_s3_full_pred_1_hit, + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, + input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0, + input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_0, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_jalr_target, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr, + input io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr, + input io_in_bits_resp_in_0_s3_full_pred_2_is_jalr, + input io_in_bits_resp_in_0_s3_full_pred_2_is_call, + input io_in_bits_resp_in_0_s3_full_pred_2_is_ret, + input io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing, + input io_in_bits_resp_in_0_s3_full_pred_2_hit, + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, + input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0, + input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_0, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_jalr_target, + input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_0, + input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr, + input io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr, + input io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing, + input io_in_bits_resp_in_0_s3_full_pred_3_hit, + input io_in_bits_resp_in_0_last_stage_ftb_entry_valid, + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset, + input [11:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower, + input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat, + input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing, + input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid, + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset, + input [19:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower, + input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat, + input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing, + input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid, + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr, + input io_in_bits_resp_in_0_last_stage_ftb_entry_carry, + input io_in_bits_resp_in_0_last_stage_ftb_entry_isCall, + input io_in_bits_resp_in_0_last_stage_ftb_entry_isRet, + input io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr, + input io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call, + input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0, + input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1, + output io_out_s2_full_pred_0_br_taken_mask_0, + output io_out_s2_full_pred_0_br_taken_mask_1, + output io_out_s2_full_pred_0_slot_valids_0, + output io_out_s2_full_pred_0_slot_valids_1, + output [40:0] io_out_s2_full_pred_0_targets_0, + output [40:0] io_out_s2_full_pred_0_targets_1, + output [40:0] io_out_s2_full_pred_0_jalr_target, + output [3:0] io_out_s2_full_pred_0_offsets_0, + output [3:0] io_out_s2_full_pred_0_offsets_1, + output [40:0] io_out_s2_full_pred_0_fallThroughAddr, + output io_out_s2_full_pred_0_is_br_sharing, + output io_out_s2_full_pred_0_hit, + output io_out_s2_full_pred_1_br_taken_mask_0, + output io_out_s2_full_pred_1_br_taken_mask_1, + output io_out_s2_full_pred_1_slot_valids_0, + output io_out_s2_full_pred_1_slot_valids_1, + output [40:0] io_out_s2_full_pred_1_targets_0, + output [40:0] io_out_s2_full_pred_1_targets_1, + output [40:0] io_out_s2_full_pred_1_jalr_target, + output [3:0] io_out_s2_full_pred_1_offsets_0, + output [3:0] io_out_s2_full_pred_1_offsets_1, + output [40:0] io_out_s2_full_pred_1_fallThroughAddr, + output io_out_s2_full_pred_1_is_br_sharing, + output io_out_s2_full_pred_1_hit, + output io_out_s2_full_pred_2_br_taken_mask_0, + output io_out_s2_full_pred_2_br_taken_mask_1, + output io_out_s2_full_pred_2_slot_valids_0, + output io_out_s2_full_pred_2_slot_valids_1, + output [40:0] io_out_s2_full_pred_2_targets_0, + output [40:0] io_out_s2_full_pred_2_targets_1, + output [40:0] io_out_s2_full_pred_2_jalr_target, + output [3:0] io_out_s2_full_pred_2_offsets_0, + output [3:0] io_out_s2_full_pred_2_offsets_1, + output [40:0] io_out_s2_full_pred_2_fallThroughAddr, + output io_out_s2_full_pred_2_is_jalr, + output io_out_s2_full_pred_2_is_call, + output io_out_s2_full_pred_2_is_ret, + output io_out_s2_full_pred_2_last_may_be_rvi_call, + output io_out_s2_full_pred_2_is_br_sharing, + output io_out_s2_full_pred_2_hit, + output io_out_s2_full_pred_3_br_taken_mask_0, + output io_out_s2_full_pred_3_br_taken_mask_1, + output io_out_s2_full_pred_3_slot_valids_0, + output io_out_s2_full_pred_3_slot_valids_1, + output [40:0] io_out_s2_full_pred_3_targets_0, + output [40:0] io_out_s2_full_pred_3_targets_1, + output [40:0] io_out_s2_full_pred_3_jalr_target, + output [3:0] io_out_s2_full_pred_3_offsets_0, + output [3:0] io_out_s2_full_pred_3_offsets_1, + output [40:0] io_out_s2_full_pred_3_fallThroughAddr, + output io_out_s2_full_pred_3_fallThroughErr, + output io_out_s2_full_pred_3_is_br_sharing, + output io_out_s2_full_pred_3_hit, + output io_out_s3_full_pred_0_br_taken_mask_0, + output io_out_s3_full_pred_0_br_taken_mask_1, + output io_out_s3_full_pred_0_slot_valids_0, + output io_out_s3_full_pred_0_slot_valids_1, + output [40:0] io_out_s3_full_pred_0_targets_0, + output [40:0] io_out_s3_full_pred_0_targets_1, + output [40:0] io_out_s3_full_pred_0_jalr_target, + output [40:0] io_out_s3_full_pred_0_fallThroughAddr, + output io_out_s3_full_pred_0_fallThroughErr, + output io_out_s3_full_pred_0_is_br_sharing, + output io_out_s3_full_pred_0_hit, + output io_out_s3_full_pred_1_br_taken_mask_0, + output io_out_s3_full_pred_1_br_taken_mask_1, + output io_out_s3_full_pred_1_slot_valids_0, + output io_out_s3_full_pred_1_slot_valids_1, + output [40:0] io_out_s3_full_pred_1_targets_0, + output [40:0] io_out_s3_full_pred_1_targets_1, + output [40:0] io_out_s3_full_pred_1_jalr_target, + output [40:0] io_out_s3_full_pred_1_fallThroughAddr, + output io_out_s3_full_pred_1_fallThroughErr, + output io_out_s3_full_pred_1_is_br_sharing, + output io_out_s3_full_pred_1_hit, + output io_out_s3_full_pred_2_br_taken_mask_0, + output io_out_s3_full_pred_2_br_taken_mask_1, + output io_out_s3_full_pred_2_slot_valids_0, + output io_out_s3_full_pred_2_slot_valids_1, + output [40:0] io_out_s3_full_pred_2_targets_0, + output [40:0] io_out_s3_full_pred_2_targets_1, + output [40:0] io_out_s3_full_pred_2_jalr_target, + output [40:0] io_out_s3_full_pred_2_fallThroughAddr, + output io_out_s3_full_pred_2_fallThroughErr, + output io_out_s3_full_pred_2_is_jalr, + output io_out_s3_full_pred_2_is_call, + output io_out_s3_full_pred_2_is_ret, + output io_out_s3_full_pred_2_is_br_sharing, + output io_out_s3_full_pred_2_hit, + output io_out_s3_full_pred_3_br_taken_mask_0, + output io_out_s3_full_pred_3_br_taken_mask_1, + output io_out_s3_full_pred_3_slot_valids_0, + output io_out_s3_full_pred_3_slot_valids_1, + output [40:0] io_out_s3_full_pred_3_targets_0, + output [40:0] io_out_s3_full_pred_3_targets_1, + output [40:0] io_out_s3_full_pred_3_jalr_target, + output [3:0] io_out_s3_full_pred_3_offsets_0, + output [3:0] io_out_s3_full_pred_3_offsets_1, + output [40:0] io_out_s3_full_pred_3_fallThroughAddr, + output io_out_s3_full_pred_3_fallThroughErr, + output io_out_s3_full_pred_3_is_br_sharing, + output io_out_s3_full_pred_3_hit, + output [222:0] io_out_last_stage_meta, + output io_out_last_stage_ftb_entry_valid, + output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, + output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, + output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, + output io_out_last_stage_ftb_entry_brSlots_0_sharing, + output io_out_last_stage_ftb_entry_brSlots_0_valid, + output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, + output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, + output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, + output io_out_last_stage_ftb_entry_tailSlot_sharing, + output io_out_last_stage_ftb_entry_tailSlot_valid, + output [3:0] io_out_last_stage_ftb_entry_pftAddr, + output io_out_last_stage_ftb_entry_carry, + output io_out_last_stage_ftb_entry_isCall, + output io_out_last_stage_ftb_entry_isRet, + output io_out_last_stage_ftb_entry_isJalr, + output io_out_last_stage_ftb_entry_last_may_be_rvi_call, + output io_out_last_stage_ftb_entry_always_taken_0, + output io_out_last_stage_ftb_entry_always_taken_1, + input io_s0_fire_3, + input io_s1_fire_3, + input io_s2_fire_0, + input io_s2_fire_1, + input io_s2_fire_2, + input io_s2_fire_3, + input io_update_valid, + input [40:0] io_update_bits_pc, + input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, + input [8:0] io_update_bits_spec_info_folded_hist_hist_13_folded_hist, + input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, + input [8:0] io_update_bits_spec_info_folded_hist_hist_10_folded_hist, + input [8:0] io_update_bits_spec_info_folded_hist_hist_6_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, + input io_update_bits_ftb_entry_tailSlot_sharing, + input io_update_bits_ftb_entry_tailSlot_valid, + input io_update_bits_ftb_entry_isRet, + input io_update_bits_ftb_entry_isJalr, + input io_update_bits_cfi_idx_valid, + input [3:0] io_update_bits_cfi_idx_bits, + input io_update_bits_jmp_taken, + input io_update_bits_mispred_mask_2, + input [222:0] io_update_bits_meta, + input [40:0] io_update_bits_full_target +); + + reg [2:0] resp_meta_allocate_bits_r; + reg resp_meta_allocate_valid_r; + wire resp_meta_altDiffers; + wire _tables_4_io_resp_valid; + wire [1:0] _tables_4_io_resp_bits_ctr; + wire [1:0] _tables_4_io_resp_bits_u; + wire [40:0] _tables_4_io_resp_bits_target; + wire _tables_3_io_resp_valid; + wire [1:0] _tables_3_io_resp_bits_ctr; + wire [1:0] _tables_3_io_resp_bits_u; + wire [40:0] _tables_3_io_resp_bits_target; + wire _tables_2_io_resp_valid; + wire [1:0] _tables_2_io_resp_bits_ctr; + wire [1:0] _tables_2_io_resp_bits_u; + wire [40:0] _tables_2_io_resp_bits_target; + wire _tables_1_io_resp_valid; + wire [1:0] _tables_1_io_resp_bits_ctr; + wire [1:0] _tables_1_io_resp_bits_u; + wire [40:0] _tables_1_io_resp_bits_target; + wire _tables_0_io_resp_valid; + wire [1:0] _tables_0_io_resp_bits_ctr; + wire [1:0] _tables_0_io_resp_bits_u; + wire [40:0] _tables_0_io_resp_bits_target; + reg [7:0] tickCtr; + reg s2_resps_0_valid; + reg [1:0] s2_resps_0_bits_ctr; + reg [1:0] s2_resps_0_bits_u; + reg [40:0] s2_resps_0_bits_target; + reg s2_resps_1_valid; + reg [1:0] s2_resps_1_bits_ctr; + reg [1:0] s2_resps_1_bits_u; + reg [40:0] s2_resps_1_bits_target; + reg s2_resps_2_valid; + reg [1:0] s2_resps_2_bits_ctr; + reg [1:0] s2_resps_2_bits_u; + reg [40:0] s2_resps_2_bits_target; + reg s2_resps_3_valid; + reg [1:0] s2_resps_3_bits_ctr; + reg [1:0] s2_resps_3_bits_u; + reg [40:0] s2_resps_3_bits_target; + reg s2_resps_4_valid; + reg [1:0] s2_resps_4_bits_ctr; + reg [1:0] s2_resps_4_bits_u; + reg [40:0] s2_resps_4_bits_target; + reg s3_tageTaken_dup_0; + reg s3_tageTaken_dup_1; + reg s3_tageTaken_dup_2; + reg s3_tageTaken_dup_3; + reg [40:0] s3_tageTarget_dup_0; + reg [40:0] s3_tageTarget_dup_1; + reg [40:0] s3_tageTarget_dup_2; + reg [40:0] s3_tageTarget_dup_3; + reg [40:0] s3_providerTarget; + reg [40:0] s3_altProviderTarget; + reg s3_provided; + reg [2:0] s3_provider; + reg s3_altProvided; + reg [2:0] s3_altProvider; + reg s3_finalAltPred; + reg s3_providerU; + reg [1:0] s3_providerCtr; + reg [1:0] s3_altProviderCtr; + wire updateValid = + io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_isJalr + & ~(io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_isRet) + & io_update_valid & ~io_update_bits_ftb_entry_tailSlot_sharing + & io_update_bits_jmp_taken & io_update_bits_cfi_idx_valid + & io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset; + assign resp_meta_altDiffers = s3_finalAltPred != s3_tageTaken_dup_3; + reg [63:0] s2_allocLFSR_lfsr; + wire _GEN = + updateValid & io_update_bits_mispred_mask_2 + & ~(io_update_bits_meta[100] + & io_update_bits_meta[81:41] == io_update_bits_full_target + & io_update_bits_meta[90:89] == 2'h0); + reg tables_0_io_update_valid_REG; + reg tables_0_io_update_reset_u_REG; + reg tables_0_io_update_correct_r; + reg [40:0] tables_0_io_update_target_r; + reg [40:0] tables_0_io_update_old_target_r; + reg tables_0_io_update_alloc_r; + reg [1:0] tables_0_io_update_oldCtr_r; + reg tables_0_io_update_uValid_r; + reg tables_0_io_update_u_r; + reg [40:0] tables_0_io_update_pc_r; + reg [3:0] tables_0_io_update_folded_hist_r_hist_12_folded_hist; + reg tables_1_io_update_valid_REG; + reg tables_1_io_update_reset_u_REG; + reg tables_1_io_update_correct_r; + reg [40:0] tables_1_io_update_target_r; + reg [40:0] tables_1_io_update_old_target_r; + reg tables_1_io_update_alloc_r; + reg [1:0] tables_1_io_update_oldCtr_r; + reg tables_1_io_update_uValid_r; + reg tables_1_io_update_u_r; + reg [40:0] tables_1_io_update_pc_r; + reg [7:0] tables_1_io_update_folded_hist_r_hist_14_folded_hist; + reg tables_2_io_update_valid_REG; + reg tables_2_io_update_reset_u_REG; + reg tables_2_io_update_correct_r; + reg [40:0] tables_2_io_update_target_r; + reg [40:0] tables_2_io_update_old_target_r; + reg tables_2_io_update_alloc_r; + reg [1:0] tables_2_io_update_oldCtr_r; + reg tables_2_io_update_uValid_r; + reg tables_2_io_update_u_r; + reg [40:0] tables_2_io_update_pc_r; + reg [8:0] tables_2_io_update_folded_hist_r_hist_13_folded_hist; + reg [7:0] tables_2_io_update_folded_hist_r_hist_4_folded_hist; + reg tables_3_io_update_valid_REG; + reg tables_3_io_update_reset_u_REG; + reg tables_3_io_update_correct_r; + reg [40:0] tables_3_io_update_target_r; + reg [40:0] tables_3_io_update_old_target_r; + reg tables_3_io_update_alloc_r; + reg [1:0] tables_3_io_update_oldCtr_r; + reg tables_3_io_update_uValid_r; + reg tables_3_io_update_u_r; + reg [40:0] tables_3_io_update_pc_r; + reg [8:0] tables_3_io_update_folded_hist_r_hist_6_folded_hist; + reg [7:0] tables_3_io_update_folded_hist_r_hist_2_folded_hist; + reg tables_4_io_update_valid_REG; + reg tables_4_io_update_reset_u_REG; + reg tables_4_io_update_correct_r; + reg [40:0] tables_4_io_update_target_r; + reg [40:0] tables_4_io_update_old_target_r; + reg tables_4_io_update_alloc_r; + reg [1:0] tables_4_io_update_oldCtr_r; + reg tables_4_io_update_uValid_r; + reg tables_4_io_update_u_r; + reg [40:0] tables_4_io_update_pc_r; + reg [8:0] tables_4_io_update_folded_hist_r_hist_10_folded_hist; + reg [7:0] tables_4_io_update_folded_hist_r_hist_3_folded_hist; + always @(posedge clock or posedge reset) begin + if (reset) begin + tickCtr <= 8'h0; + s2_allocLFSR_lfsr <= 64'h1234567887654321; + end + else begin + if (&tickCtr) + tickCtr <= 8'h0; + else if (_GEN) begin + if ((&tickCtr) & ~(io_update_bits_meta[86])) + tickCtr <= 8'hFF; + else if (tickCtr == 8'h0 & io_update_bits_meta[86]) + tickCtr <= 8'h0; + else if (io_update_bits_meta[86]) + tickCtr <= 8'(tickCtr - 8'h1); + else + tickCtr <= 8'(tickCtr + 8'h1); + end + if (s2_allocLFSR_lfsr == 64'h0) + s2_allocLFSR_lfsr <= 64'h1; + else + s2_allocLFSR_lfsr <= + {s2_allocLFSR_lfsr[0] ^ s2_allocLFSR_lfsr[1] ^ s2_allocLFSR_lfsr[3] + ^ s2_allocLFSR_lfsr[4], + s2_allocLFSR_lfsr[63:1]}; + end + end // always @(posedge, posedge) + wire [2:0] selectedInfo_res_1_first_tableIdx = {2'h0, s2_resps_1_valid}; + wire [2:0] selectedInfo_res_2_first_tableIdx = + s2_resps_2_valid ? 3'h2 : selectedInfo_res_1_first_tableIdx; + wire selectedInfo_res_hasOne = s2_resps_4_valid | s2_resps_3_valid; + wire selectedInfo_res_hasTwo = s2_resps_4_valid & s2_resps_3_valid; + wire selectedInfo_res_1_hasOne = s2_resps_1_valid | s2_resps_0_valid; + wire [1:0] selectedInfo_res_1_first_ctr = + s2_resps_1_valid ? s2_resps_1_bits_ctr : s2_resps_0_bits_ctr; + wire [40:0] selectedInfo_res_1_first_target = + s2_resps_1_valid ? s2_resps_1_bits_target : s2_resps_0_bits_target; + wire selectedInfo_res_2_hasOne = s2_resps_2_valid | selectedInfo_res_1_hasOne; + wire [1:0] selectedInfo_res_2_first_ctr = + s2_resps_2_valid ? s2_resps_2_bits_ctr : selectedInfo_res_1_first_ctr; + wire [40:0] selectedInfo_res_2_first_target = + s2_resps_2_valid ? s2_resps_2_bits_target : selectedInfo_res_1_first_target; + wire selectedInfo_hasOne = selectedInfo_res_hasOne | selectedInfo_res_2_hasOne; + wire selectedInfo_hasTwo = + selectedInfo_res_hasTwo | s2_resps_1_valid & s2_resps_0_valid | s2_resps_2_valid + & selectedInfo_res_1_hasOne | selectedInfo_res_hasOne & selectedInfo_res_2_hasOne; + wire [1:0] selectedInfo_first_ctr = + selectedInfo_res_hasOne + ? (s2_resps_4_valid ? s2_resps_4_bits_ctr : s2_resps_3_bits_ctr) + : selectedInfo_res_2_first_ctr; + wire [40:0] selectedInfo_first_target = + selectedInfo_res_hasOne + ? (s2_resps_4_valid ? s2_resps_4_bits_target : s2_resps_3_bits_target) + : selectedInfo_res_2_first_target; + wire _selectedInfo_T_91 = selectedInfo_res_hasOne & ~selectedInfo_res_hasTwo; + wire [40:0] selectedInfo_second_target = + (selectedInfo_res_hasOne + ? 41'h0 + : (s2_resps_2_valid + ? 41'h0 + : (s2_resps_1_valid ? 41'h0 : s2_resps_0_bits_target) + | (s2_resps_1_valid ? s2_resps_0_bits_target : 41'h0)) + | (s2_resps_2_valid ? selectedInfo_res_1_first_target : 41'h0)) + | (_selectedInfo_T_91 ? selectedInfo_res_2_first_target : 41'h0) + | (selectedInfo_res_hasTwo + ? (s2_resps_4_valid ? 41'h0 : s2_resps_3_bits_target) + | (s2_resps_4_valid ? s2_resps_3_bits_target : 41'h0) + : 41'h0); + wire providerNull = selectedInfo_first_ctr == 2'h0; + wire _s2_tageTarget_T = providerNull & selectedInfo_hasTwo; + wire _s2_tageTarget_T_3 = selectedInfo_hasTwo & providerNull; + wire _s2_tageTaken_T_9 = + selectedInfo_hasOne & ~_s2_tageTarget_T | _s2_tageTarget_T_3 | ~selectedInfo_hasOne; + wire [40:0] _s2_tageTarget_T_12 = + (selectedInfo_hasOne & ~_s2_tageTarget_T ? selectedInfo_first_target : 41'h0) + | (_s2_tageTarget_T_3 ? selectedInfo_second_target : 41'h0) + | (~selectedInfo_hasOne | providerNull & ~selectedInfo_hasTwo + ? io_in_bits_resp_in_0_s2_full_pred_3_jalr_target + : 41'h0); + wire _GEN_0 = + io_update_bits_meta[96] & io_update_bits_meta[90:89] == 2'h0 + & io_update_bits_mispred_mask_2; + wire _GEN_1 = io_update_bits_meta[99:97] == 3'h0; + wire _GEN_2 = updateValid & io_update_bits_meta[100]; + wire _GEN_3 = io_update_bits_meta[99:97] == 3'h1; + wire _GEN_4 = io_update_bits_meta[99:97] == 3'h2; + wire _GEN_5 = io_update_bits_meta[99:97] == 3'h3; + wire _GEN_6 = io_update_bits_meta[99:97] == 3'h4; + wire _updateU_T_2 = + io_update_bits_meta[92] ? ~io_update_bits_mispred_mask_2 : io_update_bits_meta[91]; + wire _updateCorrect_T = io_update_bits_meta[81:41] == io_update_bits_full_target; + wire _GEN_7 = io_update_bits_meta[85:83] == 3'h0; + wire _GEN_8 = _GEN & io_update_bits_meta[86] & _GEN_7; + wire updateMask_0 = + _GEN_8 | _GEN_2 & (_GEN_1 | _GEN_0 & io_update_bits_meta[95:93] == 3'h0); + wire _GEN_9 = io_update_bits_meta[85:83] == 3'h1; + wire _GEN_10 = _GEN & io_update_bits_meta[86] & _GEN_9; + wire updateMask_1 = + _GEN_10 | _GEN_2 & (_GEN_3 | _GEN_0 & io_update_bits_meta[95:93] == 3'h1); + wire _GEN_11 = io_update_bits_meta[85:83] == 3'h2; + wire _GEN_12 = _GEN & io_update_bits_meta[86] & _GEN_11; + wire updateMask_2 = + _GEN_12 | _GEN_2 & (_GEN_4 | _GEN_0 & io_update_bits_meta[95:93] == 3'h2); + wire _GEN_13 = io_update_bits_meta[85:83] == 3'h3; + wire _GEN_14 = _GEN & io_update_bits_meta[86] & _GEN_13; + wire updateMask_3 = + _GEN_14 | _GEN_2 & (_GEN_5 | _GEN_0 & io_update_bits_meta[95:93] == 3'h3); + wire _GEN_15 = io_update_bits_meta[85:83] == 3'h4; + wire _GEN_16 = _GEN & io_update_bits_meta[86] & _GEN_15; + wire updateMask_4 = + _GEN_16 | _GEN_2 & (_GEN_6 | _GEN_0 & io_update_bits_meta[95:93] == 3'h4); + wire _GEN_17 = _GEN & io_update_bits_meta[86]; + wire [2:0] selectedInfo_first_tableIdx = + selectedInfo_res_hasOne + ? (s2_resps_4_valid ? 3'h4 : 3'h3) + : selectedInfo_res_2_first_tableIdx; + wire [1:0] selectedInfo_second_ctr = + (selectedInfo_res_hasOne + ? 2'h0 + : (s2_resps_2_valid + ? 2'h0 + : (s2_resps_1_valid ? 2'h0 : s2_resps_0_bits_ctr) + | (s2_resps_1_valid ? s2_resps_0_bits_ctr : 2'h0)) + | (s2_resps_2_valid ? selectedInfo_res_1_first_ctr : 2'h0)) + | (_selectedInfo_T_91 ? selectedInfo_res_2_first_ctr : 2'h0) + | (selectedInfo_res_hasTwo + ? (s2_resps_4_valid ? 2'h0 : s2_resps_3_bits_ctr) + | (s2_resps_4_valid ? s2_resps_3_bits_ctr : 2'h0) + : 2'h0); + wire [7:0] _s2_allocatableSlots_T_17 = 8'h1 << selectedInfo_first_tableIdx; + wire [4:0] _GEN_18 = _s2_allocatableSlots_T_17[4:0] | _s2_allocatableSlots_T_17[5:1]; + wire [4:0] _GEN_19 = + ~({_GEN_18[4] | selectedInfo_first_tableIdx == 3'h6 | (&selectedInfo_first_tableIdx), + _GEN_18[3:0] | _s2_allocatableSlots_T_17[5:2] | _s2_allocatableSlots_T_17[6:3] + | _s2_allocatableSlots_T_17[7:4]} & {5{selectedInfo_hasOne}}) + & {~s2_resps_4_valid & s2_resps_4_bits_u == 2'h0, + ~s2_resps_3_valid & s2_resps_3_bits_u == 2'h0, + ~s2_resps_2_valid & s2_resps_2_bits_u == 2'h0, + ~s2_resps_1_valid & s2_resps_1_bits_u == 2'h0, + ~s2_resps_0_valid & s2_resps_0_bits_u == 2'h0}; + wire [4:0] _GEN_20 = _GEN_19 & s2_allocLFSR_lfsr[4:0]; + wire [2:0] s2_maskedEntry = + _GEN_20[0] + ? 3'h0 + : _GEN_20[1] + ? 3'h1 + : _GEN_20[2] ? 3'h2 : _GEN_20[3] ? 3'h3 : _GEN_20[4] ? 3'h4 : 3'h7; + wire [7:0] _s2_allocEntry_T = {3'h0, _GEN_19} >> s2_maskedEntry; + always @(posedge clock) begin + if (io_s1_fire_3) begin + s2_resps_0_valid <= _tables_0_io_resp_valid; + s2_resps_0_bits_ctr <= _tables_0_io_resp_bits_ctr; + s2_resps_0_bits_u <= _tables_0_io_resp_bits_u; + s2_resps_0_bits_target <= _tables_0_io_resp_bits_target; + s2_resps_1_valid <= _tables_1_io_resp_valid; + s2_resps_1_bits_ctr <= _tables_1_io_resp_bits_ctr; + s2_resps_1_bits_u <= _tables_1_io_resp_bits_u; + s2_resps_1_bits_target <= _tables_1_io_resp_bits_target; + s2_resps_2_valid <= _tables_2_io_resp_valid; + s2_resps_2_bits_ctr <= _tables_2_io_resp_bits_ctr; + s2_resps_2_bits_u <= _tables_2_io_resp_bits_u; + s2_resps_2_bits_target <= _tables_2_io_resp_bits_target; + s2_resps_3_valid <= _tables_3_io_resp_valid; + s2_resps_3_bits_ctr <= _tables_3_io_resp_bits_ctr; + s2_resps_3_bits_u <= _tables_3_io_resp_bits_u; + s2_resps_3_bits_target <= _tables_3_io_resp_bits_target; + s2_resps_4_valid <= _tables_4_io_resp_valid; + s2_resps_4_bits_ctr <= _tables_4_io_resp_bits_ctr; + s2_resps_4_bits_u <= _tables_4_io_resp_bits_u; + s2_resps_4_bits_target <= _tables_4_io_resp_bits_target; + end + if (io_s2_fire_0) begin + s3_tageTaken_dup_0 <= _s2_tageTaken_T_9; + s3_tageTarget_dup_0 <= _s2_tageTarget_T_12; + end + if (io_s2_fire_1) begin + s3_tageTaken_dup_1 <= _s2_tageTaken_T_9; + s3_tageTarget_dup_1 <= _s2_tageTarget_T_12; + end + if (io_s2_fire_2) begin + s3_tageTaken_dup_2 <= _s2_tageTaken_T_9; + s3_tageTarget_dup_2 <= _s2_tageTarget_T_12; + end + if (io_s2_fire_3) begin + s3_tageTaken_dup_3 <= _s2_tageTaken_T_9; + s3_tageTarget_dup_3 <= _s2_tageTarget_T_12; + s3_providerTarget <= selectedInfo_first_target; + s3_altProviderTarget <= selectedInfo_second_target; + s3_provided <= selectedInfo_hasOne; + s3_provider <= selectedInfo_first_tableIdx; + s3_altProvided <= selectedInfo_hasTwo; + s3_altProvider <= + (selectedInfo_res_hasOne | ~s2_resps_2_valid + ? 3'h0 + : selectedInfo_res_1_first_tableIdx) + | (_selectedInfo_T_91 ? selectedInfo_res_2_first_tableIdx : 3'h0) + | (selectedInfo_res_hasTwo + ? (s2_resps_4_valid ? 3'h0 : 3'h3) | (s2_resps_4_valid ? 3'h3 : 3'h0) + : 3'h0); + s3_finalAltPred <= ~selectedInfo_hasTwo | selectedInfo_second_ctr[1]; + s3_providerU <= + selectedInfo_res_hasOne + ? (s2_resps_4_valid ? s2_resps_4_bits_u[0] : s2_resps_3_bits_u[0]) + : s2_resps_2_valid + ? s2_resps_2_bits_u[0] + : s2_resps_1_valid ? s2_resps_1_bits_u[0] : s2_resps_0_bits_u[0]; + s3_providerCtr <= selectedInfo_first_ctr; + s3_altProviderCtr <= selectedInfo_second_ctr; + resp_meta_allocate_valid_r <= |_GEN_19; + resp_meta_allocate_bits_r <= + _s2_allocEntry_T[0] + ? s2_maskedEntry + : _GEN_19[0] + ? 3'h0 + : _GEN_19[1] + ? 3'h1 + : _GEN_19[2] ? 3'h2 : _GEN_19[3] ? 3'h3 : _GEN_19[4] ? 3'h4 : 3'h7; + end + tables_0_io_update_valid_REG <= updateMask_0; + tables_0_io_update_reset_u_REG <= &tickCtr; + if (updateMask_0) begin + tables_0_io_update_correct_r <= _GEN_8 | _GEN_1 & _updateCorrect_T; + tables_0_io_update_target_r <= io_update_bits_full_target; + tables_0_io_update_old_target_r <= + _GEN_1 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; + tables_0_io_update_alloc_r <= _GEN_17 & _GEN_7; + tables_0_io_update_oldCtr_r <= + _GEN_1 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; + tables_0_io_update_uValid_r <= _GEN_8 | _GEN_2 & _GEN_1; + tables_0_io_update_u_r <= ~_GEN_8 & _updateU_T_2; + tables_0_io_update_pc_r <= io_update_bits_pc; + tables_0_io_update_folded_hist_r_hist_12_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_12_folded_hist; + end + tables_1_io_update_valid_REG <= updateMask_1; + tables_1_io_update_reset_u_REG <= &tickCtr; + if (updateMask_1) begin + tables_1_io_update_correct_r <= _GEN_10 | _GEN_3 & _updateCorrect_T; + tables_1_io_update_target_r <= io_update_bits_full_target; + tables_1_io_update_old_target_r <= + _GEN_3 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; + tables_1_io_update_alloc_r <= _GEN_17 & _GEN_9; + tables_1_io_update_oldCtr_r <= + _GEN_3 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; + tables_1_io_update_uValid_r <= _GEN_10 | _GEN_2 & _GEN_3; + tables_1_io_update_u_r <= ~_GEN_10 & _updateU_T_2; + tables_1_io_update_pc_r <= io_update_bits_pc; + tables_1_io_update_folded_hist_r_hist_14_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_14_folded_hist; + end + tables_2_io_update_valid_REG <= updateMask_2; + tables_2_io_update_reset_u_REG <= &tickCtr; + if (updateMask_2) begin + tables_2_io_update_correct_r <= _GEN_12 | _GEN_4 & _updateCorrect_T; + tables_2_io_update_target_r <= io_update_bits_full_target; + tables_2_io_update_old_target_r <= + _GEN_4 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; + tables_2_io_update_alloc_r <= _GEN_17 & _GEN_11; + tables_2_io_update_oldCtr_r <= + _GEN_4 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; + tables_2_io_update_uValid_r <= _GEN_12 | _GEN_2 & _GEN_4; + tables_2_io_update_u_r <= ~_GEN_12 & _updateU_T_2; + tables_2_io_update_pc_r <= io_update_bits_pc; + tables_2_io_update_folded_hist_r_hist_13_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_13_folded_hist; + tables_2_io_update_folded_hist_r_hist_4_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_4_folded_hist; + end + tables_3_io_update_valid_REG <= updateMask_3; + tables_3_io_update_reset_u_REG <= &tickCtr; + if (updateMask_3) begin + tables_3_io_update_correct_r <= _GEN_14 | _GEN_5 & _updateCorrect_T; + tables_3_io_update_target_r <= io_update_bits_full_target; + tables_3_io_update_old_target_r <= + _GEN_5 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; + tables_3_io_update_alloc_r <= _GEN_17 & _GEN_13; + tables_3_io_update_oldCtr_r <= + _GEN_5 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; + tables_3_io_update_uValid_r <= _GEN_14 | _GEN_2 & _GEN_5; + tables_3_io_update_u_r <= ~_GEN_14 & _updateU_T_2; + tables_3_io_update_pc_r <= io_update_bits_pc; + tables_3_io_update_folded_hist_r_hist_6_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_6_folded_hist; + tables_3_io_update_folded_hist_r_hist_2_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_2_folded_hist; + end + tables_4_io_update_valid_REG <= updateMask_4; + tables_4_io_update_reset_u_REG <= &tickCtr; + if (updateMask_4) begin + tables_4_io_update_correct_r <= _GEN_16 | _GEN_6 & _updateCorrect_T; + tables_4_io_update_target_r <= io_update_bits_full_target; + tables_4_io_update_old_target_r <= + _GEN_6 ? io_update_bits_meta[81:41] : io_update_bits_meta[40:0]; + tables_4_io_update_alloc_r <= _GEN_17 & _GEN_15; + tables_4_io_update_oldCtr_r <= + _GEN_6 ? io_update_bits_meta[90:89] : io_update_bits_meta[88:87]; + tables_4_io_update_uValid_r <= _GEN_16 | _GEN_2 & _GEN_6; + tables_4_io_update_u_r <= ~_GEN_16 & _updateU_T_2; + tables_4_io_update_pc_r <= io_update_bits_pc; + tables_4_io_update_folded_hist_r_hist_10_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_10_folded_hist; + tables_4_io_update_folded_hist_r_hist_3_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_3_folded_hist; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:79]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [6:0] i = 7'h0; i < 7'h50; i += 7'h1) begin + _RANDOM[i] = `RANDOM; + end + tickCtr = _RANDOM[7'hF][25:18]; + s2_resps_0_valid = _RANDOM[7'hF][26]; + s2_resps_0_bits_ctr = _RANDOM[7'hF][28:27]; + s2_resps_0_bits_u = _RANDOM[7'hF][30:29]; + s2_resps_0_bits_target = {_RANDOM[7'hF][31], _RANDOM[7'h10], _RANDOM[7'h11][7:0]}; + s2_resps_1_valid = _RANDOM[7'h11][8]; + s2_resps_1_bits_ctr = _RANDOM[7'h11][10:9]; + s2_resps_1_bits_u = _RANDOM[7'h11][12:11]; + s2_resps_1_bits_target = {_RANDOM[7'h11][31:13], _RANDOM[7'h12][21:0]}; + s2_resps_2_valid = _RANDOM[7'h12][22]; + s2_resps_2_bits_ctr = _RANDOM[7'h12][24:23]; + s2_resps_2_bits_u = _RANDOM[7'h12][26:25]; + s2_resps_2_bits_target = + {_RANDOM[7'h12][31:27], _RANDOM[7'h13], _RANDOM[7'h14][3:0]}; + s2_resps_3_valid = _RANDOM[7'h14][4]; + s2_resps_3_bits_ctr = _RANDOM[7'h14][6:5]; + s2_resps_3_bits_u = _RANDOM[7'h14][8:7]; + s2_resps_3_bits_target = {_RANDOM[7'h14][31:9], _RANDOM[7'h15][17:0]}; + s2_resps_4_valid = _RANDOM[7'h15][18]; + s2_resps_4_bits_ctr = _RANDOM[7'h15][20:19]; + s2_resps_4_bits_u = _RANDOM[7'h15][22:21]; + s2_resps_4_bits_target = {_RANDOM[7'h15][31:23], _RANDOM[7'h16]}; + s3_tageTaken_dup_0 = _RANDOM[7'h1A][27]; + s3_tageTaken_dup_1 = _RANDOM[7'h1A][28]; + s3_tageTaken_dup_2 = _RANDOM[7'h1A][29]; + s3_tageTaken_dup_3 = _RANDOM[7'h1A][30]; + s3_tageTarget_dup_0 = {_RANDOM[7'h1A][31], _RANDOM[7'h1B], _RANDOM[7'h1C][7:0]}; + s3_tageTarget_dup_1 = {_RANDOM[7'h1C][31:8], _RANDOM[7'h1D][16:0]}; + s3_tageTarget_dup_2 = {_RANDOM[7'h1D][31:17], _RANDOM[7'h1E][25:0]}; + s3_tageTarget_dup_3 = + {_RANDOM[7'h1E][31:26], _RANDOM[7'h1F], _RANDOM[7'h20][2:0]}; + s3_providerTarget = {_RANDOM[7'h20][31:3], _RANDOM[7'h21][11:0]}; + s3_altProviderTarget = {_RANDOM[7'h21][31:12], _RANDOM[7'h22][20:0]}; + s3_provided = _RANDOM[7'h22][21]; + s3_provider = _RANDOM[7'h22][24:22]; + s3_altProvided = _RANDOM[7'h22][25]; + s3_altProvider = _RANDOM[7'h22][28:26]; + s3_finalAltPred = _RANDOM[7'h22][29]; + s3_providerU = _RANDOM[7'h22][30]; + s3_providerCtr = {_RANDOM[7'h22][31], _RANDOM[7'h23][0]}; + s3_altProviderCtr = _RANDOM[7'h23][2:1]; + s2_allocLFSR_lfsr = {_RANDOM[7'h23][31:3], _RANDOM[7'h24], _RANDOM[7'h25][2:0]}; + resp_meta_allocate_valid_r = _RANDOM[7'h25][3]; + resp_meta_allocate_bits_r = _RANDOM[7'h25][6:4]; + tables_0_io_update_valid_REG = _RANDOM[7'h25][7]; + tables_0_io_update_reset_u_REG = _RANDOM[7'h25][8]; + tables_0_io_update_correct_r = _RANDOM[7'h25][9]; + tables_0_io_update_target_r = {_RANDOM[7'h25][31:10], _RANDOM[7'h26][18:0]}; + tables_0_io_update_old_target_r = {_RANDOM[7'h26][31:19], _RANDOM[7'h27][27:0]}; + tables_0_io_update_alloc_r = _RANDOM[7'h27][28]; + tables_0_io_update_oldCtr_r = _RANDOM[7'h27][30:29]; + tables_0_io_update_uValid_r = _RANDOM[7'h27][31]; + tables_0_io_update_u_r = _RANDOM[7'h28][0]; + tables_0_io_update_pc_r = {_RANDOM[7'h28][31:1], _RANDOM[7'h29][9:0]}; + tables_0_io_update_folded_hist_r_hist_12_folded_hist = _RANDOM[7'h2A][27:24]; + tables_1_io_update_valid_REG = _RANDOM[7'h2D][30]; + tables_1_io_update_reset_u_REG = _RANDOM[7'h2D][31]; + tables_1_io_update_correct_r = _RANDOM[7'h2E][0]; + tables_1_io_update_target_r = {_RANDOM[7'h2E][31:1], _RANDOM[7'h2F][9:0]}; + tables_1_io_update_old_target_r = {_RANDOM[7'h2F][31:10], _RANDOM[7'h30][18:0]}; + tables_1_io_update_alloc_r = _RANDOM[7'h30][19]; + tables_1_io_update_oldCtr_r = _RANDOM[7'h30][21:20]; + tables_1_io_update_uValid_r = _RANDOM[7'h30][22]; + tables_1_io_update_u_r = _RANDOM[7'h30][23]; + tables_1_io_update_pc_r = + {_RANDOM[7'h30][31:24], _RANDOM[7'h31], _RANDOM[7'h32][0]}; + tables_1_io_update_folded_hist_r_hist_14_folded_hist = + {_RANDOM[7'h32][31:30], _RANDOM[7'h33][5:0]}; + tables_2_io_update_valid_REG = _RANDOM[7'h36][21]; + tables_2_io_update_reset_u_REG = _RANDOM[7'h36][22]; + tables_2_io_update_correct_r = _RANDOM[7'h36][23]; + tables_2_io_update_target_r = + {_RANDOM[7'h36][31:24], _RANDOM[7'h37], _RANDOM[7'h38][0]}; + tables_2_io_update_old_target_r = {_RANDOM[7'h38][31:1], _RANDOM[7'h39][9:0]}; + tables_2_io_update_alloc_r = _RANDOM[7'h39][10]; + tables_2_io_update_oldCtr_r = _RANDOM[7'h39][12:11]; + tables_2_io_update_uValid_r = _RANDOM[7'h39][13]; + tables_2_io_update_u_r = _RANDOM[7'h39][14]; + tables_2_io_update_pc_r = {_RANDOM[7'h39][31:15], _RANDOM[7'h3A][23:0]}; + tables_2_io_update_folded_hist_r_hist_13_folded_hist = + {_RANDOM[7'h3B][31:29], _RANDOM[7'h3C][5:0]}; + tables_2_io_update_folded_hist_r_hist_4_folded_hist = _RANDOM[7'h3E][8:1]; + tables_3_io_update_valid_REG = _RANDOM[7'h3F][12]; + tables_3_io_update_reset_u_REG = _RANDOM[7'h3F][13]; + tables_3_io_update_correct_r = _RANDOM[7'h3F][14]; + tables_3_io_update_target_r = {_RANDOM[7'h3F][31:15], _RANDOM[7'h40][23:0]}; + tables_3_io_update_old_target_r = + {_RANDOM[7'h40][31:24], _RANDOM[7'h41], _RANDOM[7'h42][0]}; + tables_3_io_update_alloc_r = _RANDOM[7'h42][1]; + tables_3_io_update_oldCtr_r = _RANDOM[7'h42][3:2]; + tables_3_io_update_uValid_r = _RANDOM[7'h42][4]; + tables_3_io_update_u_r = _RANDOM[7'h42][5]; + tables_3_io_update_pc_r = {_RANDOM[7'h42][31:6], _RANDOM[7'h43][14:0]}; + tables_3_io_update_folded_hist_r_hist_6_folded_hist = _RANDOM[7'h46][16:8]; + tables_3_io_update_folded_hist_r_hist_2_folded_hist = _RANDOM[7'h47][15:8]; + tables_4_io_update_valid_REG = _RANDOM[7'h48][3]; + tables_4_io_update_reset_u_REG = _RANDOM[7'h48][4]; + tables_4_io_update_correct_r = _RANDOM[7'h48][5]; + tables_4_io_update_target_r = {_RANDOM[7'h48][31:6], _RANDOM[7'h49][14:0]}; + tables_4_io_update_old_target_r = {_RANDOM[7'h49][31:15], _RANDOM[7'h4A][23:0]}; + tables_4_io_update_alloc_r = _RANDOM[7'h4A][24]; + tables_4_io_update_oldCtr_r = _RANDOM[7'h4A][26:25]; + tables_4_io_update_uValid_r = _RANDOM[7'h4A][27]; + tables_4_io_update_u_r = _RANDOM[7'h4A][28]; + tables_4_io_update_pc_r = + {_RANDOM[7'h4A][31:29], _RANDOM[7'h4B], _RANDOM[7'h4C][5:0]}; + tables_4_io_update_folded_hist_r_hist_10_folded_hist = _RANDOM[7'h4E][8:0]; + tables_4_io_update_folded_hist_r_hist_3_folded_hist = _RANDOM[7'h4F][30:23]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + tickCtr = 8'h0; + s2_allocLFSR_lfsr = 64'h1234567887654321; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + ITTageTable tables_0 ( + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_12_folded_hist + (io_in_bits_folded_hist_3_hist_12_folded_hist), + .io_resp_valid (_tables_0_io_resp_valid), + .io_resp_bits_ctr (_tables_0_io_resp_bits_ctr), + .io_resp_bits_u (_tables_0_io_resp_bits_u), + .io_resp_bits_target (_tables_0_io_resp_bits_target), + .io_update_pc (tables_0_io_update_pc_r), + .io_update_folded_hist_hist_12_folded_hist + (tables_0_io_update_folded_hist_r_hist_12_folded_hist), + .io_update_valid (tables_0_io_update_valid_REG), + .io_update_correct (tables_0_io_update_correct_r), + .io_update_alloc (tables_0_io_update_alloc_r), + .io_update_oldCtr (tables_0_io_update_oldCtr_r), + .io_update_uValid (tables_0_io_update_uValid_r), + .io_update_u (tables_0_io_update_u_r), + .io_update_reset_u (tables_0_io_update_reset_u_REG), + .io_update_target (tables_0_io_update_target_r), + .io_update_old_target (tables_0_io_update_old_target_r) + ); + ITTageTable_1 tables_1 ( + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_14_folded_hist + (io_in_bits_folded_hist_3_hist_14_folded_hist), + .io_resp_valid (_tables_1_io_resp_valid), + .io_resp_bits_ctr (_tables_1_io_resp_bits_ctr), + .io_resp_bits_u (_tables_1_io_resp_bits_u), + .io_resp_bits_target (_tables_1_io_resp_bits_target), + .io_update_pc (tables_1_io_update_pc_r), + .io_update_folded_hist_hist_14_folded_hist + (tables_1_io_update_folded_hist_r_hist_14_folded_hist), + .io_update_valid (tables_1_io_update_valid_REG), + .io_update_correct (tables_1_io_update_correct_r), + .io_update_alloc (tables_1_io_update_alloc_r), + .io_update_oldCtr (tables_1_io_update_oldCtr_r), + .io_update_uValid (tables_1_io_update_uValid_r), + .io_update_u (tables_1_io_update_u_r), + .io_update_reset_u (tables_1_io_update_reset_u_REG), + .io_update_target (tables_1_io_update_target_r), + .io_update_old_target (tables_1_io_update_old_target_r) + ); + ITTageTable_2 tables_2 ( + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_13_folded_hist + (io_in_bits_folded_hist_3_hist_13_folded_hist), + .io_req_bits_folded_hist_hist_4_folded_hist + (io_in_bits_folded_hist_3_hist_4_folded_hist), + .io_resp_valid (_tables_2_io_resp_valid), + .io_resp_bits_ctr (_tables_2_io_resp_bits_ctr), + .io_resp_bits_u (_tables_2_io_resp_bits_u), + .io_resp_bits_target (_tables_2_io_resp_bits_target), + .io_update_pc (tables_2_io_update_pc_r), + .io_update_folded_hist_hist_13_folded_hist + (tables_2_io_update_folded_hist_r_hist_13_folded_hist), + .io_update_folded_hist_hist_4_folded_hist + (tables_2_io_update_folded_hist_r_hist_4_folded_hist), + .io_update_valid (tables_2_io_update_valid_REG), + .io_update_correct (tables_2_io_update_correct_r), + .io_update_alloc (tables_2_io_update_alloc_r), + .io_update_oldCtr (tables_2_io_update_oldCtr_r), + .io_update_uValid (tables_2_io_update_uValid_r), + .io_update_u (tables_2_io_update_u_r), + .io_update_reset_u (tables_2_io_update_reset_u_REG), + .io_update_target (tables_2_io_update_target_r), + .io_update_old_target (tables_2_io_update_old_target_r) + ); + ITTageTable_3 tables_3 ( + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_6_folded_hist + (io_in_bits_folded_hist_3_hist_6_folded_hist), + .io_req_bits_folded_hist_hist_2_folded_hist + (io_in_bits_folded_hist_3_hist_2_folded_hist), + .io_resp_valid (_tables_3_io_resp_valid), + .io_resp_bits_ctr (_tables_3_io_resp_bits_ctr), + .io_resp_bits_u (_tables_3_io_resp_bits_u), + .io_resp_bits_target (_tables_3_io_resp_bits_target), + .io_update_pc (tables_3_io_update_pc_r), + .io_update_folded_hist_hist_6_folded_hist + (tables_3_io_update_folded_hist_r_hist_6_folded_hist), + .io_update_folded_hist_hist_2_folded_hist + (tables_3_io_update_folded_hist_r_hist_2_folded_hist), + .io_update_valid (tables_3_io_update_valid_REG), + .io_update_correct (tables_3_io_update_correct_r), + .io_update_alloc (tables_3_io_update_alloc_r), + .io_update_oldCtr (tables_3_io_update_oldCtr_r), + .io_update_uValid (tables_3_io_update_uValid_r), + .io_update_u (tables_3_io_update_u_r), + .io_update_reset_u (tables_3_io_update_reset_u_REG), + .io_update_target (tables_3_io_update_target_r), + .io_update_old_target (tables_3_io_update_old_target_r) + ); + ITTageTable_4 tables_4 ( + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_10_folded_hist + (io_in_bits_folded_hist_3_hist_10_folded_hist), + .io_req_bits_folded_hist_hist_3_folded_hist + (io_in_bits_folded_hist_3_hist_3_folded_hist), + .io_resp_valid (_tables_4_io_resp_valid), + .io_resp_bits_ctr (_tables_4_io_resp_bits_ctr), + .io_resp_bits_u (_tables_4_io_resp_bits_u), + .io_resp_bits_target (_tables_4_io_resp_bits_target), + .io_update_pc (tables_4_io_update_pc_r), + .io_update_folded_hist_hist_10_folded_hist + (tables_4_io_update_folded_hist_r_hist_10_folded_hist), + .io_update_folded_hist_hist_3_folded_hist + (tables_4_io_update_folded_hist_r_hist_3_folded_hist), + .io_update_valid (tables_4_io_update_valid_REG), + .io_update_correct (tables_4_io_update_correct_r), + .io_update_alloc (tables_4_io_update_alloc_r), + .io_update_oldCtr (tables_4_io_update_oldCtr_r), + .io_update_uValid (tables_4_io_update_uValid_r), + .io_update_u (tables_4_io_update_u_r), + .io_update_reset_u (tables_4_io_update_reset_u_REG), + .io_update_target (tables_4_io_update_target_r), + .io_update_old_target (tables_4_io_update_old_target_r) + ); + assign io_out_s2_full_pred_0_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0; + assign io_out_s2_full_pred_0_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1; + assign io_out_s2_full_pred_0_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0; + assign io_out_s2_full_pred_0_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1; + assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0; + assign io_out_s2_full_pred_0_targets_1 = io_in_bits_resp_in_0_s2_full_pred_0_targets_1; + assign io_out_s2_full_pred_0_jalr_target = + io_in_bits_resp_in_0_s2_full_pred_0_jalr_target; + assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0; + assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1; + assign io_out_s2_full_pred_0_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr; + assign io_out_s2_full_pred_0_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing; + assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit; + assign io_out_s2_full_pred_1_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0; + assign io_out_s2_full_pred_1_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1; + assign io_out_s2_full_pred_1_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0; + assign io_out_s2_full_pred_1_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1; + assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0; + assign io_out_s2_full_pred_1_targets_1 = io_in_bits_resp_in_0_s2_full_pred_1_targets_1; + assign io_out_s2_full_pred_1_jalr_target = + io_in_bits_resp_in_0_s2_full_pred_1_jalr_target; + assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0; + assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1; + assign io_out_s2_full_pred_1_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr; + assign io_out_s2_full_pred_1_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing; + assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit; + assign io_out_s2_full_pred_2_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; + assign io_out_s2_full_pred_2_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; + assign io_out_s2_full_pred_2_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0; + assign io_out_s2_full_pred_2_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1; + assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0; + assign io_out_s2_full_pred_2_targets_1 = io_in_bits_resp_in_0_s2_full_pred_2_targets_1; + assign io_out_s2_full_pred_2_jalr_target = + io_in_bits_resp_in_0_s2_full_pred_2_jalr_target; + assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0; + assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1; + assign io_out_s2_full_pred_2_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr; + assign io_out_s2_full_pred_2_is_jalr = io_in_bits_resp_in_0_s2_full_pred_2_is_jalr; + assign io_out_s2_full_pred_2_is_call = io_in_bits_resp_in_0_s2_full_pred_2_is_call; + assign io_out_s2_full_pred_2_is_ret = io_in_bits_resp_in_0_s2_full_pred_2_is_ret; + assign io_out_s2_full_pred_2_last_may_be_rvi_call = + io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call; + assign io_out_s2_full_pred_2_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing; + assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit; + assign io_out_s2_full_pred_3_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0; + assign io_out_s2_full_pred_3_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1; + assign io_out_s2_full_pred_3_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0; + assign io_out_s2_full_pred_3_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1; + assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0; + assign io_out_s2_full_pred_3_targets_1 = io_in_bits_resp_in_0_s2_full_pred_3_targets_1; + assign io_out_s2_full_pred_3_jalr_target = + io_in_bits_resp_in_0_s2_full_pred_3_jalr_target; + assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0; + assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1; + assign io_out_s2_full_pred_3_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr; + assign io_out_s2_full_pred_3_fallThroughErr = + io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr; + assign io_out_s2_full_pred_3_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing; + assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit; + assign io_out_s3_full_pred_0_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0; + assign io_out_s3_full_pred_0_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1; + assign io_out_s3_full_pred_0_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0; + assign io_out_s3_full_pred_0_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1; + assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0; + assign io_out_s3_full_pred_0_targets_1 = io_in_bits_resp_in_0_s3_full_pred_0_targets_1; + assign io_out_s3_full_pred_0_jalr_target = + s3_tageTaken_dup_0 + ? s3_tageTarget_dup_0 + : io_in_bits_resp_in_0_s3_full_pred_0_jalr_target; + assign io_out_s3_full_pred_0_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr; + assign io_out_s3_full_pred_0_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr; + assign io_out_s3_full_pred_0_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing; + assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit; + assign io_out_s3_full_pred_1_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0; + assign io_out_s3_full_pred_1_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1; + assign io_out_s3_full_pred_1_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0; + assign io_out_s3_full_pred_1_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1; + assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0; + assign io_out_s3_full_pred_1_targets_1 = io_in_bits_resp_in_0_s3_full_pred_1_targets_1; + assign io_out_s3_full_pred_1_jalr_target = + s3_tageTaken_dup_1 + ? s3_tageTarget_dup_1 + : io_in_bits_resp_in_0_s3_full_pred_1_jalr_target; + assign io_out_s3_full_pred_1_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr; + assign io_out_s3_full_pred_1_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr; + assign io_out_s3_full_pred_1_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing; + assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit; + assign io_out_s3_full_pred_2_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; + assign io_out_s3_full_pred_2_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; + assign io_out_s3_full_pred_2_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0; + assign io_out_s3_full_pred_2_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1; + assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0; + assign io_out_s3_full_pred_2_targets_1 = io_in_bits_resp_in_0_s3_full_pred_2_targets_1; + assign io_out_s3_full_pred_2_jalr_target = + s3_tageTaken_dup_2 + ? s3_tageTarget_dup_2 + : io_in_bits_resp_in_0_s3_full_pred_2_jalr_target; + assign io_out_s3_full_pred_2_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr; + assign io_out_s3_full_pred_2_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr; + assign io_out_s3_full_pred_2_is_jalr = io_in_bits_resp_in_0_s3_full_pred_2_is_jalr; + assign io_out_s3_full_pred_2_is_call = io_in_bits_resp_in_0_s3_full_pred_2_is_call; + assign io_out_s3_full_pred_2_is_ret = io_in_bits_resp_in_0_s3_full_pred_2_is_ret; + assign io_out_s3_full_pred_2_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing; + assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit; + assign io_out_s3_full_pred_3_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0; + assign io_out_s3_full_pred_3_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1; + assign io_out_s3_full_pred_3_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0; + assign io_out_s3_full_pred_3_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1; + assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0; + assign io_out_s3_full_pred_3_targets_1 = io_in_bits_resp_in_0_s3_full_pred_3_targets_1; + assign io_out_s3_full_pred_3_jalr_target = + s3_tageTaken_dup_3 + ? s3_tageTarget_dup_3 + : io_in_bits_resp_in_0_s3_full_pred_3_jalr_target; + assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0; + assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1; + assign io_out_s3_full_pred_3_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr; + assign io_out_s3_full_pred_3_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr; + assign io_out_s3_full_pred_3_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing; + assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit; + assign io_out_last_stage_meta = + {122'h0, + s3_provided, + s3_provider, + s3_altProvided, + s3_altProvider, + resp_meta_altDiffers, + s3_providerU, + s3_providerCtr, + s3_altProviderCtr, + resp_meta_allocate_valid_r, + resp_meta_allocate_bits_r, + s3_tageTaken_dup_3, + s3_providerTarget, + s3_altProviderTarget}; + assign io_out_last_stage_ftb_entry_valid = + io_in_bits_resp_in_0_last_stage_ftb_entry_valid; + assign io_out_last_stage_ftb_entry_brSlots_0_offset = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset; + assign io_out_last_stage_ftb_entry_brSlots_0_lower = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower; + assign io_out_last_stage_ftb_entry_brSlots_0_tarStat = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat; + assign io_out_last_stage_ftb_entry_brSlots_0_sharing = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing; + assign io_out_last_stage_ftb_entry_brSlots_0_valid = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid; + assign io_out_last_stage_ftb_entry_tailSlot_offset = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset; + assign io_out_last_stage_ftb_entry_tailSlot_lower = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower; + assign io_out_last_stage_ftb_entry_tailSlot_tarStat = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat; + assign io_out_last_stage_ftb_entry_tailSlot_sharing = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing; + assign io_out_last_stage_ftb_entry_tailSlot_valid = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid; + assign io_out_last_stage_ftb_entry_pftAddr = + io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr; + assign io_out_last_stage_ftb_entry_carry = + io_in_bits_resp_in_0_last_stage_ftb_entry_carry; + assign io_out_last_stage_ftb_entry_isCall = + io_in_bits_resp_in_0_last_stage_ftb_entry_isCall; + assign io_out_last_stage_ftb_entry_isRet = + io_in_bits_resp_in_0_last_stage_ftb_entry_isRet; + assign io_out_last_stage_ftb_entry_isJalr = + io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr; + assign io_out_last_stage_ftb_entry_last_may_be_rvi_call = + io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call; + assign io_out_last_stage_ftb_entry_always_taken_0 = + io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0; + assign io_out_last_stage_ftb_entry_always_taken_1 = + io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1; +endmodule + diff --git a/rtl/BPUTop/ITTageTable.sv b/rtl/BPUTop/ITTageTable.sv new file mode 100644 index 0000000..c704d8d --- /dev/null +++ b/rtl/BPUTop/ITTageTable.sv @@ -0,0 +1,226 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module ITTageTable( + input clock, + input reset, + input io_req_valid, + input [40:0] io_req_bits_pc, + input [3:0] io_req_bits_folded_hist_hist_12_folded_hist, + output io_resp_valid, + output [1:0] io_resp_bits_ctr, + output [1:0] io_resp_bits_u, + output [40:0] io_resp_bits_target, + input [40:0] io_update_pc, + input [3:0] io_update_folded_hist_hist_12_folded_hist, + input io_update_valid, + input io_update_correct, + input io_update_alloc, + input [1:0] io_update_oldCtr, + input io_update_uValid, + input io_update_u, + input io_update_reset_u, + input [40:0] io_update_target, + input [40:0] io_update_old_target +); + + wire _resp_invalid_by_write_T_2; + wire _wrbypass_io_hit; + wire [1:0] _wrbypass_io_hit_data_0_bits; + wire _table_banks_1_io_r_resp_data_0_valid; + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; + wire [40:0] _table_banks_1_io_r_resp_data_0_target; + wire _table_banks_0_io_r_resp_data_0_valid; + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; + wire [40:0] _table_banks_0_io_r_resp_data_0_target; + wire _us_io_rdata_0; + wire [3:0] _GEN = io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist; + reg [8:0] s1_tag; + reg s1_bank_req_1h_0; + reg s1_bank_req_1h_1; + wire [6:0] _table_banks_1_io_r_req_bits_setIdx_T = {io_req_bits_pc[8:5], _GEN[3:1]}; + reg s1_bank_has_write_on_this_req_0; + reg s1_bank_has_write_on_this_req_1; + wire [3:0] _GEN_0 = io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist; + wire [7:0] update_idx = {io_update_pc[8:5], _GEN_0}; + wire [8:0] update_tag = + {io_update_pc[17:14], + {io_update_pc[13], io_update_pc[12:9] ^ io_update_folded_hist_hist_12_folded_hist} + ^ {io_update_folded_hist_hist_12_folded_hist, 1'h0}}; + wire [6:0] update_idx_in_bank = {io_update_pc[8:5], _GEN_0[3:1]}; + assign _resp_invalid_by_write_T_2 = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1; + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(_GEN_0[0]); + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & _GEN_0[0]; + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; + wire [1:0] update_wdata_ctr = + io_update_alloc + ? 2'h2 + : (&old_ctr) & io_update_correct + ? 2'h3 + : update_wdata_ctr_oldSatNotTaken & ~io_update_correct + ? 2'h0 + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); + wire [40:0] update_wdata_target = + io_update_alloc | update_wdata_ctr_oldSatNotTaken + ? io_update_target + : io_update_old_target; + always @(posedge clock) begin + if (io_req_valid) begin + s1_tag <= + {io_req_bits_pc[17:14], + {io_req_bits_pc[13], + io_req_bits_pc[12:9] ^ io_req_bits_folded_hist_hist_12_folded_hist} + ^ {io_req_bits_folded_hist_hist_12_folded_hist, 1'h0}}; + s1_bank_req_1h_0 <= ~(_GEN[0]); + s1_bank_req_1h_1 <= _GEN[0]; + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + s1_tag = _RANDOM[/*Zero width*/ 1'b0][16:8]; + s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][17]; + s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][18]; + s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][19]; + s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][20]; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Folded1WDataModuleTemplate us ( + .clock (clock), + .reset (reset), + .io_ren_0 (io_req_valid), + .io_raddr_0 ({io_req_bits_pc[8:5], _GEN}), + .io_rdata_0 (_us_io_rdata_0), + .io_wen (io_update_uValid), + .io_waddr (update_idx), + .io_wdata (io_update_u), + .io_resetEn (io_update_reset_u) + ); + FoldedSRAMTemplate_21 table_banks_0 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & ~(_GEN[0])), + .io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T), + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), + .io_w_req_bits_setIdx (update_idx_in_bank), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (update_wdata_ctr), + .io_w_req_bits_data_0_target (update_wdata_target) + ); + FoldedSRAMTemplate_21 table_banks_1 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & _GEN[0]), + .io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T), + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), + .io_w_req_bits_setIdx (update_idx_in_bank), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (update_wdata_ctr), + .io_w_req_bits_data_0_target (update_wdata_target) + ); + WrBypass_41 wrbypass ( + .clock (clock), + .reset (reset), + .io_wen (io_update_valid), + .io_write_idx (update_idx), + .io_write_data_0 (update_wdata_ctr), + .io_hit (_wrbypass_io_hit), + .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) + ); + assign io_resp_valid = + (s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1 + & _table_banks_1_io_r_resp_data_0_valid) + & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag + & ~_resp_invalid_by_write_T_2; + assign io_resp_bits_ctr = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; + assign io_resp_bits_target = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0); +endmodule + diff --git a/rtl/BPUTop/ITTageTable_1.sv b/rtl/BPUTop/ITTageTable_1.sv new file mode 100644 index 0000000..39d6899 --- /dev/null +++ b/rtl/BPUTop/ITTageTable_1.sv @@ -0,0 +1,221 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module ITTageTable_1( + input clock, + input reset, + input io_req_valid, + input [40:0] io_req_bits_pc, + input [7:0] io_req_bits_folded_hist_hist_14_folded_hist, + output io_resp_valid, + output [1:0] io_resp_bits_ctr, + output [1:0] io_resp_bits_u, + output [40:0] io_resp_bits_target, + input [40:0] io_update_pc, + input [7:0] io_update_folded_hist_hist_14_folded_hist, + input io_update_valid, + input io_update_correct, + input io_update_alloc, + input [1:0] io_update_oldCtr, + input io_update_uValid, + input io_update_u, + input io_update_reset_u, + input [40:0] io_update_target, + input [40:0] io_update_old_target +); + + wire _resp_invalid_by_write_T_2; + wire _wrbypass_io_hit; + wire [1:0] _wrbypass_io_hit_data_0_bits; + wire _table_banks_1_io_r_resp_data_0_valid; + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; + wire [40:0] _table_banks_1_io_r_resp_data_0_target; + wire _table_banks_0_io_r_resp_data_0_valid; + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; + wire [40:0] _table_banks_0_io_r_resp_data_0_target; + wire _us_io_rdata_0; + wire [7:0] s0_idx = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist; + reg [8:0] s1_tag; + reg s1_bank_req_1h_0; + reg s1_bank_req_1h_1; + reg s1_bank_has_write_on_this_req_0; + reg s1_bank_has_write_on_this_req_1; + wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist; + wire [8:0] update_tag = + {io_update_pc[17], io_update_pc[16:9] ^ io_update_folded_hist_hist_14_folded_hist} + ^ {io_update_folded_hist_hist_14_folded_hist, 1'h0}; + assign _resp_invalid_by_write_T_2 = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1; + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; + wire [1:0] update_wdata_ctr = + io_update_alloc + ? 2'h2 + : (&old_ctr) & io_update_correct + ? 2'h3 + : update_wdata_ctr_oldSatNotTaken & ~io_update_correct + ? 2'h0 + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); + wire [40:0] update_wdata_target = + io_update_alloc | update_wdata_ctr_oldSatNotTaken + ? io_update_target + : io_update_old_target; + always @(posedge clock) begin + if (io_req_valid) begin + s1_tag <= + {io_req_bits_pc[17], + io_req_bits_pc[16:9] ^ io_req_bits_folded_hist_hist_14_folded_hist} + ^ {io_req_bits_folded_hist_hist_14_folded_hist, 1'h0}; + s1_bank_req_1h_0 <= ~(s0_idx[0]); + s1_bank_req_1h_1 <= s0_idx[0]; + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + s1_tag = _RANDOM[/*Zero width*/ 1'b0][16:8]; + s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][17]; + s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][18]; + s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][19]; + s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][20]; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Folded1WDataModuleTemplate us ( + .clock (clock), + .reset (reset), + .io_ren_0 (io_req_valid), + .io_raddr_0 (s0_idx), + .io_rdata_0 (_us_io_rdata_0), + .io_wen (io_update_uValid), + .io_waddr (update_idx), + .io_wdata (io_update_u), + .io_resetEn (io_update_reset_u) + ); + FoldedSRAMTemplate_21 table_banks_0 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & ~(s0_idx[0])), + .io_r_req_bits_setIdx (s0_idx[7:1]), + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), + .io_w_req_bits_setIdx (update_idx[7:1]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (update_wdata_ctr), + .io_w_req_bits_data_0_target (update_wdata_target) + ); + FoldedSRAMTemplate_21 table_banks_1 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & s0_idx[0]), + .io_r_req_bits_setIdx (s0_idx[7:1]), + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), + .io_w_req_bits_setIdx (update_idx[7:1]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (update_wdata_ctr), + .io_w_req_bits_data_0_target (update_wdata_target) + ); + WrBypass_41 wrbypass ( + .clock (clock), + .reset (reset), + .io_wen (io_update_valid), + .io_write_idx (update_idx), + .io_write_data_0 (update_wdata_ctr), + .io_hit (_wrbypass_io_hit), + .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) + ); + assign io_resp_valid = + (s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1 + & _table_banks_1_io_r_resp_data_0_valid) + & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag + & ~_resp_invalid_by_write_T_2; + assign io_resp_bits_ctr = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; + assign io_resp_bits_target = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0); +endmodule + diff --git a/rtl/BPUTop/ITTageTable_2.sv b/rtl/BPUTop/ITTageTable_2.sv new file mode 100644 index 0000000..ca46372 --- /dev/null +++ b/rtl/BPUTop/ITTageTable_2.sv @@ -0,0 +1,222 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module ITTageTable_2( + input clock, + input reset, + input io_req_valid, + input [40:0] io_req_bits_pc, + input [8:0] io_req_bits_folded_hist_hist_13_folded_hist, + input [7:0] io_req_bits_folded_hist_hist_4_folded_hist, + output io_resp_valid, + output [1:0] io_resp_bits_ctr, + output [1:0] io_resp_bits_u, + output [40:0] io_resp_bits_target, + input [40:0] io_update_pc, + input [8:0] io_update_folded_hist_hist_13_folded_hist, + input [7:0] io_update_folded_hist_hist_4_folded_hist, + input io_update_valid, + input io_update_correct, + input io_update_alloc, + input [1:0] io_update_oldCtr, + input io_update_uValid, + input io_update_u, + input io_update_reset_u, + input [40:0] io_update_target, + input [40:0] io_update_old_target +); + + wire _resp_invalid_by_write_T_2; + wire _wrbypass_io_hit; + wire [1:0] _wrbypass_io_hit_data_0_bits; + wire _table_banks_1_io_r_resp_data_0_valid; + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; + wire [40:0] _table_banks_1_io_r_resp_data_0_target; + wire _table_banks_0_io_r_resp_data_0_valid; + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; + wire [40:0] _table_banks_0_io_r_resp_data_0_target; + wire _us_io_rdata_0; + wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_13_folded_hist; + reg [8:0] s1_tag; + reg s1_bank_req_1h_0; + reg s1_bank_req_1h_1; + reg s1_bank_has_write_on_this_req_0; + reg s1_bank_has_write_on_this_req_1; + wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_13_folded_hist; + wire [8:0] update_tag = + io_update_pc[18:10] ^ io_update_folded_hist_hist_13_folded_hist + ^ {io_update_folded_hist_hist_4_folded_hist, 1'h0}; + assign _resp_invalid_by_write_T_2 = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1; + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; + wire [1:0] update_wdata_ctr = + io_update_alloc + ? 2'h2 + : (&old_ctr) & io_update_correct + ? 2'h3 + : update_wdata_ctr_oldSatNotTaken & ~io_update_correct + ? 2'h0 + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); + wire [40:0] update_wdata_target = + io_update_alloc | update_wdata_ctr_oldSatNotTaken + ? io_update_target + : io_update_old_target; + always @(posedge clock) begin + if (io_req_valid) begin + s1_tag <= + io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_13_folded_hist + ^ {io_req_bits_folded_hist_hist_4_folded_hist, 1'h0}; + s1_bank_req_1h_0 <= ~(s0_idx[0]); + s1_bank_req_1h_1 <= s0_idx[0]; + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9]; + s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18]; + s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19]; + s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20]; + s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21]; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Folded1WDataModuleTemplate_2 us ( + .clock (clock), + .reset (reset), + .io_ren_0 (io_req_valid), + .io_raddr_0 (s0_idx), + .io_rdata_0 (_us_io_rdata_0), + .io_wen (io_update_uValid), + .io_waddr (update_idx), + .io_wdata (io_update_u), + .io_resetEn (io_update_reset_u) + ); + FoldedSRAMTemplate_25 table_banks_0 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & ~(s0_idx[0])), + .io_r_req_bits_setIdx (s0_idx[8:1]), + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), + .io_w_req_bits_setIdx (update_idx[8:1]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (update_wdata_ctr), + .io_w_req_bits_data_0_target (update_wdata_target) + ); + FoldedSRAMTemplate_25 table_banks_1 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & s0_idx[0]), + .io_r_req_bits_setIdx (s0_idx[8:1]), + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), + .io_w_req_bits_setIdx (update_idx[8:1]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (update_wdata_ctr), + .io_w_req_bits_data_0_target (update_wdata_target) + ); + WrBypass_43 wrbypass ( + .clock (clock), + .reset (reset), + .io_wen (io_update_valid), + .io_write_idx (update_idx), + .io_write_data_0 (update_wdata_ctr), + .io_hit (_wrbypass_io_hit), + .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) + ); + assign io_resp_valid = + (s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1 + & _table_banks_1_io_r_resp_data_0_valid) + & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag + & ~_resp_invalid_by_write_T_2; + assign io_resp_bits_ctr = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; + assign io_resp_bits_target = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0); +endmodule + diff --git a/rtl/BPUTop/ITTageTable_3.sv b/rtl/BPUTop/ITTageTable_3.sv new file mode 100644 index 0000000..ceb65d4 --- /dev/null +++ b/rtl/BPUTop/ITTageTable_3.sv @@ -0,0 +1,222 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module ITTageTable_3( + input clock, + input reset, + input io_req_valid, + input [40:0] io_req_bits_pc, + input [8:0] io_req_bits_folded_hist_hist_6_folded_hist, + input [7:0] io_req_bits_folded_hist_hist_2_folded_hist, + output io_resp_valid, + output [1:0] io_resp_bits_ctr, + output [1:0] io_resp_bits_u, + output [40:0] io_resp_bits_target, + input [40:0] io_update_pc, + input [8:0] io_update_folded_hist_hist_6_folded_hist, + input [7:0] io_update_folded_hist_hist_2_folded_hist, + input io_update_valid, + input io_update_correct, + input io_update_alloc, + input [1:0] io_update_oldCtr, + input io_update_uValid, + input io_update_u, + input io_update_reset_u, + input [40:0] io_update_target, + input [40:0] io_update_old_target +); + + wire _resp_invalid_by_write_T_2; + wire _wrbypass_io_hit; + wire [1:0] _wrbypass_io_hit_data_0_bits; + wire _table_banks_1_io_r_resp_data_0_valid; + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; + wire [40:0] _table_banks_1_io_r_resp_data_0_target; + wire _table_banks_0_io_r_resp_data_0_valid; + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; + wire [40:0] _table_banks_0_io_r_resp_data_0_target; + wire _us_io_rdata_0; + wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_6_folded_hist; + reg [8:0] s1_tag; + reg s1_bank_req_1h_0; + reg s1_bank_req_1h_1; + reg s1_bank_has_write_on_this_req_0; + reg s1_bank_has_write_on_this_req_1; + wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_6_folded_hist; + wire [8:0] update_tag = + io_update_pc[18:10] ^ io_update_folded_hist_hist_6_folded_hist + ^ {io_update_folded_hist_hist_2_folded_hist, 1'h0}; + assign _resp_invalid_by_write_T_2 = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1; + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; + wire [1:0] update_wdata_ctr = + io_update_alloc + ? 2'h2 + : (&old_ctr) & io_update_correct + ? 2'h3 + : update_wdata_ctr_oldSatNotTaken & ~io_update_correct + ? 2'h0 + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); + wire [40:0] update_wdata_target = + io_update_alloc | update_wdata_ctr_oldSatNotTaken + ? io_update_target + : io_update_old_target; + always @(posedge clock) begin + if (io_req_valid) begin + s1_tag <= + io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_6_folded_hist + ^ {io_req_bits_folded_hist_hist_2_folded_hist, 1'h0}; + s1_bank_req_1h_0 <= ~(s0_idx[0]); + s1_bank_req_1h_1 <= s0_idx[0]; + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9]; + s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18]; + s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19]; + s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20]; + s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21]; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Folded1WDataModuleTemplate_2 us ( + .clock (clock), + .reset (reset), + .io_ren_0 (io_req_valid), + .io_raddr_0 (s0_idx), + .io_rdata_0 (_us_io_rdata_0), + .io_wen (io_update_uValid), + .io_waddr (update_idx), + .io_wdata (io_update_u), + .io_resetEn (io_update_reset_u) + ); + FoldedSRAMTemplate_25 table_banks_0 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & ~(s0_idx[0])), + .io_r_req_bits_setIdx (s0_idx[8:1]), + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), + .io_w_req_bits_setIdx (update_idx[8:1]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (update_wdata_ctr), + .io_w_req_bits_data_0_target (update_wdata_target) + ); + FoldedSRAMTemplate_25 table_banks_1 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & s0_idx[0]), + .io_r_req_bits_setIdx (s0_idx[8:1]), + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), + .io_w_req_bits_setIdx (update_idx[8:1]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (update_wdata_ctr), + .io_w_req_bits_data_0_target (update_wdata_target) + ); + WrBypass_43 wrbypass ( + .clock (clock), + .reset (reset), + .io_wen (io_update_valid), + .io_write_idx (update_idx), + .io_write_data_0 (update_wdata_ctr), + .io_hit (_wrbypass_io_hit), + .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) + ); + assign io_resp_valid = + (s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1 + & _table_banks_1_io_r_resp_data_0_valid) + & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag + & ~_resp_invalid_by_write_T_2; + assign io_resp_bits_ctr = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; + assign io_resp_bits_target = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0); +endmodule + diff --git a/rtl/BPUTop/ITTageTable_4.sv b/rtl/BPUTop/ITTageTable_4.sv new file mode 100644 index 0000000..d6a6102 --- /dev/null +++ b/rtl/BPUTop/ITTageTable_4.sv @@ -0,0 +1,222 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module ITTageTable_4( + input clock, + input reset, + input io_req_valid, + input [40:0] io_req_bits_pc, + input [8:0] io_req_bits_folded_hist_hist_10_folded_hist, + input [7:0] io_req_bits_folded_hist_hist_3_folded_hist, + output io_resp_valid, + output [1:0] io_resp_bits_ctr, + output [1:0] io_resp_bits_u, + output [40:0] io_resp_bits_target, + input [40:0] io_update_pc, + input [8:0] io_update_folded_hist_hist_10_folded_hist, + input [7:0] io_update_folded_hist_hist_3_folded_hist, + input io_update_valid, + input io_update_correct, + input io_update_alloc, + input [1:0] io_update_oldCtr, + input io_update_uValid, + input io_update_u, + input io_update_reset_u, + input [40:0] io_update_target, + input [40:0] io_update_old_target +); + + wire _resp_invalid_by_write_T_2; + wire _wrbypass_io_hit; + wire [1:0] _wrbypass_io_hit_data_0_bits; + wire _table_banks_1_io_r_resp_data_0_valid; + wire [8:0] _table_banks_1_io_r_resp_data_0_tag; + wire [1:0] _table_banks_1_io_r_resp_data_0_ctr; + wire [40:0] _table_banks_1_io_r_resp_data_0_target; + wire _table_banks_0_io_r_resp_data_0_valid; + wire [8:0] _table_banks_0_io_r_resp_data_0_tag; + wire [1:0] _table_banks_0_io_r_resp_data_0_ctr; + wire [40:0] _table_banks_0_io_r_resp_data_0_target; + wire _us_io_rdata_0; + wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_10_folded_hist; + reg [8:0] s1_tag; + reg s1_bank_req_1h_0; + reg s1_bank_req_1h_1; + reg s1_bank_has_write_on_this_req_0; + reg s1_bank_has_write_on_this_req_1; + wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_10_folded_hist; + wire [8:0] update_tag = + io_update_pc[18:10] ^ io_update_folded_hist_hist_10_folded_hist + ^ {io_update_folded_hist_hist_3_folded_hist, 1'h0}; + assign _resp_invalid_by_write_T_2 = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1; + wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]); + wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0]; + wire [1:0] old_ctr = + _wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr; + wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0; + wire [1:0] update_wdata_ctr = + io_update_alloc + ? 2'h2 + : (&old_ctr) & io_update_correct + ? 2'h3 + : update_wdata_ctr_oldSatNotTaken & ~io_update_correct + ? 2'h0 + : io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1); + wire [40:0] update_wdata_target = + io_update_alloc | update_wdata_ctr_oldSatNotTaken + ? io_update_target + : io_update_old_target; + always @(posedge clock) begin + if (io_req_valid) begin + s1_tag <= + io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_10_folded_hist + ^ {io_req_bits_folded_hist_hist_3_folded_hist, 1'h0}; + s1_bank_req_1h_0 <= ~(s0_idx[0]); + s1_bank_req_1h_1 <= s0_idx[0]; + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9]; + s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18]; + s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19]; + s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20]; + s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21]; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Folded1WDataModuleTemplate_2 us ( + .clock (clock), + .reset (reset), + .io_ren_0 (io_req_valid), + .io_raddr_0 (s0_idx), + .io_rdata_0 (_us_io_rdata_0), + .io_wen (io_update_uValid), + .io_waddr (update_idx), + .io_wdata (io_update_u), + .io_resetEn (io_update_reset_u) + ); + FoldedSRAMTemplate_25 table_banks_0 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & ~(s0_idx[0])), + .io_r_req_bits_setIdx (s0_idx[8:1]), + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), + .io_w_req_bits_setIdx (update_idx[8:1]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (update_wdata_ctr), + .io_w_req_bits_data_0_target (update_wdata_target) + ); + FoldedSRAMTemplate_25 table_banks_1 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid & s0_idx[0]), + .io_r_req_bits_setIdx (s0_idx[8:1]), + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), + .io_w_req_bits_setIdx (update_idx[8:1]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (update_wdata_ctr), + .io_w_req_bits_data_0_target (update_wdata_target) + ); + WrBypass_43 wrbypass ( + .clock (clock), + .reset (reset), + .io_wen (io_update_valid), + .io_write_idx (update_idx), + .io_write_data_0 (update_wdata_ctr), + .io_hit (_wrbypass_io_hit), + .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits) + ); + assign io_resp_valid = + (s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1 + & _table_banks_1_io_r_resp_data_0_valid) + & ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag + & ~_resp_invalid_by_write_T_2; + assign io_resp_bits_ctr = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0); + assign io_resp_bits_u = {1'h0, _us_io_rdata_0}; + assign io_resp_bits_target = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0); +endmodule + diff --git a/rtl/BPUTop/Predictor.sv b/rtl/BPUTop/Predictor.sv new file mode 100644 index 0000000..3e93bbe --- /dev/null +++ b/rtl/BPUTop/Predictor.sv @@ -0,0 +1,33300 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module Predictor( + input clock, + input reset, + input io_bpu_to_ftq_resp_ready, + output io_bpu_to_ftq_resp_valid, + output [40:0] io_bpu_to_ftq_resp_bits_s1_pc_3, + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_0, + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_1, + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_0, + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_1, + output [40:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_0, + output [40:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_1, + output [3:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_0, + output [3:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_1, + output [40:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughAddr, + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughErr, + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_is_br_sharing, + output io_bpu_to_ftq_resp_bits_s1_full_pred_3_hit, + output [40:0] io_bpu_to_ftq_resp_bits_s2_pc_3, + output io_bpu_to_ftq_resp_bits_s2_valid_3, + output io_bpu_to_ftq_resp_bits_s2_hasRedirect_3, + output io_bpu_to_ftq_resp_bits_s2_ftq_idx_flag, + output [5:0] io_bpu_to_ftq_resp_bits_s2_ftq_idx_value, + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_0, + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_1, + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_0, + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_1, + output [40:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_0, + output [40:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_1, + output [3:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_0, + output [3:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_1, + output [40:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughAddr, + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughErr, + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_is_br_sharing, + output io_bpu_to_ftq_resp_bits_s2_full_pred_3_hit, + output [40:0] io_bpu_to_ftq_resp_bits_s3_pc_3, + output io_bpu_to_ftq_resp_bits_s3_valid_3, + output io_bpu_to_ftq_resp_bits_s3_hasRedirect_3, + output io_bpu_to_ftq_resp_bits_s3_ftq_idx_flag, + output [5:0] io_bpu_to_ftq_resp_bits_s3_ftq_idx_value, + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_0, + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_1, + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_0, + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_1, + output [40:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_0, + output [40:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_1, + output [3:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_0, + output [3:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_1, + output [40:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughAddr, + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughErr, + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_is_br_sharing, + output io_bpu_to_ftq_resp_bits_s3_full_pred_3_hit, + output [222:0] io_bpu_to_ftq_resp_bits_last_stage_meta, + output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_17_folded_hist, + output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_16_folded_hist, + output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_15_folded_hist, + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_14_folded_hist, + output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_13_folded_hist, + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_12_folded_hist, + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_11_folded_hist, + output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_10_folded_hist, + output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_9_folded_hist, + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_8_folded_hist, + output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_7_folded_hist, + output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_6_folded_hist, + output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_5_folded_hist, + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_4_folded_hist, + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_3_folded_hist, + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_2_folded_hist, + output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_1_folded_hist, + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_0_folded_hist, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_0, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_1, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_2, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_3, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_0, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_1, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_2, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_3, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_0, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_1, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_2, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_3, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_0, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_1, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_2, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_3, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_0, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_1, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_2, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_3, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_0, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_1, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_2, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_3, + output [2:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_lastBrNumOH, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_flag, + output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_value, + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_ssp, + output [1:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_sctr, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_flag, + output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_value, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_flag, + output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_value, + output io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_flag, + output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_value, + output [40:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_topAddr, + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_valid, + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_offset, + output [11:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_lower, + output [1:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_tarStat, + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_sharing, + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_valid, + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_offset, + output [19:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_lower, + output [1:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_tarStat, + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_sharing, + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_valid, + output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_pftAddr, + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_carry, + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isCall, + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isRet, + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isJalr, + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_last_may_be_rvi_call, + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_0, + output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_1, + input io_ftq_to_bpu_redirect_valid, + input io_ftq_to_bpu_redirect_bits_level, + input [40:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_pc, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet, + input [3:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp, + input [1:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag, + input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag, + input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag, + input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value, + input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist, + input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist, + input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist, + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist, + input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist, + input [3:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist, + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist, + input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist, + input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist, + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist, + input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist, + input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist, + input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist, + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist, + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist, + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist, + input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist, + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3, + input [2:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag, + input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value, + input [40:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_target, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_taken, + input [1:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_shift, + input io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist, + input io_ftq_to_bpu_update_valid, + input [40:0] io_ftq_to_bpu_update_bits_pc, + input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist, + input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist, + input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist, + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist, + input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist, + input [3:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist, + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist, + input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist, + input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist, + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist, + input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist, + input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist, + input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist, + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist, + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist, + input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist, + input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist, + input io_ftq_to_bpu_update_bits_ftb_entry_valid, + input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset, + input [11:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower, + input [1:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat, + input io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing, + input io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid, + input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset, + input [19:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower, + input [1:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat, + input io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing, + input io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid, + input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_pftAddr, + input io_ftq_to_bpu_update_bits_ftb_entry_carry, + input io_ftq_to_bpu_update_bits_ftb_entry_isCall, + input io_ftq_to_bpu_update_bits_ftb_entry_isRet, + input io_ftq_to_bpu_update_bits_ftb_entry_isJalr, + input io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call, + input io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0, + input io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1, + input io_ftq_to_bpu_update_bits_cfi_idx_valid, + input [3:0] io_ftq_to_bpu_update_bits_cfi_idx_bits, + input io_ftq_to_bpu_update_bits_br_taken_mask_0, + input io_ftq_to_bpu_update_bits_br_taken_mask_1, + input io_ftq_to_bpu_update_bits_jmp_taken, + input io_ftq_to_bpu_update_bits_mispred_mask_0, + input io_ftq_to_bpu_update_bits_mispred_mask_1, + input io_ftq_to_bpu_update_bits_mispred_mask_2, + input io_ftq_to_bpu_update_bits_old_entry, + input [222:0] io_ftq_to_bpu_update_bits_meta, + input [40:0] io_ftq_to_bpu_update_bits_full_target, + input io_ftq_to_bpu_enq_ptr_flag, + input [5:0] io_ftq_to_bpu_enq_ptr_value, + input io_ctrl_ubtb_enable, + input io_ctrl_btb_enable, + input io_ctrl_tage_enable, + input io_ctrl_sc_enable, + input io_ctrl_ras_enable, + input [35:0] io_reset_vector, + output [5:0] io_perf_0_value, + output [5:0] io_perf_1_value, + output [5:0] io_perf_2_value, + output [5:0] io_perf_3_value, + output [5:0] io_perf_4_value, + output [5:0] io_perf_5_value, + output [5:0] io_perf_6_value +); + + wire s3_redirect_dup_3; + wire s3_redirect_dup_2; + wire s3_redirect_dup_0; + wire s2_redirect_dup_2; + wire s2_redirect_dup_0; + wire s1_fire_dup_3; + wire s1_fire_dup_2; + wire s1_fire_dup_1; + wire s1_fire_dup_0; + wire _ghv_write_datas_255_ppm_out_res; + wire _ghv_write_datas_254_ppm_out_res; + wire _ghv_write_datas_253_ppm_out_res; + wire _ghv_write_datas_252_ppm_out_res; + wire _ghv_write_datas_251_ppm_out_res; + wire _ghv_write_datas_250_ppm_out_res; + wire _ghv_write_datas_249_ppm_out_res; + wire _ghv_write_datas_248_ppm_out_res; + wire _ghv_write_datas_247_ppm_out_res; + wire _ghv_write_datas_246_ppm_out_res; + wire _ghv_write_datas_245_ppm_out_res; + wire _ghv_write_datas_244_ppm_out_res; + wire _ghv_write_datas_243_ppm_out_res; + wire _ghv_write_datas_242_ppm_out_res; + wire _ghv_write_datas_241_ppm_out_res; + wire _ghv_write_datas_240_ppm_out_res; + wire _ghv_write_datas_239_ppm_out_res; + wire _ghv_write_datas_238_ppm_out_res; + wire _ghv_write_datas_237_ppm_out_res; + wire _ghv_write_datas_236_ppm_out_res; + wire _ghv_write_datas_235_ppm_out_res; + wire _ghv_write_datas_234_ppm_out_res; + wire _ghv_write_datas_233_ppm_out_res; + wire _ghv_write_datas_232_ppm_out_res; + wire _ghv_write_datas_231_ppm_out_res; + wire _ghv_write_datas_230_ppm_out_res; + wire _ghv_write_datas_229_ppm_out_res; + wire _ghv_write_datas_228_ppm_out_res; + wire _ghv_write_datas_227_ppm_out_res; + wire _ghv_write_datas_226_ppm_out_res; + wire _ghv_write_datas_225_ppm_out_res; + wire _ghv_write_datas_224_ppm_out_res; + wire _ghv_write_datas_223_ppm_out_res; + wire _ghv_write_datas_222_ppm_out_res; + wire _ghv_write_datas_221_ppm_out_res; + wire _ghv_write_datas_220_ppm_out_res; + wire _ghv_write_datas_219_ppm_out_res; + wire _ghv_write_datas_218_ppm_out_res; + wire _ghv_write_datas_217_ppm_out_res; + wire _ghv_write_datas_216_ppm_out_res; + wire _ghv_write_datas_215_ppm_out_res; + wire _ghv_write_datas_214_ppm_out_res; + wire _ghv_write_datas_213_ppm_out_res; + wire _ghv_write_datas_212_ppm_out_res; + wire _ghv_write_datas_211_ppm_out_res; + wire _ghv_write_datas_210_ppm_out_res; + wire _ghv_write_datas_209_ppm_out_res; + wire _ghv_write_datas_208_ppm_out_res; + wire _ghv_write_datas_207_ppm_out_res; + wire _ghv_write_datas_206_ppm_out_res; + wire _ghv_write_datas_205_ppm_out_res; + wire _ghv_write_datas_204_ppm_out_res; + wire _ghv_write_datas_203_ppm_out_res; + wire _ghv_write_datas_202_ppm_out_res; + wire _ghv_write_datas_201_ppm_out_res; + wire _ghv_write_datas_200_ppm_out_res; + wire _ghv_write_datas_199_ppm_out_res; + wire _ghv_write_datas_198_ppm_out_res; + wire _ghv_write_datas_197_ppm_out_res; + wire _ghv_write_datas_196_ppm_out_res; + wire _ghv_write_datas_195_ppm_out_res; + wire _ghv_write_datas_194_ppm_out_res; + wire _ghv_write_datas_193_ppm_out_res; + wire _ghv_write_datas_192_ppm_out_res; + wire _ghv_write_datas_191_ppm_out_res; + wire _ghv_write_datas_190_ppm_out_res; + wire _ghv_write_datas_189_ppm_out_res; + wire _ghv_write_datas_188_ppm_out_res; + wire _ghv_write_datas_187_ppm_out_res; + wire _ghv_write_datas_186_ppm_out_res; + wire _ghv_write_datas_185_ppm_out_res; + wire _ghv_write_datas_184_ppm_out_res; + wire _ghv_write_datas_183_ppm_out_res; + wire _ghv_write_datas_182_ppm_out_res; + wire _ghv_write_datas_181_ppm_out_res; + wire _ghv_write_datas_180_ppm_out_res; + wire _ghv_write_datas_179_ppm_out_res; + wire _ghv_write_datas_178_ppm_out_res; + wire _ghv_write_datas_177_ppm_out_res; + wire _ghv_write_datas_176_ppm_out_res; + wire _ghv_write_datas_175_ppm_out_res; + wire _ghv_write_datas_174_ppm_out_res; + wire _ghv_write_datas_173_ppm_out_res; + wire _ghv_write_datas_172_ppm_out_res; + wire _ghv_write_datas_171_ppm_out_res; + wire _ghv_write_datas_170_ppm_out_res; + wire _ghv_write_datas_169_ppm_out_res; + wire _ghv_write_datas_168_ppm_out_res; + wire _ghv_write_datas_167_ppm_out_res; + wire _ghv_write_datas_166_ppm_out_res; + wire _ghv_write_datas_165_ppm_out_res; + wire _ghv_write_datas_164_ppm_out_res; + wire _ghv_write_datas_163_ppm_out_res; + wire _ghv_write_datas_162_ppm_out_res; + wire _ghv_write_datas_161_ppm_out_res; + wire _ghv_write_datas_160_ppm_out_res; + wire _ghv_write_datas_159_ppm_out_res; + wire _ghv_write_datas_158_ppm_out_res; + wire _ghv_write_datas_157_ppm_out_res; + wire _ghv_write_datas_156_ppm_out_res; + wire _ghv_write_datas_155_ppm_out_res; + wire _ghv_write_datas_154_ppm_out_res; + wire _ghv_write_datas_153_ppm_out_res; + wire _ghv_write_datas_152_ppm_out_res; + wire _ghv_write_datas_151_ppm_out_res; + wire _ghv_write_datas_150_ppm_out_res; + wire _ghv_write_datas_149_ppm_out_res; + wire _ghv_write_datas_148_ppm_out_res; + wire _ghv_write_datas_147_ppm_out_res; + wire _ghv_write_datas_146_ppm_out_res; + wire _ghv_write_datas_145_ppm_out_res; + wire _ghv_write_datas_144_ppm_out_res; + wire _ghv_write_datas_143_ppm_out_res; + wire _ghv_write_datas_142_ppm_out_res; + wire _ghv_write_datas_141_ppm_out_res; + wire _ghv_write_datas_140_ppm_out_res; + wire _ghv_write_datas_139_ppm_out_res; + wire _ghv_write_datas_138_ppm_out_res; + wire _ghv_write_datas_137_ppm_out_res; + wire _ghv_write_datas_136_ppm_out_res; + wire _ghv_write_datas_135_ppm_out_res; + wire _ghv_write_datas_134_ppm_out_res; + wire _ghv_write_datas_133_ppm_out_res; + wire _ghv_write_datas_132_ppm_out_res; + wire _ghv_write_datas_131_ppm_out_res; + wire _ghv_write_datas_130_ppm_out_res; + wire _ghv_write_datas_129_ppm_out_res; + wire _ghv_write_datas_128_ppm_out_res; + wire _ghv_write_datas_127_ppm_out_res; + wire _ghv_write_datas_126_ppm_out_res; + wire _ghv_write_datas_125_ppm_out_res; + wire _ghv_write_datas_124_ppm_out_res; + wire _ghv_write_datas_123_ppm_out_res; + wire _ghv_write_datas_122_ppm_out_res; + wire _ghv_write_datas_121_ppm_out_res; + wire _ghv_write_datas_120_ppm_out_res; + wire _ghv_write_datas_119_ppm_out_res; + wire _ghv_write_datas_118_ppm_out_res; + wire _ghv_write_datas_117_ppm_out_res; + wire _ghv_write_datas_116_ppm_out_res; + wire _ghv_write_datas_115_ppm_out_res; + wire _ghv_write_datas_114_ppm_out_res; + wire _ghv_write_datas_113_ppm_out_res; + wire _ghv_write_datas_112_ppm_out_res; + wire _ghv_write_datas_111_ppm_out_res; + wire _ghv_write_datas_110_ppm_out_res; + wire _ghv_write_datas_109_ppm_out_res; + wire _ghv_write_datas_108_ppm_out_res; + wire _ghv_write_datas_107_ppm_out_res; + wire _ghv_write_datas_106_ppm_out_res; + wire _ghv_write_datas_105_ppm_out_res; + wire _ghv_write_datas_104_ppm_out_res; + wire _ghv_write_datas_103_ppm_out_res; + wire _ghv_write_datas_102_ppm_out_res; + wire _ghv_write_datas_101_ppm_out_res; + wire _ghv_write_datas_100_ppm_out_res; + wire _ghv_write_datas_99_ppm_out_res; + wire _ghv_write_datas_98_ppm_out_res; + wire _ghv_write_datas_97_ppm_out_res; + wire _ghv_write_datas_96_ppm_out_res; + wire _ghv_write_datas_95_ppm_out_res; + wire _ghv_write_datas_94_ppm_out_res; + wire _ghv_write_datas_93_ppm_out_res; + wire _ghv_write_datas_92_ppm_out_res; + wire _ghv_write_datas_91_ppm_out_res; + wire _ghv_write_datas_90_ppm_out_res; + wire _ghv_write_datas_89_ppm_out_res; + wire _ghv_write_datas_88_ppm_out_res; + wire _ghv_write_datas_87_ppm_out_res; + wire _ghv_write_datas_86_ppm_out_res; + wire _ghv_write_datas_85_ppm_out_res; + wire _ghv_write_datas_84_ppm_out_res; + wire _ghv_write_datas_83_ppm_out_res; + wire _ghv_write_datas_82_ppm_out_res; + wire _ghv_write_datas_81_ppm_out_res; + wire _ghv_write_datas_80_ppm_out_res; + wire _ghv_write_datas_79_ppm_out_res; + wire _ghv_write_datas_78_ppm_out_res; + wire _ghv_write_datas_77_ppm_out_res; + wire _ghv_write_datas_76_ppm_out_res; + wire _ghv_write_datas_75_ppm_out_res; + wire _ghv_write_datas_74_ppm_out_res; + wire _ghv_write_datas_73_ppm_out_res; + wire _ghv_write_datas_72_ppm_out_res; + wire _ghv_write_datas_71_ppm_out_res; + wire _ghv_write_datas_70_ppm_out_res; + wire _ghv_write_datas_69_ppm_out_res; + wire _ghv_write_datas_68_ppm_out_res; + wire _ghv_write_datas_67_ppm_out_res; + wire _ghv_write_datas_66_ppm_out_res; + wire _ghv_write_datas_65_ppm_out_res; + wire _ghv_write_datas_64_ppm_out_res; + wire _ghv_write_datas_63_ppm_out_res; + wire _ghv_write_datas_62_ppm_out_res; + wire _ghv_write_datas_61_ppm_out_res; + wire _ghv_write_datas_60_ppm_out_res; + wire _ghv_write_datas_59_ppm_out_res; + wire _ghv_write_datas_58_ppm_out_res; + wire _ghv_write_datas_57_ppm_out_res; + wire _ghv_write_datas_56_ppm_out_res; + wire _ghv_write_datas_55_ppm_out_res; + wire _ghv_write_datas_54_ppm_out_res; + wire _ghv_write_datas_53_ppm_out_res; + wire _ghv_write_datas_52_ppm_out_res; + wire _ghv_write_datas_51_ppm_out_res; + wire _ghv_write_datas_50_ppm_out_res; + wire _ghv_write_datas_49_ppm_out_res; + wire _ghv_write_datas_48_ppm_out_res; + wire _ghv_write_datas_47_ppm_out_res; + wire _ghv_write_datas_46_ppm_out_res; + wire _ghv_write_datas_45_ppm_out_res; + wire _ghv_write_datas_44_ppm_out_res; + wire _ghv_write_datas_43_ppm_out_res; + wire _ghv_write_datas_42_ppm_out_res; + wire _ghv_write_datas_41_ppm_out_res; + wire _ghv_write_datas_40_ppm_out_res; + wire _ghv_write_datas_39_ppm_out_res; + wire _ghv_write_datas_38_ppm_out_res; + wire _ghv_write_datas_37_ppm_out_res; + wire _ghv_write_datas_36_ppm_out_res; + wire _ghv_write_datas_35_ppm_out_res; + wire _ghv_write_datas_34_ppm_out_res; + wire _ghv_write_datas_33_ppm_out_res; + wire _ghv_write_datas_32_ppm_out_res; + wire _ghv_write_datas_31_ppm_out_res; + wire _ghv_write_datas_30_ppm_out_res; + wire _ghv_write_datas_29_ppm_out_res; + wire _ghv_write_datas_28_ppm_out_res; + wire _ghv_write_datas_27_ppm_out_res; + wire _ghv_write_datas_26_ppm_out_res; + wire _ghv_write_datas_25_ppm_out_res; + wire _ghv_write_datas_24_ppm_out_res; + wire _ghv_write_datas_23_ppm_out_res; + wire _ghv_write_datas_22_ppm_out_res; + wire _ghv_write_datas_21_ppm_out_res; + wire _ghv_write_datas_20_ppm_out_res; + wire _ghv_write_datas_19_ppm_out_res; + wire _ghv_write_datas_18_ppm_out_res; + wire _ghv_write_datas_17_ppm_out_res; + wire _ghv_write_datas_16_ppm_out_res; + wire _ghv_write_datas_15_ppm_out_res; + wire _ghv_write_datas_14_ppm_out_res; + wire _ghv_write_datas_13_ppm_out_res; + wire _ghv_write_datas_12_ppm_out_res; + wire _ghv_write_datas_11_ppm_out_res; + wire _ghv_write_datas_10_ppm_out_res; + wire _ghv_write_datas_9_ppm_out_res; + wire _ghv_write_datas_8_ppm_out_res; + wire _ghv_write_datas_7_ppm_out_res; + wire _ghv_write_datas_6_ppm_out_res; + wire _ghv_write_datas_5_ppm_out_res; + wire _ghv_write_datas_4_ppm_out_res; + wire _ghv_write_datas_3_ppm_out_res; + wire _ghv_write_datas_2_ppm_out_res; + wire _ghv_write_datas_1_ppm_out_res; + wire _ghv_write_datas_0_ppm_out_res; + wire [2:0] _s0_last_br_num_oh_dup_3_ppm_out_res; + wire [2:0] _s0_last_br_num_oh_dup_2_ppm_out_res; + wire [2:0] _s0_last_br_num_oh_dup_1_ppm_out_res; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; + wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; + wire _s0_ghist_ptr_dup_3_ppm_out_res_flag; + wire [7:0] _s0_ghist_ptr_dup_3_ppm_out_res_value; + wire _s0_ghist_ptr_dup_2_ppm_out_res_flag; + wire [7:0] _s0_ghist_ptr_dup_2_ppm_out_res_value; + wire _s0_ghist_ptr_dup_1_ppm_out_res_flag; + wire [7:0] _s0_ghist_ptr_dup_1_ppm_out_res_value; + wire _s0_ghist_ptr_dup_0_ppm_out_res_flag; + wire [7:0] _s0_ghist_ptr_dup_0_ppm_out_res_value; + wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; + wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; + wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; + wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; + wire [3:0] _s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; + wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; + wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; + wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; + wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; + wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; + wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; + wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; + wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; + wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; + wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; + wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; + wire [3:0] _s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; + wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; + wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; + wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; + wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; + wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; + wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; + wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; + wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; + wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; + wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; + wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; + wire [3:0] _s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; + wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; + wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; + wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; + wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; + wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; + wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; + wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; + wire [40:0] _s0_pc_dup_3_ppm_out_res; + wire [40:0] _s0_pc_dup_2_ppm_out_res; + wire [40:0] _s0_pc_dup_1_ppm_out_res; + wire [40:0] _s0_pc_dup_0_ppm_out_res; + wire [35:0] _reset_vector_delay_io_out; + wire [40:0] _predictors_io_out_s1_pc_0; + wire [40:0] _predictors_io_out_s1_pc_1; + wire [40:0] _predictors_io_out_s1_pc_2; + wire [40:0] _predictors_io_out_s1_pc_3; + wire _predictors_io_out_s1_full_pred_0_br_taken_mask_0; + wire _predictors_io_out_s1_full_pred_0_br_taken_mask_1; + wire _predictors_io_out_s1_full_pred_0_slot_valids_0; + wire _predictors_io_out_s1_full_pred_0_slot_valids_1; + wire [40:0] _predictors_io_out_s1_full_pred_0_targets_0; + wire [40:0] _predictors_io_out_s1_full_pred_0_targets_1; + wire [3:0] _predictors_io_out_s1_full_pred_0_offsets_0; + wire [3:0] _predictors_io_out_s1_full_pred_0_offsets_1; + wire [40:0] _predictors_io_out_s1_full_pred_0_fallThroughAddr; + wire _predictors_io_out_s1_full_pred_0_is_br_sharing; + wire _predictors_io_out_s1_full_pred_0_hit; + wire _predictors_io_out_s1_full_pred_1_br_taken_mask_0; + wire _predictors_io_out_s1_full_pred_1_br_taken_mask_1; + wire _predictors_io_out_s1_full_pred_1_slot_valids_0; + wire _predictors_io_out_s1_full_pred_1_slot_valids_1; + wire [40:0] _predictors_io_out_s1_full_pred_1_targets_0; + wire [40:0] _predictors_io_out_s1_full_pred_1_targets_1; + wire [3:0] _predictors_io_out_s1_full_pred_1_offsets_0; + wire [3:0] _predictors_io_out_s1_full_pred_1_offsets_1; + wire [40:0] _predictors_io_out_s1_full_pred_1_fallThroughAddr; + wire _predictors_io_out_s1_full_pred_1_is_br_sharing; + wire _predictors_io_out_s1_full_pred_1_hit; + wire _predictors_io_out_s1_full_pred_2_br_taken_mask_0; + wire _predictors_io_out_s1_full_pred_2_br_taken_mask_1; + wire _predictors_io_out_s1_full_pred_2_slot_valids_0; + wire _predictors_io_out_s1_full_pred_2_slot_valids_1; + wire [40:0] _predictors_io_out_s1_full_pred_2_targets_0; + wire [40:0] _predictors_io_out_s1_full_pred_2_targets_1; + wire [3:0] _predictors_io_out_s1_full_pred_2_offsets_0; + wire [3:0] _predictors_io_out_s1_full_pred_2_offsets_1; + wire [40:0] _predictors_io_out_s1_full_pred_2_fallThroughAddr; + wire _predictors_io_out_s1_full_pred_2_is_br_sharing; + wire _predictors_io_out_s1_full_pred_2_hit; + wire _predictors_io_out_s1_full_pred_3_br_taken_mask_0; + wire _predictors_io_out_s1_full_pred_3_br_taken_mask_1; + wire _predictors_io_out_s1_full_pred_3_slot_valids_0; + wire _predictors_io_out_s1_full_pred_3_slot_valids_1; + wire [40:0] _predictors_io_out_s1_full_pred_3_targets_0; + wire [40:0] _predictors_io_out_s1_full_pred_3_targets_1; + wire [3:0] _predictors_io_out_s1_full_pred_3_offsets_0; + wire [3:0] _predictors_io_out_s1_full_pred_3_offsets_1; + wire [40:0] _predictors_io_out_s1_full_pred_3_fallThroughAddr; + wire _predictors_io_out_s1_full_pred_3_is_br_sharing; + wire _predictors_io_out_s1_full_pred_3_hit; + wire [40:0] _predictors_io_out_s2_pc_0; + wire [40:0] _predictors_io_out_s2_pc_1; + wire [40:0] _predictors_io_out_s2_pc_2; + wire [40:0] _predictors_io_out_s2_pc_3; + wire _predictors_io_out_s2_full_pred_0_br_taken_mask_0; + wire _predictors_io_out_s2_full_pred_0_br_taken_mask_1; + wire _predictors_io_out_s2_full_pred_0_slot_valids_0; + wire _predictors_io_out_s2_full_pred_0_slot_valids_1; + wire [40:0] _predictors_io_out_s2_full_pred_0_targets_0; + wire [40:0] _predictors_io_out_s2_full_pred_0_targets_1; + wire [3:0] _predictors_io_out_s2_full_pred_0_offsets_0; + wire [3:0] _predictors_io_out_s2_full_pred_0_offsets_1; + wire [40:0] _predictors_io_out_s2_full_pred_0_fallThroughAddr; + wire _predictors_io_out_s2_full_pred_0_is_br_sharing; + wire _predictors_io_out_s2_full_pred_0_hit; + wire _predictors_io_out_s2_full_pred_1_br_taken_mask_0; + wire _predictors_io_out_s2_full_pred_1_br_taken_mask_1; + wire _predictors_io_out_s2_full_pred_1_slot_valids_0; + wire _predictors_io_out_s2_full_pred_1_slot_valids_1; + wire [40:0] _predictors_io_out_s2_full_pred_1_targets_0; + wire [40:0] _predictors_io_out_s2_full_pred_1_targets_1; + wire [3:0] _predictors_io_out_s2_full_pred_1_offsets_0; + wire [3:0] _predictors_io_out_s2_full_pred_1_offsets_1; + wire [40:0] _predictors_io_out_s2_full_pred_1_fallThroughAddr; + wire _predictors_io_out_s2_full_pred_1_is_br_sharing; + wire _predictors_io_out_s2_full_pred_1_hit; + wire _predictors_io_out_s2_full_pred_2_br_taken_mask_0; + wire _predictors_io_out_s2_full_pred_2_br_taken_mask_1; + wire _predictors_io_out_s2_full_pred_2_slot_valids_0; + wire _predictors_io_out_s2_full_pred_2_slot_valids_1; + wire [40:0] _predictors_io_out_s2_full_pred_2_targets_0; + wire [40:0] _predictors_io_out_s2_full_pred_2_targets_1; + wire [3:0] _predictors_io_out_s2_full_pred_2_offsets_0; + wire [3:0] _predictors_io_out_s2_full_pred_2_offsets_1; + wire [40:0] _predictors_io_out_s2_full_pred_2_fallThroughAddr; + wire _predictors_io_out_s2_full_pred_2_is_br_sharing; + wire _predictors_io_out_s2_full_pred_2_hit; + wire _predictors_io_out_s2_full_pred_3_br_taken_mask_0; + wire _predictors_io_out_s2_full_pred_3_br_taken_mask_1; + wire _predictors_io_out_s2_full_pred_3_slot_valids_0; + wire _predictors_io_out_s2_full_pred_3_slot_valids_1; + wire [40:0] _predictors_io_out_s2_full_pred_3_targets_0; + wire [40:0] _predictors_io_out_s2_full_pred_3_targets_1; + wire [3:0] _predictors_io_out_s2_full_pred_3_offsets_0; + wire [3:0] _predictors_io_out_s2_full_pred_3_offsets_1; + wire [40:0] _predictors_io_out_s2_full_pred_3_fallThroughAddr; + wire _predictors_io_out_s2_full_pred_3_is_br_sharing; + wire _predictors_io_out_s2_full_pred_3_hit; + wire [40:0] _predictors_io_out_s3_pc_0; + wire [40:0] _predictors_io_out_s3_pc_1; + wire [40:0] _predictors_io_out_s3_pc_2; + wire [40:0] _predictors_io_out_s3_pc_3; + wire _predictors_io_out_s3_full_pred_0_br_taken_mask_0; + wire _predictors_io_out_s3_full_pred_0_br_taken_mask_1; + wire _predictors_io_out_s3_full_pred_0_slot_valids_0; + wire _predictors_io_out_s3_full_pred_0_slot_valids_1; + wire [40:0] _predictors_io_out_s3_full_pred_0_targets_0; + wire [40:0] _predictors_io_out_s3_full_pred_0_targets_1; + wire [40:0] _predictors_io_out_s3_full_pred_0_fallThroughAddr; + wire _predictors_io_out_s3_full_pred_0_fallThroughErr; + wire _predictors_io_out_s3_full_pred_0_is_br_sharing; + wire _predictors_io_out_s3_full_pred_0_hit; + wire _predictors_io_out_s3_full_pred_1_br_taken_mask_0; + wire _predictors_io_out_s3_full_pred_1_br_taken_mask_1; + wire _predictors_io_out_s3_full_pred_1_slot_valids_0; + wire _predictors_io_out_s3_full_pred_1_slot_valids_1; + wire [40:0] _predictors_io_out_s3_full_pred_1_targets_0; + wire [40:0] _predictors_io_out_s3_full_pred_1_targets_1; + wire [40:0] _predictors_io_out_s3_full_pred_1_fallThroughAddr; + wire _predictors_io_out_s3_full_pred_1_fallThroughErr; + wire _predictors_io_out_s3_full_pred_1_is_br_sharing; + wire _predictors_io_out_s3_full_pred_1_hit; + wire _predictors_io_out_s3_full_pred_2_br_taken_mask_0; + wire _predictors_io_out_s3_full_pred_2_br_taken_mask_1; + wire _predictors_io_out_s3_full_pred_2_slot_valids_0; + wire _predictors_io_out_s3_full_pred_2_slot_valids_1; + wire [40:0] _predictors_io_out_s3_full_pred_2_targets_0; + wire [40:0] _predictors_io_out_s3_full_pred_2_targets_1; + wire [40:0] _predictors_io_out_s3_full_pred_2_fallThroughAddr; + wire _predictors_io_out_s3_full_pred_2_fallThroughErr; + wire _predictors_io_out_s3_full_pred_2_is_br_sharing; + wire _predictors_io_out_s3_full_pred_2_hit; + wire _predictors_io_out_s3_full_pred_3_br_taken_mask_0; + wire _predictors_io_out_s3_full_pred_3_br_taken_mask_1; + wire _predictors_io_out_s3_full_pred_3_slot_valids_0; + wire _predictors_io_out_s3_full_pred_3_slot_valids_1; + wire [40:0] _predictors_io_out_s3_full_pred_3_targets_0; + wire [40:0] _predictors_io_out_s3_full_pred_3_targets_1; + wire [40:0] _predictors_io_out_s3_full_pred_3_fallThroughAddr; + wire _predictors_io_out_s3_full_pred_3_fallThroughErr; + wire _predictors_io_out_s3_full_pred_3_is_br_sharing; + wire _predictors_io_out_s3_full_pred_3_hit; + wire _predictors_io_s1_ready; + wire [5:0] _predictors_io_perf_0_value; + wire [5:0] _predictors_io_perf_1_value; + wire [5:0] _predictors_io_perf_2_value; + wire [5:0] _predictors_io_perf_3_value; + wire [5:0] _predictors_io_perf_4_value; + wire [5:0] _predictors_io_perf_5_value; + wire [5:0] _predictors_io_perf_6_value; + wire _ctrl_delay_io_out_ubtb_enable; + wire _ctrl_delay_io_out_btb_enable; + wire _ctrl_delay_io_out_tage_enable; + wire _ctrl_delay_io_out_sc_enable; + wire _ctrl_delay_io_out_ras_enable; + reg s1_valid_dup_3; + reg s2_valid_dup_3; + reg s3_valid_dup_3; + reg [40:0] s0_pc_reg_dup_0; + reg [40:0] s0_pc_reg_dup_1; + reg [40:0] s0_pc_reg_dup_2; + reg [40:0] s0_pc_reg_dup_3; + reg REG; + reg REG_1; + reg [10:0] s0_folded_gh_reg_dup_1_hist_17_folded_hist; + reg [10:0] s0_folded_gh_reg_dup_1_hist_16_folded_hist; + reg [6:0] s0_folded_gh_reg_dup_1_hist_15_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_1_hist_14_folded_hist; + reg [8:0] s0_folded_gh_reg_dup_1_hist_13_folded_hist; + reg [3:0] s0_folded_gh_reg_dup_1_hist_12_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_1_hist_11_folded_hist; + reg [8:0] s0_folded_gh_reg_dup_1_hist_10_folded_hist; + reg [6:0] s0_folded_gh_reg_dup_1_hist_9_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_1_hist_8_folded_hist; + reg [6:0] s0_folded_gh_reg_dup_1_hist_7_folded_hist; + reg [8:0] s0_folded_gh_reg_dup_1_hist_6_folded_hist; + reg [6:0] s0_folded_gh_reg_dup_1_hist_5_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_1_hist_4_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_1_hist_3_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_1_hist_2_folded_hist; + reg [10:0] s0_folded_gh_reg_dup_1_hist_1_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_1_hist_0_folded_hist; + reg [10:0] s0_folded_gh_reg_dup_2_hist_17_folded_hist; + reg [10:0] s0_folded_gh_reg_dup_2_hist_16_folded_hist; + reg [6:0] s0_folded_gh_reg_dup_2_hist_15_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_2_hist_14_folded_hist; + reg [8:0] s0_folded_gh_reg_dup_2_hist_13_folded_hist; + reg [3:0] s0_folded_gh_reg_dup_2_hist_12_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_2_hist_11_folded_hist; + reg [8:0] s0_folded_gh_reg_dup_2_hist_10_folded_hist; + reg [6:0] s0_folded_gh_reg_dup_2_hist_9_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_2_hist_8_folded_hist; + reg [6:0] s0_folded_gh_reg_dup_2_hist_7_folded_hist; + reg [8:0] s0_folded_gh_reg_dup_2_hist_6_folded_hist; + reg [6:0] s0_folded_gh_reg_dup_2_hist_5_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_2_hist_4_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_2_hist_3_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_2_hist_2_folded_hist; + reg [10:0] s0_folded_gh_reg_dup_2_hist_1_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_2_hist_0_folded_hist; + reg [10:0] s0_folded_gh_reg_dup_3_hist_17_folded_hist; + reg [10:0] s0_folded_gh_reg_dup_3_hist_16_folded_hist; + reg [6:0] s0_folded_gh_reg_dup_3_hist_15_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_3_hist_14_folded_hist; + reg [8:0] s0_folded_gh_reg_dup_3_hist_13_folded_hist; + reg [3:0] s0_folded_gh_reg_dup_3_hist_12_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_3_hist_11_folded_hist; + reg [8:0] s0_folded_gh_reg_dup_3_hist_10_folded_hist; + reg [6:0] s0_folded_gh_reg_dup_3_hist_9_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_3_hist_8_folded_hist; + reg [6:0] s0_folded_gh_reg_dup_3_hist_7_folded_hist; + reg [8:0] s0_folded_gh_reg_dup_3_hist_6_folded_hist; + reg [6:0] s0_folded_gh_reg_dup_3_hist_5_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_3_hist_4_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_3_hist_3_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_3_hist_2_folded_hist; + reg [10:0] s0_folded_gh_reg_dup_3_hist_1_folded_hist; + reg [7:0] s0_folded_gh_reg_dup_3_hist_0_folded_hist; + reg [10:0] s1_folded_gh_dup_1_hist_17_folded_hist; + reg [10:0] s1_folded_gh_dup_1_hist_16_folded_hist; + reg [6:0] s1_folded_gh_dup_1_hist_15_folded_hist; + reg [7:0] s1_folded_gh_dup_1_hist_14_folded_hist; + reg [8:0] s1_folded_gh_dup_1_hist_13_folded_hist; + reg [3:0] s1_folded_gh_dup_1_hist_12_folded_hist; + reg [7:0] s1_folded_gh_dup_1_hist_11_folded_hist; + reg [8:0] s1_folded_gh_dup_1_hist_10_folded_hist; + reg [6:0] s1_folded_gh_dup_1_hist_9_folded_hist; + reg [7:0] s1_folded_gh_dup_1_hist_8_folded_hist; + reg [6:0] s1_folded_gh_dup_1_hist_7_folded_hist; + reg [8:0] s1_folded_gh_dup_1_hist_6_folded_hist; + reg [6:0] s1_folded_gh_dup_1_hist_5_folded_hist; + reg [7:0] s1_folded_gh_dup_1_hist_4_folded_hist; + reg [7:0] s1_folded_gh_dup_1_hist_3_folded_hist; + reg [7:0] s1_folded_gh_dup_1_hist_2_folded_hist; + reg [10:0] s1_folded_gh_dup_1_hist_1_folded_hist; + reg [7:0] s1_folded_gh_dup_1_hist_0_folded_hist; + reg [10:0] s1_folded_gh_dup_2_hist_17_folded_hist; + reg [10:0] s1_folded_gh_dup_2_hist_16_folded_hist; + reg [6:0] s1_folded_gh_dup_2_hist_15_folded_hist; + reg [7:0] s1_folded_gh_dup_2_hist_14_folded_hist; + reg [8:0] s1_folded_gh_dup_2_hist_13_folded_hist; + reg [3:0] s1_folded_gh_dup_2_hist_12_folded_hist; + reg [7:0] s1_folded_gh_dup_2_hist_11_folded_hist; + reg [8:0] s1_folded_gh_dup_2_hist_10_folded_hist; + reg [6:0] s1_folded_gh_dup_2_hist_9_folded_hist; + reg [7:0] s1_folded_gh_dup_2_hist_8_folded_hist; + reg [6:0] s1_folded_gh_dup_2_hist_7_folded_hist; + reg [8:0] s1_folded_gh_dup_2_hist_6_folded_hist; + reg [6:0] s1_folded_gh_dup_2_hist_5_folded_hist; + reg [7:0] s1_folded_gh_dup_2_hist_4_folded_hist; + reg [7:0] s1_folded_gh_dup_2_hist_3_folded_hist; + reg [7:0] s1_folded_gh_dup_2_hist_2_folded_hist; + reg [10:0] s1_folded_gh_dup_2_hist_1_folded_hist; + reg [7:0] s1_folded_gh_dup_2_hist_0_folded_hist; + reg [10:0] s1_folded_gh_dup_3_hist_17_folded_hist; + reg [10:0] s1_folded_gh_dup_3_hist_16_folded_hist; + reg [6:0] s1_folded_gh_dup_3_hist_15_folded_hist; + reg [7:0] s1_folded_gh_dup_3_hist_14_folded_hist; + reg [8:0] s1_folded_gh_dup_3_hist_13_folded_hist; + reg [3:0] s1_folded_gh_dup_3_hist_12_folded_hist; + reg [7:0] s1_folded_gh_dup_3_hist_11_folded_hist; + reg [8:0] s1_folded_gh_dup_3_hist_10_folded_hist; + reg [6:0] s1_folded_gh_dup_3_hist_9_folded_hist; + reg [7:0] s1_folded_gh_dup_3_hist_8_folded_hist; + reg [6:0] s1_folded_gh_dup_3_hist_7_folded_hist; + reg [8:0] s1_folded_gh_dup_3_hist_6_folded_hist; + reg [6:0] s1_folded_gh_dup_3_hist_5_folded_hist; + reg [7:0] s1_folded_gh_dup_3_hist_4_folded_hist; + reg [7:0] s1_folded_gh_dup_3_hist_3_folded_hist; + reg [7:0] s1_folded_gh_dup_3_hist_2_folded_hist; + reg [10:0] s1_folded_gh_dup_3_hist_1_folded_hist; + reg [7:0] s1_folded_gh_dup_3_hist_0_folded_hist; + reg [10:0] s2_folded_gh_dup_1_hist_17_folded_hist; + reg [10:0] s2_folded_gh_dup_1_hist_16_folded_hist; + reg [6:0] s2_folded_gh_dup_1_hist_15_folded_hist; + reg [7:0] s2_folded_gh_dup_1_hist_14_folded_hist; + reg [8:0] s2_folded_gh_dup_1_hist_13_folded_hist; + reg [3:0] s2_folded_gh_dup_1_hist_12_folded_hist; + reg [7:0] s2_folded_gh_dup_1_hist_11_folded_hist; + reg [8:0] s2_folded_gh_dup_1_hist_10_folded_hist; + reg [6:0] s2_folded_gh_dup_1_hist_9_folded_hist; + reg [7:0] s2_folded_gh_dup_1_hist_8_folded_hist; + reg [6:0] s2_folded_gh_dup_1_hist_7_folded_hist; + reg [8:0] s2_folded_gh_dup_1_hist_6_folded_hist; + reg [6:0] s2_folded_gh_dup_1_hist_5_folded_hist; + reg [7:0] s2_folded_gh_dup_1_hist_4_folded_hist; + reg [7:0] s2_folded_gh_dup_1_hist_3_folded_hist; + reg [7:0] s2_folded_gh_dup_1_hist_2_folded_hist; + reg [10:0] s2_folded_gh_dup_1_hist_1_folded_hist; + reg [7:0] s2_folded_gh_dup_1_hist_0_folded_hist; + reg [10:0] s2_folded_gh_dup_2_hist_17_folded_hist; + reg [10:0] s2_folded_gh_dup_2_hist_16_folded_hist; + reg [6:0] s2_folded_gh_dup_2_hist_15_folded_hist; + reg [7:0] s2_folded_gh_dup_2_hist_14_folded_hist; + reg [8:0] s2_folded_gh_dup_2_hist_13_folded_hist; + reg [3:0] s2_folded_gh_dup_2_hist_12_folded_hist; + reg [7:0] s2_folded_gh_dup_2_hist_11_folded_hist; + reg [8:0] s2_folded_gh_dup_2_hist_10_folded_hist; + reg [6:0] s2_folded_gh_dup_2_hist_9_folded_hist; + reg [7:0] s2_folded_gh_dup_2_hist_8_folded_hist; + reg [6:0] s2_folded_gh_dup_2_hist_7_folded_hist; + reg [8:0] s2_folded_gh_dup_2_hist_6_folded_hist; + reg [6:0] s2_folded_gh_dup_2_hist_5_folded_hist; + reg [7:0] s2_folded_gh_dup_2_hist_4_folded_hist; + reg [7:0] s2_folded_gh_dup_2_hist_3_folded_hist; + reg [7:0] s2_folded_gh_dup_2_hist_2_folded_hist; + reg [10:0] s2_folded_gh_dup_2_hist_1_folded_hist; + reg [7:0] s2_folded_gh_dup_2_hist_0_folded_hist; + reg [10:0] s2_folded_gh_dup_3_hist_17_folded_hist; + reg [10:0] s2_folded_gh_dup_3_hist_16_folded_hist; + reg [6:0] s2_folded_gh_dup_3_hist_15_folded_hist; + reg [7:0] s2_folded_gh_dup_3_hist_14_folded_hist; + reg [8:0] s2_folded_gh_dup_3_hist_13_folded_hist; + reg [3:0] s2_folded_gh_dup_3_hist_12_folded_hist; + reg [7:0] s2_folded_gh_dup_3_hist_11_folded_hist; + reg [8:0] s2_folded_gh_dup_3_hist_10_folded_hist; + reg [6:0] s2_folded_gh_dup_3_hist_9_folded_hist; + reg [7:0] s2_folded_gh_dup_3_hist_8_folded_hist; + reg [6:0] s2_folded_gh_dup_3_hist_7_folded_hist; + reg [8:0] s2_folded_gh_dup_3_hist_6_folded_hist; + reg [6:0] s2_folded_gh_dup_3_hist_5_folded_hist; + reg [7:0] s2_folded_gh_dup_3_hist_4_folded_hist; + reg [7:0] s2_folded_gh_dup_3_hist_3_folded_hist; + reg [7:0] s2_folded_gh_dup_3_hist_2_folded_hist; + reg [10:0] s2_folded_gh_dup_3_hist_1_folded_hist; + reg [7:0] s2_folded_gh_dup_3_hist_0_folded_hist; + reg [10:0] s3_folded_gh_dup_1_hist_17_folded_hist; + reg [10:0] s3_folded_gh_dup_1_hist_16_folded_hist; + reg [6:0] s3_folded_gh_dup_1_hist_15_folded_hist; + reg [7:0] s3_folded_gh_dup_1_hist_14_folded_hist; + reg [8:0] s3_folded_gh_dup_1_hist_13_folded_hist; + reg [3:0] s3_folded_gh_dup_1_hist_12_folded_hist; + reg [7:0] s3_folded_gh_dup_1_hist_11_folded_hist; + reg [8:0] s3_folded_gh_dup_1_hist_10_folded_hist; + reg [6:0] s3_folded_gh_dup_1_hist_9_folded_hist; + reg [7:0] s3_folded_gh_dup_1_hist_8_folded_hist; + reg [6:0] s3_folded_gh_dup_1_hist_7_folded_hist; + reg [8:0] s3_folded_gh_dup_1_hist_6_folded_hist; + reg [6:0] s3_folded_gh_dup_1_hist_5_folded_hist; + reg [7:0] s3_folded_gh_dup_1_hist_4_folded_hist; + reg [7:0] s3_folded_gh_dup_1_hist_3_folded_hist; + reg [7:0] s3_folded_gh_dup_1_hist_2_folded_hist; + reg [10:0] s3_folded_gh_dup_1_hist_1_folded_hist; + reg [7:0] s3_folded_gh_dup_1_hist_0_folded_hist; + reg [10:0] s3_folded_gh_dup_2_hist_17_folded_hist; + reg [10:0] s3_folded_gh_dup_2_hist_16_folded_hist; + reg [6:0] s3_folded_gh_dup_2_hist_15_folded_hist; + reg [7:0] s3_folded_gh_dup_2_hist_14_folded_hist; + reg [8:0] s3_folded_gh_dup_2_hist_13_folded_hist; + reg [3:0] s3_folded_gh_dup_2_hist_12_folded_hist; + reg [7:0] s3_folded_gh_dup_2_hist_11_folded_hist; + reg [8:0] s3_folded_gh_dup_2_hist_10_folded_hist; + reg [6:0] s3_folded_gh_dup_2_hist_9_folded_hist; + reg [7:0] s3_folded_gh_dup_2_hist_8_folded_hist; + reg [6:0] s3_folded_gh_dup_2_hist_7_folded_hist; + reg [8:0] s3_folded_gh_dup_2_hist_6_folded_hist; + reg [6:0] s3_folded_gh_dup_2_hist_5_folded_hist; + reg [7:0] s3_folded_gh_dup_2_hist_4_folded_hist; + reg [7:0] s3_folded_gh_dup_2_hist_3_folded_hist; + reg [7:0] s3_folded_gh_dup_2_hist_2_folded_hist; + reg [10:0] s3_folded_gh_dup_2_hist_1_folded_hist; + reg [7:0] s3_folded_gh_dup_2_hist_0_folded_hist; + reg [10:0] s3_folded_gh_dup_3_hist_17_folded_hist; + reg [10:0] s3_folded_gh_dup_3_hist_16_folded_hist; + reg [6:0] s3_folded_gh_dup_3_hist_15_folded_hist; + reg [7:0] s3_folded_gh_dup_3_hist_14_folded_hist; + reg [8:0] s3_folded_gh_dup_3_hist_13_folded_hist; + reg [3:0] s3_folded_gh_dup_3_hist_12_folded_hist; + reg [7:0] s3_folded_gh_dup_3_hist_11_folded_hist; + reg [8:0] s3_folded_gh_dup_3_hist_10_folded_hist; + reg [6:0] s3_folded_gh_dup_3_hist_9_folded_hist; + reg [7:0] s3_folded_gh_dup_3_hist_8_folded_hist; + reg [6:0] s3_folded_gh_dup_3_hist_7_folded_hist; + reg [8:0] s3_folded_gh_dup_3_hist_6_folded_hist; + reg [6:0] s3_folded_gh_dup_3_hist_5_folded_hist; + reg [7:0] s3_folded_gh_dup_3_hist_4_folded_hist; + reg [7:0] s3_folded_gh_dup_3_hist_3_folded_hist; + reg [7:0] s3_folded_gh_dup_3_hist_2_folded_hist; + reg [10:0] s3_folded_gh_dup_3_hist_1_folded_hist; + reg [7:0] s3_folded_gh_dup_3_hist_0_folded_hist; + reg [2:0] s0_last_br_num_oh_reg_dup_1; + reg [2:0] s0_last_br_num_oh_reg_dup_2; + reg [2:0] s0_last_br_num_oh_reg_dup_3; + reg [2:0] s1_last_br_num_oh_dup_1; + reg [2:0] s1_last_br_num_oh_dup_2; + reg [2:0] s1_last_br_num_oh_dup_3; + reg [2:0] s2_last_br_num_oh_dup_1; + reg [2:0] s2_last_br_num_oh_dup_2; + reg [2:0] s2_last_br_num_oh_dup_3; + reg [2:0] s3_last_br_num_oh_dup_1; + reg [2:0] s3_last_br_num_oh_dup_2; + reg [2:0] s3_last_br_num_oh_dup_3; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2; + reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; + reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; + reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; + reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; + reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; + reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; + reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; + reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; + reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; + reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; + reg ghv_0; + reg ghv_1; + reg ghv_2; + reg ghv_3; + reg ghv_4; + reg ghv_5; + reg ghv_6; + reg ghv_7; + reg ghv_8; + reg ghv_9; + reg ghv_10; + reg ghv_11; + reg ghv_12; + reg ghv_13; + reg ghv_14; + reg ghv_15; + reg ghv_16; + reg ghv_17; + reg ghv_18; + reg ghv_19; + reg ghv_20; + reg ghv_21; + reg ghv_22; + reg ghv_23; + reg ghv_24; + reg ghv_25; + reg ghv_26; + reg ghv_27; + reg ghv_28; + reg ghv_29; + reg ghv_30; + reg ghv_31; + reg ghv_32; + reg ghv_33; + reg ghv_34; + reg ghv_35; + reg ghv_36; + reg ghv_37; + reg ghv_38; + reg ghv_39; + reg ghv_40; + reg ghv_41; + reg ghv_42; + reg ghv_43; + reg ghv_44; + reg ghv_45; + reg ghv_46; + reg ghv_47; + reg ghv_48; + reg ghv_49; + reg ghv_50; + reg ghv_51; + reg ghv_52; + reg ghv_53; + reg ghv_54; + reg ghv_55; + reg ghv_56; + reg ghv_57; + reg ghv_58; + reg ghv_59; + reg ghv_60; + reg ghv_61; + reg ghv_62; + reg ghv_63; + reg ghv_64; + reg ghv_65; + reg ghv_66; + reg ghv_67; + reg ghv_68; + reg ghv_69; + reg ghv_70; + reg ghv_71; + reg ghv_72; + reg ghv_73; + reg ghv_74; + reg ghv_75; + reg ghv_76; + reg ghv_77; + reg ghv_78; + reg ghv_79; + reg ghv_80; + reg ghv_81; + reg ghv_82; + reg ghv_83; + reg ghv_84; + reg ghv_85; + reg ghv_86; + reg ghv_87; + reg ghv_88; + reg ghv_89; + reg ghv_90; + reg ghv_91; + reg ghv_92; + reg ghv_93; + reg ghv_94; + reg ghv_95; + reg ghv_96; + reg ghv_97; + reg ghv_98; + reg ghv_99; + reg ghv_100; + reg ghv_101; + reg ghv_102; + reg ghv_103; + reg ghv_104; + reg ghv_105; + reg ghv_106; + reg ghv_107; + reg ghv_108; + reg ghv_109; + reg ghv_110; + reg ghv_111; + reg ghv_112; + reg ghv_113; + reg ghv_114; + reg ghv_115; + reg ghv_116; + reg ghv_117; + reg ghv_118; + reg ghv_119; + reg ghv_120; + reg ghv_121; + reg ghv_122; + reg ghv_123; + reg ghv_124; + reg ghv_125; + reg ghv_126; + reg ghv_127; + reg ghv_128; + reg ghv_129; + reg ghv_130; + reg ghv_131; + reg ghv_132; + reg ghv_133; + reg ghv_134; + reg ghv_135; + reg ghv_136; + reg ghv_137; + reg ghv_138; + reg ghv_139; + reg ghv_140; + reg ghv_141; + reg ghv_142; + reg ghv_143; + reg ghv_144; + reg ghv_145; + reg ghv_146; + reg ghv_147; + reg ghv_148; + reg ghv_149; + reg ghv_150; + reg ghv_151; + reg ghv_152; + reg ghv_153; + reg ghv_154; + reg ghv_155; + reg ghv_156; + reg ghv_157; + reg ghv_158; + reg ghv_159; + reg ghv_160; + reg ghv_161; + reg ghv_162; + reg ghv_163; + reg ghv_164; + reg ghv_165; + reg ghv_166; + reg ghv_167; + reg ghv_168; + reg ghv_169; + reg ghv_170; + reg ghv_171; + reg ghv_172; + reg ghv_173; + reg ghv_174; + reg ghv_175; + reg ghv_176; + reg ghv_177; + reg ghv_178; + reg ghv_179; + reg ghv_180; + reg ghv_181; + reg ghv_182; + reg ghv_183; + reg ghv_184; + reg ghv_185; + reg ghv_186; + reg ghv_187; + reg ghv_188; + reg ghv_189; + reg ghv_190; + reg ghv_191; + reg ghv_192; + reg ghv_193; + reg ghv_194; + reg ghv_195; + reg ghv_196; + reg ghv_197; + reg ghv_198; + reg ghv_199; + reg ghv_200; + reg ghv_201; + reg ghv_202; + reg ghv_203; + reg ghv_204; + reg ghv_205; + reg ghv_206; + reg ghv_207; + reg ghv_208; + reg ghv_209; + reg ghv_210; + reg ghv_211; + reg ghv_212; + reg ghv_213; + reg ghv_214; + reg ghv_215; + reg ghv_216; + reg ghv_217; + reg ghv_218; + reg ghv_219; + reg ghv_220; + reg ghv_221; + reg ghv_222; + reg ghv_223; + reg ghv_224; + reg ghv_225; + reg ghv_226; + reg ghv_227; + reg ghv_228; + reg ghv_229; + reg ghv_230; + reg ghv_231; + reg ghv_232; + reg ghv_233; + reg ghv_234; + reg ghv_235; + reg ghv_236; + reg ghv_237; + reg ghv_238; + reg ghv_239; + reg ghv_240; + reg ghv_241; + reg ghv_242; + reg ghv_243; + reg ghv_244; + reg ghv_245; + reg ghv_246; + reg ghv_247; + reg ghv_248; + reg ghv_249; + reg ghv_250; + reg ghv_251; + reg ghv_252; + reg ghv_253; + reg ghv_254; + reg ghv_255; + reg s0_ghist_ptr_reg_dup_0_flag; + reg [7:0] s0_ghist_ptr_reg_dup_0_value; + reg s0_ghist_ptr_reg_dup_1_flag; + reg [7:0] s0_ghist_ptr_reg_dup_1_value; + reg s0_ghist_ptr_reg_dup_2_flag; + reg [7:0] s0_ghist_ptr_reg_dup_2_value; + reg s0_ghist_ptr_reg_dup_3_flag; + reg [7:0] s0_ghist_ptr_reg_dup_3_value; + reg s1_ghist_ptr_dup_0_flag; + reg [7:0] s1_ghist_ptr_dup_0_value; + reg s1_ghist_ptr_dup_1_flag; + reg [7:0] s1_ghist_ptr_dup_1_value; + reg s1_ghist_ptr_dup_2_flag; + reg [7:0] s1_ghist_ptr_dup_2_value; + reg s1_ghist_ptr_dup_3_flag; + reg [7:0] s1_ghist_ptr_dup_3_value; + reg s2_ghist_ptr_dup_0_flag; + reg [7:0] s2_ghist_ptr_dup_0_value; + reg s2_ghist_ptr_dup_1_flag; + reg [7:0] s2_ghist_ptr_dup_1_value; + reg s2_ghist_ptr_dup_2_flag; + reg [7:0] s2_ghist_ptr_dup_2_value; + reg s2_ghist_ptr_dup_3_flag; + reg [7:0] s2_ghist_ptr_dup_3_value; + reg s3_ghist_ptr_dup_0_flag; + reg [7:0] s3_ghist_ptr_dup_0_value; + reg s3_ghist_ptr_dup_1_flag; + reg [7:0] s3_ghist_ptr_dup_1_value; + reg s3_ghist_ptr_dup_2_flag; + reg [7:0] s3_ghist_ptr_dup_2_value; + reg s3_ghist_ptr_dup_3_flag; + reg [7:0] s3_ghist_ptr_dup_3_value; + reg do_redirect_dup_next_valid_last_r; + reg do_redirect_dup_next_bits_r_level; + reg [40:0] do_redirect_dup_next_bits_r_cfiUpdate_pc; + reg do_redirect_dup_next_bits_r_cfiUpdate_pd_isRVC; + reg do_redirect_dup_next_bits_r_cfiUpdate_pd_isCall; + reg do_redirect_dup_next_bits_r_cfiUpdate_pd_isRet; + reg [3:0] do_redirect_dup_next_bits_r_cfiUpdate_ssp; + reg [1:0] do_redirect_dup_next_bits_r_cfiUpdate_sctr; + reg do_redirect_dup_next_bits_r_cfiUpdate_TOSW_flag; + reg [4:0] do_redirect_dup_next_bits_r_cfiUpdate_TOSW_value; + reg do_redirect_dup_next_bits_r_cfiUpdate_TOSR_flag; + reg [4:0] do_redirect_dup_next_bits_r_cfiUpdate_TOSR_value; + reg do_redirect_dup_next_bits_r_cfiUpdate_NOS_flag; + reg [4:0] do_redirect_dup_next_bits_r_cfiUpdate_NOS_value; + reg [10:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist; + reg [10:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist; + reg [6:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist; + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist; + reg [8:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist; + reg [3:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist; + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist; + reg [8:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist; + reg [6:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist; + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist; + reg [6:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist; + reg [8:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist; + reg [6:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist; + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist; + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist; + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist; + reg [10:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist; + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2; + reg do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_3; + reg [2:0] do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH; + reg do_redirect_dup_next_bits_r_cfiUpdate_histPtr_flag; + reg [7:0] do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value; + reg [40:0] do_redirect_dup_next_bits_r_cfiUpdate_target; + reg do_redirect_dup_next_bits_r_cfiUpdate_taken; + reg [1:0] do_redirect_dup_next_bits_r_cfiUpdate_shift; + reg do_redirect_dup_next_bits_r_cfiUpdate_addIntoHist; + wire s2_flush_dup_3 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_3; + wire s0_fire_dup_0 = + _predictors_io_s1_ready & (s1_fire_dup_0 | ~s1_valid_dup_3); + wire s0_fire_dup_1 = + _predictors_io_s1_ready & (s1_fire_dup_1 | ~s1_valid_dup_3); + wire s0_fire_dup_2 = + _predictors_io_s1_ready & (s1_fire_dup_2 | ~s1_valid_dup_3); + wire s0_fire_dup_3 = + _predictors_io_s1_ready & (s1_fire_dup_3 | ~s1_valid_dup_3); + assign s1_fire_dup_0 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; + assign s1_fire_dup_1 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; + assign s1_fire_dup_2 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; + assign s1_fire_dup_3 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; + wire [8:0] _GEN = {s1_ghist_ptr_dup_0_flag, s1_ghist_ptr_dup_0_value}; + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1 = + 9'(_GEN - 9'h100); + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6 = + 9'(_GEN + 9'hFF); + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11 = + 9'(_GEN + 9'hFE); + wire [8:0] _GEN_0 = {s1_ghist_ptr_dup_1_flag, s1_ghist_ptr_dup_1_value}; + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16 = + 9'(_GEN_0 - 9'h100); + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21 = + 9'(_GEN_0 + 9'hFF); + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26 = + 9'(_GEN_0 + 9'hFE); + wire [8:0] _GEN_1 = {s1_ghist_ptr_dup_2_flag, s1_ghist_ptr_dup_2_value}; + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31 = + 9'(_GEN_1 - 9'h100); + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36 = + 9'(_GEN_1 + 9'hFF); + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41 = + 9'(_GEN_1 + 9'hFE); + wire [8:0] _GEN_2 = {s1_ghist_ptr_dup_3_flag, s1_ghist_ptr_dup_3_value}; + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46 = + 9'(_GEN_2 - 9'h100); + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51 = + 9'(_GEN_2 + 9'hFF); + wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56 = + 9'(_GEN_2 + 9'hFE); + wire _s1_ghv_wdatas_T_190528 = + _predictors_io_out_s1_full_pred_0_slot_valids_1 + & _predictors_io_out_s1_full_pred_0_is_br_sharing; + wire _s1_predicted_ghist_ptr_dup_T_4 = + ~_predictors_io_out_s1_full_pred_0_hit + | ~(_predictors_io_out_s1_full_pred_0_slot_valids_0 | _s1_ghv_wdatas_T_190528); + wire s1_pred_info_takenMask_0_0 = + _predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0; + wire _cfiIndex_bits_T_94 = + _predictors_io_out_s1_full_pred_0_is_br_sharing + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1; + wire _s1_predicted_ghist_ptr_dup_T_32 = + _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit; + wire _s1_predicted_ghist_ptr_dup_T_60 = + _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit; + wire _s1_ghv_wdatas_T_190589 = + _predictors_io_out_s1_full_pred_1_slot_valids_1 + & _predictors_io_out_s1_full_pred_1_is_br_sharing; + wire _s1_predicted_ghist_ptr_dup_T_65 = + ~_predictors_io_out_s1_full_pred_1_hit + | ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_ghv_wdatas_T_190589); + wire s1_pred_info_takenMask_1_0 = + _predictors_io_out_s1_full_pred_1_slot_valids_0 + & _predictors_io_out_s1_full_pred_1_br_taken_mask_0; + wire _cfiIndex_bits_T_115 = + _predictors_io_out_s1_full_pred_1_is_br_sharing + & _predictors_io_out_s1_full_pred_1_br_taken_mask_1; + wire _s1_predicted_ghist_ptr_dup_T_93 = + _predictors_io_out_s1_full_pred_1_slot_valids_0 + & (s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit + | ~_s1_ghv_wdatas_T_190589) & _predictors_io_out_s1_full_pred_1_hit; + wire _s1_predicted_ghist_ptr_dup_T_121 = + _s1_ghv_wdatas_T_190589 + & ~(s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit) + & _predictors_io_out_s1_full_pred_1_hit; + wire _s1_ghv_wdatas_T_190650 = + _predictors_io_out_s1_full_pred_2_slot_valids_1 + & _predictors_io_out_s1_full_pred_2_is_br_sharing; + wire _s1_predicted_ghist_ptr_dup_T_126 = + ~_predictors_io_out_s1_full_pred_2_hit + | ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_ghv_wdatas_T_190650); + wire s1_pred_info_takenMask_2_0 = + _predictors_io_out_s1_full_pred_2_slot_valids_0 + & _predictors_io_out_s1_full_pred_2_br_taken_mask_0; + wire _cfiIndex_bits_T_136 = + _predictors_io_out_s1_full_pred_2_is_br_sharing + & _predictors_io_out_s1_full_pred_2_br_taken_mask_1; + wire _s1_predicted_ghist_ptr_dup_T_154 = + _predictors_io_out_s1_full_pred_2_slot_valids_0 + & (s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit + | ~_s1_ghv_wdatas_T_190650) & _predictors_io_out_s1_full_pred_2_hit; + wire _s1_predicted_ghist_ptr_dup_T_182 = + _s1_ghv_wdatas_T_190650 + & ~(s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit) + & _predictors_io_out_s1_full_pred_2_hit; + wire _s1_ghv_wdatas_T_190711 = + _predictors_io_out_s1_full_pred_3_slot_valids_1 + & _predictors_io_out_s1_full_pred_3_is_br_sharing; + wire _s1_predicted_ghist_ptr_dup_T_187 = + ~_predictors_io_out_s1_full_pred_3_hit + | ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_ghv_wdatas_T_190711); + wire s1_pred_info_takenMask_3_0 = + _predictors_io_out_s1_full_pred_3_slot_valids_0 + & _predictors_io_out_s1_full_pred_3_br_taken_mask_0; + wire _cfiIndex_bits_T_157 = + _predictors_io_out_s1_full_pred_3_is_br_sharing + & _predictors_io_out_s1_full_pred_3_br_taken_mask_1; + wire _s1_predicted_ghist_ptr_dup_T_215 = + _predictors_io_out_s1_full_pred_3_slot_valids_0 + & (s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit + | ~_s1_ghv_wdatas_T_190711) & _predictors_io_out_s1_full_pred_3_hit; + wire _s1_predicted_ghist_ptr_dup_T_243 = + _s1_ghv_wdatas_T_190711 + & ~(s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit) + & _predictors_io_out_s1_full_pred_3_hit; + wire _s1_possible_predicted_fhs_dup_T_11 = + _predictors_io_out_s1_full_pred_1_slot_valids_0 + & _predictors_io_out_s1_full_pred_1_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_1_hit | _s1_ghv_wdatas_T_190589 + & _predictors_io_out_s1_full_pred_1_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_1_hit; + wire _s1_possible_predicted_fhs_dup_T_17 = + _predictors_io_out_s1_full_pred_2_slot_valids_0 + & _predictors_io_out_s1_full_pred_2_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_2_hit | _s1_ghv_wdatas_T_190650 + & _predictors_io_out_s1_full_pred_2_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_2_hit; + wire _s1_possible_predicted_fhs_dup_T_23 = + _predictors_io_out_s1_full_pred_3_slot_valids_0 + & _predictors_io_out_s1_full_pred_3_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_3_hit | _s1_ghv_wdatas_T_190711 + & _predictors_io_out_s1_full_pred_3_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_3_hit; + wire _s1_possible_predicted_fhs_dup_T_271 = + _s1_possible_predicted_fhs_dup_T_11 + & (~_predictors_io_out_s1_full_pred_1_hit + | ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_ghv_wdatas_T_190589)); + wire + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 = + _s1_possible_predicted_fhs_dup_T_11 & _predictors_io_out_s1_full_pred_1_slot_valids_0 + & (s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit + | ~_s1_ghv_wdatas_T_190589) & _predictors_io_out_s1_full_pred_1_hit; + wire + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 = + _s1_possible_predicted_fhs_dup_T_11 & _s1_ghv_wdatas_T_190589 + & ~(s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit) + & _predictors_io_out_s1_full_pred_1_hit; + wire _s1_possible_predicted_fhs_dup_T_274 = + _s1_possible_predicted_fhs_dup_T_17 + & (~_predictors_io_out_s1_full_pred_2_hit + | ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_ghv_wdatas_T_190650)); + wire + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 = + _s1_possible_predicted_fhs_dup_T_17 & _predictors_io_out_s1_full_pred_2_slot_valids_0 + & (s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit + | ~_s1_ghv_wdatas_T_190650) & _predictors_io_out_s1_full_pred_2_hit; + wire + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 = + _s1_possible_predicted_fhs_dup_T_17 & _s1_ghv_wdatas_T_190650 + & ~(s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit) + & _predictors_io_out_s1_full_pred_2_hit; + wire _s1_possible_predicted_fhs_dup_T_277 = + _s1_possible_predicted_fhs_dup_T_23 + & (~_predictors_io_out_s1_full_pred_3_hit + | ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_ghv_wdatas_T_190711)); + wire + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 = + _s1_possible_predicted_fhs_dup_T_23 & _predictors_io_out_s1_full_pred_3_slot_valids_0 + & (s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit + | ~_s1_ghv_wdatas_T_190711) & _predictors_io_out_s1_full_pred_3_hit; + wire + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 = + _s1_possible_predicted_fhs_dup_T_23 & _s1_ghv_wdatas_T_190711 + & ~(s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit) + & _predictors_io_out_s1_full_pred_3_hit; + wire _s1_predicted_fh_dup_T_65 = + ~_predictors_io_out_s1_full_pred_1_hit + | ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_ghv_wdatas_T_190589); + wire _s1_predicted_fh_dup_T_93 = + _predictors_io_out_s1_full_pred_1_slot_valids_0 + & (s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit + | ~_s1_ghv_wdatas_T_190589) & _predictors_io_out_s1_full_pred_1_hit; + wire _s1_predicted_fh_dup_T_121 = + _s1_ghv_wdatas_T_190589 + & ~(s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit) + & _predictors_io_out_s1_full_pred_1_hit; + wire _s1_predicted_fh_dup_T_126 = + ~_predictors_io_out_s1_full_pred_2_hit + | ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_ghv_wdatas_T_190650); + wire _s1_predicted_fh_dup_T_154 = + _predictors_io_out_s1_full_pred_2_slot_valids_0 + & (s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit + | ~_s1_ghv_wdatas_T_190650) & _predictors_io_out_s1_full_pred_2_hit; + wire _s1_predicted_fh_dup_T_182 = + _s1_ghv_wdatas_T_190650 + & ~(s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit) + & _predictors_io_out_s1_full_pred_2_hit; + wire _s1_predicted_fh_dup_T_187 = + ~_predictors_io_out_s1_full_pred_3_hit + | ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_ghv_wdatas_T_190711); + wire _s1_predicted_fh_dup_T_215 = + _predictors_io_out_s1_full_pred_3_slot_valids_0 + & (s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit + | ~_s1_ghv_wdatas_T_190711) & _predictors_io_out_s1_full_pred_3_hit; + wire _s1_predicted_fh_dup_T_243 = + _s1_ghv_wdatas_T_190711 + & ~(s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit) + & _predictors_io_out_s1_full_pred_3_hit; + wire [255:0] _GEN_3 = + {{ghv_255}, + {ghv_254}, + {ghv_253}, + {ghv_252}, + {ghv_251}, + {ghv_250}, + {ghv_249}, + {ghv_248}, + {ghv_247}, + {ghv_246}, + {ghv_245}, + {ghv_244}, + {ghv_243}, + {ghv_242}, + {ghv_241}, + {ghv_240}, + {ghv_239}, + {ghv_238}, + {ghv_237}, + {ghv_236}, + {ghv_235}, + {ghv_234}, + {ghv_233}, + {ghv_232}, + {ghv_231}, + {ghv_230}, + {ghv_229}, + {ghv_228}, + {ghv_227}, + {ghv_226}, + {ghv_225}, + {ghv_224}, + {ghv_223}, + {ghv_222}, + {ghv_221}, + {ghv_220}, + {ghv_219}, + {ghv_218}, + {ghv_217}, + {ghv_216}, + {ghv_215}, + {ghv_214}, + {ghv_213}, + {ghv_212}, + {ghv_211}, + {ghv_210}, + {ghv_209}, + {ghv_208}, + {ghv_207}, + {ghv_206}, + {ghv_205}, + {ghv_204}, + {ghv_203}, + {ghv_202}, + {ghv_201}, + {ghv_200}, + {ghv_199}, + {ghv_198}, + {ghv_197}, + {ghv_196}, + {ghv_195}, + {ghv_194}, + {ghv_193}, + {ghv_192}, + {ghv_191}, + {ghv_190}, + {ghv_189}, + {ghv_188}, + {ghv_187}, + {ghv_186}, + {ghv_185}, + {ghv_184}, + {ghv_183}, + {ghv_182}, + {ghv_181}, + {ghv_180}, + {ghv_179}, + {ghv_178}, + {ghv_177}, + {ghv_176}, + {ghv_175}, + {ghv_174}, + {ghv_173}, + {ghv_172}, + {ghv_171}, + {ghv_170}, + {ghv_169}, + {ghv_168}, + {ghv_167}, + {ghv_166}, + {ghv_165}, + {ghv_164}, + {ghv_163}, + {ghv_162}, + {ghv_161}, + {ghv_160}, + {ghv_159}, + {ghv_158}, + {ghv_157}, + {ghv_156}, + {ghv_155}, + {ghv_154}, + {ghv_153}, + {ghv_152}, + {ghv_151}, + {ghv_150}, + {ghv_149}, + {ghv_148}, + {ghv_147}, + {ghv_146}, + {ghv_145}, + {ghv_144}, + {ghv_143}, + {ghv_142}, + {ghv_141}, + {ghv_140}, + {ghv_139}, + {ghv_138}, + {ghv_137}, + {ghv_136}, + {ghv_135}, + {ghv_134}, + {ghv_133}, + {ghv_132}, + {ghv_131}, + {ghv_130}, + {ghv_129}, + {ghv_128}, + {ghv_127}, + {ghv_126}, + {ghv_125}, + {ghv_124}, + {ghv_123}, + {ghv_122}, + {ghv_121}, + {ghv_120}, + {ghv_119}, + {ghv_118}, + {ghv_117}, + {ghv_116}, + {ghv_115}, + {ghv_114}, + {ghv_113}, + {ghv_112}, + {ghv_111}, + {ghv_110}, + {ghv_109}, + {ghv_108}, + {ghv_107}, + {ghv_106}, + {ghv_105}, + {ghv_104}, + {ghv_103}, + {ghv_102}, + {ghv_101}, + {ghv_100}, + {ghv_99}, + {ghv_98}, + {ghv_97}, + {ghv_96}, + {ghv_95}, + {ghv_94}, + {ghv_93}, + {ghv_92}, + {ghv_91}, + {ghv_90}, + {ghv_89}, + {ghv_88}, + {ghv_87}, + {ghv_86}, + {ghv_85}, + {ghv_84}, + {ghv_83}, + {ghv_82}, + {ghv_81}, + {ghv_80}, + {ghv_79}, + {ghv_78}, + {ghv_77}, + {ghv_76}, + {ghv_75}, + {ghv_74}, + {ghv_73}, + {ghv_72}, + {ghv_71}, + {ghv_70}, + {ghv_69}, + {ghv_68}, + {ghv_67}, + {ghv_66}, + {ghv_65}, + {ghv_64}, + {ghv_63}, + {ghv_62}, + {ghv_61}, + {ghv_60}, + {ghv_59}, + {ghv_58}, + {ghv_57}, + {ghv_56}, + {ghv_55}, + {ghv_54}, + {ghv_53}, + {ghv_52}, + {ghv_51}, + {ghv_50}, + {ghv_49}, + {ghv_48}, + {ghv_47}, + {ghv_46}, + {ghv_45}, + {ghv_44}, + {ghv_43}, + {ghv_42}, + {ghv_41}, + {ghv_40}, + {ghv_39}, + {ghv_38}, + {ghv_37}, + {ghv_36}, + {ghv_35}, + {ghv_34}, + {ghv_33}, + {ghv_32}, + {ghv_31}, + {ghv_30}, + {ghv_29}, + {ghv_28}, + {ghv_27}, + {ghv_26}, + {ghv_25}, + {ghv_24}, + {ghv_23}, + {ghv_22}, + {ghv_21}, + {ghv_20}, + {ghv_19}, + {ghv_18}, + {ghv_17}, + {ghv_16}, + {ghv_15}, + {ghv_14}, + {ghv_13}, + {ghv_12}, + {ghv_11}, + {ghv_10}, + {ghv_9}, + {ghv_8}, + {ghv_7}, + {ghv_6}, + {ghv_5}, + {ghv_4}, + {ghv_3}, + {ghv_2}, + {ghv_1}, + {ghv_0}}; + wire s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0 = + _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hA)]; + wire s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2 = + _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h8)]; + wire s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3 = + _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h7)]; + wire s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0 = + _GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hD)]; + wire s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0 = + _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hA)]; + wire s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2 = + _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h8)]; + wire s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3 = + _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h7)]; + wire s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0 = + _GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hD)]; + wire s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0 = + _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hA)]; + wire s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2 = + _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h8)]; + wire s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3 = + _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h7)]; + wire s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0 = + _GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hD)]; + wire s1_pred_info_takenMask_0_1 = + _predictors_io_out_s1_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_94 | ~_predictors_io_out_s1_full_pred_0_is_br_sharing); + wire [40:0] _GEN_4 = + _predictors_io_out_s1_full_pred_0_hit + ? 41'h0 + : 41'(_predictors_io_out_s1_pc_0 + 41'h20); + wire s1_pred_info_takenMask_1_1 = + _predictors_io_out_s1_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_115 | ~_predictors_io_out_s1_full_pred_1_is_br_sharing); + wire [40:0] _GEN_5 = + _predictors_io_out_s1_full_pred_1_hit + ? 41'h0 + : 41'(_predictors_io_out_s1_pc_1 + 41'h20); + wire s1_pred_info_takenMask_2_1 = + _predictors_io_out_s1_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_136 | ~_predictors_io_out_s1_full_pred_2_is_br_sharing); + wire [40:0] _GEN_6 = + _predictors_io_out_s1_full_pred_2_hit + ? 41'h0 + : 41'(_predictors_io_out_s1_pc_2 + 41'h20); + wire s1_pred_info_takenMask_3_1 = + _predictors_io_out_s1_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_157 | ~_predictors_io_out_s1_full_pred_3_is_br_sharing); + wire [40:0] _GEN_7 = + _predictors_io_out_s1_full_pred_3_hit + ? 41'h0 + : 41'(_predictors_io_out_s1_pc_3 + 41'h20); + wire _GEN_8 = + _predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_ghv_wdatas_T_190589; + wire _GEN_9 = + s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit; + wire _GEN_10 = _GEN_9 | ~_s1_ghv_wdatas_T_190589; + wire _GEN_11 = + _predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_ghv_wdatas_T_190650; + wire _GEN_12 = + s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit; + wire _GEN_13 = _GEN_12 | ~_s1_ghv_wdatas_T_190650; + wire _GEN_14 = + _predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_ghv_wdatas_T_190711; + wire _GEN_15 = + s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit; + wire _GEN_16 = _GEN_15 | ~_s1_ghv_wdatas_T_190711; + wire _ghv_wens_0_T = + ~(|s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_1_T = + s1_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_2_T = + s1_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_3_T = + s1_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_4_T = + s1_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_5_T = + s1_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_6_T = + s1_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_7_T = + s1_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_8_T = + s1_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_9_T = + s1_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_10_T = + s1_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_11_T = + s1_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_12_T = + s1_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_13_T = + s1_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_14_T = + s1_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_15_T = + s1_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h10 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_16_T = + s1_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h11 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_17_T = + s1_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h12 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_18_T = + s1_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h13 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_19_T = + s1_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h14 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_20_T = + s1_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h15 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_21_T = + s1_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h16 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_22_T = + s1_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h17 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_23_T = + s1_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h18 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_24_T = + s1_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h19 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_25_T = + s1_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_26_T = + s1_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_27_T = + s1_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_28_T = + s1_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_29_T = + s1_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_30_T = + s1_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_31_T = + s1_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h20 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_32_T = + s1_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h21 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_33_T = + s1_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h22 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_34_T = + s1_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h23 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_35_T = + s1_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h24 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_36_T = + s1_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h25 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_37_T = + s1_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h26 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_38_T = + s1_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h27 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_39_T = + s1_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h28 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_40_T = + s1_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h29 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_41_T = + s1_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_42_T = + s1_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_43_T = + s1_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_44_T = + s1_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_45_T = + s1_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_46_T = + s1_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_47_T = + s1_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h30 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_48_T = + s1_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h31 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_49_T = + s1_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h32 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_50_T = + s1_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h33 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_51_T = + s1_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h34 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_52_T = + s1_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h35 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_53_T = + s1_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h36 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_54_T = + s1_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h37 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_55_T = + s1_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h38 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_56_T = + s1_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h39 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_57_T = + s1_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_58_T = + s1_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_59_T = + s1_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_60_T = + s1_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_61_T = + s1_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_62_T = + s1_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_63_T = + s1_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h40 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_64_T = + s1_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h41 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_65_T = + s1_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h42 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_66_T = + s1_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h43 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_67_T = + s1_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h44 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_68_T = + s1_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h45 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_69_T = + s1_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h46 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_70_T = + s1_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h47 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_71_T = + s1_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h48 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_72_T = + s1_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h49 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_73_T = + s1_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_74_T = + s1_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_75_T = + s1_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_76_T = + s1_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_77_T = + s1_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_78_T = + s1_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_79_T = + s1_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h50 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_80_T = + s1_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h51 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_81_T = + s1_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h52 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_82_T = + s1_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h53 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_83_T = + s1_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h54 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_84_T = + s1_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h55 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_85_T = + s1_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h56 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_86_T = + s1_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h57 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_87_T = + s1_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h58 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_88_T = + s1_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h59 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_89_T = + s1_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_90_T = + s1_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_91_T = + s1_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_92_T = + s1_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_93_T = + s1_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_94_T = + s1_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_95_T = + s1_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h60 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_96_T = + s1_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h61 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_97_T = + s1_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h62 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_98_T = + s1_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h63 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_99_T = + s1_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h64 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_100_T = + s1_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h65 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_101_T = + s1_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h66 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_102_T = + s1_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h67 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_103_T = + s1_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h68 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_104_T = + s1_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h69 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_105_T = + s1_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_106_T = + s1_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_107_T = + s1_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_108_T = + s1_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_109_T = + s1_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_110_T = + s1_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_111_T = + s1_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h70 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_112_T = + s1_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h71 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_113_T = + s1_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h72 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_114_T = + s1_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h73 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_115_T = + s1_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h74 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_116_T = + s1_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h75 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_117_T = + s1_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h76 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_118_T = + s1_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h77 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_119_T = + s1_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h78 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_120_T = + s1_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h79 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_121_T = + s1_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_122_T = + s1_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_123_T = + s1_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_124_T = + s1_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_125_T = + s1_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_126_T = + s1_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_127_T = + s1_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h80 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_128_T = + s1_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h81 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_129_T = + s1_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h82 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_130_T = + s1_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h83 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_131_T = + s1_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h84 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_132_T = + s1_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h85 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_133_T = + s1_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h86 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_134_T = + s1_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h87 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_135_T = + s1_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h88 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_136_T = + s1_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h89 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_137_T = + s1_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_138_T = + s1_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_139_T = + s1_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_140_T = + s1_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_141_T = + s1_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_142_T = + s1_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_143_T = + s1_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h90 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_144_T = + s1_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h91 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_145_T = + s1_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h92 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_146_T = + s1_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h93 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_147_T = + s1_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h94 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_148_T = + s1_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h95 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_149_T = + s1_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h96 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_150_T = + s1_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h97 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_151_T = + s1_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h98 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_152_T = + s1_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h99 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_153_T = + s1_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_154_T = + s1_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_155_T = + s1_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_156_T = + s1_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_157_T = + s1_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_158_T = + s1_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_159_T = + s1_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_160_T = + s1_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_161_T = + s1_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_162_T = + s1_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_163_T = + s1_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_164_T = + s1_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_165_T = + s1_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_166_T = + s1_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_167_T = + s1_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_168_T = + s1_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_169_T = + s1_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_170_T = + s1_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_171_T = + s1_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_172_T = + s1_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_173_T = + s1_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_174_T = + s1_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_175_T = + s1_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_176_T = + s1_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_177_T = + s1_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_178_T = + s1_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_179_T = + s1_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_180_T = + s1_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_181_T = + s1_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_182_T = + s1_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_183_T = + s1_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_184_T = + s1_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_185_T = + s1_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_186_T = + s1_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_187_T = + s1_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_188_T = + s1_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_189_T = + s1_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_190_T = + s1_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_191_T = + s1_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_192_T = + s1_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_193_T = + s1_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_194_T = + s1_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_195_T = + s1_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_196_T = + s1_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_197_T = + s1_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_198_T = + s1_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_199_T = + s1_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_200_T = + s1_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_201_T = + s1_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_202_T = + s1_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_203_T = + s1_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_204_T = + s1_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_205_T = + s1_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_206_T = + s1_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_207_T = + s1_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_208_T = + s1_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_209_T = + s1_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_210_T = + s1_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_211_T = + s1_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_212_T = + s1_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_213_T = + s1_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_214_T = + s1_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_215_T = + s1_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_216_T = + s1_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_217_T = + s1_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_218_T = + s1_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_219_T = + s1_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_220_T = + s1_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_221_T = + s1_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_222_T = + s1_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_223_T = + s1_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_224_T = + s1_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_225_T = + s1_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_226_T = + s1_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_227_T = + s1_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_228_T = + s1_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_229_T = + s1_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_230_T = + s1_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_231_T = + s1_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_232_T = + s1_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_233_T = + s1_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_234_T = + s1_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_235_T = + s1_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_236_T = + s1_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hED & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_237_T = + s1_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_238_T = + s1_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_239_T = + s1_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_240_T = + s1_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_241_T = + s1_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_242_T = + s1_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_243_T = + s1_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_244_T = + s1_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_245_T = + s1_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_246_T = + s1_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_247_T = + s1_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_248_T = + s1_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_249_T = + s1_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_250_T = + s1_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_251_T = + s1_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_252_T = + s1_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_253_T = + s1_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_254_T = + s1_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | (&s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire _ghv_wens_255_T = + (&s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & s1_valid_dup_3 | ~(|s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & s1_valid_dup_3; + wire [8:0] _GEN_17 = {s2_ghist_ptr_dup_0_flag, s2_ghist_ptr_dup_0_value}; + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1 = + 9'(_GEN_17 - 9'h100); + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6 = + 9'(_GEN_17 + 9'hFF); + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11 = + 9'(_GEN_17 + 9'hFE); + wire [8:0] _GEN_18 = {s2_ghist_ptr_dup_1_flag, s2_ghist_ptr_dup_1_value}; + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16 = + 9'(_GEN_18 - 9'h100); + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21 = + 9'(_GEN_18 + 9'hFF); + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26 = + 9'(_GEN_18 + 9'hFE); + wire [8:0] _GEN_19 = {s2_ghist_ptr_dup_2_flag, s2_ghist_ptr_dup_2_value}; + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31 = + 9'(_GEN_19 - 9'h100); + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36 = + 9'(_GEN_19 + 9'hFF); + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41 = + 9'(_GEN_19 + 9'hFE); + wire [8:0] _GEN_20 = {s2_ghist_ptr_dup_3_flag, s2_ghist_ptr_dup_3_value}; + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46 = + 9'(_GEN_20 - 9'h100); + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51 = + 9'(_GEN_20 + 9'hFF); + wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56 = + 9'(_GEN_20 + 9'hFE); + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 = + _predictors_io_out_s2_full_pred_0_slot_valids_1 + & _predictors_io_out_s2_full_pred_0_is_br_sharing; + wire _s2_predicted_ghist_ptr_dup_T_4 = + ~_predictors_io_out_s2_full_pred_0_hit + | ~(_predictors_io_out_s2_full_pred_0_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56); + wire _cfiIndex_bits_T_261 = + _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _predictors_io_out_s2_full_pred_0_br_taken_mask_0; + wire _cfiIndex_bits_T_262 = + _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_br_taken_mask_1; + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 = + _predictors_io_out_s2_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s2_full_pred_0_slot_valids_1; + wire _s2_predicted_ghist_ptr_dup_T_32 = + _predictors_io_out_s2_full_pred_0_slot_valids_0 + & (_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56) + & _predictors_io_out_s2_full_pred_0_hit; + wire _s2_predicted_ghist_ptr_dup_T_60 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _predictors_io_out_s2_full_pred_0_hit; + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117 = + _predictors_io_out_s2_full_pred_1_slot_valids_1 + & _predictors_io_out_s2_full_pred_1_is_br_sharing; + wire _s2_predicted_ghist_ptr_dup_T_65 = + ~_predictors_io_out_s2_full_pred_1_hit + | ~(_predictors_io_out_s2_full_pred_1_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117); + wire _cfiIndex_bits_T_282 = + _predictors_io_out_s2_full_pred_1_slot_valids_0 + & _predictors_io_out_s2_full_pred_1_br_taken_mask_0; + wire _cfiIndex_bits_T_283 = + _predictors_io_out_s2_full_pred_1_is_br_sharing + & _predictors_io_out_s2_full_pred_1_br_taken_mask_1; + wire _s2_predicted_ghist_ptr_dup_T_93 = + _predictors_io_out_s2_full_pred_1_slot_valids_0 + & (_cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117) + & _predictors_io_out_s2_full_pred_1_hit; + wire _s2_predicted_ghist_ptr_dup_T_121 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117 + & ~(_cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit) + & _predictors_io_out_s2_full_pred_1_hit; + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178 = + _predictors_io_out_s2_full_pred_2_slot_valids_1 + & _predictors_io_out_s2_full_pred_2_is_br_sharing; + wire _s2_predicted_ghist_ptr_dup_T_126 = + ~_predictors_io_out_s2_full_pred_2_hit + | ~(_predictors_io_out_s2_full_pred_2_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178); + wire _cfiIndex_bits_T_303 = + _predictors_io_out_s2_full_pred_2_slot_valids_0 + & _predictors_io_out_s2_full_pred_2_br_taken_mask_0; + wire _cfiIndex_bits_T_304 = + _predictors_io_out_s2_full_pred_2_is_br_sharing + & _predictors_io_out_s2_full_pred_2_br_taken_mask_1; + wire _s2_predicted_ghist_ptr_dup_T_154 = + _predictors_io_out_s2_full_pred_2_slot_valids_0 + & (_cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178) + & _predictors_io_out_s2_full_pred_2_hit; + wire _s2_predicted_ghist_ptr_dup_T_182 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178 + & ~(_cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit) + & _predictors_io_out_s2_full_pred_2_hit; + wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239 = + _predictors_io_out_s2_full_pred_3_slot_valids_1 + & _predictors_io_out_s2_full_pred_3_is_br_sharing; + wire _s2_predicted_ghist_ptr_dup_T_187 = + ~_predictors_io_out_s2_full_pred_3_hit + | ~(_predictors_io_out_s2_full_pred_3_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239); + wire _cfiIndex_bits_T_324 = + _predictors_io_out_s2_full_pred_3_slot_valids_0 + & _predictors_io_out_s2_full_pred_3_br_taken_mask_0; + wire _cfiIndex_bits_T_325 = + _predictors_io_out_s2_full_pred_3_is_br_sharing + & _predictors_io_out_s2_full_pred_3_br_taken_mask_1; + wire _s2_predicted_ghist_ptr_dup_T_215 = + _predictors_io_out_s2_full_pred_3_slot_valids_0 + & (_cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239) + & _predictors_io_out_s2_full_pred_3_hit; + wire _s2_predicted_ghist_ptr_dup_T_243 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239 + & ~(_cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit) + & _predictors_io_out_s2_full_pred_3_hit; + wire _s2_predicted_fh_dup_T_65 = + ~_predictors_io_out_s2_full_pred_1_hit + | ~(_predictors_io_out_s2_full_pred_1_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117); + wire _s2_predicted_fh_dup_T_93 = + _predictors_io_out_s2_full_pred_1_slot_valids_0 + & (_cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117) + & _predictors_io_out_s2_full_pred_1_hit; + wire _s2_predicted_fh_dup_T_121 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117 + & ~(_cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit) + & _predictors_io_out_s2_full_pred_1_hit; + wire _s2_predicted_fh_dup_T_126 = + ~_predictors_io_out_s2_full_pred_2_hit + | ~(_predictors_io_out_s2_full_pred_2_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178); + wire _s2_predicted_fh_dup_T_154 = + _predictors_io_out_s2_full_pred_2_slot_valids_0 + & (_cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178) + & _predictors_io_out_s2_full_pred_2_hit; + wire _s2_predicted_fh_dup_T_182 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178 + & ~(_cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit) + & _predictors_io_out_s2_full_pred_2_hit; + wire _s2_predicted_fh_dup_T_187 = + ~_predictors_io_out_s2_full_pred_3_hit + | ~(_predictors_io_out_s2_full_pred_3_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239); + wire _s2_predicted_fh_dup_T_215 = + _predictors_io_out_s2_full_pred_3_slot_valids_0 + & (_cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239) + & _predictors_io_out_s2_full_pred_3_hit; + wire _s2_predicted_fh_dup_T_243 = + _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239 + & ~(_cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit) + & _predictors_io_out_s2_full_pred_3_hit; + wire s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0 = + _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hA)]; + wire s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2 = + _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h8)]; + wire s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3 = + _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h7)]; + wire s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0 = + _GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hD)]; + wire s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0 = + _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hA)]; + wire s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2 = + _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h8)]; + wire s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3 = + _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h7)]; + wire s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0 = + _GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hD)]; + wire s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0 = + _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hA)]; + wire s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2 = + _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h8)]; + wire s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3 = + _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h7)]; + wire s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0 = + _GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hD)]; + reg previous_s1_pred_info_hit_0; + reg previous_s1_pred_info_hit_1; + reg previous_s1_pred_info_hit_2; + reg previous_s1_pred_info_hit_3; + reg [40:0] previous_s1_pred_info_target_0; + reg [40:0] previous_s1_pred_info_target_1; + reg [40:0] previous_s1_pred_info_target_2; + reg [40:0] previous_s1_pred_info_target_3; + reg previous_s1_pred_info_lastBrPosOH_0_0; + reg previous_s1_pred_info_lastBrPosOH_0_1; + reg previous_s1_pred_info_lastBrPosOH_0_2; + reg previous_s1_pred_info_lastBrPosOH_1_0; + reg previous_s1_pred_info_lastBrPosOH_1_1; + reg previous_s1_pred_info_lastBrPosOH_1_2; + reg previous_s1_pred_info_lastBrPosOH_2_0; + reg previous_s1_pred_info_lastBrPosOH_2_1; + reg previous_s1_pred_info_lastBrPosOH_2_2; + reg previous_s1_pred_info_lastBrPosOH_3_0; + reg previous_s1_pred_info_lastBrPosOH_3_1; + reg previous_s1_pred_info_lastBrPosOH_3_2; + reg previous_s1_pred_info_taken_0; + reg previous_s1_pred_info_taken_1; + reg previous_s1_pred_info_taken_2; + reg previous_s1_pred_info_taken_3; + reg previous_s1_pred_info_takenMask_0_0; + reg previous_s1_pred_info_takenMask_0_1; + reg previous_s1_pred_info_takenMask_1_0; + reg previous_s1_pred_info_takenMask_1_1; + reg previous_s1_pred_info_takenMask_2_0; + reg previous_s1_pred_info_takenMask_2_1; + reg previous_s1_pred_info_takenMask_3_0; + reg previous_s1_pred_info_takenMask_3_1; + reg [3:0] previous_s1_pred_info_cfiIndex_0; + reg [3:0] previous_s1_pred_info_cfiIndex_1; + reg [3:0] previous_s1_pred_info_cfiIndex_2; + reg [3:0] previous_s1_pred_info_cfiIndex_3; + wire [40:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T = + 41'(_predictors_io_out_s2_pc_0 + 41'h20); + wire [40:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_2 = + 41'(_predictors_io_out_s2_pc_1 + 41'h20); + wire [40:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_4 = + 41'(_predictors_io_out_s2_pc_2 + 41'h20); + wire [40:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_6 = + 41'(_predictors_io_out_s2_pc_3 + 41'h20); + assign s2_redirect_dup_0 = + s2_valid_dup_3 + & (previous_s1_pred_info_takenMask_0_0 & previous_s1_pred_info_hit_0 + & _predictors_io_out_s2_full_pred_0_targets_0 != previous_s1_pred_info_target_0 + | ~previous_s1_pred_info_takenMask_0_0 & previous_s1_pred_info_takenMask_0_1 + & previous_s1_pred_info_hit_0 + & _predictors_io_out_s2_full_pred_0_targets_1 != previous_s1_pred_info_target_0 + | {previous_s1_pred_info_takenMask_0_1, + previous_s1_pred_info_takenMask_0_0} == 2'h0 & previous_s1_pred_info_hit_0 + & _predictors_io_out_s2_full_pred_0_fallThroughAddr != previous_s1_pred_info_target_0 + | ~previous_s1_pred_info_hit_0 + & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T != previous_s1_pred_info_target_0 + | {previous_s1_pred_info_lastBrPosOH_0_2, + previous_s1_pred_info_lastBrPosOH_0_1, + previous_s1_pred_info_lastBrPosOH_0_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 + & _predictors_io_out_s2_full_pred_0_hit) + & _predictors_io_out_s2_full_pred_0_hit, + _predictors_io_out_s2_full_pred_0_slot_valids_0 + & (_cfiIndex_bits_T_261 + & _predictors_io_out_s2_full_pred_0_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56) + & _predictors_io_out_s2_full_pred_0_hit, + ~_predictors_io_out_s2_full_pred_0_hit + | ~(_predictors_io_out_s2_full_pred_0_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56)} + | previous_s1_pred_info_taken_0 != (|{_predictors_io_out_s2_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_262 + | ~_predictors_io_out_s2_full_pred_0_is_br_sharing) + & _predictors_io_out_s2_full_pred_0_hit, + _cfiIndex_bits_T_261 + & _predictors_io_out_s2_full_pred_0_hit}) + | previous_s1_pred_info_taken_0 + & (|{_predictors_io_out_s2_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_262 | ~_predictors_io_out_s2_full_pred_0_is_br_sharing) + & _predictors_io_out_s2_full_pred_0_hit, + _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit}) + & previous_s1_pred_info_cfiIndex_0 != ((_cfiIndex_bits_T_261 + & _predictors_io_out_s2_full_pred_0_hit + ? _predictors_io_out_s2_full_pred_0_offsets_0 + : _predictors_io_out_s2_full_pred_0_offsets_1) + | {4{{_predictors_io_out_s2_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_262 + | ~_predictors_io_out_s2_full_pred_0_is_br_sharing) + & _predictors_io_out_s2_full_pred_0_hit, + _cfiIndex_bits_T_261 + & _predictors_io_out_s2_full_pred_0_hit} == 2'h0}})); + wire s2_redirect_dup_1 = + s2_valid_dup_3 + & (previous_s1_pred_info_takenMask_1_0 & previous_s1_pred_info_hit_1 + & _predictors_io_out_s2_full_pred_1_targets_0 != previous_s1_pred_info_target_1 + | ~previous_s1_pred_info_takenMask_1_0 & previous_s1_pred_info_takenMask_1_1 + & previous_s1_pred_info_hit_1 + & _predictors_io_out_s2_full_pred_1_targets_1 != previous_s1_pred_info_target_1 + | {previous_s1_pred_info_takenMask_1_1, + previous_s1_pred_info_takenMask_1_0} == 2'h0 & previous_s1_pred_info_hit_1 + & _predictors_io_out_s2_full_pred_1_fallThroughAddr != previous_s1_pred_info_target_1 + | ~previous_s1_pred_info_hit_1 + & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_2 != previous_s1_pred_info_target_1 + | {previous_s1_pred_info_lastBrPosOH_1_2, + previous_s1_pred_info_lastBrPosOH_1_1, + previous_s1_pred_info_lastBrPosOH_1_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117 + & ~(_cfiIndex_bits_T_282 + & _predictors_io_out_s2_full_pred_1_hit) + & _predictors_io_out_s2_full_pred_1_hit, + _predictors_io_out_s2_full_pred_1_slot_valids_0 + & (_cfiIndex_bits_T_282 + & _predictors_io_out_s2_full_pred_1_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117) + & _predictors_io_out_s2_full_pred_1_hit, + ~_predictors_io_out_s2_full_pred_1_hit + | ~(_predictors_io_out_s2_full_pred_1_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117)} + | previous_s1_pred_info_taken_1 != (|{_predictors_io_out_s2_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_283 + | ~_predictors_io_out_s2_full_pred_1_is_br_sharing) + & _predictors_io_out_s2_full_pred_1_hit, + _cfiIndex_bits_T_282 + & _predictors_io_out_s2_full_pred_1_hit}) + | previous_s1_pred_info_taken_1 + & (|{_predictors_io_out_s2_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_283 | ~_predictors_io_out_s2_full_pred_1_is_br_sharing) + & _predictors_io_out_s2_full_pred_1_hit, + _cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit}) + & previous_s1_pred_info_cfiIndex_1 != ((_cfiIndex_bits_T_282 + & _predictors_io_out_s2_full_pred_1_hit + ? _predictors_io_out_s2_full_pred_1_offsets_0 + : _predictors_io_out_s2_full_pred_1_offsets_1) + | {4{{_predictors_io_out_s2_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_283 + | ~_predictors_io_out_s2_full_pred_1_is_br_sharing) + & _predictors_io_out_s2_full_pred_1_hit, + _cfiIndex_bits_T_282 + & _predictors_io_out_s2_full_pred_1_hit} == 2'h0}})); + assign s2_redirect_dup_2 = + s2_valid_dup_3 + & (previous_s1_pred_info_takenMask_2_0 & previous_s1_pred_info_hit_2 + & _predictors_io_out_s2_full_pred_2_targets_0 != previous_s1_pred_info_target_2 + | ~previous_s1_pred_info_takenMask_2_0 & previous_s1_pred_info_takenMask_2_1 + & previous_s1_pred_info_hit_2 + & _predictors_io_out_s2_full_pred_2_targets_1 != previous_s1_pred_info_target_2 + | {previous_s1_pred_info_takenMask_2_1, + previous_s1_pred_info_takenMask_2_0} == 2'h0 & previous_s1_pred_info_hit_2 + & _predictors_io_out_s2_full_pred_2_fallThroughAddr != previous_s1_pred_info_target_2 + | ~previous_s1_pred_info_hit_2 + & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_4 != previous_s1_pred_info_target_2 + | {previous_s1_pred_info_lastBrPosOH_2_2, + previous_s1_pred_info_lastBrPosOH_2_1, + previous_s1_pred_info_lastBrPosOH_2_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178 + & ~(_cfiIndex_bits_T_303 + & _predictors_io_out_s2_full_pred_2_hit) + & _predictors_io_out_s2_full_pred_2_hit, + _predictors_io_out_s2_full_pred_2_slot_valids_0 + & (_cfiIndex_bits_T_303 + & _predictors_io_out_s2_full_pred_2_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178) + & _predictors_io_out_s2_full_pred_2_hit, + ~_predictors_io_out_s2_full_pred_2_hit + | ~(_predictors_io_out_s2_full_pred_2_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178)} + | previous_s1_pred_info_taken_2 != (|{_predictors_io_out_s2_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_304 + | ~_predictors_io_out_s2_full_pred_2_is_br_sharing) + & _predictors_io_out_s2_full_pred_2_hit, + _cfiIndex_bits_T_303 + & _predictors_io_out_s2_full_pred_2_hit}) + | previous_s1_pred_info_taken_2 + & (|{_predictors_io_out_s2_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_304 | ~_predictors_io_out_s2_full_pred_2_is_br_sharing) + & _predictors_io_out_s2_full_pred_2_hit, + _cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit}) + & previous_s1_pred_info_cfiIndex_2 != ((_cfiIndex_bits_T_303 + & _predictors_io_out_s2_full_pred_2_hit + ? _predictors_io_out_s2_full_pred_2_offsets_0 + : _predictors_io_out_s2_full_pred_2_offsets_1) + | {4{{_predictors_io_out_s2_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_304 + | ~_predictors_io_out_s2_full_pred_2_is_br_sharing) + & _predictors_io_out_s2_full_pred_2_hit, + _cfiIndex_bits_T_303 + & _predictors_io_out_s2_full_pred_2_hit} == 2'h0}})); + wire s2_redirect_dup_3 = + s2_valid_dup_3 + & (previous_s1_pred_info_takenMask_3_0 & previous_s1_pred_info_hit_3 + & _predictors_io_out_s2_full_pred_3_targets_0 != previous_s1_pred_info_target_3 + | ~previous_s1_pred_info_takenMask_3_0 & previous_s1_pred_info_takenMask_3_1 + & previous_s1_pred_info_hit_3 + & _predictors_io_out_s2_full_pred_3_targets_1 != previous_s1_pred_info_target_3 + | {previous_s1_pred_info_takenMask_3_1, + previous_s1_pred_info_takenMask_3_0} == 2'h0 & previous_s1_pred_info_hit_3 + & _predictors_io_out_s2_full_pred_3_fallThroughAddr != previous_s1_pred_info_target_3 + | ~previous_s1_pred_info_hit_3 + & _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_6 != previous_s1_pred_info_target_3 + | {previous_s1_pred_info_lastBrPosOH_3_2, + previous_s1_pred_info_lastBrPosOH_3_1, + previous_s1_pred_info_lastBrPosOH_3_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239 + & ~(_cfiIndex_bits_T_324 + & _predictors_io_out_s2_full_pred_3_hit) + & _predictors_io_out_s2_full_pred_3_hit, + _predictors_io_out_s2_full_pred_3_slot_valids_0 + & (_cfiIndex_bits_T_324 + & _predictors_io_out_s2_full_pred_3_hit + | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239) + & _predictors_io_out_s2_full_pred_3_hit, + ~_predictors_io_out_s2_full_pred_3_hit + | ~(_predictors_io_out_s2_full_pred_3_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239)} + | previous_s1_pred_info_taken_3 != (|{_predictors_io_out_s2_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_325 + | ~_predictors_io_out_s2_full_pred_3_is_br_sharing) + & _predictors_io_out_s2_full_pred_3_hit, + _cfiIndex_bits_T_324 + & _predictors_io_out_s2_full_pred_3_hit}) + | previous_s1_pred_info_taken_3 + & (|{_predictors_io_out_s2_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_325 | ~_predictors_io_out_s2_full_pred_3_is_br_sharing) + & _predictors_io_out_s2_full_pred_3_hit, + _cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit}) + & previous_s1_pred_info_cfiIndex_3 != ((_cfiIndex_bits_T_324 + & _predictors_io_out_s2_full_pred_3_hit + ? _predictors_io_out_s2_full_pred_3_offsets_0 + : _predictors_io_out_s2_full_pred_3_offsets_1) + | {4{{_predictors_io_out_s2_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_325 + | ~_predictors_io_out_s2_full_pred_3_is_br_sharing) + & _predictors_io_out_s2_full_pred_3_hit, + _cfiIndex_bits_T_324 + & _predictors_io_out_s2_full_pred_3_hit} == 2'h0}})); + wire _GEN_21 = + _predictors_io_out_s2_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_262 | ~_predictors_io_out_s2_full_pred_0_is_br_sharing); + wire _GEN_22 = + _predictors_io_out_s2_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_283 | ~_predictors_io_out_s2_full_pred_1_is_br_sharing); + wire _GEN_23 = + _predictors_io_out_s2_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_304 | ~_predictors_io_out_s2_full_pred_2_is_br_sharing); + wire _GEN_24 = + _predictors_io_out_s2_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_325 | ~_predictors_io_out_s2_full_pred_3_is_br_sharing); + wire _GEN_25 = _cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit; + wire _GEN_26 = _cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit; + wire _GEN_27 = _cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit; + wire _ghv_wens_0_T_1 = + ~(|s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_1_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_2_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_3_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_4_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_5_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_6_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_7_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_8_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_9_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_10_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_11_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_12_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_13_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_14_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_15_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h10 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_16_T_1 = + s2_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h11 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_17_T_1 = + s2_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_18_T_1 = + s2_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h13 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_19_T_1 = + s2_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h14 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_20_T_1 = + s2_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h15 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_21_T_1 = + s2_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h16 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_22_T_1 = + s2_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h17 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_23_T_1 = + s2_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h18 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_24_T_1 = + s2_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h19 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_25_T_1 = + s2_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_26_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_27_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_28_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_29_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_30_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_31_T_1 = + s2_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h20 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_32_T_1 = + s2_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h21 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_33_T_1 = + s2_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h22 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_34_T_1 = + s2_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h23 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_35_T_1 = + s2_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h24 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_36_T_1 = + s2_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h25 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_37_T_1 = + s2_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h26 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_38_T_1 = + s2_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h27 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_39_T_1 = + s2_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h28 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_40_T_1 = + s2_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h29 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_41_T_1 = + s2_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_42_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_43_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_44_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_45_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_46_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_47_T_1 = + s2_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h30 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_48_T_1 = + s2_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h31 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_49_T_1 = + s2_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h32 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_50_T_1 = + s2_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h33 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_51_T_1 = + s2_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h34 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_52_T_1 = + s2_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h35 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_53_T_1 = + s2_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h36 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_54_T_1 = + s2_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h37 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_55_T_1 = + s2_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h38 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_56_T_1 = + s2_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h39 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_57_T_1 = + s2_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_58_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_59_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_60_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_61_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_62_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_63_T_1 = + s2_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h40 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_64_T_1 = + s2_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h41 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_65_T_1 = + s2_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h42 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_66_T_1 = + s2_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h43 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_67_T_1 = + s2_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h44 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_68_T_1 = + s2_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h45 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_69_T_1 = + s2_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h46 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_70_T_1 = + s2_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h47 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_71_T_1 = + s2_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h48 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_72_T_1 = + s2_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h49 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_73_T_1 = + s2_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_74_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_75_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_76_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_77_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_78_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_79_T_1 = + s2_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h50 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_80_T_1 = + s2_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h51 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_81_T_1 = + s2_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h52 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_82_T_1 = + s2_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h53 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_83_T_1 = + s2_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h54 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_84_T_1 = + s2_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h55 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_85_T_1 = + s2_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h56 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_86_T_1 = + s2_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h57 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_87_T_1 = + s2_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h58 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_88_T_1 = + s2_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h59 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_89_T_1 = + s2_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_90_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_91_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_92_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_93_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_94_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_95_T_1 = + s2_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h60 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_96_T_1 = + s2_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h61 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_97_T_1 = + s2_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h62 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_98_T_1 = + s2_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h63 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_99_T_1 = + s2_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h64 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_100_T_1 = + s2_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h65 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_101_T_1 = + s2_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h66 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_102_T_1 = + s2_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h67 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_103_T_1 = + s2_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h68 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_104_T_1 = + s2_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h69 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_105_T_1 = + s2_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_106_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_107_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_108_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_109_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_110_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_111_T_1 = + s2_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h70 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_112_T_1 = + s2_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h71 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_113_T_1 = + s2_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h72 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_114_T_1 = + s2_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h73 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_115_T_1 = + s2_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h74 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_116_T_1 = + s2_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h75 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_117_T_1 = + s2_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h76 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_118_T_1 = + s2_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h77 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_119_T_1 = + s2_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h78 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_120_T_1 = + s2_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h79 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_121_T_1 = + s2_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_122_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_123_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_124_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_125_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_126_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_127_T_1 = + s2_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h80 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_128_T_1 = + s2_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h81 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_129_T_1 = + s2_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h82 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_130_T_1 = + s2_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h83 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_131_T_1 = + s2_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h84 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_132_T_1 = + s2_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h85 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_133_T_1 = + s2_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h86 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_134_T_1 = + s2_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h87 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_135_T_1 = + s2_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h88 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_136_T_1 = + s2_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h89 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_137_T_1 = + s2_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_138_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_139_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_140_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_141_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_142_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_143_T_1 = + s2_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h90 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_144_T_1 = + s2_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h91 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_145_T_1 = + s2_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h92 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_146_T_1 = + s2_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h93 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_147_T_1 = + s2_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h94 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_148_T_1 = + s2_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h95 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_149_T_1 = + s2_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h96 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_150_T_1 = + s2_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h97 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_151_T_1 = + s2_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h98 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_152_T_1 = + s2_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h99 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_153_T_1 = + s2_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_154_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_155_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_156_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_157_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_158_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_159_T_1 = + s2_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_160_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_161_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_162_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_163_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_164_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_165_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_166_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_167_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_168_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_169_T_1 = + s2_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_170_T_1 = + s2_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_171_T_1 = + s2_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_172_T_1 = + s2_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_173_T_1 = + s2_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_174_T_1 = + s2_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_175_T_1 = + s2_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_176_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_177_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_178_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_179_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_180_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_181_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_182_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_183_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_184_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_185_T_1 = + s2_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_186_T_1 = + s2_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_187_T_1 = + s2_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_188_T_1 = + s2_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_189_T_1 = + s2_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_190_T_1 = + s2_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_191_T_1 = + s2_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_192_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_193_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_194_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_195_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_196_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_197_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_198_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_199_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_200_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_201_T_1 = + s2_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_202_T_1 = + s2_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_203_T_1 = + s2_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_204_T_1 = + s2_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_205_T_1 = + s2_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_206_T_1 = + s2_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_207_T_1 = + s2_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_208_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_209_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_210_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_211_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_212_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_213_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_214_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_215_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_216_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_217_T_1 = + s2_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_218_T_1 = + s2_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_219_T_1 = + s2_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_220_T_1 = + s2_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_221_T_1 = + s2_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_222_T_1 = + s2_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_223_T_1 = + s2_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_224_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_225_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_226_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_227_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_228_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_229_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_230_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_231_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_232_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_233_T_1 = + s2_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_234_T_1 = + s2_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_235_T_1 = + s2_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_236_T_1 = + s2_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hED + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_237_T_1 = + s2_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_238_T_1 = + s2_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_239_T_1 = + s2_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_240_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_241_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_242_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_243_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_244_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_245_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_246_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_247_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_248_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_249_T_1 = + s2_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_250_T_1 = + s2_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_251_T_1 = + s2_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_252_T_1 = + s2_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_253_T_1 = + s2_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_254_T_1 = + s2_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | (&s2_ghist_ptr_dup_0_value) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire _ghv_wens_255_T_1 = + (&s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & s2_redirect_dup_0 | ~(|s2_ghist_ptr_dup_0_value) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; + wire [8:0] _GEN_28 = {s3_ghist_ptr_dup_0_flag, s3_ghist_ptr_dup_0_value}; + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1 = + 9'(_GEN_28 - 9'h100); + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6 = + 9'(_GEN_28 + 9'hFF); + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11 = + 9'(_GEN_28 + 9'hFE); + wire [8:0] _GEN_29 = {s3_ghist_ptr_dup_1_flag, s3_ghist_ptr_dup_1_value}; + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16 = + 9'(_GEN_29 - 9'h100); + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21 = + 9'(_GEN_29 + 9'hFF); + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26 = + 9'(_GEN_29 + 9'hFE); + wire [8:0] _GEN_30 = {s3_ghist_ptr_dup_2_flag, s3_ghist_ptr_dup_2_value}; + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31 = + 9'(_GEN_30 - 9'h100); + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36 = + 9'(_GEN_30 + 9'hFF); + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41 = + 9'(_GEN_30 + 9'hFE); + wire [8:0] _GEN_31 = {s3_ghist_ptr_dup_3_flag, s3_ghist_ptr_dup_3_value}; + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46 = + 9'(_GEN_31 - 9'h100); + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51 = + 9'(_GEN_31 + 9'hFF); + wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56 = + 9'(_GEN_31 + 9'hFE); + wire _s3_ghv_wdatas_T_57998 = + _predictors_io_out_s3_full_pred_0_slot_valids_1 + & _predictors_io_out_s3_full_pred_0_is_br_sharing; + wire _s3_predicted_ghist_ptr_dup_T_4 = + ~_predictors_io_out_s3_full_pred_0_hit + | ~(_predictors_io_out_s3_full_pred_0_slot_valids_0 | _s3_ghv_wdatas_T_57998); + wire _s3_redirect_on_jalr_target_dup_T_8 = + _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _predictors_io_out_s3_full_pred_0_br_taken_mask_0; + wire _s3_redirect_on_jalr_target_dup_T_9 = + _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_br_taken_mask_1; + wire _s3_both_first_taken_dup_T_7 = + _predictors_io_out_s3_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s3_full_pred_0_slot_valids_1; + wire _s3_predicted_ghist_ptr_dup_T_32 = + _predictors_io_out_s3_full_pred_0_slot_valids_0 + & (_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | ~_s3_ghv_wdatas_T_57998) & _predictors_io_out_s3_full_pred_0_hit; + wire _s3_predicted_ghist_ptr_dup_T_60 = + _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _predictors_io_out_s3_full_pred_0_hit; + wire _s3_ghv_wdatas_T_58023 = + _predictors_io_out_s3_full_pred_1_slot_valids_1 + & _predictors_io_out_s3_full_pred_1_is_br_sharing; + wire _s3_predicted_ghist_ptr_dup_T_65 = + ~_predictors_io_out_s3_full_pred_1_hit + | ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 | _s3_ghv_wdatas_T_58023); + wire _s3_redirect_on_jalr_target_dup_T_28 = + _predictors_io_out_s3_full_pred_1_slot_valids_0 + & _predictors_io_out_s3_full_pred_1_br_taken_mask_0; + wire _s3_redirect_on_jalr_target_dup_T_29 = + _predictors_io_out_s3_full_pred_1_is_br_sharing + & _predictors_io_out_s3_full_pred_1_br_taken_mask_1; + wire _s3_predicted_ghist_ptr_dup_T_93 = + _predictors_io_out_s3_full_pred_1_slot_valids_0 + & (_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit + | ~_s3_ghv_wdatas_T_58023) & _predictors_io_out_s3_full_pred_1_hit; + wire _s3_predicted_ghist_ptr_dup_T_121 = + _s3_ghv_wdatas_T_58023 + & ~(_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit) + & _predictors_io_out_s3_full_pred_1_hit; + wire _s3_ghv_wdatas_T_58048 = + _predictors_io_out_s3_full_pred_2_slot_valids_1 + & _predictors_io_out_s3_full_pred_2_is_br_sharing; + wire _s3_predicted_ghist_ptr_dup_T_126 = + ~_predictors_io_out_s3_full_pred_2_hit + | ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 | _s3_ghv_wdatas_T_58048); + wire _s3_redirect_on_jalr_target_dup_T_48 = + _predictors_io_out_s3_full_pred_2_slot_valids_0 + & _predictors_io_out_s3_full_pred_2_br_taken_mask_0; + wire _s3_redirect_on_jalr_target_dup_T_49 = + _predictors_io_out_s3_full_pred_2_is_br_sharing + & _predictors_io_out_s3_full_pred_2_br_taken_mask_1; + wire _s3_predicted_ghist_ptr_dup_T_154 = + _predictors_io_out_s3_full_pred_2_slot_valids_0 + & (_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit + | ~_s3_ghv_wdatas_T_58048) & _predictors_io_out_s3_full_pred_2_hit; + wire _s3_predicted_ghist_ptr_dup_T_182 = + _s3_ghv_wdatas_T_58048 + & ~(_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit) + & _predictors_io_out_s3_full_pred_2_hit; + wire _s3_ghv_wdatas_T_58073 = + _predictors_io_out_s3_full_pred_3_slot_valids_1 + & _predictors_io_out_s3_full_pred_3_is_br_sharing; + wire _s3_predicted_ghist_ptr_dup_T_187 = + ~_predictors_io_out_s3_full_pred_3_hit + | ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 | _s3_ghv_wdatas_T_58073); + wire _s3_redirect_on_jalr_target_dup_T_68 = + _predictors_io_out_s3_full_pred_3_slot_valids_0 + & _predictors_io_out_s3_full_pred_3_br_taken_mask_0; + wire _s3_redirect_on_jalr_target_dup_T_69 = + _predictors_io_out_s3_full_pred_3_is_br_sharing + & _predictors_io_out_s3_full_pred_3_br_taken_mask_1; + wire _s3_predicted_ghist_ptr_dup_T_215 = + _predictors_io_out_s3_full_pred_3_slot_valids_0 + & (_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit + | ~_s3_ghv_wdatas_T_58073) & _predictors_io_out_s3_full_pred_3_hit; + wire _s3_predicted_ghist_ptr_dup_T_243 = + _s3_ghv_wdatas_T_58073 + & ~(_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit) + & _predictors_io_out_s3_full_pred_3_hit; + wire _s3_predicted_fh_dup_T_65 = + ~_predictors_io_out_s3_full_pred_1_hit + | ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 | _s3_ghv_wdatas_T_58023); + wire _s3_predicted_fh_dup_T_93 = + _predictors_io_out_s3_full_pred_1_slot_valids_0 + & (_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit + | ~_s3_ghv_wdatas_T_58023) & _predictors_io_out_s3_full_pred_1_hit; + wire _s3_predicted_fh_dup_T_121 = + _s3_ghv_wdatas_T_58023 + & ~(_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit) + & _predictors_io_out_s3_full_pred_1_hit; + wire _s3_predicted_fh_dup_T_126 = + ~_predictors_io_out_s3_full_pred_2_hit + | ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 | _s3_ghv_wdatas_T_58048); + wire _s3_predicted_fh_dup_T_154 = + _predictors_io_out_s3_full_pred_2_slot_valids_0 + & (_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit + | ~_s3_ghv_wdatas_T_58048) & _predictors_io_out_s3_full_pred_2_hit; + wire _s3_predicted_fh_dup_T_182 = + _s3_ghv_wdatas_T_58048 + & ~(_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit) + & _predictors_io_out_s3_full_pred_2_hit; + wire _s3_predicted_fh_dup_T_187 = + ~_predictors_io_out_s3_full_pred_3_hit + | ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 | _s3_ghv_wdatas_T_58073); + wire _s3_predicted_fh_dup_T_215 = + _predictors_io_out_s3_full_pred_3_slot_valids_0 + & (_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit + | ~_s3_ghv_wdatas_T_58073) & _predictors_io_out_s3_full_pred_3_hit; + wire _s3_predicted_fh_dup_T_243 = + _s3_ghv_wdatas_T_58073 + & ~(_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit) + & _predictors_io_out_s3_full_pred_3_hit; + wire s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0 = + _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hA)]; + wire s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2 = + _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h8)]; + wire s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3 = + _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h7)]; + wire s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0 = + _GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hD)]; + wire s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0 = + _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hA)]; + wire s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2 = + _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h8)]; + wire s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3 = + _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h7)]; + wire s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0 = + _GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hD)]; + wire s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0 = + _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hA)]; + wire s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2 = + _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h8)]; + wire s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3 = + _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h7)]; + wire s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0 = + _GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hD)]; + reg [40:0] previous_s2_pred_pc_0; + reg [40:0] previous_s2_pred_pc_1; + reg [40:0] previous_s2_pred_pc_2; + reg [40:0] previous_s2_pred_pc_3; + reg previous_s2_pred_full_pred_0_br_taken_mask_0; + reg previous_s2_pred_full_pred_0_br_taken_mask_1; + reg previous_s2_pred_full_pred_0_slot_valids_0; + reg previous_s2_pred_full_pred_0_slot_valids_1; + reg [40:0] previous_s2_pred_full_pred_0_targets_0; + reg [40:0] previous_s2_pred_full_pred_0_targets_1; + reg [40:0] previous_s2_pred_full_pred_0_fallThroughAddr; + reg previous_s2_pred_full_pred_0_is_br_sharing; + reg previous_s2_pred_full_pred_0_hit; + reg previous_s2_pred_full_pred_1_br_taken_mask_0; + reg previous_s2_pred_full_pred_1_br_taken_mask_1; + reg previous_s2_pred_full_pred_1_slot_valids_0; + reg previous_s2_pred_full_pred_1_slot_valids_1; + reg [40:0] previous_s2_pred_full_pred_1_targets_0; + reg [40:0] previous_s2_pred_full_pred_1_targets_1; + reg [40:0] previous_s2_pred_full_pred_1_fallThroughAddr; + reg previous_s2_pred_full_pred_1_is_br_sharing; + reg previous_s2_pred_full_pred_1_hit; + reg previous_s2_pred_full_pred_2_br_taken_mask_0; + reg previous_s2_pred_full_pred_2_br_taken_mask_1; + reg previous_s2_pred_full_pred_2_slot_valids_0; + reg previous_s2_pred_full_pred_2_slot_valids_1; + reg [40:0] previous_s2_pred_full_pred_2_targets_0; + reg [40:0] previous_s2_pred_full_pred_2_targets_1; + reg [40:0] previous_s2_pred_full_pred_2_fallThroughAddr; + reg previous_s2_pred_full_pred_2_is_br_sharing; + reg previous_s2_pred_full_pred_2_hit; + reg previous_s2_pred_full_pred_3_br_taken_mask_0; + reg previous_s2_pred_full_pred_3_br_taken_mask_1; + reg previous_s2_pred_full_pred_3_slot_valids_0; + reg previous_s2_pred_full_pred_3_slot_valids_1; + reg [40:0] previous_s2_pred_full_pred_3_targets_0; + reg [40:0] previous_s2_pred_full_pred_3_targets_1; + reg [40:0] previous_s2_pred_full_pred_3_fallThroughAddr; + reg previous_s2_pred_full_pred_3_is_br_sharing; + reg previous_s2_pred_full_pred_3_hit; + wire _s3_redirect_on_target_dup_T_56 = + previous_s2_pred_full_pred_0_slot_valids_0 + & previous_s2_pred_full_pred_0_br_taken_mask_0; + wire _s3_redirect_on_target_dup_T_70 = + previous_s2_pred_full_pred_1_slot_valids_0 + & previous_s2_pred_full_pred_1_br_taken_mask_0; + wire _s3_redirect_on_target_dup_T_84 = + previous_s2_pred_full_pred_2_slot_valids_0 + & previous_s2_pred_full_pred_2_br_taken_mask_0; + wire _s3_redirect_on_target_dup_T_98 = + previous_s2_pred_full_pred_3_slot_valids_0 + & previous_s2_pred_full_pred_3_br_taken_mask_0; + wire _s3_redirect_on_target_dup_T_4 = + _predictors_io_out_s3_full_pred_0_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_9 + | ~_predictors_io_out_s3_full_pred_0_is_br_sharing); + wire [40:0] _s3_redirect_on_target_dup_T_5 = + 41'(_predictors_io_out_s3_pc_0 + 41'h20); + wire _s3_redirect_on_target_dup_T_18 = + _predictors_io_out_s3_full_pred_1_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_29 + | ~_predictors_io_out_s3_full_pred_1_is_br_sharing); + wire [40:0] _s3_redirect_on_target_dup_T_19 = + 41'(_predictors_io_out_s3_pc_1 + 41'h20); + wire _s3_redirect_on_target_dup_T_32 = + _predictors_io_out_s3_full_pred_2_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_49 + | ~_predictors_io_out_s3_full_pred_2_is_br_sharing); + wire [40:0] _s3_redirect_on_target_dup_T_33 = + 41'(_predictors_io_out_s3_pc_2 + 41'h20); + wire _s3_redirect_on_target_dup_T_46 = + _predictors_io_out_s3_full_pred_3_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_69 + | ~_predictors_io_out_s3_full_pred_3_is_br_sharing); + wire [40:0] _s3_redirect_on_target_dup_T_47 = + 41'(_predictors_io_out_s3_pc_3 + 41'h20); + wire _s3_redirect_on_target_dup_T_60 = + previous_s2_pred_full_pred_0_slot_valids_1 + & (previous_s2_pred_full_pred_0_is_br_sharing + & previous_s2_pred_full_pred_0_br_taken_mask_1 + | ~previous_s2_pred_full_pred_0_is_br_sharing); + wire _s3_redirect_on_target_dup_T_74 = + previous_s2_pred_full_pred_1_slot_valids_1 + & (previous_s2_pred_full_pred_1_is_br_sharing + & previous_s2_pred_full_pred_1_br_taken_mask_1 + | ~previous_s2_pred_full_pred_1_is_br_sharing); + wire _s3_redirect_on_target_dup_T_88 = + previous_s2_pred_full_pred_2_slot_valids_1 + & (previous_s2_pred_full_pred_2_is_br_sharing + & previous_s2_pred_full_pred_2_br_taken_mask_1 + | ~previous_s2_pred_full_pred_2_is_br_sharing); + wire _s3_redirect_on_target_dup_T_102 = + previous_s2_pred_full_pred_3_slot_valids_1 + & (previous_s2_pred_full_pred_3_is_br_sharing + & previous_s2_pred_full_pred_3_br_taken_mask_1 + | ~previous_s2_pred_full_pred_3_is_br_sharing); + assign s3_redirect_dup_0 = + s3_valid_dup_3 + & ({_s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit, + _s3_redirect_on_jalr_target_dup_T_8 + & _predictors_io_out_s3_full_pred_0_hit} != {previous_s2_pred_full_pred_0_br_taken_mask_1 + & previous_s2_pred_full_pred_0_slot_valids_1 + & previous_s2_pred_full_pred_0_is_br_sharing + & previous_s2_pred_full_pred_0_hit, + _s3_redirect_on_target_dup_T_56 + & previous_s2_pred_full_pred_0_hit} + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + & _s3_redirect_on_target_dup_T_56 & previous_s2_pred_full_pred_0_hit) + | ((_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + ? _predictors_io_out_s3_full_pred_0_targets_0 + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_8 & _s3_redirect_on_target_dup_T_4 + & _predictors_io_out_s3_full_pred_0_hit + ? _predictors_io_out_s3_full_pred_0_targets_1 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_4, _s3_redirect_on_jalr_target_dup_T_8} == 2'h0 + & _predictors_io_out_s3_full_pred_0_hit + ? _predictors_io_out_s3_full_pred_0_fallThroughAddr + : 41'h0) + | (_predictors_io_out_s3_full_pred_0_hit + ? 41'h0 + : _s3_redirect_on_target_dup_T_5)) != ((_s3_redirect_on_target_dup_T_56 + & previous_s2_pred_full_pred_0_hit + ? previous_s2_pred_full_pred_0_targets_0 + : 41'h0) + | (~_s3_redirect_on_target_dup_T_56 + & _s3_redirect_on_target_dup_T_60 + & previous_s2_pred_full_pred_0_hit + ? previous_s2_pred_full_pred_0_targets_1 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_60, + _s3_redirect_on_target_dup_T_56} == 2'h0 + & previous_s2_pred_full_pred_0_hit + ? previous_s2_pred_full_pred_0_fallThroughAddr + : 41'h0) + | (previous_s2_pred_full_pred_0_hit + ? 41'h0 + : 41'(previous_s2_pred_pc_0 + + 41'h20))) + | _predictors_io_out_s3_full_pred_0_hit + & _predictors_io_out_s3_full_pred_0_fallThroughErr); + wire s3_redirect_dup_1 = + s3_valid_dup_3 + & ({_predictors_io_out_s3_full_pred_1_br_taken_mask_1 + & _predictors_io_out_s3_full_pred_1_slot_valids_1 + & _predictors_io_out_s3_full_pred_1_is_br_sharing + & _predictors_io_out_s3_full_pred_1_hit, + _s3_redirect_on_jalr_target_dup_T_28 + & _predictors_io_out_s3_full_pred_1_hit} != {previous_s2_pred_full_pred_1_br_taken_mask_1 + & previous_s2_pred_full_pred_1_slot_valids_1 + & previous_s2_pred_full_pred_1_is_br_sharing + & previous_s2_pred_full_pred_1_hit, + _s3_redirect_on_target_dup_T_70 + & previous_s2_pred_full_pred_1_hit} + & ~(_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit + & _s3_redirect_on_target_dup_T_70 & previous_s2_pred_full_pred_1_hit) + | ((_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit + ? _predictors_io_out_s3_full_pred_1_targets_0 + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_28 & _s3_redirect_on_target_dup_T_18 + & _predictors_io_out_s3_full_pred_1_hit + ? _predictors_io_out_s3_full_pred_1_targets_1 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_18, + _s3_redirect_on_jalr_target_dup_T_28} == 2'h0 + & _predictors_io_out_s3_full_pred_1_hit + ? _predictors_io_out_s3_full_pred_1_fallThroughAddr + : 41'h0) + | (_predictors_io_out_s3_full_pred_1_hit + ? 41'h0 + : _s3_redirect_on_target_dup_T_19)) != ((_s3_redirect_on_target_dup_T_70 + & previous_s2_pred_full_pred_1_hit + ? previous_s2_pred_full_pred_1_targets_0 + : 41'h0) + | (~_s3_redirect_on_target_dup_T_70 + & _s3_redirect_on_target_dup_T_74 + & previous_s2_pred_full_pred_1_hit + ? previous_s2_pred_full_pred_1_targets_1 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_74, + _s3_redirect_on_target_dup_T_70} == 2'h0 + & previous_s2_pred_full_pred_1_hit + ? previous_s2_pred_full_pred_1_fallThroughAddr + : 41'h0) + | (previous_s2_pred_full_pred_1_hit + ? 41'h0 + : 41'(previous_s2_pred_pc_1 + + 41'h20))) + | _predictors_io_out_s3_full_pred_1_hit + & _predictors_io_out_s3_full_pred_1_fallThroughErr); + assign s3_redirect_dup_2 = + s3_valid_dup_3 + & ({_predictors_io_out_s3_full_pred_2_br_taken_mask_1 + & _predictors_io_out_s3_full_pred_2_slot_valids_1 + & _predictors_io_out_s3_full_pred_2_is_br_sharing + & _predictors_io_out_s3_full_pred_2_hit, + _s3_redirect_on_jalr_target_dup_T_48 + & _predictors_io_out_s3_full_pred_2_hit} != {previous_s2_pred_full_pred_2_br_taken_mask_1 + & previous_s2_pred_full_pred_2_slot_valids_1 + & previous_s2_pred_full_pred_2_is_br_sharing + & previous_s2_pred_full_pred_2_hit, + _s3_redirect_on_target_dup_T_84 + & previous_s2_pred_full_pred_2_hit} + & ~(_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit + & _s3_redirect_on_target_dup_T_84 & previous_s2_pred_full_pred_2_hit) + | ((_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit + ? _predictors_io_out_s3_full_pred_2_targets_0 + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_48 & _s3_redirect_on_target_dup_T_32 + & _predictors_io_out_s3_full_pred_2_hit + ? _predictors_io_out_s3_full_pred_2_targets_1 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_32, + _s3_redirect_on_jalr_target_dup_T_48} == 2'h0 + & _predictors_io_out_s3_full_pred_2_hit + ? _predictors_io_out_s3_full_pred_2_fallThroughAddr + : 41'h0) + | (_predictors_io_out_s3_full_pred_2_hit + ? 41'h0 + : _s3_redirect_on_target_dup_T_33)) != ((_s3_redirect_on_target_dup_T_84 + & previous_s2_pred_full_pred_2_hit + ? previous_s2_pred_full_pred_2_targets_0 + : 41'h0) + | (~_s3_redirect_on_target_dup_T_84 + & _s3_redirect_on_target_dup_T_88 + & previous_s2_pred_full_pred_2_hit + ? previous_s2_pred_full_pred_2_targets_1 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_88, + _s3_redirect_on_target_dup_T_84} == 2'h0 + & previous_s2_pred_full_pred_2_hit + ? previous_s2_pred_full_pred_2_fallThroughAddr + : 41'h0) + | (previous_s2_pred_full_pred_2_hit + ? 41'h0 + : 41'(previous_s2_pred_pc_2 + + 41'h20))) + | _predictors_io_out_s3_full_pred_2_hit + & _predictors_io_out_s3_full_pred_2_fallThroughErr); + assign s3_redirect_dup_3 = + s3_valid_dup_3 + & ({_predictors_io_out_s3_full_pred_3_br_taken_mask_1 + & _predictors_io_out_s3_full_pred_3_slot_valids_1 + & _predictors_io_out_s3_full_pred_3_is_br_sharing + & _predictors_io_out_s3_full_pred_3_hit, + _s3_redirect_on_jalr_target_dup_T_68 + & _predictors_io_out_s3_full_pred_3_hit} != {previous_s2_pred_full_pred_3_br_taken_mask_1 + & previous_s2_pred_full_pred_3_slot_valids_1 + & previous_s2_pred_full_pred_3_is_br_sharing + & previous_s2_pred_full_pred_3_hit, + _s3_redirect_on_target_dup_T_98 + & previous_s2_pred_full_pred_3_hit} + & ~(_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit + & _s3_redirect_on_target_dup_T_98 & previous_s2_pred_full_pred_3_hit) + | ((_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit + ? _predictors_io_out_s3_full_pred_3_targets_0 + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_68 & _s3_redirect_on_target_dup_T_46 + & _predictors_io_out_s3_full_pred_3_hit + ? _predictors_io_out_s3_full_pred_3_targets_1 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_46, + _s3_redirect_on_jalr_target_dup_T_68} == 2'h0 + & _predictors_io_out_s3_full_pred_3_hit + ? _predictors_io_out_s3_full_pred_3_fallThroughAddr + : 41'h0) + | (_predictors_io_out_s3_full_pred_3_hit + ? 41'h0 + : _s3_redirect_on_target_dup_T_47)) != ((_s3_redirect_on_target_dup_T_98 + & previous_s2_pred_full_pred_3_hit + ? previous_s2_pred_full_pred_3_targets_0 + : 41'h0) + | (~_s3_redirect_on_target_dup_T_98 + & _s3_redirect_on_target_dup_T_102 + & previous_s2_pred_full_pred_3_hit + ? previous_s2_pred_full_pred_3_targets_1 + : 41'h0) + | ({_s3_redirect_on_target_dup_T_102, + _s3_redirect_on_target_dup_T_98} == 2'h0 + & previous_s2_pred_full_pred_3_hit + ? previous_s2_pred_full_pred_3_fallThroughAddr + : 41'h0) + | (previous_s2_pred_full_pred_3_hit + ? 41'h0 + : 41'(previous_s2_pred_pc_3 + + 41'h20))) + | _predictors_io_out_s3_full_pred_3_hit + & _predictors_io_out_s3_full_pred_3_fallThroughErr); + wire _GEN_32 = + _predictors_io_out_s3_full_pred_0_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_9 + | ~_predictors_io_out_s3_full_pred_0_is_br_sharing); + wire _GEN_33 = + _predictors_io_out_s3_full_pred_1_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_29 + | ~_predictors_io_out_s3_full_pred_1_is_br_sharing); + wire _GEN_34 = + _predictors_io_out_s3_full_pred_2_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_49 + | ~_predictors_io_out_s3_full_pred_2_is_br_sharing); + wire _GEN_35 = + _predictors_io_out_s3_full_pred_3_slot_valids_1 + & (_s3_redirect_on_jalr_target_dup_T_69 + | ~_predictors_io_out_s3_full_pred_3_is_br_sharing); + wire _GEN_36 = + _s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit; + wire _GEN_37 = + _s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit; + wire _GEN_38 = + _s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit; + wire _ghv_wens_0_T_2 = + ~(|s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_1_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_2_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_3_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_4_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_5_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_6_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_7_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_8_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_9_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_10_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_11_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_12_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_13_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_14_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_15_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h10 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_16_T_2 = + s3_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h11 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_17_T_2 = + s3_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h12 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_18_T_2 = + s3_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h13 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_19_T_2 = + s3_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h14 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_20_T_2 = + s3_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h15 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_21_T_2 = + s3_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h16 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_22_T_2 = + s3_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h17 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_23_T_2 = + s3_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h18 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_24_T_2 = + s3_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h19 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_25_T_2 = + s3_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_26_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_27_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_28_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_29_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_30_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_31_T_2 = + s3_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h20 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_32_T_2 = + s3_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h21 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_33_T_2 = + s3_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h22 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_34_T_2 = + s3_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h23 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_35_T_2 = + s3_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h24 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_36_T_2 = + s3_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h25 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_37_T_2 = + s3_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h26 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_38_T_2 = + s3_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h27 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_39_T_2 = + s3_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h28 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_40_T_2 = + s3_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h29 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_41_T_2 = + s3_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_42_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_43_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_44_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_45_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_46_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_47_T_2 = + s3_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h30 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_48_T_2 = + s3_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h31 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_49_T_2 = + s3_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h32 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_50_T_2 = + s3_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h33 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_51_T_2 = + s3_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h34 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_52_T_2 = + s3_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h35 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_53_T_2 = + s3_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h36 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_54_T_2 = + s3_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h37 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_55_T_2 = + s3_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h38 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_56_T_2 = + s3_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h39 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_57_T_2 = + s3_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_58_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_59_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_60_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_61_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_62_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_63_T_2 = + s3_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h40 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_64_T_2 = + s3_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h41 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_65_T_2 = + s3_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h42 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_66_T_2 = + s3_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h43 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_67_T_2 = + s3_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h44 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_68_T_2 = + s3_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h45 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_69_T_2 = + s3_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h46 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_70_T_2 = + s3_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h47 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_71_T_2 = + s3_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h48 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_72_T_2 = + s3_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h49 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_73_T_2 = + s3_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_74_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_75_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_76_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_77_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_78_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_79_T_2 = + s3_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h50 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_80_T_2 = + s3_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h51 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_81_T_2 = + s3_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h52 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_82_T_2 = + s3_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h53 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_83_T_2 = + s3_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h54 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_84_T_2 = + s3_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h55 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_85_T_2 = + s3_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h56 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_86_T_2 = + s3_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h57 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_87_T_2 = + s3_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h58 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_88_T_2 = + s3_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h59 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_89_T_2 = + s3_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_90_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_91_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_92_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_93_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_94_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_95_T_2 = + s3_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h60 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_96_T_2 = + s3_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h61 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_97_T_2 = + s3_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h62 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_98_T_2 = + s3_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h63 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_99_T_2 = + s3_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h64 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_100_T_2 = + s3_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h65 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_101_T_2 = + s3_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h66 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_102_T_2 = + s3_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h67 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_103_T_2 = + s3_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h68 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_104_T_2 = + s3_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h69 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_105_T_2 = + s3_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_106_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_107_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_108_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_109_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_110_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_111_T_2 = + s3_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h70 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_112_T_2 = + s3_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h71 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_113_T_2 = + s3_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h72 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_114_T_2 = + s3_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h73 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_115_T_2 = + s3_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h74 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_116_T_2 = + s3_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h75 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_117_T_2 = + s3_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h76 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_118_T_2 = + s3_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h77 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_119_T_2 = + s3_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h78 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_120_T_2 = + s3_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h79 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_121_T_2 = + s3_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_122_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_123_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_124_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_125_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_126_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_127_T_2 = + s3_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h80 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_128_T_2 = + s3_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h81 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_129_T_2 = + s3_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h82 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_130_T_2 = + s3_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h83 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_131_T_2 = + s3_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h84 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_132_T_2 = + s3_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h85 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_133_T_2 = + s3_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h86 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_134_T_2 = + s3_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h87 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_135_T_2 = + s3_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h88 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_136_T_2 = + s3_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h89 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_137_T_2 = + s3_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_138_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_139_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_140_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_141_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_142_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_143_T_2 = + s3_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h90 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_144_T_2 = + s3_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h91 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_145_T_2 = + s3_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h92 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_146_T_2 = + s3_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h93 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_147_T_2 = + s3_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h94 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_148_T_2 = + s3_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h95 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_149_T_2 = + s3_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h96 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_150_T_2 = + s3_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h97 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_151_T_2 = + s3_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h98 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_152_T_2 = + s3_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h99 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_153_T_2 = + s3_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_154_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_155_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_156_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_157_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_158_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_159_T_2 = + s3_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_160_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_161_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_162_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_163_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_164_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_165_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_166_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_167_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_168_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_169_T_2 = + s3_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_170_T_2 = + s3_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_171_T_2 = + s3_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_172_T_2 = + s3_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_173_T_2 = + s3_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_174_T_2 = + s3_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_175_T_2 = + s3_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_176_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_177_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_178_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_179_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_180_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_181_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_182_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_183_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_184_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_185_T_2 = + s3_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_186_T_2 = + s3_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_187_T_2 = + s3_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_188_T_2 = + s3_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_189_T_2 = + s3_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_190_T_2 = + s3_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_191_T_2 = + s3_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_192_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_193_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_194_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_195_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_196_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_197_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_198_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_199_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_200_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_201_T_2 = + s3_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_202_T_2 = + s3_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_203_T_2 = + s3_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_204_T_2 = + s3_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_205_T_2 = + s3_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_206_T_2 = + s3_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_207_T_2 = + s3_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_208_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_209_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_210_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_211_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_212_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_213_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_214_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_215_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_216_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_217_T_2 = + s3_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_218_T_2 = + s3_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_219_T_2 = + s3_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_220_T_2 = + s3_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_221_T_2 = + s3_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_222_T_2 = + s3_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_223_T_2 = + s3_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_224_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_225_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_226_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_227_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_228_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_229_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_230_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_231_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_232_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_233_T_2 = + s3_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_234_T_2 = + s3_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_235_T_2 = + s3_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_236_T_2 = + s3_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hED & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_237_T_2 = + s3_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_238_T_2 = + s3_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_239_T_2 = + s3_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_240_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_241_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_242_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_243_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_244_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_245_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_246_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_247_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_248_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_249_T_2 = + s3_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_250_T_2 = + s3_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_251_T_2 = + s3_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_252_T_2 = + s3_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_253_T_2 = + s3_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_254_T_2 = + s3_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | (&s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + wire _ghv_wens_255_T_2 = + (&s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & s3_redirect_dup_0 | ~(|s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & s3_redirect_dup_0; + reg s2_ftq_idx_flag; + reg [5:0] s2_ftq_idx_value; + reg s3_ftq_idx_flag; + reg [5:0] s3_ftq_idx_value; + reg predictors_io_update_valid_REG; + reg [40:0] predictors_io_update_bits_r_pc; + reg [10:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_17_folded_hist; + reg [10:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_16_folded_hist; + reg [6:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_15_folded_hist; + reg [7:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_14_folded_hist; + reg [8:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_13_folded_hist; + reg [3:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_12_folded_hist; + reg [7:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_11_folded_hist; + reg [8:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_10_folded_hist; + reg [6:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_9_folded_hist; + reg [7:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_8_folded_hist; + reg [6:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_7_folded_hist; + reg [8:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_6_folded_hist; + reg [6:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_5_folded_hist; + reg [7:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_4_folded_hist; + reg [7:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_3_folded_hist; + reg [7:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_2_folded_hist; + reg [10:0] predictors_io_update_bits_r_spec_info_folded_hist_hist_1_folded_hist; + reg predictors_io_update_bits_r_ftb_entry_valid; + reg [3:0] predictors_io_update_bits_r_ftb_entry_brSlots_0_offset; + reg [11:0] predictors_io_update_bits_r_ftb_entry_brSlots_0_lower; + reg [1:0] predictors_io_update_bits_r_ftb_entry_brSlots_0_tarStat; + reg predictors_io_update_bits_r_ftb_entry_brSlots_0_sharing; + reg predictors_io_update_bits_r_ftb_entry_brSlots_0_valid; + reg [3:0] predictors_io_update_bits_r_ftb_entry_tailSlot_offset; + reg [19:0] predictors_io_update_bits_r_ftb_entry_tailSlot_lower; + reg [1:0] predictors_io_update_bits_r_ftb_entry_tailSlot_tarStat; + reg predictors_io_update_bits_r_ftb_entry_tailSlot_sharing; + reg predictors_io_update_bits_r_ftb_entry_tailSlot_valid; + reg [3:0] predictors_io_update_bits_r_ftb_entry_pftAddr; + reg predictors_io_update_bits_r_ftb_entry_carry; + reg predictors_io_update_bits_r_ftb_entry_isCall; + reg predictors_io_update_bits_r_ftb_entry_isRet; + reg predictors_io_update_bits_r_ftb_entry_isJalr; + reg predictors_io_update_bits_r_ftb_entry_last_may_be_rvi_call; + reg predictors_io_update_bits_r_ftb_entry_always_taken_0; + reg predictors_io_update_bits_r_ftb_entry_always_taken_1; + reg predictors_io_update_bits_r_cfi_idx_valid; + reg [3:0] predictors_io_update_bits_r_cfi_idx_bits; + reg predictors_io_update_bits_r_br_taken_mask_0; + reg predictors_io_update_bits_r_br_taken_mask_1; + reg predictors_io_update_bits_r_jmp_taken; + reg predictors_io_update_bits_r_mispred_mask_0; + reg predictors_io_update_bits_r_mispred_mask_1; + reg predictors_io_update_bits_r_mispred_mask_2; + reg predictors_io_update_bits_r_old_entry; + reg [222:0] predictors_io_update_bits_r_meta; + reg [40:0] predictors_io_update_bits_r_full_target; + wire [1:0] _shouldShiftVec_dup_T_46 = + 2'(do_redirect_dup_next_bits_r_cfiUpdate_shift - 2'h1); + wire [3:0] _shouldShiftVec_dup_T_4 = 4'h1 << _shouldShiftVec_dup_T_46; + wire [1:0] _GEN_39 = _shouldShiftVec_dup_T_4[1:0] | _shouldShiftVec_dup_T_4[2:1]; + wire shouldShiftVec_dup_0_0 = + (|do_redirect_dup_next_bits_r_cfiUpdate_shift) + & (_GEN_39[0] | _shouldShiftVec_dup_T_46 == 2'h2 | (&_shouldShiftVec_dup_T_46)); + wire shouldShiftVec_dup_0_1 = + (|do_redirect_dup_next_bits_r_cfiUpdate_shift) + & (_GEN_39[1] | (&_shouldShiftVec_dup_T_46)); + wire real_br_taken_mask_dup_0_0 = + do_redirect_dup_next_bits_r_cfiUpdate_shift == 2'h1 + & do_redirect_dup_next_bits_r_cfiUpdate_taken + & do_redirect_dup_next_bits_r_cfiUpdate_addIntoHist; + wire real_br_taken_mask_dup_0_1 = + do_redirect_dup_next_bits_r_cfiUpdate_shift == 2'h2 + & do_redirect_dup_next_bits_r_cfiUpdate_taken + & do_redirect_dup_next_bits_r_cfiUpdate_addIntoHist; + wire [8:0] _updated_ptr_dup_flipped_new_ptr_T_6 = + 9'(9'h100 - {7'h0, do_redirect_dup_next_bits_r_cfiUpdate_shift}); + wire [8:0] _GEN_40 = + {do_redirect_dup_next_bits_r_cfiUpdate_histPtr_flag, + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value}; + wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_T_1 = + 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); + wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_T_6 = + 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); + wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_T_11 = + 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); + wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_T_16 = + 9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); + wire _updated_ghist_1_T = + do_redirect_dup_next_bits_r_cfiUpdate_taken + & do_redirect_dup_next_bits_r_cfiUpdate_addIntoHist; + wire _GEN_41 = + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[0] + | _updated_ghist_1_T; + wire [7:0] updated_fh_dup_res_hist_0_fh_3_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; + wire _GEN_42 = + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[0] + | _updated_ghist_1_T; + wire [3:0] updated_fh_dup_res_hist_12_fh_3_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; + wire _GEN_43 = + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[0] + | _updated_ghist_1_T; + wire [7:0] updated_fh_dup_res_hist_14_fh_3_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; + wire [7:0] updated_fh_dup_res_hist_0_fh_6_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; + wire [3:0] updated_fh_dup_res_hist_12_fh_6_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; + wire [7:0] updated_fh_dup_res_hist_14_fh_6_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; + wire [7:0] updated_fh_dup_res_hist_0_fh_9_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; + wire [3:0] updated_fh_dup_res_hist_12_fh_9_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; + wire [7:0] updated_fh_dup_res_hist_14_fh_9_folded_hist = + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; + wire [3:0] _GEN_44 = {2'h0, do_redirect_dup_next_bits_r_cfiUpdate_shift}; + wire [3:0] _thisBrNumOH_dup_T_1 = 4'h1 << _GEN_44; + wire [3:0] _thisBrNumOH_dup_T_2 = 4'h1 << _GEN_44; + wire [3:0] _thisBrNumOH_dup_T_3 = 4'h1 << _GEN_44; + wire thisAheadFhOb_dup_1_afhob_0_bits_0 = + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hA)]; + wire thisAheadFhOb_dup_1_afhob_0_bits_2 = + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h8)]; + wire thisAheadFhOb_dup_1_afhob_0_bits_3 = + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h7)]; + wire thisAheadFhOb_dup_1_afhob_1_bits_0 = + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hD)]; + wire thisAheadFhOb_dup_2_afhob_0_bits_0 = + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hA)]; + wire thisAheadFhOb_dup_2_afhob_0_bits_2 = + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h8)]; + wire thisAheadFhOb_dup_2_afhob_0_bits_3 = + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h7)]; + wire thisAheadFhOb_dup_2_afhob_1_bits_0 = + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hD)]; + wire thisAheadFhOb_dup_3_afhob_0_bits_0 = + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hA)]; + wire thisAheadFhOb_dup_3_afhob_0_bits_2 = + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h8)]; + wire thisAheadFhOb_dup_3_afhob_0_bits_3 = + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h7)]; + wire thisAheadFhOb_dup_3_afhob_1_bits_0 = + _GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hD)]; + wire _ghv_wens_0_T_3 = + ~(|do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_1_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_2_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_3_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_4_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_5_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_6_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_7_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_8_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9 & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_9_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_10_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_11_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_12_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_13_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_14_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_15_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h10 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_16_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h10 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h11 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_17_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h11 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h12 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_18_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h12 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h13 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_19_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h13 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h14 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_20_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h14 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h15 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_21_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h15 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h16 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_22_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h16 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h17 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_23_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h17 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h18 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_24_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h18 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h19 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_25_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h19 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_26_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_27_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_28_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_29_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_30_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_31_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h20 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_32_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h20 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h21 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_33_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h21 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h22 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_34_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h22 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h23 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_35_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h23 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h24 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_36_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h24 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h25 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_37_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h25 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h26 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_38_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h26 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h27 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_39_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h27 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h28 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_40_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h28 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h29 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_41_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h29 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_42_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_43_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_44_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_45_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_46_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_47_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h30 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_48_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h30 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h31 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_49_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h31 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h32 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_50_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h32 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h33 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_51_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h33 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h34 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_52_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h34 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h35 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_53_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h35 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h36 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_54_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h36 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h37 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_55_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h37 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h38 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_56_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h38 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h39 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_57_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h39 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_58_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_59_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_60_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_61_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_62_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_63_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h40 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_64_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h40 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h41 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_65_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h41 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h42 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_66_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h42 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h43 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_67_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h43 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h44 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_68_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h44 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h45 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_69_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h45 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h46 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_70_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h46 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h47 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_71_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h47 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h48 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_72_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h48 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h49 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_73_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h49 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_74_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_75_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_76_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_77_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_78_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_79_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h50 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_80_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h50 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h51 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_81_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h51 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h52 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_82_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h52 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h53 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_83_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h53 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h54 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_84_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h54 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h55 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_85_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h55 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h56 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_86_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h56 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h57 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_87_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h57 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h58 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_88_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h58 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h59 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_89_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h59 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_90_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_91_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_92_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_93_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_94_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_95_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h60 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_96_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h60 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h61 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_97_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h61 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h62 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_98_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h62 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h63 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_99_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h63 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h64 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_100_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h64 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h65 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_101_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h65 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h66 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_102_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h66 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h67 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_103_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h67 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h68 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_104_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h68 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h69 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_105_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h69 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_106_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_107_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_108_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_109_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_110_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_111_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h70 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_112_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h70 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h71 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_113_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h71 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h72 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_114_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h72 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h73 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_115_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h73 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h74 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_116_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h74 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h75 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_117_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h75 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h76 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_118_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h76 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h77 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_119_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h77 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h78 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_120_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h78 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h79 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_121_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h79 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_122_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_123_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_124_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_125_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_126_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_127_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h80 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_128_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h80 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h81 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_129_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h81 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h82 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_130_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h82 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h83 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_131_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h83 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h84 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_132_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h84 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h85 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_133_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h85 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h86 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_134_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h86 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h87 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_135_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h87 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h88 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_136_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h88 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h89 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_137_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h89 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_138_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_139_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_140_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_141_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_142_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_143_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h90 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_144_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h90 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h91 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_145_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h91 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h92 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_146_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h92 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h93 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_147_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h93 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h94 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_148_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h94 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h95 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_149_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h95 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h96 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_150_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h96 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h97 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_151_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h97 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h98 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_152_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h98 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h99 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_153_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h99 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9A + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_154_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9A & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9B + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_155_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9B & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9C + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_156_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9C & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9D + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_157_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9D & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9E + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_158_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9E & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9F + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_159_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9F & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_160_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_161_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_162_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_163_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_164_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_165_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_166_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_167_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_168_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_169_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAA + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_170_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAB + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_171_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAC + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_172_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAD + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_173_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAD & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAE + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_174_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAF + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_175_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAF & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_176_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_177_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_178_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_179_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_180_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_181_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_182_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_183_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_184_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_185_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBA + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_186_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBB + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_187_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBC + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_188_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBD + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_189_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBD & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBE + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_190_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBF + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_191_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBF & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_192_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_193_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_194_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_195_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_196_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_197_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_198_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_199_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_200_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_201_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCA + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_202_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCB + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_203_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCC + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_204_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCD + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_205_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCD & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCE + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_206_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCF + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_207_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCF & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_208_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_209_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_210_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_211_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_212_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_213_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_214_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_215_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_216_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_217_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDA + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_218_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDB + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_219_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDC + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_220_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDD + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_221_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDD & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDE + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_222_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDF + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_223_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDF & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_224_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_225_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_226_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_227_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_228_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_229_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_230_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_231_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_232_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_233_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEA + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_234_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEB + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_235_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEC + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_236_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hED + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_237_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hED & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEE + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_238_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEF + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_239_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEF & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF0 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_240_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF0 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF1 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_241_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF1 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF2 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_242_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF2 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF3 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_243_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF3 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF4 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_244_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF4 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF5 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_245_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF5 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF6 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_246_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF6 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF7 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_247_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF7 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF8 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_248_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF8 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF9 + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_249_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF9 & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFA + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_250_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFA & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFB + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_251_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFB & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFC + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_252_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFC & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFD + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_253_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFD & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFE + & shouldShiftVec_dup_0_1 & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_254_T_3 = + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFE & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | (&do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire _ghv_wens_255_T_3 = + (&do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 + & do_redirect_dup_next_valid_last_r + | ~(|do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_1 + & do_redirect_dup_next_valid_last_r; + wire [3:0][10:0] _GEN_45 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[8], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[7:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[10], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[9]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[9], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[8:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist}}; + wire [3:0][10:0] _GEN_46 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[8], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[7], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[6:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[10], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[9]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[9], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[8], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[7:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist}}; + wire [3:0][6:0] _GEN_47 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[3:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[6], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[5]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[4:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist}}; + wire [3:0][7:0] _GEN_48 = + {{updated_fh_dup_res_hist_14_fh_3_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[5:0], + 1'h0, + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[6:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_14_fh_3_folded_hist}}; + wire [3:0][8:0] _GEN_49 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[6:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[3], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[2], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[1:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[7:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[2:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist}}; + wire [3:0][3:0] _GEN_50 = + {{updated_fh_dup_res_hist_12_fh_3_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[1:0], + 1'h0, + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[2:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_12_fh_3_folded_hist}}; + wire [3:0][7:0] _GEN_51 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[5:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[7], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[6:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[1], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist}}; + wire [3:0][8:0] _GEN_52 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[6:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[2:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[7:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[3:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist}}; + wire [3:0][6:0] _GEN_53 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[3], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[2], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[1:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[6], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[5:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[2:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist}}; + wire [3:0][7:0] _GEN_54 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[4:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[6]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[6], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[5:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist}}; + wire [3:0][6:0] _GEN_55 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[4:1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[0], + 1'h0, + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[5:1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist}}; + wire [3:0][8:0] _GEN_56 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[6], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[4:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[7], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[6], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[5:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist}}; + wire [3:0][6:0] _GEN_57 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[4:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[6], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[5:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist}}; + wire [3:0][7:0] _GEN_58 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[2:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[7], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[6:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[3:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist}}; + wire [3:0][7:0] _GEN_59 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[5:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[6:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist}}; + wire [3:0][7:0] _GEN_60 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[5:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[6:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist}}; + wire [3:0][10:0] _GEN_61 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[8:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[10], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[9]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[9:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[1], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist}}; + wire [3:0][7:0] _GEN_62 = + {{updated_fh_dup_res_hist_0_fh_3_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[5:0], + 1'h0, + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[6:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_0_fh_3_folded_hist}}; + wire [3:0][10:0] _GEN_63 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[8], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[7:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[10], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[9]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[9], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[8:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist}}; + wire [3:0][10:0] _GEN_64 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[8], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[7], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[6:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[10], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[9]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[9], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[8], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[7:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist}}; + wire [3:0][6:0] _GEN_65 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[3:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[6], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[5]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[4:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist}}; + wire [3:0][7:0] _GEN_66 = + {{updated_fh_dup_res_hist_14_fh_6_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[5:0], + 1'h0, + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[6:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_14_fh_6_folded_hist}}; + wire [3:0][8:0] _GEN_67 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[6:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[3], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[2], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[1:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[7:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[2:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist}}; + wire [3:0][3:0] _GEN_68 = + {{updated_fh_dup_res_hist_12_fh_6_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[1:0], + 1'h0, + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[2:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_12_fh_6_folded_hist}}; + wire [3:0][7:0] _GEN_69 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[5:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[7], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[6:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[1], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist}}; + wire [3:0][8:0] _GEN_70 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[6:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[2:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[7:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[3:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist}}; + wire [3:0][6:0] _GEN_71 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[3], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[2], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[1:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[6], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[5:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[2:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist}}; + wire [3:0][7:0] _GEN_72 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[4:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[6]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[6], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[5:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist}}; + wire [3:0][6:0] _GEN_73 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[4:1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[0], + 1'h0, + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[5:1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist}}; + wire [3:0][8:0] _GEN_74 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[6], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[4:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[7], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[6], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[5:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist}}; + wire [3:0][6:0] _GEN_75 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[4:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[6], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[5:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist}}; + wire [3:0][7:0] _GEN_76 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[2:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[7], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[6:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[3:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist}}; + wire [3:0][7:0] _GEN_77 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[5:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[6:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist}}; + wire [3:0][7:0] _GEN_78 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[5:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[6:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist}}; + wire [3:0][10:0] _GEN_79 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[8:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[10], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[9]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[9:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[1], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist}}; + wire [3:0][7:0] _GEN_80 = + {{updated_fh_dup_res_hist_0_fh_6_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[5:0], + 1'h0, + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[6:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_0_fh_6_folded_hist}}; + wire [3:0][10:0] _GEN_81 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[8], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[7:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[10], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[9]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[9], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[8:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist}}; + wire [3:0][10:0] _GEN_82 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[8], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[7], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[6:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[10], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[9]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[9], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[8], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[7:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist}}; + wire [3:0][6:0] _GEN_83 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[3:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[6], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[5]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[4:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist}}; + wire [3:0][7:0] _GEN_84 = + {{updated_fh_dup_res_hist_14_fh_9_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[5:0], + 1'h0, + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist[6:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_14_fh_9_folded_hist}}; + wire [3:0][8:0] _GEN_85 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[6:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[3], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[2], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[1:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[7:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[2:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist}}; + wire [3:0][3:0] _GEN_86 = + {{updated_fh_dup_res_hist_12_fh_9_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[1:0], + 1'h0, + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist[2:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_12_fh_9_folded_hist}}; + wire [3:0][7:0] _GEN_87 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[5:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[7], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[6:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[1], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist}}; + wire [3:0][8:0] _GEN_88 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[6:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[2:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[7:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[3:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist}}; + wire [3:0][6:0] _GEN_89 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[3], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[2], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[1:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[6], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[5:4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[2:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist}}; + wire [3:0][7:0] _GEN_90 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[4:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[6]}}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[6], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[5:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist}}; + wire [3:0][6:0] _GEN_91 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[4:1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[0], + 1'h0, + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[5:1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist}}; + wire [3:0][8:0] _GEN_92 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist}, + {{(do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[6], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[5], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[4:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[8], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[7]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[7], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[6], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[5:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist[8]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist}}; + wire [3:0][6:0] _GEN_93 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[4:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[6], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[5]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[5:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist[6]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist}}; + wire [3:0][7:0] _GEN_94 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[4], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[3], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[2:0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[7], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[6:5], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[4], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[3:0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist}}; + wire [3:0][7:0] _GEN_95 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[5:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[6:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist}}; + wire [3:0][7:0] _GEN_96 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[5:0], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[7], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[6]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[6:0], + _updated_ghist_1_T + ^ (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist[7]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist}}; + wire [3:0][10:0] _GEN_97 = + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[8:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[1], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[0], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[10], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[9]}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[9:2], + (do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[0] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[1] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 + | do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH[2] + & do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2) + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[1], + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[0], + _updated_ghist_1_T + ^ do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist[10]}}, + {do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist}}; + wire [3:0][7:0] _GEN_98 = + {{updated_fh_dup_res_hist_0_fh_9_folded_hist}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[5:0], + 1'h0, + _updated_ghist_1_T}}, + {{do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist[6:0], + _updated_ghist_1_T}}, + {updated_fh_dup_res_hist_0_fh_9_folded_hist}}; + reg [5:0] io_perf_0_value_REG; + reg [5:0] io_perf_0_value_REG_1; + reg [5:0] io_perf_1_value_REG; + reg [5:0] io_perf_1_value_REG_1; + reg [5:0] io_perf_2_value_REG; + reg [5:0] io_perf_2_value_REG_1; + reg [5:0] io_perf_3_value_REG; + reg [5:0] io_perf_3_value_REG_1; + reg [5:0] io_perf_4_value_REG; + reg [5:0] io_perf_4_value_REG_1; + reg [5:0] io_perf_5_value_REG; + reg [5:0] io_perf_5_value_REG_1; + reg [5:0] io_perf_6_value_REG; + reg [5:0] io_perf_6_value_REG_1; + wire _GEN_99 = + s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit; + wire s2_flush_dup_0 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_0; + wire s2_flush_dup_1 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_1; + wire s2_flush_dup_2 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_2; + wire s1_flush_dup_0 = s2_flush_dup_0 | s2_redirect_dup_0; + wire s1_flush_dup_1 = s2_flush_dup_1 | s2_redirect_dup_1; + wire s1_flush_dup_2 = s2_flush_dup_2 | s2_redirect_dup_2; + wire s1_flush_dup_3 = s2_flush_dup_3 | s2_redirect_dup_3; + wire _GEN_100 = s3_valid_dup_3 | io_ftq_to_bpu_redirect_valid; + always @(posedge clock or posedge reset) begin + if (reset) begin + s1_valid_dup_3 <= 1'h0; + s2_valid_dup_3 <= 1'h0; + s3_valid_dup_3 <= 1'h0; + s0_folded_gh_reg_dup_1_hist_17_folded_hist <= 11'h0; + s0_folded_gh_reg_dup_1_hist_16_folded_hist <= 11'h0; + s0_folded_gh_reg_dup_1_hist_15_folded_hist <= 7'h0; + s0_folded_gh_reg_dup_1_hist_14_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_1_hist_13_folded_hist <= 9'h0; + s0_folded_gh_reg_dup_1_hist_12_folded_hist <= 4'h0; + s0_folded_gh_reg_dup_1_hist_11_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_1_hist_10_folded_hist <= 9'h0; + s0_folded_gh_reg_dup_1_hist_9_folded_hist <= 7'h0; + s0_folded_gh_reg_dup_1_hist_8_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_1_hist_7_folded_hist <= 7'h0; + s0_folded_gh_reg_dup_1_hist_6_folded_hist <= 9'h0; + s0_folded_gh_reg_dup_1_hist_5_folded_hist <= 7'h0; + s0_folded_gh_reg_dup_1_hist_4_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_1_hist_3_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_1_hist_2_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_1_hist_1_folded_hist <= 11'h0; + s0_folded_gh_reg_dup_1_hist_0_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_2_hist_17_folded_hist <= 11'h0; + s0_folded_gh_reg_dup_2_hist_16_folded_hist <= 11'h0; + s0_folded_gh_reg_dup_2_hist_15_folded_hist <= 7'h0; + s0_folded_gh_reg_dup_2_hist_14_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_2_hist_13_folded_hist <= 9'h0; + s0_folded_gh_reg_dup_2_hist_12_folded_hist <= 4'h0; + s0_folded_gh_reg_dup_2_hist_11_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_2_hist_10_folded_hist <= 9'h0; + s0_folded_gh_reg_dup_2_hist_9_folded_hist <= 7'h0; + s0_folded_gh_reg_dup_2_hist_8_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_2_hist_7_folded_hist <= 7'h0; + s0_folded_gh_reg_dup_2_hist_6_folded_hist <= 9'h0; + s0_folded_gh_reg_dup_2_hist_5_folded_hist <= 7'h0; + s0_folded_gh_reg_dup_2_hist_4_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_2_hist_3_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_2_hist_2_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_2_hist_1_folded_hist <= 11'h0; + s0_folded_gh_reg_dup_2_hist_0_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_3_hist_17_folded_hist <= 11'h0; + s0_folded_gh_reg_dup_3_hist_16_folded_hist <= 11'h0; + s0_folded_gh_reg_dup_3_hist_15_folded_hist <= 7'h0; + s0_folded_gh_reg_dup_3_hist_14_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_3_hist_13_folded_hist <= 9'h0; + s0_folded_gh_reg_dup_3_hist_12_folded_hist <= 4'h0; + s0_folded_gh_reg_dup_3_hist_11_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_3_hist_10_folded_hist <= 9'h0; + s0_folded_gh_reg_dup_3_hist_9_folded_hist <= 7'h0; + s0_folded_gh_reg_dup_3_hist_8_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_3_hist_7_folded_hist <= 7'h0; + s0_folded_gh_reg_dup_3_hist_6_folded_hist <= 9'h0; + s0_folded_gh_reg_dup_3_hist_5_folded_hist <= 7'h0; + s0_folded_gh_reg_dup_3_hist_4_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_3_hist_3_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_3_hist_2_folded_hist <= 8'h0; + s0_folded_gh_reg_dup_3_hist_1_folded_hist <= 11'h0; + s0_folded_gh_reg_dup_3_hist_0_folded_hist <= 8'h0; + s1_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; + s1_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; + s1_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; + s1_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; + s1_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; + s1_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; + s1_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; + s1_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; + s1_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; + s1_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; + s1_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; + s1_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; + s1_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; + s1_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; + s1_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; + s1_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; + s1_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; + s1_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; + s1_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; + s1_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; + s1_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; + s1_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; + s1_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; + s1_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; + s1_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; + s1_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; + s1_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; + s1_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; + s1_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; + s1_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; + s1_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; + s1_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; + s1_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; + s1_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; + s1_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; + s1_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; + s1_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; + s1_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; + s1_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; + s1_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; + s1_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; + s1_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; + s1_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; + s1_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; + s1_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; + s1_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; + s1_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; + s1_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; + s1_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; + s1_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; + s1_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; + s1_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; + s1_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; + s1_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; + s2_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; + s2_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; + s2_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; + s2_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; + s2_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; + s2_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; + s2_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; + s2_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; + s2_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; + s2_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; + s2_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; + s2_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; + s2_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; + s2_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; + s2_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; + s2_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; + s2_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; + s2_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; + s2_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; + s2_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; + s2_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; + s2_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; + s2_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; + s2_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; + s2_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; + s2_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; + s2_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; + s2_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; + s2_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; + s2_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; + s2_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; + s2_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; + s2_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; + s2_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; + s2_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; + s2_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; + s2_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; + s2_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; + s2_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; + s2_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; + s2_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; + s2_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; + s2_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; + s2_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; + s2_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; + s2_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; + s2_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; + s2_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; + s2_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; + s2_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; + s2_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; + s2_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; + s2_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; + s2_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; + s3_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; + s3_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; + s3_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; + s3_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; + s3_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; + s3_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; + s3_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; + s3_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; + s3_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; + s3_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; + s3_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; + s3_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; + s3_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; + s3_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; + s3_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; + s3_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; + s3_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; + s3_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; + s3_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; + s3_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; + s3_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; + s3_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; + s3_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; + s3_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; + s3_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; + s3_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; + s3_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; + s3_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; + s3_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; + s3_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; + s3_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; + s3_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; + s3_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; + s3_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; + s3_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; + s3_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; + s3_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; + s3_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; + s3_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; + s3_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; + s3_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; + s3_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; + s3_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; + s3_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; + s3_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; + s3_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; + s3_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; + s3_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; + s3_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; + s3_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; + s3_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; + s3_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; + s3_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; + s3_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; + s0_last_br_num_oh_reg_dup_1 <= 3'h0; + s0_last_br_num_oh_reg_dup_2 <= 3'h0; + s0_last_br_num_oh_reg_dup_3 <= 3'h0; + s1_last_br_num_oh_dup_1 <= 3'h0; + s1_last_br_num_oh_dup_2 <= 3'h0; + s1_last_br_num_oh_dup_3 <= 3'h0; + s2_last_br_num_oh_dup_1 <= 3'h0; + s2_last_br_num_oh_dup_2 <= 3'h0; + s2_last_br_num_oh_dup_3 <= 3'h0; + s3_last_br_num_oh_dup_1 <= 3'h0; + s3_last_br_num_oh_dup_2 <= 3'h0; + s3_last_br_num_oh_dup_3 <= 3'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 <= 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; + ghv_0 <= 1'h0; + ghv_1 <= 1'h0; + ghv_2 <= 1'h0; + ghv_3 <= 1'h0; + ghv_4 <= 1'h0; + ghv_5 <= 1'h0; + ghv_6 <= 1'h0; + ghv_7 <= 1'h0; + ghv_8 <= 1'h0; + ghv_9 <= 1'h0; + ghv_10 <= 1'h0; + ghv_11 <= 1'h0; + ghv_12 <= 1'h0; + ghv_13 <= 1'h0; + ghv_14 <= 1'h0; + ghv_15 <= 1'h0; + ghv_16 <= 1'h0; + ghv_17 <= 1'h0; + ghv_18 <= 1'h0; + ghv_19 <= 1'h0; + ghv_20 <= 1'h0; + ghv_21 <= 1'h0; + ghv_22 <= 1'h0; + ghv_23 <= 1'h0; + ghv_24 <= 1'h0; + ghv_25 <= 1'h0; + ghv_26 <= 1'h0; + ghv_27 <= 1'h0; + ghv_28 <= 1'h0; + ghv_29 <= 1'h0; + ghv_30 <= 1'h0; + ghv_31 <= 1'h0; + ghv_32 <= 1'h0; + ghv_33 <= 1'h0; + ghv_34 <= 1'h0; + ghv_35 <= 1'h0; + ghv_36 <= 1'h0; + ghv_37 <= 1'h0; + ghv_38 <= 1'h0; + ghv_39 <= 1'h0; + ghv_40 <= 1'h0; + ghv_41 <= 1'h0; + ghv_42 <= 1'h0; + ghv_43 <= 1'h0; + ghv_44 <= 1'h0; + ghv_45 <= 1'h0; + ghv_46 <= 1'h0; + ghv_47 <= 1'h0; + ghv_48 <= 1'h0; + ghv_49 <= 1'h0; + ghv_50 <= 1'h0; + ghv_51 <= 1'h0; + ghv_52 <= 1'h0; + ghv_53 <= 1'h0; + ghv_54 <= 1'h0; + ghv_55 <= 1'h0; + ghv_56 <= 1'h0; + ghv_57 <= 1'h0; + ghv_58 <= 1'h0; + ghv_59 <= 1'h0; + ghv_60 <= 1'h0; + ghv_61 <= 1'h0; + ghv_62 <= 1'h0; + ghv_63 <= 1'h0; + ghv_64 <= 1'h0; + ghv_65 <= 1'h0; + ghv_66 <= 1'h0; + ghv_67 <= 1'h0; + ghv_68 <= 1'h0; + ghv_69 <= 1'h0; + ghv_70 <= 1'h0; + ghv_71 <= 1'h0; + ghv_72 <= 1'h0; + ghv_73 <= 1'h0; + ghv_74 <= 1'h0; + ghv_75 <= 1'h0; + ghv_76 <= 1'h0; + ghv_77 <= 1'h0; + ghv_78 <= 1'h0; + ghv_79 <= 1'h0; + ghv_80 <= 1'h0; + ghv_81 <= 1'h0; + ghv_82 <= 1'h0; + ghv_83 <= 1'h0; + ghv_84 <= 1'h0; + ghv_85 <= 1'h0; + ghv_86 <= 1'h0; + ghv_87 <= 1'h0; + ghv_88 <= 1'h0; + ghv_89 <= 1'h0; + ghv_90 <= 1'h0; + ghv_91 <= 1'h0; + ghv_92 <= 1'h0; + ghv_93 <= 1'h0; + ghv_94 <= 1'h0; + ghv_95 <= 1'h0; + ghv_96 <= 1'h0; + ghv_97 <= 1'h0; + ghv_98 <= 1'h0; + ghv_99 <= 1'h0; + ghv_100 <= 1'h0; + ghv_101 <= 1'h0; + ghv_102 <= 1'h0; + ghv_103 <= 1'h0; + ghv_104 <= 1'h0; + ghv_105 <= 1'h0; + ghv_106 <= 1'h0; + ghv_107 <= 1'h0; + ghv_108 <= 1'h0; + ghv_109 <= 1'h0; + ghv_110 <= 1'h0; + ghv_111 <= 1'h0; + ghv_112 <= 1'h0; + ghv_113 <= 1'h0; + ghv_114 <= 1'h0; + ghv_115 <= 1'h0; + ghv_116 <= 1'h0; + ghv_117 <= 1'h0; + ghv_118 <= 1'h0; + ghv_119 <= 1'h0; + ghv_120 <= 1'h0; + ghv_121 <= 1'h0; + ghv_122 <= 1'h0; + ghv_123 <= 1'h0; + ghv_124 <= 1'h0; + ghv_125 <= 1'h0; + ghv_126 <= 1'h0; + ghv_127 <= 1'h0; + ghv_128 <= 1'h0; + ghv_129 <= 1'h0; + ghv_130 <= 1'h0; + ghv_131 <= 1'h0; + ghv_132 <= 1'h0; + ghv_133 <= 1'h0; + ghv_134 <= 1'h0; + ghv_135 <= 1'h0; + ghv_136 <= 1'h0; + ghv_137 <= 1'h0; + ghv_138 <= 1'h0; + ghv_139 <= 1'h0; + ghv_140 <= 1'h0; + ghv_141 <= 1'h0; + ghv_142 <= 1'h0; + ghv_143 <= 1'h0; + ghv_144 <= 1'h0; + ghv_145 <= 1'h0; + ghv_146 <= 1'h0; + ghv_147 <= 1'h0; + ghv_148 <= 1'h0; + ghv_149 <= 1'h0; + ghv_150 <= 1'h0; + ghv_151 <= 1'h0; + ghv_152 <= 1'h0; + ghv_153 <= 1'h0; + ghv_154 <= 1'h0; + ghv_155 <= 1'h0; + ghv_156 <= 1'h0; + ghv_157 <= 1'h0; + ghv_158 <= 1'h0; + ghv_159 <= 1'h0; + ghv_160 <= 1'h0; + ghv_161 <= 1'h0; + ghv_162 <= 1'h0; + ghv_163 <= 1'h0; + ghv_164 <= 1'h0; + ghv_165 <= 1'h0; + ghv_166 <= 1'h0; + ghv_167 <= 1'h0; + ghv_168 <= 1'h0; + ghv_169 <= 1'h0; + ghv_170 <= 1'h0; + ghv_171 <= 1'h0; + ghv_172 <= 1'h0; + ghv_173 <= 1'h0; + ghv_174 <= 1'h0; + ghv_175 <= 1'h0; + ghv_176 <= 1'h0; + ghv_177 <= 1'h0; + ghv_178 <= 1'h0; + ghv_179 <= 1'h0; + ghv_180 <= 1'h0; + ghv_181 <= 1'h0; + ghv_182 <= 1'h0; + ghv_183 <= 1'h0; + ghv_184 <= 1'h0; + ghv_185 <= 1'h0; + ghv_186 <= 1'h0; + ghv_187 <= 1'h0; + ghv_188 <= 1'h0; + ghv_189 <= 1'h0; + ghv_190 <= 1'h0; + ghv_191 <= 1'h0; + ghv_192 <= 1'h0; + ghv_193 <= 1'h0; + ghv_194 <= 1'h0; + ghv_195 <= 1'h0; + ghv_196 <= 1'h0; + ghv_197 <= 1'h0; + ghv_198 <= 1'h0; + ghv_199 <= 1'h0; + ghv_200 <= 1'h0; + ghv_201 <= 1'h0; + ghv_202 <= 1'h0; + ghv_203 <= 1'h0; + ghv_204 <= 1'h0; + ghv_205 <= 1'h0; + ghv_206 <= 1'h0; + ghv_207 <= 1'h0; + ghv_208 <= 1'h0; + ghv_209 <= 1'h0; + ghv_210 <= 1'h0; + ghv_211 <= 1'h0; + ghv_212 <= 1'h0; + ghv_213 <= 1'h0; + ghv_214 <= 1'h0; + ghv_215 <= 1'h0; + ghv_216 <= 1'h0; + ghv_217 <= 1'h0; + ghv_218 <= 1'h0; + ghv_219 <= 1'h0; + ghv_220 <= 1'h0; + ghv_221 <= 1'h0; + ghv_222 <= 1'h0; + ghv_223 <= 1'h0; + ghv_224 <= 1'h0; + ghv_225 <= 1'h0; + ghv_226 <= 1'h0; + ghv_227 <= 1'h0; + ghv_228 <= 1'h0; + ghv_229 <= 1'h0; + ghv_230 <= 1'h0; + ghv_231 <= 1'h0; + ghv_232 <= 1'h0; + ghv_233 <= 1'h0; + ghv_234 <= 1'h0; + ghv_235 <= 1'h0; + ghv_236 <= 1'h0; + ghv_237 <= 1'h0; + ghv_238 <= 1'h0; + ghv_239 <= 1'h0; + ghv_240 <= 1'h0; + ghv_241 <= 1'h0; + ghv_242 <= 1'h0; + ghv_243 <= 1'h0; + ghv_244 <= 1'h0; + ghv_245 <= 1'h0; + ghv_246 <= 1'h0; + ghv_247 <= 1'h0; + ghv_248 <= 1'h0; + ghv_249 <= 1'h0; + ghv_250 <= 1'h0; + ghv_251 <= 1'h0; + ghv_252 <= 1'h0; + ghv_253 <= 1'h0; + ghv_254 <= 1'h0; + ghv_255 <= 1'h0; + s0_ghist_ptr_reg_dup_0_flag <= 1'h0; + s0_ghist_ptr_reg_dup_0_value <= 8'h0; + s0_ghist_ptr_reg_dup_1_flag <= 1'h0; + s0_ghist_ptr_reg_dup_1_value <= 8'h0; + s0_ghist_ptr_reg_dup_2_flag <= 1'h0; + s0_ghist_ptr_reg_dup_2_value <= 8'h0; + s0_ghist_ptr_reg_dup_3_flag <= 1'h0; + s0_ghist_ptr_reg_dup_3_value <= 8'h0; + s1_ghist_ptr_dup_0_flag <= 1'h0; + s1_ghist_ptr_dup_0_value <= 8'h0; + s1_ghist_ptr_dup_1_flag <= 1'h0; + s1_ghist_ptr_dup_1_value <= 8'h0; + s1_ghist_ptr_dup_2_flag <= 1'h0; + s1_ghist_ptr_dup_2_value <= 8'h0; + s1_ghist_ptr_dup_3_flag <= 1'h0; + s1_ghist_ptr_dup_3_value <= 8'h0; + s2_ghist_ptr_dup_0_flag <= 1'h0; + s2_ghist_ptr_dup_0_value <= 8'h0; + s2_ghist_ptr_dup_1_flag <= 1'h0; + s2_ghist_ptr_dup_1_value <= 8'h0; + s2_ghist_ptr_dup_2_flag <= 1'h0; + s2_ghist_ptr_dup_2_value <= 8'h0; + s2_ghist_ptr_dup_3_flag <= 1'h0; + s2_ghist_ptr_dup_3_value <= 8'h0; + s3_ghist_ptr_dup_0_flag <= 1'h0; + s3_ghist_ptr_dup_0_value <= 8'h0; + s3_ghist_ptr_dup_1_flag <= 1'h0; + s3_ghist_ptr_dup_1_value <= 8'h0; + s3_ghist_ptr_dup_2_flag <= 1'h0; + s3_ghist_ptr_dup_2_value <= 8'h0; + s3_ghist_ptr_dup_3_flag <= 1'h0; + s3_ghist_ptr_dup_3_value <= 8'h0; + do_redirect_dup_next_valid_last_r <= 1'h0; + previous_s1_pred_info_hit_0 <= 1'h0; + previous_s1_pred_info_hit_1 <= 1'h0; + previous_s1_pred_info_hit_2 <= 1'h0; + previous_s1_pred_info_hit_3 <= 1'h0; + previous_s1_pred_info_target_0 <= 41'h0; + previous_s1_pred_info_target_1 <= 41'h0; + previous_s1_pred_info_target_2 <= 41'h0; + previous_s1_pred_info_target_3 <= 41'h0; + previous_s1_pred_info_lastBrPosOH_0_0 <= 1'h0; + previous_s1_pred_info_lastBrPosOH_0_1 <= 1'h0; + previous_s1_pred_info_lastBrPosOH_0_2 <= 1'h0; + previous_s1_pred_info_lastBrPosOH_1_0 <= 1'h0; + previous_s1_pred_info_lastBrPosOH_1_1 <= 1'h0; + previous_s1_pred_info_lastBrPosOH_1_2 <= 1'h0; + previous_s1_pred_info_lastBrPosOH_2_0 <= 1'h0; + previous_s1_pred_info_lastBrPosOH_2_1 <= 1'h0; + previous_s1_pred_info_lastBrPosOH_2_2 <= 1'h0; + previous_s1_pred_info_lastBrPosOH_3_0 <= 1'h0; + previous_s1_pred_info_lastBrPosOH_3_1 <= 1'h0; + previous_s1_pred_info_lastBrPosOH_3_2 <= 1'h0; + previous_s1_pred_info_taken_0 <= 1'h0; + previous_s1_pred_info_taken_1 <= 1'h0; + previous_s1_pred_info_taken_2 <= 1'h0; + previous_s1_pred_info_taken_3 <= 1'h0; + previous_s1_pred_info_takenMask_0_0 <= 1'h0; + previous_s1_pred_info_takenMask_0_1 <= 1'h0; + previous_s1_pred_info_takenMask_1_0 <= 1'h0; + previous_s1_pred_info_takenMask_1_1 <= 1'h0; + previous_s1_pred_info_takenMask_2_0 <= 1'h0; + previous_s1_pred_info_takenMask_2_1 <= 1'h0; + previous_s1_pred_info_takenMask_3_0 <= 1'h0; + previous_s1_pred_info_takenMask_3_1 <= 1'h0; + previous_s1_pred_info_cfiIndex_0 <= 4'h0; + previous_s1_pred_info_cfiIndex_1 <= 4'h0; + previous_s1_pred_info_cfiIndex_2 <= 4'h0; + previous_s1_pred_info_cfiIndex_3 <= 4'h0; + previous_s2_pred_pc_0 <= 41'h0; + previous_s2_pred_pc_1 <= 41'h0; + previous_s2_pred_pc_2 <= 41'h0; + previous_s2_pred_pc_3 <= 41'h0; + previous_s2_pred_full_pred_0_br_taken_mask_0 <= 1'h0; + previous_s2_pred_full_pred_0_br_taken_mask_1 <= 1'h0; + previous_s2_pred_full_pred_0_slot_valids_0 <= 1'h0; + previous_s2_pred_full_pred_0_slot_valids_1 <= 1'h0; + previous_s2_pred_full_pred_0_targets_0 <= 41'h0; + previous_s2_pred_full_pred_0_targets_1 <= 41'h0; + previous_s2_pred_full_pred_0_fallThroughAddr <= 41'h0; + previous_s2_pred_full_pred_0_is_br_sharing <= 1'h0; + previous_s2_pred_full_pred_0_hit <= 1'h0; + previous_s2_pred_full_pred_1_br_taken_mask_0 <= 1'h0; + previous_s2_pred_full_pred_1_br_taken_mask_1 <= 1'h0; + previous_s2_pred_full_pred_1_slot_valids_0 <= 1'h0; + previous_s2_pred_full_pred_1_slot_valids_1 <= 1'h0; + previous_s2_pred_full_pred_1_targets_0 <= 41'h0; + previous_s2_pred_full_pred_1_targets_1 <= 41'h0; + previous_s2_pred_full_pred_1_fallThroughAddr <= 41'h0; + previous_s2_pred_full_pred_1_is_br_sharing <= 1'h0; + previous_s2_pred_full_pred_1_hit <= 1'h0; + previous_s2_pred_full_pred_2_br_taken_mask_0 <= 1'h0; + previous_s2_pred_full_pred_2_br_taken_mask_1 <= 1'h0; + previous_s2_pred_full_pred_2_slot_valids_0 <= 1'h0; + previous_s2_pred_full_pred_2_slot_valids_1 <= 1'h0; + previous_s2_pred_full_pred_2_targets_0 <= 41'h0; + previous_s2_pred_full_pred_2_targets_1 <= 41'h0; + previous_s2_pred_full_pred_2_fallThroughAddr <= 41'h0; + previous_s2_pred_full_pred_2_is_br_sharing <= 1'h0; + previous_s2_pred_full_pred_2_hit <= 1'h0; + previous_s2_pred_full_pred_3_br_taken_mask_0 <= 1'h0; + previous_s2_pred_full_pred_3_br_taken_mask_1 <= 1'h0; + previous_s2_pred_full_pred_3_slot_valids_0 <= 1'h0; + previous_s2_pred_full_pred_3_slot_valids_1 <= 1'h0; + previous_s2_pred_full_pred_3_targets_0 <= 41'h0; + previous_s2_pred_full_pred_3_targets_1 <= 41'h0; + previous_s2_pred_full_pred_3_fallThroughAddr <= 41'h0; + previous_s2_pred_full_pred_3_is_br_sharing <= 1'h0; + previous_s2_pred_full_pred_3_hit <= 1'h0; + predictors_io_update_valid_REG <= 1'h0; + end + else begin + s1_valid_dup_3 <= + ~io_ftq_to_bpu_redirect_valid + & (s0_fire_dup_3 + | ~(s1_flush_dup_3 | s1_fire_dup_3 | io_ftq_to_bpu_redirect_valid) + & (s0_fire_dup_2 + | ~(s1_flush_dup_2 | s1_fire_dup_2 | io_ftq_to_bpu_redirect_valid) + & (s0_fire_dup_1 + | ~(s1_flush_dup_1 | s1_fire_dup_1 | io_ftq_to_bpu_redirect_valid) + & (s0_fire_dup_0 | ~(s1_flush_dup_0 | s1_fire_dup_0) + & s1_valid_dup_3)))); + s2_valid_dup_3 <= + ~s2_flush_dup_3 + & (s1_fire_dup_3 + ? ~s1_flush_dup_3 + : ~(s2_valid_dup_3 | s2_flush_dup_2) + & (s1_fire_dup_2 + ? ~s1_flush_dup_2 + : ~(s2_valid_dup_3 | s2_flush_dup_1) + & (s1_fire_dup_1 + ? ~s1_flush_dup_1 + : ~(s2_valid_dup_3 | s2_flush_dup_0) & s1_fire_dup_0 + & ~s1_flush_dup_0))); + s3_valid_dup_3 <= + ~io_ftq_to_bpu_redirect_valid + & (s2_valid_dup_3 + ? ~s2_flush_dup_3 + : ~_GEN_100 + & (s2_valid_dup_3 + ? ~s2_flush_dup_2 + : ~_GEN_100 + & (s2_valid_dup_3 + ? ~s2_flush_dup_1 + : ~_GEN_100 & s2_valid_dup_3 & ~s2_flush_dup_0))); + s0_folded_gh_reg_dup_1_hist_17_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; + s0_folded_gh_reg_dup_1_hist_16_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; + s0_folded_gh_reg_dup_1_hist_15_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; + s0_folded_gh_reg_dup_1_hist_14_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; + s0_folded_gh_reg_dup_1_hist_13_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; + s0_folded_gh_reg_dup_1_hist_12_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; + s0_folded_gh_reg_dup_1_hist_11_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; + s0_folded_gh_reg_dup_1_hist_10_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; + s0_folded_gh_reg_dup_1_hist_9_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; + s0_folded_gh_reg_dup_1_hist_8_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; + s0_folded_gh_reg_dup_1_hist_7_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; + s0_folded_gh_reg_dup_1_hist_6_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; + s0_folded_gh_reg_dup_1_hist_5_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; + s0_folded_gh_reg_dup_1_hist_4_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; + s0_folded_gh_reg_dup_1_hist_3_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; + s0_folded_gh_reg_dup_1_hist_2_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; + s0_folded_gh_reg_dup_1_hist_1_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; + s0_folded_gh_reg_dup_1_hist_0_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; + s0_folded_gh_reg_dup_2_hist_17_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; + s0_folded_gh_reg_dup_2_hist_16_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; + s0_folded_gh_reg_dup_2_hist_15_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; + s0_folded_gh_reg_dup_2_hist_14_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; + s0_folded_gh_reg_dup_2_hist_13_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; + s0_folded_gh_reg_dup_2_hist_12_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; + s0_folded_gh_reg_dup_2_hist_11_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; + s0_folded_gh_reg_dup_2_hist_10_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; + s0_folded_gh_reg_dup_2_hist_9_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; + s0_folded_gh_reg_dup_2_hist_8_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; + s0_folded_gh_reg_dup_2_hist_7_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; + s0_folded_gh_reg_dup_2_hist_6_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; + s0_folded_gh_reg_dup_2_hist_5_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; + s0_folded_gh_reg_dup_2_hist_4_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; + s0_folded_gh_reg_dup_2_hist_3_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; + s0_folded_gh_reg_dup_2_hist_2_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; + s0_folded_gh_reg_dup_2_hist_1_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; + s0_folded_gh_reg_dup_2_hist_0_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; + s0_folded_gh_reg_dup_3_hist_17_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; + s0_folded_gh_reg_dup_3_hist_16_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; + s0_folded_gh_reg_dup_3_hist_15_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; + s0_folded_gh_reg_dup_3_hist_14_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; + s0_folded_gh_reg_dup_3_hist_13_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; + s0_folded_gh_reg_dup_3_hist_12_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; + s0_folded_gh_reg_dup_3_hist_11_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; + s0_folded_gh_reg_dup_3_hist_10_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; + s0_folded_gh_reg_dup_3_hist_9_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; + s0_folded_gh_reg_dup_3_hist_8_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; + s0_folded_gh_reg_dup_3_hist_7_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; + s0_folded_gh_reg_dup_3_hist_6_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; + s0_folded_gh_reg_dup_3_hist_5_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; + s0_folded_gh_reg_dup_3_hist_4_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; + s0_folded_gh_reg_dup_3_hist_3_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; + s0_folded_gh_reg_dup_3_hist_2_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; + s0_folded_gh_reg_dup_3_hist_1_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; + s0_folded_gh_reg_dup_3_hist_0_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; + if (s0_fire_dup_1) begin + s1_folded_gh_dup_1_hist_17_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; + s1_folded_gh_dup_1_hist_16_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; + s1_folded_gh_dup_1_hist_15_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; + s1_folded_gh_dup_1_hist_14_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; + s1_folded_gh_dup_1_hist_13_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; + s1_folded_gh_dup_1_hist_12_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; + s1_folded_gh_dup_1_hist_11_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; + s1_folded_gh_dup_1_hist_10_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; + s1_folded_gh_dup_1_hist_9_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; + s1_folded_gh_dup_1_hist_8_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; + s1_folded_gh_dup_1_hist_7_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; + s1_folded_gh_dup_1_hist_6_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; + s1_folded_gh_dup_1_hist_5_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; + s1_folded_gh_dup_1_hist_4_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; + s1_folded_gh_dup_1_hist_3_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; + s1_folded_gh_dup_1_hist_2_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; + s1_folded_gh_dup_1_hist_1_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; + s1_folded_gh_dup_1_hist_0_folded_hist <= + _s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; + s1_folded_gh_dup_2_hist_17_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; + s1_folded_gh_dup_2_hist_16_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; + s1_folded_gh_dup_2_hist_15_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; + s1_folded_gh_dup_2_hist_14_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; + s1_folded_gh_dup_2_hist_13_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; + s1_folded_gh_dup_2_hist_12_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; + s1_folded_gh_dup_2_hist_11_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; + s1_folded_gh_dup_2_hist_10_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; + s1_folded_gh_dup_2_hist_9_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; + s1_folded_gh_dup_2_hist_8_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; + s1_folded_gh_dup_2_hist_7_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; + s1_folded_gh_dup_2_hist_6_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; + s1_folded_gh_dup_2_hist_5_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; + s1_folded_gh_dup_2_hist_4_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; + s1_folded_gh_dup_2_hist_3_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; + s1_folded_gh_dup_2_hist_2_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; + s1_folded_gh_dup_2_hist_1_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; + s1_folded_gh_dup_2_hist_0_folded_hist <= + _s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; + s1_folded_gh_dup_3_hist_17_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; + s1_folded_gh_dup_3_hist_16_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; + s1_folded_gh_dup_3_hist_15_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; + s1_folded_gh_dup_3_hist_14_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; + s1_folded_gh_dup_3_hist_13_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; + s1_folded_gh_dup_3_hist_12_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; + s1_folded_gh_dup_3_hist_11_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; + s1_folded_gh_dup_3_hist_10_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; + s1_folded_gh_dup_3_hist_9_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; + s1_folded_gh_dup_3_hist_8_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; + s1_folded_gh_dup_3_hist_7_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; + s1_folded_gh_dup_3_hist_6_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; + s1_folded_gh_dup_3_hist_5_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; + s1_folded_gh_dup_3_hist_4_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; + s1_folded_gh_dup_3_hist_3_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; + s1_folded_gh_dup_3_hist_2_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; + s1_folded_gh_dup_3_hist_1_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; + s1_folded_gh_dup_3_hist_0_folded_hist <= + _s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; + s1_last_br_num_oh_dup_1 <= _s0_last_br_num_oh_dup_1_ppm_out_res; + s1_last_br_num_oh_dup_2 <= _s0_last_br_num_oh_dup_2_ppm_out_res; + s1_last_br_num_oh_dup_3 <= _s0_last_br_num_oh_dup_3_ppm_out_res; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; + s1_ghist_ptr_dup_0_flag <= _s0_ghist_ptr_dup_0_ppm_out_res_flag; + s1_ghist_ptr_dup_0_value <= _s0_ghist_ptr_dup_0_ppm_out_res_value; + s1_ghist_ptr_dup_1_flag <= _s0_ghist_ptr_dup_1_ppm_out_res_flag; + s1_ghist_ptr_dup_1_value <= _s0_ghist_ptr_dup_1_ppm_out_res_value; + s1_ghist_ptr_dup_2_flag <= _s0_ghist_ptr_dup_2_ppm_out_res_flag; + s1_ghist_ptr_dup_2_value <= _s0_ghist_ptr_dup_2_ppm_out_res_value; + s1_ghist_ptr_dup_3_flag <= _s0_ghist_ptr_dup_3_ppm_out_res_flag; + s1_ghist_ptr_dup_3_value <= _s0_ghist_ptr_dup_3_ppm_out_res_value; + end + if (s1_fire_dup_1) begin + s2_folded_gh_dup_1_hist_17_folded_hist <= s1_folded_gh_dup_1_hist_17_folded_hist; + s2_folded_gh_dup_1_hist_16_folded_hist <= s1_folded_gh_dup_1_hist_16_folded_hist; + s2_folded_gh_dup_1_hist_15_folded_hist <= s1_folded_gh_dup_1_hist_15_folded_hist; + s2_folded_gh_dup_1_hist_14_folded_hist <= s1_folded_gh_dup_1_hist_14_folded_hist; + s2_folded_gh_dup_1_hist_13_folded_hist <= s1_folded_gh_dup_1_hist_13_folded_hist; + s2_folded_gh_dup_1_hist_12_folded_hist <= s1_folded_gh_dup_1_hist_12_folded_hist; + s2_folded_gh_dup_1_hist_11_folded_hist <= s1_folded_gh_dup_1_hist_11_folded_hist; + s2_folded_gh_dup_1_hist_10_folded_hist <= s1_folded_gh_dup_1_hist_10_folded_hist; + s2_folded_gh_dup_1_hist_9_folded_hist <= s1_folded_gh_dup_1_hist_9_folded_hist; + s2_folded_gh_dup_1_hist_8_folded_hist <= s1_folded_gh_dup_1_hist_8_folded_hist; + s2_folded_gh_dup_1_hist_7_folded_hist <= s1_folded_gh_dup_1_hist_7_folded_hist; + s2_folded_gh_dup_1_hist_6_folded_hist <= s1_folded_gh_dup_1_hist_6_folded_hist; + s2_folded_gh_dup_1_hist_5_folded_hist <= s1_folded_gh_dup_1_hist_5_folded_hist; + s2_folded_gh_dup_1_hist_4_folded_hist <= s1_folded_gh_dup_1_hist_4_folded_hist; + s2_folded_gh_dup_1_hist_3_folded_hist <= s1_folded_gh_dup_1_hist_3_folded_hist; + s2_folded_gh_dup_1_hist_2_folded_hist <= s1_folded_gh_dup_1_hist_2_folded_hist; + s2_folded_gh_dup_1_hist_1_folded_hist <= s1_folded_gh_dup_1_hist_1_folded_hist; + s2_folded_gh_dup_1_hist_0_folded_hist <= s1_folded_gh_dup_1_hist_0_folded_hist; + s2_folded_gh_dup_2_hist_17_folded_hist <= s1_folded_gh_dup_2_hist_17_folded_hist; + s2_folded_gh_dup_2_hist_16_folded_hist <= s1_folded_gh_dup_2_hist_16_folded_hist; + s2_folded_gh_dup_2_hist_15_folded_hist <= s1_folded_gh_dup_2_hist_15_folded_hist; + s2_folded_gh_dup_2_hist_14_folded_hist <= s1_folded_gh_dup_2_hist_14_folded_hist; + s2_folded_gh_dup_2_hist_13_folded_hist <= s1_folded_gh_dup_2_hist_13_folded_hist; + s2_folded_gh_dup_2_hist_12_folded_hist <= s1_folded_gh_dup_2_hist_12_folded_hist; + s2_folded_gh_dup_2_hist_11_folded_hist <= s1_folded_gh_dup_2_hist_11_folded_hist; + s2_folded_gh_dup_2_hist_10_folded_hist <= s1_folded_gh_dup_2_hist_10_folded_hist; + s2_folded_gh_dup_2_hist_9_folded_hist <= s1_folded_gh_dup_2_hist_9_folded_hist; + s2_folded_gh_dup_2_hist_8_folded_hist <= s1_folded_gh_dup_2_hist_8_folded_hist; + s2_folded_gh_dup_2_hist_7_folded_hist <= s1_folded_gh_dup_2_hist_7_folded_hist; + s2_folded_gh_dup_2_hist_6_folded_hist <= s1_folded_gh_dup_2_hist_6_folded_hist; + s2_folded_gh_dup_2_hist_5_folded_hist <= s1_folded_gh_dup_2_hist_5_folded_hist; + s2_folded_gh_dup_2_hist_4_folded_hist <= s1_folded_gh_dup_2_hist_4_folded_hist; + s2_folded_gh_dup_2_hist_3_folded_hist <= s1_folded_gh_dup_2_hist_3_folded_hist; + s2_folded_gh_dup_2_hist_2_folded_hist <= s1_folded_gh_dup_2_hist_2_folded_hist; + s2_folded_gh_dup_2_hist_1_folded_hist <= s1_folded_gh_dup_2_hist_1_folded_hist; + s2_folded_gh_dup_2_hist_0_folded_hist <= s1_folded_gh_dup_2_hist_0_folded_hist; + s2_folded_gh_dup_3_hist_17_folded_hist <= s1_folded_gh_dup_3_hist_17_folded_hist; + s2_folded_gh_dup_3_hist_16_folded_hist <= s1_folded_gh_dup_3_hist_16_folded_hist; + s2_folded_gh_dup_3_hist_15_folded_hist <= s1_folded_gh_dup_3_hist_15_folded_hist; + s2_folded_gh_dup_3_hist_14_folded_hist <= s1_folded_gh_dup_3_hist_14_folded_hist; + s2_folded_gh_dup_3_hist_13_folded_hist <= s1_folded_gh_dup_3_hist_13_folded_hist; + s2_folded_gh_dup_3_hist_12_folded_hist <= s1_folded_gh_dup_3_hist_12_folded_hist; + s2_folded_gh_dup_3_hist_11_folded_hist <= s1_folded_gh_dup_3_hist_11_folded_hist; + s2_folded_gh_dup_3_hist_10_folded_hist <= s1_folded_gh_dup_3_hist_10_folded_hist; + s2_folded_gh_dup_3_hist_9_folded_hist <= s1_folded_gh_dup_3_hist_9_folded_hist; + s2_folded_gh_dup_3_hist_8_folded_hist <= s1_folded_gh_dup_3_hist_8_folded_hist; + s2_folded_gh_dup_3_hist_7_folded_hist <= s1_folded_gh_dup_3_hist_7_folded_hist; + s2_folded_gh_dup_3_hist_6_folded_hist <= s1_folded_gh_dup_3_hist_6_folded_hist; + s2_folded_gh_dup_3_hist_5_folded_hist <= s1_folded_gh_dup_3_hist_5_folded_hist; + s2_folded_gh_dup_3_hist_4_folded_hist <= s1_folded_gh_dup_3_hist_4_folded_hist; + s2_folded_gh_dup_3_hist_3_folded_hist <= s1_folded_gh_dup_3_hist_3_folded_hist; + s2_folded_gh_dup_3_hist_2_folded_hist <= s1_folded_gh_dup_3_hist_2_folded_hist; + s2_folded_gh_dup_3_hist_1_folded_hist <= s1_folded_gh_dup_3_hist_1_folded_hist; + s2_folded_gh_dup_3_hist_0_folded_hist <= s1_folded_gh_dup_3_hist_0_folded_hist; + s2_last_br_num_oh_dup_1 <= s1_last_br_num_oh_dup_1; + s2_last_br_num_oh_dup_2 <= s1_last_br_num_oh_dup_2; + s2_last_br_num_oh_dup_3 <= s1_last_br_num_oh_dup_3; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; + s2_ghist_ptr_dup_0_flag <= s1_ghist_ptr_dup_0_flag; + s2_ghist_ptr_dup_0_value <= s1_ghist_ptr_dup_0_value; + s2_ghist_ptr_dup_1_flag <= s1_ghist_ptr_dup_1_flag; + s2_ghist_ptr_dup_1_value <= s1_ghist_ptr_dup_1_value; + s2_ghist_ptr_dup_2_flag <= s1_ghist_ptr_dup_2_flag; + s2_ghist_ptr_dup_2_value <= s1_ghist_ptr_dup_2_value; + s2_ghist_ptr_dup_3_flag <= s1_ghist_ptr_dup_3_flag; + s2_ghist_ptr_dup_3_value <= s1_ghist_ptr_dup_3_value; + end + if (s2_valid_dup_3) begin + s3_folded_gh_dup_1_hist_17_folded_hist <= s2_folded_gh_dup_1_hist_17_folded_hist; + s3_folded_gh_dup_1_hist_16_folded_hist <= s2_folded_gh_dup_1_hist_16_folded_hist; + s3_folded_gh_dup_1_hist_15_folded_hist <= s2_folded_gh_dup_1_hist_15_folded_hist; + s3_folded_gh_dup_1_hist_14_folded_hist <= s2_folded_gh_dup_1_hist_14_folded_hist; + s3_folded_gh_dup_1_hist_13_folded_hist <= s2_folded_gh_dup_1_hist_13_folded_hist; + s3_folded_gh_dup_1_hist_12_folded_hist <= s2_folded_gh_dup_1_hist_12_folded_hist; + s3_folded_gh_dup_1_hist_11_folded_hist <= s2_folded_gh_dup_1_hist_11_folded_hist; + s3_folded_gh_dup_1_hist_10_folded_hist <= s2_folded_gh_dup_1_hist_10_folded_hist; + s3_folded_gh_dup_1_hist_9_folded_hist <= s2_folded_gh_dup_1_hist_9_folded_hist; + s3_folded_gh_dup_1_hist_8_folded_hist <= s2_folded_gh_dup_1_hist_8_folded_hist; + s3_folded_gh_dup_1_hist_7_folded_hist <= s2_folded_gh_dup_1_hist_7_folded_hist; + s3_folded_gh_dup_1_hist_6_folded_hist <= s2_folded_gh_dup_1_hist_6_folded_hist; + s3_folded_gh_dup_1_hist_5_folded_hist <= s2_folded_gh_dup_1_hist_5_folded_hist; + s3_folded_gh_dup_1_hist_4_folded_hist <= s2_folded_gh_dup_1_hist_4_folded_hist; + s3_folded_gh_dup_1_hist_3_folded_hist <= s2_folded_gh_dup_1_hist_3_folded_hist; + s3_folded_gh_dup_1_hist_2_folded_hist <= s2_folded_gh_dup_1_hist_2_folded_hist; + s3_folded_gh_dup_1_hist_1_folded_hist <= s2_folded_gh_dup_1_hist_1_folded_hist; + s3_folded_gh_dup_1_hist_0_folded_hist <= s2_folded_gh_dup_1_hist_0_folded_hist; + s3_folded_gh_dup_2_hist_17_folded_hist <= s2_folded_gh_dup_2_hist_17_folded_hist; + s3_folded_gh_dup_2_hist_16_folded_hist <= s2_folded_gh_dup_2_hist_16_folded_hist; + s3_folded_gh_dup_2_hist_15_folded_hist <= s2_folded_gh_dup_2_hist_15_folded_hist; + s3_folded_gh_dup_2_hist_14_folded_hist <= s2_folded_gh_dup_2_hist_14_folded_hist; + s3_folded_gh_dup_2_hist_13_folded_hist <= s2_folded_gh_dup_2_hist_13_folded_hist; + s3_folded_gh_dup_2_hist_12_folded_hist <= s2_folded_gh_dup_2_hist_12_folded_hist; + s3_folded_gh_dup_2_hist_11_folded_hist <= s2_folded_gh_dup_2_hist_11_folded_hist; + s3_folded_gh_dup_2_hist_10_folded_hist <= s2_folded_gh_dup_2_hist_10_folded_hist; + s3_folded_gh_dup_2_hist_9_folded_hist <= s2_folded_gh_dup_2_hist_9_folded_hist; + s3_folded_gh_dup_2_hist_8_folded_hist <= s2_folded_gh_dup_2_hist_8_folded_hist; + s3_folded_gh_dup_2_hist_7_folded_hist <= s2_folded_gh_dup_2_hist_7_folded_hist; + s3_folded_gh_dup_2_hist_6_folded_hist <= s2_folded_gh_dup_2_hist_6_folded_hist; + s3_folded_gh_dup_2_hist_5_folded_hist <= s2_folded_gh_dup_2_hist_5_folded_hist; + s3_folded_gh_dup_2_hist_4_folded_hist <= s2_folded_gh_dup_2_hist_4_folded_hist; + s3_folded_gh_dup_2_hist_3_folded_hist <= s2_folded_gh_dup_2_hist_3_folded_hist; + s3_folded_gh_dup_2_hist_2_folded_hist <= s2_folded_gh_dup_2_hist_2_folded_hist; + s3_folded_gh_dup_2_hist_1_folded_hist <= s2_folded_gh_dup_2_hist_1_folded_hist; + s3_folded_gh_dup_2_hist_0_folded_hist <= s2_folded_gh_dup_2_hist_0_folded_hist; + s3_folded_gh_dup_3_hist_17_folded_hist <= s2_folded_gh_dup_3_hist_17_folded_hist; + s3_folded_gh_dup_3_hist_16_folded_hist <= s2_folded_gh_dup_3_hist_16_folded_hist; + s3_folded_gh_dup_3_hist_15_folded_hist <= s2_folded_gh_dup_3_hist_15_folded_hist; + s3_folded_gh_dup_3_hist_14_folded_hist <= s2_folded_gh_dup_3_hist_14_folded_hist; + s3_folded_gh_dup_3_hist_13_folded_hist <= s2_folded_gh_dup_3_hist_13_folded_hist; + s3_folded_gh_dup_3_hist_12_folded_hist <= s2_folded_gh_dup_3_hist_12_folded_hist; + s3_folded_gh_dup_3_hist_11_folded_hist <= s2_folded_gh_dup_3_hist_11_folded_hist; + s3_folded_gh_dup_3_hist_10_folded_hist <= s2_folded_gh_dup_3_hist_10_folded_hist; + s3_folded_gh_dup_3_hist_9_folded_hist <= s2_folded_gh_dup_3_hist_9_folded_hist; + s3_folded_gh_dup_3_hist_8_folded_hist <= s2_folded_gh_dup_3_hist_8_folded_hist; + s3_folded_gh_dup_3_hist_7_folded_hist <= s2_folded_gh_dup_3_hist_7_folded_hist; + s3_folded_gh_dup_3_hist_6_folded_hist <= s2_folded_gh_dup_3_hist_6_folded_hist; + s3_folded_gh_dup_3_hist_5_folded_hist <= s2_folded_gh_dup_3_hist_5_folded_hist; + s3_folded_gh_dup_3_hist_4_folded_hist <= s2_folded_gh_dup_3_hist_4_folded_hist; + s3_folded_gh_dup_3_hist_3_folded_hist <= s2_folded_gh_dup_3_hist_3_folded_hist; + s3_folded_gh_dup_3_hist_2_folded_hist <= s2_folded_gh_dup_3_hist_2_folded_hist; + s3_folded_gh_dup_3_hist_1_folded_hist <= s2_folded_gh_dup_3_hist_1_folded_hist; + s3_folded_gh_dup_3_hist_0_folded_hist <= s2_folded_gh_dup_3_hist_0_folded_hist; + s3_last_br_num_oh_dup_1 <= s2_last_br_num_oh_dup_1; + s3_last_br_num_oh_dup_2 <= s2_last_br_num_oh_dup_2; + s3_last_br_num_oh_dup_3 <= s2_last_br_num_oh_dup_3; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; + s3_ghist_ptr_dup_0_flag <= s2_ghist_ptr_dup_0_flag; + s3_ghist_ptr_dup_0_value <= s2_ghist_ptr_dup_0_value; + s3_ghist_ptr_dup_1_flag <= s2_ghist_ptr_dup_1_flag; + s3_ghist_ptr_dup_1_value <= s2_ghist_ptr_dup_1_value; + s3_ghist_ptr_dup_2_flag <= s2_ghist_ptr_dup_2_flag; + s3_ghist_ptr_dup_2_value <= s2_ghist_ptr_dup_2_value; + s3_ghist_ptr_dup_3_flag <= s2_ghist_ptr_dup_3_flag; + s3_ghist_ptr_dup_3_value <= s2_ghist_ptr_dup_3_value; + previous_s2_pred_pc_0 <= _predictors_io_out_s2_pc_0; + previous_s2_pred_pc_1 <= _predictors_io_out_s2_pc_1; + previous_s2_pred_pc_2 <= _predictors_io_out_s2_pc_2; + previous_s2_pred_pc_3 <= _predictors_io_out_s2_pc_3; + previous_s2_pred_full_pred_0_br_taken_mask_0 <= + _predictors_io_out_s2_full_pred_0_br_taken_mask_0; + previous_s2_pred_full_pred_0_br_taken_mask_1 <= + _predictors_io_out_s2_full_pred_0_br_taken_mask_1; + previous_s2_pred_full_pred_0_slot_valids_0 <= + _predictors_io_out_s2_full_pred_0_slot_valids_0; + previous_s2_pred_full_pred_0_slot_valids_1 <= + _predictors_io_out_s2_full_pred_0_slot_valids_1; + previous_s2_pred_full_pred_0_targets_0 <= + _predictors_io_out_s2_full_pred_0_targets_0; + previous_s2_pred_full_pred_0_targets_1 <= + _predictors_io_out_s2_full_pred_0_targets_1; + previous_s2_pred_full_pred_0_fallThroughAddr <= + _predictors_io_out_s2_full_pred_0_fallThroughAddr; + previous_s2_pred_full_pred_0_is_br_sharing <= + _predictors_io_out_s2_full_pred_0_is_br_sharing; + previous_s2_pred_full_pred_0_hit <= _predictors_io_out_s2_full_pred_0_hit; + previous_s2_pred_full_pred_1_br_taken_mask_0 <= + _predictors_io_out_s2_full_pred_1_br_taken_mask_0; + previous_s2_pred_full_pred_1_br_taken_mask_1 <= + _predictors_io_out_s2_full_pred_1_br_taken_mask_1; + previous_s2_pred_full_pred_1_slot_valids_0 <= + _predictors_io_out_s2_full_pred_1_slot_valids_0; + previous_s2_pred_full_pred_1_slot_valids_1 <= + _predictors_io_out_s2_full_pred_1_slot_valids_1; + previous_s2_pred_full_pred_1_targets_0 <= + _predictors_io_out_s2_full_pred_1_targets_0; + previous_s2_pred_full_pred_1_targets_1 <= + _predictors_io_out_s2_full_pred_1_targets_1; + previous_s2_pred_full_pred_1_fallThroughAddr <= + _predictors_io_out_s2_full_pred_1_fallThroughAddr; + previous_s2_pred_full_pred_1_is_br_sharing <= + _predictors_io_out_s2_full_pred_1_is_br_sharing; + previous_s2_pred_full_pred_1_hit <= _predictors_io_out_s2_full_pred_1_hit; + previous_s2_pred_full_pred_2_br_taken_mask_0 <= + _predictors_io_out_s2_full_pred_2_br_taken_mask_0; + previous_s2_pred_full_pred_2_br_taken_mask_1 <= + _predictors_io_out_s2_full_pred_2_br_taken_mask_1; + previous_s2_pred_full_pred_2_slot_valids_0 <= + _predictors_io_out_s2_full_pred_2_slot_valids_0; + previous_s2_pred_full_pred_2_slot_valids_1 <= + _predictors_io_out_s2_full_pred_2_slot_valids_1; + previous_s2_pred_full_pred_2_targets_0 <= + _predictors_io_out_s2_full_pred_2_targets_0; + previous_s2_pred_full_pred_2_targets_1 <= + _predictors_io_out_s2_full_pred_2_targets_1; + previous_s2_pred_full_pred_2_fallThroughAddr <= + _predictors_io_out_s2_full_pred_2_fallThroughAddr; + previous_s2_pred_full_pred_2_is_br_sharing <= + _predictors_io_out_s2_full_pred_2_is_br_sharing; + previous_s2_pred_full_pred_2_hit <= _predictors_io_out_s2_full_pred_2_hit; + previous_s2_pred_full_pred_3_br_taken_mask_0 <= + _predictors_io_out_s2_full_pred_3_br_taken_mask_0; + previous_s2_pred_full_pred_3_br_taken_mask_1 <= + _predictors_io_out_s2_full_pred_3_br_taken_mask_1; + previous_s2_pred_full_pred_3_slot_valids_0 <= + _predictors_io_out_s2_full_pred_3_slot_valids_0; + previous_s2_pred_full_pred_3_slot_valids_1 <= + _predictors_io_out_s2_full_pred_3_slot_valids_1; + previous_s2_pred_full_pred_3_targets_0 <= + _predictors_io_out_s2_full_pred_3_targets_0; + previous_s2_pred_full_pred_3_targets_1 <= + _predictors_io_out_s2_full_pred_3_targets_1; + previous_s2_pred_full_pred_3_fallThroughAddr <= + _predictors_io_out_s2_full_pred_3_fallThroughAddr; + previous_s2_pred_full_pred_3_is_br_sharing <= + _predictors_io_out_s2_full_pred_3_is_br_sharing; + previous_s2_pred_full_pred_3_hit <= _predictors_io_out_s2_full_pred_3_hit; + end + s0_last_br_num_oh_reg_dup_1 <= _s0_last_br_num_oh_dup_1_ppm_out_res; + s0_last_br_num_oh_reg_dup_2 <= _s0_last_br_num_oh_dup_2_ppm_out_res; + s0_last_br_num_oh_reg_dup_3 <= _s0_last_br_num_oh_dup_3_ppm_out_res; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 <= + _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; + if (_ghv_wens_0_T | _ghv_wens_0_T_1 | _ghv_wens_0_T_2 | _ghv_wens_0_T_3) + ghv_0 <= _ghv_write_datas_0_ppm_out_res; + if (_ghv_wens_1_T | _ghv_wens_1_T_1 | _ghv_wens_1_T_2 | _ghv_wens_1_T_3) + ghv_1 <= _ghv_write_datas_1_ppm_out_res; + if (_ghv_wens_2_T | _ghv_wens_2_T_1 | _ghv_wens_2_T_2 | _ghv_wens_2_T_3) + ghv_2 <= _ghv_write_datas_2_ppm_out_res; + if (_ghv_wens_3_T | _ghv_wens_3_T_1 | _ghv_wens_3_T_2 | _ghv_wens_3_T_3) + ghv_3 <= _ghv_write_datas_3_ppm_out_res; + if (_ghv_wens_4_T | _ghv_wens_4_T_1 | _ghv_wens_4_T_2 | _ghv_wens_4_T_3) + ghv_4 <= _ghv_write_datas_4_ppm_out_res; + if (_ghv_wens_5_T | _ghv_wens_5_T_1 | _ghv_wens_5_T_2 | _ghv_wens_5_T_3) + ghv_5 <= _ghv_write_datas_5_ppm_out_res; + if (_ghv_wens_6_T | _ghv_wens_6_T_1 | _ghv_wens_6_T_2 | _ghv_wens_6_T_3) + ghv_6 <= _ghv_write_datas_6_ppm_out_res; + if (_ghv_wens_7_T | _ghv_wens_7_T_1 | _ghv_wens_7_T_2 | _ghv_wens_7_T_3) + ghv_7 <= _ghv_write_datas_7_ppm_out_res; + if (_ghv_wens_8_T | _ghv_wens_8_T_1 | _ghv_wens_8_T_2 | _ghv_wens_8_T_3) + ghv_8 <= _ghv_write_datas_8_ppm_out_res; + if (_ghv_wens_9_T | _ghv_wens_9_T_1 | _ghv_wens_9_T_2 | _ghv_wens_9_T_3) + ghv_9 <= _ghv_write_datas_9_ppm_out_res; + if (_ghv_wens_10_T | _ghv_wens_10_T_1 | _ghv_wens_10_T_2 | _ghv_wens_10_T_3) + ghv_10 <= _ghv_write_datas_10_ppm_out_res; + if (_ghv_wens_11_T | _ghv_wens_11_T_1 | _ghv_wens_11_T_2 | _ghv_wens_11_T_3) + ghv_11 <= _ghv_write_datas_11_ppm_out_res; + if (_ghv_wens_12_T | _ghv_wens_12_T_1 | _ghv_wens_12_T_2 | _ghv_wens_12_T_3) + ghv_12 <= _ghv_write_datas_12_ppm_out_res; + if (_ghv_wens_13_T | _ghv_wens_13_T_1 | _ghv_wens_13_T_2 | _ghv_wens_13_T_3) + ghv_13 <= _ghv_write_datas_13_ppm_out_res; + if (_ghv_wens_14_T | _ghv_wens_14_T_1 | _ghv_wens_14_T_2 | _ghv_wens_14_T_3) + ghv_14 <= _ghv_write_datas_14_ppm_out_res; + if (_ghv_wens_15_T | _ghv_wens_15_T_1 | _ghv_wens_15_T_2 | _ghv_wens_15_T_3) + ghv_15 <= _ghv_write_datas_15_ppm_out_res; + if (_ghv_wens_16_T | _ghv_wens_16_T_1 | _ghv_wens_16_T_2 | _ghv_wens_16_T_3) + ghv_16 <= _ghv_write_datas_16_ppm_out_res; + if (_ghv_wens_17_T | _ghv_wens_17_T_1 | _ghv_wens_17_T_2 | _ghv_wens_17_T_3) + ghv_17 <= _ghv_write_datas_17_ppm_out_res; + if (_ghv_wens_18_T | _ghv_wens_18_T_1 | _ghv_wens_18_T_2 | _ghv_wens_18_T_3) + ghv_18 <= _ghv_write_datas_18_ppm_out_res; + if (_ghv_wens_19_T | _ghv_wens_19_T_1 | _ghv_wens_19_T_2 | _ghv_wens_19_T_3) + ghv_19 <= _ghv_write_datas_19_ppm_out_res; + if (_ghv_wens_20_T | _ghv_wens_20_T_1 | _ghv_wens_20_T_2 | _ghv_wens_20_T_3) + ghv_20 <= _ghv_write_datas_20_ppm_out_res; + if (_ghv_wens_21_T | _ghv_wens_21_T_1 | _ghv_wens_21_T_2 | _ghv_wens_21_T_3) + ghv_21 <= _ghv_write_datas_21_ppm_out_res; + if (_ghv_wens_22_T | _ghv_wens_22_T_1 | _ghv_wens_22_T_2 | _ghv_wens_22_T_3) + ghv_22 <= _ghv_write_datas_22_ppm_out_res; + if (_ghv_wens_23_T | _ghv_wens_23_T_1 | _ghv_wens_23_T_2 | _ghv_wens_23_T_3) + ghv_23 <= _ghv_write_datas_23_ppm_out_res; + if (_ghv_wens_24_T | _ghv_wens_24_T_1 | _ghv_wens_24_T_2 | _ghv_wens_24_T_3) + ghv_24 <= _ghv_write_datas_24_ppm_out_res; + if (_ghv_wens_25_T | _ghv_wens_25_T_1 | _ghv_wens_25_T_2 | _ghv_wens_25_T_3) + ghv_25 <= _ghv_write_datas_25_ppm_out_res; + if (_ghv_wens_26_T | _ghv_wens_26_T_1 | _ghv_wens_26_T_2 | _ghv_wens_26_T_3) + ghv_26 <= _ghv_write_datas_26_ppm_out_res; + if (_ghv_wens_27_T | _ghv_wens_27_T_1 | _ghv_wens_27_T_2 | _ghv_wens_27_T_3) + ghv_27 <= _ghv_write_datas_27_ppm_out_res; + if (_ghv_wens_28_T | _ghv_wens_28_T_1 | _ghv_wens_28_T_2 | _ghv_wens_28_T_3) + ghv_28 <= _ghv_write_datas_28_ppm_out_res; + if (_ghv_wens_29_T | _ghv_wens_29_T_1 | _ghv_wens_29_T_2 | _ghv_wens_29_T_3) + ghv_29 <= _ghv_write_datas_29_ppm_out_res; + if (_ghv_wens_30_T | _ghv_wens_30_T_1 | _ghv_wens_30_T_2 | _ghv_wens_30_T_3) + ghv_30 <= _ghv_write_datas_30_ppm_out_res; + if (_ghv_wens_31_T | _ghv_wens_31_T_1 | _ghv_wens_31_T_2 | _ghv_wens_31_T_3) + ghv_31 <= _ghv_write_datas_31_ppm_out_res; + if (_ghv_wens_32_T | _ghv_wens_32_T_1 | _ghv_wens_32_T_2 | _ghv_wens_32_T_3) + ghv_32 <= _ghv_write_datas_32_ppm_out_res; + if (_ghv_wens_33_T | _ghv_wens_33_T_1 | _ghv_wens_33_T_2 | _ghv_wens_33_T_3) + ghv_33 <= _ghv_write_datas_33_ppm_out_res; + if (_ghv_wens_34_T | _ghv_wens_34_T_1 | _ghv_wens_34_T_2 | _ghv_wens_34_T_3) + ghv_34 <= _ghv_write_datas_34_ppm_out_res; + if (_ghv_wens_35_T | _ghv_wens_35_T_1 | _ghv_wens_35_T_2 | _ghv_wens_35_T_3) + ghv_35 <= _ghv_write_datas_35_ppm_out_res; + if (_ghv_wens_36_T | _ghv_wens_36_T_1 | _ghv_wens_36_T_2 | _ghv_wens_36_T_3) + ghv_36 <= _ghv_write_datas_36_ppm_out_res; + if (_ghv_wens_37_T | _ghv_wens_37_T_1 | _ghv_wens_37_T_2 | _ghv_wens_37_T_3) + ghv_37 <= _ghv_write_datas_37_ppm_out_res; + if (_ghv_wens_38_T | _ghv_wens_38_T_1 | _ghv_wens_38_T_2 | _ghv_wens_38_T_3) + ghv_38 <= _ghv_write_datas_38_ppm_out_res; + if (_ghv_wens_39_T | _ghv_wens_39_T_1 | _ghv_wens_39_T_2 | _ghv_wens_39_T_3) + ghv_39 <= _ghv_write_datas_39_ppm_out_res; + if (_ghv_wens_40_T | _ghv_wens_40_T_1 | _ghv_wens_40_T_2 | _ghv_wens_40_T_3) + ghv_40 <= _ghv_write_datas_40_ppm_out_res; + if (_ghv_wens_41_T | _ghv_wens_41_T_1 | _ghv_wens_41_T_2 | _ghv_wens_41_T_3) + ghv_41 <= _ghv_write_datas_41_ppm_out_res; + if (_ghv_wens_42_T | _ghv_wens_42_T_1 | _ghv_wens_42_T_2 | _ghv_wens_42_T_3) + ghv_42 <= _ghv_write_datas_42_ppm_out_res; + if (_ghv_wens_43_T | _ghv_wens_43_T_1 | _ghv_wens_43_T_2 | _ghv_wens_43_T_3) + ghv_43 <= _ghv_write_datas_43_ppm_out_res; + if (_ghv_wens_44_T | _ghv_wens_44_T_1 | _ghv_wens_44_T_2 | _ghv_wens_44_T_3) + ghv_44 <= _ghv_write_datas_44_ppm_out_res; + if (_ghv_wens_45_T | _ghv_wens_45_T_1 | _ghv_wens_45_T_2 | _ghv_wens_45_T_3) + ghv_45 <= _ghv_write_datas_45_ppm_out_res; + if (_ghv_wens_46_T | _ghv_wens_46_T_1 | _ghv_wens_46_T_2 | _ghv_wens_46_T_3) + ghv_46 <= _ghv_write_datas_46_ppm_out_res; + if (_ghv_wens_47_T | _ghv_wens_47_T_1 | _ghv_wens_47_T_2 | _ghv_wens_47_T_3) + ghv_47 <= _ghv_write_datas_47_ppm_out_res; + if (_ghv_wens_48_T | _ghv_wens_48_T_1 | _ghv_wens_48_T_2 | _ghv_wens_48_T_3) + ghv_48 <= _ghv_write_datas_48_ppm_out_res; + if (_ghv_wens_49_T | _ghv_wens_49_T_1 | _ghv_wens_49_T_2 | _ghv_wens_49_T_3) + ghv_49 <= _ghv_write_datas_49_ppm_out_res; + if (_ghv_wens_50_T | _ghv_wens_50_T_1 | _ghv_wens_50_T_2 | _ghv_wens_50_T_3) + ghv_50 <= _ghv_write_datas_50_ppm_out_res; + if (_ghv_wens_51_T | _ghv_wens_51_T_1 | _ghv_wens_51_T_2 | _ghv_wens_51_T_3) + ghv_51 <= _ghv_write_datas_51_ppm_out_res; + if (_ghv_wens_52_T | _ghv_wens_52_T_1 | _ghv_wens_52_T_2 | _ghv_wens_52_T_3) + ghv_52 <= _ghv_write_datas_52_ppm_out_res; + if (_ghv_wens_53_T | _ghv_wens_53_T_1 | _ghv_wens_53_T_2 | _ghv_wens_53_T_3) + ghv_53 <= _ghv_write_datas_53_ppm_out_res; + if (_ghv_wens_54_T | _ghv_wens_54_T_1 | _ghv_wens_54_T_2 | _ghv_wens_54_T_3) + ghv_54 <= _ghv_write_datas_54_ppm_out_res; + if (_ghv_wens_55_T | _ghv_wens_55_T_1 | _ghv_wens_55_T_2 | _ghv_wens_55_T_3) + ghv_55 <= _ghv_write_datas_55_ppm_out_res; + if (_ghv_wens_56_T | _ghv_wens_56_T_1 | _ghv_wens_56_T_2 | _ghv_wens_56_T_3) + ghv_56 <= _ghv_write_datas_56_ppm_out_res; + if (_ghv_wens_57_T | _ghv_wens_57_T_1 | _ghv_wens_57_T_2 | _ghv_wens_57_T_3) + ghv_57 <= _ghv_write_datas_57_ppm_out_res; + if (_ghv_wens_58_T | _ghv_wens_58_T_1 | _ghv_wens_58_T_2 | _ghv_wens_58_T_3) + ghv_58 <= _ghv_write_datas_58_ppm_out_res; + if (_ghv_wens_59_T | _ghv_wens_59_T_1 | _ghv_wens_59_T_2 | _ghv_wens_59_T_3) + ghv_59 <= _ghv_write_datas_59_ppm_out_res; + if (_ghv_wens_60_T | _ghv_wens_60_T_1 | _ghv_wens_60_T_2 | _ghv_wens_60_T_3) + ghv_60 <= _ghv_write_datas_60_ppm_out_res; + if (_ghv_wens_61_T | _ghv_wens_61_T_1 | _ghv_wens_61_T_2 | _ghv_wens_61_T_3) + ghv_61 <= _ghv_write_datas_61_ppm_out_res; + if (_ghv_wens_62_T | _ghv_wens_62_T_1 | _ghv_wens_62_T_2 | _ghv_wens_62_T_3) + ghv_62 <= _ghv_write_datas_62_ppm_out_res; + if (_ghv_wens_63_T | _ghv_wens_63_T_1 | _ghv_wens_63_T_2 | _ghv_wens_63_T_3) + ghv_63 <= _ghv_write_datas_63_ppm_out_res; + if (_ghv_wens_64_T | _ghv_wens_64_T_1 | _ghv_wens_64_T_2 | _ghv_wens_64_T_3) + ghv_64 <= _ghv_write_datas_64_ppm_out_res; + if (_ghv_wens_65_T | _ghv_wens_65_T_1 | _ghv_wens_65_T_2 | _ghv_wens_65_T_3) + ghv_65 <= _ghv_write_datas_65_ppm_out_res; + if (_ghv_wens_66_T | _ghv_wens_66_T_1 | _ghv_wens_66_T_2 | _ghv_wens_66_T_3) + ghv_66 <= _ghv_write_datas_66_ppm_out_res; + if (_ghv_wens_67_T | _ghv_wens_67_T_1 | _ghv_wens_67_T_2 | _ghv_wens_67_T_3) + ghv_67 <= _ghv_write_datas_67_ppm_out_res; + if (_ghv_wens_68_T | _ghv_wens_68_T_1 | _ghv_wens_68_T_2 | _ghv_wens_68_T_3) + ghv_68 <= _ghv_write_datas_68_ppm_out_res; + if (_ghv_wens_69_T | _ghv_wens_69_T_1 | _ghv_wens_69_T_2 | _ghv_wens_69_T_3) + ghv_69 <= _ghv_write_datas_69_ppm_out_res; + if (_ghv_wens_70_T | _ghv_wens_70_T_1 | _ghv_wens_70_T_2 | _ghv_wens_70_T_3) + ghv_70 <= _ghv_write_datas_70_ppm_out_res; + if (_ghv_wens_71_T | _ghv_wens_71_T_1 | _ghv_wens_71_T_2 | _ghv_wens_71_T_3) + ghv_71 <= _ghv_write_datas_71_ppm_out_res; + if (_ghv_wens_72_T | _ghv_wens_72_T_1 | _ghv_wens_72_T_2 | _ghv_wens_72_T_3) + ghv_72 <= _ghv_write_datas_72_ppm_out_res; + if (_ghv_wens_73_T | _ghv_wens_73_T_1 | _ghv_wens_73_T_2 | _ghv_wens_73_T_3) + ghv_73 <= _ghv_write_datas_73_ppm_out_res; + if (_ghv_wens_74_T | _ghv_wens_74_T_1 | _ghv_wens_74_T_2 | _ghv_wens_74_T_3) + ghv_74 <= _ghv_write_datas_74_ppm_out_res; + if (_ghv_wens_75_T | _ghv_wens_75_T_1 | _ghv_wens_75_T_2 | _ghv_wens_75_T_3) + ghv_75 <= _ghv_write_datas_75_ppm_out_res; + if (_ghv_wens_76_T | _ghv_wens_76_T_1 | _ghv_wens_76_T_2 | _ghv_wens_76_T_3) + ghv_76 <= _ghv_write_datas_76_ppm_out_res; + if (_ghv_wens_77_T | _ghv_wens_77_T_1 | _ghv_wens_77_T_2 | _ghv_wens_77_T_3) + ghv_77 <= _ghv_write_datas_77_ppm_out_res; + if (_ghv_wens_78_T | _ghv_wens_78_T_1 | _ghv_wens_78_T_2 | _ghv_wens_78_T_3) + ghv_78 <= _ghv_write_datas_78_ppm_out_res; + if (_ghv_wens_79_T | _ghv_wens_79_T_1 | _ghv_wens_79_T_2 | _ghv_wens_79_T_3) + ghv_79 <= _ghv_write_datas_79_ppm_out_res; + if (_ghv_wens_80_T | _ghv_wens_80_T_1 | _ghv_wens_80_T_2 | _ghv_wens_80_T_3) + ghv_80 <= _ghv_write_datas_80_ppm_out_res; + if (_ghv_wens_81_T | _ghv_wens_81_T_1 | _ghv_wens_81_T_2 | _ghv_wens_81_T_3) + ghv_81 <= _ghv_write_datas_81_ppm_out_res; + if (_ghv_wens_82_T | _ghv_wens_82_T_1 | _ghv_wens_82_T_2 | _ghv_wens_82_T_3) + ghv_82 <= _ghv_write_datas_82_ppm_out_res; + if (_ghv_wens_83_T | _ghv_wens_83_T_1 | _ghv_wens_83_T_2 | _ghv_wens_83_T_3) + ghv_83 <= _ghv_write_datas_83_ppm_out_res; + if (_ghv_wens_84_T | _ghv_wens_84_T_1 | _ghv_wens_84_T_2 | _ghv_wens_84_T_3) + ghv_84 <= _ghv_write_datas_84_ppm_out_res; + if (_ghv_wens_85_T | _ghv_wens_85_T_1 | _ghv_wens_85_T_2 | _ghv_wens_85_T_3) + ghv_85 <= _ghv_write_datas_85_ppm_out_res; + if (_ghv_wens_86_T | _ghv_wens_86_T_1 | _ghv_wens_86_T_2 | _ghv_wens_86_T_3) + ghv_86 <= _ghv_write_datas_86_ppm_out_res; + if (_ghv_wens_87_T | _ghv_wens_87_T_1 | _ghv_wens_87_T_2 | _ghv_wens_87_T_3) + ghv_87 <= _ghv_write_datas_87_ppm_out_res; + if (_ghv_wens_88_T | _ghv_wens_88_T_1 | _ghv_wens_88_T_2 | _ghv_wens_88_T_3) + ghv_88 <= _ghv_write_datas_88_ppm_out_res; + if (_ghv_wens_89_T | _ghv_wens_89_T_1 | _ghv_wens_89_T_2 | _ghv_wens_89_T_3) + ghv_89 <= _ghv_write_datas_89_ppm_out_res; + if (_ghv_wens_90_T | _ghv_wens_90_T_1 | _ghv_wens_90_T_2 | _ghv_wens_90_T_3) + ghv_90 <= _ghv_write_datas_90_ppm_out_res; + if (_ghv_wens_91_T | _ghv_wens_91_T_1 | _ghv_wens_91_T_2 | _ghv_wens_91_T_3) + ghv_91 <= _ghv_write_datas_91_ppm_out_res; + if (_ghv_wens_92_T | _ghv_wens_92_T_1 | _ghv_wens_92_T_2 | _ghv_wens_92_T_3) + ghv_92 <= _ghv_write_datas_92_ppm_out_res; + if (_ghv_wens_93_T | _ghv_wens_93_T_1 | _ghv_wens_93_T_2 | _ghv_wens_93_T_3) + ghv_93 <= _ghv_write_datas_93_ppm_out_res; + if (_ghv_wens_94_T | _ghv_wens_94_T_1 | _ghv_wens_94_T_2 | _ghv_wens_94_T_3) + ghv_94 <= _ghv_write_datas_94_ppm_out_res; + if (_ghv_wens_95_T | _ghv_wens_95_T_1 | _ghv_wens_95_T_2 | _ghv_wens_95_T_3) + ghv_95 <= _ghv_write_datas_95_ppm_out_res; + if (_ghv_wens_96_T | _ghv_wens_96_T_1 | _ghv_wens_96_T_2 | _ghv_wens_96_T_3) + ghv_96 <= _ghv_write_datas_96_ppm_out_res; + if (_ghv_wens_97_T | _ghv_wens_97_T_1 | _ghv_wens_97_T_2 | _ghv_wens_97_T_3) + ghv_97 <= _ghv_write_datas_97_ppm_out_res; + if (_ghv_wens_98_T | _ghv_wens_98_T_1 | _ghv_wens_98_T_2 | _ghv_wens_98_T_3) + ghv_98 <= _ghv_write_datas_98_ppm_out_res; + if (_ghv_wens_99_T | _ghv_wens_99_T_1 | _ghv_wens_99_T_2 | _ghv_wens_99_T_3) + ghv_99 <= _ghv_write_datas_99_ppm_out_res; + if (_ghv_wens_100_T | _ghv_wens_100_T_1 | _ghv_wens_100_T_2 | _ghv_wens_100_T_3) + ghv_100 <= _ghv_write_datas_100_ppm_out_res; + if (_ghv_wens_101_T | _ghv_wens_101_T_1 | _ghv_wens_101_T_2 | _ghv_wens_101_T_3) + ghv_101 <= _ghv_write_datas_101_ppm_out_res; + if (_ghv_wens_102_T | _ghv_wens_102_T_1 | _ghv_wens_102_T_2 | _ghv_wens_102_T_3) + ghv_102 <= _ghv_write_datas_102_ppm_out_res; + if (_ghv_wens_103_T | _ghv_wens_103_T_1 | _ghv_wens_103_T_2 | _ghv_wens_103_T_3) + ghv_103 <= _ghv_write_datas_103_ppm_out_res; + if (_ghv_wens_104_T | _ghv_wens_104_T_1 | _ghv_wens_104_T_2 | _ghv_wens_104_T_3) + ghv_104 <= _ghv_write_datas_104_ppm_out_res; + if (_ghv_wens_105_T | _ghv_wens_105_T_1 | _ghv_wens_105_T_2 | _ghv_wens_105_T_3) + ghv_105 <= _ghv_write_datas_105_ppm_out_res; + if (_ghv_wens_106_T | _ghv_wens_106_T_1 | _ghv_wens_106_T_2 | _ghv_wens_106_T_3) + ghv_106 <= _ghv_write_datas_106_ppm_out_res; + if (_ghv_wens_107_T | _ghv_wens_107_T_1 | _ghv_wens_107_T_2 | _ghv_wens_107_T_3) + ghv_107 <= _ghv_write_datas_107_ppm_out_res; + if (_ghv_wens_108_T | _ghv_wens_108_T_1 | _ghv_wens_108_T_2 | _ghv_wens_108_T_3) + ghv_108 <= _ghv_write_datas_108_ppm_out_res; + if (_ghv_wens_109_T | _ghv_wens_109_T_1 | _ghv_wens_109_T_2 | _ghv_wens_109_T_3) + ghv_109 <= _ghv_write_datas_109_ppm_out_res; + if (_ghv_wens_110_T | _ghv_wens_110_T_1 | _ghv_wens_110_T_2 | _ghv_wens_110_T_3) + ghv_110 <= _ghv_write_datas_110_ppm_out_res; + if (_ghv_wens_111_T | _ghv_wens_111_T_1 | _ghv_wens_111_T_2 | _ghv_wens_111_T_3) + ghv_111 <= _ghv_write_datas_111_ppm_out_res; + if (_ghv_wens_112_T | _ghv_wens_112_T_1 | _ghv_wens_112_T_2 | _ghv_wens_112_T_3) + ghv_112 <= _ghv_write_datas_112_ppm_out_res; + if (_ghv_wens_113_T | _ghv_wens_113_T_1 | _ghv_wens_113_T_2 | _ghv_wens_113_T_3) + ghv_113 <= _ghv_write_datas_113_ppm_out_res; + if (_ghv_wens_114_T | _ghv_wens_114_T_1 | _ghv_wens_114_T_2 | _ghv_wens_114_T_3) + ghv_114 <= _ghv_write_datas_114_ppm_out_res; + if (_ghv_wens_115_T | _ghv_wens_115_T_1 | _ghv_wens_115_T_2 | _ghv_wens_115_T_3) + ghv_115 <= _ghv_write_datas_115_ppm_out_res; + if (_ghv_wens_116_T | _ghv_wens_116_T_1 | _ghv_wens_116_T_2 | _ghv_wens_116_T_3) + ghv_116 <= _ghv_write_datas_116_ppm_out_res; + if (_ghv_wens_117_T | _ghv_wens_117_T_1 | _ghv_wens_117_T_2 | _ghv_wens_117_T_3) + ghv_117 <= _ghv_write_datas_117_ppm_out_res; + if (_ghv_wens_118_T | _ghv_wens_118_T_1 | _ghv_wens_118_T_2 | _ghv_wens_118_T_3) + ghv_118 <= _ghv_write_datas_118_ppm_out_res; + if (_ghv_wens_119_T | _ghv_wens_119_T_1 | _ghv_wens_119_T_2 | _ghv_wens_119_T_3) + ghv_119 <= _ghv_write_datas_119_ppm_out_res; + if (_ghv_wens_120_T | _ghv_wens_120_T_1 | _ghv_wens_120_T_2 | _ghv_wens_120_T_3) + ghv_120 <= _ghv_write_datas_120_ppm_out_res; + if (_ghv_wens_121_T | _ghv_wens_121_T_1 | _ghv_wens_121_T_2 | _ghv_wens_121_T_3) + ghv_121 <= _ghv_write_datas_121_ppm_out_res; + if (_ghv_wens_122_T | _ghv_wens_122_T_1 | _ghv_wens_122_T_2 | _ghv_wens_122_T_3) + ghv_122 <= _ghv_write_datas_122_ppm_out_res; + if (_ghv_wens_123_T | _ghv_wens_123_T_1 | _ghv_wens_123_T_2 | _ghv_wens_123_T_3) + ghv_123 <= _ghv_write_datas_123_ppm_out_res; + if (_ghv_wens_124_T | _ghv_wens_124_T_1 | _ghv_wens_124_T_2 | _ghv_wens_124_T_3) + ghv_124 <= _ghv_write_datas_124_ppm_out_res; + if (_ghv_wens_125_T | _ghv_wens_125_T_1 | _ghv_wens_125_T_2 | _ghv_wens_125_T_3) + ghv_125 <= _ghv_write_datas_125_ppm_out_res; + if (_ghv_wens_126_T | _ghv_wens_126_T_1 | _ghv_wens_126_T_2 | _ghv_wens_126_T_3) + ghv_126 <= _ghv_write_datas_126_ppm_out_res; + if (_ghv_wens_127_T | _ghv_wens_127_T_1 | _ghv_wens_127_T_2 | _ghv_wens_127_T_3) + ghv_127 <= _ghv_write_datas_127_ppm_out_res; + if (_ghv_wens_128_T | _ghv_wens_128_T_1 | _ghv_wens_128_T_2 | _ghv_wens_128_T_3) + ghv_128 <= _ghv_write_datas_128_ppm_out_res; + if (_ghv_wens_129_T | _ghv_wens_129_T_1 | _ghv_wens_129_T_2 | _ghv_wens_129_T_3) + ghv_129 <= _ghv_write_datas_129_ppm_out_res; + if (_ghv_wens_130_T | _ghv_wens_130_T_1 | _ghv_wens_130_T_2 | _ghv_wens_130_T_3) + ghv_130 <= _ghv_write_datas_130_ppm_out_res; + if (_ghv_wens_131_T | _ghv_wens_131_T_1 | _ghv_wens_131_T_2 | _ghv_wens_131_T_3) + ghv_131 <= _ghv_write_datas_131_ppm_out_res; + if (_ghv_wens_132_T | _ghv_wens_132_T_1 | _ghv_wens_132_T_2 | _ghv_wens_132_T_3) + ghv_132 <= _ghv_write_datas_132_ppm_out_res; + if (_ghv_wens_133_T | _ghv_wens_133_T_1 | _ghv_wens_133_T_2 | _ghv_wens_133_T_3) + ghv_133 <= _ghv_write_datas_133_ppm_out_res; + if (_ghv_wens_134_T | _ghv_wens_134_T_1 | _ghv_wens_134_T_2 | _ghv_wens_134_T_3) + ghv_134 <= _ghv_write_datas_134_ppm_out_res; + if (_ghv_wens_135_T | _ghv_wens_135_T_1 | _ghv_wens_135_T_2 | _ghv_wens_135_T_3) + ghv_135 <= _ghv_write_datas_135_ppm_out_res; + if (_ghv_wens_136_T | _ghv_wens_136_T_1 | _ghv_wens_136_T_2 | _ghv_wens_136_T_3) + ghv_136 <= _ghv_write_datas_136_ppm_out_res; + if (_ghv_wens_137_T | _ghv_wens_137_T_1 | _ghv_wens_137_T_2 | _ghv_wens_137_T_3) + ghv_137 <= _ghv_write_datas_137_ppm_out_res; + if (_ghv_wens_138_T | _ghv_wens_138_T_1 | _ghv_wens_138_T_2 | _ghv_wens_138_T_3) + ghv_138 <= _ghv_write_datas_138_ppm_out_res; + if (_ghv_wens_139_T | _ghv_wens_139_T_1 | _ghv_wens_139_T_2 | _ghv_wens_139_T_3) + ghv_139 <= _ghv_write_datas_139_ppm_out_res; + if (_ghv_wens_140_T | _ghv_wens_140_T_1 | _ghv_wens_140_T_2 | _ghv_wens_140_T_3) + ghv_140 <= _ghv_write_datas_140_ppm_out_res; + if (_ghv_wens_141_T | _ghv_wens_141_T_1 | _ghv_wens_141_T_2 | _ghv_wens_141_T_3) + ghv_141 <= _ghv_write_datas_141_ppm_out_res; + if (_ghv_wens_142_T | _ghv_wens_142_T_1 | _ghv_wens_142_T_2 | _ghv_wens_142_T_3) + ghv_142 <= _ghv_write_datas_142_ppm_out_res; + if (_ghv_wens_143_T | _ghv_wens_143_T_1 | _ghv_wens_143_T_2 | _ghv_wens_143_T_3) + ghv_143 <= _ghv_write_datas_143_ppm_out_res; + if (_ghv_wens_144_T | _ghv_wens_144_T_1 | _ghv_wens_144_T_2 | _ghv_wens_144_T_3) + ghv_144 <= _ghv_write_datas_144_ppm_out_res; + if (_ghv_wens_145_T | _ghv_wens_145_T_1 | _ghv_wens_145_T_2 | _ghv_wens_145_T_3) + ghv_145 <= _ghv_write_datas_145_ppm_out_res; + if (_ghv_wens_146_T | _ghv_wens_146_T_1 | _ghv_wens_146_T_2 | _ghv_wens_146_T_3) + ghv_146 <= _ghv_write_datas_146_ppm_out_res; + if (_ghv_wens_147_T | _ghv_wens_147_T_1 | _ghv_wens_147_T_2 | _ghv_wens_147_T_3) + ghv_147 <= _ghv_write_datas_147_ppm_out_res; + if (_ghv_wens_148_T | _ghv_wens_148_T_1 | _ghv_wens_148_T_2 | _ghv_wens_148_T_3) + ghv_148 <= _ghv_write_datas_148_ppm_out_res; + if (_ghv_wens_149_T | _ghv_wens_149_T_1 | _ghv_wens_149_T_2 | _ghv_wens_149_T_3) + ghv_149 <= _ghv_write_datas_149_ppm_out_res; + if (_ghv_wens_150_T | _ghv_wens_150_T_1 | _ghv_wens_150_T_2 | _ghv_wens_150_T_3) + ghv_150 <= _ghv_write_datas_150_ppm_out_res; + if (_ghv_wens_151_T | _ghv_wens_151_T_1 | _ghv_wens_151_T_2 | _ghv_wens_151_T_3) + ghv_151 <= _ghv_write_datas_151_ppm_out_res; + if (_ghv_wens_152_T | _ghv_wens_152_T_1 | _ghv_wens_152_T_2 | _ghv_wens_152_T_3) + ghv_152 <= _ghv_write_datas_152_ppm_out_res; + if (_ghv_wens_153_T | _ghv_wens_153_T_1 | _ghv_wens_153_T_2 | _ghv_wens_153_T_3) + ghv_153 <= _ghv_write_datas_153_ppm_out_res; + if (_ghv_wens_154_T | _ghv_wens_154_T_1 | _ghv_wens_154_T_2 | _ghv_wens_154_T_3) + ghv_154 <= _ghv_write_datas_154_ppm_out_res; + if (_ghv_wens_155_T | _ghv_wens_155_T_1 | _ghv_wens_155_T_2 | _ghv_wens_155_T_3) + ghv_155 <= _ghv_write_datas_155_ppm_out_res; + if (_ghv_wens_156_T | _ghv_wens_156_T_1 | _ghv_wens_156_T_2 | _ghv_wens_156_T_3) + ghv_156 <= _ghv_write_datas_156_ppm_out_res; + if (_ghv_wens_157_T | _ghv_wens_157_T_1 | _ghv_wens_157_T_2 | _ghv_wens_157_T_3) + ghv_157 <= _ghv_write_datas_157_ppm_out_res; + if (_ghv_wens_158_T | _ghv_wens_158_T_1 | _ghv_wens_158_T_2 | _ghv_wens_158_T_3) + ghv_158 <= _ghv_write_datas_158_ppm_out_res; + if (_ghv_wens_159_T | _ghv_wens_159_T_1 | _ghv_wens_159_T_2 | _ghv_wens_159_T_3) + ghv_159 <= _ghv_write_datas_159_ppm_out_res; + if (_ghv_wens_160_T | _ghv_wens_160_T_1 | _ghv_wens_160_T_2 | _ghv_wens_160_T_3) + ghv_160 <= _ghv_write_datas_160_ppm_out_res; + if (_ghv_wens_161_T | _ghv_wens_161_T_1 | _ghv_wens_161_T_2 | _ghv_wens_161_T_3) + ghv_161 <= _ghv_write_datas_161_ppm_out_res; + if (_ghv_wens_162_T | _ghv_wens_162_T_1 | _ghv_wens_162_T_2 | _ghv_wens_162_T_3) + ghv_162 <= _ghv_write_datas_162_ppm_out_res; + if (_ghv_wens_163_T | _ghv_wens_163_T_1 | _ghv_wens_163_T_2 | _ghv_wens_163_T_3) + ghv_163 <= _ghv_write_datas_163_ppm_out_res; + if (_ghv_wens_164_T | _ghv_wens_164_T_1 | _ghv_wens_164_T_2 | _ghv_wens_164_T_3) + ghv_164 <= _ghv_write_datas_164_ppm_out_res; + if (_ghv_wens_165_T | _ghv_wens_165_T_1 | _ghv_wens_165_T_2 | _ghv_wens_165_T_3) + ghv_165 <= _ghv_write_datas_165_ppm_out_res; + if (_ghv_wens_166_T | _ghv_wens_166_T_1 | _ghv_wens_166_T_2 | _ghv_wens_166_T_3) + ghv_166 <= _ghv_write_datas_166_ppm_out_res; + if (_ghv_wens_167_T | _ghv_wens_167_T_1 | _ghv_wens_167_T_2 | _ghv_wens_167_T_3) + ghv_167 <= _ghv_write_datas_167_ppm_out_res; + if (_ghv_wens_168_T | _ghv_wens_168_T_1 | _ghv_wens_168_T_2 | _ghv_wens_168_T_3) + ghv_168 <= _ghv_write_datas_168_ppm_out_res; + if (_ghv_wens_169_T | _ghv_wens_169_T_1 | _ghv_wens_169_T_2 | _ghv_wens_169_T_3) + ghv_169 <= _ghv_write_datas_169_ppm_out_res; + if (_ghv_wens_170_T | _ghv_wens_170_T_1 | _ghv_wens_170_T_2 | _ghv_wens_170_T_3) + ghv_170 <= _ghv_write_datas_170_ppm_out_res; + if (_ghv_wens_171_T | _ghv_wens_171_T_1 | _ghv_wens_171_T_2 | _ghv_wens_171_T_3) + ghv_171 <= _ghv_write_datas_171_ppm_out_res; + if (_ghv_wens_172_T | _ghv_wens_172_T_1 | _ghv_wens_172_T_2 | _ghv_wens_172_T_3) + ghv_172 <= _ghv_write_datas_172_ppm_out_res; + if (_ghv_wens_173_T | _ghv_wens_173_T_1 | _ghv_wens_173_T_2 | _ghv_wens_173_T_3) + ghv_173 <= _ghv_write_datas_173_ppm_out_res; + if (_ghv_wens_174_T | _ghv_wens_174_T_1 | _ghv_wens_174_T_2 | _ghv_wens_174_T_3) + ghv_174 <= _ghv_write_datas_174_ppm_out_res; + if (_ghv_wens_175_T | _ghv_wens_175_T_1 | _ghv_wens_175_T_2 | _ghv_wens_175_T_3) + ghv_175 <= _ghv_write_datas_175_ppm_out_res; + if (_ghv_wens_176_T | _ghv_wens_176_T_1 | _ghv_wens_176_T_2 | _ghv_wens_176_T_3) + ghv_176 <= _ghv_write_datas_176_ppm_out_res; + if (_ghv_wens_177_T | _ghv_wens_177_T_1 | _ghv_wens_177_T_2 | _ghv_wens_177_T_3) + ghv_177 <= _ghv_write_datas_177_ppm_out_res; + if (_ghv_wens_178_T | _ghv_wens_178_T_1 | _ghv_wens_178_T_2 | _ghv_wens_178_T_3) + ghv_178 <= _ghv_write_datas_178_ppm_out_res; + if (_ghv_wens_179_T | _ghv_wens_179_T_1 | _ghv_wens_179_T_2 | _ghv_wens_179_T_3) + ghv_179 <= _ghv_write_datas_179_ppm_out_res; + if (_ghv_wens_180_T | _ghv_wens_180_T_1 | _ghv_wens_180_T_2 | _ghv_wens_180_T_3) + ghv_180 <= _ghv_write_datas_180_ppm_out_res; + if (_ghv_wens_181_T | _ghv_wens_181_T_1 | _ghv_wens_181_T_2 | _ghv_wens_181_T_3) + ghv_181 <= _ghv_write_datas_181_ppm_out_res; + if (_ghv_wens_182_T | _ghv_wens_182_T_1 | _ghv_wens_182_T_2 | _ghv_wens_182_T_3) + ghv_182 <= _ghv_write_datas_182_ppm_out_res; + if (_ghv_wens_183_T | _ghv_wens_183_T_1 | _ghv_wens_183_T_2 | _ghv_wens_183_T_3) + ghv_183 <= _ghv_write_datas_183_ppm_out_res; + if (_ghv_wens_184_T | _ghv_wens_184_T_1 | _ghv_wens_184_T_2 | _ghv_wens_184_T_3) + ghv_184 <= _ghv_write_datas_184_ppm_out_res; + if (_ghv_wens_185_T | _ghv_wens_185_T_1 | _ghv_wens_185_T_2 | _ghv_wens_185_T_3) + ghv_185 <= _ghv_write_datas_185_ppm_out_res; + if (_ghv_wens_186_T | _ghv_wens_186_T_1 | _ghv_wens_186_T_2 | _ghv_wens_186_T_3) + ghv_186 <= _ghv_write_datas_186_ppm_out_res; + if (_ghv_wens_187_T | _ghv_wens_187_T_1 | _ghv_wens_187_T_2 | _ghv_wens_187_T_3) + ghv_187 <= _ghv_write_datas_187_ppm_out_res; + if (_ghv_wens_188_T | _ghv_wens_188_T_1 | _ghv_wens_188_T_2 | _ghv_wens_188_T_3) + ghv_188 <= _ghv_write_datas_188_ppm_out_res; + if (_ghv_wens_189_T | _ghv_wens_189_T_1 | _ghv_wens_189_T_2 | _ghv_wens_189_T_3) + ghv_189 <= _ghv_write_datas_189_ppm_out_res; + if (_ghv_wens_190_T | _ghv_wens_190_T_1 | _ghv_wens_190_T_2 | _ghv_wens_190_T_3) + ghv_190 <= _ghv_write_datas_190_ppm_out_res; + if (_ghv_wens_191_T | _ghv_wens_191_T_1 | _ghv_wens_191_T_2 | _ghv_wens_191_T_3) + ghv_191 <= _ghv_write_datas_191_ppm_out_res; + if (_ghv_wens_192_T | _ghv_wens_192_T_1 | _ghv_wens_192_T_2 | _ghv_wens_192_T_3) + ghv_192 <= _ghv_write_datas_192_ppm_out_res; + if (_ghv_wens_193_T | _ghv_wens_193_T_1 | _ghv_wens_193_T_2 | _ghv_wens_193_T_3) + ghv_193 <= _ghv_write_datas_193_ppm_out_res; + if (_ghv_wens_194_T | _ghv_wens_194_T_1 | _ghv_wens_194_T_2 | _ghv_wens_194_T_3) + ghv_194 <= _ghv_write_datas_194_ppm_out_res; + if (_ghv_wens_195_T | _ghv_wens_195_T_1 | _ghv_wens_195_T_2 | _ghv_wens_195_T_3) + ghv_195 <= _ghv_write_datas_195_ppm_out_res; + if (_ghv_wens_196_T | _ghv_wens_196_T_1 | _ghv_wens_196_T_2 | _ghv_wens_196_T_3) + ghv_196 <= _ghv_write_datas_196_ppm_out_res; + if (_ghv_wens_197_T | _ghv_wens_197_T_1 | _ghv_wens_197_T_2 | _ghv_wens_197_T_3) + ghv_197 <= _ghv_write_datas_197_ppm_out_res; + if (_ghv_wens_198_T | _ghv_wens_198_T_1 | _ghv_wens_198_T_2 | _ghv_wens_198_T_3) + ghv_198 <= _ghv_write_datas_198_ppm_out_res; + if (_ghv_wens_199_T | _ghv_wens_199_T_1 | _ghv_wens_199_T_2 | _ghv_wens_199_T_3) + ghv_199 <= _ghv_write_datas_199_ppm_out_res; + if (_ghv_wens_200_T | _ghv_wens_200_T_1 | _ghv_wens_200_T_2 | _ghv_wens_200_T_3) + ghv_200 <= _ghv_write_datas_200_ppm_out_res; + if (_ghv_wens_201_T | _ghv_wens_201_T_1 | _ghv_wens_201_T_2 | _ghv_wens_201_T_3) + ghv_201 <= _ghv_write_datas_201_ppm_out_res; + if (_ghv_wens_202_T | _ghv_wens_202_T_1 | _ghv_wens_202_T_2 | _ghv_wens_202_T_3) + ghv_202 <= _ghv_write_datas_202_ppm_out_res; + if (_ghv_wens_203_T | _ghv_wens_203_T_1 | _ghv_wens_203_T_2 | _ghv_wens_203_T_3) + ghv_203 <= _ghv_write_datas_203_ppm_out_res; + if (_ghv_wens_204_T | _ghv_wens_204_T_1 | _ghv_wens_204_T_2 | _ghv_wens_204_T_3) + ghv_204 <= _ghv_write_datas_204_ppm_out_res; + if (_ghv_wens_205_T | _ghv_wens_205_T_1 | _ghv_wens_205_T_2 | _ghv_wens_205_T_3) + ghv_205 <= _ghv_write_datas_205_ppm_out_res; + if (_ghv_wens_206_T | _ghv_wens_206_T_1 | _ghv_wens_206_T_2 | _ghv_wens_206_T_3) + ghv_206 <= _ghv_write_datas_206_ppm_out_res; + if (_ghv_wens_207_T | _ghv_wens_207_T_1 | _ghv_wens_207_T_2 | _ghv_wens_207_T_3) + ghv_207 <= _ghv_write_datas_207_ppm_out_res; + if (_ghv_wens_208_T | _ghv_wens_208_T_1 | _ghv_wens_208_T_2 | _ghv_wens_208_T_3) + ghv_208 <= _ghv_write_datas_208_ppm_out_res; + if (_ghv_wens_209_T | _ghv_wens_209_T_1 | _ghv_wens_209_T_2 | _ghv_wens_209_T_3) + ghv_209 <= _ghv_write_datas_209_ppm_out_res; + if (_ghv_wens_210_T | _ghv_wens_210_T_1 | _ghv_wens_210_T_2 | _ghv_wens_210_T_3) + ghv_210 <= _ghv_write_datas_210_ppm_out_res; + if (_ghv_wens_211_T | _ghv_wens_211_T_1 | _ghv_wens_211_T_2 | _ghv_wens_211_T_3) + ghv_211 <= _ghv_write_datas_211_ppm_out_res; + if (_ghv_wens_212_T | _ghv_wens_212_T_1 | _ghv_wens_212_T_2 | _ghv_wens_212_T_3) + ghv_212 <= _ghv_write_datas_212_ppm_out_res; + if (_ghv_wens_213_T | _ghv_wens_213_T_1 | _ghv_wens_213_T_2 | _ghv_wens_213_T_3) + ghv_213 <= _ghv_write_datas_213_ppm_out_res; + if (_ghv_wens_214_T | _ghv_wens_214_T_1 | _ghv_wens_214_T_2 | _ghv_wens_214_T_3) + ghv_214 <= _ghv_write_datas_214_ppm_out_res; + if (_ghv_wens_215_T | _ghv_wens_215_T_1 | _ghv_wens_215_T_2 | _ghv_wens_215_T_3) + ghv_215 <= _ghv_write_datas_215_ppm_out_res; + if (_ghv_wens_216_T | _ghv_wens_216_T_1 | _ghv_wens_216_T_2 | _ghv_wens_216_T_3) + ghv_216 <= _ghv_write_datas_216_ppm_out_res; + if (_ghv_wens_217_T | _ghv_wens_217_T_1 | _ghv_wens_217_T_2 | _ghv_wens_217_T_3) + ghv_217 <= _ghv_write_datas_217_ppm_out_res; + if (_ghv_wens_218_T | _ghv_wens_218_T_1 | _ghv_wens_218_T_2 | _ghv_wens_218_T_3) + ghv_218 <= _ghv_write_datas_218_ppm_out_res; + if (_ghv_wens_219_T | _ghv_wens_219_T_1 | _ghv_wens_219_T_2 | _ghv_wens_219_T_3) + ghv_219 <= _ghv_write_datas_219_ppm_out_res; + if (_ghv_wens_220_T | _ghv_wens_220_T_1 | _ghv_wens_220_T_2 | _ghv_wens_220_T_3) + ghv_220 <= _ghv_write_datas_220_ppm_out_res; + if (_ghv_wens_221_T | _ghv_wens_221_T_1 | _ghv_wens_221_T_2 | _ghv_wens_221_T_3) + ghv_221 <= _ghv_write_datas_221_ppm_out_res; + if (_ghv_wens_222_T | _ghv_wens_222_T_1 | _ghv_wens_222_T_2 | _ghv_wens_222_T_3) + ghv_222 <= _ghv_write_datas_222_ppm_out_res; + if (_ghv_wens_223_T | _ghv_wens_223_T_1 | _ghv_wens_223_T_2 | _ghv_wens_223_T_3) + ghv_223 <= _ghv_write_datas_223_ppm_out_res; + if (_ghv_wens_224_T | _ghv_wens_224_T_1 | _ghv_wens_224_T_2 | _ghv_wens_224_T_3) + ghv_224 <= _ghv_write_datas_224_ppm_out_res; + if (_ghv_wens_225_T | _ghv_wens_225_T_1 | _ghv_wens_225_T_2 | _ghv_wens_225_T_3) + ghv_225 <= _ghv_write_datas_225_ppm_out_res; + if (_ghv_wens_226_T | _ghv_wens_226_T_1 | _ghv_wens_226_T_2 | _ghv_wens_226_T_3) + ghv_226 <= _ghv_write_datas_226_ppm_out_res; + if (_ghv_wens_227_T | _ghv_wens_227_T_1 | _ghv_wens_227_T_2 | _ghv_wens_227_T_3) + ghv_227 <= _ghv_write_datas_227_ppm_out_res; + if (_ghv_wens_228_T | _ghv_wens_228_T_1 | _ghv_wens_228_T_2 | _ghv_wens_228_T_3) + ghv_228 <= _ghv_write_datas_228_ppm_out_res; + if (_ghv_wens_229_T | _ghv_wens_229_T_1 | _ghv_wens_229_T_2 | _ghv_wens_229_T_3) + ghv_229 <= _ghv_write_datas_229_ppm_out_res; + if (_ghv_wens_230_T | _ghv_wens_230_T_1 | _ghv_wens_230_T_2 | _ghv_wens_230_T_3) + ghv_230 <= _ghv_write_datas_230_ppm_out_res; + if (_ghv_wens_231_T | _ghv_wens_231_T_1 | _ghv_wens_231_T_2 | _ghv_wens_231_T_3) + ghv_231 <= _ghv_write_datas_231_ppm_out_res; + if (_ghv_wens_232_T | _ghv_wens_232_T_1 | _ghv_wens_232_T_2 | _ghv_wens_232_T_3) + ghv_232 <= _ghv_write_datas_232_ppm_out_res; + if (_ghv_wens_233_T | _ghv_wens_233_T_1 | _ghv_wens_233_T_2 | _ghv_wens_233_T_3) + ghv_233 <= _ghv_write_datas_233_ppm_out_res; + if (_ghv_wens_234_T | _ghv_wens_234_T_1 | _ghv_wens_234_T_2 | _ghv_wens_234_T_3) + ghv_234 <= _ghv_write_datas_234_ppm_out_res; + if (_ghv_wens_235_T | _ghv_wens_235_T_1 | _ghv_wens_235_T_2 | _ghv_wens_235_T_3) + ghv_235 <= _ghv_write_datas_235_ppm_out_res; + if (_ghv_wens_236_T | _ghv_wens_236_T_1 | _ghv_wens_236_T_2 | _ghv_wens_236_T_3) + ghv_236 <= _ghv_write_datas_236_ppm_out_res; + if (_ghv_wens_237_T | _ghv_wens_237_T_1 | _ghv_wens_237_T_2 | _ghv_wens_237_T_3) + ghv_237 <= _ghv_write_datas_237_ppm_out_res; + if (_ghv_wens_238_T | _ghv_wens_238_T_1 | _ghv_wens_238_T_2 | _ghv_wens_238_T_3) + ghv_238 <= _ghv_write_datas_238_ppm_out_res; + if (_ghv_wens_239_T | _ghv_wens_239_T_1 | _ghv_wens_239_T_2 | _ghv_wens_239_T_3) + ghv_239 <= _ghv_write_datas_239_ppm_out_res; + if (_ghv_wens_240_T | _ghv_wens_240_T_1 | _ghv_wens_240_T_2 | _ghv_wens_240_T_3) + ghv_240 <= _ghv_write_datas_240_ppm_out_res; + if (_ghv_wens_241_T | _ghv_wens_241_T_1 | _ghv_wens_241_T_2 | _ghv_wens_241_T_3) + ghv_241 <= _ghv_write_datas_241_ppm_out_res; + if (_ghv_wens_242_T | _ghv_wens_242_T_1 | _ghv_wens_242_T_2 | _ghv_wens_242_T_3) + ghv_242 <= _ghv_write_datas_242_ppm_out_res; + if (_ghv_wens_243_T | _ghv_wens_243_T_1 | _ghv_wens_243_T_2 | _ghv_wens_243_T_3) + ghv_243 <= _ghv_write_datas_243_ppm_out_res; + if (_ghv_wens_244_T | _ghv_wens_244_T_1 | _ghv_wens_244_T_2 | _ghv_wens_244_T_3) + ghv_244 <= _ghv_write_datas_244_ppm_out_res; + if (_ghv_wens_245_T | _ghv_wens_245_T_1 | _ghv_wens_245_T_2 | _ghv_wens_245_T_3) + ghv_245 <= _ghv_write_datas_245_ppm_out_res; + if (_ghv_wens_246_T | _ghv_wens_246_T_1 | _ghv_wens_246_T_2 | _ghv_wens_246_T_3) + ghv_246 <= _ghv_write_datas_246_ppm_out_res; + if (_ghv_wens_247_T | _ghv_wens_247_T_1 | _ghv_wens_247_T_2 | _ghv_wens_247_T_3) + ghv_247 <= _ghv_write_datas_247_ppm_out_res; + if (_ghv_wens_248_T | _ghv_wens_248_T_1 | _ghv_wens_248_T_2 | _ghv_wens_248_T_3) + ghv_248 <= _ghv_write_datas_248_ppm_out_res; + if (_ghv_wens_249_T | _ghv_wens_249_T_1 | _ghv_wens_249_T_2 | _ghv_wens_249_T_3) + ghv_249 <= _ghv_write_datas_249_ppm_out_res; + if (_ghv_wens_250_T | _ghv_wens_250_T_1 | _ghv_wens_250_T_2 | _ghv_wens_250_T_3) + ghv_250 <= _ghv_write_datas_250_ppm_out_res; + if (_ghv_wens_251_T | _ghv_wens_251_T_1 | _ghv_wens_251_T_2 | _ghv_wens_251_T_3) + ghv_251 <= _ghv_write_datas_251_ppm_out_res; + if (_ghv_wens_252_T | _ghv_wens_252_T_1 | _ghv_wens_252_T_2 | _ghv_wens_252_T_3) + ghv_252 <= _ghv_write_datas_252_ppm_out_res; + if (_ghv_wens_253_T | _ghv_wens_253_T_1 | _ghv_wens_253_T_2 | _ghv_wens_253_T_3) + ghv_253 <= _ghv_write_datas_253_ppm_out_res; + if (_ghv_wens_254_T | _ghv_wens_254_T_1 | _ghv_wens_254_T_2 | _ghv_wens_254_T_3) + ghv_254 <= _ghv_write_datas_254_ppm_out_res; + if (_ghv_wens_255_T | _ghv_wens_255_T_1 | _ghv_wens_255_T_2 | _ghv_wens_255_T_3) + ghv_255 <= _ghv_write_datas_255_ppm_out_res; + s0_ghist_ptr_reg_dup_0_flag <= _s0_ghist_ptr_dup_0_ppm_out_res_flag; + s0_ghist_ptr_reg_dup_0_value <= _s0_ghist_ptr_dup_0_ppm_out_res_value; + s0_ghist_ptr_reg_dup_1_flag <= _s0_ghist_ptr_dup_1_ppm_out_res_flag; + s0_ghist_ptr_reg_dup_1_value <= _s0_ghist_ptr_dup_1_ppm_out_res_value; + s0_ghist_ptr_reg_dup_2_flag <= _s0_ghist_ptr_dup_2_ppm_out_res_flag; + s0_ghist_ptr_reg_dup_2_value <= _s0_ghist_ptr_dup_2_ppm_out_res_value; + s0_ghist_ptr_reg_dup_3_flag <= _s0_ghist_ptr_dup_3_ppm_out_res_flag; + s0_ghist_ptr_reg_dup_3_value <= _s0_ghist_ptr_dup_3_ppm_out_res_value; + if (io_ftq_to_bpu_redirect_valid | do_redirect_dup_next_valid_last_r) + do_redirect_dup_next_valid_last_r <= io_ftq_to_bpu_redirect_valid; + if (s1_fire_dup_0) begin + previous_s1_pred_info_hit_0 <= _predictors_io_out_s1_full_pred_0_hit; + previous_s1_pred_info_hit_1 <= _predictors_io_out_s1_full_pred_1_hit; + previous_s1_pred_info_hit_2 <= _predictors_io_out_s1_full_pred_2_hit; + previous_s1_pred_info_hit_3 <= _predictors_io_out_s1_full_pred_3_hit; + previous_s1_pred_info_target_0 <= + (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_targets_0 + : 41'h0) + | (~s1_pred_info_takenMask_0_0 & s1_pred_info_takenMask_0_1 + & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_targets_1 + : 41'h0) + | ({s1_pred_info_takenMask_0_1, s1_pred_info_takenMask_0_0} == 2'h0 + & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_fallThroughAddr + : 41'h0) | _GEN_4; + previous_s1_pred_info_target_1 <= + (s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_targets_0 + : 41'h0) + | (~s1_pred_info_takenMask_1_0 & s1_pred_info_takenMask_1_1 + & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_targets_1 + : 41'h0) + | ({s1_pred_info_takenMask_1_1, s1_pred_info_takenMask_1_0} == 2'h0 + & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_fallThroughAddr + : 41'h0) | _GEN_5; + previous_s1_pred_info_target_2 <= + (s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_targets_0 + : 41'h0) + | (~s1_pred_info_takenMask_2_0 & s1_pred_info_takenMask_2_1 + & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_targets_1 + : 41'h0) + | ({s1_pred_info_takenMask_2_1, s1_pred_info_takenMask_2_0} == 2'h0 + & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_fallThroughAddr + : 41'h0) | _GEN_6; + previous_s1_pred_info_target_3 <= + (s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_targets_0 + : 41'h0) + | (~s1_pred_info_takenMask_3_0 & s1_pred_info_takenMask_3_1 + & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_targets_1 + : 41'h0) + | ({s1_pred_info_takenMask_3_1, s1_pred_info_takenMask_3_0} == 2'h0 + & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_fallThroughAddr + : 41'h0) | _GEN_7; + previous_s1_pred_info_lastBrPosOH_0_0 <= + ~_predictors_io_out_s1_full_pred_0_hit + | ~(_predictors_io_out_s1_full_pred_0_slot_valids_0 | _s1_ghv_wdatas_T_190528); + previous_s1_pred_info_lastBrPosOH_0_1 <= + _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_GEN_99 | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit; + previous_s1_pred_info_lastBrPosOH_0_2 <= + _s1_ghv_wdatas_T_190528 & ~_GEN_99 & _predictors_io_out_s1_full_pred_0_hit; + previous_s1_pred_info_lastBrPosOH_1_0 <= + ~_predictors_io_out_s1_full_pred_1_hit | ~_GEN_8; + previous_s1_pred_info_lastBrPosOH_1_1 <= + _predictors_io_out_s1_full_pred_1_slot_valids_0 & _GEN_10 + & _predictors_io_out_s1_full_pred_1_hit; + previous_s1_pred_info_lastBrPosOH_1_2 <= + _s1_ghv_wdatas_T_190589 & ~_GEN_9 & _predictors_io_out_s1_full_pred_1_hit; + previous_s1_pred_info_lastBrPosOH_2_0 <= + ~_predictors_io_out_s1_full_pred_2_hit | ~_GEN_11; + previous_s1_pred_info_lastBrPosOH_2_1 <= + _predictors_io_out_s1_full_pred_2_slot_valids_0 & _GEN_13 + & _predictors_io_out_s1_full_pred_2_hit; + previous_s1_pred_info_lastBrPosOH_2_2 <= + _s1_ghv_wdatas_T_190650 & ~_GEN_12 & _predictors_io_out_s1_full_pred_2_hit; + previous_s1_pred_info_lastBrPosOH_3_0 <= + ~_predictors_io_out_s1_full_pred_3_hit | ~_GEN_14; + previous_s1_pred_info_lastBrPosOH_3_1 <= + _predictors_io_out_s1_full_pred_3_slot_valids_0 & _GEN_16 + & _predictors_io_out_s1_full_pred_3_hit; + previous_s1_pred_info_lastBrPosOH_3_2 <= + _s1_ghv_wdatas_T_190711 & ~_GEN_15 & _predictors_io_out_s1_full_pred_3_hit; + previous_s1_pred_info_taken_0 <= + |{_predictors_io_out_s1_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_94 | ~_predictors_io_out_s1_full_pred_0_is_br_sharing) + & _predictors_io_out_s1_full_pred_0_hit, + s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit}; + previous_s1_pred_info_taken_1 <= + |{_predictors_io_out_s1_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_115 | ~_predictors_io_out_s1_full_pred_1_is_br_sharing) + & _predictors_io_out_s1_full_pred_1_hit, + s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit}; + previous_s1_pred_info_taken_2 <= + |{_predictors_io_out_s1_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_136 | ~_predictors_io_out_s1_full_pred_2_is_br_sharing) + & _predictors_io_out_s1_full_pred_2_hit, + s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit}; + previous_s1_pred_info_taken_3 <= + |{_predictors_io_out_s1_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_157 | ~_predictors_io_out_s1_full_pred_3_is_br_sharing) + & _predictors_io_out_s1_full_pred_3_hit, + s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit}; + previous_s1_pred_info_takenMask_0_0 <= s1_pred_info_takenMask_0_0; + previous_s1_pred_info_takenMask_0_1 <= s1_pred_info_takenMask_0_1; + previous_s1_pred_info_takenMask_1_0 <= s1_pred_info_takenMask_1_0; + previous_s1_pred_info_takenMask_1_1 <= s1_pred_info_takenMask_1_1; + previous_s1_pred_info_takenMask_2_0 <= s1_pred_info_takenMask_2_0; + previous_s1_pred_info_takenMask_2_1 <= s1_pred_info_takenMask_2_1; + previous_s1_pred_info_takenMask_3_0 <= s1_pred_info_takenMask_3_0; + previous_s1_pred_info_takenMask_3_1 <= s1_pred_info_takenMask_3_1; + previous_s1_pred_info_cfiIndex_0 <= + (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_offsets_0 + : _predictors_io_out_s1_full_pred_0_offsets_1) + | {4{{_predictors_io_out_s1_full_pred_0_slot_valids_1 + & (_cfiIndex_bits_T_94 + | ~_predictors_io_out_s1_full_pred_0_is_br_sharing) + & _predictors_io_out_s1_full_pred_0_hit, + s1_pred_info_takenMask_0_0 + & _predictors_io_out_s1_full_pred_0_hit} == 2'h0}}; + previous_s1_pred_info_cfiIndex_1 <= + (s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_offsets_0 + : _predictors_io_out_s1_full_pred_1_offsets_1) + | {4{{_predictors_io_out_s1_full_pred_1_slot_valids_1 + & (_cfiIndex_bits_T_115 + | ~_predictors_io_out_s1_full_pred_1_is_br_sharing) + & _predictors_io_out_s1_full_pred_1_hit, + s1_pred_info_takenMask_1_0 + & _predictors_io_out_s1_full_pred_1_hit} == 2'h0}}; + previous_s1_pred_info_cfiIndex_2 <= + (s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_offsets_0 + : _predictors_io_out_s1_full_pred_2_offsets_1) + | {4{{_predictors_io_out_s1_full_pred_2_slot_valids_1 + & (_cfiIndex_bits_T_136 + | ~_predictors_io_out_s1_full_pred_2_is_br_sharing) + & _predictors_io_out_s1_full_pred_2_hit, + s1_pred_info_takenMask_2_0 + & _predictors_io_out_s1_full_pred_2_hit} == 2'h0}}; + previous_s1_pred_info_cfiIndex_3 <= + (s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_offsets_0 + : _predictors_io_out_s1_full_pred_3_offsets_1) + | {4{{_predictors_io_out_s1_full_pred_3_slot_valids_1 + & (_cfiIndex_bits_T_157 + | ~_predictors_io_out_s1_full_pred_3_is_br_sharing) + & _predictors_io_out_s1_full_pred_3_hit, + s1_pred_info_takenMask_3_0 + & _predictors_io_out_s1_full_pred_3_hit} == 2'h0}}; + end + predictors_io_update_valid_REG <= io_ftq_to_bpu_update_valid; + end + end // always @(posedge, posedge) + wire [40:0] _GEN_101 = {5'h0, _reset_vector_delay_io_out}; + always @(posedge clock) begin + s0_pc_reg_dup_0 <= REG_1 ? _GEN_101 : _s0_pc_dup_0_ppm_out_res; + s0_pc_reg_dup_1 <= REG_1 ? _GEN_101 : _s0_pc_dup_1_ppm_out_res; + s0_pc_reg_dup_2 <= REG_1 ? _GEN_101 : _s0_pc_dup_2_ppm_out_res; + s0_pc_reg_dup_3 <= REG_1 ? _GEN_101 : _s0_pc_dup_3_ppm_out_res; + REG <= reset; + REG_1 <= REG & ~reset; + if (io_ftq_to_bpu_redirect_valid) begin + do_redirect_dup_next_bits_r_level <= io_ftq_to_bpu_redirect_bits_level; + do_redirect_dup_next_bits_r_cfiUpdate_pc <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_pc; + do_redirect_dup_next_bits_r_cfiUpdate_pd_isRVC <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC; + do_redirect_dup_next_bits_r_cfiUpdate_pd_isCall <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall; + do_redirect_dup_next_bits_r_cfiUpdate_pd_isRet <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet; + do_redirect_dup_next_bits_r_cfiUpdate_ssp <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp; + do_redirect_dup_next_bits_r_cfiUpdate_sctr <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr; + do_redirect_dup_next_bits_r_cfiUpdate_TOSW_flag <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag; + do_redirect_dup_next_bits_r_cfiUpdate_TOSW_value <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value; + do_redirect_dup_next_bits_r_cfiUpdate_TOSR_flag <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag; + do_redirect_dup_next_bits_r_cfiUpdate_TOSR_value <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value; + do_redirect_dup_next_bits_r_cfiUpdate_NOS_flag <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag; + do_redirect_dup_next_bits_r_cfiUpdate_NOS_value <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_3 <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3; + do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH; + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_flag <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag; + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value; + do_redirect_dup_next_bits_r_cfiUpdate_target <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_target; + do_redirect_dup_next_bits_r_cfiUpdate_taken <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_taken; + do_redirect_dup_next_bits_r_cfiUpdate_shift <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_shift; + do_redirect_dup_next_bits_r_cfiUpdate_addIntoHist <= + io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist; + end + if (s1_fire_dup_0) begin + s2_ftq_idx_flag <= io_ftq_to_bpu_enq_ptr_flag; + s2_ftq_idx_value <= io_ftq_to_bpu_enq_ptr_value; + end + if (s2_valid_dup_3) begin + s3_ftq_idx_flag <= s2_ftq_idx_flag; + s3_ftq_idx_value <= s2_ftq_idx_value; + end + if (io_ftq_to_bpu_update_valid) begin + predictors_io_update_bits_r_pc <= io_ftq_to_bpu_update_bits_pc; + predictors_io_update_bits_r_spec_info_folded_hist_hist_17_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_16_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_15_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_14_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_13_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_12_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_11_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_10_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_9_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_8_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_7_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_6_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_5_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_4_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_3_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_2_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist; + predictors_io_update_bits_r_spec_info_folded_hist_hist_1_folded_hist <= + io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist; + predictors_io_update_bits_r_ftb_entry_valid <= + io_ftq_to_bpu_update_bits_ftb_entry_valid; + predictors_io_update_bits_r_ftb_entry_brSlots_0_offset <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset; + predictors_io_update_bits_r_ftb_entry_brSlots_0_lower <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower; + predictors_io_update_bits_r_ftb_entry_brSlots_0_tarStat <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat; + predictors_io_update_bits_r_ftb_entry_brSlots_0_sharing <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing; + predictors_io_update_bits_r_ftb_entry_brSlots_0_valid <= + io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid; + predictors_io_update_bits_r_ftb_entry_tailSlot_offset <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset; + predictors_io_update_bits_r_ftb_entry_tailSlot_lower <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower; + predictors_io_update_bits_r_ftb_entry_tailSlot_tarStat <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat; + predictors_io_update_bits_r_ftb_entry_tailSlot_sharing <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing; + predictors_io_update_bits_r_ftb_entry_tailSlot_valid <= + io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid; + predictors_io_update_bits_r_ftb_entry_pftAddr <= + io_ftq_to_bpu_update_bits_ftb_entry_pftAddr; + predictors_io_update_bits_r_ftb_entry_carry <= + io_ftq_to_bpu_update_bits_ftb_entry_carry; + predictors_io_update_bits_r_ftb_entry_isCall <= + io_ftq_to_bpu_update_bits_ftb_entry_isCall; + predictors_io_update_bits_r_ftb_entry_isRet <= + io_ftq_to_bpu_update_bits_ftb_entry_isRet; + predictors_io_update_bits_r_ftb_entry_isJalr <= + io_ftq_to_bpu_update_bits_ftb_entry_isJalr; + predictors_io_update_bits_r_ftb_entry_last_may_be_rvi_call <= + io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call; + predictors_io_update_bits_r_ftb_entry_always_taken_0 <= + io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0; + predictors_io_update_bits_r_ftb_entry_always_taken_1 <= + io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1; + predictors_io_update_bits_r_cfi_idx_valid <= + io_ftq_to_bpu_update_bits_cfi_idx_valid; + predictors_io_update_bits_r_cfi_idx_bits <= io_ftq_to_bpu_update_bits_cfi_idx_bits; + predictors_io_update_bits_r_br_taken_mask_0 <= + io_ftq_to_bpu_update_bits_br_taken_mask_0; + predictors_io_update_bits_r_br_taken_mask_1 <= + io_ftq_to_bpu_update_bits_br_taken_mask_1; + predictors_io_update_bits_r_jmp_taken <= io_ftq_to_bpu_update_bits_jmp_taken; + predictors_io_update_bits_r_mispred_mask_0 <= + io_ftq_to_bpu_update_bits_mispred_mask_0; + predictors_io_update_bits_r_mispred_mask_1 <= + io_ftq_to_bpu_update_bits_mispred_mask_1; + predictors_io_update_bits_r_mispred_mask_2 <= + io_ftq_to_bpu_update_bits_mispred_mask_2; + predictors_io_update_bits_r_old_entry <= io_ftq_to_bpu_update_bits_old_entry; + predictors_io_update_bits_r_meta <= io_ftq_to_bpu_update_bits_meta; + predictors_io_update_bits_r_full_target <= io_ftq_to_bpu_update_bits_full_target; + end + io_perf_0_value_REG <= _predictors_io_perf_0_value; + io_perf_0_value_REG_1 <= io_perf_0_value_REG; + io_perf_1_value_REG <= _predictors_io_perf_1_value; + io_perf_1_value_REG_1 <= io_perf_1_value_REG; + io_perf_2_value_REG <= _predictors_io_perf_2_value; + io_perf_2_value_REG_1 <= io_perf_2_value_REG; + io_perf_3_value_REG <= _predictors_io_perf_3_value; + io_perf_3_value_REG_1 <= io_perf_3_value_REG; + io_perf_4_value_REG <= _predictors_io_perf_4_value; + io_perf_4_value_REG_1 <= io_perf_4_value_REG; + io_perf_5_value_REG <= _predictors_io_perf_5_value; + io_perf_5_value_REG_1 <= io_perf_5_value_REG; + io_perf_6_value_REG <= _predictors_io_perf_6_value; + io_perf_6_value_REG_1 <= io_perf_6_value_REG; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:210]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [7:0] i = 8'h0; i < 8'hD3; i += 8'h1) begin + _RANDOM[i] = `RANDOM; + end + s1_valid_dup_3 = _RANDOM[8'h3][27]; + s2_valid_dup_3 = _RANDOM[8'h3][28]; + s3_valid_dup_3 = _RANDOM[8'h3][29]; + s0_pc_reg_dup_0 = {_RANDOM[8'h3][31:30], _RANDOM[8'h4], _RANDOM[8'h5][6:0]}; + s0_pc_reg_dup_1 = {_RANDOM[8'h5][31:7], _RANDOM[8'h6][15:0]}; + s0_pc_reg_dup_2 = {_RANDOM[8'h6][31:16], _RANDOM[8'h7][24:0]}; + s0_pc_reg_dup_3 = {_RANDOM[8'h7][31:25], _RANDOM[8'h8], _RANDOM[8'h9][1:0]}; + REG = _RANDOM[8'h9][2]; + REG_1 = _RANDOM[8'h9][3]; + s0_folded_gh_reg_dup_1_hist_17_folded_hist = _RANDOM[8'h11][29:19]; + s0_folded_gh_reg_dup_1_hist_16_folded_hist = + {_RANDOM[8'h11][31:30], _RANDOM[8'h12][8:0]}; + s0_folded_gh_reg_dup_1_hist_15_folded_hist = _RANDOM[8'h12][15:9]; + s0_folded_gh_reg_dup_1_hist_14_folded_hist = _RANDOM[8'h12][23:16]; + s0_folded_gh_reg_dup_1_hist_13_folded_hist = + {_RANDOM[8'h12][31:24], _RANDOM[8'h13][0]}; + s0_folded_gh_reg_dup_1_hist_12_folded_hist = _RANDOM[8'h13][4:1]; + s0_folded_gh_reg_dup_1_hist_11_folded_hist = _RANDOM[8'h13][12:5]; + s0_folded_gh_reg_dup_1_hist_10_folded_hist = _RANDOM[8'h13][21:13]; + s0_folded_gh_reg_dup_1_hist_9_folded_hist = _RANDOM[8'h13][28:22]; + s0_folded_gh_reg_dup_1_hist_8_folded_hist = + {_RANDOM[8'h13][31:29], _RANDOM[8'h14][4:0]}; + s0_folded_gh_reg_dup_1_hist_7_folded_hist = _RANDOM[8'h14][11:5]; + s0_folded_gh_reg_dup_1_hist_6_folded_hist = _RANDOM[8'h14][20:12]; + s0_folded_gh_reg_dup_1_hist_5_folded_hist = _RANDOM[8'h14][27:21]; + s0_folded_gh_reg_dup_1_hist_4_folded_hist = + {_RANDOM[8'h14][31:28], _RANDOM[8'h15][3:0]}; + s0_folded_gh_reg_dup_1_hist_3_folded_hist = _RANDOM[8'h15][11:4]; + s0_folded_gh_reg_dup_1_hist_2_folded_hist = _RANDOM[8'h15][19:12]; + s0_folded_gh_reg_dup_1_hist_1_folded_hist = _RANDOM[8'h15][30:20]; + s0_folded_gh_reg_dup_1_hist_0_folded_hist = + {_RANDOM[8'h15][31], _RANDOM[8'h16][6:0]}; + s0_folded_gh_reg_dup_2_hist_17_folded_hist = _RANDOM[8'h16][17:7]; + s0_folded_gh_reg_dup_2_hist_16_folded_hist = _RANDOM[8'h16][28:18]; + s0_folded_gh_reg_dup_2_hist_15_folded_hist = + {_RANDOM[8'h16][31:29], _RANDOM[8'h17][3:0]}; + s0_folded_gh_reg_dup_2_hist_14_folded_hist = _RANDOM[8'h17][11:4]; + s0_folded_gh_reg_dup_2_hist_13_folded_hist = _RANDOM[8'h17][20:12]; + s0_folded_gh_reg_dup_2_hist_12_folded_hist = _RANDOM[8'h17][24:21]; + s0_folded_gh_reg_dup_2_hist_11_folded_hist = + {_RANDOM[8'h17][31:25], _RANDOM[8'h18][0]}; + s0_folded_gh_reg_dup_2_hist_10_folded_hist = _RANDOM[8'h18][9:1]; + s0_folded_gh_reg_dup_2_hist_9_folded_hist = _RANDOM[8'h18][16:10]; + s0_folded_gh_reg_dup_2_hist_8_folded_hist = _RANDOM[8'h18][24:17]; + s0_folded_gh_reg_dup_2_hist_7_folded_hist = _RANDOM[8'h18][31:25]; + s0_folded_gh_reg_dup_2_hist_6_folded_hist = _RANDOM[8'h19][8:0]; + s0_folded_gh_reg_dup_2_hist_5_folded_hist = _RANDOM[8'h19][15:9]; + s0_folded_gh_reg_dup_2_hist_4_folded_hist = _RANDOM[8'h19][23:16]; + s0_folded_gh_reg_dup_2_hist_3_folded_hist = _RANDOM[8'h19][31:24]; + s0_folded_gh_reg_dup_2_hist_2_folded_hist = _RANDOM[8'h1A][7:0]; + s0_folded_gh_reg_dup_2_hist_1_folded_hist = _RANDOM[8'h1A][18:8]; + s0_folded_gh_reg_dup_2_hist_0_folded_hist = _RANDOM[8'h1A][26:19]; + s0_folded_gh_reg_dup_3_hist_17_folded_hist = + {_RANDOM[8'h1A][31:27], _RANDOM[8'h1B][5:0]}; + s0_folded_gh_reg_dup_3_hist_16_folded_hist = _RANDOM[8'h1B][16:6]; + s0_folded_gh_reg_dup_3_hist_15_folded_hist = _RANDOM[8'h1B][23:17]; + s0_folded_gh_reg_dup_3_hist_14_folded_hist = _RANDOM[8'h1B][31:24]; + s0_folded_gh_reg_dup_3_hist_13_folded_hist = _RANDOM[8'h1C][8:0]; + s0_folded_gh_reg_dup_3_hist_12_folded_hist = _RANDOM[8'h1C][12:9]; + s0_folded_gh_reg_dup_3_hist_11_folded_hist = _RANDOM[8'h1C][20:13]; + s0_folded_gh_reg_dup_3_hist_10_folded_hist = _RANDOM[8'h1C][29:21]; + s0_folded_gh_reg_dup_3_hist_9_folded_hist = + {_RANDOM[8'h1C][31:30], _RANDOM[8'h1D][4:0]}; + s0_folded_gh_reg_dup_3_hist_8_folded_hist = _RANDOM[8'h1D][12:5]; + s0_folded_gh_reg_dup_3_hist_7_folded_hist = _RANDOM[8'h1D][19:13]; + s0_folded_gh_reg_dup_3_hist_6_folded_hist = _RANDOM[8'h1D][28:20]; + s0_folded_gh_reg_dup_3_hist_5_folded_hist = + {_RANDOM[8'h1D][31:29], _RANDOM[8'h1E][3:0]}; + s0_folded_gh_reg_dup_3_hist_4_folded_hist = _RANDOM[8'h1E][11:4]; + s0_folded_gh_reg_dup_3_hist_3_folded_hist = _RANDOM[8'h1E][19:12]; + s0_folded_gh_reg_dup_3_hist_2_folded_hist = _RANDOM[8'h1E][27:20]; + s0_folded_gh_reg_dup_3_hist_1_folded_hist = + {_RANDOM[8'h1E][31:28], _RANDOM[8'h1F][6:0]}; + s0_folded_gh_reg_dup_3_hist_0_folded_hist = _RANDOM[8'h1F][14:7]; + s1_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h24][13:3]; + s1_folded_gh_dup_1_hist_16_folded_hist = _RANDOM[8'h24][24:14]; + s1_folded_gh_dup_1_hist_15_folded_hist = _RANDOM[8'h24][31:25]; + s1_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h25][7:0]; + s1_folded_gh_dup_1_hist_13_folded_hist = _RANDOM[8'h25][16:8]; + s1_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h25][20:17]; + s1_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h25][28:21]; + s1_folded_gh_dup_1_hist_10_folded_hist = + {_RANDOM[8'h25][31:29], _RANDOM[8'h26][5:0]}; + s1_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h26][12:6]; + s1_folded_gh_dup_1_hist_8_folded_hist = _RANDOM[8'h26][20:13]; + s1_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h26][27:21]; + s1_folded_gh_dup_1_hist_6_folded_hist = + {_RANDOM[8'h26][31:28], _RANDOM[8'h27][4:0]}; + s1_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h27][11:5]; + s1_folded_gh_dup_1_hist_4_folded_hist = _RANDOM[8'h27][19:12]; + s1_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h27][27:20]; + s1_folded_gh_dup_1_hist_2_folded_hist = + {_RANDOM[8'h27][31:28], _RANDOM[8'h28][3:0]}; + s1_folded_gh_dup_1_hist_1_folded_hist = _RANDOM[8'h28][14:4]; + s1_folded_gh_dup_1_hist_0_folded_hist = _RANDOM[8'h28][22:15]; + s1_folded_gh_dup_2_hist_17_folded_hist = + {_RANDOM[8'h28][31:23], _RANDOM[8'h29][1:0]}; + s1_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h29][12:2]; + s1_folded_gh_dup_2_hist_15_folded_hist = _RANDOM[8'h29][19:13]; + s1_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h29][27:20]; + s1_folded_gh_dup_2_hist_13_folded_hist = + {_RANDOM[8'h29][31:28], _RANDOM[8'h2A][4:0]}; + s1_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h2A][8:5]; + s1_folded_gh_dup_2_hist_11_folded_hist = _RANDOM[8'h2A][16:9]; + s1_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h2A][25:17]; + s1_folded_gh_dup_2_hist_9_folded_hist = + {_RANDOM[8'h2A][31:26], _RANDOM[8'h2B][0]}; + s1_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h2B][8:1]; + s1_folded_gh_dup_2_hist_7_folded_hist = _RANDOM[8'h2B][15:9]; + s1_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h2B][24:16]; + s1_folded_gh_dup_2_hist_5_folded_hist = _RANDOM[8'h2B][31:25]; + s1_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h2C][7:0]; + s1_folded_gh_dup_2_hist_3_folded_hist = _RANDOM[8'h2C][15:8]; + s1_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h2C][23:16]; + s1_folded_gh_dup_2_hist_1_folded_hist = + {_RANDOM[8'h2C][31:24], _RANDOM[8'h2D][2:0]}; + s1_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h2D][10:3]; + s1_folded_gh_dup_3_hist_17_folded_hist = _RANDOM[8'h2D][21:11]; + s1_folded_gh_dup_3_hist_16_folded_hist = + {_RANDOM[8'h2D][31:22], _RANDOM[8'h2E][0]}; + s1_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h2E][7:1]; + s1_folded_gh_dup_3_hist_14_folded_hist = _RANDOM[8'h2E][15:8]; + s1_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h2E][24:16]; + s1_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h2E][28:25]; + s1_folded_gh_dup_3_hist_11_folded_hist = + {_RANDOM[8'h2E][31:29], _RANDOM[8'h2F][4:0]}; + s1_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h2F][13:5]; + s1_folded_gh_dup_3_hist_9_folded_hist = _RANDOM[8'h2F][20:14]; + s1_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h2F][28:21]; + s1_folded_gh_dup_3_hist_7_folded_hist = + {_RANDOM[8'h2F][31:29], _RANDOM[8'h30][3:0]}; + s1_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h30][12:4]; + s1_folded_gh_dup_3_hist_5_folded_hist = _RANDOM[8'h30][19:13]; + s1_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h30][27:20]; + s1_folded_gh_dup_3_hist_3_folded_hist = + {_RANDOM[8'h30][31:28], _RANDOM[8'h31][3:0]}; + s1_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h31][11:4]; + s1_folded_gh_dup_3_hist_1_folded_hist = _RANDOM[8'h31][22:12]; + s1_folded_gh_dup_3_hist_0_folded_hist = _RANDOM[8'h31][30:23]; + s2_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h36][29:19]; + s2_folded_gh_dup_1_hist_16_folded_hist = + {_RANDOM[8'h36][31:30], _RANDOM[8'h37][8:0]}; + s2_folded_gh_dup_1_hist_15_folded_hist = _RANDOM[8'h37][15:9]; + s2_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h37][23:16]; + s2_folded_gh_dup_1_hist_13_folded_hist = + {_RANDOM[8'h37][31:24], _RANDOM[8'h38][0]}; + s2_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h38][4:1]; + s2_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h38][12:5]; + s2_folded_gh_dup_1_hist_10_folded_hist = _RANDOM[8'h38][21:13]; + s2_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h38][28:22]; + s2_folded_gh_dup_1_hist_8_folded_hist = + {_RANDOM[8'h38][31:29], _RANDOM[8'h39][4:0]}; + s2_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h39][11:5]; + s2_folded_gh_dup_1_hist_6_folded_hist = _RANDOM[8'h39][20:12]; + s2_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h39][27:21]; + s2_folded_gh_dup_1_hist_4_folded_hist = + {_RANDOM[8'h39][31:28], _RANDOM[8'h3A][3:0]}; + s2_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h3A][11:4]; + s2_folded_gh_dup_1_hist_2_folded_hist = _RANDOM[8'h3A][19:12]; + s2_folded_gh_dup_1_hist_1_folded_hist = _RANDOM[8'h3A][30:20]; + s2_folded_gh_dup_1_hist_0_folded_hist = {_RANDOM[8'h3A][31], _RANDOM[8'h3B][6:0]}; + s2_folded_gh_dup_2_hist_17_folded_hist = _RANDOM[8'h3B][17:7]; + s2_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h3B][28:18]; + s2_folded_gh_dup_2_hist_15_folded_hist = + {_RANDOM[8'h3B][31:29], _RANDOM[8'h3C][3:0]}; + s2_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h3C][11:4]; + s2_folded_gh_dup_2_hist_13_folded_hist = _RANDOM[8'h3C][20:12]; + s2_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h3C][24:21]; + s2_folded_gh_dup_2_hist_11_folded_hist = + {_RANDOM[8'h3C][31:25], _RANDOM[8'h3D][0]}; + s2_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h3D][9:1]; + s2_folded_gh_dup_2_hist_9_folded_hist = _RANDOM[8'h3D][16:10]; + s2_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h3D][24:17]; + s2_folded_gh_dup_2_hist_7_folded_hist = _RANDOM[8'h3D][31:25]; + s2_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h3E][8:0]; + s2_folded_gh_dup_2_hist_5_folded_hist = _RANDOM[8'h3E][15:9]; + s2_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h3E][23:16]; + s2_folded_gh_dup_2_hist_3_folded_hist = _RANDOM[8'h3E][31:24]; + s2_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h3F][7:0]; + s2_folded_gh_dup_2_hist_1_folded_hist = _RANDOM[8'h3F][18:8]; + s2_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h3F][26:19]; + s2_folded_gh_dup_3_hist_17_folded_hist = + {_RANDOM[8'h3F][31:27], _RANDOM[8'h40][5:0]}; + s2_folded_gh_dup_3_hist_16_folded_hist = _RANDOM[8'h40][16:6]; + s2_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h40][23:17]; + s2_folded_gh_dup_3_hist_14_folded_hist = _RANDOM[8'h40][31:24]; + s2_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h41][8:0]; + s2_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h41][12:9]; + s2_folded_gh_dup_3_hist_11_folded_hist = _RANDOM[8'h41][20:13]; + s2_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h41][29:21]; + s2_folded_gh_dup_3_hist_9_folded_hist = + {_RANDOM[8'h41][31:30], _RANDOM[8'h42][4:0]}; + s2_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h42][12:5]; + s2_folded_gh_dup_3_hist_7_folded_hist = _RANDOM[8'h42][19:13]; + s2_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h42][28:20]; + s2_folded_gh_dup_3_hist_5_folded_hist = + {_RANDOM[8'h42][31:29], _RANDOM[8'h43][3:0]}; + s2_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h43][11:4]; + s2_folded_gh_dup_3_hist_3_folded_hist = _RANDOM[8'h43][19:12]; + s2_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h43][27:20]; + s2_folded_gh_dup_3_hist_1_folded_hist = + {_RANDOM[8'h43][31:28], _RANDOM[8'h44][6:0]}; + s2_folded_gh_dup_3_hist_0_folded_hist = _RANDOM[8'h44][14:7]; + s3_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h49][13:3]; + s3_folded_gh_dup_1_hist_16_folded_hist = _RANDOM[8'h49][24:14]; + s3_folded_gh_dup_1_hist_15_folded_hist = _RANDOM[8'h49][31:25]; + s3_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h4A][7:0]; + s3_folded_gh_dup_1_hist_13_folded_hist = _RANDOM[8'h4A][16:8]; + s3_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h4A][20:17]; + s3_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h4A][28:21]; + s3_folded_gh_dup_1_hist_10_folded_hist = + {_RANDOM[8'h4A][31:29], _RANDOM[8'h4B][5:0]}; + s3_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h4B][12:6]; + s3_folded_gh_dup_1_hist_8_folded_hist = _RANDOM[8'h4B][20:13]; + s3_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h4B][27:21]; + s3_folded_gh_dup_1_hist_6_folded_hist = + {_RANDOM[8'h4B][31:28], _RANDOM[8'h4C][4:0]}; + s3_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h4C][11:5]; + s3_folded_gh_dup_1_hist_4_folded_hist = _RANDOM[8'h4C][19:12]; + s3_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h4C][27:20]; + s3_folded_gh_dup_1_hist_2_folded_hist = + {_RANDOM[8'h4C][31:28], _RANDOM[8'h4D][3:0]}; + s3_folded_gh_dup_1_hist_1_folded_hist = _RANDOM[8'h4D][14:4]; + s3_folded_gh_dup_1_hist_0_folded_hist = _RANDOM[8'h4D][22:15]; + s3_folded_gh_dup_2_hist_17_folded_hist = + {_RANDOM[8'h4D][31:23], _RANDOM[8'h4E][1:0]}; + s3_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h4E][12:2]; + s3_folded_gh_dup_2_hist_15_folded_hist = _RANDOM[8'h4E][19:13]; + s3_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h4E][27:20]; + s3_folded_gh_dup_2_hist_13_folded_hist = + {_RANDOM[8'h4E][31:28], _RANDOM[8'h4F][4:0]}; + s3_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h4F][8:5]; + s3_folded_gh_dup_2_hist_11_folded_hist = _RANDOM[8'h4F][16:9]; + s3_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h4F][25:17]; + s3_folded_gh_dup_2_hist_9_folded_hist = + {_RANDOM[8'h4F][31:26], _RANDOM[8'h50][0]}; + s3_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h50][8:1]; + s3_folded_gh_dup_2_hist_7_folded_hist = _RANDOM[8'h50][15:9]; + s3_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h50][24:16]; + s3_folded_gh_dup_2_hist_5_folded_hist = _RANDOM[8'h50][31:25]; + s3_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h51][7:0]; + s3_folded_gh_dup_2_hist_3_folded_hist = _RANDOM[8'h51][15:8]; + s3_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h51][23:16]; + s3_folded_gh_dup_2_hist_1_folded_hist = + {_RANDOM[8'h51][31:24], _RANDOM[8'h52][2:0]}; + s3_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h52][10:3]; + s3_folded_gh_dup_3_hist_17_folded_hist = _RANDOM[8'h52][21:11]; + s3_folded_gh_dup_3_hist_16_folded_hist = + {_RANDOM[8'h52][31:22], _RANDOM[8'h53][0]}; + s3_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h53][7:1]; + s3_folded_gh_dup_3_hist_14_folded_hist = _RANDOM[8'h53][15:8]; + s3_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h53][24:16]; + s3_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h53][28:25]; + s3_folded_gh_dup_3_hist_11_folded_hist = + {_RANDOM[8'h53][31:29], _RANDOM[8'h54][4:0]}; + s3_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h54][13:5]; + s3_folded_gh_dup_3_hist_9_folded_hist = _RANDOM[8'h54][20:14]; + s3_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h54][28:21]; + s3_folded_gh_dup_3_hist_7_folded_hist = + {_RANDOM[8'h54][31:29], _RANDOM[8'h55][3:0]}; + s3_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h55][12:4]; + s3_folded_gh_dup_3_hist_5_folded_hist = _RANDOM[8'h55][19:13]; + s3_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h55][27:20]; + s3_folded_gh_dup_3_hist_3_folded_hist = + {_RANDOM[8'h55][31:28], _RANDOM[8'h56][3:0]}; + s3_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h56][11:4]; + s3_folded_gh_dup_3_hist_1_folded_hist = _RANDOM[8'h56][22:12]; + s3_folded_gh_dup_3_hist_0_folded_hist = _RANDOM[8'h56][30:23]; + s0_last_br_num_oh_reg_dup_1 = _RANDOM[8'h57][4:2]; + s0_last_br_num_oh_reg_dup_2 = _RANDOM[8'h57][7:5]; + s0_last_br_num_oh_reg_dup_3 = _RANDOM[8'h57][10:8]; + s1_last_br_num_oh_dup_1 = _RANDOM[8'h57][16:14]; + s1_last_br_num_oh_dup_2 = _RANDOM[8'h57][19:17]; + s1_last_br_num_oh_dup_3 = _RANDOM[8'h57][22:20]; + s2_last_br_num_oh_dup_1 = _RANDOM[8'h57][28:26]; + s2_last_br_num_oh_dup_2 = _RANDOM[8'h57][31:29]; + s2_last_br_num_oh_dup_3 = _RANDOM[8'h58][2:0]; + s3_last_br_num_oh_dup_1 = _RANDOM[8'h58][8:6]; + s3_last_br_num_oh_dup_2 = _RANDOM[8'h58][11:9]; + s3_last_br_num_oh_dup_3 = _RANDOM[8'h58][14:12]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 = _RANDOM[8'h59][7]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 = _RANDOM[8'h59][8]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 = _RANDOM[8'h59][9]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 = _RANDOM[8'h59][10]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 = _RANDOM[8'h59][11]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 = _RANDOM[8'h59][12]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 = _RANDOM[8'h59][13]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 = _RANDOM[8'h59][14]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 = _RANDOM[8'h59][15]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 = _RANDOM[8'h59][16]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 = _RANDOM[8'h59][17]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 = _RANDOM[8'h59][18]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 = _RANDOM[8'h59][19]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 = _RANDOM[8'h59][20]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 = _RANDOM[8'h59][21]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 = _RANDOM[8'h59][22]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 = _RANDOM[8'h59][23]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 = _RANDOM[8'h59][24]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 = _RANDOM[8'h59][25]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 = _RANDOM[8'h59][26]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 = _RANDOM[8'h59][27]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 = _RANDOM[8'h59][28]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 = _RANDOM[8'h59][29]; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 = _RANDOM[8'h59][30]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 = _RANDOM[8'h59][31]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 = _RANDOM[8'h5A][0]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 = _RANDOM[8'h5A][1]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 = _RANDOM[8'h5A][2]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 = _RANDOM[8'h5A][3]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 = _RANDOM[8'h5A][4]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 = _RANDOM[8'h5A][5]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 = _RANDOM[8'h5A][6]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 = _RANDOM[8'h5A][7]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 = _RANDOM[8'h5A][8]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 = _RANDOM[8'h5A][9]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 = _RANDOM[8'h5A][10]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 = _RANDOM[8'h5A][11]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 = _RANDOM[8'h5A][12]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 = _RANDOM[8'h5A][13]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 = _RANDOM[8'h5A][14]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 = _RANDOM[8'h5A][15]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 = _RANDOM[8'h5A][16]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 = _RANDOM[8'h5A][17]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 = _RANDOM[8'h5A][18]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 = _RANDOM[8'h5A][19]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 = _RANDOM[8'h5A][20]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 = _RANDOM[8'h5A][21]; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 = _RANDOM[8'h5A][22]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 = _RANDOM[8'h5A][23]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 = _RANDOM[8'h5A][24]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 = _RANDOM[8'h5A][25]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 = _RANDOM[8'h5A][26]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 = _RANDOM[8'h5A][27]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 = _RANDOM[8'h5A][28]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 = _RANDOM[8'h5A][29]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 = _RANDOM[8'h5A][30]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 = _RANDOM[8'h5A][31]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 = _RANDOM[8'h5B][0]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 = _RANDOM[8'h5B][1]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 = _RANDOM[8'h5B][2]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 = _RANDOM[8'h5B][3]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 = _RANDOM[8'h5B][4]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 = _RANDOM[8'h5B][5]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 = _RANDOM[8'h5B][6]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 = _RANDOM[8'h5B][7]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 = _RANDOM[8'h5B][8]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 = _RANDOM[8'h5B][9]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 = _RANDOM[8'h5B][10]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 = _RANDOM[8'h5B][11]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 = _RANDOM[8'h5B][12]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 = _RANDOM[8'h5B][13]; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 = _RANDOM[8'h5B][14]; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h5C][7]; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h5C][8]; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h5C][9]; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h5C][10]; + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h5C][11]; + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h5C][12]; + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h5C][13]; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h5C][15]; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h5C][16]; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h5C][17]; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h5C][18]; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h5C][19]; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h5C][20]; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h5C][21]; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h5C][22]; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h5C][23]; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h5C][24]; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h5C][25]; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h5C][26]; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h5C][27]; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h5C][28]; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h5C][29]; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h5C][30]; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h5C][31]; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h5D][0]; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h5D][1]; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h5D][2]; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h5D][3]; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h5D][4]; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h5D][5]; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h5D][6]; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h5D][7]; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h5D][8]; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h5D][9]; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h5D][10]; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h5D][11]; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h5D][12]; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h5D][13]; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h5D][14]; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h5D][15]; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h5D][16]; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h5D][17]; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h5D][18]; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h5D][19]; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h5D][20]; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h5D][21]; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h5D][22]; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h5D][23]; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h5D][24]; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h5D][25]; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h5D][26]; + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h5D][27]; + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h5D][28]; + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h5D][29]; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h5D][31]; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h5E][0]; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h5E][1]; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h5E][2]; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h5E][3]; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h5E][4]; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h5E][5]; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h5E][6]; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h5E][7]; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h5E][8]; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h5E][9]; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h5E][10]; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h5E][11]; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h5E][12]; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h5E][13]; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h5E][14]; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h5F][7]; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h5F][8]; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h5F][9]; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h5F][10]; + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h5F][11]; + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h5F][12]; + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h5F][13]; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h5F][15]; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h5F][16]; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h5F][17]; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h5F][18]; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h5F][19]; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h5F][20]; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h5F][21]; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h5F][22]; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h5F][23]; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h5F][24]; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h5F][25]; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h5F][26]; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h5F][27]; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h5F][28]; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h5F][29]; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h5F][30]; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h5F][31]; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h60][0]; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h60][1]; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h60][2]; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h60][3]; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h60][4]; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h60][5]; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h60][6]; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h60][7]; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h60][8]; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h60][9]; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h60][10]; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h60][11]; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h60][12]; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h60][13]; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h60][14]; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h60][15]; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h60][16]; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h60][17]; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h60][18]; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h60][19]; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h60][20]; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h60][21]; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h60][22]; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h60][23]; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h60][24]; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h60][25]; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h60][26]; + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h60][27]; + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h60][28]; + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h60][29]; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h60][31]; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h61][0]; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h61][1]; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h61][2]; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h61][3]; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h61][4]; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h61][5]; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h61][6]; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h61][7]; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h61][8]; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h61][9]; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h61][10]; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h61][11]; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h61][12]; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h61][13]; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h61][14]; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h62][7]; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h62][8]; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h62][9]; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h62][10]; + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h62][11]; + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h62][12]; + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h62][13]; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h62][15]; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h62][16]; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h62][17]; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h62][18]; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h62][19]; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h62][20]; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h62][21]; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h62][22]; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h62][23]; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h62][24]; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h62][25]; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h62][26]; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h62][27]; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h62][28]; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h62][29]; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h62][30]; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h62][31]; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h63][0]; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h63][1]; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h63][2]; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h63][3]; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h63][4]; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h63][5]; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h63][6]; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h63][7]; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h63][8]; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h63][9]; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h63][10]; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h63][11]; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h63][12]; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h63][13]; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h63][14]; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h63][15]; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h63][16]; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h63][17]; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h63][18]; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h63][19]; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h63][20]; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h63][21]; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h63][22]; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h63][23]; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h63][24]; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h63][25]; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h63][26]; + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h63][27]; + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h63][28]; + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h63][29]; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h63][31]; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h64][0]; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h64][1]; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h64][2]; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h64][3]; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h64][4]; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h64][5]; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h64][6]; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h64][7]; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h64][8]; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h64][9]; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h64][10]; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h64][11]; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h64][12]; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h64][13]; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h64][14]; + ghv_0 = _RANDOM[8'h64][15]; + ghv_1 = _RANDOM[8'h64][16]; + ghv_2 = _RANDOM[8'h64][17]; + ghv_3 = _RANDOM[8'h64][18]; + ghv_4 = _RANDOM[8'h64][19]; + ghv_5 = _RANDOM[8'h64][20]; + ghv_6 = _RANDOM[8'h64][21]; + ghv_7 = _RANDOM[8'h64][22]; + ghv_8 = _RANDOM[8'h64][23]; + ghv_9 = _RANDOM[8'h64][24]; + ghv_10 = _RANDOM[8'h64][25]; + ghv_11 = _RANDOM[8'h64][26]; + ghv_12 = _RANDOM[8'h64][27]; + ghv_13 = _RANDOM[8'h64][28]; + ghv_14 = _RANDOM[8'h64][29]; + ghv_15 = _RANDOM[8'h64][30]; + ghv_16 = _RANDOM[8'h64][31]; + ghv_17 = _RANDOM[8'h65][0]; + ghv_18 = _RANDOM[8'h65][1]; + ghv_19 = _RANDOM[8'h65][2]; + ghv_20 = _RANDOM[8'h65][3]; + ghv_21 = _RANDOM[8'h65][4]; + ghv_22 = _RANDOM[8'h65][5]; + ghv_23 = _RANDOM[8'h65][6]; + ghv_24 = _RANDOM[8'h65][7]; + ghv_25 = _RANDOM[8'h65][8]; + ghv_26 = _RANDOM[8'h65][9]; + ghv_27 = _RANDOM[8'h65][10]; + ghv_28 = _RANDOM[8'h65][11]; + ghv_29 = _RANDOM[8'h65][12]; + ghv_30 = _RANDOM[8'h65][13]; + ghv_31 = _RANDOM[8'h65][14]; + ghv_32 = _RANDOM[8'h65][15]; + ghv_33 = _RANDOM[8'h65][16]; + ghv_34 = _RANDOM[8'h65][17]; + ghv_35 = _RANDOM[8'h65][18]; + ghv_36 = _RANDOM[8'h65][19]; + ghv_37 = _RANDOM[8'h65][20]; + ghv_38 = _RANDOM[8'h65][21]; + ghv_39 = _RANDOM[8'h65][22]; + ghv_40 = _RANDOM[8'h65][23]; + ghv_41 = _RANDOM[8'h65][24]; + ghv_42 = _RANDOM[8'h65][25]; + ghv_43 = _RANDOM[8'h65][26]; + ghv_44 = _RANDOM[8'h65][27]; + ghv_45 = _RANDOM[8'h65][28]; + ghv_46 = _RANDOM[8'h65][29]; + ghv_47 = _RANDOM[8'h65][30]; + ghv_48 = _RANDOM[8'h65][31]; + ghv_49 = _RANDOM[8'h66][0]; + ghv_50 = _RANDOM[8'h66][1]; + ghv_51 = _RANDOM[8'h66][2]; + ghv_52 = _RANDOM[8'h66][3]; + ghv_53 = _RANDOM[8'h66][4]; + ghv_54 = _RANDOM[8'h66][5]; + ghv_55 = _RANDOM[8'h66][6]; + ghv_56 = _RANDOM[8'h66][7]; + ghv_57 = _RANDOM[8'h66][8]; + ghv_58 = _RANDOM[8'h66][9]; + ghv_59 = _RANDOM[8'h66][10]; + ghv_60 = _RANDOM[8'h66][11]; + ghv_61 = _RANDOM[8'h66][12]; + ghv_62 = _RANDOM[8'h66][13]; + ghv_63 = _RANDOM[8'h66][14]; + ghv_64 = _RANDOM[8'h66][15]; + ghv_65 = _RANDOM[8'h66][16]; + ghv_66 = _RANDOM[8'h66][17]; + ghv_67 = _RANDOM[8'h66][18]; + ghv_68 = _RANDOM[8'h66][19]; + ghv_69 = _RANDOM[8'h66][20]; + ghv_70 = _RANDOM[8'h66][21]; + ghv_71 = _RANDOM[8'h66][22]; + ghv_72 = _RANDOM[8'h66][23]; + ghv_73 = _RANDOM[8'h66][24]; + ghv_74 = _RANDOM[8'h66][25]; + ghv_75 = _RANDOM[8'h66][26]; + ghv_76 = _RANDOM[8'h66][27]; + ghv_77 = _RANDOM[8'h66][28]; + ghv_78 = _RANDOM[8'h66][29]; + ghv_79 = _RANDOM[8'h66][30]; + ghv_80 = _RANDOM[8'h66][31]; + ghv_81 = _RANDOM[8'h67][0]; + ghv_82 = _RANDOM[8'h67][1]; + ghv_83 = _RANDOM[8'h67][2]; + ghv_84 = _RANDOM[8'h67][3]; + ghv_85 = _RANDOM[8'h67][4]; + ghv_86 = _RANDOM[8'h67][5]; + ghv_87 = _RANDOM[8'h67][6]; + ghv_88 = _RANDOM[8'h67][7]; + ghv_89 = _RANDOM[8'h67][8]; + ghv_90 = _RANDOM[8'h67][9]; + ghv_91 = _RANDOM[8'h67][10]; + ghv_92 = _RANDOM[8'h67][11]; + ghv_93 = _RANDOM[8'h67][12]; + ghv_94 = _RANDOM[8'h67][13]; + ghv_95 = _RANDOM[8'h67][14]; + ghv_96 = _RANDOM[8'h67][15]; + ghv_97 = _RANDOM[8'h67][16]; + ghv_98 = _RANDOM[8'h67][17]; + ghv_99 = _RANDOM[8'h67][18]; + ghv_100 = _RANDOM[8'h67][19]; + ghv_101 = _RANDOM[8'h67][20]; + ghv_102 = _RANDOM[8'h67][21]; + ghv_103 = _RANDOM[8'h67][22]; + ghv_104 = _RANDOM[8'h67][23]; + ghv_105 = _RANDOM[8'h67][24]; + ghv_106 = _RANDOM[8'h67][25]; + ghv_107 = _RANDOM[8'h67][26]; + ghv_108 = _RANDOM[8'h67][27]; + ghv_109 = _RANDOM[8'h67][28]; + ghv_110 = _RANDOM[8'h67][29]; + ghv_111 = _RANDOM[8'h67][30]; + ghv_112 = _RANDOM[8'h67][31]; + ghv_113 = _RANDOM[8'h68][0]; + ghv_114 = _RANDOM[8'h68][1]; + ghv_115 = _RANDOM[8'h68][2]; + ghv_116 = _RANDOM[8'h68][3]; + ghv_117 = _RANDOM[8'h68][4]; + ghv_118 = _RANDOM[8'h68][5]; + ghv_119 = _RANDOM[8'h68][6]; + ghv_120 = _RANDOM[8'h68][7]; + ghv_121 = _RANDOM[8'h68][8]; + ghv_122 = _RANDOM[8'h68][9]; + ghv_123 = _RANDOM[8'h68][10]; + ghv_124 = _RANDOM[8'h68][11]; + ghv_125 = _RANDOM[8'h68][12]; + ghv_126 = _RANDOM[8'h68][13]; + ghv_127 = _RANDOM[8'h68][14]; + ghv_128 = _RANDOM[8'h68][15]; + ghv_129 = _RANDOM[8'h68][16]; + ghv_130 = _RANDOM[8'h68][17]; + ghv_131 = _RANDOM[8'h68][18]; + ghv_132 = _RANDOM[8'h68][19]; + ghv_133 = _RANDOM[8'h68][20]; + ghv_134 = _RANDOM[8'h68][21]; + ghv_135 = _RANDOM[8'h68][22]; + ghv_136 = _RANDOM[8'h68][23]; + ghv_137 = _RANDOM[8'h68][24]; + ghv_138 = _RANDOM[8'h68][25]; + ghv_139 = _RANDOM[8'h68][26]; + ghv_140 = _RANDOM[8'h68][27]; + ghv_141 = _RANDOM[8'h68][28]; + ghv_142 = _RANDOM[8'h68][29]; + ghv_143 = _RANDOM[8'h68][30]; + ghv_144 = _RANDOM[8'h68][31]; + ghv_145 = _RANDOM[8'h69][0]; + ghv_146 = _RANDOM[8'h69][1]; + ghv_147 = _RANDOM[8'h69][2]; + ghv_148 = _RANDOM[8'h69][3]; + ghv_149 = _RANDOM[8'h69][4]; + ghv_150 = _RANDOM[8'h69][5]; + ghv_151 = _RANDOM[8'h69][6]; + ghv_152 = _RANDOM[8'h69][7]; + ghv_153 = _RANDOM[8'h69][8]; + ghv_154 = _RANDOM[8'h69][9]; + ghv_155 = _RANDOM[8'h69][10]; + ghv_156 = _RANDOM[8'h69][11]; + ghv_157 = _RANDOM[8'h69][12]; + ghv_158 = _RANDOM[8'h69][13]; + ghv_159 = _RANDOM[8'h69][14]; + ghv_160 = _RANDOM[8'h69][15]; + ghv_161 = _RANDOM[8'h69][16]; + ghv_162 = _RANDOM[8'h69][17]; + ghv_163 = _RANDOM[8'h69][18]; + ghv_164 = _RANDOM[8'h69][19]; + ghv_165 = _RANDOM[8'h69][20]; + ghv_166 = _RANDOM[8'h69][21]; + ghv_167 = _RANDOM[8'h69][22]; + ghv_168 = _RANDOM[8'h69][23]; + ghv_169 = _RANDOM[8'h69][24]; + ghv_170 = _RANDOM[8'h69][25]; + ghv_171 = _RANDOM[8'h69][26]; + ghv_172 = _RANDOM[8'h69][27]; + ghv_173 = _RANDOM[8'h69][28]; + ghv_174 = _RANDOM[8'h69][29]; + ghv_175 = _RANDOM[8'h69][30]; + ghv_176 = _RANDOM[8'h69][31]; + ghv_177 = _RANDOM[8'h6A][0]; + ghv_178 = _RANDOM[8'h6A][1]; + ghv_179 = _RANDOM[8'h6A][2]; + ghv_180 = _RANDOM[8'h6A][3]; + ghv_181 = _RANDOM[8'h6A][4]; + ghv_182 = _RANDOM[8'h6A][5]; + ghv_183 = _RANDOM[8'h6A][6]; + ghv_184 = _RANDOM[8'h6A][7]; + ghv_185 = _RANDOM[8'h6A][8]; + ghv_186 = _RANDOM[8'h6A][9]; + ghv_187 = _RANDOM[8'h6A][10]; + ghv_188 = _RANDOM[8'h6A][11]; + ghv_189 = _RANDOM[8'h6A][12]; + ghv_190 = _RANDOM[8'h6A][13]; + ghv_191 = _RANDOM[8'h6A][14]; + ghv_192 = _RANDOM[8'h6A][15]; + ghv_193 = _RANDOM[8'h6A][16]; + ghv_194 = _RANDOM[8'h6A][17]; + ghv_195 = _RANDOM[8'h6A][18]; + ghv_196 = _RANDOM[8'h6A][19]; + ghv_197 = _RANDOM[8'h6A][20]; + ghv_198 = _RANDOM[8'h6A][21]; + ghv_199 = _RANDOM[8'h6A][22]; + ghv_200 = _RANDOM[8'h6A][23]; + ghv_201 = _RANDOM[8'h6A][24]; + ghv_202 = _RANDOM[8'h6A][25]; + ghv_203 = _RANDOM[8'h6A][26]; + ghv_204 = _RANDOM[8'h6A][27]; + ghv_205 = _RANDOM[8'h6A][28]; + ghv_206 = _RANDOM[8'h6A][29]; + ghv_207 = _RANDOM[8'h6A][30]; + ghv_208 = _RANDOM[8'h6A][31]; + ghv_209 = _RANDOM[8'h6B][0]; + ghv_210 = _RANDOM[8'h6B][1]; + ghv_211 = _RANDOM[8'h6B][2]; + ghv_212 = _RANDOM[8'h6B][3]; + ghv_213 = _RANDOM[8'h6B][4]; + ghv_214 = _RANDOM[8'h6B][5]; + ghv_215 = _RANDOM[8'h6B][6]; + ghv_216 = _RANDOM[8'h6B][7]; + ghv_217 = _RANDOM[8'h6B][8]; + ghv_218 = _RANDOM[8'h6B][9]; + ghv_219 = _RANDOM[8'h6B][10]; + ghv_220 = _RANDOM[8'h6B][11]; + ghv_221 = _RANDOM[8'h6B][12]; + ghv_222 = _RANDOM[8'h6B][13]; + ghv_223 = _RANDOM[8'h6B][14]; + ghv_224 = _RANDOM[8'h6B][15]; + ghv_225 = _RANDOM[8'h6B][16]; + ghv_226 = _RANDOM[8'h6B][17]; + ghv_227 = _RANDOM[8'h6B][18]; + ghv_228 = _RANDOM[8'h6B][19]; + ghv_229 = _RANDOM[8'h6B][20]; + ghv_230 = _RANDOM[8'h6B][21]; + ghv_231 = _RANDOM[8'h6B][22]; + ghv_232 = _RANDOM[8'h6B][23]; + ghv_233 = _RANDOM[8'h6B][24]; + ghv_234 = _RANDOM[8'h6B][25]; + ghv_235 = _RANDOM[8'h6B][26]; + ghv_236 = _RANDOM[8'h6B][27]; + ghv_237 = _RANDOM[8'h6B][28]; + ghv_238 = _RANDOM[8'h6B][29]; + ghv_239 = _RANDOM[8'h6B][30]; + ghv_240 = _RANDOM[8'h6B][31]; + ghv_241 = _RANDOM[8'h6C][0]; + ghv_242 = _RANDOM[8'h6C][1]; + ghv_243 = _RANDOM[8'h6C][2]; + ghv_244 = _RANDOM[8'h6C][3]; + ghv_245 = _RANDOM[8'h6C][4]; + ghv_246 = _RANDOM[8'h6C][5]; + ghv_247 = _RANDOM[8'h6C][6]; + ghv_248 = _RANDOM[8'h6C][7]; + ghv_249 = _RANDOM[8'h6C][8]; + ghv_250 = _RANDOM[8'h6C][9]; + ghv_251 = _RANDOM[8'h6C][10]; + ghv_252 = _RANDOM[8'h6C][11]; + ghv_253 = _RANDOM[8'h6C][12]; + ghv_254 = _RANDOM[8'h6C][13]; + ghv_255 = _RANDOM[8'h6C][14]; + s0_ghist_ptr_reg_dup_0_flag = _RANDOM[8'h6C][15]; + s0_ghist_ptr_reg_dup_0_value = _RANDOM[8'h6C][23:16]; + s0_ghist_ptr_reg_dup_1_flag = _RANDOM[8'h6C][24]; + s0_ghist_ptr_reg_dup_1_value = {_RANDOM[8'h6C][31:25], _RANDOM[8'h6D][0]}; + s0_ghist_ptr_reg_dup_2_flag = _RANDOM[8'h6D][1]; + s0_ghist_ptr_reg_dup_2_value = _RANDOM[8'h6D][9:2]; + s0_ghist_ptr_reg_dup_3_flag = _RANDOM[8'h6D][10]; + s0_ghist_ptr_reg_dup_3_value = _RANDOM[8'h6D][18:11]; + s1_ghist_ptr_dup_0_flag = _RANDOM[8'h6D][19]; + s1_ghist_ptr_dup_0_value = _RANDOM[8'h6D][27:20]; + s1_ghist_ptr_dup_1_flag = _RANDOM[8'h6D][28]; + s1_ghist_ptr_dup_1_value = {_RANDOM[8'h6D][31:29], _RANDOM[8'h6E][4:0]}; + s1_ghist_ptr_dup_2_flag = _RANDOM[8'h6E][5]; + s1_ghist_ptr_dup_2_value = _RANDOM[8'h6E][13:6]; + s1_ghist_ptr_dup_3_flag = _RANDOM[8'h6E][14]; + s1_ghist_ptr_dup_3_value = _RANDOM[8'h6E][22:15]; + s2_ghist_ptr_dup_0_flag = _RANDOM[8'h6E][23]; + s2_ghist_ptr_dup_0_value = _RANDOM[8'h6E][31:24]; + s2_ghist_ptr_dup_1_flag = _RANDOM[8'h6F][0]; + s2_ghist_ptr_dup_1_value = _RANDOM[8'h6F][8:1]; + s2_ghist_ptr_dup_2_flag = _RANDOM[8'h6F][9]; + s2_ghist_ptr_dup_2_value = _RANDOM[8'h6F][17:10]; + s2_ghist_ptr_dup_3_flag = _RANDOM[8'h6F][18]; + s2_ghist_ptr_dup_3_value = _RANDOM[8'h6F][26:19]; + s3_ghist_ptr_dup_0_flag = _RANDOM[8'h6F][27]; + s3_ghist_ptr_dup_0_value = {_RANDOM[8'h6F][31:28], _RANDOM[8'h70][3:0]}; + s3_ghist_ptr_dup_1_flag = _RANDOM[8'h70][4]; + s3_ghist_ptr_dup_1_value = _RANDOM[8'h70][12:5]; + s3_ghist_ptr_dup_2_flag = _RANDOM[8'h70][13]; + s3_ghist_ptr_dup_2_value = _RANDOM[8'h70][21:14]; + s3_ghist_ptr_dup_3_flag = _RANDOM[8'h70][22]; + s3_ghist_ptr_dup_3_value = _RANDOM[8'h70][30:23]; + do_redirect_dup_next_valid_last_r = _RANDOM[8'h70][31]; + do_redirect_dup_next_bits_r_level = _RANDOM[8'h71][21]; + do_redirect_dup_next_bits_r_cfiUpdate_pc = + {_RANDOM[8'h71][31:23], _RANDOM[8'h72]}; + do_redirect_dup_next_bits_r_cfiUpdate_pd_isRVC = _RANDOM[8'h73][1]; + do_redirect_dup_next_bits_r_cfiUpdate_pd_isCall = _RANDOM[8'h73][4]; + do_redirect_dup_next_bits_r_cfiUpdate_pd_isRet = _RANDOM[8'h73][5]; + do_redirect_dup_next_bits_r_cfiUpdate_ssp = _RANDOM[8'h73][9:6]; + do_redirect_dup_next_bits_r_cfiUpdate_sctr = _RANDOM[8'h73][11:10]; + do_redirect_dup_next_bits_r_cfiUpdate_TOSW_flag = _RANDOM[8'h73][12]; + do_redirect_dup_next_bits_r_cfiUpdate_TOSW_value = _RANDOM[8'h73][17:13]; + do_redirect_dup_next_bits_r_cfiUpdate_TOSR_flag = _RANDOM[8'h73][18]; + do_redirect_dup_next_bits_r_cfiUpdate_TOSR_value = _RANDOM[8'h73][23:19]; + do_redirect_dup_next_bits_r_cfiUpdate_NOS_flag = _RANDOM[8'h73][24]; + do_redirect_dup_next_bits_r_cfiUpdate_NOS_value = _RANDOM[8'h73][29:25]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_17_folded_hist = + _RANDOM[8'h75][17:7]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_16_folded_hist = + _RANDOM[8'h75][28:18]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_15_folded_hist = + {_RANDOM[8'h75][31:29], _RANDOM[8'h76][3:0]}; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_14_folded_hist = + _RANDOM[8'h76][11:4]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_13_folded_hist = + _RANDOM[8'h76][20:12]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_12_folded_hist = + _RANDOM[8'h76][24:21]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_11_folded_hist = + {_RANDOM[8'h76][31:25], _RANDOM[8'h77][0]}; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_10_folded_hist = + _RANDOM[8'h77][9:1]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_9_folded_hist = + _RANDOM[8'h77][16:10]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_8_folded_hist = + _RANDOM[8'h77][24:17]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_7_folded_hist = + _RANDOM[8'h77][31:25]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_6_folded_hist = + _RANDOM[8'h78][8:0]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_5_folded_hist = + _RANDOM[8'h78][15:9]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_4_folded_hist = + _RANDOM[8'h78][23:16]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_3_folded_hist = + _RANDOM[8'h78][31:24]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_2_folded_hist = + _RANDOM[8'h79][7:0]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_1_folded_hist = + _RANDOM[8'h79][18:8]; + do_redirect_dup_next_bits_r_cfiUpdate_folded_hist_hist_0_folded_hist = + _RANDOM[8'h79][26:19]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_0 = _RANDOM[8'h79][27]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_1 = _RANDOM[8'h79][28]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_2 = _RANDOM[8'h79][29]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_5_bits_3 = _RANDOM[8'h79][30]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_0 = _RANDOM[8'h79][31]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_1 = _RANDOM[8'h7A][0]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_4_bits_2 = _RANDOM[8'h7A][1]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_0 = _RANDOM[8'h7A][3]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_1 = _RANDOM[8'h7A][4]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_2 = _RANDOM[8'h7A][5]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_3_bits_3 = _RANDOM[8'h7A][6]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_0 = _RANDOM[8'h7A][7]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_1 = _RANDOM[8'h7A][8]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_2 = _RANDOM[8'h7A][9]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_2_bits_3 = _RANDOM[8'h7A][10]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_0 = _RANDOM[8'h7A][11]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_1 = _RANDOM[8'h7A][12]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_2 = _RANDOM[8'h7A][13]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_1_bits_3 = _RANDOM[8'h7A][14]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_0 = _RANDOM[8'h7A][15]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_1 = _RANDOM[8'h7A][16]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_2 = _RANDOM[8'h7A][17]; + do_redirect_dup_next_bits_r_cfiUpdate_afhob_afhob_0_bits_3 = _RANDOM[8'h7A][18]; + do_redirect_dup_next_bits_r_cfiUpdate_lastBrNumOH = _RANDOM[8'h7A][21:19]; + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_flag = _RANDOM[8'h7A][26]; + do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value = + {_RANDOM[8'h7A][31:27], _RANDOM[8'h7B][2:0]}; + do_redirect_dup_next_bits_r_cfiUpdate_target = + {_RANDOM[8'h7B][31:27], _RANDOM[8'h7C], _RANDOM[8'h7D][3:0]}; + do_redirect_dup_next_bits_r_cfiUpdate_taken = _RANDOM[8'h7D][4]; + do_redirect_dup_next_bits_r_cfiUpdate_shift = _RANDOM[8'h7D][7:6]; + do_redirect_dup_next_bits_r_cfiUpdate_addIntoHist = _RANDOM[8'h7D][8]; + previous_s1_pred_info_hit_0 = _RANDOM[8'h7F][23]; + previous_s1_pred_info_hit_1 = _RANDOM[8'h7F][24]; + previous_s1_pred_info_hit_2 = _RANDOM[8'h7F][25]; + previous_s1_pred_info_hit_3 = _RANDOM[8'h7F][26]; + previous_s1_pred_info_target_0 = + {_RANDOM[8'h7F][31:27], _RANDOM[8'h80], _RANDOM[8'h81][3:0]}; + previous_s1_pred_info_target_1 = {_RANDOM[8'h81][31:4], _RANDOM[8'h82][12:0]}; + previous_s1_pred_info_target_2 = {_RANDOM[8'h82][31:13], _RANDOM[8'h83][21:0]}; + previous_s1_pred_info_target_3 = {_RANDOM[8'h83][31:22], _RANDOM[8'h84][30:0]}; + previous_s1_pred_info_lastBrPosOH_0_0 = _RANDOM[8'h84][31]; + previous_s1_pred_info_lastBrPosOH_0_1 = _RANDOM[8'h85][0]; + previous_s1_pred_info_lastBrPosOH_0_2 = _RANDOM[8'h85][1]; + previous_s1_pred_info_lastBrPosOH_1_0 = _RANDOM[8'h85][2]; + previous_s1_pred_info_lastBrPosOH_1_1 = _RANDOM[8'h85][3]; + previous_s1_pred_info_lastBrPosOH_1_2 = _RANDOM[8'h85][4]; + previous_s1_pred_info_lastBrPosOH_2_0 = _RANDOM[8'h85][5]; + previous_s1_pred_info_lastBrPosOH_2_1 = _RANDOM[8'h85][6]; + previous_s1_pred_info_lastBrPosOH_2_2 = _RANDOM[8'h85][7]; + previous_s1_pred_info_lastBrPosOH_3_0 = _RANDOM[8'h85][8]; + previous_s1_pred_info_lastBrPosOH_3_1 = _RANDOM[8'h85][9]; + previous_s1_pred_info_lastBrPosOH_3_2 = _RANDOM[8'h85][10]; + previous_s1_pred_info_taken_0 = _RANDOM[8'h85][11]; + previous_s1_pred_info_taken_1 = _RANDOM[8'h85][12]; + previous_s1_pred_info_taken_2 = _RANDOM[8'h85][13]; + previous_s1_pred_info_taken_3 = _RANDOM[8'h85][14]; + previous_s1_pred_info_takenMask_0_0 = _RANDOM[8'h85][15]; + previous_s1_pred_info_takenMask_0_1 = _RANDOM[8'h85][16]; + previous_s1_pred_info_takenMask_1_0 = _RANDOM[8'h85][17]; + previous_s1_pred_info_takenMask_1_1 = _RANDOM[8'h85][18]; + previous_s1_pred_info_takenMask_2_0 = _RANDOM[8'h85][19]; + previous_s1_pred_info_takenMask_2_1 = _RANDOM[8'h85][20]; + previous_s1_pred_info_takenMask_3_0 = _RANDOM[8'h85][21]; + previous_s1_pred_info_takenMask_3_1 = _RANDOM[8'h85][22]; + previous_s1_pred_info_cfiIndex_0 = _RANDOM[8'h85][26:23]; + previous_s1_pred_info_cfiIndex_1 = _RANDOM[8'h85][30:27]; + previous_s1_pred_info_cfiIndex_2 = {_RANDOM[8'h85][31], _RANDOM[8'h86][2:0]}; + previous_s1_pred_info_cfiIndex_3 = _RANDOM[8'h86][6:3]; + previous_s2_pred_pc_0 = {_RANDOM[8'h86][31:7], _RANDOM[8'h87][15:0]}; + previous_s2_pred_pc_1 = {_RANDOM[8'h87][31:16], _RANDOM[8'h88][24:0]}; + previous_s2_pred_pc_2 = + {_RANDOM[8'h88][31:25], _RANDOM[8'h89], _RANDOM[8'h8A][1:0]}; + previous_s2_pred_pc_3 = {_RANDOM[8'h8A][31:2], _RANDOM[8'h8B][10:0]}; + previous_s2_pred_full_pred_0_br_taken_mask_0 = _RANDOM[8'h8B][26]; + previous_s2_pred_full_pred_0_br_taken_mask_1 = _RANDOM[8'h8B][27]; + previous_s2_pred_full_pred_0_slot_valids_0 = _RANDOM[8'h8B][28]; + previous_s2_pred_full_pred_0_slot_valids_1 = _RANDOM[8'h8B][29]; + previous_s2_pred_full_pred_0_targets_0 = + {_RANDOM[8'h8B][31:30], _RANDOM[8'h8C], _RANDOM[8'h8D][6:0]}; + previous_s2_pred_full_pred_0_targets_1 = + {_RANDOM[8'h8D][31:7], _RANDOM[8'h8E][15:0]}; + previous_s2_pred_full_pred_0_fallThroughAddr = + {_RANDOM[8'h90][31:1], _RANDOM[8'h91][9:0]}; + previous_s2_pred_full_pred_0_is_br_sharing = _RANDOM[8'h91][16]; + previous_s2_pred_full_pred_0_hit = _RANDOM[8'h91][17]; + previous_s2_pred_full_pred_1_br_taken_mask_0 = _RANDOM[8'h91][18]; + previous_s2_pred_full_pred_1_br_taken_mask_1 = _RANDOM[8'h91][19]; + previous_s2_pred_full_pred_1_slot_valids_0 = _RANDOM[8'h91][20]; + previous_s2_pred_full_pred_1_slot_valids_1 = _RANDOM[8'h91][21]; + previous_s2_pred_full_pred_1_targets_0 = + {_RANDOM[8'h91][31:22], _RANDOM[8'h92][30:0]}; + previous_s2_pred_full_pred_1_targets_1 = + {_RANDOM[8'h92][31], _RANDOM[8'h93], _RANDOM[8'h94][7:0]}; + previous_s2_pred_full_pred_1_fallThroughAddr = + {_RANDOM[8'h95][31:25], _RANDOM[8'h96], _RANDOM[8'h97][1:0]}; + previous_s2_pred_full_pred_1_is_br_sharing = _RANDOM[8'h97][8]; + previous_s2_pred_full_pred_1_hit = _RANDOM[8'h97][9]; + previous_s2_pred_full_pred_2_br_taken_mask_0 = _RANDOM[8'h97][10]; + previous_s2_pred_full_pred_2_br_taken_mask_1 = _RANDOM[8'h97][11]; + previous_s2_pred_full_pred_2_slot_valids_0 = _RANDOM[8'h97][12]; + previous_s2_pred_full_pred_2_slot_valids_1 = _RANDOM[8'h97][13]; + previous_s2_pred_full_pred_2_targets_0 = + {_RANDOM[8'h97][31:14], _RANDOM[8'h98][22:0]}; + previous_s2_pred_full_pred_2_targets_1 = {_RANDOM[8'h98][31:23], _RANDOM[8'h99]}; + previous_s2_pred_full_pred_2_fallThroughAddr = + {_RANDOM[8'h9B][31:17], _RANDOM[8'h9C][25:0]}; + previous_s2_pred_full_pred_2_is_br_sharing = _RANDOM[8'h9D][0]; + previous_s2_pred_full_pred_2_hit = _RANDOM[8'h9D][1]; + previous_s2_pred_full_pred_3_br_taken_mask_0 = _RANDOM[8'h9D][2]; + previous_s2_pred_full_pred_3_br_taken_mask_1 = _RANDOM[8'h9D][3]; + previous_s2_pred_full_pred_3_slot_valids_0 = _RANDOM[8'h9D][4]; + previous_s2_pred_full_pred_3_slot_valids_1 = _RANDOM[8'h9D][5]; + previous_s2_pred_full_pred_3_targets_0 = + {_RANDOM[8'h9D][31:6], _RANDOM[8'h9E][14:0]}; + previous_s2_pred_full_pred_3_targets_1 = + {_RANDOM[8'h9E][31:15], _RANDOM[8'h9F][23:0]}; + previous_s2_pred_full_pred_3_fallThroughAddr = + {_RANDOM[8'hA1][31:9], _RANDOM[8'hA2][17:0]}; + previous_s2_pred_full_pred_3_is_br_sharing = _RANDOM[8'hA2][24]; + previous_s2_pred_full_pred_3_hit = _RANDOM[8'hA2][25]; + s2_ftq_idx_flag = _RANDOM[8'hA2][26]; + s2_ftq_idx_value = {_RANDOM[8'hA2][31:27], _RANDOM[8'hA3][0]}; + s3_ftq_idx_flag = _RANDOM[8'hA3][1]; + s3_ftq_idx_value = _RANDOM[8'hA3][7:2]; + predictors_io_update_valid_REG = _RANDOM[8'hA3][8]; + predictors_io_update_bits_r_pc = {_RANDOM[8'hA3][31:9], _RANDOM[8'hA4][17:0]}; + predictors_io_update_bits_r_spec_info_folded_hist_hist_17_folded_hist = + _RANDOM[8'hA4][28:18]; + predictors_io_update_bits_r_spec_info_folded_hist_hist_16_folded_hist = + {_RANDOM[8'hA4][31:29], _RANDOM[8'hA5][7:0]}; + predictors_io_update_bits_r_spec_info_folded_hist_hist_15_folded_hist = + _RANDOM[8'hA5][14:8]; + predictors_io_update_bits_r_spec_info_folded_hist_hist_14_folded_hist = + _RANDOM[8'hA5][22:15]; + predictors_io_update_bits_r_spec_info_folded_hist_hist_13_folded_hist = + _RANDOM[8'hA5][31:23]; + predictors_io_update_bits_r_spec_info_folded_hist_hist_12_folded_hist = + _RANDOM[8'hA6][3:0]; + predictors_io_update_bits_r_spec_info_folded_hist_hist_11_folded_hist = + _RANDOM[8'hA6][11:4]; + predictors_io_update_bits_r_spec_info_folded_hist_hist_10_folded_hist = + _RANDOM[8'hA6][20:12]; + predictors_io_update_bits_r_spec_info_folded_hist_hist_9_folded_hist = + _RANDOM[8'hA6][27:21]; + predictors_io_update_bits_r_spec_info_folded_hist_hist_8_folded_hist = + {_RANDOM[8'hA6][31:28], _RANDOM[8'hA7][3:0]}; + predictors_io_update_bits_r_spec_info_folded_hist_hist_7_folded_hist = + _RANDOM[8'hA7][10:4]; + predictors_io_update_bits_r_spec_info_folded_hist_hist_6_folded_hist = + _RANDOM[8'hA7][19:11]; + predictors_io_update_bits_r_spec_info_folded_hist_hist_5_folded_hist = + _RANDOM[8'hA7][26:20]; + predictors_io_update_bits_r_spec_info_folded_hist_hist_4_folded_hist = + {_RANDOM[8'hA7][31:27], _RANDOM[8'hA8][2:0]}; + predictors_io_update_bits_r_spec_info_folded_hist_hist_3_folded_hist = + _RANDOM[8'hA8][10:3]; + predictors_io_update_bits_r_spec_info_folded_hist_hist_2_folded_hist = + _RANDOM[8'hA8][18:11]; + predictors_io_update_bits_r_spec_info_folded_hist_hist_1_folded_hist = + _RANDOM[8'hA8][29:19]; + predictors_io_update_bits_r_ftb_entry_valid = _RANDOM[8'hAC][11]; + predictors_io_update_bits_r_ftb_entry_brSlots_0_offset = _RANDOM[8'hAC][15:12]; + predictors_io_update_bits_r_ftb_entry_brSlots_0_lower = _RANDOM[8'hAC][27:16]; + predictors_io_update_bits_r_ftb_entry_brSlots_0_tarStat = _RANDOM[8'hAC][29:28]; + predictors_io_update_bits_r_ftb_entry_brSlots_0_sharing = _RANDOM[8'hAC][30]; + predictors_io_update_bits_r_ftb_entry_brSlots_0_valid = _RANDOM[8'hAC][31]; + predictors_io_update_bits_r_ftb_entry_tailSlot_offset = _RANDOM[8'hAD][3:0]; + predictors_io_update_bits_r_ftb_entry_tailSlot_lower = _RANDOM[8'hAD][23:4]; + predictors_io_update_bits_r_ftb_entry_tailSlot_tarStat = _RANDOM[8'hAD][25:24]; + predictors_io_update_bits_r_ftb_entry_tailSlot_sharing = _RANDOM[8'hAD][26]; + predictors_io_update_bits_r_ftb_entry_tailSlot_valid = _RANDOM[8'hAD][27]; + predictors_io_update_bits_r_ftb_entry_pftAddr = _RANDOM[8'hAD][31:28]; + predictors_io_update_bits_r_ftb_entry_carry = _RANDOM[8'hAE][0]; + predictors_io_update_bits_r_ftb_entry_isCall = _RANDOM[8'hAE][1]; + predictors_io_update_bits_r_ftb_entry_isRet = _RANDOM[8'hAE][2]; + predictors_io_update_bits_r_ftb_entry_isJalr = _RANDOM[8'hAE][3]; + predictors_io_update_bits_r_ftb_entry_last_may_be_rvi_call = _RANDOM[8'hAE][4]; + predictors_io_update_bits_r_ftb_entry_always_taken_0 = _RANDOM[8'hAE][5]; + predictors_io_update_bits_r_ftb_entry_always_taken_1 = _RANDOM[8'hAE][6]; + predictors_io_update_bits_r_cfi_idx_valid = _RANDOM[8'hAE][7]; + predictors_io_update_bits_r_cfi_idx_bits = _RANDOM[8'hAE][11:8]; + predictors_io_update_bits_r_br_taken_mask_0 = _RANDOM[8'hAE][12]; + predictors_io_update_bits_r_br_taken_mask_1 = _RANDOM[8'hAE][13]; + predictors_io_update_bits_r_jmp_taken = _RANDOM[8'hAE][16]; + predictors_io_update_bits_r_mispred_mask_0 = _RANDOM[8'hAE][17]; + predictors_io_update_bits_r_mispred_mask_1 = _RANDOM[8'hAE][18]; + predictors_io_update_bits_r_mispred_mask_2 = _RANDOM[8'hAE][19]; + predictors_io_update_bits_r_old_entry = _RANDOM[8'hAE][24]; + predictors_io_update_bits_r_meta = + {_RANDOM[8'hAE][31:25], + _RANDOM[8'hAF], + _RANDOM[8'hB0], + _RANDOM[8'hB1], + _RANDOM[8'hB2], + _RANDOM[8'hB3], + _RANDOM[8'hB4], + _RANDOM[8'hB5][23:0]}; + predictors_io_update_bits_r_full_target = + {_RANDOM[8'hB5][31:24], _RANDOM[8'hB6], _RANDOM[8'hB7][0]}; + io_perf_0_value_REG = _RANDOM[8'hCF][18:13]; + io_perf_0_value_REG_1 = _RANDOM[8'hCF][24:19]; + io_perf_1_value_REG = _RANDOM[8'hCF][30:25]; + io_perf_1_value_REG_1 = {_RANDOM[8'hCF][31], _RANDOM[8'hD0][4:0]}; + io_perf_2_value_REG = _RANDOM[8'hD0][10:5]; + io_perf_2_value_REG_1 = _RANDOM[8'hD0][16:11]; + io_perf_3_value_REG = _RANDOM[8'hD0][22:17]; + io_perf_3_value_REG_1 = _RANDOM[8'hD0][28:23]; + io_perf_4_value_REG = {_RANDOM[8'hD0][31:29], _RANDOM[8'hD1][2:0]}; + io_perf_4_value_REG_1 = _RANDOM[8'hD1][8:3]; + io_perf_5_value_REG = _RANDOM[8'hD1][14:9]; + io_perf_5_value_REG_1 = _RANDOM[8'hD1][20:15]; + io_perf_6_value_REG = _RANDOM[8'hD1][26:21]; + io_perf_6_value_REG_1 = {_RANDOM[8'hD1][31:27], _RANDOM[8'hD2][0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + s1_valid_dup_3 = 1'h0; + s2_valid_dup_3 = 1'h0; + s3_valid_dup_3 = 1'h0; + s0_folded_gh_reg_dup_1_hist_17_folded_hist = 11'h0; + s0_folded_gh_reg_dup_1_hist_16_folded_hist = 11'h0; + s0_folded_gh_reg_dup_1_hist_15_folded_hist = 7'h0; + s0_folded_gh_reg_dup_1_hist_14_folded_hist = 8'h0; + s0_folded_gh_reg_dup_1_hist_13_folded_hist = 9'h0; + s0_folded_gh_reg_dup_1_hist_12_folded_hist = 4'h0; + s0_folded_gh_reg_dup_1_hist_11_folded_hist = 8'h0; + s0_folded_gh_reg_dup_1_hist_10_folded_hist = 9'h0; + s0_folded_gh_reg_dup_1_hist_9_folded_hist = 7'h0; + s0_folded_gh_reg_dup_1_hist_8_folded_hist = 8'h0; + s0_folded_gh_reg_dup_1_hist_7_folded_hist = 7'h0; + s0_folded_gh_reg_dup_1_hist_6_folded_hist = 9'h0; + s0_folded_gh_reg_dup_1_hist_5_folded_hist = 7'h0; + s0_folded_gh_reg_dup_1_hist_4_folded_hist = 8'h0; + s0_folded_gh_reg_dup_1_hist_3_folded_hist = 8'h0; + s0_folded_gh_reg_dup_1_hist_2_folded_hist = 8'h0; + s0_folded_gh_reg_dup_1_hist_1_folded_hist = 11'h0; + s0_folded_gh_reg_dup_1_hist_0_folded_hist = 8'h0; + s0_folded_gh_reg_dup_2_hist_17_folded_hist = 11'h0; + s0_folded_gh_reg_dup_2_hist_16_folded_hist = 11'h0; + s0_folded_gh_reg_dup_2_hist_15_folded_hist = 7'h0; + s0_folded_gh_reg_dup_2_hist_14_folded_hist = 8'h0; + s0_folded_gh_reg_dup_2_hist_13_folded_hist = 9'h0; + s0_folded_gh_reg_dup_2_hist_12_folded_hist = 4'h0; + s0_folded_gh_reg_dup_2_hist_11_folded_hist = 8'h0; + s0_folded_gh_reg_dup_2_hist_10_folded_hist = 9'h0; + s0_folded_gh_reg_dup_2_hist_9_folded_hist = 7'h0; + s0_folded_gh_reg_dup_2_hist_8_folded_hist = 8'h0; + s0_folded_gh_reg_dup_2_hist_7_folded_hist = 7'h0; + s0_folded_gh_reg_dup_2_hist_6_folded_hist = 9'h0; + s0_folded_gh_reg_dup_2_hist_5_folded_hist = 7'h0; + s0_folded_gh_reg_dup_2_hist_4_folded_hist = 8'h0; + s0_folded_gh_reg_dup_2_hist_3_folded_hist = 8'h0; + s0_folded_gh_reg_dup_2_hist_2_folded_hist = 8'h0; + s0_folded_gh_reg_dup_2_hist_1_folded_hist = 11'h0; + s0_folded_gh_reg_dup_2_hist_0_folded_hist = 8'h0; + s0_folded_gh_reg_dup_3_hist_17_folded_hist = 11'h0; + s0_folded_gh_reg_dup_3_hist_16_folded_hist = 11'h0; + s0_folded_gh_reg_dup_3_hist_15_folded_hist = 7'h0; + s0_folded_gh_reg_dup_3_hist_14_folded_hist = 8'h0; + s0_folded_gh_reg_dup_3_hist_13_folded_hist = 9'h0; + s0_folded_gh_reg_dup_3_hist_12_folded_hist = 4'h0; + s0_folded_gh_reg_dup_3_hist_11_folded_hist = 8'h0; + s0_folded_gh_reg_dup_3_hist_10_folded_hist = 9'h0; + s0_folded_gh_reg_dup_3_hist_9_folded_hist = 7'h0; + s0_folded_gh_reg_dup_3_hist_8_folded_hist = 8'h0; + s0_folded_gh_reg_dup_3_hist_7_folded_hist = 7'h0; + s0_folded_gh_reg_dup_3_hist_6_folded_hist = 9'h0; + s0_folded_gh_reg_dup_3_hist_5_folded_hist = 7'h0; + s0_folded_gh_reg_dup_3_hist_4_folded_hist = 8'h0; + s0_folded_gh_reg_dup_3_hist_3_folded_hist = 8'h0; + s0_folded_gh_reg_dup_3_hist_2_folded_hist = 8'h0; + s0_folded_gh_reg_dup_3_hist_1_folded_hist = 11'h0; + s0_folded_gh_reg_dup_3_hist_0_folded_hist = 8'h0; + s1_folded_gh_dup_1_hist_17_folded_hist = 11'h0; + s1_folded_gh_dup_1_hist_16_folded_hist = 11'h0; + s1_folded_gh_dup_1_hist_15_folded_hist = 7'h0; + s1_folded_gh_dup_1_hist_14_folded_hist = 8'h0; + s1_folded_gh_dup_1_hist_13_folded_hist = 9'h0; + s1_folded_gh_dup_1_hist_12_folded_hist = 4'h0; + s1_folded_gh_dup_1_hist_11_folded_hist = 8'h0; + s1_folded_gh_dup_1_hist_10_folded_hist = 9'h0; + s1_folded_gh_dup_1_hist_9_folded_hist = 7'h0; + s1_folded_gh_dup_1_hist_8_folded_hist = 8'h0; + s1_folded_gh_dup_1_hist_7_folded_hist = 7'h0; + s1_folded_gh_dup_1_hist_6_folded_hist = 9'h0; + s1_folded_gh_dup_1_hist_5_folded_hist = 7'h0; + s1_folded_gh_dup_1_hist_4_folded_hist = 8'h0; + s1_folded_gh_dup_1_hist_3_folded_hist = 8'h0; + s1_folded_gh_dup_1_hist_2_folded_hist = 8'h0; + s1_folded_gh_dup_1_hist_1_folded_hist = 11'h0; + s1_folded_gh_dup_1_hist_0_folded_hist = 8'h0; + s1_folded_gh_dup_2_hist_17_folded_hist = 11'h0; + s1_folded_gh_dup_2_hist_16_folded_hist = 11'h0; + s1_folded_gh_dup_2_hist_15_folded_hist = 7'h0; + s1_folded_gh_dup_2_hist_14_folded_hist = 8'h0; + s1_folded_gh_dup_2_hist_13_folded_hist = 9'h0; + s1_folded_gh_dup_2_hist_12_folded_hist = 4'h0; + s1_folded_gh_dup_2_hist_11_folded_hist = 8'h0; + s1_folded_gh_dup_2_hist_10_folded_hist = 9'h0; + s1_folded_gh_dup_2_hist_9_folded_hist = 7'h0; + s1_folded_gh_dup_2_hist_8_folded_hist = 8'h0; + s1_folded_gh_dup_2_hist_7_folded_hist = 7'h0; + s1_folded_gh_dup_2_hist_6_folded_hist = 9'h0; + s1_folded_gh_dup_2_hist_5_folded_hist = 7'h0; + s1_folded_gh_dup_2_hist_4_folded_hist = 8'h0; + s1_folded_gh_dup_2_hist_3_folded_hist = 8'h0; + s1_folded_gh_dup_2_hist_2_folded_hist = 8'h0; + s1_folded_gh_dup_2_hist_1_folded_hist = 11'h0; + s1_folded_gh_dup_2_hist_0_folded_hist = 8'h0; + s1_folded_gh_dup_3_hist_17_folded_hist = 11'h0; + s1_folded_gh_dup_3_hist_16_folded_hist = 11'h0; + s1_folded_gh_dup_3_hist_15_folded_hist = 7'h0; + s1_folded_gh_dup_3_hist_14_folded_hist = 8'h0; + s1_folded_gh_dup_3_hist_13_folded_hist = 9'h0; + s1_folded_gh_dup_3_hist_12_folded_hist = 4'h0; + s1_folded_gh_dup_3_hist_11_folded_hist = 8'h0; + s1_folded_gh_dup_3_hist_10_folded_hist = 9'h0; + s1_folded_gh_dup_3_hist_9_folded_hist = 7'h0; + s1_folded_gh_dup_3_hist_8_folded_hist = 8'h0; + s1_folded_gh_dup_3_hist_7_folded_hist = 7'h0; + s1_folded_gh_dup_3_hist_6_folded_hist = 9'h0; + s1_folded_gh_dup_3_hist_5_folded_hist = 7'h0; + s1_folded_gh_dup_3_hist_4_folded_hist = 8'h0; + s1_folded_gh_dup_3_hist_3_folded_hist = 8'h0; + s1_folded_gh_dup_3_hist_2_folded_hist = 8'h0; + s1_folded_gh_dup_3_hist_1_folded_hist = 11'h0; + s1_folded_gh_dup_3_hist_0_folded_hist = 8'h0; + s2_folded_gh_dup_1_hist_17_folded_hist = 11'h0; + s2_folded_gh_dup_1_hist_16_folded_hist = 11'h0; + s2_folded_gh_dup_1_hist_15_folded_hist = 7'h0; + s2_folded_gh_dup_1_hist_14_folded_hist = 8'h0; + s2_folded_gh_dup_1_hist_13_folded_hist = 9'h0; + s2_folded_gh_dup_1_hist_12_folded_hist = 4'h0; + s2_folded_gh_dup_1_hist_11_folded_hist = 8'h0; + s2_folded_gh_dup_1_hist_10_folded_hist = 9'h0; + s2_folded_gh_dup_1_hist_9_folded_hist = 7'h0; + s2_folded_gh_dup_1_hist_8_folded_hist = 8'h0; + s2_folded_gh_dup_1_hist_7_folded_hist = 7'h0; + s2_folded_gh_dup_1_hist_6_folded_hist = 9'h0; + s2_folded_gh_dup_1_hist_5_folded_hist = 7'h0; + s2_folded_gh_dup_1_hist_4_folded_hist = 8'h0; + s2_folded_gh_dup_1_hist_3_folded_hist = 8'h0; + s2_folded_gh_dup_1_hist_2_folded_hist = 8'h0; + s2_folded_gh_dup_1_hist_1_folded_hist = 11'h0; + s2_folded_gh_dup_1_hist_0_folded_hist = 8'h0; + s2_folded_gh_dup_2_hist_17_folded_hist = 11'h0; + s2_folded_gh_dup_2_hist_16_folded_hist = 11'h0; + s2_folded_gh_dup_2_hist_15_folded_hist = 7'h0; + s2_folded_gh_dup_2_hist_14_folded_hist = 8'h0; + s2_folded_gh_dup_2_hist_13_folded_hist = 9'h0; + s2_folded_gh_dup_2_hist_12_folded_hist = 4'h0; + s2_folded_gh_dup_2_hist_11_folded_hist = 8'h0; + s2_folded_gh_dup_2_hist_10_folded_hist = 9'h0; + s2_folded_gh_dup_2_hist_9_folded_hist = 7'h0; + s2_folded_gh_dup_2_hist_8_folded_hist = 8'h0; + s2_folded_gh_dup_2_hist_7_folded_hist = 7'h0; + s2_folded_gh_dup_2_hist_6_folded_hist = 9'h0; + s2_folded_gh_dup_2_hist_5_folded_hist = 7'h0; + s2_folded_gh_dup_2_hist_4_folded_hist = 8'h0; + s2_folded_gh_dup_2_hist_3_folded_hist = 8'h0; + s2_folded_gh_dup_2_hist_2_folded_hist = 8'h0; + s2_folded_gh_dup_2_hist_1_folded_hist = 11'h0; + s2_folded_gh_dup_2_hist_0_folded_hist = 8'h0; + s2_folded_gh_dup_3_hist_17_folded_hist = 11'h0; + s2_folded_gh_dup_3_hist_16_folded_hist = 11'h0; + s2_folded_gh_dup_3_hist_15_folded_hist = 7'h0; + s2_folded_gh_dup_3_hist_14_folded_hist = 8'h0; + s2_folded_gh_dup_3_hist_13_folded_hist = 9'h0; + s2_folded_gh_dup_3_hist_12_folded_hist = 4'h0; + s2_folded_gh_dup_3_hist_11_folded_hist = 8'h0; + s2_folded_gh_dup_3_hist_10_folded_hist = 9'h0; + s2_folded_gh_dup_3_hist_9_folded_hist = 7'h0; + s2_folded_gh_dup_3_hist_8_folded_hist = 8'h0; + s2_folded_gh_dup_3_hist_7_folded_hist = 7'h0; + s2_folded_gh_dup_3_hist_6_folded_hist = 9'h0; + s2_folded_gh_dup_3_hist_5_folded_hist = 7'h0; + s2_folded_gh_dup_3_hist_4_folded_hist = 8'h0; + s2_folded_gh_dup_3_hist_3_folded_hist = 8'h0; + s2_folded_gh_dup_3_hist_2_folded_hist = 8'h0; + s2_folded_gh_dup_3_hist_1_folded_hist = 11'h0; + s2_folded_gh_dup_3_hist_0_folded_hist = 8'h0; + s3_folded_gh_dup_1_hist_17_folded_hist = 11'h0; + s3_folded_gh_dup_1_hist_16_folded_hist = 11'h0; + s3_folded_gh_dup_1_hist_15_folded_hist = 7'h0; + s3_folded_gh_dup_1_hist_14_folded_hist = 8'h0; + s3_folded_gh_dup_1_hist_13_folded_hist = 9'h0; + s3_folded_gh_dup_1_hist_12_folded_hist = 4'h0; + s3_folded_gh_dup_1_hist_11_folded_hist = 8'h0; + s3_folded_gh_dup_1_hist_10_folded_hist = 9'h0; + s3_folded_gh_dup_1_hist_9_folded_hist = 7'h0; + s3_folded_gh_dup_1_hist_8_folded_hist = 8'h0; + s3_folded_gh_dup_1_hist_7_folded_hist = 7'h0; + s3_folded_gh_dup_1_hist_6_folded_hist = 9'h0; + s3_folded_gh_dup_1_hist_5_folded_hist = 7'h0; + s3_folded_gh_dup_1_hist_4_folded_hist = 8'h0; + s3_folded_gh_dup_1_hist_3_folded_hist = 8'h0; + s3_folded_gh_dup_1_hist_2_folded_hist = 8'h0; + s3_folded_gh_dup_1_hist_1_folded_hist = 11'h0; + s3_folded_gh_dup_1_hist_0_folded_hist = 8'h0; + s3_folded_gh_dup_2_hist_17_folded_hist = 11'h0; + s3_folded_gh_dup_2_hist_16_folded_hist = 11'h0; + s3_folded_gh_dup_2_hist_15_folded_hist = 7'h0; + s3_folded_gh_dup_2_hist_14_folded_hist = 8'h0; + s3_folded_gh_dup_2_hist_13_folded_hist = 9'h0; + s3_folded_gh_dup_2_hist_12_folded_hist = 4'h0; + s3_folded_gh_dup_2_hist_11_folded_hist = 8'h0; + s3_folded_gh_dup_2_hist_10_folded_hist = 9'h0; + s3_folded_gh_dup_2_hist_9_folded_hist = 7'h0; + s3_folded_gh_dup_2_hist_8_folded_hist = 8'h0; + s3_folded_gh_dup_2_hist_7_folded_hist = 7'h0; + s3_folded_gh_dup_2_hist_6_folded_hist = 9'h0; + s3_folded_gh_dup_2_hist_5_folded_hist = 7'h0; + s3_folded_gh_dup_2_hist_4_folded_hist = 8'h0; + s3_folded_gh_dup_2_hist_3_folded_hist = 8'h0; + s3_folded_gh_dup_2_hist_2_folded_hist = 8'h0; + s3_folded_gh_dup_2_hist_1_folded_hist = 11'h0; + s3_folded_gh_dup_2_hist_0_folded_hist = 8'h0; + s3_folded_gh_dup_3_hist_17_folded_hist = 11'h0; + s3_folded_gh_dup_3_hist_16_folded_hist = 11'h0; + s3_folded_gh_dup_3_hist_15_folded_hist = 7'h0; + s3_folded_gh_dup_3_hist_14_folded_hist = 8'h0; + s3_folded_gh_dup_3_hist_13_folded_hist = 9'h0; + s3_folded_gh_dup_3_hist_12_folded_hist = 4'h0; + s3_folded_gh_dup_3_hist_11_folded_hist = 8'h0; + s3_folded_gh_dup_3_hist_10_folded_hist = 9'h0; + s3_folded_gh_dup_3_hist_9_folded_hist = 7'h0; + s3_folded_gh_dup_3_hist_8_folded_hist = 8'h0; + s3_folded_gh_dup_3_hist_7_folded_hist = 7'h0; + s3_folded_gh_dup_3_hist_6_folded_hist = 9'h0; + s3_folded_gh_dup_3_hist_5_folded_hist = 7'h0; + s3_folded_gh_dup_3_hist_4_folded_hist = 8'h0; + s3_folded_gh_dup_3_hist_3_folded_hist = 8'h0; + s3_folded_gh_dup_3_hist_2_folded_hist = 8'h0; + s3_folded_gh_dup_3_hist_1_folded_hist = 11'h0; + s3_folded_gh_dup_3_hist_0_folded_hist = 8'h0; + s0_last_br_num_oh_reg_dup_1 = 3'h0; + s0_last_br_num_oh_reg_dup_2 = 3'h0; + s0_last_br_num_oh_reg_dup_3 = 3'h0; + s1_last_br_num_oh_dup_1 = 3'h0; + s1_last_br_num_oh_dup_2 = 3'h0; + s1_last_br_num_oh_dup_3 = 3'h0; + s2_last_br_num_oh_dup_1 = 3'h0; + s2_last_br_num_oh_dup_2 = 3'h0; + s2_last_br_num_oh_dup_3 = 3'h0; + s3_last_br_num_oh_dup_1 = 3'h0; + s3_last_br_num_oh_dup_2 = 3'h0; + s3_last_br_num_oh_dup_3 = 3'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 = 1'h0; + s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; + s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; + s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; + s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; + ghv_0 = 1'h0; + ghv_1 = 1'h0; + ghv_2 = 1'h0; + ghv_3 = 1'h0; + ghv_4 = 1'h0; + ghv_5 = 1'h0; + ghv_6 = 1'h0; + ghv_7 = 1'h0; + ghv_8 = 1'h0; + ghv_9 = 1'h0; + ghv_10 = 1'h0; + ghv_11 = 1'h0; + ghv_12 = 1'h0; + ghv_13 = 1'h0; + ghv_14 = 1'h0; + ghv_15 = 1'h0; + ghv_16 = 1'h0; + ghv_17 = 1'h0; + ghv_18 = 1'h0; + ghv_19 = 1'h0; + ghv_20 = 1'h0; + ghv_21 = 1'h0; + ghv_22 = 1'h0; + ghv_23 = 1'h0; + ghv_24 = 1'h0; + ghv_25 = 1'h0; + ghv_26 = 1'h0; + ghv_27 = 1'h0; + ghv_28 = 1'h0; + ghv_29 = 1'h0; + ghv_30 = 1'h0; + ghv_31 = 1'h0; + ghv_32 = 1'h0; + ghv_33 = 1'h0; + ghv_34 = 1'h0; + ghv_35 = 1'h0; + ghv_36 = 1'h0; + ghv_37 = 1'h0; + ghv_38 = 1'h0; + ghv_39 = 1'h0; + ghv_40 = 1'h0; + ghv_41 = 1'h0; + ghv_42 = 1'h0; + ghv_43 = 1'h0; + ghv_44 = 1'h0; + ghv_45 = 1'h0; + ghv_46 = 1'h0; + ghv_47 = 1'h0; + ghv_48 = 1'h0; + ghv_49 = 1'h0; + ghv_50 = 1'h0; + ghv_51 = 1'h0; + ghv_52 = 1'h0; + ghv_53 = 1'h0; + ghv_54 = 1'h0; + ghv_55 = 1'h0; + ghv_56 = 1'h0; + ghv_57 = 1'h0; + ghv_58 = 1'h0; + ghv_59 = 1'h0; + ghv_60 = 1'h0; + ghv_61 = 1'h0; + ghv_62 = 1'h0; + ghv_63 = 1'h0; + ghv_64 = 1'h0; + ghv_65 = 1'h0; + ghv_66 = 1'h0; + ghv_67 = 1'h0; + ghv_68 = 1'h0; + ghv_69 = 1'h0; + ghv_70 = 1'h0; + ghv_71 = 1'h0; + ghv_72 = 1'h0; + ghv_73 = 1'h0; + ghv_74 = 1'h0; + ghv_75 = 1'h0; + ghv_76 = 1'h0; + ghv_77 = 1'h0; + ghv_78 = 1'h0; + ghv_79 = 1'h0; + ghv_80 = 1'h0; + ghv_81 = 1'h0; + ghv_82 = 1'h0; + ghv_83 = 1'h0; + ghv_84 = 1'h0; + ghv_85 = 1'h0; + ghv_86 = 1'h0; + ghv_87 = 1'h0; + ghv_88 = 1'h0; + ghv_89 = 1'h0; + ghv_90 = 1'h0; + ghv_91 = 1'h0; + ghv_92 = 1'h0; + ghv_93 = 1'h0; + ghv_94 = 1'h0; + ghv_95 = 1'h0; + ghv_96 = 1'h0; + ghv_97 = 1'h0; + ghv_98 = 1'h0; + ghv_99 = 1'h0; + ghv_100 = 1'h0; + ghv_101 = 1'h0; + ghv_102 = 1'h0; + ghv_103 = 1'h0; + ghv_104 = 1'h0; + ghv_105 = 1'h0; + ghv_106 = 1'h0; + ghv_107 = 1'h0; + ghv_108 = 1'h0; + ghv_109 = 1'h0; + ghv_110 = 1'h0; + ghv_111 = 1'h0; + ghv_112 = 1'h0; + ghv_113 = 1'h0; + ghv_114 = 1'h0; + ghv_115 = 1'h0; + ghv_116 = 1'h0; + ghv_117 = 1'h0; + ghv_118 = 1'h0; + ghv_119 = 1'h0; + ghv_120 = 1'h0; + ghv_121 = 1'h0; + ghv_122 = 1'h0; + ghv_123 = 1'h0; + ghv_124 = 1'h0; + ghv_125 = 1'h0; + ghv_126 = 1'h0; + ghv_127 = 1'h0; + ghv_128 = 1'h0; + ghv_129 = 1'h0; + ghv_130 = 1'h0; + ghv_131 = 1'h0; + ghv_132 = 1'h0; + ghv_133 = 1'h0; + ghv_134 = 1'h0; + ghv_135 = 1'h0; + ghv_136 = 1'h0; + ghv_137 = 1'h0; + ghv_138 = 1'h0; + ghv_139 = 1'h0; + ghv_140 = 1'h0; + ghv_141 = 1'h0; + ghv_142 = 1'h0; + ghv_143 = 1'h0; + ghv_144 = 1'h0; + ghv_145 = 1'h0; + ghv_146 = 1'h0; + ghv_147 = 1'h0; + ghv_148 = 1'h0; + ghv_149 = 1'h0; + ghv_150 = 1'h0; + ghv_151 = 1'h0; + ghv_152 = 1'h0; + ghv_153 = 1'h0; + ghv_154 = 1'h0; + ghv_155 = 1'h0; + ghv_156 = 1'h0; + ghv_157 = 1'h0; + ghv_158 = 1'h0; + ghv_159 = 1'h0; + ghv_160 = 1'h0; + ghv_161 = 1'h0; + ghv_162 = 1'h0; + ghv_163 = 1'h0; + ghv_164 = 1'h0; + ghv_165 = 1'h0; + ghv_166 = 1'h0; + ghv_167 = 1'h0; + ghv_168 = 1'h0; + ghv_169 = 1'h0; + ghv_170 = 1'h0; + ghv_171 = 1'h0; + ghv_172 = 1'h0; + ghv_173 = 1'h0; + ghv_174 = 1'h0; + ghv_175 = 1'h0; + ghv_176 = 1'h0; + ghv_177 = 1'h0; + ghv_178 = 1'h0; + ghv_179 = 1'h0; + ghv_180 = 1'h0; + ghv_181 = 1'h0; + ghv_182 = 1'h0; + ghv_183 = 1'h0; + ghv_184 = 1'h0; + ghv_185 = 1'h0; + ghv_186 = 1'h0; + ghv_187 = 1'h0; + ghv_188 = 1'h0; + ghv_189 = 1'h0; + ghv_190 = 1'h0; + ghv_191 = 1'h0; + ghv_192 = 1'h0; + ghv_193 = 1'h0; + ghv_194 = 1'h0; + ghv_195 = 1'h0; + ghv_196 = 1'h0; + ghv_197 = 1'h0; + ghv_198 = 1'h0; + ghv_199 = 1'h0; + ghv_200 = 1'h0; + ghv_201 = 1'h0; + ghv_202 = 1'h0; + ghv_203 = 1'h0; + ghv_204 = 1'h0; + ghv_205 = 1'h0; + ghv_206 = 1'h0; + ghv_207 = 1'h0; + ghv_208 = 1'h0; + ghv_209 = 1'h0; + ghv_210 = 1'h0; + ghv_211 = 1'h0; + ghv_212 = 1'h0; + ghv_213 = 1'h0; + ghv_214 = 1'h0; + ghv_215 = 1'h0; + ghv_216 = 1'h0; + ghv_217 = 1'h0; + ghv_218 = 1'h0; + ghv_219 = 1'h0; + ghv_220 = 1'h0; + ghv_221 = 1'h0; + ghv_222 = 1'h0; + ghv_223 = 1'h0; + ghv_224 = 1'h0; + ghv_225 = 1'h0; + ghv_226 = 1'h0; + ghv_227 = 1'h0; + ghv_228 = 1'h0; + ghv_229 = 1'h0; + ghv_230 = 1'h0; + ghv_231 = 1'h0; + ghv_232 = 1'h0; + ghv_233 = 1'h0; + ghv_234 = 1'h0; + ghv_235 = 1'h0; + ghv_236 = 1'h0; + ghv_237 = 1'h0; + ghv_238 = 1'h0; + ghv_239 = 1'h0; + ghv_240 = 1'h0; + ghv_241 = 1'h0; + ghv_242 = 1'h0; + ghv_243 = 1'h0; + ghv_244 = 1'h0; + ghv_245 = 1'h0; + ghv_246 = 1'h0; + ghv_247 = 1'h0; + ghv_248 = 1'h0; + ghv_249 = 1'h0; + ghv_250 = 1'h0; + ghv_251 = 1'h0; + ghv_252 = 1'h0; + ghv_253 = 1'h0; + ghv_254 = 1'h0; + ghv_255 = 1'h0; + s0_ghist_ptr_reg_dup_0_flag = 1'h0; + s0_ghist_ptr_reg_dup_0_value = 8'h0; + s0_ghist_ptr_reg_dup_1_flag = 1'h0; + s0_ghist_ptr_reg_dup_1_value = 8'h0; + s0_ghist_ptr_reg_dup_2_flag = 1'h0; + s0_ghist_ptr_reg_dup_2_value = 8'h0; + s0_ghist_ptr_reg_dup_3_flag = 1'h0; + s0_ghist_ptr_reg_dup_3_value = 8'h0; + s1_ghist_ptr_dup_0_flag = 1'h0; + s1_ghist_ptr_dup_0_value = 8'h0; + s1_ghist_ptr_dup_1_flag = 1'h0; + s1_ghist_ptr_dup_1_value = 8'h0; + s1_ghist_ptr_dup_2_flag = 1'h0; + s1_ghist_ptr_dup_2_value = 8'h0; + s1_ghist_ptr_dup_3_flag = 1'h0; + s1_ghist_ptr_dup_3_value = 8'h0; + s2_ghist_ptr_dup_0_flag = 1'h0; + s2_ghist_ptr_dup_0_value = 8'h0; + s2_ghist_ptr_dup_1_flag = 1'h0; + s2_ghist_ptr_dup_1_value = 8'h0; + s2_ghist_ptr_dup_2_flag = 1'h0; + s2_ghist_ptr_dup_2_value = 8'h0; + s2_ghist_ptr_dup_3_flag = 1'h0; + s2_ghist_ptr_dup_3_value = 8'h0; + s3_ghist_ptr_dup_0_flag = 1'h0; + s3_ghist_ptr_dup_0_value = 8'h0; + s3_ghist_ptr_dup_1_flag = 1'h0; + s3_ghist_ptr_dup_1_value = 8'h0; + s3_ghist_ptr_dup_2_flag = 1'h0; + s3_ghist_ptr_dup_2_value = 8'h0; + s3_ghist_ptr_dup_3_flag = 1'h0; + s3_ghist_ptr_dup_3_value = 8'h0; + do_redirect_dup_next_valid_last_r = 1'h0; + previous_s1_pred_info_hit_0 = 1'h0; + previous_s1_pred_info_hit_1 = 1'h0; + previous_s1_pred_info_hit_2 = 1'h0; + previous_s1_pred_info_hit_3 = 1'h0; + previous_s1_pred_info_target_0 = 41'h0; + previous_s1_pred_info_target_1 = 41'h0; + previous_s1_pred_info_target_2 = 41'h0; + previous_s1_pred_info_target_3 = 41'h0; + previous_s1_pred_info_lastBrPosOH_0_0 = 1'h0; + previous_s1_pred_info_lastBrPosOH_0_1 = 1'h0; + previous_s1_pred_info_lastBrPosOH_0_2 = 1'h0; + previous_s1_pred_info_lastBrPosOH_1_0 = 1'h0; + previous_s1_pred_info_lastBrPosOH_1_1 = 1'h0; + previous_s1_pred_info_lastBrPosOH_1_2 = 1'h0; + previous_s1_pred_info_lastBrPosOH_2_0 = 1'h0; + previous_s1_pred_info_lastBrPosOH_2_1 = 1'h0; + previous_s1_pred_info_lastBrPosOH_2_2 = 1'h0; + previous_s1_pred_info_lastBrPosOH_3_0 = 1'h0; + previous_s1_pred_info_lastBrPosOH_3_1 = 1'h0; + previous_s1_pred_info_lastBrPosOH_3_2 = 1'h0; + previous_s1_pred_info_taken_0 = 1'h0; + previous_s1_pred_info_taken_1 = 1'h0; + previous_s1_pred_info_taken_2 = 1'h0; + previous_s1_pred_info_taken_3 = 1'h0; + previous_s1_pred_info_takenMask_0_0 = 1'h0; + previous_s1_pred_info_takenMask_0_1 = 1'h0; + previous_s1_pred_info_takenMask_1_0 = 1'h0; + previous_s1_pred_info_takenMask_1_1 = 1'h0; + previous_s1_pred_info_takenMask_2_0 = 1'h0; + previous_s1_pred_info_takenMask_2_1 = 1'h0; + previous_s1_pred_info_takenMask_3_0 = 1'h0; + previous_s1_pred_info_takenMask_3_1 = 1'h0; + previous_s1_pred_info_cfiIndex_0 = 4'h0; + previous_s1_pred_info_cfiIndex_1 = 4'h0; + previous_s1_pred_info_cfiIndex_2 = 4'h0; + previous_s1_pred_info_cfiIndex_3 = 4'h0; + previous_s2_pred_pc_0 = 41'h0; + previous_s2_pred_pc_1 = 41'h0; + previous_s2_pred_pc_2 = 41'h0; + previous_s2_pred_pc_3 = 41'h0; + previous_s2_pred_full_pred_0_br_taken_mask_0 = 1'h0; + previous_s2_pred_full_pred_0_br_taken_mask_1 = 1'h0; + previous_s2_pred_full_pred_0_slot_valids_0 = 1'h0; + previous_s2_pred_full_pred_0_slot_valids_1 = 1'h0; + previous_s2_pred_full_pred_0_targets_0 = 41'h0; + previous_s2_pred_full_pred_0_targets_1 = 41'h0; + previous_s2_pred_full_pred_0_fallThroughAddr = 41'h0; + previous_s2_pred_full_pred_0_is_br_sharing = 1'h0; + previous_s2_pred_full_pred_0_hit = 1'h0; + previous_s2_pred_full_pred_1_br_taken_mask_0 = 1'h0; + previous_s2_pred_full_pred_1_br_taken_mask_1 = 1'h0; + previous_s2_pred_full_pred_1_slot_valids_0 = 1'h0; + previous_s2_pred_full_pred_1_slot_valids_1 = 1'h0; + previous_s2_pred_full_pred_1_targets_0 = 41'h0; + previous_s2_pred_full_pred_1_targets_1 = 41'h0; + previous_s2_pred_full_pred_1_fallThroughAddr = 41'h0; + previous_s2_pred_full_pred_1_is_br_sharing = 1'h0; + previous_s2_pred_full_pred_1_hit = 1'h0; + previous_s2_pred_full_pred_2_br_taken_mask_0 = 1'h0; + previous_s2_pred_full_pred_2_br_taken_mask_1 = 1'h0; + previous_s2_pred_full_pred_2_slot_valids_0 = 1'h0; + previous_s2_pred_full_pred_2_slot_valids_1 = 1'h0; + previous_s2_pred_full_pred_2_targets_0 = 41'h0; + previous_s2_pred_full_pred_2_targets_1 = 41'h0; + previous_s2_pred_full_pred_2_fallThroughAddr = 41'h0; + previous_s2_pred_full_pred_2_is_br_sharing = 1'h0; + previous_s2_pred_full_pred_2_hit = 1'h0; + previous_s2_pred_full_pred_3_br_taken_mask_0 = 1'h0; + previous_s2_pred_full_pred_3_br_taken_mask_1 = 1'h0; + previous_s2_pred_full_pred_3_slot_valids_0 = 1'h0; + previous_s2_pred_full_pred_3_slot_valids_1 = 1'h0; + previous_s2_pred_full_pred_3_targets_0 = 41'h0; + previous_s2_pred_full_pred_3_targets_1 = 41'h0; + previous_s2_pred_full_pred_3_fallThroughAddr = 41'h0; + previous_s2_pred_full_pred_3_is_br_sharing = 1'h0; + previous_s2_pred_full_pred_3_hit = 1'h0; + predictors_io_update_valid_REG = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + DelayN_1 ctrl_delay ( + .clock (clock), + .io_in_ubtb_enable (io_ctrl_ubtb_enable), + .io_in_btb_enable (io_ctrl_btb_enable), + .io_in_tage_enable (io_ctrl_tage_enable), + .io_in_sc_enable (io_ctrl_sc_enable), + .io_in_ras_enable (io_ctrl_ras_enable), + .io_out_ubtb_enable (_ctrl_delay_io_out_ubtb_enable), + .io_out_btb_enable (_ctrl_delay_io_out_btb_enable), + .io_out_tage_enable (_ctrl_delay_io_out_tage_enable), + .io_out_sc_enable (_ctrl_delay_io_out_sc_enable), + .io_out_ras_enable (_ctrl_delay_io_out_ras_enable) + ); + Composer predictors ( + .clock (clock), + .reset (reset), + .io_reset_vector (io_reset_vector), + .io_in_bits_s0_pc_0 (_s0_pc_dup_0_ppm_out_res), + .io_in_bits_s0_pc_1 (_s0_pc_dup_1_ppm_out_res), + .io_in_bits_s0_pc_2 (_s0_pc_dup_2_ppm_out_res), + .io_in_bits_s0_pc_3 (_s0_pc_dup_3_ppm_out_res), + .io_in_bits_folded_hist_1_hist_17_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist), + .io_in_bits_folded_hist_1_hist_16_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist), + .io_in_bits_folded_hist_1_hist_15_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist), + .io_in_bits_folded_hist_1_hist_14_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist), + .io_in_bits_folded_hist_1_hist_9_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist), + .io_in_bits_folded_hist_1_hist_8_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist), + .io_in_bits_folded_hist_1_hist_7_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist), + .io_in_bits_folded_hist_1_hist_5_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist), + .io_in_bits_folded_hist_1_hist_4_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist), + .io_in_bits_folded_hist_1_hist_3_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist), + .io_in_bits_folded_hist_1_hist_1_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist), + .io_in_bits_folded_hist_3_hist_14_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist), + .io_in_bits_folded_hist_3_hist_13_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist), + .io_in_bits_folded_hist_3_hist_12_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist), + .io_in_bits_folded_hist_3_hist_11_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist), + .io_in_bits_folded_hist_3_hist_10_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist), + .io_in_bits_folded_hist_3_hist_6_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist), + .io_in_bits_folded_hist_3_hist_4_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist), + .io_in_bits_folded_hist_3_hist_3_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist), + .io_in_bits_folded_hist_3_hist_2_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist), + .io_out_s1_pc_0 + (_predictors_io_out_s1_pc_0), + .io_out_s1_pc_1 + (_predictors_io_out_s1_pc_1), + .io_out_s1_pc_2 + (_predictors_io_out_s1_pc_2), + .io_out_s1_pc_3 + (_predictors_io_out_s1_pc_3), + .io_out_s1_full_pred_0_br_taken_mask_0 + (_predictors_io_out_s1_full_pred_0_br_taken_mask_0), + .io_out_s1_full_pred_0_br_taken_mask_1 + (_predictors_io_out_s1_full_pred_0_br_taken_mask_1), + .io_out_s1_full_pred_0_slot_valids_0 + (_predictors_io_out_s1_full_pred_0_slot_valids_0), + .io_out_s1_full_pred_0_slot_valids_1 + (_predictors_io_out_s1_full_pred_0_slot_valids_1), + .io_out_s1_full_pred_0_targets_0 + (_predictors_io_out_s1_full_pred_0_targets_0), + .io_out_s1_full_pred_0_targets_1 + (_predictors_io_out_s1_full_pred_0_targets_1), + .io_out_s1_full_pred_0_offsets_0 + (_predictors_io_out_s1_full_pred_0_offsets_0), + .io_out_s1_full_pred_0_offsets_1 + (_predictors_io_out_s1_full_pred_0_offsets_1), + .io_out_s1_full_pred_0_fallThroughAddr + (_predictors_io_out_s1_full_pred_0_fallThroughAddr), + .io_out_s1_full_pred_0_is_br_sharing + (_predictors_io_out_s1_full_pred_0_is_br_sharing), + .io_out_s1_full_pred_0_hit + (_predictors_io_out_s1_full_pred_0_hit), + .io_out_s1_full_pred_1_br_taken_mask_0 + (_predictors_io_out_s1_full_pred_1_br_taken_mask_0), + .io_out_s1_full_pred_1_br_taken_mask_1 + (_predictors_io_out_s1_full_pred_1_br_taken_mask_1), + .io_out_s1_full_pred_1_slot_valids_0 + (_predictors_io_out_s1_full_pred_1_slot_valids_0), + .io_out_s1_full_pred_1_slot_valids_1 + (_predictors_io_out_s1_full_pred_1_slot_valids_1), + .io_out_s1_full_pred_1_targets_0 + (_predictors_io_out_s1_full_pred_1_targets_0), + .io_out_s1_full_pred_1_targets_1 + (_predictors_io_out_s1_full_pred_1_targets_1), + .io_out_s1_full_pred_1_offsets_0 + (_predictors_io_out_s1_full_pred_1_offsets_0), + .io_out_s1_full_pred_1_offsets_1 + (_predictors_io_out_s1_full_pred_1_offsets_1), + .io_out_s1_full_pred_1_fallThroughAddr + (_predictors_io_out_s1_full_pred_1_fallThroughAddr), + .io_out_s1_full_pred_1_is_br_sharing + (_predictors_io_out_s1_full_pred_1_is_br_sharing), + .io_out_s1_full_pred_1_hit + (_predictors_io_out_s1_full_pred_1_hit), + .io_out_s1_full_pred_2_br_taken_mask_0 + (_predictors_io_out_s1_full_pred_2_br_taken_mask_0), + .io_out_s1_full_pred_2_br_taken_mask_1 + (_predictors_io_out_s1_full_pred_2_br_taken_mask_1), + .io_out_s1_full_pred_2_slot_valids_0 + (_predictors_io_out_s1_full_pred_2_slot_valids_0), + .io_out_s1_full_pred_2_slot_valids_1 + (_predictors_io_out_s1_full_pred_2_slot_valids_1), + .io_out_s1_full_pred_2_targets_0 + (_predictors_io_out_s1_full_pred_2_targets_0), + .io_out_s1_full_pred_2_targets_1 + (_predictors_io_out_s1_full_pred_2_targets_1), + .io_out_s1_full_pred_2_offsets_0 + (_predictors_io_out_s1_full_pred_2_offsets_0), + .io_out_s1_full_pred_2_offsets_1 + (_predictors_io_out_s1_full_pred_2_offsets_1), + .io_out_s1_full_pred_2_fallThroughAddr + (_predictors_io_out_s1_full_pred_2_fallThroughAddr), + .io_out_s1_full_pred_2_is_br_sharing + (_predictors_io_out_s1_full_pred_2_is_br_sharing), + .io_out_s1_full_pred_2_hit + (_predictors_io_out_s1_full_pred_2_hit), + .io_out_s1_full_pred_3_br_taken_mask_0 + (_predictors_io_out_s1_full_pred_3_br_taken_mask_0), + .io_out_s1_full_pred_3_br_taken_mask_1 + (_predictors_io_out_s1_full_pred_3_br_taken_mask_1), + .io_out_s1_full_pred_3_slot_valids_0 + (_predictors_io_out_s1_full_pred_3_slot_valids_0), + .io_out_s1_full_pred_3_slot_valids_1 + (_predictors_io_out_s1_full_pred_3_slot_valids_1), + .io_out_s1_full_pred_3_targets_0 + (_predictors_io_out_s1_full_pred_3_targets_0), + .io_out_s1_full_pred_3_targets_1 + (_predictors_io_out_s1_full_pred_3_targets_1), + .io_out_s1_full_pred_3_offsets_0 + (_predictors_io_out_s1_full_pred_3_offsets_0), + .io_out_s1_full_pred_3_offsets_1 + (_predictors_io_out_s1_full_pred_3_offsets_1), + .io_out_s1_full_pred_3_fallThroughAddr + (_predictors_io_out_s1_full_pred_3_fallThroughAddr), + .io_out_s1_full_pred_3_fallThroughErr + (io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughErr), + .io_out_s1_full_pred_3_is_br_sharing + (_predictors_io_out_s1_full_pred_3_is_br_sharing), + .io_out_s1_full_pred_3_hit + (_predictors_io_out_s1_full_pred_3_hit), + .io_out_s2_pc_0 + (_predictors_io_out_s2_pc_0), + .io_out_s2_pc_1 + (_predictors_io_out_s2_pc_1), + .io_out_s2_pc_2 + (_predictors_io_out_s2_pc_2), + .io_out_s2_pc_3 + (_predictors_io_out_s2_pc_3), + .io_out_s2_full_pred_0_br_taken_mask_0 + (_predictors_io_out_s2_full_pred_0_br_taken_mask_0), + .io_out_s2_full_pred_0_br_taken_mask_1 + (_predictors_io_out_s2_full_pred_0_br_taken_mask_1), + .io_out_s2_full_pred_0_slot_valids_0 + (_predictors_io_out_s2_full_pred_0_slot_valids_0), + .io_out_s2_full_pred_0_slot_valids_1 + (_predictors_io_out_s2_full_pred_0_slot_valids_1), + .io_out_s2_full_pred_0_targets_0 + (_predictors_io_out_s2_full_pred_0_targets_0), + .io_out_s2_full_pred_0_targets_1 + (_predictors_io_out_s2_full_pred_0_targets_1), + .io_out_s2_full_pred_0_offsets_0 + (_predictors_io_out_s2_full_pred_0_offsets_0), + .io_out_s2_full_pred_0_offsets_1 + (_predictors_io_out_s2_full_pred_0_offsets_1), + .io_out_s2_full_pred_0_fallThroughAddr + (_predictors_io_out_s2_full_pred_0_fallThroughAddr), + .io_out_s2_full_pred_0_is_br_sharing + (_predictors_io_out_s2_full_pred_0_is_br_sharing), + .io_out_s2_full_pred_0_hit + (_predictors_io_out_s2_full_pred_0_hit), + .io_out_s2_full_pred_1_br_taken_mask_0 + (_predictors_io_out_s2_full_pred_1_br_taken_mask_0), + .io_out_s2_full_pred_1_br_taken_mask_1 + (_predictors_io_out_s2_full_pred_1_br_taken_mask_1), + .io_out_s2_full_pred_1_slot_valids_0 + (_predictors_io_out_s2_full_pred_1_slot_valids_0), + .io_out_s2_full_pred_1_slot_valids_1 + (_predictors_io_out_s2_full_pred_1_slot_valids_1), + .io_out_s2_full_pred_1_targets_0 + (_predictors_io_out_s2_full_pred_1_targets_0), + .io_out_s2_full_pred_1_targets_1 + (_predictors_io_out_s2_full_pred_1_targets_1), + .io_out_s2_full_pred_1_offsets_0 + (_predictors_io_out_s2_full_pred_1_offsets_0), + .io_out_s2_full_pred_1_offsets_1 + (_predictors_io_out_s2_full_pred_1_offsets_1), + .io_out_s2_full_pred_1_fallThroughAddr + (_predictors_io_out_s2_full_pred_1_fallThroughAddr), + .io_out_s2_full_pred_1_is_br_sharing + (_predictors_io_out_s2_full_pred_1_is_br_sharing), + .io_out_s2_full_pred_1_hit + (_predictors_io_out_s2_full_pred_1_hit), + .io_out_s2_full_pred_2_br_taken_mask_0 + (_predictors_io_out_s2_full_pred_2_br_taken_mask_0), + .io_out_s2_full_pred_2_br_taken_mask_1 + (_predictors_io_out_s2_full_pred_2_br_taken_mask_1), + .io_out_s2_full_pred_2_slot_valids_0 + (_predictors_io_out_s2_full_pred_2_slot_valids_0), + .io_out_s2_full_pred_2_slot_valids_1 + (_predictors_io_out_s2_full_pred_2_slot_valids_1), + .io_out_s2_full_pred_2_targets_0 + (_predictors_io_out_s2_full_pred_2_targets_0), + .io_out_s2_full_pred_2_targets_1 + (_predictors_io_out_s2_full_pred_2_targets_1), + .io_out_s2_full_pred_2_offsets_0 + (_predictors_io_out_s2_full_pred_2_offsets_0), + .io_out_s2_full_pred_2_offsets_1 + (_predictors_io_out_s2_full_pred_2_offsets_1), + .io_out_s2_full_pred_2_fallThroughAddr + (_predictors_io_out_s2_full_pred_2_fallThroughAddr), + .io_out_s2_full_pred_2_is_br_sharing + (_predictors_io_out_s2_full_pred_2_is_br_sharing), + .io_out_s2_full_pred_2_hit + (_predictors_io_out_s2_full_pred_2_hit), + .io_out_s2_full_pred_3_br_taken_mask_0 + (_predictors_io_out_s2_full_pred_3_br_taken_mask_0), + .io_out_s2_full_pred_3_br_taken_mask_1 + (_predictors_io_out_s2_full_pred_3_br_taken_mask_1), + .io_out_s2_full_pred_3_slot_valids_0 + (_predictors_io_out_s2_full_pred_3_slot_valids_0), + .io_out_s2_full_pred_3_slot_valids_1 + (_predictors_io_out_s2_full_pred_3_slot_valids_1), + .io_out_s2_full_pred_3_targets_0 + (_predictors_io_out_s2_full_pred_3_targets_0), + .io_out_s2_full_pred_3_targets_1 + (_predictors_io_out_s2_full_pred_3_targets_1), + .io_out_s2_full_pred_3_offsets_0 + (_predictors_io_out_s2_full_pred_3_offsets_0), + .io_out_s2_full_pred_3_offsets_1 + (_predictors_io_out_s2_full_pred_3_offsets_1), + .io_out_s2_full_pred_3_fallThroughAddr + (_predictors_io_out_s2_full_pred_3_fallThroughAddr), + .io_out_s2_full_pred_3_fallThroughErr + (io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughErr), + .io_out_s2_full_pred_3_is_br_sharing + (_predictors_io_out_s2_full_pred_3_is_br_sharing), + .io_out_s2_full_pred_3_hit + (_predictors_io_out_s2_full_pred_3_hit), + .io_out_s3_pc_0 + (_predictors_io_out_s3_pc_0), + .io_out_s3_pc_1 + (_predictors_io_out_s3_pc_1), + .io_out_s3_pc_2 + (_predictors_io_out_s3_pc_2), + .io_out_s3_pc_3 + (_predictors_io_out_s3_pc_3), + .io_out_s3_full_pred_0_br_taken_mask_0 + (_predictors_io_out_s3_full_pred_0_br_taken_mask_0), + .io_out_s3_full_pred_0_br_taken_mask_1 + (_predictors_io_out_s3_full_pred_0_br_taken_mask_1), + .io_out_s3_full_pred_0_slot_valids_0 + (_predictors_io_out_s3_full_pred_0_slot_valids_0), + .io_out_s3_full_pred_0_slot_valids_1 + (_predictors_io_out_s3_full_pred_0_slot_valids_1), + .io_out_s3_full_pred_0_targets_0 + (_predictors_io_out_s3_full_pred_0_targets_0), + .io_out_s3_full_pred_0_targets_1 + (_predictors_io_out_s3_full_pred_0_targets_1), + .io_out_s3_full_pred_0_fallThroughAddr + (_predictors_io_out_s3_full_pred_0_fallThroughAddr), + .io_out_s3_full_pred_0_fallThroughErr + (_predictors_io_out_s3_full_pred_0_fallThroughErr), + .io_out_s3_full_pred_0_is_br_sharing + (_predictors_io_out_s3_full_pred_0_is_br_sharing), + .io_out_s3_full_pred_0_hit + (_predictors_io_out_s3_full_pred_0_hit), + .io_out_s3_full_pred_1_br_taken_mask_0 + (_predictors_io_out_s3_full_pred_1_br_taken_mask_0), + .io_out_s3_full_pred_1_br_taken_mask_1 + (_predictors_io_out_s3_full_pred_1_br_taken_mask_1), + .io_out_s3_full_pred_1_slot_valids_0 + (_predictors_io_out_s3_full_pred_1_slot_valids_0), + .io_out_s3_full_pred_1_slot_valids_1 + (_predictors_io_out_s3_full_pred_1_slot_valids_1), + .io_out_s3_full_pred_1_targets_0 + (_predictors_io_out_s3_full_pred_1_targets_0), + .io_out_s3_full_pred_1_targets_1 + (_predictors_io_out_s3_full_pred_1_targets_1), + .io_out_s3_full_pred_1_fallThroughAddr + (_predictors_io_out_s3_full_pred_1_fallThroughAddr), + .io_out_s3_full_pred_1_fallThroughErr + (_predictors_io_out_s3_full_pred_1_fallThroughErr), + .io_out_s3_full_pred_1_is_br_sharing + (_predictors_io_out_s3_full_pred_1_is_br_sharing), + .io_out_s3_full_pred_1_hit + (_predictors_io_out_s3_full_pred_1_hit), + .io_out_s3_full_pred_2_br_taken_mask_0 + (_predictors_io_out_s3_full_pred_2_br_taken_mask_0), + .io_out_s3_full_pred_2_br_taken_mask_1 + (_predictors_io_out_s3_full_pred_2_br_taken_mask_1), + .io_out_s3_full_pred_2_slot_valids_0 + (_predictors_io_out_s3_full_pred_2_slot_valids_0), + .io_out_s3_full_pred_2_slot_valids_1 + (_predictors_io_out_s3_full_pred_2_slot_valids_1), + .io_out_s3_full_pred_2_targets_0 + (_predictors_io_out_s3_full_pred_2_targets_0), + .io_out_s3_full_pred_2_targets_1 + (_predictors_io_out_s3_full_pred_2_targets_1), + .io_out_s3_full_pred_2_fallThroughAddr + (_predictors_io_out_s3_full_pred_2_fallThroughAddr), + .io_out_s3_full_pred_2_fallThroughErr + (_predictors_io_out_s3_full_pred_2_fallThroughErr), + .io_out_s3_full_pred_2_is_br_sharing + (_predictors_io_out_s3_full_pred_2_is_br_sharing), + .io_out_s3_full_pred_2_hit + (_predictors_io_out_s3_full_pred_2_hit), + .io_out_s3_full_pred_3_br_taken_mask_0 + (_predictors_io_out_s3_full_pred_3_br_taken_mask_0), + .io_out_s3_full_pred_3_br_taken_mask_1 + (_predictors_io_out_s3_full_pred_3_br_taken_mask_1), + .io_out_s3_full_pred_3_slot_valids_0 + (_predictors_io_out_s3_full_pred_3_slot_valids_0), + .io_out_s3_full_pred_3_slot_valids_1 + (_predictors_io_out_s3_full_pred_3_slot_valids_1), + .io_out_s3_full_pred_3_targets_0 + (_predictors_io_out_s3_full_pred_3_targets_0), + .io_out_s3_full_pred_3_targets_1 + (_predictors_io_out_s3_full_pred_3_targets_1), + .io_out_s3_full_pred_3_offsets_0 + (io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_0), + .io_out_s3_full_pred_3_offsets_1 + (io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_1), + .io_out_s3_full_pred_3_fallThroughAddr + (_predictors_io_out_s3_full_pred_3_fallThroughAddr), + .io_out_s3_full_pred_3_fallThroughErr + (_predictors_io_out_s3_full_pred_3_fallThroughErr), + .io_out_s3_full_pred_3_is_br_sharing + (_predictors_io_out_s3_full_pred_3_is_br_sharing), + .io_out_s3_full_pred_3_hit + (_predictors_io_out_s3_full_pred_3_hit), + .io_out_last_stage_meta + (io_bpu_to_ftq_resp_bits_last_stage_meta), + .io_out_last_stage_spec_info_ssp + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_ssp), + .io_out_last_stage_spec_info_sctr + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_sctr), + .io_out_last_stage_spec_info_TOSW_flag + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_flag), + .io_out_last_stage_spec_info_TOSW_value + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_value), + .io_out_last_stage_spec_info_TOSR_flag + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_flag), + .io_out_last_stage_spec_info_TOSR_value + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_value), + .io_out_last_stage_spec_info_NOS_flag + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_flag), + .io_out_last_stage_spec_info_NOS_value + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_value), + .io_out_last_stage_spec_info_topAddr + (io_bpu_to_ftq_resp_bits_last_stage_spec_info_topAddr), + .io_out_last_stage_ftb_entry_valid + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_valid), + .io_out_last_stage_ftb_entry_brSlots_0_offset + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_offset), + .io_out_last_stage_ftb_entry_brSlots_0_lower + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_lower), + .io_out_last_stage_ftb_entry_brSlots_0_tarStat + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_tarStat), + .io_out_last_stage_ftb_entry_brSlots_0_sharing + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_sharing), + .io_out_last_stage_ftb_entry_brSlots_0_valid + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_valid), + .io_out_last_stage_ftb_entry_tailSlot_offset + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_offset), + .io_out_last_stage_ftb_entry_tailSlot_lower + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_lower), + .io_out_last_stage_ftb_entry_tailSlot_tarStat + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_tarStat), + .io_out_last_stage_ftb_entry_tailSlot_sharing + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_sharing), + .io_out_last_stage_ftb_entry_tailSlot_valid + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_valid), + .io_out_last_stage_ftb_entry_pftAddr + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_pftAddr), + .io_out_last_stage_ftb_entry_carry + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_carry), + .io_out_last_stage_ftb_entry_isCall + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isCall), + .io_out_last_stage_ftb_entry_isRet + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isRet), + .io_out_last_stage_ftb_entry_isJalr + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isJalr), + .io_out_last_stage_ftb_entry_last_may_be_rvi_call + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_last_may_be_rvi_call), + .io_out_last_stage_ftb_entry_always_taken_0 + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_0), + .io_out_last_stage_ftb_entry_always_taken_1 + (io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_1), + .io_ctrl_ubtb_enable + (_ctrl_delay_io_out_ubtb_enable), + .io_ctrl_btb_enable + (_ctrl_delay_io_out_btb_enable), + .io_ctrl_tage_enable + (_ctrl_delay_io_out_tage_enable), + .io_ctrl_sc_enable + (_ctrl_delay_io_out_sc_enable), + .io_ctrl_ras_enable + (_ctrl_delay_io_out_ras_enable), + .io_s0_fire_0 (s0_fire_dup_0), + .io_s0_fire_1 (s0_fire_dup_1), + .io_s0_fire_2 (s0_fire_dup_2), + .io_s0_fire_3 (s0_fire_dup_3), + .io_s1_fire_0 (s1_fire_dup_0), + .io_s1_fire_1 (s1_fire_dup_1), + .io_s1_fire_2 (s1_fire_dup_2), + .io_s1_fire_3 (s1_fire_dup_3), + .io_s2_fire_0 (s2_valid_dup_3), + .io_s2_fire_1 (s2_valid_dup_3), + .io_s2_fire_2 (s2_valid_dup_3), + .io_s2_fire_3 (s2_valid_dup_3), + .io_s3_fire_2 (s3_valid_dup_3), + .io_s3_redirect_2 (s3_redirect_dup_2), + .io_s1_ready (_predictors_io_s1_ready), + .io_update_valid + (predictors_io_update_valid_REG), + .io_update_bits_pc + (predictors_io_update_bits_r_pc), + .io_update_bits_spec_info_folded_hist_hist_17_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_17_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_16_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_16_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_15_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_15_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_14_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_14_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_13_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_13_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_12_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_12_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_11_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_11_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_10_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_10_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_9_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_9_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_8_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_8_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_7_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_7_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_6_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_6_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_5_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_5_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_4_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_4_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_3_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_3_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_2_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_2_folded_hist), + .io_update_bits_spec_info_folded_hist_hist_1_folded_hist + (predictors_io_update_bits_r_spec_info_folded_hist_hist_1_folded_hist), + .io_update_bits_ftb_entry_valid + (predictors_io_update_bits_r_ftb_entry_valid), + .io_update_bits_ftb_entry_brSlots_0_offset + (predictors_io_update_bits_r_ftb_entry_brSlots_0_offset), + .io_update_bits_ftb_entry_brSlots_0_lower + (predictors_io_update_bits_r_ftb_entry_brSlots_0_lower), + .io_update_bits_ftb_entry_brSlots_0_tarStat + (predictors_io_update_bits_r_ftb_entry_brSlots_0_tarStat), + .io_update_bits_ftb_entry_brSlots_0_sharing + (predictors_io_update_bits_r_ftb_entry_brSlots_0_sharing), + .io_update_bits_ftb_entry_brSlots_0_valid + (predictors_io_update_bits_r_ftb_entry_brSlots_0_valid), + .io_update_bits_ftb_entry_tailSlot_offset + (predictors_io_update_bits_r_ftb_entry_tailSlot_offset), + .io_update_bits_ftb_entry_tailSlot_lower + (predictors_io_update_bits_r_ftb_entry_tailSlot_lower), + .io_update_bits_ftb_entry_tailSlot_tarStat + (predictors_io_update_bits_r_ftb_entry_tailSlot_tarStat), + .io_update_bits_ftb_entry_tailSlot_sharing + (predictors_io_update_bits_r_ftb_entry_tailSlot_sharing), + .io_update_bits_ftb_entry_tailSlot_valid + (predictors_io_update_bits_r_ftb_entry_tailSlot_valid), + .io_update_bits_ftb_entry_pftAddr + (predictors_io_update_bits_r_ftb_entry_pftAddr), + .io_update_bits_ftb_entry_carry + (predictors_io_update_bits_r_ftb_entry_carry), + .io_update_bits_ftb_entry_isCall + (predictors_io_update_bits_r_ftb_entry_isCall), + .io_update_bits_ftb_entry_isRet + (predictors_io_update_bits_r_ftb_entry_isRet), + .io_update_bits_ftb_entry_isJalr + (predictors_io_update_bits_r_ftb_entry_isJalr), + .io_update_bits_ftb_entry_last_may_be_rvi_call + (predictors_io_update_bits_r_ftb_entry_last_may_be_rvi_call), + .io_update_bits_ftb_entry_always_taken_0 + (predictors_io_update_bits_r_ftb_entry_always_taken_0), + .io_update_bits_ftb_entry_always_taken_1 + (predictors_io_update_bits_r_ftb_entry_always_taken_1), + .io_update_bits_cfi_idx_valid + (predictors_io_update_bits_r_cfi_idx_valid), + .io_update_bits_cfi_idx_bits + (predictors_io_update_bits_r_cfi_idx_bits), + .io_update_bits_br_taken_mask_0 + (predictors_io_update_bits_r_br_taken_mask_0), + .io_update_bits_br_taken_mask_1 + (predictors_io_update_bits_r_br_taken_mask_1), + .io_update_bits_jmp_taken + (predictors_io_update_bits_r_jmp_taken), + .io_update_bits_mispred_mask_0 + (predictors_io_update_bits_r_mispred_mask_0), + .io_update_bits_mispred_mask_1 + (predictors_io_update_bits_r_mispred_mask_1), + .io_update_bits_mispred_mask_2 + (predictors_io_update_bits_r_mispred_mask_2), + .io_update_bits_old_entry + (predictors_io_update_bits_r_old_entry), + .io_update_bits_meta + (predictors_io_update_bits_r_meta), + .io_update_bits_full_target + (predictors_io_update_bits_r_full_target), + .io_redirect_valid + (do_redirect_dup_next_valid_last_r), + .io_redirect_bits_level + (do_redirect_dup_next_bits_r_level), + .io_redirect_bits_cfiUpdate_pc + (do_redirect_dup_next_bits_r_cfiUpdate_pc), + .io_redirect_bits_cfiUpdate_pd_isRVC + (do_redirect_dup_next_bits_r_cfiUpdate_pd_isRVC), + .io_redirect_bits_cfiUpdate_pd_isCall + (do_redirect_dup_next_bits_r_cfiUpdate_pd_isCall), + .io_redirect_bits_cfiUpdate_pd_isRet + (do_redirect_dup_next_bits_r_cfiUpdate_pd_isRet), + .io_redirect_bits_cfiUpdate_ssp + (do_redirect_dup_next_bits_r_cfiUpdate_ssp), + .io_redirect_bits_cfiUpdate_sctr + (do_redirect_dup_next_bits_r_cfiUpdate_sctr), + .io_redirect_bits_cfiUpdate_TOSW_flag + (do_redirect_dup_next_bits_r_cfiUpdate_TOSW_flag), + .io_redirect_bits_cfiUpdate_TOSW_value + (do_redirect_dup_next_bits_r_cfiUpdate_TOSW_value), + .io_redirect_bits_cfiUpdate_TOSR_flag + (do_redirect_dup_next_bits_r_cfiUpdate_TOSR_flag), + .io_redirect_bits_cfiUpdate_TOSR_value + (do_redirect_dup_next_bits_r_cfiUpdate_TOSR_value), + .io_redirect_bits_cfiUpdate_NOS_flag + (do_redirect_dup_next_bits_r_cfiUpdate_NOS_flag), + .io_redirect_bits_cfiUpdate_NOS_value + (do_redirect_dup_next_bits_r_cfiUpdate_NOS_value), + .io_perf_0_value + (_predictors_io_perf_0_value), + .io_perf_1_value + (_predictors_io_perf_1_value), + .io_perf_2_value + (_predictors_io_perf_2_value), + .io_perf_3_value + (_predictors_io_perf_3_value), + .io_perf_4_value + (_predictors_io_perf_4_value), + .io_perf_5_value + (_predictors_io_perf_5_value), + .io_perf_6_value + (_predictors_io_perf_6_value) + ); + DelayN_2 reset_vector_delay ( + .clock (clock), + .io_in (io_reset_vector), + .io_out (_reset_vector_delay_io_out) + ); + PriorityMuxModule s0_pc_dup_0_ppm ( + .s2_target_sel + (s2_redirect_dup_0 & ~s3_redirect_dup_0 & ~do_redirect_dup_next_valid_last_r), + .s2_target_src + ((_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + ? _predictors_io_out_s2_full_pred_0_targets_0 + : 41'h0) + | (~_cfiIndex_bits_T_261 & _GEN_21 & _predictors_io_out_s2_full_pred_0_hit + ? _predictors_io_out_s2_full_pred_0_targets_1 + : 41'h0) + | ({_GEN_21, _cfiIndex_bits_T_261} == 2'h0 & _predictors_io_out_s2_full_pred_0_hit + ? _predictors_io_out_s2_full_pred_0_fallThroughAddr + : 41'h0) + | (_predictors_io_out_s2_full_pred_0_hit + ? 41'h0 + : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T)), + .s1_target_sel + (s1_valid_dup_3 & ~s2_redirect_dup_0 & ~s3_redirect_dup_0 + & ~do_redirect_dup_next_valid_last_r), + .s1_target_src + ((s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_targets_0 + : 41'h0) + | (~s1_pred_info_takenMask_0_0 & s1_pred_info_takenMask_0_1 + & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_targets_1 + : 41'h0) + | ({s1_pred_info_takenMask_0_1, s1_pred_info_takenMask_0_0} == 2'h0 + & _predictors_io_out_s1_full_pred_0_hit + ? _predictors_io_out_s1_full_pred_0_fallThroughAddr + : 41'h0) | _GEN_4), + .s3_target_sel (s3_redirect_dup_0 & ~do_redirect_dup_next_valid_last_r), + .s3_target_src + ((_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + ? _predictors_io_out_s3_full_pred_0_targets_0 + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_8 & _GEN_32 + & _predictors_io_out_s3_full_pred_0_hit + ? _predictors_io_out_s3_full_pred_0_targets_1 + : 41'h0) + | ({_GEN_32, _s3_redirect_on_jalr_target_dup_T_8} == 2'h0 + & _predictors_io_out_s3_full_pred_0_hit + ? _predictors_io_out_s3_full_pred_0_fallThroughAddr + : 41'h0) + | (_predictors_io_out_s3_full_pred_0_hit + ? 41'h0 + : _s3_redirect_on_target_dup_T_5)), + .redirect_target_sel (do_redirect_dup_next_valid_last_r), + .redirect_target_src (do_redirect_dup_next_bits_r_cfiUpdate_target), + .stallPC_src (s0_pc_reg_dup_0), + .out_res (_s0_pc_dup_0_ppm_out_res) + ); + PriorityMuxModule s0_pc_dup_1_ppm ( + .s2_target_sel + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), + .s2_target_src + ((_cfiIndex_bits_T_282 & _predictors_io_out_s2_full_pred_1_hit + ? _predictors_io_out_s2_full_pred_1_targets_0 + : 41'h0) + | (~_cfiIndex_bits_T_282 & _GEN_22 & _predictors_io_out_s2_full_pred_1_hit + ? _predictors_io_out_s2_full_pred_1_targets_1 + : 41'h0) + | ({_GEN_22, _cfiIndex_bits_T_282} == 2'h0 & _predictors_io_out_s2_full_pred_1_hit + ? _predictors_io_out_s2_full_pred_1_fallThroughAddr + : 41'h0) + | (_predictors_io_out_s2_full_pred_1_hit + ? 41'h0 + : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_2)), + .s1_target_sel + (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 + & ~do_redirect_dup_next_valid_last_r), + .s1_target_src + ((s1_pred_info_takenMask_1_0 & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_targets_0 + : 41'h0) + | (~s1_pred_info_takenMask_1_0 & s1_pred_info_takenMask_1_1 + & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_targets_1 + : 41'h0) + | ({s1_pred_info_takenMask_1_1, s1_pred_info_takenMask_1_0} == 2'h0 + & _predictors_io_out_s1_full_pred_1_hit + ? _predictors_io_out_s1_full_pred_1_fallThroughAddr + : 41'h0) | _GEN_5), + .s3_target_sel (s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), + .s3_target_src + ((_s3_redirect_on_jalr_target_dup_T_28 & _predictors_io_out_s3_full_pred_1_hit + ? _predictors_io_out_s3_full_pred_1_targets_0 + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_28 & _GEN_33 + & _predictors_io_out_s3_full_pred_1_hit + ? _predictors_io_out_s3_full_pred_1_targets_1 + : 41'h0) + | ({_GEN_33, _s3_redirect_on_jalr_target_dup_T_28} == 2'h0 + & _predictors_io_out_s3_full_pred_1_hit + ? _predictors_io_out_s3_full_pred_1_fallThroughAddr + : 41'h0) + | (_predictors_io_out_s3_full_pred_1_hit + ? 41'h0 + : _s3_redirect_on_target_dup_T_19)), + .redirect_target_sel (do_redirect_dup_next_valid_last_r), + .redirect_target_src (do_redirect_dup_next_bits_r_cfiUpdate_target), + .stallPC_src (s0_pc_reg_dup_1), + .out_res (_s0_pc_dup_1_ppm_out_res) + ); + PriorityMuxModule s0_pc_dup_2_ppm ( + .s2_target_sel + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), + .s2_target_src + ((_cfiIndex_bits_T_303 & _predictors_io_out_s2_full_pred_2_hit + ? _predictors_io_out_s2_full_pred_2_targets_0 + : 41'h0) + | (~_cfiIndex_bits_T_303 & _GEN_23 & _predictors_io_out_s2_full_pred_2_hit + ? _predictors_io_out_s2_full_pred_2_targets_1 + : 41'h0) + | ({_GEN_23, _cfiIndex_bits_T_303} == 2'h0 & _predictors_io_out_s2_full_pred_2_hit + ? _predictors_io_out_s2_full_pred_2_fallThroughAddr + : 41'h0) + | (_predictors_io_out_s2_full_pred_2_hit + ? 41'h0 + : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_4)), + .s1_target_sel + (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 + & ~do_redirect_dup_next_valid_last_r), + .s1_target_src + ((s1_pred_info_takenMask_2_0 & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_targets_0 + : 41'h0) + | (~s1_pred_info_takenMask_2_0 & s1_pred_info_takenMask_2_1 + & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_targets_1 + : 41'h0) + | ({s1_pred_info_takenMask_2_1, s1_pred_info_takenMask_2_0} == 2'h0 + & _predictors_io_out_s1_full_pred_2_hit + ? _predictors_io_out_s1_full_pred_2_fallThroughAddr + : 41'h0) | _GEN_6), + .s3_target_sel (s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), + .s3_target_src + ((_s3_redirect_on_jalr_target_dup_T_48 & _predictors_io_out_s3_full_pred_2_hit + ? _predictors_io_out_s3_full_pred_2_targets_0 + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_48 & _GEN_34 + & _predictors_io_out_s3_full_pred_2_hit + ? _predictors_io_out_s3_full_pred_2_targets_1 + : 41'h0) + | ({_GEN_34, _s3_redirect_on_jalr_target_dup_T_48} == 2'h0 + & _predictors_io_out_s3_full_pred_2_hit + ? _predictors_io_out_s3_full_pred_2_fallThroughAddr + : 41'h0) + | (_predictors_io_out_s3_full_pred_2_hit + ? 41'h0 + : _s3_redirect_on_target_dup_T_33)), + .redirect_target_sel (do_redirect_dup_next_valid_last_r), + .redirect_target_src (do_redirect_dup_next_bits_r_cfiUpdate_target), + .stallPC_src (s0_pc_reg_dup_2), + .out_res (_s0_pc_dup_2_ppm_out_res) + ); + PriorityMuxModule s0_pc_dup_3_ppm ( + .s2_target_sel + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), + .s2_target_src + ((_cfiIndex_bits_T_324 & _predictors_io_out_s2_full_pred_3_hit + ? _predictors_io_out_s2_full_pred_3_targets_0 + : 41'h0) + | (~_cfiIndex_bits_T_324 & _GEN_24 & _predictors_io_out_s2_full_pred_3_hit + ? _predictors_io_out_s2_full_pred_3_targets_1 + : 41'h0) + | ({_GEN_24, _cfiIndex_bits_T_324} == 2'h0 & _predictors_io_out_s2_full_pred_3_hit + ? _predictors_io_out_s2_full_pred_3_fallThroughAddr + : 41'h0) + | (_predictors_io_out_s2_full_pred_3_hit + ? 41'h0 + : _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_T_6)), + .s1_target_sel + (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 + & ~do_redirect_dup_next_valid_last_r), + .s1_target_src + ((s1_pred_info_takenMask_3_0 & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_targets_0 + : 41'h0) + | (~s1_pred_info_takenMask_3_0 & s1_pred_info_takenMask_3_1 + & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_targets_1 + : 41'h0) + | ({s1_pred_info_takenMask_3_1, s1_pred_info_takenMask_3_0} == 2'h0 + & _predictors_io_out_s1_full_pred_3_hit + ? _predictors_io_out_s1_full_pred_3_fallThroughAddr + : 41'h0) | _GEN_7), + .s3_target_sel (s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), + .s3_target_src + ((_s3_redirect_on_jalr_target_dup_T_68 & _predictors_io_out_s3_full_pred_3_hit + ? _predictors_io_out_s3_full_pred_3_targets_0 + : 41'h0) + | (~_s3_redirect_on_jalr_target_dup_T_68 & _GEN_35 + & _predictors_io_out_s3_full_pred_3_hit + ? _predictors_io_out_s3_full_pred_3_targets_1 + : 41'h0) + | ({_GEN_35, _s3_redirect_on_jalr_target_dup_T_68} == 2'h0 + & _predictors_io_out_s3_full_pred_3_hit + ? _predictors_io_out_s3_full_pred_3_fallThroughAddr + : 41'h0) + | (_predictors_io_out_s3_full_pred_3_hit + ? 41'h0 + : _s3_redirect_on_target_dup_T_47)), + .redirect_target_sel (do_redirect_dup_next_valid_last_r), + .redirect_target_src (do_redirect_dup_next_bits_r_cfiUpdate_target), + .stallPC_src (s0_pc_reg_dup_3), + .out_res (_s0_pc_dup_3_ppm_out_res) + ); + PriorityMuxModule_4 s0_folded_gh_dup_1_ppm ( + .s2_FGH_sel + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), + .s2_FGH_src_hist_17_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_17_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_93 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_17_folded_hist[9], + s2_folded_gh_dup_1_hist_17_folded_hist[8:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_17_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_T_121 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s2_folded_gh_dup_1_hist_17_folded_hist[8], + s2_folded_gh_dup_1_hist_17_folded_hist[7:0], + s2_folded_gh_dup_1_hist_17_folded_hist[10], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_17_folded_hist[9]} + : 11'h0)), + .s2_FGH_src_hist_16_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_16_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_16_folded_hist[9], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s2_folded_gh_dup_1_hist_16_folded_hist[8], + s2_folded_gh_dup_1_hist_16_folded_hist[7:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_16_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_T_121 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s2_folded_gh_dup_1_hist_16_folded_hist[8], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s2_folded_gh_dup_1_hist_16_folded_hist[7], + s2_folded_gh_dup_1_hist_16_folded_hist[6:0], + s2_folded_gh_dup_1_hist_16_folded_hist[10], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_16_folded_hist[9]} + : 11'h0)), + .s2_FGH_src_hist_15_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_15_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_93 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_15_folded_hist[5], + s2_folded_gh_dup_1_hist_15_folded_hist[4:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_15_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_T_121 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s2_folded_gh_dup_1_hist_15_folded_hist[4], + s2_folded_gh_dup_1_hist_15_folded_hist[3:0], + s2_folded_gh_dup_1_hist_15_folded_hist[6], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_15_folded_hist[5]} + : 7'h0)), + .s2_FGH_src_hist_14_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_14_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_14_folded_hist[6:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0} + : 8'h0) + | (_s2_predicted_fh_dup_T_121 + ? {s2_folded_gh_dup_1_hist_14_folded_hist[5:0], + 1'h0, + _predictors_io_out_s2_full_pred_1_br_taken_mask_1} + : 8'h0)), + .s2_FGH_src_hist_13_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_13_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_13_folded_hist[7:4], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_13_folded_hist[3], + s2_folded_gh_dup_1_hist_13_folded_hist[2:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_13_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_T_121 + ? {s2_folded_gh_dup_1_hist_13_folded_hist[6:4], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_13_folded_hist[3], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s2_folded_gh_dup_1_hist_13_folded_hist[2], + s2_folded_gh_dup_1_hist_13_folded_hist[1:0], + s2_folded_gh_dup_1_hist_13_folded_hist[8], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_13_folded_hist[7]} + : 9'h0)), + .s2_FGH_src_hist_12_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_12_folded_hist : 4'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_12_folded_hist[2:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0} + : 4'h0) + | (_s2_predicted_fh_dup_T_121 + ? {s2_folded_gh_dup_1_hist_12_folded_hist[1:0], + 1'h0, + _predictors_io_out_s2_full_pred_1_br_taken_mask_1} + : 4'h0)), + .s2_FGH_src_hist_11_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_11_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_11_folded_hist[6:2], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2) + ^ s2_folded_gh_dup_1_hist_11_folded_hist[1], + s2_folded_gh_dup_1_hist_11_folded_hist[0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_11_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_121 + ? {s2_folded_gh_dup_1_hist_11_folded_hist[5:2], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2) + ^ s2_folded_gh_dup_1_hist_11_folded_hist[1], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3) + ^ s2_folded_gh_dup_1_hist_11_folded_hist[0], + s2_folded_gh_dup_1_hist_11_folded_hist[7], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_11_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_10_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_10_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_10_folded_hist[7:5], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_10_folded_hist[4], + s2_folded_gh_dup_1_hist_10_folded_hist[3:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_10_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_T_121 + ? {s2_folded_gh_dup_1_hist_10_folded_hist[6:5], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_10_folded_hist[4], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s2_folded_gh_dup_1_hist_10_folded_hist[3], + s2_folded_gh_dup_1_hist_10_folded_hist[2:0], + s2_folded_gh_dup_1_hist_10_folded_hist[8], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_10_folded_hist[7]} + : 9'h0)), + .s2_FGH_src_hist_9_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_9_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_9_folded_hist[5:4], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_9_folded_hist[3], + s2_folded_gh_dup_1_hist_9_folded_hist[2:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_9_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_T_121 + ? {s2_folded_gh_dup_1_hist_9_folded_hist[4], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_9_folded_hist[3], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s2_folded_gh_dup_1_hist_9_folded_hist[2], + s2_folded_gh_dup_1_hist_9_folded_hist[1:0], + s2_folded_gh_dup_1_hist_9_folded_hist[6], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_9_folded_hist[5]} + : 7'h0)), + .s2_FGH_src_hist_8_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_8_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s2_folded_gh_dup_1_hist_8_folded_hist[6], + s2_folded_gh_dup_1_hist_8_folded_hist[5:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_8_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_121 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s2_folded_gh_dup_1_hist_8_folded_hist[5], + s2_folded_gh_dup_1_hist_8_folded_hist[4:0], + s2_folded_gh_dup_1_hist_8_folded_hist[7], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s2_folded_gh_dup_1_hist_8_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_7_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_7_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_7_folded_hist[5:1], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) + ^ s2_folded_gh_dup_1_hist_7_folded_hist[0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_7_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_T_121 + ? {s2_folded_gh_dup_1_hist_7_folded_hist[4:1], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) + ^ s2_folded_gh_dup_1_hist_7_folded_hist[0], + 1'h0, + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_7_folded_hist[5]} + : 7'h0)), + .s2_FGH_src_hist_6_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_6_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_6_folded_hist[7], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s2_folded_gh_dup_1_hist_6_folded_hist[6], + s2_folded_gh_dup_1_hist_6_folded_hist[5:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_6_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_T_121 + ? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s2_folded_gh_dup_1_hist_6_folded_hist[6], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) + ^ s2_folded_gh_dup_1_hist_6_folded_hist[5], + s2_folded_gh_dup_1_hist_6_folded_hist[4:0], + s2_folded_gh_dup_1_hist_6_folded_hist[8], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_6_folded_hist[7]} + : 9'h0)), + .s2_FGH_src_hist_5_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_5_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_5_folded_hist[5:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s2_folded_gh_dup_1_hist_5_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_T_121 + ? {s2_folded_gh_dup_1_hist_5_folded_hist[4:0], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s2_folded_gh_dup_1_hist_5_folded_hist[6], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s2_folded_gh_dup_1_hist_5_folded_hist[5]} + : 7'h0)), + .s2_FGH_src_hist_4_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_4_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_4_folded_hist[6:5], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_4_folded_hist[4], + s2_folded_gh_dup_1_hist_4_folded_hist[3:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_4_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_121 + ? {s2_folded_gh_dup_1_hist_4_folded_hist[5], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_4_folded_hist[4], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s2_folded_gh_dup_1_hist_4_folded_hist[3], + s2_folded_gh_dup_1_hist_4_folded_hist[2:0], + s2_folded_gh_dup_1_hist_4_folded_hist[7], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_4_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_3_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_3_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_3_folded_hist[6:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_3_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_121 + ? {s2_folded_gh_dup_1_hist_3_folded_hist[5:0], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s2_folded_gh_dup_1_hist_3_folded_hist[7], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s2_folded_gh_dup_1_hist_3_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_2_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_2_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_2_folded_hist[6:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s2_folded_gh_dup_1_hist_2_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_121 + ? {s2_folded_gh_dup_1_hist_2_folded_hist[5:0], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s2_folded_gh_dup_1_hist_2_folded_hist[7], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_1[0] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) + ^ s2_folded_gh_dup_1_hist_2_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_1_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_1_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_1_folded_hist[9:2], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_1_folded_hist[1], + s2_folded_gh_dup_1_hist_1_folded_hist[0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0 + ^ s2_folded_gh_dup_1_hist_1_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_T_121 + ? {s2_folded_gh_dup_1_hist_1_folded_hist[8:2], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s2_folded_gh_dup_1_hist_1_folded_hist[1], + (s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s2_last_br_num_oh_dup_1[1] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s2_last_br_num_oh_dup_1[2] + & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s2_folded_gh_dup_1_hist_1_folded_hist[0], + s2_folded_gh_dup_1_hist_1_folded_hist[10], + _predictors_io_out_s2_full_pred_1_br_taken_mask_1 + ^ s2_folded_gh_dup_1_hist_1_folded_hist[9]} + : 11'h0)), + .s2_FGH_src_hist_0_folded_hist + ((_s2_predicted_fh_dup_T_65 ? s2_folded_gh_dup_1_hist_0_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_93 + ? {s2_folded_gh_dup_1_hist_0_folded_hist[6:0], + _predictors_io_out_s2_full_pred_1_br_taken_mask_0} + : 8'h0) + | (_s2_predicted_fh_dup_T_121 + ? {s2_folded_gh_dup_1_hist_0_folded_hist[5:0], + 1'h0, + _predictors_io_out_s2_full_pred_1_br_taken_mask_1} + : 8'h0)), + .s1_FGH_sel + (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 + & ~do_redirect_dup_next_valid_last_r), + .s1_FGH_src_hist_17_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_17_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_93 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_17_folded_hist[9], + s1_folded_gh_dup_1_hist_17_folded_hist[8:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ s1_folded_gh_dup_1_hist_17_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_T_121 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s1_folded_gh_dup_1_hist_17_folded_hist[8], + s1_folded_gh_dup_1_hist_17_folded_hist[7:0], + s1_folded_gh_dup_1_hist_17_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_17_folded_hist[9]} + : 11'h0)), + .s1_FGH_src_hist_16_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_16_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_16_folded_hist[9], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s1_folded_gh_dup_1_hist_16_folded_hist[8], + s1_folded_gh_dup_1_hist_16_folded_hist[7:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ s1_folded_gh_dup_1_hist_16_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_T_121 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s1_folded_gh_dup_1_hist_16_folded_hist[8], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s1_folded_gh_dup_1_hist_16_folded_hist[7], + s1_folded_gh_dup_1_hist_16_folded_hist[6:0], + s1_folded_gh_dup_1_hist_16_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ s1_folded_gh_dup_1_hist_16_folded_hist[9]} + : 11'h0)), + .s1_FGH_src_hist_15_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_15_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_93 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_15_folded_hist[5], + s1_folded_gh_dup_1_hist_15_folded_hist[4:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ s1_folded_gh_dup_1_hist_15_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_T_121 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s1_folded_gh_dup_1_hist_15_folded_hist[4], + s1_folded_gh_dup_1_hist_15_folded_hist[3:0], + s1_folded_gh_dup_1_hist_15_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_15_folded_hist[5]} + : 7'h0)), + .s1_FGH_src_hist_14_folded_hist + ((_s1_predicted_fh_dup_T_65 + ? {s1_folded_gh_dup_1_hist_14_folded_hist[7:1], + s1_folded_gh_dup_1_hist_14_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_271} + : 8'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_14_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8} + : 8'h0) + | (_s1_predicted_fh_dup_T_121 + ? {s1_folded_gh_dup_1_hist_14_folded_hist[5:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11} + : 8'h0)), + .s1_FGH_src_hist_13_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_13_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_13_folded_hist[7:4], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_13_folded_hist[3], + s1_folded_gh_dup_1_hist_13_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ s1_folded_gh_dup_1_hist_13_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_T_121 + ? {s1_folded_gh_dup_1_hist_13_folded_hist[6:4], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_13_folded_hist[3], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s1_folded_gh_dup_1_hist_13_folded_hist[2], + s1_folded_gh_dup_1_hist_13_folded_hist[1:0], + s1_folded_gh_dup_1_hist_13_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ s1_folded_gh_dup_1_hist_13_folded_hist[7]} + : 9'h0)), + .s1_FGH_src_hist_12_folded_hist + ((_s1_predicted_fh_dup_T_65 + ? {s1_folded_gh_dup_1_hist_12_folded_hist[3:1], + s1_folded_gh_dup_1_hist_12_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_271} + : 4'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_12_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8} + : 4'h0) + | (_s1_predicted_fh_dup_T_121 + ? {s1_folded_gh_dup_1_hist_12_folded_hist[1:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11} + : 4'h0)), + .s1_FGH_src_hist_11_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_11_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_11_folded_hist[6:2], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2) + ^ s1_folded_gh_dup_1_hist_11_folded_hist[1], + s1_folded_gh_dup_1_hist_11_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ s1_folded_gh_dup_1_hist_11_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_121 + ? {s1_folded_gh_dup_1_hist_11_folded_hist[5:2], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2) + ^ s1_folded_gh_dup_1_hist_11_folded_hist[1], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3) + ^ s1_folded_gh_dup_1_hist_11_folded_hist[0], + s1_folded_gh_dup_1_hist_11_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ s1_folded_gh_dup_1_hist_11_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_10_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_10_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_10_folded_hist[7:5], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_10_folded_hist[4], + s1_folded_gh_dup_1_hist_10_folded_hist[3:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ s1_folded_gh_dup_1_hist_10_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_T_121 + ? {s1_folded_gh_dup_1_hist_10_folded_hist[6:5], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_10_folded_hist[4], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s1_folded_gh_dup_1_hist_10_folded_hist[3], + s1_folded_gh_dup_1_hist_10_folded_hist[2:0], + s1_folded_gh_dup_1_hist_10_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ s1_folded_gh_dup_1_hist_10_folded_hist[7]} + : 9'h0)), + .s1_FGH_src_hist_9_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_9_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_9_folded_hist[5:4], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_9_folded_hist[3], + s1_folded_gh_dup_1_hist_9_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ s1_folded_gh_dup_1_hist_9_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_T_121 + ? {s1_folded_gh_dup_1_hist_9_folded_hist[4], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_9_folded_hist[3], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s1_folded_gh_dup_1_hist_9_folded_hist[2], + s1_folded_gh_dup_1_hist_9_folded_hist[1:0], + s1_folded_gh_dup_1_hist_9_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ s1_folded_gh_dup_1_hist_9_folded_hist[5]} + : 7'h0)), + .s1_FGH_src_hist_8_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_8_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_93 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s1_folded_gh_dup_1_hist_8_folded_hist[6], + s1_folded_gh_dup_1_hist_8_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ s1_folded_gh_dup_1_hist_8_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_121 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s1_folded_gh_dup_1_hist_8_folded_hist[5], + s1_folded_gh_dup_1_hist_8_folded_hist[4:0], + s1_folded_gh_dup_1_hist_8_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s1_folded_gh_dup_1_hist_8_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_7_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_7_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_7_folded_hist[5:1], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) + ^ s1_folded_gh_dup_1_hist_7_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ s1_folded_gh_dup_1_hist_7_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_T_121 + ? {s1_folded_gh_dup_1_hist_7_folded_hist[4:1], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) + ^ s1_folded_gh_dup_1_hist_7_folded_hist[0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ s1_folded_gh_dup_1_hist_7_folded_hist[5]} + : 7'h0)), + .s1_FGH_src_hist_6_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_6_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_6_folded_hist[7], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s1_folded_gh_dup_1_hist_6_folded_hist[6], + s1_folded_gh_dup_1_hist_6_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ s1_folded_gh_dup_1_hist_6_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_T_121 + ? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s1_folded_gh_dup_1_hist_6_folded_hist[6], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) + ^ s1_folded_gh_dup_1_hist_6_folded_hist[5], + s1_folded_gh_dup_1_hist_6_folded_hist[4:0], + s1_folded_gh_dup_1_hist_6_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ s1_folded_gh_dup_1_hist_6_folded_hist[7]} + : 9'h0)), + .s1_FGH_src_hist_5_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_5_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_5_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s1_folded_gh_dup_1_hist_5_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_T_121 + ? {s1_folded_gh_dup_1_hist_5_folded_hist[4:0], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s1_folded_gh_dup_1_hist_5_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s1_folded_gh_dup_1_hist_5_folded_hist[5]} + : 7'h0)), + .s1_FGH_src_hist_4_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_4_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_4_folded_hist[6:5], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_4_folded_hist[4], + s1_folded_gh_dup_1_hist_4_folded_hist[3:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ s1_folded_gh_dup_1_hist_4_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_121 + ? {s1_folded_gh_dup_1_hist_4_folded_hist[5], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_4_folded_hist[4], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s1_folded_gh_dup_1_hist_4_folded_hist[3], + s1_folded_gh_dup_1_hist_4_folded_hist[2:0], + s1_folded_gh_dup_1_hist_4_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ s1_folded_gh_dup_1_hist_4_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_3_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_3_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_3_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_3_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_121 + ? {s1_folded_gh_dup_1_hist_3_folded_hist[5:0], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s1_folded_gh_dup_1_hist_3_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s1_folded_gh_dup_1_hist_3_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_2_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_2_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_2_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s1_folded_gh_dup_1_hist_2_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_121 + ? {s1_folded_gh_dup_1_hist_2_folded_hist[5:0], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s1_folded_gh_dup_1_hist_2_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ (s1_last_br_num_oh_dup_1[0] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) + ^ s1_folded_gh_dup_1_hist_2_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_1_folded_hist + ((_s1_predicted_fh_dup_T_65 ? s1_folded_gh_dup_1_hist_1_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_1_folded_hist[9:2], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_1_folded_hist[1], + s1_folded_gh_dup_1_hist_1_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8 + ^ s1_folded_gh_dup_1_hist_1_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_T_121 + ? {s1_folded_gh_dup_1_hist_1_folded_hist[8:2], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s1_folded_gh_dup_1_hist_1_folded_hist[1], + (s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s1_last_br_num_oh_dup_1[1] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s1_last_br_num_oh_dup_1[2] + & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s1_folded_gh_dup_1_hist_1_folded_hist[0], + s1_folded_gh_dup_1_hist_1_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11 + ^ s1_folded_gh_dup_1_hist_1_folded_hist[9]} + : 11'h0)), + .s1_FGH_src_hist_0_folded_hist + ((_s1_predicted_fh_dup_T_65 + ? {s1_folded_gh_dup_1_hist_0_folded_hist[7:1], + s1_folded_gh_dup_1_hist_0_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_271} + : 8'h0) + | (_s1_predicted_fh_dup_T_93 + ? {s1_folded_gh_dup_1_hist_0_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_8} + : 8'h0) + | (_s1_predicted_fh_dup_T_121 + ? {s1_folded_gh_dup_1_hist_0_folded_hist[5:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_11} + : 8'h0)), + .s3_FGH_sel + (s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), + .s3_FGH_src_hist_17_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_17_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_93 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_17_folded_hist[9], + s3_folded_gh_dup_1_hist_17_folded_hist[8:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_17_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_T_121 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s3_folded_gh_dup_1_hist_17_folded_hist[8], + s3_folded_gh_dup_1_hist_17_folded_hist[7:0], + s3_folded_gh_dup_1_hist_17_folded_hist[10], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_17_folded_hist[9]} + : 11'h0)), + .s3_FGH_src_hist_16_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_16_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_16_folded_hist[9], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s3_folded_gh_dup_1_hist_16_folded_hist[8], + s3_folded_gh_dup_1_hist_16_folded_hist[7:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_16_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_T_121 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s3_folded_gh_dup_1_hist_16_folded_hist[8], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s3_folded_gh_dup_1_hist_16_folded_hist[7], + s3_folded_gh_dup_1_hist_16_folded_hist[6:0], + s3_folded_gh_dup_1_hist_16_folded_hist[10], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_16_folded_hist[9]} + : 11'h0)), + .s3_FGH_src_hist_15_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_15_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_93 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_15_folded_hist[5], + s3_folded_gh_dup_1_hist_15_folded_hist[4:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_15_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_T_121 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s3_folded_gh_dup_1_hist_15_folded_hist[4], + s3_folded_gh_dup_1_hist_15_folded_hist[3:0], + s3_folded_gh_dup_1_hist_15_folded_hist[6], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_15_folded_hist[5]} + : 7'h0)), + .s3_FGH_src_hist_14_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_14_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_14_folded_hist[6:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0} + : 8'h0) + | (_s3_predicted_fh_dup_T_121 + ? {s3_folded_gh_dup_1_hist_14_folded_hist[5:0], + 1'h0, + _predictors_io_out_s3_full_pred_1_br_taken_mask_1} + : 8'h0)), + .s3_FGH_src_hist_13_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_13_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_13_folded_hist[7:4], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_13_folded_hist[3], + s3_folded_gh_dup_1_hist_13_folded_hist[2:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_13_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_T_121 + ? {s3_folded_gh_dup_1_hist_13_folded_hist[6:4], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_13_folded_hist[3], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s3_folded_gh_dup_1_hist_13_folded_hist[2], + s3_folded_gh_dup_1_hist_13_folded_hist[1:0], + s3_folded_gh_dup_1_hist_13_folded_hist[8], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_13_folded_hist[7]} + : 9'h0)), + .s3_FGH_src_hist_12_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_12_folded_hist : 4'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_12_folded_hist[2:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0} + : 4'h0) + | (_s3_predicted_fh_dup_T_121 + ? {s3_folded_gh_dup_1_hist_12_folded_hist[1:0], + 1'h0, + _predictors_io_out_s3_full_pred_1_br_taken_mask_1} + : 4'h0)), + .s3_FGH_src_hist_11_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_11_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_11_folded_hist[6:2], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2) + ^ s3_folded_gh_dup_1_hist_11_folded_hist[1], + s3_folded_gh_dup_1_hist_11_folded_hist[0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_11_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_121 + ? {s3_folded_gh_dup_1_hist_11_folded_hist[5:2], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2) + ^ s3_folded_gh_dup_1_hist_11_folded_hist[1], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3) + ^ s3_folded_gh_dup_1_hist_11_folded_hist[0], + s3_folded_gh_dup_1_hist_11_folded_hist[7], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_11_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_10_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_10_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_10_folded_hist[7:5], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_10_folded_hist[4], + s3_folded_gh_dup_1_hist_10_folded_hist[3:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_10_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_T_121 + ? {s3_folded_gh_dup_1_hist_10_folded_hist[6:5], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_10_folded_hist[4], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s3_folded_gh_dup_1_hist_10_folded_hist[3], + s3_folded_gh_dup_1_hist_10_folded_hist[2:0], + s3_folded_gh_dup_1_hist_10_folded_hist[8], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_10_folded_hist[7]} + : 9'h0)), + .s3_FGH_src_hist_9_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_9_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_9_folded_hist[5:4], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_9_folded_hist[3], + s3_folded_gh_dup_1_hist_9_folded_hist[2:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_9_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_T_121 + ? {s3_folded_gh_dup_1_hist_9_folded_hist[4], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_9_folded_hist[3], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s3_folded_gh_dup_1_hist_9_folded_hist[2], + s3_folded_gh_dup_1_hist_9_folded_hist[1:0], + s3_folded_gh_dup_1_hist_9_folded_hist[6], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_9_folded_hist[5]} + : 7'h0)), + .s3_FGH_src_hist_8_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_8_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s3_folded_gh_dup_1_hist_8_folded_hist[6], + s3_folded_gh_dup_1_hist_8_folded_hist[5:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_8_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_121 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s3_folded_gh_dup_1_hist_8_folded_hist[5], + s3_folded_gh_dup_1_hist_8_folded_hist[4:0], + s3_folded_gh_dup_1_hist_8_folded_hist[7], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s3_folded_gh_dup_1_hist_8_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_7_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_7_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_7_folded_hist[5:1], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) + ^ s3_folded_gh_dup_1_hist_7_folded_hist[0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_7_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_T_121 + ? {s3_folded_gh_dup_1_hist_7_folded_hist[4:1], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2) + ^ s3_folded_gh_dup_1_hist_7_folded_hist[0], + 1'h0, + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_7_folded_hist[5]} + : 7'h0)), + .s3_FGH_src_hist_6_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_6_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_6_folded_hist[7], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s3_folded_gh_dup_1_hist_6_folded_hist[6], + s3_folded_gh_dup_1_hist_6_folded_hist[5:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_6_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_T_121 + ? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s3_folded_gh_dup_1_hist_6_folded_hist[6], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) + ^ s3_folded_gh_dup_1_hist_6_folded_hist[5], + s3_folded_gh_dup_1_hist_6_folded_hist[4:0], + s3_folded_gh_dup_1_hist_6_folded_hist[8], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_6_folded_hist[7]} + : 9'h0)), + .s3_FGH_src_hist_5_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_5_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_5_folded_hist[5:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s3_folded_gh_dup_1_hist_5_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_T_121 + ? {s3_folded_gh_dup_1_hist_5_folded_hist[4:0], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2) + ^ s3_folded_gh_dup_1_hist_5_folded_hist[6], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3) + ^ s3_folded_gh_dup_1_hist_5_folded_hist[5]} + : 7'h0)), + .s3_FGH_src_hist_4_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_4_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_4_folded_hist[6:5], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_4_folded_hist[4], + s3_folded_gh_dup_1_hist_4_folded_hist[3:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_4_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_121 + ? {s3_folded_gh_dup_1_hist_4_folded_hist[5], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_4_folded_hist[4], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s3_folded_gh_dup_1_hist_4_folded_hist[3], + s3_folded_gh_dup_1_hist_4_folded_hist[2:0], + s3_folded_gh_dup_1_hist_4_folded_hist[7], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_4_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_3_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_3_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_3_folded_hist[6:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_3_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_121 + ? {s3_folded_gh_dup_1_hist_3_folded_hist[5:0], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2) + ^ s3_folded_gh_dup_1_hist_3_folded_hist[7], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3) + ^ s3_folded_gh_dup_1_hist_3_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_2_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_2_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_2_folded_hist[6:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s3_folded_gh_dup_1_hist_2_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_121 + ? {s3_folded_gh_dup_1_hist_2_folded_hist[5:0], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2) + ^ s3_folded_gh_dup_1_hist_2_folded_hist[7], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_1[0] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3) + ^ s3_folded_gh_dup_1_hist_2_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_1_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_1_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_1_folded_hist[9:2], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_1_folded_hist[1], + s3_folded_gh_dup_1_hist_1_folded_hist[0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0 + ^ s3_folded_gh_dup_1_hist_1_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_T_121 + ? {s3_folded_gh_dup_1_hist_1_folded_hist[8:2], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2) + ^ s3_folded_gh_dup_1_hist_1_folded_hist[1], + (s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 + | s3_last_br_num_oh_dup_1[1] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 + | s3_last_br_num_oh_dup_1[2] + & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3) + ^ s3_folded_gh_dup_1_hist_1_folded_hist[0], + s3_folded_gh_dup_1_hist_1_folded_hist[10], + _predictors_io_out_s3_full_pred_1_br_taken_mask_1 + ^ s3_folded_gh_dup_1_hist_1_folded_hist[9]} + : 11'h0)), + .s3_FGH_src_hist_0_folded_hist + ((_s3_predicted_fh_dup_T_65 ? s3_folded_gh_dup_1_hist_0_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_93 + ? {s3_folded_gh_dup_1_hist_0_folded_hist[6:0], + _predictors_io_out_s3_full_pred_1_br_taken_mask_0} + : 8'h0) + | (_s3_predicted_fh_dup_T_121 + ? {s3_folded_gh_dup_1_hist_0_folded_hist[5:0], + 1'h0, + _predictors_io_out_s3_full_pred_1_br_taken_mask_1} + : 8'h0)), + .redirect_FGHT_sel (do_redirect_dup_next_valid_last_r), + .redirect_FGHT_src_hist_17_folded_hist + (_GEN_45[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_16_folded_hist + (_GEN_46[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_15_folded_hist + (_GEN_47[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_14_folded_hist + (_GEN_48[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_13_folded_hist + (_GEN_49[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_12_folded_hist + (_GEN_50[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_11_folded_hist + (_GEN_51[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_10_folded_hist + (_GEN_52[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_9_folded_hist + (_GEN_53[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_8_folded_hist + (_GEN_54[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_7_folded_hist + (_GEN_55[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_6_folded_hist + (_GEN_56[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_5_folded_hist + (_GEN_57[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_4_folded_hist + (_GEN_58[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_3_folded_hist + (_GEN_59[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_2_folded_hist + (_GEN_60[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_1_folded_hist + (_GEN_61[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_0_folded_hist + (_GEN_62[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_1_hist_17_folded_hist), + .stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_1_hist_16_folded_hist), + .stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_1_hist_15_folded_hist), + .stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_1_hist_14_folded_hist), + .stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_1_hist_13_folded_hist), + .stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_1_hist_12_folded_hist), + .stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_1_hist_11_folded_hist), + .stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_1_hist_10_folded_hist), + .stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_1_hist_9_folded_hist), + .stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_1_hist_8_folded_hist), + .stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_1_hist_7_folded_hist), + .stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_1_hist_6_folded_hist), + .stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_1_hist_5_folded_hist), + .stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_1_hist_4_folded_hist), + .stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_1_hist_3_folded_hist), + .stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_1_hist_2_folded_hist), + .stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_1_hist_1_folded_hist), + .stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_1_hist_0_folded_hist), + .out_res_hist_17_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist), + .out_res_hist_16_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist), + .out_res_hist_15_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist), + .out_res_hist_14_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist), + .out_res_hist_13_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist), + .out_res_hist_12_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist), + .out_res_hist_11_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist), + .out_res_hist_10_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist), + .out_res_hist_9_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist), + .out_res_hist_8_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist), + .out_res_hist_7_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist), + .out_res_hist_6_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist), + .out_res_hist_5_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist), + .out_res_hist_4_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist), + .out_res_hist_3_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist), + .out_res_hist_2_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist), + .out_res_hist_1_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist), + .out_res_hist_0_folded_hist + (_s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist) + ); + PriorityMuxModule_4 s0_folded_gh_dup_2_ppm ( + .s2_FGH_sel + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), + .s2_FGH_src_hist_17_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_17_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_154 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_17_folded_hist[9], + s2_folded_gh_dup_2_hist_17_folded_hist[8:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_17_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_T_182 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s2_folded_gh_dup_2_hist_17_folded_hist[8], + s2_folded_gh_dup_2_hist_17_folded_hist[7:0], + s2_folded_gh_dup_2_hist_17_folded_hist[10], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_17_folded_hist[9]} + : 11'h0)), + .s2_FGH_src_hist_16_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_16_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_16_folded_hist[9], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s2_folded_gh_dup_2_hist_16_folded_hist[8], + s2_folded_gh_dup_2_hist_16_folded_hist[7:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_16_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_T_182 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s2_folded_gh_dup_2_hist_16_folded_hist[8], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s2_folded_gh_dup_2_hist_16_folded_hist[7], + s2_folded_gh_dup_2_hist_16_folded_hist[6:0], + s2_folded_gh_dup_2_hist_16_folded_hist[10], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_16_folded_hist[9]} + : 11'h0)), + .s2_FGH_src_hist_15_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_15_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_154 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_15_folded_hist[5], + s2_folded_gh_dup_2_hist_15_folded_hist[4:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_15_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_T_182 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s2_folded_gh_dup_2_hist_15_folded_hist[4], + s2_folded_gh_dup_2_hist_15_folded_hist[3:0], + s2_folded_gh_dup_2_hist_15_folded_hist[6], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_15_folded_hist[5]} + : 7'h0)), + .s2_FGH_src_hist_14_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_14_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_14_folded_hist[6:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0} + : 8'h0) + | (_s2_predicted_fh_dup_T_182 + ? {s2_folded_gh_dup_2_hist_14_folded_hist[5:0], + 1'h0, + _predictors_io_out_s2_full_pred_2_br_taken_mask_1} + : 8'h0)), + .s2_FGH_src_hist_13_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_13_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_13_folded_hist[7:4], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_13_folded_hist[3], + s2_folded_gh_dup_2_hist_13_folded_hist[2:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_13_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_T_182 + ? {s2_folded_gh_dup_2_hist_13_folded_hist[6:4], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_13_folded_hist[3], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s2_folded_gh_dup_2_hist_13_folded_hist[2], + s2_folded_gh_dup_2_hist_13_folded_hist[1:0], + s2_folded_gh_dup_2_hist_13_folded_hist[8], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_13_folded_hist[7]} + : 9'h0)), + .s2_FGH_src_hist_12_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_12_folded_hist : 4'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_12_folded_hist[2:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0} + : 4'h0) + | (_s2_predicted_fh_dup_T_182 + ? {s2_folded_gh_dup_2_hist_12_folded_hist[1:0], + 1'h0, + _predictors_io_out_s2_full_pred_2_br_taken_mask_1} + : 4'h0)), + .s2_FGH_src_hist_11_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_11_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_11_folded_hist[6:2], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2) + ^ s2_folded_gh_dup_2_hist_11_folded_hist[1], + s2_folded_gh_dup_2_hist_11_folded_hist[0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_11_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_182 + ? {s2_folded_gh_dup_2_hist_11_folded_hist[5:2], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2) + ^ s2_folded_gh_dup_2_hist_11_folded_hist[1], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3) + ^ s2_folded_gh_dup_2_hist_11_folded_hist[0], + s2_folded_gh_dup_2_hist_11_folded_hist[7], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_11_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_10_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_10_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_10_folded_hist[7:5], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_10_folded_hist[4], + s2_folded_gh_dup_2_hist_10_folded_hist[3:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_10_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_T_182 + ? {s2_folded_gh_dup_2_hist_10_folded_hist[6:5], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_10_folded_hist[4], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s2_folded_gh_dup_2_hist_10_folded_hist[3], + s2_folded_gh_dup_2_hist_10_folded_hist[2:0], + s2_folded_gh_dup_2_hist_10_folded_hist[8], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_10_folded_hist[7]} + : 9'h0)), + .s2_FGH_src_hist_9_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_9_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_9_folded_hist[5:4], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_9_folded_hist[3], + s2_folded_gh_dup_2_hist_9_folded_hist[2:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_9_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_T_182 + ? {s2_folded_gh_dup_2_hist_9_folded_hist[4], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_9_folded_hist[3], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s2_folded_gh_dup_2_hist_9_folded_hist[2], + s2_folded_gh_dup_2_hist_9_folded_hist[1:0], + s2_folded_gh_dup_2_hist_9_folded_hist[6], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_9_folded_hist[5]} + : 7'h0)), + .s2_FGH_src_hist_8_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_8_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s2_folded_gh_dup_2_hist_8_folded_hist[6], + s2_folded_gh_dup_2_hist_8_folded_hist[5:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_8_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_182 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s2_folded_gh_dup_2_hist_8_folded_hist[5], + s2_folded_gh_dup_2_hist_8_folded_hist[4:0], + s2_folded_gh_dup_2_hist_8_folded_hist[7], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s2_folded_gh_dup_2_hist_8_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_7_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_7_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_7_folded_hist[5:1], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) + ^ s2_folded_gh_dup_2_hist_7_folded_hist[0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_7_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_T_182 + ? {s2_folded_gh_dup_2_hist_7_folded_hist[4:1], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) + ^ s2_folded_gh_dup_2_hist_7_folded_hist[0], + 1'h0, + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_7_folded_hist[5]} + : 7'h0)), + .s2_FGH_src_hist_6_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_6_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_6_folded_hist[7], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s2_folded_gh_dup_2_hist_6_folded_hist[6], + s2_folded_gh_dup_2_hist_6_folded_hist[5:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_6_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_T_182 + ? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s2_folded_gh_dup_2_hist_6_folded_hist[6], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) + ^ s2_folded_gh_dup_2_hist_6_folded_hist[5], + s2_folded_gh_dup_2_hist_6_folded_hist[4:0], + s2_folded_gh_dup_2_hist_6_folded_hist[8], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_6_folded_hist[7]} + : 9'h0)), + .s2_FGH_src_hist_5_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_5_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_5_folded_hist[5:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s2_folded_gh_dup_2_hist_5_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_T_182 + ? {s2_folded_gh_dup_2_hist_5_folded_hist[4:0], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s2_folded_gh_dup_2_hist_5_folded_hist[6], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s2_folded_gh_dup_2_hist_5_folded_hist[5]} + : 7'h0)), + .s2_FGH_src_hist_4_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_4_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_4_folded_hist[6:5], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_4_folded_hist[4], + s2_folded_gh_dup_2_hist_4_folded_hist[3:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_4_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_182 + ? {s2_folded_gh_dup_2_hist_4_folded_hist[5], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_4_folded_hist[4], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s2_folded_gh_dup_2_hist_4_folded_hist[3], + s2_folded_gh_dup_2_hist_4_folded_hist[2:0], + s2_folded_gh_dup_2_hist_4_folded_hist[7], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_4_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_3_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_3_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_3_folded_hist[6:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_3_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_182 + ? {s2_folded_gh_dup_2_hist_3_folded_hist[5:0], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s2_folded_gh_dup_2_hist_3_folded_hist[7], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s2_folded_gh_dup_2_hist_3_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_2_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_2_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_2_folded_hist[6:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s2_folded_gh_dup_2_hist_2_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_182 + ? {s2_folded_gh_dup_2_hist_2_folded_hist[5:0], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s2_folded_gh_dup_2_hist_2_folded_hist[7], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_2[0] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) + ^ s2_folded_gh_dup_2_hist_2_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_1_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_1_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_1_folded_hist[9:2], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_1_folded_hist[1], + s2_folded_gh_dup_2_hist_1_folded_hist[0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0 + ^ s2_folded_gh_dup_2_hist_1_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_T_182 + ? {s2_folded_gh_dup_2_hist_1_folded_hist[8:2], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s2_folded_gh_dup_2_hist_1_folded_hist[1], + (s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s2_last_br_num_oh_dup_2[1] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s2_last_br_num_oh_dup_2[2] + & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s2_folded_gh_dup_2_hist_1_folded_hist[0], + s2_folded_gh_dup_2_hist_1_folded_hist[10], + _predictors_io_out_s2_full_pred_2_br_taken_mask_1 + ^ s2_folded_gh_dup_2_hist_1_folded_hist[9]} + : 11'h0)), + .s2_FGH_src_hist_0_folded_hist + ((_s2_predicted_fh_dup_T_126 ? s2_folded_gh_dup_2_hist_0_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_154 + ? {s2_folded_gh_dup_2_hist_0_folded_hist[6:0], + _predictors_io_out_s2_full_pred_2_br_taken_mask_0} + : 8'h0) + | (_s2_predicted_fh_dup_T_182 + ? {s2_folded_gh_dup_2_hist_0_folded_hist[5:0], + 1'h0, + _predictors_io_out_s2_full_pred_2_br_taken_mask_1} + : 8'h0)), + .s1_FGH_sel + (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 + & ~do_redirect_dup_next_valid_last_r), + .s1_FGH_src_hist_17_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_17_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_154 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_17_folded_hist[9], + s1_folded_gh_dup_2_hist_17_folded_hist[8:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ s1_folded_gh_dup_2_hist_17_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_T_182 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s1_folded_gh_dup_2_hist_17_folded_hist[8], + s1_folded_gh_dup_2_hist_17_folded_hist[7:0], + s1_folded_gh_dup_2_hist_17_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_17_folded_hist[9]} + : 11'h0)), + .s1_FGH_src_hist_16_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_16_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_16_folded_hist[9], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s1_folded_gh_dup_2_hist_16_folded_hist[8], + s1_folded_gh_dup_2_hist_16_folded_hist[7:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ s1_folded_gh_dup_2_hist_16_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_T_182 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s1_folded_gh_dup_2_hist_16_folded_hist[8], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s1_folded_gh_dup_2_hist_16_folded_hist[7], + s1_folded_gh_dup_2_hist_16_folded_hist[6:0], + s1_folded_gh_dup_2_hist_16_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ s1_folded_gh_dup_2_hist_16_folded_hist[9]} + : 11'h0)), + .s1_FGH_src_hist_15_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_15_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_154 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_15_folded_hist[5], + s1_folded_gh_dup_2_hist_15_folded_hist[4:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ s1_folded_gh_dup_2_hist_15_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_T_182 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s1_folded_gh_dup_2_hist_15_folded_hist[4], + s1_folded_gh_dup_2_hist_15_folded_hist[3:0], + s1_folded_gh_dup_2_hist_15_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_15_folded_hist[5]} + : 7'h0)), + .s1_FGH_src_hist_14_folded_hist + ((_s1_predicted_fh_dup_T_126 + ? {s1_folded_gh_dup_2_hist_14_folded_hist[7:1], + s1_folded_gh_dup_2_hist_14_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_274} + : 8'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_14_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14} + : 8'h0) + | (_s1_predicted_fh_dup_T_182 + ? {s1_folded_gh_dup_2_hist_14_folded_hist[5:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17} + : 8'h0)), + .s1_FGH_src_hist_13_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_13_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_13_folded_hist[7:4], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_13_folded_hist[3], + s1_folded_gh_dup_2_hist_13_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ s1_folded_gh_dup_2_hist_13_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_T_182 + ? {s1_folded_gh_dup_2_hist_13_folded_hist[6:4], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_13_folded_hist[3], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s1_folded_gh_dup_2_hist_13_folded_hist[2], + s1_folded_gh_dup_2_hist_13_folded_hist[1:0], + s1_folded_gh_dup_2_hist_13_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ s1_folded_gh_dup_2_hist_13_folded_hist[7]} + : 9'h0)), + .s1_FGH_src_hist_12_folded_hist + ((_s1_predicted_fh_dup_T_126 + ? {s1_folded_gh_dup_2_hist_12_folded_hist[3:1], + s1_folded_gh_dup_2_hist_12_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_274} + : 4'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_12_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14} + : 4'h0) + | (_s1_predicted_fh_dup_T_182 + ? {s1_folded_gh_dup_2_hist_12_folded_hist[1:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17} + : 4'h0)), + .s1_FGH_src_hist_11_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_11_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_11_folded_hist[6:2], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2) + ^ s1_folded_gh_dup_2_hist_11_folded_hist[1], + s1_folded_gh_dup_2_hist_11_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ s1_folded_gh_dup_2_hist_11_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_182 + ? {s1_folded_gh_dup_2_hist_11_folded_hist[5:2], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2) + ^ s1_folded_gh_dup_2_hist_11_folded_hist[1], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3) + ^ s1_folded_gh_dup_2_hist_11_folded_hist[0], + s1_folded_gh_dup_2_hist_11_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ s1_folded_gh_dup_2_hist_11_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_10_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_10_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_10_folded_hist[7:5], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_10_folded_hist[4], + s1_folded_gh_dup_2_hist_10_folded_hist[3:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ s1_folded_gh_dup_2_hist_10_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_T_182 + ? {s1_folded_gh_dup_2_hist_10_folded_hist[6:5], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_10_folded_hist[4], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s1_folded_gh_dup_2_hist_10_folded_hist[3], + s1_folded_gh_dup_2_hist_10_folded_hist[2:0], + s1_folded_gh_dup_2_hist_10_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ s1_folded_gh_dup_2_hist_10_folded_hist[7]} + : 9'h0)), + .s1_FGH_src_hist_9_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_9_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_9_folded_hist[5:4], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_9_folded_hist[3], + s1_folded_gh_dup_2_hist_9_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ s1_folded_gh_dup_2_hist_9_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_T_182 + ? {s1_folded_gh_dup_2_hist_9_folded_hist[4], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_9_folded_hist[3], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s1_folded_gh_dup_2_hist_9_folded_hist[2], + s1_folded_gh_dup_2_hist_9_folded_hist[1:0], + s1_folded_gh_dup_2_hist_9_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ s1_folded_gh_dup_2_hist_9_folded_hist[5]} + : 7'h0)), + .s1_FGH_src_hist_8_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_8_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_154 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s1_folded_gh_dup_2_hist_8_folded_hist[6], + s1_folded_gh_dup_2_hist_8_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ s1_folded_gh_dup_2_hist_8_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_182 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s1_folded_gh_dup_2_hist_8_folded_hist[5], + s1_folded_gh_dup_2_hist_8_folded_hist[4:0], + s1_folded_gh_dup_2_hist_8_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s1_folded_gh_dup_2_hist_8_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_7_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_7_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_7_folded_hist[5:1], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) + ^ s1_folded_gh_dup_2_hist_7_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ s1_folded_gh_dup_2_hist_7_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_T_182 + ? {s1_folded_gh_dup_2_hist_7_folded_hist[4:1], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) + ^ s1_folded_gh_dup_2_hist_7_folded_hist[0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ s1_folded_gh_dup_2_hist_7_folded_hist[5]} + : 7'h0)), + .s1_FGH_src_hist_6_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_6_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_6_folded_hist[7], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s1_folded_gh_dup_2_hist_6_folded_hist[6], + s1_folded_gh_dup_2_hist_6_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ s1_folded_gh_dup_2_hist_6_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_T_182 + ? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s1_folded_gh_dup_2_hist_6_folded_hist[6], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) + ^ s1_folded_gh_dup_2_hist_6_folded_hist[5], + s1_folded_gh_dup_2_hist_6_folded_hist[4:0], + s1_folded_gh_dup_2_hist_6_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ s1_folded_gh_dup_2_hist_6_folded_hist[7]} + : 9'h0)), + .s1_FGH_src_hist_5_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_5_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_5_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s1_folded_gh_dup_2_hist_5_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_T_182 + ? {s1_folded_gh_dup_2_hist_5_folded_hist[4:0], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s1_folded_gh_dup_2_hist_5_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s1_folded_gh_dup_2_hist_5_folded_hist[5]} + : 7'h0)), + .s1_FGH_src_hist_4_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_4_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_4_folded_hist[6:5], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_4_folded_hist[4], + s1_folded_gh_dup_2_hist_4_folded_hist[3:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ s1_folded_gh_dup_2_hist_4_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_182 + ? {s1_folded_gh_dup_2_hist_4_folded_hist[5], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_4_folded_hist[4], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s1_folded_gh_dup_2_hist_4_folded_hist[3], + s1_folded_gh_dup_2_hist_4_folded_hist[2:0], + s1_folded_gh_dup_2_hist_4_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ s1_folded_gh_dup_2_hist_4_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_3_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_3_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_3_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_3_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_182 + ? {s1_folded_gh_dup_2_hist_3_folded_hist[5:0], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s1_folded_gh_dup_2_hist_3_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s1_folded_gh_dup_2_hist_3_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_2_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_2_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_2_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s1_folded_gh_dup_2_hist_2_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_182 + ? {s1_folded_gh_dup_2_hist_2_folded_hist[5:0], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s1_folded_gh_dup_2_hist_2_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ (s1_last_br_num_oh_dup_2[0] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) + ^ s1_folded_gh_dup_2_hist_2_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_1_folded_hist + ((_s1_predicted_fh_dup_T_126 ? s1_folded_gh_dup_2_hist_1_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_1_folded_hist[9:2], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_1_folded_hist[1], + s1_folded_gh_dup_2_hist_1_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14 + ^ s1_folded_gh_dup_2_hist_1_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_T_182 + ? {s1_folded_gh_dup_2_hist_1_folded_hist[8:2], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s1_folded_gh_dup_2_hist_1_folded_hist[1], + (s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s1_last_br_num_oh_dup_2[1] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s1_last_br_num_oh_dup_2[2] + & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s1_folded_gh_dup_2_hist_1_folded_hist[0], + s1_folded_gh_dup_2_hist_1_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17 + ^ s1_folded_gh_dup_2_hist_1_folded_hist[9]} + : 11'h0)), + .s1_FGH_src_hist_0_folded_hist + ((_s1_predicted_fh_dup_T_126 + ? {s1_folded_gh_dup_2_hist_0_folded_hist[7:1], + s1_folded_gh_dup_2_hist_0_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_274} + : 8'h0) + | (_s1_predicted_fh_dup_T_154 + ? {s1_folded_gh_dup_2_hist_0_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_14} + : 8'h0) + | (_s1_predicted_fh_dup_T_182 + ? {s1_folded_gh_dup_2_hist_0_folded_hist[5:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_17} + : 8'h0)), + .s3_FGH_sel + (s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), + .s3_FGH_src_hist_17_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_17_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_154 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_17_folded_hist[9], + s3_folded_gh_dup_2_hist_17_folded_hist[8:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_17_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_T_182 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s3_folded_gh_dup_2_hist_17_folded_hist[8], + s3_folded_gh_dup_2_hist_17_folded_hist[7:0], + s3_folded_gh_dup_2_hist_17_folded_hist[10], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_17_folded_hist[9]} + : 11'h0)), + .s3_FGH_src_hist_16_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_16_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_16_folded_hist[9], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s3_folded_gh_dup_2_hist_16_folded_hist[8], + s3_folded_gh_dup_2_hist_16_folded_hist[7:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_16_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_T_182 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s3_folded_gh_dup_2_hist_16_folded_hist[8], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s3_folded_gh_dup_2_hist_16_folded_hist[7], + s3_folded_gh_dup_2_hist_16_folded_hist[6:0], + s3_folded_gh_dup_2_hist_16_folded_hist[10], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_16_folded_hist[9]} + : 11'h0)), + .s3_FGH_src_hist_15_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_15_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_154 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_15_folded_hist[5], + s3_folded_gh_dup_2_hist_15_folded_hist[4:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_15_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_T_182 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s3_folded_gh_dup_2_hist_15_folded_hist[4], + s3_folded_gh_dup_2_hist_15_folded_hist[3:0], + s3_folded_gh_dup_2_hist_15_folded_hist[6], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_15_folded_hist[5]} + : 7'h0)), + .s3_FGH_src_hist_14_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_14_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_14_folded_hist[6:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0} + : 8'h0) + | (_s3_predicted_fh_dup_T_182 + ? {s3_folded_gh_dup_2_hist_14_folded_hist[5:0], + 1'h0, + _predictors_io_out_s3_full_pred_2_br_taken_mask_1} + : 8'h0)), + .s3_FGH_src_hist_13_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_13_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_13_folded_hist[7:4], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_13_folded_hist[3], + s3_folded_gh_dup_2_hist_13_folded_hist[2:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_13_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_T_182 + ? {s3_folded_gh_dup_2_hist_13_folded_hist[6:4], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_13_folded_hist[3], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s3_folded_gh_dup_2_hist_13_folded_hist[2], + s3_folded_gh_dup_2_hist_13_folded_hist[1:0], + s3_folded_gh_dup_2_hist_13_folded_hist[8], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_13_folded_hist[7]} + : 9'h0)), + .s3_FGH_src_hist_12_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_12_folded_hist : 4'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_12_folded_hist[2:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0} + : 4'h0) + | (_s3_predicted_fh_dup_T_182 + ? {s3_folded_gh_dup_2_hist_12_folded_hist[1:0], + 1'h0, + _predictors_io_out_s3_full_pred_2_br_taken_mask_1} + : 4'h0)), + .s3_FGH_src_hist_11_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_11_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_11_folded_hist[6:2], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2) + ^ s3_folded_gh_dup_2_hist_11_folded_hist[1], + s3_folded_gh_dup_2_hist_11_folded_hist[0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_11_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_182 + ? {s3_folded_gh_dup_2_hist_11_folded_hist[5:2], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2) + ^ s3_folded_gh_dup_2_hist_11_folded_hist[1], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3) + ^ s3_folded_gh_dup_2_hist_11_folded_hist[0], + s3_folded_gh_dup_2_hist_11_folded_hist[7], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_11_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_10_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_10_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_10_folded_hist[7:5], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_10_folded_hist[4], + s3_folded_gh_dup_2_hist_10_folded_hist[3:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_10_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_T_182 + ? {s3_folded_gh_dup_2_hist_10_folded_hist[6:5], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_10_folded_hist[4], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s3_folded_gh_dup_2_hist_10_folded_hist[3], + s3_folded_gh_dup_2_hist_10_folded_hist[2:0], + s3_folded_gh_dup_2_hist_10_folded_hist[8], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_10_folded_hist[7]} + : 9'h0)), + .s3_FGH_src_hist_9_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_9_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_9_folded_hist[5:4], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_9_folded_hist[3], + s3_folded_gh_dup_2_hist_9_folded_hist[2:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_9_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_T_182 + ? {s3_folded_gh_dup_2_hist_9_folded_hist[4], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_9_folded_hist[3], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s3_folded_gh_dup_2_hist_9_folded_hist[2], + s3_folded_gh_dup_2_hist_9_folded_hist[1:0], + s3_folded_gh_dup_2_hist_9_folded_hist[6], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_9_folded_hist[5]} + : 7'h0)), + .s3_FGH_src_hist_8_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_8_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s3_folded_gh_dup_2_hist_8_folded_hist[6], + s3_folded_gh_dup_2_hist_8_folded_hist[5:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_8_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_182 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s3_folded_gh_dup_2_hist_8_folded_hist[5], + s3_folded_gh_dup_2_hist_8_folded_hist[4:0], + s3_folded_gh_dup_2_hist_8_folded_hist[7], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s3_folded_gh_dup_2_hist_8_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_7_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_7_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_7_folded_hist[5:1], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) + ^ s3_folded_gh_dup_2_hist_7_folded_hist[0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_7_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_T_182 + ? {s3_folded_gh_dup_2_hist_7_folded_hist[4:1], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2) + ^ s3_folded_gh_dup_2_hist_7_folded_hist[0], + 1'h0, + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_7_folded_hist[5]} + : 7'h0)), + .s3_FGH_src_hist_6_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_6_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_6_folded_hist[7], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s3_folded_gh_dup_2_hist_6_folded_hist[6], + s3_folded_gh_dup_2_hist_6_folded_hist[5:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_6_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_T_182 + ? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s3_folded_gh_dup_2_hist_6_folded_hist[6], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) + ^ s3_folded_gh_dup_2_hist_6_folded_hist[5], + s3_folded_gh_dup_2_hist_6_folded_hist[4:0], + s3_folded_gh_dup_2_hist_6_folded_hist[8], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_6_folded_hist[7]} + : 9'h0)), + .s3_FGH_src_hist_5_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_5_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_5_folded_hist[5:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s3_folded_gh_dup_2_hist_5_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_T_182 + ? {s3_folded_gh_dup_2_hist_5_folded_hist[4:0], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2) + ^ s3_folded_gh_dup_2_hist_5_folded_hist[6], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3) + ^ s3_folded_gh_dup_2_hist_5_folded_hist[5]} + : 7'h0)), + .s3_FGH_src_hist_4_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_4_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_4_folded_hist[6:5], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_4_folded_hist[4], + s3_folded_gh_dup_2_hist_4_folded_hist[3:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_4_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_182 + ? {s3_folded_gh_dup_2_hist_4_folded_hist[5], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_4_folded_hist[4], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s3_folded_gh_dup_2_hist_4_folded_hist[3], + s3_folded_gh_dup_2_hist_4_folded_hist[2:0], + s3_folded_gh_dup_2_hist_4_folded_hist[7], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_4_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_3_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_3_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_3_folded_hist[6:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_3_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_182 + ? {s3_folded_gh_dup_2_hist_3_folded_hist[5:0], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2) + ^ s3_folded_gh_dup_2_hist_3_folded_hist[7], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3) + ^ s3_folded_gh_dup_2_hist_3_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_2_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_2_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_2_folded_hist[6:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s3_folded_gh_dup_2_hist_2_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_182 + ? {s3_folded_gh_dup_2_hist_2_folded_hist[5:0], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2) + ^ s3_folded_gh_dup_2_hist_2_folded_hist[7], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_2[0] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3) + ^ s3_folded_gh_dup_2_hist_2_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_1_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_1_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_1_folded_hist[9:2], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_1_folded_hist[1], + s3_folded_gh_dup_2_hist_1_folded_hist[0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0 + ^ s3_folded_gh_dup_2_hist_1_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_T_182 + ? {s3_folded_gh_dup_2_hist_1_folded_hist[8:2], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2) + ^ s3_folded_gh_dup_2_hist_1_folded_hist[1], + (s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 + | s3_last_br_num_oh_dup_2[1] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 + | s3_last_br_num_oh_dup_2[2] + & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3) + ^ s3_folded_gh_dup_2_hist_1_folded_hist[0], + s3_folded_gh_dup_2_hist_1_folded_hist[10], + _predictors_io_out_s3_full_pred_2_br_taken_mask_1 + ^ s3_folded_gh_dup_2_hist_1_folded_hist[9]} + : 11'h0)), + .s3_FGH_src_hist_0_folded_hist + ((_s3_predicted_fh_dup_T_126 ? s3_folded_gh_dup_2_hist_0_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_154 + ? {s3_folded_gh_dup_2_hist_0_folded_hist[6:0], + _predictors_io_out_s3_full_pred_2_br_taken_mask_0} + : 8'h0) + | (_s3_predicted_fh_dup_T_182 + ? {s3_folded_gh_dup_2_hist_0_folded_hist[5:0], + 1'h0, + _predictors_io_out_s3_full_pred_2_br_taken_mask_1} + : 8'h0)), + .redirect_FGHT_sel (do_redirect_dup_next_valid_last_r), + .redirect_FGHT_src_hist_17_folded_hist + (_GEN_63[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_16_folded_hist + (_GEN_64[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_15_folded_hist + (_GEN_65[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_14_folded_hist + (_GEN_66[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_13_folded_hist + (_GEN_67[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_12_folded_hist + (_GEN_68[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_11_folded_hist + (_GEN_69[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_10_folded_hist + (_GEN_70[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_9_folded_hist + (_GEN_71[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_8_folded_hist + (_GEN_72[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_7_folded_hist + (_GEN_73[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_6_folded_hist + (_GEN_74[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_5_folded_hist + (_GEN_75[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_4_folded_hist + (_GEN_76[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_3_folded_hist + (_GEN_77[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_2_folded_hist + (_GEN_78[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_1_folded_hist + (_GEN_79[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_0_folded_hist + (_GEN_80[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_2_hist_17_folded_hist), + .stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_2_hist_16_folded_hist), + .stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_2_hist_15_folded_hist), + .stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_2_hist_14_folded_hist), + .stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_2_hist_13_folded_hist), + .stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_2_hist_12_folded_hist), + .stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_2_hist_11_folded_hist), + .stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_2_hist_10_folded_hist), + .stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_2_hist_9_folded_hist), + .stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_2_hist_8_folded_hist), + .stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_2_hist_7_folded_hist), + .stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_2_hist_6_folded_hist), + .stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_2_hist_5_folded_hist), + .stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_2_hist_4_folded_hist), + .stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_2_hist_3_folded_hist), + .stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_2_hist_2_folded_hist), + .stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_2_hist_1_folded_hist), + .stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_2_hist_0_folded_hist), + .out_res_hist_17_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist), + .out_res_hist_16_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist), + .out_res_hist_15_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist), + .out_res_hist_14_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist), + .out_res_hist_13_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist), + .out_res_hist_12_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist), + .out_res_hist_11_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist), + .out_res_hist_10_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist), + .out_res_hist_9_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist), + .out_res_hist_8_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist), + .out_res_hist_7_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist), + .out_res_hist_6_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist), + .out_res_hist_5_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist), + .out_res_hist_4_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist), + .out_res_hist_3_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist), + .out_res_hist_2_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist), + .out_res_hist_1_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist), + .out_res_hist_0_folded_hist + (_s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist) + ); + PriorityMuxModule_4 s0_folded_gh_dup_3_ppm ( + .s2_FGH_sel + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), + .s2_FGH_src_hist_17_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_17_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_215 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_17_folded_hist[9], + s2_folded_gh_dup_3_hist_17_folded_hist[8:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_17_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_T_243 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s2_folded_gh_dup_3_hist_17_folded_hist[8], + s2_folded_gh_dup_3_hist_17_folded_hist[7:0], + s2_folded_gh_dup_3_hist_17_folded_hist[10], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_17_folded_hist[9]} + : 11'h0)), + .s2_FGH_src_hist_16_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_16_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_16_folded_hist[9], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s2_folded_gh_dup_3_hist_16_folded_hist[8], + s2_folded_gh_dup_3_hist_16_folded_hist[7:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_16_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_T_243 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s2_folded_gh_dup_3_hist_16_folded_hist[8], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s2_folded_gh_dup_3_hist_16_folded_hist[7], + s2_folded_gh_dup_3_hist_16_folded_hist[6:0], + s2_folded_gh_dup_3_hist_16_folded_hist[10], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_16_folded_hist[9]} + : 11'h0)), + .s2_FGH_src_hist_15_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_15_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_215 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_15_folded_hist[5], + s2_folded_gh_dup_3_hist_15_folded_hist[4:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_15_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_T_243 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s2_folded_gh_dup_3_hist_15_folded_hist[4], + s2_folded_gh_dup_3_hist_15_folded_hist[3:0], + s2_folded_gh_dup_3_hist_15_folded_hist[6], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_15_folded_hist[5]} + : 7'h0)), + .s2_FGH_src_hist_14_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_14_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_14_folded_hist[6:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0} + : 8'h0) + | (_s2_predicted_fh_dup_T_243 + ? {s2_folded_gh_dup_3_hist_14_folded_hist[5:0], + 1'h0, + _predictors_io_out_s2_full_pred_3_br_taken_mask_1} + : 8'h0)), + .s2_FGH_src_hist_13_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_13_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_13_folded_hist[7:4], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_13_folded_hist[3], + s2_folded_gh_dup_3_hist_13_folded_hist[2:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_13_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_T_243 + ? {s2_folded_gh_dup_3_hist_13_folded_hist[6:4], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_13_folded_hist[3], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s2_folded_gh_dup_3_hist_13_folded_hist[2], + s2_folded_gh_dup_3_hist_13_folded_hist[1:0], + s2_folded_gh_dup_3_hist_13_folded_hist[8], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_13_folded_hist[7]} + : 9'h0)), + .s2_FGH_src_hist_12_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_12_folded_hist : 4'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_12_folded_hist[2:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0} + : 4'h0) + | (_s2_predicted_fh_dup_T_243 + ? {s2_folded_gh_dup_3_hist_12_folded_hist[1:0], + 1'h0, + _predictors_io_out_s2_full_pred_3_br_taken_mask_1} + : 4'h0)), + .s2_FGH_src_hist_11_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_11_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_11_folded_hist[6:2], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2) + ^ s2_folded_gh_dup_3_hist_11_folded_hist[1], + s2_folded_gh_dup_3_hist_11_folded_hist[0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_11_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_243 + ? {s2_folded_gh_dup_3_hist_11_folded_hist[5:2], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2) + ^ s2_folded_gh_dup_3_hist_11_folded_hist[1], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3) + ^ s2_folded_gh_dup_3_hist_11_folded_hist[0], + s2_folded_gh_dup_3_hist_11_folded_hist[7], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_11_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_10_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_10_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_10_folded_hist[7:5], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_10_folded_hist[4], + s2_folded_gh_dup_3_hist_10_folded_hist[3:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_10_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_T_243 + ? {s2_folded_gh_dup_3_hist_10_folded_hist[6:5], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_10_folded_hist[4], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s2_folded_gh_dup_3_hist_10_folded_hist[3], + s2_folded_gh_dup_3_hist_10_folded_hist[2:0], + s2_folded_gh_dup_3_hist_10_folded_hist[8], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_10_folded_hist[7]} + : 9'h0)), + .s2_FGH_src_hist_9_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_9_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_9_folded_hist[5:4], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_9_folded_hist[3], + s2_folded_gh_dup_3_hist_9_folded_hist[2:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_9_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_T_243 + ? {s2_folded_gh_dup_3_hist_9_folded_hist[4], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_9_folded_hist[3], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s2_folded_gh_dup_3_hist_9_folded_hist[2], + s2_folded_gh_dup_3_hist_9_folded_hist[1:0], + s2_folded_gh_dup_3_hist_9_folded_hist[6], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_9_folded_hist[5]} + : 7'h0)), + .s2_FGH_src_hist_8_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_8_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s2_folded_gh_dup_3_hist_8_folded_hist[6], + s2_folded_gh_dup_3_hist_8_folded_hist[5:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_8_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_243 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s2_folded_gh_dup_3_hist_8_folded_hist[5], + s2_folded_gh_dup_3_hist_8_folded_hist[4:0], + s2_folded_gh_dup_3_hist_8_folded_hist[7], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s2_folded_gh_dup_3_hist_8_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_7_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_7_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_7_folded_hist[5:1], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) + ^ s2_folded_gh_dup_3_hist_7_folded_hist[0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_7_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_T_243 + ? {s2_folded_gh_dup_3_hist_7_folded_hist[4:1], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) + ^ s2_folded_gh_dup_3_hist_7_folded_hist[0], + 1'h0, + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_7_folded_hist[5]} + : 7'h0)), + .s2_FGH_src_hist_6_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_6_folded_hist : 9'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_6_folded_hist[7], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s2_folded_gh_dup_3_hist_6_folded_hist[6], + s2_folded_gh_dup_3_hist_6_folded_hist[5:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_6_folded_hist[8]} + : 9'h0) + | (_s2_predicted_fh_dup_T_243 + ? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s2_folded_gh_dup_3_hist_6_folded_hist[6], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) + ^ s2_folded_gh_dup_3_hist_6_folded_hist[5], + s2_folded_gh_dup_3_hist_6_folded_hist[4:0], + s2_folded_gh_dup_3_hist_6_folded_hist[8], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_6_folded_hist[7]} + : 9'h0)), + .s2_FGH_src_hist_5_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_5_folded_hist : 7'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_5_folded_hist[5:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s2_folded_gh_dup_3_hist_5_folded_hist[6]} + : 7'h0) + | (_s2_predicted_fh_dup_T_243 + ? {s2_folded_gh_dup_3_hist_5_folded_hist[4:0], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s2_folded_gh_dup_3_hist_5_folded_hist[6], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s2_folded_gh_dup_3_hist_5_folded_hist[5]} + : 7'h0)), + .s2_FGH_src_hist_4_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_4_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_4_folded_hist[6:5], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_4_folded_hist[4], + s2_folded_gh_dup_3_hist_4_folded_hist[3:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_4_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_243 + ? {s2_folded_gh_dup_3_hist_4_folded_hist[5], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_4_folded_hist[4], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s2_folded_gh_dup_3_hist_4_folded_hist[3], + s2_folded_gh_dup_3_hist_4_folded_hist[2:0], + s2_folded_gh_dup_3_hist_4_folded_hist[7], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_4_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_3_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_3_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_3_folded_hist[6:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_3_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_243 + ? {s2_folded_gh_dup_3_hist_3_folded_hist[5:0], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s2_folded_gh_dup_3_hist_3_folded_hist[7], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s2_folded_gh_dup_3_hist_3_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_2_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_2_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_2_folded_hist[6:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s2_folded_gh_dup_3_hist_2_folded_hist[7]} + : 8'h0) + | (_s2_predicted_fh_dup_T_243 + ? {s2_folded_gh_dup_3_hist_2_folded_hist[5:0], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s2_folded_gh_dup_3_hist_2_folded_hist[7], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ (s2_last_br_num_oh_dup_3[0] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) + ^ s2_folded_gh_dup_3_hist_2_folded_hist[6]} + : 8'h0)), + .s2_FGH_src_hist_1_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_1_folded_hist : 11'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_1_folded_hist[9:2], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_1_folded_hist[1], + s2_folded_gh_dup_3_hist_1_folded_hist[0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0 + ^ s2_folded_gh_dup_3_hist_1_folded_hist[10]} + : 11'h0) + | (_s2_predicted_fh_dup_T_243 + ? {s2_folded_gh_dup_3_hist_1_folded_hist[8:2], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s2_folded_gh_dup_3_hist_1_folded_hist[1], + (s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s2_last_br_num_oh_dup_3[1] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s2_last_br_num_oh_dup_3[2] + & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s2_folded_gh_dup_3_hist_1_folded_hist[0], + s2_folded_gh_dup_3_hist_1_folded_hist[10], + _predictors_io_out_s2_full_pred_3_br_taken_mask_1 + ^ s2_folded_gh_dup_3_hist_1_folded_hist[9]} + : 11'h0)), + .s2_FGH_src_hist_0_folded_hist + ((_s2_predicted_fh_dup_T_187 ? s2_folded_gh_dup_3_hist_0_folded_hist : 8'h0) + | (_s2_predicted_fh_dup_T_215 + ? {s2_folded_gh_dup_3_hist_0_folded_hist[6:0], + _predictors_io_out_s2_full_pred_3_br_taken_mask_0} + : 8'h0) + | (_s2_predicted_fh_dup_T_243 + ? {s2_folded_gh_dup_3_hist_0_folded_hist[5:0], + 1'h0, + _predictors_io_out_s2_full_pred_3_br_taken_mask_1} + : 8'h0)), + .s1_FGH_sel + (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 + & ~do_redirect_dup_next_valid_last_r), + .s1_FGH_src_hist_17_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_17_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_215 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_17_folded_hist[9], + s1_folded_gh_dup_3_hist_17_folded_hist[8:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ s1_folded_gh_dup_3_hist_17_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_T_243 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s1_folded_gh_dup_3_hist_17_folded_hist[8], + s1_folded_gh_dup_3_hist_17_folded_hist[7:0], + s1_folded_gh_dup_3_hist_17_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_17_folded_hist[9]} + : 11'h0)), + .s1_FGH_src_hist_16_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_16_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_16_folded_hist[9], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s1_folded_gh_dup_3_hist_16_folded_hist[8], + s1_folded_gh_dup_3_hist_16_folded_hist[7:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ s1_folded_gh_dup_3_hist_16_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_T_243 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s1_folded_gh_dup_3_hist_16_folded_hist[8], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s1_folded_gh_dup_3_hist_16_folded_hist[7], + s1_folded_gh_dup_3_hist_16_folded_hist[6:0], + s1_folded_gh_dup_3_hist_16_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ s1_folded_gh_dup_3_hist_16_folded_hist[9]} + : 11'h0)), + .s1_FGH_src_hist_15_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_15_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_215 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_15_folded_hist[5], + s1_folded_gh_dup_3_hist_15_folded_hist[4:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ s1_folded_gh_dup_3_hist_15_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_T_243 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s1_folded_gh_dup_3_hist_15_folded_hist[4], + s1_folded_gh_dup_3_hist_15_folded_hist[3:0], + s1_folded_gh_dup_3_hist_15_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_15_folded_hist[5]} + : 7'h0)), + .s1_FGH_src_hist_14_folded_hist + ((_s1_predicted_fh_dup_T_187 + ? {s1_folded_gh_dup_3_hist_14_folded_hist[7:1], + s1_folded_gh_dup_3_hist_14_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_277} + : 8'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_14_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20} + : 8'h0) + | (_s1_predicted_fh_dup_T_243 + ? {s1_folded_gh_dup_3_hist_14_folded_hist[5:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23} + : 8'h0)), + .s1_FGH_src_hist_13_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_13_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_13_folded_hist[7:4], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_13_folded_hist[3], + s1_folded_gh_dup_3_hist_13_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ s1_folded_gh_dup_3_hist_13_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_T_243 + ? {s1_folded_gh_dup_3_hist_13_folded_hist[6:4], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_13_folded_hist[3], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s1_folded_gh_dup_3_hist_13_folded_hist[2], + s1_folded_gh_dup_3_hist_13_folded_hist[1:0], + s1_folded_gh_dup_3_hist_13_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ s1_folded_gh_dup_3_hist_13_folded_hist[7]} + : 9'h0)), + .s1_FGH_src_hist_12_folded_hist + ((_s1_predicted_fh_dup_T_187 + ? {s1_folded_gh_dup_3_hist_12_folded_hist[3:1], + s1_folded_gh_dup_3_hist_12_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_277} + : 4'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_12_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20} + : 4'h0) + | (_s1_predicted_fh_dup_T_243 + ? {s1_folded_gh_dup_3_hist_12_folded_hist[1:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23} + : 4'h0)), + .s1_FGH_src_hist_11_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_11_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_11_folded_hist[6:2], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2) + ^ s1_folded_gh_dup_3_hist_11_folded_hist[1], + s1_folded_gh_dup_3_hist_11_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ s1_folded_gh_dup_3_hist_11_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_243 + ? {s1_folded_gh_dup_3_hist_11_folded_hist[5:2], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2) + ^ s1_folded_gh_dup_3_hist_11_folded_hist[1], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3) + ^ s1_folded_gh_dup_3_hist_11_folded_hist[0], + s1_folded_gh_dup_3_hist_11_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ s1_folded_gh_dup_3_hist_11_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_10_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_10_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_10_folded_hist[7:5], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_10_folded_hist[4], + s1_folded_gh_dup_3_hist_10_folded_hist[3:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ s1_folded_gh_dup_3_hist_10_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_T_243 + ? {s1_folded_gh_dup_3_hist_10_folded_hist[6:5], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_10_folded_hist[4], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s1_folded_gh_dup_3_hist_10_folded_hist[3], + s1_folded_gh_dup_3_hist_10_folded_hist[2:0], + s1_folded_gh_dup_3_hist_10_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ s1_folded_gh_dup_3_hist_10_folded_hist[7]} + : 9'h0)), + .s1_FGH_src_hist_9_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_9_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_9_folded_hist[5:4], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_9_folded_hist[3], + s1_folded_gh_dup_3_hist_9_folded_hist[2:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ s1_folded_gh_dup_3_hist_9_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_T_243 + ? {s1_folded_gh_dup_3_hist_9_folded_hist[4], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_9_folded_hist[3], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s1_folded_gh_dup_3_hist_9_folded_hist[2], + s1_folded_gh_dup_3_hist_9_folded_hist[1:0], + s1_folded_gh_dup_3_hist_9_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ s1_folded_gh_dup_3_hist_9_folded_hist[5]} + : 7'h0)), + .s1_FGH_src_hist_8_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_8_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_215 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s1_folded_gh_dup_3_hist_8_folded_hist[6], + s1_folded_gh_dup_3_hist_8_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ s1_folded_gh_dup_3_hist_8_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_243 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s1_folded_gh_dup_3_hist_8_folded_hist[5], + s1_folded_gh_dup_3_hist_8_folded_hist[4:0], + s1_folded_gh_dup_3_hist_8_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s1_folded_gh_dup_3_hist_8_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_7_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_7_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_7_folded_hist[5:1], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) + ^ s1_folded_gh_dup_3_hist_7_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ s1_folded_gh_dup_3_hist_7_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_T_243 + ? {s1_folded_gh_dup_3_hist_7_folded_hist[4:1], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) + ^ s1_folded_gh_dup_3_hist_7_folded_hist[0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ s1_folded_gh_dup_3_hist_7_folded_hist[5]} + : 7'h0)), + .s1_FGH_src_hist_6_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_6_folded_hist : 9'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_6_folded_hist[7], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s1_folded_gh_dup_3_hist_6_folded_hist[6], + s1_folded_gh_dup_3_hist_6_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ s1_folded_gh_dup_3_hist_6_folded_hist[8]} + : 9'h0) + | (_s1_predicted_fh_dup_T_243 + ? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s1_folded_gh_dup_3_hist_6_folded_hist[6], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) + ^ s1_folded_gh_dup_3_hist_6_folded_hist[5], + s1_folded_gh_dup_3_hist_6_folded_hist[4:0], + s1_folded_gh_dup_3_hist_6_folded_hist[8], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ s1_folded_gh_dup_3_hist_6_folded_hist[7]} + : 9'h0)), + .s1_FGH_src_hist_5_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_5_folded_hist : 7'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_5_folded_hist[5:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s1_folded_gh_dup_3_hist_5_folded_hist[6]} + : 7'h0) + | (_s1_predicted_fh_dup_T_243 + ? {s1_folded_gh_dup_3_hist_5_folded_hist[4:0], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s1_folded_gh_dup_3_hist_5_folded_hist[6], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s1_folded_gh_dup_3_hist_5_folded_hist[5]} + : 7'h0)), + .s1_FGH_src_hist_4_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_4_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_4_folded_hist[6:5], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_4_folded_hist[4], + s1_folded_gh_dup_3_hist_4_folded_hist[3:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ s1_folded_gh_dup_3_hist_4_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_243 + ? {s1_folded_gh_dup_3_hist_4_folded_hist[5], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_4_folded_hist[4], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s1_folded_gh_dup_3_hist_4_folded_hist[3], + s1_folded_gh_dup_3_hist_4_folded_hist[2:0], + s1_folded_gh_dup_3_hist_4_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ s1_folded_gh_dup_3_hist_4_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_3_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_3_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_3_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_3_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_243 + ? {s1_folded_gh_dup_3_hist_3_folded_hist[5:0], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s1_folded_gh_dup_3_hist_3_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s1_folded_gh_dup_3_hist_3_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_2_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_2_folded_hist : 8'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_2_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s1_folded_gh_dup_3_hist_2_folded_hist[7]} + : 8'h0) + | (_s1_predicted_fh_dup_T_243 + ? {s1_folded_gh_dup_3_hist_2_folded_hist[5:0], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s1_folded_gh_dup_3_hist_2_folded_hist[7], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ (s1_last_br_num_oh_dup_3[0] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) + ^ s1_folded_gh_dup_3_hist_2_folded_hist[6]} + : 8'h0)), + .s1_FGH_src_hist_1_folded_hist + ((_s1_predicted_fh_dup_T_187 ? s1_folded_gh_dup_3_hist_1_folded_hist : 11'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_1_folded_hist[9:2], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_1_folded_hist[1], + s1_folded_gh_dup_3_hist_1_folded_hist[0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20 + ^ s1_folded_gh_dup_3_hist_1_folded_hist[10]} + : 11'h0) + | (_s1_predicted_fh_dup_T_243 + ? {s1_folded_gh_dup_3_hist_1_folded_hist[8:2], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s1_folded_gh_dup_3_hist_1_folded_hist[1], + (s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s1_last_br_num_oh_dup_3[1] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s1_last_br_num_oh_dup_3[2] + & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s1_folded_gh_dup_3_hist_1_folded_hist[0], + s1_folded_gh_dup_3_hist_1_folded_hist[10], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23 + ^ s1_folded_gh_dup_3_hist_1_folded_hist[9]} + : 11'h0)), + .s1_FGH_src_hist_0_folded_hist + ((_s1_predicted_fh_dup_T_187 + ? {s1_folded_gh_dup_3_hist_0_folded_hist[7:1], + s1_folded_gh_dup_3_hist_0_folded_hist[0] + | _s1_possible_predicted_fhs_dup_T_277} + : 8'h0) + | (_s1_predicted_fh_dup_T_215 + ? {s1_folded_gh_dup_3_hist_0_folded_hist[6:0], + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_20} + : 8'h0) + | (_s1_predicted_fh_dup_T_243 + ? {s1_folded_gh_dup_3_hist_0_folded_hist[5:0], + 1'h0, + _s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_T_23} + : 8'h0)), + .s3_FGH_sel + (s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), + .s3_FGH_src_hist_17_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_17_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_215 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_17_folded_hist[9], + s3_folded_gh_dup_3_hist_17_folded_hist[8:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_17_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_T_243 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s3_folded_gh_dup_3_hist_17_folded_hist[8], + s3_folded_gh_dup_3_hist_17_folded_hist[7:0], + s3_folded_gh_dup_3_hist_17_folded_hist[10], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_17_folded_hist[9]} + : 11'h0)), + .s3_FGH_src_hist_16_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_16_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_16_folded_hist[9], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s3_folded_gh_dup_3_hist_16_folded_hist[8], + s3_folded_gh_dup_3_hist_16_folded_hist[7:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_16_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_T_243 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s3_folded_gh_dup_3_hist_16_folded_hist[8], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s3_folded_gh_dup_3_hist_16_folded_hist[7], + s3_folded_gh_dup_3_hist_16_folded_hist[6:0], + s3_folded_gh_dup_3_hist_16_folded_hist[10], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_16_folded_hist[9]} + : 11'h0)), + .s3_FGH_src_hist_15_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_15_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_215 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_15_folded_hist[5], + s3_folded_gh_dup_3_hist_15_folded_hist[4:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_15_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_T_243 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s3_folded_gh_dup_3_hist_15_folded_hist[4], + s3_folded_gh_dup_3_hist_15_folded_hist[3:0], + s3_folded_gh_dup_3_hist_15_folded_hist[6], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_15_folded_hist[5]} + : 7'h0)), + .s3_FGH_src_hist_14_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_14_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_14_folded_hist[6:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0} + : 8'h0) + | (_s3_predicted_fh_dup_T_243 + ? {s3_folded_gh_dup_3_hist_14_folded_hist[5:0], + 1'h0, + _predictors_io_out_s3_full_pred_3_br_taken_mask_1} + : 8'h0)), + .s3_FGH_src_hist_13_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_13_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_13_folded_hist[7:4], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_13_folded_hist[3], + s3_folded_gh_dup_3_hist_13_folded_hist[2:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_13_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_T_243 + ? {s3_folded_gh_dup_3_hist_13_folded_hist[6:4], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_13_folded_hist[3], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s3_folded_gh_dup_3_hist_13_folded_hist[2], + s3_folded_gh_dup_3_hist_13_folded_hist[1:0], + s3_folded_gh_dup_3_hist_13_folded_hist[8], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_13_folded_hist[7]} + : 9'h0)), + .s3_FGH_src_hist_12_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_12_folded_hist : 4'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_12_folded_hist[2:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0} + : 4'h0) + | (_s3_predicted_fh_dup_T_243 + ? {s3_folded_gh_dup_3_hist_12_folded_hist[1:0], + 1'h0, + _predictors_io_out_s3_full_pred_3_br_taken_mask_1} + : 4'h0)), + .s3_FGH_src_hist_11_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_11_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_11_folded_hist[6:2], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2) + ^ s3_folded_gh_dup_3_hist_11_folded_hist[1], + s3_folded_gh_dup_3_hist_11_folded_hist[0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_11_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_243 + ? {s3_folded_gh_dup_3_hist_11_folded_hist[5:2], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2) + ^ s3_folded_gh_dup_3_hist_11_folded_hist[1], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3) + ^ s3_folded_gh_dup_3_hist_11_folded_hist[0], + s3_folded_gh_dup_3_hist_11_folded_hist[7], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_11_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_10_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_10_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_10_folded_hist[7:5], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_10_folded_hist[4], + s3_folded_gh_dup_3_hist_10_folded_hist[3:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_10_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_T_243 + ? {s3_folded_gh_dup_3_hist_10_folded_hist[6:5], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_10_folded_hist[4], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s3_folded_gh_dup_3_hist_10_folded_hist[3], + s3_folded_gh_dup_3_hist_10_folded_hist[2:0], + s3_folded_gh_dup_3_hist_10_folded_hist[8], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_10_folded_hist[7]} + : 9'h0)), + .s3_FGH_src_hist_9_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_9_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_9_folded_hist[5:4], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_9_folded_hist[3], + s3_folded_gh_dup_3_hist_9_folded_hist[2:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_9_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_T_243 + ? {s3_folded_gh_dup_3_hist_9_folded_hist[4], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_9_folded_hist[3], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s3_folded_gh_dup_3_hist_9_folded_hist[2], + s3_folded_gh_dup_3_hist_9_folded_hist[1:0], + s3_folded_gh_dup_3_hist_9_folded_hist[6], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_9_folded_hist[5]} + : 7'h0)), + .s3_FGH_src_hist_8_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_8_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s3_folded_gh_dup_3_hist_8_folded_hist[6], + s3_folded_gh_dup_3_hist_8_folded_hist[5:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_8_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_243 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s3_folded_gh_dup_3_hist_8_folded_hist[5], + s3_folded_gh_dup_3_hist_8_folded_hist[4:0], + s3_folded_gh_dup_3_hist_8_folded_hist[7], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s3_folded_gh_dup_3_hist_8_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_7_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_7_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_7_folded_hist[5:1], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) + ^ s3_folded_gh_dup_3_hist_7_folded_hist[0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_7_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_T_243 + ? {s3_folded_gh_dup_3_hist_7_folded_hist[4:1], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2) + ^ s3_folded_gh_dup_3_hist_7_folded_hist[0], + 1'h0, + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_7_folded_hist[5]} + : 7'h0)), + .s3_FGH_src_hist_6_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_6_folded_hist : 9'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_6_folded_hist[7], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s3_folded_gh_dup_3_hist_6_folded_hist[6], + s3_folded_gh_dup_3_hist_6_folded_hist[5:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_6_folded_hist[8]} + : 9'h0) + | (_s3_predicted_fh_dup_T_243 + ? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s3_folded_gh_dup_3_hist_6_folded_hist[6], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) + ^ s3_folded_gh_dup_3_hist_6_folded_hist[5], + s3_folded_gh_dup_3_hist_6_folded_hist[4:0], + s3_folded_gh_dup_3_hist_6_folded_hist[8], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_6_folded_hist[7]} + : 9'h0)), + .s3_FGH_src_hist_5_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_5_folded_hist : 7'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_5_folded_hist[5:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s3_folded_gh_dup_3_hist_5_folded_hist[6]} + : 7'h0) + | (_s3_predicted_fh_dup_T_243 + ? {s3_folded_gh_dup_3_hist_5_folded_hist[4:0], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2) + ^ s3_folded_gh_dup_3_hist_5_folded_hist[6], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3) + ^ s3_folded_gh_dup_3_hist_5_folded_hist[5]} + : 7'h0)), + .s3_FGH_src_hist_4_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_4_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_4_folded_hist[6:5], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_4_folded_hist[4], + s3_folded_gh_dup_3_hist_4_folded_hist[3:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_4_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_243 + ? {s3_folded_gh_dup_3_hist_4_folded_hist[5], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_4_folded_hist[4], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s3_folded_gh_dup_3_hist_4_folded_hist[3], + s3_folded_gh_dup_3_hist_4_folded_hist[2:0], + s3_folded_gh_dup_3_hist_4_folded_hist[7], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_4_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_3_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_3_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_3_folded_hist[6:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_3_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_243 + ? {s3_folded_gh_dup_3_hist_3_folded_hist[5:0], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2) + ^ s3_folded_gh_dup_3_hist_3_folded_hist[7], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3) + ^ s3_folded_gh_dup_3_hist_3_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_2_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_2_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_2_folded_hist[6:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s3_folded_gh_dup_3_hist_2_folded_hist[7]} + : 8'h0) + | (_s3_predicted_fh_dup_T_243 + ? {s3_folded_gh_dup_3_hist_2_folded_hist[5:0], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2) + ^ s3_folded_gh_dup_3_hist_2_folded_hist[7], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ (s3_last_br_num_oh_dup_3[0] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3) + ^ s3_folded_gh_dup_3_hist_2_folded_hist[6]} + : 8'h0)), + .s3_FGH_src_hist_1_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_1_folded_hist : 11'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_1_folded_hist[9:2], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_1_folded_hist[1], + s3_folded_gh_dup_3_hist_1_folded_hist[0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0 + ^ s3_folded_gh_dup_3_hist_1_folded_hist[10]} + : 11'h0) + | (_s3_predicted_fh_dup_T_243 + ? {s3_folded_gh_dup_3_hist_1_folded_hist[8:2], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2) + ^ s3_folded_gh_dup_3_hist_1_folded_hist[1], + (s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 + | s3_last_br_num_oh_dup_3[1] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 + | s3_last_br_num_oh_dup_3[2] + & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3) + ^ s3_folded_gh_dup_3_hist_1_folded_hist[0], + s3_folded_gh_dup_3_hist_1_folded_hist[10], + _predictors_io_out_s3_full_pred_3_br_taken_mask_1 + ^ s3_folded_gh_dup_3_hist_1_folded_hist[9]} + : 11'h0)), + .s3_FGH_src_hist_0_folded_hist + ((_s3_predicted_fh_dup_T_187 ? s3_folded_gh_dup_3_hist_0_folded_hist : 8'h0) + | (_s3_predicted_fh_dup_T_215 + ? {s3_folded_gh_dup_3_hist_0_folded_hist[6:0], + _predictors_io_out_s3_full_pred_3_br_taken_mask_0} + : 8'h0) + | (_s3_predicted_fh_dup_T_243 + ? {s3_folded_gh_dup_3_hist_0_folded_hist[5:0], + 1'h0, + _predictors_io_out_s3_full_pred_3_br_taken_mask_1} + : 8'h0)), + .redirect_FGHT_sel (do_redirect_dup_next_valid_last_r), + .redirect_FGHT_src_hist_17_folded_hist + (_GEN_81[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_16_folded_hist + (_GEN_82[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_15_folded_hist + (_GEN_83[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_14_folded_hist + (_GEN_84[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_13_folded_hist + (_GEN_85[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_12_folded_hist + (_GEN_86[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_11_folded_hist + (_GEN_87[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_10_folded_hist + (_GEN_88[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_9_folded_hist + (_GEN_89[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_8_folded_hist + (_GEN_90[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_7_folded_hist + (_GEN_91[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_6_folded_hist + (_GEN_92[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_5_folded_hist + (_GEN_93[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_4_folded_hist + (_GEN_94[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_3_folded_hist + (_GEN_95[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_2_folded_hist + (_GEN_96[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_1_folded_hist + (_GEN_97[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .redirect_FGHT_src_hist_0_folded_hist + (_GEN_98[do_redirect_dup_next_bits_r_cfiUpdate_shift]), + .stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_3_hist_17_folded_hist), + .stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_3_hist_16_folded_hist), + .stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_3_hist_15_folded_hist), + .stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_3_hist_14_folded_hist), + .stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_3_hist_13_folded_hist), + .stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_3_hist_12_folded_hist), + .stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_3_hist_11_folded_hist), + .stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_3_hist_10_folded_hist), + .stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_3_hist_9_folded_hist), + .stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_3_hist_8_folded_hist), + .stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_3_hist_7_folded_hist), + .stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_3_hist_6_folded_hist), + .stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_3_hist_5_folded_hist), + .stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_3_hist_4_folded_hist), + .stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_3_hist_3_folded_hist), + .stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_3_hist_2_folded_hist), + .stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_3_hist_1_folded_hist), + .stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_3_hist_0_folded_hist), + .out_res_hist_17_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist), + .out_res_hist_16_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist), + .out_res_hist_15_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist), + .out_res_hist_14_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist), + .out_res_hist_13_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist), + .out_res_hist_12_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist), + .out_res_hist_11_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist), + .out_res_hist_10_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist), + .out_res_hist_9_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist), + .out_res_hist_8_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist), + .out_res_hist_7_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist), + .out_res_hist_6_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist), + .out_res_hist_5_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist), + .out_res_hist_4_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist), + .out_res_hist_3_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist), + .out_res_hist_2_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist), + .out_res_hist_1_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist), + .out_res_hist_0_folded_hist + (_s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist) + ); + PriorityMuxModule_8 s0_ghist_ptr_dup_0_ppm ( + .s2_GHPtr_sel + (s2_redirect_dup_0 & ~s3_redirect_dup_0 & ~do_redirect_dup_next_valid_last_r), + .s2_GHPtr_src_flag + (_s2_predicted_ghist_ptr_dup_T_4 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1[8]) + | _s2_predicted_ghist_ptr_dup_T_32 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6[8]) + | _s2_predicted_ghist_ptr_dup_T_60 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11[8])), + .s2_GHPtr_src_value + ((_s2_predicted_ghist_ptr_dup_T_4 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_T_32 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_T_60 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11[7:0] + : 8'h0)), + .s1_GHPtr_sel + (s1_valid_dup_3 & ~s2_redirect_dup_0 & ~s3_redirect_dup_0 + & ~do_redirect_dup_next_valid_last_r), + .s1_GHPtr_src_flag + (_s1_predicted_ghist_ptr_dup_T_4 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1[8]) + | _s1_predicted_ghist_ptr_dup_T_32 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6[8]) + | _s1_predicted_ghist_ptr_dup_T_60 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11[8])), + .s1_GHPtr_src_value + ((_s1_predicted_ghist_ptr_dup_T_4 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_T_32 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_T_60 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11[7:0] + : 8'h0)), + .s3_GHPtr_sel (s3_redirect_dup_0 & ~do_redirect_dup_next_valid_last_r), + .s3_GHPtr_src_flag + (_s3_predicted_ghist_ptr_dup_T_4 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1[8]) + | _s3_predicted_ghist_ptr_dup_T_32 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6[8]) + | _s3_predicted_ghist_ptr_dup_T_60 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11[8])), + .s3_GHPtr_src_value + ((_s3_predicted_ghist_ptr_dup_T_4 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_1[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_T_32 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_6[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_T_60 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_11[7:0] + : 8'h0)), + .redirect_GHPtr_sel (do_redirect_dup_next_valid_last_r), + .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_T_1[8])), + .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_T_1[7:0]), + .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_0_flag), + .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_0_value), + .out_res_flag (_s0_ghist_ptr_dup_0_ppm_out_res_flag), + .out_res_value (_s0_ghist_ptr_dup_0_ppm_out_res_value) + ); + PriorityMuxModule_8 s0_ghist_ptr_dup_1_ppm ( + .s2_GHPtr_sel + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), + .s2_GHPtr_src_flag + (_s2_predicted_ghist_ptr_dup_T_65 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16[8]) + | _s2_predicted_ghist_ptr_dup_T_93 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21[8]) + | _s2_predicted_ghist_ptr_dup_T_121 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26[8])), + .s2_GHPtr_src_value + ((_s2_predicted_ghist_ptr_dup_T_65 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_T_93 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_T_121 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26[7:0] + : 8'h0)), + .s1_GHPtr_sel + (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 + & ~do_redirect_dup_next_valid_last_r), + .s1_GHPtr_src_flag + (_s1_predicted_ghist_ptr_dup_T_65 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16[8]) + | _s1_predicted_ghist_ptr_dup_T_93 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21[8]) + | _s1_predicted_ghist_ptr_dup_T_121 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26[8])), + .s1_GHPtr_src_value + ((_s1_predicted_ghist_ptr_dup_T_65 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_T_93 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_T_121 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26[7:0] + : 8'h0)), + .s3_GHPtr_sel (s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), + .s3_GHPtr_src_flag + (_s3_predicted_ghist_ptr_dup_T_65 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16[8]) + | _s3_predicted_ghist_ptr_dup_T_93 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21[8]) + | _s3_predicted_ghist_ptr_dup_T_121 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26[8])), + .s3_GHPtr_src_value + ((_s3_predicted_ghist_ptr_dup_T_65 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_16[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_T_93 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_21[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_T_121 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_26[7:0] + : 8'h0)), + .redirect_GHPtr_sel (do_redirect_dup_next_valid_last_r), + .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_T_6[8])), + .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_T_6[7:0]), + .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_1_flag), + .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_1_value), + .out_res_flag (_s0_ghist_ptr_dup_1_ppm_out_res_flag), + .out_res_value (_s0_ghist_ptr_dup_1_ppm_out_res_value) + ); + PriorityMuxModule_8 s0_ghist_ptr_dup_2_ppm ( + .s2_GHPtr_sel + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), + .s2_GHPtr_src_flag + (_s2_predicted_ghist_ptr_dup_T_126 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31[8]) + | _s2_predicted_ghist_ptr_dup_T_154 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36[8]) + | _s2_predicted_ghist_ptr_dup_T_182 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41[8])), + .s2_GHPtr_src_value + ((_s2_predicted_ghist_ptr_dup_T_126 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_T_154 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_T_182 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41[7:0] + : 8'h0)), + .s1_GHPtr_sel + (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 + & ~do_redirect_dup_next_valid_last_r), + .s1_GHPtr_src_flag + (_s1_predicted_ghist_ptr_dup_T_126 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31[8]) + | _s1_predicted_ghist_ptr_dup_T_154 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36[8]) + | _s1_predicted_ghist_ptr_dup_T_182 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41[8])), + .s1_GHPtr_src_value + ((_s1_predicted_ghist_ptr_dup_T_126 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_T_154 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_T_182 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41[7:0] + : 8'h0)), + .s3_GHPtr_sel (s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), + .s3_GHPtr_src_flag + (_s3_predicted_ghist_ptr_dup_T_126 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31[8]) + | _s3_predicted_ghist_ptr_dup_T_154 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36[8]) + | _s3_predicted_ghist_ptr_dup_T_182 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41[8])), + .s3_GHPtr_src_value + ((_s3_predicted_ghist_ptr_dup_T_126 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_31[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_T_154 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_36[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_T_182 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_41[7:0] + : 8'h0)), + .redirect_GHPtr_sel (do_redirect_dup_next_valid_last_r), + .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_T_11[8])), + .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_T_11[7:0]), + .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_2_flag), + .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_2_value), + .out_res_flag (_s0_ghist_ptr_dup_2_ppm_out_res_flag), + .out_res_value (_s0_ghist_ptr_dup_2_ppm_out_res_value) + ); + PriorityMuxModule_8 s0_ghist_ptr_dup_3_ppm ( + .s2_GHPtr_sel + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), + .s2_GHPtr_src_flag + (_s2_predicted_ghist_ptr_dup_T_187 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46[8]) + | _s2_predicted_ghist_ptr_dup_T_215 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51[8]) + | _s2_predicted_ghist_ptr_dup_T_243 + & ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56[8])), + .s2_GHPtr_src_value + ((_s2_predicted_ghist_ptr_dup_T_187 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_T_215 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51[7:0] + : 8'h0) + | (_s2_predicted_ghist_ptr_dup_T_243 + ? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56[7:0] + : 8'h0)), + .s1_GHPtr_sel + (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 + & ~do_redirect_dup_next_valid_last_r), + .s1_GHPtr_src_flag + (_s1_predicted_ghist_ptr_dup_T_187 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46[8]) + | _s1_predicted_ghist_ptr_dup_T_215 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51[8]) + | _s1_predicted_ghist_ptr_dup_T_243 + & ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56[8])), + .s1_GHPtr_src_value + ((_s1_predicted_ghist_ptr_dup_T_187 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_T_215 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51[7:0] + : 8'h0) + | (_s1_predicted_ghist_ptr_dup_T_243 + ? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56[7:0] + : 8'h0)), + .s3_GHPtr_sel (s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), + .s3_GHPtr_src_flag + (_s3_predicted_ghist_ptr_dup_T_187 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46[8]) + | _s3_predicted_ghist_ptr_dup_T_215 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51[8]) + | _s3_predicted_ghist_ptr_dup_T_243 + & ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56[8])), + .s3_GHPtr_src_value + ((_s3_predicted_ghist_ptr_dup_T_187 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_46[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_T_215 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_51[7:0] + : 8'h0) + | (_s3_predicted_ghist_ptr_dup_T_243 + ? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_T_56[7:0] + : 8'h0)), + .redirect_GHPtr_sel (do_redirect_dup_next_valid_last_r), + .redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_T_16[8])), + .redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_T_16[7:0]), + .stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_3_flag), + .stallGHPtr_src_value (s0_ghist_ptr_reg_dup_3_value), + .out_res_flag (_s0_ghist_ptr_dup_3_ppm_out_res_flag), + .out_res_value (_s0_ghist_ptr_dup_3_ppm_out_res_value) + ); + PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_1_ppm ( + .s2_AFHOB_sel + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), + .s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h77)]), + .s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h76)]), + .s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h75)]), + .s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h74)]), + .s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2), + .s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3), + .s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h6)]), + .s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h5)]), + .s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h10)]), + .s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hF)]), + .s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hE)]), + .s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0), + .s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h20)]), + .s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1F)]), + .s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1E)]), + .s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1D)]), + .s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0), + .s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hC)]), + .s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hB)]), + .s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0), + .s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0), + .s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h9)]), + .s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2), + .s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3), + .s1_AFHOB_sel + (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 + & ~do_redirect_dup_next_valid_last_r), + .s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h77)]), + .s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h76)]), + .s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h75)]), + .s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h74)]), + .s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2), + .s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3), + .s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h6)]), + .s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h5)]), + .s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h10)]), + .s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hF)]), + .s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hE)]), + .s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0), + .s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h20)]), + .s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1F)]), + .s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1E)]), + .s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1D)]), + .s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0), + .s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hC)]), + .s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hB)]), + .s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0), + .s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0), + .s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h9)]), + .s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2), + .s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3), + .s3_AFHOB_sel + (s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), + .s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h77)]), + .s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h76)]), + .s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h75)]), + .s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h74)]), + .s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2), + .s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3), + .s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h6)]), + .s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h5)]), + .s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h10)]), + .s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hF)]), + .s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hE)]), + .s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0), + .s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h20)]), + .s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1F)]), + .s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1E)]), + .s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1D)]), + .s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0), + .s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hC)]), + .s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hB)]), + .s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0), + .s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0), + .s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h9)]), + .s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2), + .s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3), + .redirect_AFHOB_sel (do_redirect_dup_next_valid_last_r), + .redirect_AFHOB_src_afhob_5_bits_0 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h77)]), + .redirect_AFHOB_src_afhob_5_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h76)]), + .redirect_AFHOB_src_afhob_5_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h75)]), + .redirect_AFHOB_src_afhob_5_bits_3 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h74)]), + .redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_1_afhob_0_bits_2), + .redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_1_afhob_0_bits_3), + .redirect_AFHOB_src_afhob_4_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h6)]), + .redirect_AFHOB_src_afhob_4_bits_3 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h5)]), + .redirect_AFHOB_src_afhob_3_bits_0 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h10)]), + .redirect_AFHOB_src_afhob_3_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hF)]), + .redirect_AFHOB_src_afhob_3_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hE)]), + .redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_1_afhob_1_bits_0), + .redirect_AFHOB_src_afhob_2_bits_0 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h20)]), + .redirect_AFHOB_src_afhob_2_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1F)]), + .redirect_AFHOB_src_afhob_2_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1E)]), + .redirect_AFHOB_src_afhob_2_bits_3 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1D)]), + .redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_1_afhob_1_bits_0), + .redirect_AFHOB_src_afhob_1_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hC)]), + .redirect_AFHOB_src_afhob_1_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hB)]), + .redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_1_afhob_0_bits_0), + .redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_1_afhob_0_bits_0), + .redirect_AFHOB_src_afhob_0_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h9)]), + .redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_1_afhob_0_bits_2), + .redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_1_afhob_0_bits_3), + .stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0), + .stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1), + .stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2), + .stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3), + .stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0), + .stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1), + .stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2), + .stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3), + .stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0), + .stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1), + .stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2), + .stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3), + .stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0), + .stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1), + .stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2), + .stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3), + .stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0), + .stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1), + .stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2), + .stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3), + .stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0), + .stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1), + .stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2), + .stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3), + .out_res_afhob_5_bits_0 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0), + .out_res_afhob_5_bits_1 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1), + .out_res_afhob_5_bits_2 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2), + .out_res_afhob_5_bits_3 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3), + .out_res_afhob_4_bits_0 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0), + .out_res_afhob_4_bits_1 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1), + .out_res_afhob_4_bits_2 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2), + .out_res_afhob_4_bits_3 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_3), + .out_res_afhob_3_bits_0 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0), + .out_res_afhob_3_bits_1 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1), + .out_res_afhob_3_bits_2 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2), + .out_res_afhob_3_bits_3 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3), + .out_res_afhob_2_bits_0 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0), + .out_res_afhob_2_bits_1 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1), + .out_res_afhob_2_bits_2 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2), + .out_res_afhob_2_bits_3 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3), + .out_res_afhob_1_bits_0 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0), + .out_res_afhob_1_bits_1 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1), + .out_res_afhob_1_bits_2 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2), + .out_res_afhob_1_bits_3 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3), + .out_res_afhob_0_bits_0 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0), + .out_res_afhob_0_bits_1 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1), + .out_res_afhob_0_bits_2 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2), + .out_res_afhob_0_bits_3 + (_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3) + ); + PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_2_ppm ( + .s2_AFHOB_sel + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), + .s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h77)]), + .s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h76)]), + .s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h75)]), + .s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h74)]), + .s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2), + .s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3), + .s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h6)]), + .s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h5)]), + .s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h10)]), + .s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hF)]), + .s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hE)]), + .s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0), + .s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h20)]), + .s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1F)]), + .s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1E)]), + .s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1D)]), + .s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0), + .s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hC)]), + .s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hB)]), + .s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0), + .s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0), + .s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h9)]), + .s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2), + .s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3), + .s1_AFHOB_sel + (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 + & ~do_redirect_dup_next_valid_last_r), + .s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h77)]), + .s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h76)]), + .s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h75)]), + .s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h74)]), + .s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2), + .s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3), + .s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h6)]), + .s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h5)]), + .s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h10)]), + .s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hF)]), + .s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hE)]), + .s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0), + .s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h20)]), + .s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1F)]), + .s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1E)]), + .s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1D)]), + .s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0), + .s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hC)]), + .s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hB)]), + .s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0), + .s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0), + .s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h9)]), + .s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2), + .s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3), + .s3_AFHOB_sel + (s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), + .s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h77)]), + .s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h76)]), + .s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h75)]), + .s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h74)]), + .s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2), + .s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3), + .s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h6)]), + .s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h5)]), + .s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h10)]), + .s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hF)]), + .s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hE)]), + .s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0), + .s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h20)]), + .s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1F)]), + .s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1E)]), + .s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1D)]), + .s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0), + .s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hC)]), + .s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hB)]), + .s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0), + .s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0), + .s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h9)]), + .s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2), + .s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3), + .redirect_AFHOB_sel (do_redirect_dup_next_valid_last_r), + .redirect_AFHOB_src_afhob_5_bits_0 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h77)]), + .redirect_AFHOB_src_afhob_5_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h76)]), + .redirect_AFHOB_src_afhob_5_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h75)]), + .redirect_AFHOB_src_afhob_5_bits_3 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h74)]), + .redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_2_afhob_0_bits_2), + .redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_2_afhob_0_bits_3), + .redirect_AFHOB_src_afhob_4_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h6)]), + .redirect_AFHOB_src_afhob_4_bits_3 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h5)]), + .redirect_AFHOB_src_afhob_3_bits_0 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h10)]), + .redirect_AFHOB_src_afhob_3_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hF)]), + .redirect_AFHOB_src_afhob_3_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hE)]), + .redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_2_afhob_1_bits_0), + .redirect_AFHOB_src_afhob_2_bits_0 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h20)]), + .redirect_AFHOB_src_afhob_2_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1F)]), + .redirect_AFHOB_src_afhob_2_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1E)]), + .redirect_AFHOB_src_afhob_2_bits_3 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1D)]), + .redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_2_afhob_1_bits_0), + .redirect_AFHOB_src_afhob_1_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hC)]), + .redirect_AFHOB_src_afhob_1_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hB)]), + .redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_2_afhob_0_bits_0), + .redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_2_afhob_0_bits_0), + .redirect_AFHOB_src_afhob_0_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h9)]), + .redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_2_afhob_0_bits_2), + .redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_2_afhob_0_bits_3), + .stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0), + .stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1), + .stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2), + .stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3), + .stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0), + .stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1), + .stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2), + .stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3), + .stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0), + .stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1), + .stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2), + .stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3), + .stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0), + .stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1), + .stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2), + .stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3), + .stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0), + .stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1), + .stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2), + .stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3), + .stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0), + .stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1), + .stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2), + .stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3), + .out_res_afhob_5_bits_0 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0), + .out_res_afhob_5_bits_1 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1), + .out_res_afhob_5_bits_2 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2), + .out_res_afhob_5_bits_3 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3), + .out_res_afhob_4_bits_0 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0), + .out_res_afhob_4_bits_1 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1), + .out_res_afhob_4_bits_2 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2), + .out_res_afhob_4_bits_3 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3), + .out_res_afhob_3_bits_0 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0), + .out_res_afhob_3_bits_1 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1), + .out_res_afhob_3_bits_2 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2), + .out_res_afhob_3_bits_3 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3), + .out_res_afhob_2_bits_0 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0), + .out_res_afhob_2_bits_1 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1), + .out_res_afhob_2_bits_2 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2), + .out_res_afhob_2_bits_3 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3), + .out_res_afhob_1_bits_0 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0), + .out_res_afhob_1_bits_1 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1), + .out_res_afhob_1_bits_2 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2), + .out_res_afhob_1_bits_3 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3), + .out_res_afhob_0_bits_0 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0), + .out_res_afhob_0_bits_1 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1), + .out_res_afhob_0_bits_2 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2), + .out_res_afhob_0_bits_3 + (_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3) + ); + PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_3_ppm ( + .s2_AFHOB_sel + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), + .s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h77)]), + .s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h76)]), + .s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h75)]), + .s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h74)]), + .s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2), + .s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3), + .s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h6)]), + .s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h5)]), + .s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h10)]), + .s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hF)]), + .s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hE)]), + .s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0), + .s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h20)]), + .s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1F)]), + .s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1E)]), + .s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1D)]), + .s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0), + .s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hC)]), + .s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hB)]), + .s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0), + .s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0), + .s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h9)]), + .s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2), + .s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3), + .s1_AFHOB_sel + (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 + & ~do_redirect_dup_next_valid_last_r), + .s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h77)]), + .s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h76)]), + .s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h75)]), + .s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h74)]), + .s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2), + .s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3), + .s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h6)]), + .s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h5)]), + .s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h10)]), + .s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hF)]), + .s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hE)]), + .s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0), + .s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h20)]), + .s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1F)]), + .s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1E)]), + .s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1D)]), + .s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0), + .s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hC)]), + .s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hB)]), + .s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0), + .s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0), + .s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h9)]), + .s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2), + .s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3), + .s3_AFHOB_sel + (s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), + .s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h77)]), + .s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h76)]), + .s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h75)]), + .s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h74)]), + .s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2), + .s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3), + .s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h6)]), + .s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h5)]), + .s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h10)]), + .s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hF)]), + .s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hE)]), + .s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0), + .s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h20)]), + .s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1F)]), + .s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1E)]), + .s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1D)]), + .s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0), + .s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hC)]), + .s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hB)]), + .s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0), + .s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0), + .s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h9)]), + .s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2), + .s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3), + .redirect_AFHOB_sel (do_redirect_dup_next_valid_last_r), + .redirect_AFHOB_src_afhob_5_bits_0 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h77)]), + .redirect_AFHOB_src_afhob_5_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h76)]), + .redirect_AFHOB_src_afhob_5_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h75)]), + .redirect_AFHOB_src_afhob_5_bits_3 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h74)]), + .redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_3_afhob_0_bits_2), + .redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_3_afhob_0_bits_3), + .redirect_AFHOB_src_afhob_4_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h6)]), + .redirect_AFHOB_src_afhob_4_bits_3 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h5)]), + .redirect_AFHOB_src_afhob_3_bits_0 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h10)]), + .redirect_AFHOB_src_afhob_3_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hF)]), + .redirect_AFHOB_src_afhob_3_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hE)]), + .redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_3_afhob_1_bits_0), + .redirect_AFHOB_src_afhob_2_bits_0 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h20)]), + .redirect_AFHOB_src_afhob_2_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1F)]), + .redirect_AFHOB_src_afhob_2_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1E)]), + .redirect_AFHOB_src_afhob_2_bits_3 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h1D)]), + .redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_3_afhob_1_bits_0), + .redirect_AFHOB_src_afhob_1_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hC)]), + .redirect_AFHOB_src_afhob_1_bits_2 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'hB)]), + .redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_3_afhob_0_bits_0), + .redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_3_afhob_0_bits_0), + .redirect_AFHOB_src_afhob_0_bits_1 + (_GEN_3[8'(do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value + 8'h9)]), + .redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_3_afhob_0_bits_2), + .redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_3_afhob_0_bits_3), + .stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0), + .stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1), + .stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2), + .stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3), + .stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0), + .stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1), + .stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2), + .stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3), + .stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0), + .stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1), + .stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2), + .stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3), + .stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0), + .stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1), + .stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2), + .stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3), + .stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0), + .stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1), + .stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2), + .stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3), + .stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0), + .stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1), + .stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2), + .stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3), + .out_res_afhob_5_bits_0 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0), + .out_res_afhob_5_bits_1 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1), + .out_res_afhob_5_bits_2 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2), + .out_res_afhob_5_bits_3 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3), + .out_res_afhob_4_bits_0 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0), + .out_res_afhob_4_bits_1 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1), + .out_res_afhob_4_bits_2 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2), + .out_res_afhob_4_bits_3 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_3), + .out_res_afhob_3_bits_0 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0), + .out_res_afhob_3_bits_1 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1), + .out_res_afhob_3_bits_2 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2), + .out_res_afhob_3_bits_3 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3), + .out_res_afhob_2_bits_0 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0), + .out_res_afhob_2_bits_1 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1), + .out_res_afhob_2_bits_2 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2), + .out_res_afhob_2_bits_3 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3), + .out_res_afhob_1_bits_0 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0), + .out_res_afhob_1_bits_1 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1), + .out_res_afhob_1_bits_2 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2), + .out_res_afhob_1_bits_3 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3), + .out_res_afhob_0_bits_0 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0), + .out_res_afhob_0_bits_1 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1), + .out_res_afhob_0_bits_2 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2), + .out_res_afhob_0_bits_3 + (_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3) + ); + PriorityMuxModule_16 s0_last_br_num_oh_dup_1_ppm ( + .s2_BrNumOH_sel + (s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), + .s2_BrNumOH_src + ({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117 & ~_GEN_25 + & _predictors_io_out_s2_full_pred_1_hit, + _predictors_io_out_s2_full_pred_1_slot_valids_0 + & (_GEN_25 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117) + & _predictors_io_out_s2_full_pred_1_hit, + ~_predictors_io_out_s2_full_pred_1_hit + | ~(_predictors_io_out_s2_full_pred_1_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_117)}), + .s1_BrNumOH_sel + (s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1 + & ~do_redirect_dup_next_valid_last_r), + .s1_BrNumOH_src + ({_s1_ghv_wdatas_T_190589 & ~_GEN_9 & _predictors_io_out_s1_full_pred_1_hit, + _predictors_io_out_s1_full_pred_1_slot_valids_0 & _GEN_10 + & _predictors_io_out_s1_full_pred_1_hit, + ~_predictors_io_out_s1_full_pred_1_hit | ~_GEN_8}), + .s3_BrNumOH_sel (s3_redirect_dup_1 & ~do_redirect_dup_next_valid_last_r), + .s3_BrNumOH_src + ({_s3_ghv_wdatas_T_58023 & ~_GEN_36 & _predictors_io_out_s3_full_pred_1_hit, + _predictors_io_out_s3_full_pred_1_slot_valids_0 + & (_GEN_36 | ~_s3_ghv_wdatas_T_58023) & _predictors_io_out_s3_full_pred_1_hit, + ~_predictors_io_out_s3_full_pred_1_hit + | ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 | _s3_ghv_wdatas_T_58023)}), + .redirect_BrNumOH_sel (do_redirect_dup_next_valid_last_r), + .redirect_BrNumOH_src (_thisBrNumOH_dup_T_1[2:0]), + .stallBrNumOH_src (s0_last_br_num_oh_reg_dup_1), + .out_res (_s0_last_br_num_oh_dup_1_ppm_out_res) + ); + PriorityMuxModule_16 s0_last_br_num_oh_dup_2_ppm ( + .s2_BrNumOH_sel + (s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), + .s2_BrNumOH_src + ({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178 & ~_GEN_26 + & _predictors_io_out_s2_full_pred_2_hit, + _predictors_io_out_s2_full_pred_2_slot_valids_0 + & (_GEN_26 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178) + & _predictors_io_out_s2_full_pred_2_hit, + ~_predictors_io_out_s2_full_pred_2_hit + | ~(_predictors_io_out_s2_full_pred_2_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_178)}), + .s1_BrNumOH_sel + (s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2 + & ~do_redirect_dup_next_valid_last_r), + .s1_BrNumOH_src + ({_s1_ghv_wdatas_T_190650 & ~_GEN_12 & _predictors_io_out_s1_full_pred_2_hit, + _predictors_io_out_s1_full_pred_2_slot_valids_0 & _GEN_13 + & _predictors_io_out_s1_full_pred_2_hit, + ~_predictors_io_out_s1_full_pred_2_hit | ~_GEN_11}), + .s3_BrNumOH_sel (s3_redirect_dup_2 & ~do_redirect_dup_next_valid_last_r), + .s3_BrNumOH_src + ({_s3_ghv_wdatas_T_58048 & ~_GEN_37 & _predictors_io_out_s3_full_pred_2_hit, + _predictors_io_out_s3_full_pred_2_slot_valids_0 + & (_GEN_37 | ~_s3_ghv_wdatas_T_58048) & _predictors_io_out_s3_full_pred_2_hit, + ~_predictors_io_out_s3_full_pred_2_hit + | ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 | _s3_ghv_wdatas_T_58048)}), + .redirect_BrNumOH_sel (do_redirect_dup_next_valid_last_r), + .redirect_BrNumOH_src (_thisBrNumOH_dup_T_2[2:0]), + .stallBrNumOH_src (s0_last_br_num_oh_reg_dup_2), + .out_res (_s0_last_br_num_oh_dup_2_ppm_out_res) + ); + PriorityMuxModule_16 s0_last_br_num_oh_dup_3_ppm ( + .s2_BrNumOH_sel + (s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), + .s2_BrNumOH_src + ({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239 & ~_GEN_27 + & _predictors_io_out_s2_full_pred_3_hit, + _predictors_io_out_s2_full_pred_3_slot_valids_0 + & (_GEN_27 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239) + & _predictors_io_out_s2_full_pred_3_hit, + ~_predictors_io_out_s2_full_pred_3_hit + | ~(_predictors_io_out_s2_full_pred_3_slot_valids_0 + | _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_239)}), + .s1_BrNumOH_sel + (s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3 + & ~do_redirect_dup_next_valid_last_r), + .s1_BrNumOH_src + ({_s1_ghv_wdatas_T_190711 & ~_GEN_15 & _predictors_io_out_s1_full_pred_3_hit, + _predictors_io_out_s1_full_pred_3_slot_valids_0 & _GEN_16 + & _predictors_io_out_s1_full_pred_3_hit, + ~_predictors_io_out_s1_full_pred_3_hit | ~_GEN_14}), + .s3_BrNumOH_sel (s3_redirect_dup_3 & ~do_redirect_dup_next_valid_last_r), + .s3_BrNumOH_src + ({_s3_ghv_wdatas_T_58073 & ~_GEN_38 & _predictors_io_out_s3_full_pred_3_hit, + _predictors_io_out_s3_full_pred_3_slot_valids_0 + & (_GEN_38 | ~_s3_ghv_wdatas_T_58073) & _predictors_io_out_s3_full_pred_3_hit, + ~_predictors_io_out_s3_full_pred_3_hit + | ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 | _s3_ghv_wdatas_T_58073)}), + .redirect_BrNumOH_sel (do_redirect_dup_next_valid_last_r), + .redirect_BrNumOH_src (_thisBrNumOH_dup_T_3[2:0]), + .stallBrNumOH_src (s0_last_br_num_oh_reg_dup_3), + .out_res (_s0_last_br_num_oh_dup_3_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_0_ppm ( + .s2_new_bit_0_sel (_ghv_wens_0_T_1 & ~_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), + .s2_new_bit_0_src + (~(|s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_0_T & ~_ghv_wens_0_T_1 & ~_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), + .s1_new_bit_0_src + (~(|s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), + .s3_new_bit_0_src + (~(|s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (~(|do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_0_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_1_ppm ( + .s2_new_bit_0_sel (_ghv_wens_1_T_1 & ~_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_1_T & ~_ghv_wens_1_T_1 & ~_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_1_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_2_ppm ( + .s2_new_bit_0_sel (_ghv_wens_2_T_1 & ~_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_2_T & ~_ghv_wens_2_T_1 & ~_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_2_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_3_ppm ( + .s2_new_bit_0_sel (_ghv_wens_3_T_1 & ~_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_3_T & ~_ghv_wens_3_T_1 & ~_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_3_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_4_ppm ( + .s2_new_bit_0_sel (_ghv_wens_4_T_1 & ~_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_4_T & ~_ghv_wens_4_T_1 & ~_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_4_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_5_ppm ( + .s2_new_bit_0_sel (_ghv_wens_5_T_1 & ~_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_5_T & ~_ghv_wens_5_T_1 & ~_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_5_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_6_ppm ( + .s2_new_bit_0_sel (_ghv_wens_6_T_1 & ~_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_6_T & ~_ghv_wens_6_T_1 & ~_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_6_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_7_ppm ( + .s2_new_bit_0_sel (_ghv_wens_7_T_1 & ~_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_7_T & ~_ghv_wens_7_T_1 & ~_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_7_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_8_ppm ( + .s2_new_bit_0_sel (_ghv_wens_8_T_1 & ~_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_8_T & ~_ghv_wens_8_T_1 & ~_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_8_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_9_ppm ( + .s2_new_bit_0_sel (_ghv_wens_9_T_1 & ~_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_9_T & ~_ghv_wens_9_T_1 & ~_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_9_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_10_ppm ( + .s2_new_bit_0_sel (_ghv_wens_10_T_1 & ~_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_10_T & ~_ghv_wens_10_T_1 & ~_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_10_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_11_ppm ( + .s2_new_bit_0_sel (_ghv_wens_11_T_1 & ~_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_11_T & ~_ghv_wens_11_T_1 & ~_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_11_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_12_ppm ( + .s2_new_bit_0_sel (_ghv_wens_12_T_1 & ~_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_12_T & ~_ghv_wens_12_T_1 & ~_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_12_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_13_ppm ( + .s2_new_bit_0_sel (_ghv_wens_13_T_1 & ~_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_13_T & ~_ghv_wens_13_T_1 & ~_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_13_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_14_ppm ( + .s2_new_bit_0_sel (_ghv_wens_14_T_1 & ~_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_14_T & ~_ghv_wens_14_T_1 & ~_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_14_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_15_ppm ( + .s2_new_bit_0_sel (_ghv_wens_15_T_1 & ~_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h10 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_15_T & ~_ghv_wens_15_T_1 & ~_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h10 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h10 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h10 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_15_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_16_ppm ( + .s2_new_bit_0_sel (_ghv_wens_16_T_1 & ~_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h11 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_16_T & ~_ghv_wens_16_T_1 & ~_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h11 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h11 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h10 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h11 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_16_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_17_ppm ( + .s2_new_bit_0_sel (_ghv_wens_17_T_1 & ~_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h12 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_17_T & ~_ghv_wens_17_T_1 & ~_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h12 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h12 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h11 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h12 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_17_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_18_ppm ( + .s2_new_bit_0_sel (_ghv_wens_18_T_1 & ~_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h13 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_18_T & ~_ghv_wens_18_T_1 & ~_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h13 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h13 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h12 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h13 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_18_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_19_ppm ( + .s2_new_bit_0_sel (_ghv_wens_19_T_1 & ~_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h14 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_19_T & ~_ghv_wens_19_T_1 & ~_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h14 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h14 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h13 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h14 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_19_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_20_ppm ( + .s2_new_bit_0_sel (_ghv_wens_20_T_1 & ~_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h15 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_20_T & ~_ghv_wens_20_T_1 & ~_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h15 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h15 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h14 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h15 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_20_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_21_ppm ( + .s2_new_bit_0_sel (_ghv_wens_21_T_1 & ~_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h16 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_21_T & ~_ghv_wens_21_T_1 & ~_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h16 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h16 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h15 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h16 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_21_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_22_ppm ( + .s2_new_bit_0_sel (_ghv_wens_22_T_1 & ~_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h17 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_22_T & ~_ghv_wens_22_T_1 & ~_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h17 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h17 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h16 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h17 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_22_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_23_ppm ( + .s2_new_bit_0_sel (_ghv_wens_23_T_1 & ~_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h18 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_23_T & ~_ghv_wens_23_T_1 & ~_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h18 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h18 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h17 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h18 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_23_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_24_ppm ( + .s2_new_bit_0_sel (_ghv_wens_24_T_1 & ~_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h19 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_24_T & ~_ghv_wens_24_T_1 & ~_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h19 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h19 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h18 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h19 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_24_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_25_ppm ( + .s2_new_bit_0_sel (_ghv_wens_25_T_1 & ~_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_25_T & ~_ghv_wens_25_T_1 & ~_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h19 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_25_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_26_ppm ( + .s2_new_bit_0_sel (_ghv_wens_26_T_1 & ~_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_26_T & ~_ghv_wens_26_T_1 & ~_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_26_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_27_ppm ( + .s2_new_bit_0_sel (_ghv_wens_27_T_1 & ~_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_27_T & ~_ghv_wens_27_T_1 & ~_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_27_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_28_ppm ( + .s2_new_bit_0_sel (_ghv_wens_28_T_1 & ~_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_28_T & ~_ghv_wens_28_T_1 & ~_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_28_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_29_ppm ( + .s2_new_bit_0_sel (_ghv_wens_29_T_1 & ~_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_29_T & ~_ghv_wens_29_T_1 & ~_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_29_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_30_ppm ( + .s2_new_bit_0_sel (_ghv_wens_30_T_1 & ~_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h1F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_30_T & ~_ghv_wens_30_T_1 & ~_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h1F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h1F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_30_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_31_ppm ( + .s2_new_bit_0_sel (_ghv_wens_31_T_1 & ~_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h20 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_31_T & ~_ghv_wens_31_T_1 & ~_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h20 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h20 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h1F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h20 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_31_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_32_ppm ( + .s2_new_bit_0_sel (_ghv_wens_32_T_1 & ~_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h21 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_32_T & ~_ghv_wens_32_T_1 & ~_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h21 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h21 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h20 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h21 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_32_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_33_ppm ( + .s2_new_bit_0_sel (_ghv_wens_33_T_1 & ~_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h22 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_33_T & ~_ghv_wens_33_T_1 & ~_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h22 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h22 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h21 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h22 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_33_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_34_ppm ( + .s2_new_bit_0_sel (_ghv_wens_34_T_1 & ~_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h23 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_34_T & ~_ghv_wens_34_T_1 & ~_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h23 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h23 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h22 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h23 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_34_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_35_ppm ( + .s2_new_bit_0_sel (_ghv_wens_35_T_1 & ~_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h24 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_35_T & ~_ghv_wens_35_T_1 & ~_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h24 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h24 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h23 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h24 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_35_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_36_ppm ( + .s2_new_bit_0_sel (_ghv_wens_36_T_1 & ~_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h25 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_36_T & ~_ghv_wens_36_T_1 & ~_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h25 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h25 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h24 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h25 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_36_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_37_ppm ( + .s2_new_bit_0_sel (_ghv_wens_37_T_1 & ~_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h26 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_37_T & ~_ghv_wens_37_T_1 & ~_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h26 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h26 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h25 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h26 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_37_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_38_ppm ( + .s2_new_bit_0_sel (_ghv_wens_38_T_1 & ~_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h27 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_38_T & ~_ghv_wens_38_T_1 & ~_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h27 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h27 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h26 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h27 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_38_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_39_ppm ( + .s2_new_bit_0_sel (_ghv_wens_39_T_1 & ~_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h28 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_39_T & ~_ghv_wens_39_T_1 & ~_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h28 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h28 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h27 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h28 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_39_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_40_ppm ( + .s2_new_bit_0_sel (_ghv_wens_40_T_1 & ~_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h29 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_40_T & ~_ghv_wens_40_T_1 & ~_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h29 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h29 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h28 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h29 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_40_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_41_ppm ( + .s2_new_bit_0_sel (_ghv_wens_41_T_1 & ~_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_41_T & ~_ghv_wens_41_T_1 & ~_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h29 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_41_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_42_ppm ( + .s2_new_bit_0_sel (_ghv_wens_42_T_1 & ~_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_42_T & ~_ghv_wens_42_T_1 & ~_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_42_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_43_ppm ( + .s2_new_bit_0_sel (_ghv_wens_43_T_1 & ~_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_43_T & ~_ghv_wens_43_T_1 & ~_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_43_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_44_ppm ( + .s2_new_bit_0_sel (_ghv_wens_44_T_1 & ~_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_44_T & ~_ghv_wens_44_T_1 & ~_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_44_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_45_ppm ( + .s2_new_bit_0_sel (_ghv_wens_45_T_1 & ~_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_45_T & ~_ghv_wens_45_T_1 & ~_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_45_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_46_ppm ( + .s2_new_bit_0_sel (_ghv_wens_46_T_1 & ~_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h2F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_46_T & ~_ghv_wens_46_T_1 & ~_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h2F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h2F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_46_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_47_ppm ( + .s2_new_bit_0_sel (_ghv_wens_47_T_1 & ~_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h30 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_47_T & ~_ghv_wens_47_T_1 & ~_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h30 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h30 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h2F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h30 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_47_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_48_ppm ( + .s2_new_bit_0_sel (_ghv_wens_48_T_1 & ~_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h31 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_48_T & ~_ghv_wens_48_T_1 & ~_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h31 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h31 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h30 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h31 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_48_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_49_ppm ( + .s2_new_bit_0_sel (_ghv_wens_49_T_1 & ~_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h32 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_49_T & ~_ghv_wens_49_T_1 & ~_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h32 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h32 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h31 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h32 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_49_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_50_ppm ( + .s2_new_bit_0_sel (_ghv_wens_50_T_1 & ~_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h33 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_50_T & ~_ghv_wens_50_T_1 & ~_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h33 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h33 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h32 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h33 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_50_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_51_ppm ( + .s2_new_bit_0_sel (_ghv_wens_51_T_1 & ~_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h34 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_51_T & ~_ghv_wens_51_T_1 & ~_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h34 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h34 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h33 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h34 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_51_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_52_ppm ( + .s2_new_bit_0_sel (_ghv_wens_52_T_1 & ~_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h35 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_52_T & ~_ghv_wens_52_T_1 & ~_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h35 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h35 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h34 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h35 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_52_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_53_ppm ( + .s2_new_bit_0_sel (_ghv_wens_53_T_1 & ~_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h36 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_53_T & ~_ghv_wens_53_T_1 & ~_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h36 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h36 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h35 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h36 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_53_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_54_ppm ( + .s2_new_bit_0_sel (_ghv_wens_54_T_1 & ~_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h37 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_54_T & ~_ghv_wens_54_T_1 & ~_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h37 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h37 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h36 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h37 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_54_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_55_ppm ( + .s2_new_bit_0_sel (_ghv_wens_55_T_1 & ~_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h38 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_55_T & ~_ghv_wens_55_T_1 & ~_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h38 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h38 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h37 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h38 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_55_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_56_ppm ( + .s2_new_bit_0_sel (_ghv_wens_56_T_1 & ~_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h39 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_56_T & ~_ghv_wens_56_T_1 & ~_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h39 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h39 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h38 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h39 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_56_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_57_ppm ( + .s2_new_bit_0_sel (_ghv_wens_57_T_1 & ~_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_57_T & ~_ghv_wens_57_T_1 & ~_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h39 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_57_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_58_ppm ( + .s2_new_bit_0_sel (_ghv_wens_58_T_1 & ~_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_58_T & ~_ghv_wens_58_T_1 & ~_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_58_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_59_ppm ( + .s2_new_bit_0_sel (_ghv_wens_59_T_1 & ~_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_59_T & ~_ghv_wens_59_T_1 & ~_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_59_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_60_ppm ( + .s2_new_bit_0_sel (_ghv_wens_60_T_1 & ~_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_60_T & ~_ghv_wens_60_T_1 & ~_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_60_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_61_ppm ( + .s2_new_bit_0_sel (_ghv_wens_61_T_1 & ~_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_61_T & ~_ghv_wens_61_T_1 & ~_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_61_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_62_ppm ( + .s2_new_bit_0_sel (_ghv_wens_62_T_1 & ~_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h3F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_62_T & ~_ghv_wens_62_T_1 & ~_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h3F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h3F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_62_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_63_ppm ( + .s2_new_bit_0_sel (_ghv_wens_63_T_1 & ~_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h40 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_63_T & ~_ghv_wens_63_T_1 & ~_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h40 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h40 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h3F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h40 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_63_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_64_ppm ( + .s2_new_bit_0_sel (_ghv_wens_64_T_1 & ~_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h41 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_64_T & ~_ghv_wens_64_T_1 & ~_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h41 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h41 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h40 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h41 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_64_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_65_ppm ( + .s2_new_bit_0_sel (_ghv_wens_65_T_1 & ~_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h42 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_65_T & ~_ghv_wens_65_T_1 & ~_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h42 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h42 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h41 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h42 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_65_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_66_ppm ( + .s2_new_bit_0_sel (_ghv_wens_66_T_1 & ~_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h43 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_66_T & ~_ghv_wens_66_T_1 & ~_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h43 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h43 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h42 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h43 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_66_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_67_ppm ( + .s2_new_bit_0_sel (_ghv_wens_67_T_1 & ~_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h44 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_67_T & ~_ghv_wens_67_T_1 & ~_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h44 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h44 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h43 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h44 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_67_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_68_ppm ( + .s2_new_bit_0_sel (_ghv_wens_68_T_1 & ~_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h45 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_68_T & ~_ghv_wens_68_T_1 & ~_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h45 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h45 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h44 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h45 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_68_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_69_ppm ( + .s2_new_bit_0_sel (_ghv_wens_69_T_1 & ~_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h46 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_69_T & ~_ghv_wens_69_T_1 & ~_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h46 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h46 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h45 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h46 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_69_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_70_ppm ( + .s2_new_bit_0_sel (_ghv_wens_70_T_1 & ~_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h47 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_70_T & ~_ghv_wens_70_T_1 & ~_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h47 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h47 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h46 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h47 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_70_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_71_ppm ( + .s2_new_bit_0_sel (_ghv_wens_71_T_1 & ~_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h48 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_71_T & ~_ghv_wens_71_T_1 & ~_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h48 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h48 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h47 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h48 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_71_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_72_ppm ( + .s2_new_bit_0_sel (_ghv_wens_72_T_1 & ~_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h49 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_72_T & ~_ghv_wens_72_T_1 & ~_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h49 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h49 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h48 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h49 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_72_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_73_ppm ( + .s2_new_bit_0_sel (_ghv_wens_73_T_1 & ~_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_73_T & ~_ghv_wens_73_T_1 & ~_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h49 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_73_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_74_ppm ( + .s2_new_bit_0_sel (_ghv_wens_74_T_1 & ~_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_74_T & ~_ghv_wens_74_T_1 & ~_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_74_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_75_ppm ( + .s2_new_bit_0_sel (_ghv_wens_75_T_1 & ~_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_75_T & ~_ghv_wens_75_T_1 & ~_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_75_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_76_ppm ( + .s2_new_bit_0_sel (_ghv_wens_76_T_1 & ~_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_76_T & ~_ghv_wens_76_T_1 & ~_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_76_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_77_ppm ( + .s2_new_bit_0_sel (_ghv_wens_77_T_1 & ~_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_77_T & ~_ghv_wens_77_T_1 & ~_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_77_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_78_ppm ( + .s2_new_bit_0_sel (_ghv_wens_78_T_1 & ~_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h4F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_78_T & ~_ghv_wens_78_T_1 & ~_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h4F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h4F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_78_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_79_ppm ( + .s2_new_bit_0_sel (_ghv_wens_79_T_1 & ~_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h50 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_79_T & ~_ghv_wens_79_T_1 & ~_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h50 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h50 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h4F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h50 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_79_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_80_ppm ( + .s2_new_bit_0_sel (_ghv_wens_80_T_1 & ~_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h51 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_80_T & ~_ghv_wens_80_T_1 & ~_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h51 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h51 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h50 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h51 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_80_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_81_ppm ( + .s2_new_bit_0_sel (_ghv_wens_81_T_1 & ~_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h52 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_81_T & ~_ghv_wens_81_T_1 & ~_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h52 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h52 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h51 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h52 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_81_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_82_ppm ( + .s2_new_bit_0_sel (_ghv_wens_82_T_1 & ~_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h53 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_82_T & ~_ghv_wens_82_T_1 & ~_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h53 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h53 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h52 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h53 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_82_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_83_ppm ( + .s2_new_bit_0_sel (_ghv_wens_83_T_1 & ~_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h54 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_83_T & ~_ghv_wens_83_T_1 & ~_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h54 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h54 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h53 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h54 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_83_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_84_ppm ( + .s2_new_bit_0_sel (_ghv_wens_84_T_1 & ~_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h55 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_84_T & ~_ghv_wens_84_T_1 & ~_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h55 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h55 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h54 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h55 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_84_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_85_ppm ( + .s2_new_bit_0_sel (_ghv_wens_85_T_1 & ~_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h56 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_85_T & ~_ghv_wens_85_T_1 & ~_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h56 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h56 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h55 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h56 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_85_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_86_ppm ( + .s2_new_bit_0_sel (_ghv_wens_86_T_1 & ~_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h57 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_86_T & ~_ghv_wens_86_T_1 & ~_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h57 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h57 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h56 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h57 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_86_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_87_ppm ( + .s2_new_bit_0_sel (_ghv_wens_87_T_1 & ~_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h58 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_87_T & ~_ghv_wens_87_T_1 & ~_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h58 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h58 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h57 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h58 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_87_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_88_ppm ( + .s2_new_bit_0_sel (_ghv_wens_88_T_1 & ~_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h59 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_88_T & ~_ghv_wens_88_T_1 & ~_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h59 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h59 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h58 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h59 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_88_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_89_ppm ( + .s2_new_bit_0_sel (_ghv_wens_89_T_1 & ~_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_89_T & ~_ghv_wens_89_T_1 & ~_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h59 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_89_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_90_ppm ( + .s2_new_bit_0_sel (_ghv_wens_90_T_1 & ~_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_90_T & ~_ghv_wens_90_T_1 & ~_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_90_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_91_ppm ( + .s2_new_bit_0_sel (_ghv_wens_91_T_1 & ~_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_91_T & ~_ghv_wens_91_T_1 & ~_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_91_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_92_ppm ( + .s2_new_bit_0_sel (_ghv_wens_92_T_1 & ~_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_92_T & ~_ghv_wens_92_T_1 & ~_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_92_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_93_ppm ( + .s2_new_bit_0_sel (_ghv_wens_93_T_1 & ~_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_93_T & ~_ghv_wens_93_T_1 & ~_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_93_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_94_ppm ( + .s2_new_bit_0_sel (_ghv_wens_94_T_1 & ~_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h5F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_94_T & ~_ghv_wens_94_T_1 & ~_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h5F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h5F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_94_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_95_ppm ( + .s2_new_bit_0_sel (_ghv_wens_95_T_1 & ~_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h60 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_95_T & ~_ghv_wens_95_T_1 & ~_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h60 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h60 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h5F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h60 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_95_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_96_ppm ( + .s2_new_bit_0_sel (_ghv_wens_96_T_1 & ~_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h61 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_96_T & ~_ghv_wens_96_T_1 & ~_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h61 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h61 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h60 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h61 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_96_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_97_ppm ( + .s2_new_bit_0_sel (_ghv_wens_97_T_1 & ~_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h62 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_97_T & ~_ghv_wens_97_T_1 & ~_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h62 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h62 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h61 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h62 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_97_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_98_ppm ( + .s2_new_bit_0_sel (_ghv_wens_98_T_1 & ~_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h63 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_98_T & ~_ghv_wens_98_T_1 & ~_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h63 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h63 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h62 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h63 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_98_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_99_ppm ( + .s2_new_bit_0_sel (_ghv_wens_99_T_1 & ~_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h64 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_99_T & ~_ghv_wens_99_T_1 & ~_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h64 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h64 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h63 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h64 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_99_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_100_ppm ( + .s2_new_bit_0_sel (_ghv_wens_100_T_1 & ~_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h65 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_100_T & ~_ghv_wens_100_T_1 & ~_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h65 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h65 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h64 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h65 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_100_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_101_ppm ( + .s2_new_bit_0_sel (_ghv_wens_101_T_1 & ~_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h66 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_101_T & ~_ghv_wens_101_T_1 & ~_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h66 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h66 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h65 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h66 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_101_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_102_ppm ( + .s2_new_bit_0_sel (_ghv_wens_102_T_1 & ~_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h67 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_102_T & ~_ghv_wens_102_T_1 & ~_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h67 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h67 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h66 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h67 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_102_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_103_ppm ( + .s2_new_bit_0_sel (_ghv_wens_103_T_1 & ~_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h68 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_103_T & ~_ghv_wens_103_T_1 & ~_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h68 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h68 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h67 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h68 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_103_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_104_ppm ( + .s2_new_bit_0_sel (_ghv_wens_104_T_1 & ~_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h69 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_104_T & ~_ghv_wens_104_T_1 & ~_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h69 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h69 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h68 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h69 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_104_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_105_ppm ( + .s2_new_bit_0_sel (_ghv_wens_105_T_1 & ~_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_105_T & ~_ghv_wens_105_T_1 & ~_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h69 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_105_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_106_ppm ( + .s2_new_bit_0_sel (_ghv_wens_106_T_1 & ~_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_106_T & ~_ghv_wens_106_T_1 & ~_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_106_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_107_ppm ( + .s2_new_bit_0_sel (_ghv_wens_107_T_1 & ~_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_107_T & ~_ghv_wens_107_T_1 & ~_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_107_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_108_ppm ( + .s2_new_bit_0_sel (_ghv_wens_108_T_1 & ~_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_108_T & ~_ghv_wens_108_T_1 & ~_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_108_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_109_ppm ( + .s2_new_bit_0_sel (_ghv_wens_109_T_1 & ~_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_109_T & ~_ghv_wens_109_T_1 & ~_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_109_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_110_ppm ( + .s2_new_bit_0_sel (_ghv_wens_110_T_1 & ~_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h6F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_110_T & ~_ghv_wens_110_T_1 & ~_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h6F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h6F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_110_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_111_ppm ( + .s2_new_bit_0_sel (_ghv_wens_111_T_1 & ~_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h70 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_111_T & ~_ghv_wens_111_T_1 & ~_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h70 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h70 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h6F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h70 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_111_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_112_ppm ( + .s2_new_bit_0_sel (_ghv_wens_112_T_1 & ~_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h71 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_112_T & ~_ghv_wens_112_T_1 & ~_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h71 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h71 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h70 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h71 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_112_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_113_ppm ( + .s2_new_bit_0_sel (_ghv_wens_113_T_1 & ~_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h72 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_113_T & ~_ghv_wens_113_T_1 & ~_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h72 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h72 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h71 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h72 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_113_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_114_ppm ( + .s2_new_bit_0_sel (_ghv_wens_114_T_1 & ~_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h73 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_114_T & ~_ghv_wens_114_T_1 & ~_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h73 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h73 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h72 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h73 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_114_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_115_ppm ( + .s2_new_bit_0_sel (_ghv_wens_115_T_1 & ~_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h74 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_115_T & ~_ghv_wens_115_T_1 & ~_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h74 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h74 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h73 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h74 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_115_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_116_ppm ( + .s2_new_bit_0_sel (_ghv_wens_116_T_1 & ~_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h75 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_116_T & ~_ghv_wens_116_T_1 & ~_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h75 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h75 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h74 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h75 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_116_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_117_ppm ( + .s2_new_bit_0_sel (_ghv_wens_117_T_1 & ~_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h76 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_117_T & ~_ghv_wens_117_T_1 & ~_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h76 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h76 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h75 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h76 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_117_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_118_ppm ( + .s2_new_bit_0_sel (_ghv_wens_118_T_1 & ~_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h77 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_118_T & ~_ghv_wens_118_T_1 & ~_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h77 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h77 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h76 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h77 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_118_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_119_ppm ( + .s2_new_bit_0_sel (_ghv_wens_119_T_1 & ~_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h78 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_119_T & ~_ghv_wens_119_T_1 & ~_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h78 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h78 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h77 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h78 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_119_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_120_ppm ( + .s2_new_bit_0_sel (_ghv_wens_120_T_1 & ~_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h79 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_120_T & ~_ghv_wens_120_T_1 & ~_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h79 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h79 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h78 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h79 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_120_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_121_ppm ( + .s2_new_bit_0_sel (_ghv_wens_121_T_1 & ~_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_121_T & ~_ghv_wens_121_T_1 & ~_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h79 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_121_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_122_ppm ( + .s2_new_bit_0_sel (_ghv_wens_122_T_1 & ~_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_122_T & ~_ghv_wens_122_T_1 & ~_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_122_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_123_ppm ( + .s2_new_bit_0_sel (_ghv_wens_123_T_1 & ~_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_123_T & ~_ghv_wens_123_T_1 & ~_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_123_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_124_ppm ( + .s2_new_bit_0_sel (_ghv_wens_124_T_1 & ~_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_124_T & ~_ghv_wens_124_T_1 & ~_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_124_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_125_ppm ( + .s2_new_bit_0_sel (_ghv_wens_125_T_1 & ~_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_125_T & ~_ghv_wens_125_T_1 & ~_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_125_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_126_ppm ( + .s2_new_bit_0_sel (_ghv_wens_126_T_1 & ~_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h7F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_126_T & ~_ghv_wens_126_T_1 & ~_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h7F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h7F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_126_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_127_ppm ( + .s2_new_bit_0_sel (_ghv_wens_127_T_1 & ~_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h80 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_127_T & ~_ghv_wens_127_T_1 & ~_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h80 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h80 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h7F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h80 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_127_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_128_ppm ( + .s2_new_bit_0_sel (_ghv_wens_128_T_1 & ~_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h81 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_128_T & ~_ghv_wens_128_T_1 & ~_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h81 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h81 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h80 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h81 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_128_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_129_ppm ( + .s2_new_bit_0_sel (_ghv_wens_129_T_1 & ~_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h82 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_129_T & ~_ghv_wens_129_T_1 & ~_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h82 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h82 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h81 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h82 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_129_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_130_ppm ( + .s2_new_bit_0_sel (_ghv_wens_130_T_1 & ~_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h83 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_130_T & ~_ghv_wens_130_T_1 & ~_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h83 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h83 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h82 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h83 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_130_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_131_ppm ( + .s2_new_bit_0_sel (_ghv_wens_131_T_1 & ~_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h84 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_131_T & ~_ghv_wens_131_T_1 & ~_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h84 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h84 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h83 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h84 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_131_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_132_ppm ( + .s2_new_bit_0_sel (_ghv_wens_132_T_1 & ~_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h85 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_132_T & ~_ghv_wens_132_T_1 & ~_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h85 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h85 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h84 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h85 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_132_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_133_ppm ( + .s2_new_bit_0_sel (_ghv_wens_133_T_1 & ~_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h86 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_133_T & ~_ghv_wens_133_T_1 & ~_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h86 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h86 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h85 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h86 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_133_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_134_ppm ( + .s2_new_bit_0_sel (_ghv_wens_134_T_1 & ~_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h87 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_134_T & ~_ghv_wens_134_T_1 & ~_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h87 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h87 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h86 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h87 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_134_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_135_ppm ( + .s2_new_bit_0_sel (_ghv_wens_135_T_1 & ~_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h88 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_135_T & ~_ghv_wens_135_T_1 & ~_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h88 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h88 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h87 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h88 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_135_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_136_ppm ( + .s2_new_bit_0_sel (_ghv_wens_136_T_1 & ~_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h89 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_136_T & ~_ghv_wens_136_T_1 & ~_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h89 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h89 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h88 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h89 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_136_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_137_ppm ( + .s2_new_bit_0_sel (_ghv_wens_137_T_1 & ~_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_137_T & ~_ghv_wens_137_T_1 & ~_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h89 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_137_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_138_ppm ( + .s2_new_bit_0_sel (_ghv_wens_138_T_1 & ~_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_138_T & ~_ghv_wens_138_T_1 & ~_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_138_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_139_ppm ( + .s2_new_bit_0_sel (_ghv_wens_139_T_1 & ~_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_139_T & ~_ghv_wens_139_T_1 & ~_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_139_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_140_ppm ( + .s2_new_bit_0_sel (_ghv_wens_140_T_1 & ~_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_140_T & ~_ghv_wens_140_T_1 & ~_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_140_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_141_ppm ( + .s2_new_bit_0_sel (_ghv_wens_141_T_1 & ~_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_141_T & ~_ghv_wens_141_T_1 & ~_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_141_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_142_ppm ( + .s2_new_bit_0_sel (_ghv_wens_142_T_1 & ~_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h8F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_142_T & ~_ghv_wens_142_T_1 & ~_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h8F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h8F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_142_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_143_ppm ( + .s2_new_bit_0_sel (_ghv_wens_143_T_1 & ~_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h90 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_143_T & ~_ghv_wens_143_T_1 & ~_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h90 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h90 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h8F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h90 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_143_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_144_ppm ( + .s2_new_bit_0_sel (_ghv_wens_144_T_1 & ~_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h91 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_144_T & ~_ghv_wens_144_T_1 & ~_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h91 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h91 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h90 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h91 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_144_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_145_ppm ( + .s2_new_bit_0_sel (_ghv_wens_145_T_1 & ~_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h92 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_145_T & ~_ghv_wens_145_T_1 & ~_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h92 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h92 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h91 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h92 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_145_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_146_ppm ( + .s2_new_bit_0_sel (_ghv_wens_146_T_1 & ~_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h93 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_146_T & ~_ghv_wens_146_T_1 & ~_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h93 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h93 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h92 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h93 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_146_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_147_ppm ( + .s2_new_bit_0_sel (_ghv_wens_147_T_1 & ~_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h94 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_147_T & ~_ghv_wens_147_T_1 & ~_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h94 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h94 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h93 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h94 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_147_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_148_ppm ( + .s2_new_bit_0_sel (_ghv_wens_148_T_1 & ~_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h95 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_148_T & ~_ghv_wens_148_T_1 & ~_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h95 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h95 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h94 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h95 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_148_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_149_ppm ( + .s2_new_bit_0_sel (_ghv_wens_149_T_1 & ~_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h96 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_149_T & ~_ghv_wens_149_T_1 & ~_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h96 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h96 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h95 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h96 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_149_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_150_ppm ( + .s2_new_bit_0_sel (_ghv_wens_150_T_1 & ~_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h97 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_150_T & ~_ghv_wens_150_T_1 & ~_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h97 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h97 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h96 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h97 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_150_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_151_ppm ( + .s2_new_bit_0_sel (_ghv_wens_151_T_1 & ~_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h98 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_151_T & ~_ghv_wens_151_T_1 & ~_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h98 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h98 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h97 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h98 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_151_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_152_ppm ( + .s2_new_bit_0_sel (_ghv_wens_152_T_1 & ~_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h99 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_152_T & ~_ghv_wens_152_T_1 & ~_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h99 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h99 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h98 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h99 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_152_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_153_ppm ( + .s2_new_bit_0_sel (_ghv_wens_153_T_1 & ~_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9A + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_153_T & ~_ghv_wens_153_T_1 & ~_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9A & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9A & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h99 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9A + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_153_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_154_ppm ( + .s2_new_bit_0_sel (_ghv_wens_154_T_1 & ~_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9B + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_154_T & ~_ghv_wens_154_T_1 & ~_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9B & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9B & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9A + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9B + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_154_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_155_ppm ( + .s2_new_bit_0_sel (_ghv_wens_155_T_1 & ~_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9C + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_155_T & ~_ghv_wens_155_T_1 & ~_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9C & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9C & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9B + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9C + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_155_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_156_ppm ( + .s2_new_bit_0_sel (_ghv_wens_156_T_1 & ~_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9D + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_156_T & ~_ghv_wens_156_T_1 & ~_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9D & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9D & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9C + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9D + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_156_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_157_ppm ( + .s2_new_bit_0_sel (_ghv_wens_157_T_1 & ~_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9E + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_157_T & ~_ghv_wens_157_T_1 & ~_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9E & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9E & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9D + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9E + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_157_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_158_ppm ( + .s2_new_bit_0_sel (_ghv_wens_158_T_1 & ~_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'h9F + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_158_T & ~_ghv_wens_158_T_1 & ~_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'h9F & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'h9F & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9E + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9F + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_158_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_159_ppm ( + .s2_new_bit_0_sel (_ghv_wens_159_T_1 & ~_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_159_T & ~_ghv_wens_159_T_1 & ~_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'h9F + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA0 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_159_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_160_ppm ( + .s2_new_bit_0_sel (_ghv_wens_160_T_1 & ~_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_160_T & ~_ghv_wens_160_T_1 & ~_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA0 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_160_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_161_ppm ( + .s2_new_bit_0_sel (_ghv_wens_161_T_1 & ~_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_161_T & ~_ghv_wens_161_T_1 & ~_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_161_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_162_ppm ( + .s2_new_bit_0_sel (_ghv_wens_162_T_1 & ~_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_162_T & ~_ghv_wens_162_T_1 & ~_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_162_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_163_ppm ( + .s2_new_bit_0_sel (_ghv_wens_163_T_1 & ~_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_163_T & ~_ghv_wens_163_T_1 & ~_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_163_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_164_ppm ( + .s2_new_bit_0_sel (_ghv_wens_164_T_1 & ~_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_164_T & ~_ghv_wens_164_T_1 & ~_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_164_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_165_ppm ( + .s2_new_bit_0_sel (_ghv_wens_165_T_1 & ~_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_165_T & ~_ghv_wens_165_T_1 & ~_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_165_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_166_ppm ( + .s2_new_bit_0_sel (_ghv_wens_166_T_1 & ~_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_166_T & ~_ghv_wens_166_T_1 & ~_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_166_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_167_ppm ( + .s2_new_bit_0_sel (_ghv_wens_167_T_1 & ~_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_167_T & ~_ghv_wens_167_T_1 & ~_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_167_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_168_ppm ( + .s2_new_bit_0_sel (_ghv_wens_168_T_1 & ~_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hA9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_168_T & ~_ghv_wens_168_T_1 & ~_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hA9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hA9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_168_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_169_ppm ( + .s2_new_bit_0_sel (_ghv_wens_169_T_1 & ~_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hAA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_169_T & ~_ghv_wens_169_T_1 & ~_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hA9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_169_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_170_ppm ( + .s2_new_bit_0_sel (_ghv_wens_170_T_1 & ~_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hAB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_170_T & ~_ghv_wens_170_T_1 & ~_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_170_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_171_ppm ( + .s2_new_bit_0_sel (_ghv_wens_171_T_1 & ~_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hAC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_171_T & ~_ghv_wens_171_T_1 & ~_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_171_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_172_ppm ( + .s2_new_bit_0_sel (_ghv_wens_172_T_1 & ~_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hAD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_172_T & ~_ghv_wens_172_T_1 & ~_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAD + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_172_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_173_ppm ( + .s2_new_bit_0_sel (_ghv_wens_173_T_1 & ~_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hAE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_173_T & ~_ghv_wens_173_T_1 & ~_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAD + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_173_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_174_ppm ( + .s2_new_bit_0_sel (_ghv_wens_174_T_1 & ~_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hAF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_174_T & ~_ghv_wens_174_T_1 & ~_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hAF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hAF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAF + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_174_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_175_ppm ( + .s2_new_bit_0_sel (_ghv_wens_175_T_1 & ~_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_175_T & ~_ghv_wens_175_T_1 & ~_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hAF + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB0 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_175_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_176_ppm ( + .s2_new_bit_0_sel (_ghv_wens_176_T_1 & ~_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_176_T & ~_ghv_wens_176_T_1 & ~_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB0 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_176_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_177_ppm ( + .s2_new_bit_0_sel (_ghv_wens_177_T_1 & ~_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_177_T & ~_ghv_wens_177_T_1 & ~_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_177_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_178_ppm ( + .s2_new_bit_0_sel (_ghv_wens_178_T_1 & ~_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_178_T & ~_ghv_wens_178_T_1 & ~_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_178_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_179_ppm ( + .s2_new_bit_0_sel (_ghv_wens_179_T_1 & ~_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_179_T & ~_ghv_wens_179_T_1 & ~_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_179_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_180_ppm ( + .s2_new_bit_0_sel (_ghv_wens_180_T_1 & ~_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_180_T & ~_ghv_wens_180_T_1 & ~_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_180_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_181_ppm ( + .s2_new_bit_0_sel (_ghv_wens_181_T_1 & ~_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_181_T & ~_ghv_wens_181_T_1 & ~_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_181_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_182_ppm ( + .s2_new_bit_0_sel (_ghv_wens_182_T_1 & ~_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_182_T & ~_ghv_wens_182_T_1 & ~_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_182_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_183_ppm ( + .s2_new_bit_0_sel (_ghv_wens_183_T_1 & ~_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_183_T & ~_ghv_wens_183_T_1 & ~_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_183_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_184_ppm ( + .s2_new_bit_0_sel (_ghv_wens_184_T_1 & ~_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hB9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_184_T & ~_ghv_wens_184_T_1 & ~_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hB9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hB9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_184_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_185_ppm ( + .s2_new_bit_0_sel (_ghv_wens_185_T_1 & ~_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hBA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_185_T & ~_ghv_wens_185_T_1 & ~_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hB9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_185_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_186_ppm ( + .s2_new_bit_0_sel (_ghv_wens_186_T_1 & ~_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hBB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_186_T & ~_ghv_wens_186_T_1 & ~_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_186_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_187_ppm ( + .s2_new_bit_0_sel (_ghv_wens_187_T_1 & ~_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hBC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_187_T & ~_ghv_wens_187_T_1 & ~_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_187_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_188_ppm ( + .s2_new_bit_0_sel (_ghv_wens_188_T_1 & ~_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hBD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_188_T & ~_ghv_wens_188_T_1 & ~_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBD + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_188_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_189_ppm ( + .s2_new_bit_0_sel (_ghv_wens_189_T_1 & ~_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hBE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_189_T & ~_ghv_wens_189_T_1 & ~_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBD + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_189_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_190_ppm ( + .s2_new_bit_0_sel (_ghv_wens_190_T_1 & ~_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hBF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_190_T & ~_ghv_wens_190_T_1 & ~_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hBF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hBF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBF + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_190_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_191_ppm ( + .s2_new_bit_0_sel (_ghv_wens_191_T_1 & ~_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_191_T & ~_ghv_wens_191_T_1 & ~_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hBF + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC0 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_191_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_192_ppm ( + .s2_new_bit_0_sel (_ghv_wens_192_T_1 & ~_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_192_T & ~_ghv_wens_192_T_1 & ~_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC0 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_192_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_193_ppm ( + .s2_new_bit_0_sel (_ghv_wens_193_T_1 & ~_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_193_T & ~_ghv_wens_193_T_1 & ~_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_193_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_194_ppm ( + .s2_new_bit_0_sel (_ghv_wens_194_T_1 & ~_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_194_T & ~_ghv_wens_194_T_1 & ~_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_194_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_195_ppm ( + .s2_new_bit_0_sel (_ghv_wens_195_T_1 & ~_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_195_T & ~_ghv_wens_195_T_1 & ~_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_195_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_196_ppm ( + .s2_new_bit_0_sel (_ghv_wens_196_T_1 & ~_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_196_T & ~_ghv_wens_196_T_1 & ~_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_196_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_197_ppm ( + .s2_new_bit_0_sel (_ghv_wens_197_T_1 & ~_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_197_T & ~_ghv_wens_197_T_1 & ~_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_197_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_198_ppm ( + .s2_new_bit_0_sel (_ghv_wens_198_T_1 & ~_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_198_T & ~_ghv_wens_198_T_1 & ~_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_198_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_199_ppm ( + .s2_new_bit_0_sel (_ghv_wens_199_T_1 & ~_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_199_T & ~_ghv_wens_199_T_1 & ~_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_199_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_200_ppm ( + .s2_new_bit_0_sel (_ghv_wens_200_T_1 & ~_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hC9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_200_T & ~_ghv_wens_200_T_1 & ~_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hC9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hC9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_200_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_201_ppm ( + .s2_new_bit_0_sel (_ghv_wens_201_T_1 & ~_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hCA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_201_T & ~_ghv_wens_201_T_1 & ~_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hC9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_201_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_202_ppm ( + .s2_new_bit_0_sel (_ghv_wens_202_T_1 & ~_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hCB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_202_T & ~_ghv_wens_202_T_1 & ~_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_202_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_203_ppm ( + .s2_new_bit_0_sel (_ghv_wens_203_T_1 & ~_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hCC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_203_T & ~_ghv_wens_203_T_1 & ~_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_203_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_204_ppm ( + .s2_new_bit_0_sel (_ghv_wens_204_T_1 & ~_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hCD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_204_T & ~_ghv_wens_204_T_1 & ~_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCD + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_204_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_205_ppm ( + .s2_new_bit_0_sel (_ghv_wens_205_T_1 & ~_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hCE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_205_T & ~_ghv_wens_205_T_1 & ~_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCD + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_205_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_206_ppm ( + .s2_new_bit_0_sel (_ghv_wens_206_T_1 & ~_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hCF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_206_T & ~_ghv_wens_206_T_1 & ~_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hCF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hCF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCF + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_206_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_207_ppm ( + .s2_new_bit_0_sel (_ghv_wens_207_T_1 & ~_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_207_T & ~_ghv_wens_207_T_1 & ~_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hCF + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD0 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_207_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_208_ppm ( + .s2_new_bit_0_sel (_ghv_wens_208_T_1 & ~_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_208_T & ~_ghv_wens_208_T_1 & ~_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD0 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_208_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_209_ppm ( + .s2_new_bit_0_sel (_ghv_wens_209_T_1 & ~_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_209_T & ~_ghv_wens_209_T_1 & ~_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_209_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_210_ppm ( + .s2_new_bit_0_sel (_ghv_wens_210_T_1 & ~_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_210_T & ~_ghv_wens_210_T_1 & ~_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_210_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_211_ppm ( + .s2_new_bit_0_sel (_ghv_wens_211_T_1 & ~_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_211_T & ~_ghv_wens_211_T_1 & ~_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_211_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_212_ppm ( + .s2_new_bit_0_sel (_ghv_wens_212_T_1 & ~_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_212_T & ~_ghv_wens_212_T_1 & ~_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_212_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_213_ppm ( + .s2_new_bit_0_sel (_ghv_wens_213_T_1 & ~_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_213_T & ~_ghv_wens_213_T_1 & ~_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_213_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_214_ppm ( + .s2_new_bit_0_sel (_ghv_wens_214_T_1 & ~_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_214_T & ~_ghv_wens_214_T_1 & ~_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_214_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_215_ppm ( + .s2_new_bit_0_sel (_ghv_wens_215_T_1 & ~_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_215_T & ~_ghv_wens_215_T_1 & ~_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_215_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_216_ppm ( + .s2_new_bit_0_sel (_ghv_wens_216_T_1 & ~_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hD9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_216_T & ~_ghv_wens_216_T_1 & ~_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hD9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hD9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_216_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_217_ppm ( + .s2_new_bit_0_sel (_ghv_wens_217_T_1 & ~_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hDA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_217_T & ~_ghv_wens_217_T_1 & ~_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hD9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_217_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_218_ppm ( + .s2_new_bit_0_sel (_ghv_wens_218_T_1 & ~_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hDB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_218_T & ~_ghv_wens_218_T_1 & ~_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_218_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_219_ppm ( + .s2_new_bit_0_sel (_ghv_wens_219_T_1 & ~_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hDC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_219_T & ~_ghv_wens_219_T_1 & ~_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_219_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_220_ppm ( + .s2_new_bit_0_sel (_ghv_wens_220_T_1 & ~_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hDD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_220_T & ~_ghv_wens_220_T_1 & ~_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDD + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_220_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_221_ppm ( + .s2_new_bit_0_sel (_ghv_wens_221_T_1 & ~_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hDE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_221_T & ~_ghv_wens_221_T_1 & ~_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDD + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_221_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_222_ppm ( + .s2_new_bit_0_sel (_ghv_wens_222_T_1 & ~_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hDF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_222_T & ~_ghv_wens_222_T_1 & ~_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hDF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hDF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDF + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_222_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_223_ppm ( + .s2_new_bit_0_sel (_ghv_wens_223_T_1 & ~_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_223_T & ~_ghv_wens_223_T_1 & ~_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hDF + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE0 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_223_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_224_ppm ( + .s2_new_bit_0_sel (_ghv_wens_224_T_1 & ~_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_224_T & ~_ghv_wens_224_T_1 & ~_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE0 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_224_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_225_ppm ( + .s2_new_bit_0_sel (_ghv_wens_225_T_1 & ~_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_225_T & ~_ghv_wens_225_T_1 & ~_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_225_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_226_ppm ( + .s2_new_bit_0_sel (_ghv_wens_226_T_1 & ~_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_226_T & ~_ghv_wens_226_T_1 & ~_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_226_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_227_ppm ( + .s2_new_bit_0_sel (_ghv_wens_227_T_1 & ~_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_227_T & ~_ghv_wens_227_T_1 & ~_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_227_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_228_ppm ( + .s2_new_bit_0_sel (_ghv_wens_228_T_1 & ~_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_228_T & ~_ghv_wens_228_T_1 & ~_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_228_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_229_ppm ( + .s2_new_bit_0_sel (_ghv_wens_229_T_1 & ~_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_229_T & ~_ghv_wens_229_T_1 & ~_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_229_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_230_ppm ( + .s2_new_bit_0_sel (_ghv_wens_230_T_1 & ~_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_230_T & ~_ghv_wens_230_T_1 & ~_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_230_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_231_ppm ( + .s2_new_bit_0_sel (_ghv_wens_231_T_1 & ~_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_231_T & ~_ghv_wens_231_T_1 & ~_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_231_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_232_ppm ( + .s2_new_bit_0_sel (_ghv_wens_232_T_1 & ~_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hE9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_232_T & ~_ghv_wens_232_T_1 & ~_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hE9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hE9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_232_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_233_ppm ( + .s2_new_bit_0_sel (_ghv_wens_233_T_1 & ~_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hEA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_233_T & ~_ghv_wens_233_T_1 & ~_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hE9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_233_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_234_ppm ( + .s2_new_bit_0_sel (_ghv_wens_234_T_1 & ~_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hEB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_234_T & ~_ghv_wens_234_T_1 & ~_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_234_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_235_ppm ( + .s2_new_bit_0_sel (_ghv_wens_235_T_1 & ~_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hEC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_235_T & ~_ghv_wens_235_T_1 & ~_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_235_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_236_ppm ( + .s2_new_bit_0_sel (_ghv_wens_236_T_1 & ~_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hED + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_236_T & ~_ghv_wens_236_T_1 & ~_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hED & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hED & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hED + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_236_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_237_ppm ( + .s2_new_bit_0_sel (_ghv_wens_237_T_1 & ~_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hEE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_237_T & ~_ghv_wens_237_T_1 & ~_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hED + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_237_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_238_ppm ( + .s2_new_bit_0_sel (_ghv_wens_238_T_1 & ~_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hEF + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_238_T & ~_ghv_wens_238_T_1 & ~_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hEF & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hEF & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEF + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_238_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_239_ppm ( + .s2_new_bit_0_sel (_ghv_wens_239_T_1 & ~_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF0 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_239_T & ~_ghv_wens_239_T_1 & ~_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF0 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF0 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hEF + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF0 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_239_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_240_ppm ( + .s2_new_bit_0_sel (_ghv_wens_240_T_1 & ~_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF1 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_240_T & ~_ghv_wens_240_T_1 & ~_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF1 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF1 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF0 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF1 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_240_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_241_ppm ( + .s2_new_bit_0_sel (_ghv_wens_241_T_1 & ~_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF2 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_241_T & ~_ghv_wens_241_T_1 & ~_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF2 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF2 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF1 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF2 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_241_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_242_ppm ( + .s2_new_bit_0_sel (_ghv_wens_242_T_1 & ~_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF3 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_242_T & ~_ghv_wens_242_T_1 & ~_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF3 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF3 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF2 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF3 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_242_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_243_ppm ( + .s2_new_bit_0_sel (_ghv_wens_243_T_1 & ~_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF4 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_243_T & ~_ghv_wens_243_T_1 & ~_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF4 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF4 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF3 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF4 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_243_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_244_ppm ( + .s2_new_bit_0_sel (_ghv_wens_244_T_1 & ~_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF5 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_244_T & ~_ghv_wens_244_T_1 & ~_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF5 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF5 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF4 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF5 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_244_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_245_ppm ( + .s2_new_bit_0_sel (_ghv_wens_245_T_1 & ~_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF6 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_245_T & ~_ghv_wens_245_T_1 & ~_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF6 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF6 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF5 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF6 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_245_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_246_ppm ( + .s2_new_bit_0_sel (_ghv_wens_246_T_1 & ~_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF7 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_246_T & ~_ghv_wens_246_T_1 & ~_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF7 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF7 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF6 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF7 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_246_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_247_ppm ( + .s2_new_bit_0_sel (_ghv_wens_247_T_1 & ~_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF8 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_247_T & ~_ghv_wens_247_T_1 & ~_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF8 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF8 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF7 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF8 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_247_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_248_ppm ( + .s2_new_bit_0_sel (_ghv_wens_248_T_1 & ~_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hF9 + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_248_T & ~_ghv_wens_248_T_1 & ~_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hF9 & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hF9 & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF8 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF9 + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_248_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_249_ppm ( + .s2_new_bit_0_sel (_ghv_wens_249_T_1 & ~_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hFA + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_249_T & ~_ghv_wens_249_T_1 & ~_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFA & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFA & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hF9 + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFA + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_249_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_250_ppm ( + .s2_new_bit_0_sel (_ghv_wens_250_T_1 & ~_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hFB + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_250_T & ~_ghv_wens_250_T_1 & ~_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFB & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFB & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFA + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFB + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_250_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_251_ppm ( + .s2_new_bit_0_sel (_ghv_wens_251_T_1 & ~_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hFC + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_251_T & ~_ghv_wens_251_T_1 & ~_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFC & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFC & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFB + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFC + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_251_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_252_ppm ( + .s2_new_bit_0_sel (_ghv_wens_252_T_1 & ~_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hFD + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_252_T & ~_ghv_wens_252_T_1 & ~_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFD & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFD & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFC + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFD + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_252_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_253_ppm ( + .s2_new_bit_0_sel (_ghv_wens_253_T_1 & ~_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | s2_ghist_ptr_dup_0_value == 8'hFE + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_253_T & ~_ghv_wens_253_T_1 & ~_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | s1_ghist_ptr_dup_0_value == 8'hFE & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | s3_ghist_ptr_dup_0_value == 8'hFE & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFD + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFE + & shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_253_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_254_ppm ( + .s2_new_bit_0_sel (_ghv_wens_254_T_1 & ~_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), + .s2_new_bit_0_src + (s2_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | (&s2_ghist_ptr_dup_0_value) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_254_T & ~_ghv_wens_254_T_1 & ~_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), + .s1_new_bit_0_src + (s1_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | (&s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), + .s3_new_bit_0_src + (s3_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | (&s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + (do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value == 8'hFE + & shouldShiftVec_dup_0_0 & real_br_taken_mask_dup_0_0 + | (&do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_254_ppm_out_res) + ); + PriorityMuxModule_20 ghv_write_datas_255_ppm ( + .s2_new_bit_0_sel (_ghv_wens_255_T_1 & ~_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), + .s2_new_bit_0_src + ((&s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0 + & _cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit + | ~(|s2_ghist_ptr_dup_0_value) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_56 + & ~(_cfiIndex_bits_T_261 & _predictors_io_out_s2_full_pred_0_hit) + & _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 + & _predictors_io_out_s2_full_pred_0_is_br_sharing + & _predictors_io_out_s2_full_pred_0_hit), + .s1_new_bit_0_sel + (_ghv_wens_255_T & ~_ghv_wens_255_T_1 & ~_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), + .s1_new_bit_0_src + ((&s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0 + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & (s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit + | ~_s1_ghv_wdatas_T_190528) & _predictors_io_out_s1_full_pred_0_hit + | ~(|s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_T_190528 + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & (_predictors_io_out_s1_full_pred_0_slot_valids_0 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_0 + & _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_T_190528 + & _predictors_io_out_s1_full_pred_0_br_taken_mask_1 + & _predictors_io_out_s1_full_pred_0_hit) + & ~(s1_pred_info_takenMask_0_0 & _predictors_io_out_s1_full_pred_0_hit) + & _predictors_io_out_s1_full_pred_0_hit), + .s3_new_bit_0_sel (_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), + .s3_new_bit_0_src + ((&s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0 + & _s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit + | ~(|s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_T_57998 + & ~(_s3_redirect_on_jalr_target_dup_T_8 & _predictors_io_out_s3_full_pred_0_hit) + & _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing + & _predictors_io_out_s3_full_pred_0_hit), + .redirect_new_bit_0_src + ((&do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0 + & real_br_taken_mask_dup_0_0 + | ~(|do_redirect_dup_next_bits_r_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_1 + & real_br_taken_mask_dup_0_1), + .out_res (_ghv_write_datas_255_ppm_out_res) + ); + assign io_bpu_to_ftq_resp_valid = + s1_valid_dup_3 | s2_valid_dup_3 & s2_redirect_dup_2 | s3_valid_dup_3 + & s3_redirect_dup_2; + assign io_bpu_to_ftq_resp_bits_s1_pc_3 = _predictors_io_out_s1_pc_3; + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_0 = + _predictors_io_out_s1_full_pred_3_br_taken_mask_0; + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_1 = + _predictors_io_out_s1_full_pred_3_br_taken_mask_1; + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_0 = + _predictors_io_out_s1_full_pred_3_slot_valids_0; + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_1 = + _predictors_io_out_s1_full_pred_3_slot_valids_1; + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_0 = + _predictors_io_out_s1_full_pred_3_targets_0; + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_1 = + _predictors_io_out_s1_full_pred_3_targets_1; + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_0 = + _predictors_io_out_s1_full_pred_3_offsets_0; + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_1 = + _predictors_io_out_s1_full_pred_3_offsets_1; + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughAddr = + _predictors_io_out_s1_full_pred_3_fallThroughAddr; + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_is_br_sharing = + _predictors_io_out_s1_full_pred_3_is_br_sharing; + assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_hit = + _predictors_io_out_s1_full_pred_3_hit; + assign io_bpu_to_ftq_resp_bits_s2_pc_3 = _predictors_io_out_s2_pc_3; + assign io_bpu_to_ftq_resp_bits_s2_valid_3 = s2_valid_dup_3 & ~s2_flush_dup_3; + assign io_bpu_to_ftq_resp_bits_s2_hasRedirect_3 = s2_redirect_dup_3; + assign io_bpu_to_ftq_resp_bits_s2_ftq_idx_flag = s2_ftq_idx_flag; + assign io_bpu_to_ftq_resp_bits_s2_ftq_idx_value = s2_ftq_idx_value; + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_0 = + _predictors_io_out_s2_full_pred_3_br_taken_mask_0; + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_1 = + _predictors_io_out_s2_full_pred_3_br_taken_mask_1; + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_0 = + _predictors_io_out_s2_full_pred_3_slot_valids_0; + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_1 = + _predictors_io_out_s2_full_pred_3_slot_valids_1; + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_0 = + _predictors_io_out_s2_full_pred_3_targets_0; + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_1 = + _predictors_io_out_s2_full_pred_3_targets_1; + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_0 = + _predictors_io_out_s2_full_pred_3_offsets_0; + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_1 = + _predictors_io_out_s2_full_pred_3_offsets_1; + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughAddr = + _predictors_io_out_s2_full_pred_3_fallThroughAddr; + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_is_br_sharing = + _predictors_io_out_s2_full_pred_3_is_br_sharing; + assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_hit = + _predictors_io_out_s2_full_pred_3_hit; + assign io_bpu_to_ftq_resp_bits_s3_pc_3 = _predictors_io_out_s3_pc_3; + assign io_bpu_to_ftq_resp_bits_s3_valid_3 = + s3_valid_dup_3 & ~io_ftq_to_bpu_redirect_valid; + assign io_bpu_to_ftq_resp_bits_s3_hasRedirect_3 = s3_redirect_dup_3; + assign io_bpu_to_ftq_resp_bits_s3_ftq_idx_flag = s3_ftq_idx_flag; + assign io_bpu_to_ftq_resp_bits_s3_ftq_idx_value = s3_ftq_idx_value; + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_0 = + _predictors_io_out_s3_full_pred_3_br_taken_mask_0; + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_1 = + _predictors_io_out_s3_full_pred_3_br_taken_mask_1; + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_0 = + _predictors_io_out_s3_full_pred_3_slot_valids_0; + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_1 = + _predictors_io_out_s3_full_pred_3_slot_valids_1; + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_0 = + _predictors_io_out_s3_full_pred_3_targets_0; + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_1 = + _predictors_io_out_s3_full_pred_3_targets_1; + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughAddr = + _predictors_io_out_s3_full_pred_3_fallThroughAddr; + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughErr = + _predictors_io_out_s3_full_pred_3_fallThroughErr; + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_is_br_sharing = + _predictors_io_out_s3_full_pred_3_is_br_sharing; + assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_hit = + _predictors_io_out_s3_full_pred_3_hit; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_17_folded_hist = + s3_folded_gh_dup_2_hist_17_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_16_folded_hist = + s3_folded_gh_dup_2_hist_16_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_15_folded_hist = + s3_folded_gh_dup_2_hist_15_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_14_folded_hist = + s3_folded_gh_dup_2_hist_14_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_13_folded_hist = + s3_folded_gh_dup_2_hist_13_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_12_folded_hist = + s3_folded_gh_dup_2_hist_12_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_11_folded_hist = + s3_folded_gh_dup_2_hist_11_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_10_folded_hist = + s3_folded_gh_dup_2_hist_10_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_9_folded_hist = + s3_folded_gh_dup_2_hist_9_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_8_folded_hist = + s3_folded_gh_dup_2_hist_8_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_7_folded_hist = + s3_folded_gh_dup_2_hist_7_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_6_folded_hist = + s3_folded_gh_dup_2_hist_6_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_5_folded_hist = + s3_folded_gh_dup_2_hist_5_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_4_folded_hist = + s3_folded_gh_dup_2_hist_4_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_3_folded_hist = + s3_folded_gh_dup_2_hist_3_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_2_folded_hist = + s3_folded_gh_dup_2_hist_2_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_1_folded_hist = + s3_folded_gh_dup_2_hist_1_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_0_folded_hist = + s3_folded_gh_dup_2_hist_0_folded_hist; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_0 = + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_1 = + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_2 = + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_3 = + s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_0 = + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_1 = + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_2 = + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_3 = + s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_0 = + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_1 = + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_2 = + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_3 = + s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_0 = + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_1 = + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_2 = + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_3 = + s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_0 = + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_1 = + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_2 = + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_3 = + s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_0 = + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_1 = + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_2 = + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_3 = + s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_lastBrNumOH = + s3_last_br_num_oh_dup_2; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_flag = + s3_ghist_ptr_dup_2_flag; + assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_value = + s3_ghist_ptr_dup_2_value; + assign io_perf_0_value = io_perf_0_value_REG_1; + assign io_perf_1_value = io_perf_1_value_REG_1; + assign io_perf_2_value = io_perf_2_value_REG_1; + assign io_perf_3_value = io_perf_3_value_REG_1; + assign io_perf_4_value = io_perf_4_value_REG_1; + assign io_perf_5_value = io_perf_5_value_REG_1; + assign io_perf_6_value = io_perf_6_value_REG_1; +endmodule + diff --git a/rtl/BPUTop/PriorityMuxModule.sv b/rtl/BPUTop/PriorityMuxModule.sv new file mode 100644 index 0000000..bf4e801 --- /dev/null +++ b/rtl/BPUTop/PriorityMuxModule.sv @@ -0,0 +1,80 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module PriorityMuxModule( + input s2_target_sel, + input [40:0] s2_target_src, + input s1_target_sel, + input [40:0] s1_target_src, + input s3_target_sel, + input [40:0] s3_target_src, + input redirect_target_sel, + input [40:0] redirect_target_src, + input [40:0] stallPC_src, + output [40:0] out_res +); + + assign out_res = + s2_target_sel + ? s2_target_src + : s1_target_sel + ? s1_target_src + : s3_target_sel + ? s3_target_src + : redirect_target_sel ? redirect_target_src : stallPC_src; +endmodule + diff --git a/rtl/BPUTop/PriorityMuxModule_12.sv b/rtl/BPUTop/PriorityMuxModule_12.sv new file mode 100644 index 0000000..bc6bf32 --- /dev/null +++ b/rtl/BPUTop/PriorityMuxModule_12.sv @@ -0,0 +1,450 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module PriorityMuxModule_12( + input s2_AFHOB_sel, + input s2_AFHOB_src_afhob_5_bits_0, + input s2_AFHOB_src_afhob_5_bits_1, + input s2_AFHOB_src_afhob_5_bits_2, + input s2_AFHOB_src_afhob_5_bits_3, + input s2_AFHOB_src_afhob_4_bits_0, + input s2_AFHOB_src_afhob_4_bits_1, + input s2_AFHOB_src_afhob_4_bits_2, + input s2_AFHOB_src_afhob_4_bits_3, + input s2_AFHOB_src_afhob_3_bits_0, + input s2_AFHOB_src_afhob_3_bits_1, + input s2_AFHOB_src_afhob_3_bits_2, + input s2_AFHOB_src_afhob_3_bits_3, + input s2_AFHOB_src_afhob_2_bits_0, + input s2_AFHOB_src_afhob_2_bits_1, + input s2_AFHOB_src_afhob_2_bits_2, + input s2_AFHOB_src_afhob_2_bits_3, + input s2_AFHOB_src_afhob_1_bits_0, + input s2_AFHOB_src_afhob_1_bits_1, + input s2_AFHOB_src_afhob_1_bits_2, + input s2_AFHOB_src_afhob_1_bits_3, + input s2_AFHOB_src_afhob_0_bits_0, + input s2_AFHOB_src_afhob_0_bits_1, + input s2_AFHOB_src_afhob_0_bits_2, + input s2_AFHOB_src_afhob_0_bits_3, + input s1_AFHOB_sel, + input s1_AFHOB_src_afhob_5_bits_0, + input s1_AFHOB_src_afhob_5_bits_1, + input s1_AFHOB_src_afhob_5_bits_2, + input s1_AFHOB_src_afhob_5_bits_3, + input s1_AFHOB_src_afhob_4_bits_0, + input s1_AFHOB_src_afhob_4_bits_1, + input s1_AFHOB_src_afhob_4_bits_2, + input s1_AFHOB_src_afhob_4_bits_3, + input s1_AFHOB_src_afhob_3_bits_0, + input s1_AFHOB_src_afhob_3_bits_1, + input s1_AFHOB_src_afhob_3_bits_2, + input s1_AFHOB_src_afhob_3_bits_3, + input s1_AFHOB_src_afhob_2_bits_0, + input s1_AFHOB_src_afhob_2_bits_1, + input s1_AFHOB_src_afhob_2_bits_2, + input s1_AFHOB_src_afhob_2_bits_3, + input s1_AFHOB_src_afhob_1_bits_0, + input s1_AFHOB_src_afhob_1_bits_1, + input s1_AFHOB_src_afhob_1_bits_2, + input s1_AFHOB_src_afhob_1_bits_3, + input s1_AFHOB_src_afhob_0_bits_0, + input s1_AFHOB_src_afhob_0_bits_1, + input s1_AFHOB_src_afhob_0_bits_2, + input s1_AFHOB_src_afhob_0_bits_3, + input s3_AFHOB_sel, + input s3_AFHOB_src_afhob_5_bits_0, + input s3_AFHOB_src_afhob_5_bits_1, + input s3_AFHOB_src_afhob_5_bits_2, + input s3_AFHOB_src_afhob_5_bits_3, + input s3_AFHOB_src_afhob_4_bits_0, + input s3_AFHOB_src_afhob_4_bits_1, + input s3_AFHOB_src_afhob_4_bits_2, + input s3_AFHOB_src_afhob_4_bits_3, + input s3_AFHOB_src_afhob_3_bits_0, + input s3_AFHOB_src_afhob_3_bits_1, + input s3_AFHOB_src_afhob_3_bits_2, + input s3_AFHOB_src_afhob_3_bits_3, + input s3_AFHOB_src_afhob_2_bits_0, + input s3_AFHOB_src_afhob_2_bits_1, + input s3_AFHOB_src_afhob_2_bits_2, + input s3_AFHOB_src_afhob_2_bits_3, + input s3_AFHOB_src_afhob_1_bits_0, + input s3_AFHOB_src_afhob_1_bits_1, + input s3_AFHOB_src_afhob_1_bits_2, + input s3_AFHOB_src_afhob_1_bits_3, + input s3_AFHOB_src_afhob_0_bits_0, + input s3_AFHOB_src_afhob_0_bits_1, + input s3_AFHOB_src_afhob_0_bits_2, + input s3_AFHOB_src_afhob_0_bits_3, + input redirect_AFHOB_sel, + input redirect_AFHOB_src_afhob_5_bits_0, + input redirect_AFHOB_src_afhob_5_bits_1, + input redirect_AFHOB_src_afhob_5_bits_2, + input redirect_AFHOB_src_afhob_5_bits_3, + input redirect_AFHOB_src_afhob_4_bits_0, + input redirect_AFHOB_src_afhob_4_bits_1, + input redirect_AFHOB_src_afhob_4_bits_2, + input redirect_AFHOB_src_afhob_4_bits_3, + input redirect_AFHOB_src_afhob_3_bits_0, + input redirect_AFHOB_src_afhob_3_bits_1, + input redirect_AFHOB_src_afhob_3_bits_2, + input redirect_AFHOB_src_afhob_3_bits_3, + input redirect_AFHOB_src_afhob_2_bits_0, + input redirect_AFHOB_src_afhob_2_bits_1, + input redirect_AFHOB_src_afhob_2_bits_2, + input redirect_AFHOB_src_afhob_2_bits_3, + input redirect_AFHOB_src_afhob_1_bits_0, + input redirect_AFHOB_src_afhob_1_bits_1, + input redirect_AFHOB_src_afhob_1_bits_2, + input redirect_AFHOB_src_afhob_1_bits_3, + input redirect_AFHOB_src_afhob_0_bits_0, + input redirect_AFHOB_src_afhob_0_bits_1, + input redirect_AFHOB_src_afhob_0_bits_2, + input redirect_AFHOB_src_afhob_0_bits_3, + input stallAFHOB_src_afhob_5_bits_0, + input stallAFHOB_src_afhob_5_bits_1, + input stallAFHOB_src_afhob_5_bits_2, + input stallAFHOB_src_afhob_5_bits_3, + input stallAFHOB_src_afhob_4_bits_0, + input stallAFHOB_src_afhob_4_bits_1, + input stallAFHOB_src_afhob_4_bits_2, + input stallAFHOB_src_afhob_4_bits_3, + input stallAFHOB_src_afhob_3_bits_0, + input stallAFHOB_src_afhob_3_bits_1, + input stallAFHOB_src_afhob_3_bits_2, + input stallAFHOB_src_afhob_3_bits_3, + input stallAFHOB_src_afhob_2_bits_0, + input stallAFHOB_src_afhob_2_bits_1, + input stallAFHOB_src_afhob_2_bits_2, + input stallAFHOB_src_afhob_2_bits_3, + input stallAFHOB_src_afhob_1_bits_0, + input stallAFHOB_src_afhob_1_bits_1, + input stallAFHOB_src_afhob_1_bits_2, + input stallAFHOB_src_afhob_1_bits_3, + input stallAFHOB_src_afhob_0_bits_0, + input stallAFHOB_src_afhob_0_bits_1, + input stallAFHOB_src_afhob_0_bits_2, + input stallAFHOB_src_afhob_0_bits_3, + output out_res_afhob_5_bits_0, + output out_res_afhob_5_bits_1, + output out_res_afhob_5_bits_2, + output out_res_afhob_5_bits_3, + output out_res_afhob_4_bits_0, + output out_res_afhob_4_bits_1, + output out_res_afhob_4_bits_2, + output out_res_afhob_4_bits_3, + output out_res_afhob_3_bits_0, + output out_res_afhob_3_bits_1, + output out_res_afhob_3_bits_2, + output out_res_afhob_3_bits_3, + output out_res_afhob_2_bits_0, + output out_res_afhob_2_bits_1, + output out_res_afhob_2_bits_2, + output out_res_afhob_2_bits_3, + output out_res_afhob_1_bits_0, + output out_res_afhob_1_bits_1, + output out_res_afhob_1_bits_2, + output out_res_afhob_1_bits_3, + output out_res_afhob_0_bits_0, + output out_res_afhob_0_bits_1, + output out_res_afhob_0_bits_2, + output out_res_afhob_0_bits_3 +); + + assign out_res_afhob_5_bits_0 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_5_bits_0 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_5_bits_0 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_5_bits_0 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_5_bits_0 + : stallAFHOB_src_afhob_5_bits_0; + assign out_res_afhob_5_bits_1 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_5_bits_1 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_5_bits_1 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_5_bits_1 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_5_bits_1 + : stallAFHOB_src_afhob_5_bits_1; + assign out_res_afhob_5_bits_2 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_5_bits_2 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_5_bits_2 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_5_bits_2 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_5_bits_2 + : stallAFHOB_src_afhob_5_bits_2; + assign out_res_afhob_5_bits_3 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_5_bits_3 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_5_bits_3 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_5_bits_3 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_5_bits_3 + : stallAFHOB_src_afhob_5_bits_3; + assign out_res_afhob_4_bits_0 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_4_bits_0 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_4_bits_0 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_4_bits_0 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_4_bits_0 + : stallAFHOB_src_afhob_4_bits_0; + assign out_res_afhob_4_bits_1 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_4_bits_1 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_4_bits_1 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_4_bits_1 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_4_bits_1 + : stallAFHOB_src_afhob_4_bits_1; + assign out_res_afhob_4_bits_2 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_4_bits_2 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_4_bits_2 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_4_bits_2 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_4_bits_2 + : stallAFHOB_src_afhob_4_bits_2; + assign out_res_afhob_4_bits_3 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_4_bits_3 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_4_bits_3 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_4_bits_3 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_4_bits_3 + : stallAFHOB_src_afhob_4_bits_3; + assign out_res_afhob_3_bits_0 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_3_bits_0 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_3_bits_0 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_3_bits_0 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_3_bits_0 + : stallAFHOB_src_afhob_3_bits_0; + assign out_res_afhob_3_bits_1 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_3_bits_1 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_3_bits_1 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_3_bits_1 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_3_bits_1 + : stallAFHOB_src_afhob_3_bits_1; + assign out_res_afhob_3_bits_2 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_3_bits_2 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_3_bits_2 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_3_bits_2 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_3_bits_2 + : stallAFHOB_src_afhob_3_bits_2; + assign out_res_afhob_3_bits_3 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_3_bits_3 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_3_bits_3 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_3_bits_3 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_3_bits_3 + : stallAFHOB_src_afhob_3_bits_3; + assign out_res_afhob_2_bits_0 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_2_bits_0 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_2_bits_0 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_2_bits_0 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_2_bits_0 + : stallAFHOB_src_afhob_2_bits_0; + assign out_res_afhob_2_bits_1 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_2_bits_1 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_2_bits_1 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_2_bits_1 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_2_bits_1 + : stallAFHOB_src_afhob_2_bits_1; + assign out_res_afhob_2_bits_2 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_2_bits_2 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_2_bits_2 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_2_bits_2 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_2_bits_2 + : stallAFHOB_src_afhob_2_bits_2; + assign out_res_afhob_2_bits_3 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_2_bits_3 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_2_bits_3 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_2_bits_3 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_2_bits_3 + : stallAFHOB_src_afhob_2_bits_3; + assign out_res_afhob_1_bits_0 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_1_bits_0 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_1_bits_0 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_1_bits_0 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_1_bits_0 + : stallAFHOB_src_afhob_1_bits_0; + assign out_res_afhob_1_bits_1 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_1_bits_1 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_1_bits_1 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_1_bits_1 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_1_bits_1 + : stallAFHOB_src_afhob_1_bits_1; + assign out_res_afhob_1_bits_2 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_1_bits_2 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_1_bits_2 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_1_bits_2 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_1_bits_2 + : stallAFHOB_src_afhob_1_bits_2; + assign out_res_afhob_1_bits_3 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_1_bits_3 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_1_bits_3 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_1_bits_3 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_1_bits_3 + : stallAFHOB_src_afhob_1_bits_3; + assign out_res_afhob_0_bits_0 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_0_bits_0 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_0_bits_0 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_0_bits_0 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_0_bits_0 + : stallAFHOB_src_afhob_0_bits_0; + assign out_res_afhob_0_bits_1 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_0_bits_1 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_0_bits_1 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_0_bits_1 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_0_bits_1 + : stallAFHOB_src_afhob_0_bits_1; + assign out_res_afhob_0_bits_2 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_0_bits_2 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_0_bits_2 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_0_bits_2 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_0_bits_2 + : stallAFHOB_src_afhob_0_bits_2; + assign out_res_afhob_0_bits_3 = + s2_AFHOB_sel + ? s2_AFHOB_src_afhob_0_bits_3 + : s1_AFHOB_sel + ? s1_AFHOB_src_afhob_0_bits_3 + : s3_AFHOB_sel + ? s3_AFHOB_src_afhob_0_bits_3 + : redirect_AFHOB_sel + ? redirect_AFHOB_src_afhob_0_bits_3 + : stallAFHOB_src_afhob_0_bits_3; +endmodule + diff --git a/rtl/BPUTop/PriorityMuxModule_16.sv b/rtl/BPUTop/PriorityMuxModule_16.sv new file mode 100644 index 0000000..acbf06b --- /dev/null +++ b/rtl/BPUTop/PriorityMuxModule_16.sv @@ -0,0 +1,80 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module PriorityMuxModule_16( + input s2_BrNumOH_sel, + input [2:0] s2_BrNumOH_src, + input s1_BrNumOH_sel, + input [2:0] s1_BrNumOH_src, + input s3_BrNumOH_sel, + input [2:0] s3_BrNumOH_src, + input redirect_BrNumOH_sel, + input [2:0] redirect_BrNumOH_src, + input [2:0] stallBrNumOH_src, + output [2:0] out_res +); + + assign out_res = + s2_BrNumOH_sel + ? s2_BrNumOH_src + : s1_BrNumOH_sel + ? s1_BrNumOH_src + : s3_BrNumOH_sel + ? s3_BrNumOH_src + : redirect_BrNumOH_sel ? redirect_BrNumOH_src : stallBrNumOH_src; +endmodule + diff --git a/rtl/BPUTop/PriorityMuxModule_20.sv b/rtl/BPUTop/PriorityMuxModule_20.sv new file mode 100644 index 0000000..5f50222 --- /dev/null +++ b/rtl/BPUTop/PriorityMuxModule_20.sv @@ -0,0 +1,76 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module PriorityMuxModule_20( + input s2_new_bit_0_sel, + input s2_new_bit_0_src, + input s1_new_bit_0_sel, + input s1_new_bit_0_src, + input s3_new_bit_0_sel, + input s3_new_bit_0_src, + input redirect_new_bit_0_src, + output out_res +); + + assign out_res = + s2_new_bit_0_sel + ? s2_new_bit_0_src + : s1_new_bit_0_sel + ? s1_new_bit_0_src + : s3_new_bit_0_sel ? s3_new_bit_0_src : redirect_new_bit_0_src; +endmodule + diff --git a/rtl/BPUTop/PriorityMuxModule_4.sv b/rtl/BPUTop/PriorityMuxModule_4.sv new file mode 100644 index 0000000..f676fc0 --- /dev/null +++ b/rtl/BPUTop/PriorityMuxModule_4.sv @@ -0,0 +1,354 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module PriorityMuxModule_4( + input s2_FGH_sel, + input [10:0] s2_FGH_src_hist_17_folded_hist, + input [10:0] s2_FGH_src_hist_16_folded_hist, + input [6:0] s2_FGH_src_hist_15_folded_hist, + input [7:0] s2_FGH_src_hist_14_folded_hist, + input [8:0] s2_FGH_src_hist_13_folded_hist, + input [3:0] s2_FGH_src_hist_12_folded_hist, + input [7:0] s2_FGH_src_hist_11_folded_hist, + input [8:0] s2_FGH_src_hist_10_folded_hist, + input [6:0] s2_FGH_src_hist_9_folded_hist, + input [7:0] s2_FGH_src_hist_8_folded_hist, + input [6:0] s2_FGH_src_hist_7_folded_hist, + input [8:0] s2_FGH_src_hist_6_folded_hist, + input [6:0] s2_FGH_src_hist_5_folded_hist, + input [7:0] s2_FGH_src_hist_4_folded_hist, + input [7:0] s2_FGH_src_hist_3_folded_hist, + input [7:0] s2_FGH_src_hist_2_folded_hist, + input [10:0] s2_FGH_src_hist_1_folded_hist, + input [7:0] s2_FGH_src_hist_0_folded_hist, + input s1_FGH_sel, + input [10:0] s1_FGH_src_hist_17_folded_hist, + input [10:0] s1_FGH_src_hist_16_folded_hist, + input [6:0] s1_FGH_src_hist_15_folded_hist, + input [7:0] s1_FGH_src_hist_14_folded_hist, + input [8:0] s1_FGH_src_hist_13_folded_hist, + input [3:0] s1_FGH_src_hist_12_folded_hist, + input [7:0] s1_FGH_src_hist_11_folded_hist, + input [8:0] s1_FGH_src_hist_10_folded_hist, + input [6:0] s1_FGH_src_hist_9_folded_hist, + input [7:0] s1_FGH_src_hist_8_folded_hist, + input [6:0] s1_FGH_src_hist_7_folded_hist, + input [8:0] s1_FGH_src_hist_6_folded_hist, + input [6:0] s1_FGH_src_hist_5_folded_hist, + input [7:0] s1_FGH_src_hist_4_folded_hist, + input [7:0] s1_FGH_src_hist_3_folded_hist, + input [7:0] s1_FGH_src_hist_2_folded_hist, + input [10:0] s1_FGH_src_hist_1_folded_hist, + input [7:0] s1_FGH_src_hist_0_folded_hist, + input s3_FGH_sel, + input [10:0] s3_FGH_src_hist_17_folded_hist, + input [10:0] s3_FGH_src_hist_16_folded_hist, + input [6:0] s3_FGH_src_hist_15_folded_hist, + input [7:0] s3_FGH_src_hist_14_folded_hist, + input [8:0] s3_FGH_src_hist_13_folded_hist, + input [3:0] s3_FGH_src_hist_12_folded_hist, + input [7:0] s3_FGH_src_hist_11_folded_hist, + input [8:0] s3_FGH_src_hist_10_folded_hist, + input [6:0] s3_FGH_src_hist_9_folded_hist, + input [7:0] s3_FGH_src_hist_8_folded_hist, + input [6:0] s3_FGH_src_hist_7_folded_hist, + input [8:0] s3_FGH_src_hist_6_folded_hist, + input [6:0] s3_FGH_src_hist_5_folded_hist, + input [7:0] s3_FGH_src_hist_4_folded_hist, + input [7:0] s3_FGH_src_hist_3_folded_hist, + input [7:0] s3_FGH_src_hist_2_folded_hist, + input [10:0] s3_FGH_src_hist_1_folded_hist, + input [7:0] s3_FGH_src_hist_0_folded_hist, + input redirect_FGHT_sel, + input [10:0] redirect_FGHT_src_hist_17_folded_hist, + input [10:0] redirect_FGHT_src_hist_16_folded_hist, + input [6:0] redirect_FGHT_src_hist_15_folded_hist, + input [7:0] redirect_FGHT_src_hist_14_folded_hist, + input [8:0] redirect_FGHT_src_hist_13_folded_hist, + input [3:0] redirect_FGHT_src_hist_12_folded_hist, + input [7:0] redirect_FGHT_src_hist_11_folded_hist, + input [8:0] redirect_FGHT_src_hist_10_folded_hist, + input [6:0] redirect_FGHT_src_hist_9_folded_hist, + input [7:0] redirect_FGHT_src_hist_8_folded_hist, + input [6:0] redirect_FGHT_src_hist_7_folded_hist, + input [8:0] redirect_FGHT_src_hist_6_folded_hist, + input [6:0] redirect_FGHT_src_hist_5_folded_hist, + input [7:0] redirect_FGHT_src_hist_4_folded_hist, + input [7:0] redirect_FGHT_src_hist_3_folded_hist, + input [7:0] redirect_FGHT_src_hist_2_folded_hist, + input [10:0] redirect_FGHT_src_hist_1_folded_hist, + input [7:0] redirect_FGHT_src_hist_0_folded_hist, + input [10:0] stallFGH_src_hist_17_folded_hist, + input [10:0] stallFGH_src_hist_16_folded_hist, + input [6:0] stallFGH_src_hist_15_folded_hist, + input [7:0] stallFGH_src_hist_14_folded_hist, + input [8:0] stallFGH_src_hist_13_folded_hist, + input [3:0] stallFGH_src_hist_12_folded_hist, + input [7:0] stallFGH_src_hist_11_folded_hist, + input [8:0] stallFGH_src_hist_10_folded_hist, + input [6:0] stallFGH_src_hist_9_folded_hist, + input [7:0] stallFGH_src_hist_8_folded_hist, + input [6:0] stallFGH_src_hist_7_folded_hist, + input [8:0] stallFGH_src_hist_6_folded_hist, + input [6:0] stallFGH_src_hist_5_folded_hist, + input [7:0] stallFGH_src_hist_4_folded_hist, + input [7:0] stallFGH_src_hist_3_folded_hist, + input [7:0] stallFGH_src_hist_2_folded_hist, + input [10:0] stallFGH_src_hist_1_folded_hist, + input [7:0] stallFGH_src_hist_0_folded_hist, + output [10:0] out_res_hist_17_folded_hist, + output [10:0] out_res_hist_16_folded_hist, + output [6:0] out_res_hist_15_folded_hist, + output [7:0] out_res_hist_14_folded_hist, + output [8:0] out_res_hist_13_folded_hist, + output [3:0] out_res_hist_12_folded_hist, + output [7:0] out_res_hist_11_folded_hist, + output [8:0] out_res_hist_10_folded_hist, + output [6:0] out_res_hist_9_folded_hist, + output [7:0] out_res_hist_8_folded_hist, + output [6:0] out_res_hist_7_folded_hist, + output [8:0] out_res_hist_6_folded_hist, + output [6:0] out_res_hist_5_folded_hist, + output [7:0] out_res_hist_4_folded_hist, + output [7:0] out_res_hist_3_folded_hist, + output [7:0] out_res_hist_2_folded_hist, + output [10:0] out_res_hist_1_folded_hist, + output [7:0] out_res_hist_0_folded_hist +); + + assign out_res_hist_17_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_17_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_17_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_17_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_17_folded_hist + : stallFGH_src_hist_17_folded_hist; + assign out_res_hist_16_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_16_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_16_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_16_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_16_folded_hist + : stallFGH_src_hist_16_folded_hist; + assign out_res_hist_15_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_15_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_15_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_15_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_15_folded_hist + : stallFGH_src_hist_15_folded_hist; + assign out_res_hist_14_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_14_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_14_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_14_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_14_folded_hist + : stallFGH_src_hist_14_folded_hist; + assign out_res_hist_13_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_13_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_13_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_13_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_13_folded_hist + : stallFGH_src_hist_13_folded_hist; + assign out_res_hist_12_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_12_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_12_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_12_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_12_folded_hist + : stallFGH_src_hist_12_folded_hist; + assign out_res_hist_11_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_11_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_11_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_11_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_11_folded_hist + : stallFGH_src_hist_11_folded_hist; + assign out_res_hist_10_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_10_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_10_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_10_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_10_folded_hist + : stallFGH_src_hist_10_folded_hist; + assign out_res_hist_9_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_9_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_9_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_9_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_9_folded_hist + : stallFGH_src_hist_9_folded_hist; + assign out_res_hist_8_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_8_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_8_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_8_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_8_folded_hist + : stallFGH_src_hist_8_folded_hist; + assign out_res_hist_7_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_7_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_7_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_7_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_7_folded_hist + : stallFGH_src_hist_7_folded_hist; + assign out_res_hist_6_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_6_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_6_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_6_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_6_folded_hist + : stallFGH_src_hist_6_folded_hist; + assign out_res_hist_5_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_5_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_5_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_5_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_5_folded_hist + : stallFGH_src_hist_5_folded_hist; + assign out_res_hist_4_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_4_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_4_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_4_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_4_folded_hist + : stallFGH_src_hist_4_folded_hist; + assign out_res_hist_3_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_3_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_3_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_3_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_3_folded_hist + : stallFGH_src_hist_3_folded_hist; + assign out_res_hist_2_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_2_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_2_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_2_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_2_folded_hist + : stallFGH_src_hist_2_folded_hist; + assign out_res_hist_1_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_1_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_1_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_1_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_1_folded_hist + : stallFGH_src_hist_1_folded_hist; + assign out_res_hist_0_folded_hist = + s2_FGH_sel + ? s2_FGH_src_hist_0_folded_hist + : s1_FGH_sel + ? s1_FGH_src_hist_0_folded_hist + : s3_FGH_sel + ? s3_FGH_src_hist_0_folded_hist + : redirect_FGHT_sel + ? redirect_FGHT_src_hist_0_folded_hist + : stallFGH_src_hist_0_folded_hist; +endmodule + diff --git a/rtl/BPUTop/PriorityMuxModule_8.sv b/rtl/BPUTop/PriorityMuxModule_8.sv new file mode 100644 index 0000000..ca6ab36 --- /dev/null +++ b/rtl/BPUTop/PriorityMuxModule_8.sv @@ -0,0 +1,94 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module PriorityMuxModule_8( + input s2_GHPtr_sel, + input s2_GHPtr_src_flag, + input [7:0] s2_GHPtr_src_value, + input s1_GHPtr_sel, + input s1_GHPtr_src_flag, + input [7:0] s1_GHPtr_src_value, + input s3_GHPtr_sel, + input s3_GHPtr_src_flag, + input [7:0] s3_GHPtr_src_value, + input redirect_GHPtr_sel, + input redirect_GHPtr_src_flag, + input [7:0] redirect_GHPtr_src_value, + input stallGHPtr_src_flag, + input [7:0] stallGHPtr_src_value, + output out_res_flag, + output [7:0] out_res_value +); + + assign out_res_flag = + s2_GHPtr_sel + ? s2_GHPtr_src_flag + : s1_GHPtr_sel + ? s1_GHPtr_src_flag + : s3_GHPtr_sel + ? s3_GHPtr_src_flag + : redirect_GHPtr_sel ? redirect_GHPtr_src_flag : stallGHPtr_src_flag; + assign out_res_value = + s2_GHPtr_sel + ? s2_GHPtr_src_value + : s1_GHPtr_sel + ? s1_GHPtr_src_value + : s3_GHPtr_sel + ? s3_GHPtr_src_value + : redirect_GHPtr_sel ? redirect_GHPtr_src_value : stallGHPtr_src_value; +endmodule + diff --git a/rtl/BPUTop/RAS.sv b/rtl/BPUTop/RAS.sv new file mode 100644 index 0000000..500e85a --- /dev/null +++ b/rtl/BPUTop/RAS.sv @@ -0,0 +1,883 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module RAS( + input clock, + input reset, + input [35:0] io_reset_vector, + input [40:0] io_in_bits_s0_pc_0, + input [40:0] io_in_bits_s0_pc_1, + input [40:0] io_in_bits_s0_pc_2, + input [40:0] io_in_bits_s0_pc_3, + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, + input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0, + input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_0, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_jalr_target, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_0, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr, + input io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing, + input io_in_bits_resp_in_0_s2_full_pred_0_hit, + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, + input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0, + input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_0, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_jalr_target, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_0, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr, + input io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing, + input io_in_bits_resp_in_0_s2_full_pred_1_hit, + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, + input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0, + input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_0, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_jalr_target, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_0, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr, + input io_in_bits_resp_in_0_s2_full_pred_2_is_jalr, + input io_in_bits_resp_in_0_s2_full_pred_2_is_call, + input io_in_bits_resp_in_0_s2_full_pred_2_is_ret, + input io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, + input io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing, + input io_in_bits_resp_in_0_s2_full_pred_2_hit, + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, + input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0, + input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_0, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_jalr_target, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_0, + input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_1, + input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr, + input io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr, + input io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing, + input io_in_bits_resp_in_0_s2_full_pred_3_hit, + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, + input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0, + input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_0, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_jalr_target, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr, + input io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr, + input io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing, + input io_in_bits_resp_in_0_s3_full_pred_0_hit, + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, + input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0, + input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_0, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_jalr_target, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr, + input io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr, + input io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing, + input io_in_bits_resp_in_0_s3_full_pred_1_hit, + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, + input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0, + input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_0, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_jalr_target, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr, + input io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr, + input io_in_bits_resp_in_0_s3_full_pred_2_is_jalr, + input io_in_bits_resp_in_0_s3_full_pred_2_is_call, + input io_in_bits_resp_in_0_s3_full_pred_2_is_ret, + input io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing, + input io_in_bits_resp_in_0_s3_full_pred_2_hit, + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, + input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0, + input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_0, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_jalr_target, + input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_0, + input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_1, + input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr, + input io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr, + input io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing, + input io_in_bits_resp_in_0_s3_full_pred_3_hit, + input io_in_bits_resp_in_0_last_stage_ftb_entry_valid, + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset, + input [11:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower, + input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat, + input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing, + input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid, + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset, + input [19:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower, + input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat, + input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing, + input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid, + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr, + input io_in_bits_resp_in_0_last_stage_ftb_entry_carry, + input io_in_bits_resp_in_0_last_stage_ftb_entry_isCall, + input io_in_bits_resp_in_0_last_stage_ftb_entry_isRet, + input io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr, + input io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call, + input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0, + input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1, + output [40:0] io_out_s2_pc_0, + output [40:0] io_out_s2_pc_1, + output [40:0] io_out_s2_pc_2, + output [40:0] io_out_s2_pc_3, + output io_out_s2_full_pred_0_br_taken_mask_0, + output io_out_s2_full_pred_0_br_taken_mask_1, + output io_out_s2_full_pred_0_slot_valids_0, + output io_out_s2_full_pred_0_slot_valids_1, + output [40:0] io_out_s2_full_pred_0_targets_0, + output [40:0] io_out_s2_full_pred_0_targets_1, + output [3:0] io_out_s2_full_pred_0_offsets_0, + output [3:0] io_out_s2_full_pred_0_offsets_1, + output [40:0] io_out_s2_full_pred_0_fallThroughAddr, + output io_out_s2_full_pred_0_is_br_sharing, + output io_out_s2_full_pred_0_hit, + output io_out_s2_full_pred_1_br_taken_mask_0, + output io_out_s2_full_pred_1_br_taken_mask_1, + output io_out_s2_full_pred_1_slot_valids_0, + output io_out_s2_full_pred_1_slot_valids_1, + output [40:0] io_out_s2_full_pred_1_targets_0, + output [40:0] io_out_s2_full_pred_1_targets_1, + output [3:0] io_out_s2_full_pred_1_offsets_0, + output [3:0] io_out_s2_full_pred_1_offsets_1, + output [40:0] io_out_s2_full_pred_1_fallThroughAddr, + output io_out_s2_full_pred_1_is_br_sharing, + output io_out_s2_full_pred_1_hit, + output io_out_s2_full_pred_2_br_taken_mask_0, + output io_out_s2_full_pred_2_br_taken_mask_1, + output io_out_s2_full_pred_2_slot_valids_0, + output io_out_s2_full_pred_2_slot_valids_1, + output [40:0] io_out_s2_full_pred_2_targets_0, + output [40:0] io_out_s2_full_pred_2_targets_1, + output [3:0] io_out_s2_full_pred_2_offsets_0, + output [3:0] io_out_s2_full_pred_2_offsets_1, + output [40:0] io_out_s2_full_pred_2_fallThroughAddr, + output io_out_s2_full_pred_2_is_br_sharing, + output io_out_s2_full_pred_2_hit, + output io_out_s2_full_pred_3_br_taken_mask_0, + output io_out_s2_full_pred_3_br_taken_mask_1, + output io_out_s2_full_pred_3_slot_valids_0, + output io_out_s2_full_pred_3_slot_valids_1, + output [40:0] io_out_s2_full_pred_3_targets_0, + output [40:0] io_out_s2_full_pred_3_targets_1, + output [3:0] io_out_s2_full_pred_3_offsets_0, + output [3:0] io_out_s2_full_pred_3_offsets_1, + output [40:0] io_out_s2_full_pred_3_fallThroughAddr, + output io_out_s2_full_pred_3_fallThroughErr, + output io_out_s2_full_pred_3_is_br_sharing, + output io_out_s2_full_pred_3_hit, + output [40:0] io_out_s3_pc_0, + output [40:0] io_out_s3_pc_1, + output [40:0] io_out_s3_pc_2, + output [40:0] io_out_s3_pc_3, + output io_out_s3_full_pred_0_br_taken_mask_0, + output io_out_s3_full_pred_0_br_taken_mask_1, + output io_out_s3_full_pred_0_slot_valids_0, + output io_out_s3_full_pred_0_slot_valids_1, + output [40:0] io_out_s3_full_pred_0_targets_0, + output [40:0] io_out_s3_full_pred_0_targets_1, + output [40:0] io_out_s3_full_pred_0_fallThroughAddr, + output io_out_s3_full_pred_0_fallThroughErr, + output io_out_s3_full_pred_0_is_br_sharing, + output io_out_s3_full_pred_0_hit, + output io_out_s3_full_pred_1_br_taken_mask_0, + output io_out_s3_full_pred_1_br_taken_mask_1, + output io_out_s3_full_pred_1_slot_valids_0, + output io_out_s3_full_pred_1_slot_valids_1, + output [40:0] io_out_s3_full_pred_1_targets_0, + output [40:0] io_out_s3_full_pred_1_targets_1, + output [40:0] io_out_s3_full_pred_1_fallThroughAddr, + output io_out_s3_full_pred_1_fallThroughErr, + output io_out_s3_full_pred_1_is_br_sharing, + output io_out_s3_full_pred_1_hit, + output io_out_s3_full_pred_2_br_taken_mask_0, + output io_out_s3_full_pred_2_br_taken_mask_1, + output io_out_s3_full_pred_2_slot_valids_0, + output io_out_s3_full_pred_2_slot_valids_1, + output [40:0] io_out_s3_full_pred_2_targets_0, + output [40:0] io_out_s3_full_pred_2_targets_1, + output [40:0] io_out_s3_full_pred_2_fallThroughAddr, + output io_out_s3_full_pred_2_fallThroughErr, + output io_out_s3_full_pred_2_is_br_sharing, + output io_out_s3_full_pred_2_hit, + output io_out_s3_full_pred_3_br_taken_mask_0, + output io_out_s3_full_pred_3_br_taken_mask_1, + output io_out_s3_full_pred_3_slot_valids_0, + output io_out_s3_full_pred_3_slot_valids_1, + output [40:0] io_out_s3_full_pred_3_targets_0, + output [40:0] io_out_s3_full_pred_3_targets_1, + output [3:0] io_out_s3_full_pred_3_offsets_0, + output [3:0] io_out_s3_full_pred_3_offsets_1, + output [40:0] io_out_s3_full_pred_3_fallThroughAddr, + output io_out_s3_full_pred_3_fallThroughErr, + output io_out_s3_full_pred_3_is_br_sharing, + output io_out_s3_full_pred_3_hit, + output [222:0] io_out_last_stage_meta, + output [3:0] io_out_last_stage_spec_info_ssp, + output [1:0] io_out_last_stage_spec_info_sctr, + output io_out_last_stage_spec_info_TOSW_flag, + output [4:0] io_out_last_stage_spec_info_TOSW_value, + output io_out_last_stage_spec_info_TOSR_flag, + output [4:0] io_out_last_stage_spec_info_TOSR_value, + output io_out_last_stage_spec_info_NOS_flag, + output [4:0] io_out_last_stage_spec_info_NOS_value, + output [40:0] io_out_last_stage_spec_info_topAddr, + output io_out_last_stage_ftb_entry_valid, + output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, + output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, + output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, + output io_out_last_stage_ftb_entry_brSlots_0_sharing, + output io_out_last_stage_ftb_entry_brSlots_0_valid, + output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, + output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, + output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, + output io_out_last_stage_ftb_entry_tailSlot_sharing, + output io_out_last_stage_ftb_entry_tailSlot_valid, + output [3:0] io_out_last_stage_ftb_entry_pftAddr, + output io_out_last_stage_ftb_entry_carry, + output io_out_last_stage_ftb_entry_isCall, + output io_out_last_stage_ftb_entry_isRet, + output io_out_last_stage_ftb_entry_isJalr, + output io_out_last_stage_ftb_entry_last_may_be_rvi_call, + output io_out_last_stage_ftb_entry_always_taken_0, + output io_out_last_stage_ftb_entry_always_taken_1, + input io_ctrl_ras_enable, + input io_s0_fire_0, + input io_s0_fire_1, + input io_s0_fire_2, + input io_s0_fire_3, + input io_s1_fire_0, + input io_s1_fire_1, + input io_s1_fire_2, + input io_s1_fire_3, + input io_s2_fire_0, + input io_s2_fire_1, + input io_s2_fire_2, + input io_s2_fire_3, + input io_s3_fire_2, + input io_s3_redirect_2, + input io_update_valid, + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, + input io_update_bits_ftb_entry_tailSlot_valid, + input io_update_bits_ftb_entry_isCall, + input io_update_bits_ftb_entry_isRet, + input io_update_bits_cfi_idx_valid, + input [3:0] io_update_bits_cfi_idx_bits, + input io_update_bits_jmp_taken, + input [222:0] io_update_bits_meta, + input io_redirect_valid, + input io_redirect_bits_level, + input [40:0] io_redirect_bits_cfiUpdate_pc, + input io_redirect_bits_cfiUpdate_pd_isRVC, + input io_redirect_bits_cfiUpdate_pd_isCall, + input io_redirect_bits_cfiUpdate_pd_isRet, + input [3:0] io_redirect_bits_cfiUpdate_ssp, + input [1:0] io_redirect_bits_cfiUpdate_sctr, + input io_redirect_bits_cfiUpdate_TOSW_flag, + input [4:0] io_redirect_bits_cfiUpdate_TOSW_value, + input io_redirect_bits_cfiUpdate_TOSR_flag, + input [4:0] io_redirect_bits_cfiUpdate_TOSR_value, + input io_redirect_bits_cfiUpdate_NOS_flag, + input [4:0] io_redirect_bits_cfiUpdate_NOS_value +); + + wire [40:0] _RASStack_io_spec_pop_addr; + wire [3:0] _RASStack_io_ssp; + wire [2:0] _RASStack_io_sctr; + wire _RASStack_io_TOSR_flag; + wire [4:0] _RASStack_io_TOSR_value; + wire _RASStack_io_TOSW_flag; + wire [4:0] _RASStack_io_TOSW_value; + wire _RASStack_io_NOS_flag; + wire [4:0] _RASStack_io_NOS_value; + wire [35:0] _reset_vector_delay_io_out; + reg [40:0] s1_pc_dup_0; + reg [40:0] s1_pc_dup_1; + reg [40:0] s1_pc_dup_2; + reg [40:0] s1_pc_dup_3; + reg [40:0] s2_pc_dup_0; + reg [40:0] s2_pc_dup_1; + reg [40:0] s2_pc_dup_2; + reg [40:0] s2_pc_dup_3; + reg [40:0] s3_pc_dup_0; + reg [40:0] s3_pc_dup_1; + reg [40:0] s3_pc_dup_2; + reg [40:0] s3_pc_dup_3; + reg REG; + reg REG_1; + wire [40:0] _s2_spec_new_addr_T_1 = + 41'(io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr + + {39'h0, io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, 1'h0}); + wire _s2_spec_pop_T_8 = + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0 + & io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; + wire _s2_spec_pop_T_9 = + io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing + & io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; + wire s2_spec_push = + io_s2_fire_2 & ~(_s2_spec_pop_T_8 & io_in_bits_resp_in_0_s2_full_pred_2_hit) + & io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1 + & (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing) + & io_in_bits_resp_in_0_s2_full_pred_2_hit + & ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing + & io_in_bits_resp_in_0_s2_full_pred_2_is_call & ~io_s3_redirect_2; + wire s2_spec_pop = + io_s2_fire_2 & ~(_s2_spec_pop_T_8 & io_in_bits_resp_in_0_s2_full_pred_2_hit) + & io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1 + & (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing) + & io_in_bits_resp_in_0_s2_full_pred_2_hit + & ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing + & io_in_bits_resp_in_0_s2_full_pred_2_is_ret & ~io_s3_redirect_2; + wire _GEN = io_in_bits_resp_in_0_s2_full_pred_2_is_ret & io_ctrl_ras_enable; + reg [40:0] s3_top; + reg [40:0] s3_spec_new_addr; + wire _GEN_0 = io_in_bits_resp_in_0_s3_full_pred_2_is_ret & io_ctrl_ras_enable; + reg s3_pushed_in_s2; + reg s3_popped_in_s2; + wire _s3_pop_T_8 = + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0 + & io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; + wire _s3_pop_T_9 = + io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing + & io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; + wire s3_push = + ~(_s3_pop_T_8 & io_in_bits_resp_in_0_s3_full_pred_2_hit) + & io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1 + & (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing) + & io_in_bits_resp_in_0_s3_full_pred_2_hit + & ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing + & io_in_bits_resp_in_0_s3_full_pred_2_is_call; + wire s3_pop = + ~(_s3_pop_T_8 & io_in_bits_resp_in_0_s3_full_pred_2_hit) + & io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1 + & (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing) + & io_in_bits_resp_in_0_s3_full_pred_2_hit + & ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing + & io_in_bits_resp_in_0_s3_full_pred_2_is_ret; + reg [3:0] s3_meta_ssp; + reg [2:0] s3_meta_sctr; + reg s3_meta_TOSW_flag; + reg [4:0] s3_meta_TOSW_value; + reg s3_meta_TOSR_flag; + reg [4:0] s3_meta_TOSR_value; + reg s3_meta_NOS_flag; + reg [4:0] s3_meta_NOS_value; + reg redirect_next_valid_last_r; + reg redirect_next_bits_r_level; + reg [40:0] redirect_next_bits_r_cfiUpdate_pc; + reg redirect_next_bits_r_cfiUpdate_pd_isRVC; + reg redirect_next_bits_r_cfiUpdate_pd_isCall; + reg redirect_next_bits_r_cfiUpdate_pd_isRet; + reg [3:0] redirect_next_bits_r_cfiUpdate_ssp; + reg [1:0] redirect_next_bits_r_cfiUpdate_sctr; + reg redirect_next_bits_r_cfiUpdate_TOSW_flag; + reg [4:0] redirect_next_bits_r_cfiUpdate_TOSW_value; + reg redirect_next_bits_r_cfiUpdate_TOSR_flag; + reg [4:0] redirect_next_bits_r_cfiUpdate_TOSR_value; + reg redirect_next_bits_r_cfiUpdate_NOS_flag; + reg [4:0] redirect_next_bits_r_cfiUpdate_NOS_value; + wire _GEN_1 = + io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset; + wire [40:0] _GEN_2 = {5'h0, _reset_vector_delay_io_out}; + always @(posedge clock) begin + if (REG_1) begin + s1_pc_dup_0 <= _GEN_2; + s1_pc_dup_1 <= _GEN_2; + s1_pc_dup_2 <= _GEN_2; + s1_pc_dup_3 <= _GEN_2; + end + else begin + if (io_s0_fire_0) + s1_pc_dup_0 <= io_in_bits_s0_pc_0; + if (io_s0_fire_1) + s1_pc_dup_1 <= io_in_bits_s0_pc_1; + if (io_s0_fire_2) + s1_pc_dup_2 <= io_in_bits_s0_pc_2; + if (io_s0_fire_3) + s1_pc_dup_3 <= io_in_bits_s0_pc_3; + end + if (io_s1_fire_0) + s2_pc_dup_0 <= s1_pc_dup_0; + if (io_s1_fire_1) + s2_pc_dup_1 <= s1_pc_dup_1; + if (io_s1_fire_2) + s2_pc_dup_2 <= s1_pc_dup_2; + if (io_s1_fire_3) + s2_pc_dup_3 <= s1_pc_dup_3; + if (io_s2_fire_0) + s3_pc_dup_0 <= s2_pc_dup_0; + if (io_s2_fire_1) + s3_pc_dup_1 <= s2_pc_dup_1; + if (io_s2_fire_2) begin + s3_pc_dup_2 <= s2_pc_dup_2; + s3_top <= _RASStack_io_spec_pop_addr; + s3_spec_new_addr <= _s2_spec_new_addr_T_1; + s3_pushed_in_s2 <= s2_spec_push; + s3_popped_in_s2 <= s2_spec_pop; + s3_meta_ssp <= _RASStack_io_ssp; + s3_meta_sctr <= _RASStack_io_sctr; + s3_meta_TOSW_flag <= _RASStack_io_TOSW_flag; + s3_meta_TOSW_value <= _RASStack_io_TOSW_value; + s3_meta_TOSR_flag <= _RASStack_io_TOSR_flag; + s3_meta_TOSR_value <= _RASStack_io_TOSR_value; + s3_meta_NOS_flag <= _RASStack_io_NOS_flag; + s3_meta_NOS_value <= _RASStack_io_NOS_value; + end + if (io_s2_fire_3) + s3_pc_dup_3 <= s2_pc_dup_3; + REG <= reset; + REG_1 <= REG & ~reset; + if (io_redirect_valid) begin + redirect_next_bits_r_level <= io_redirect_bits_level; + redirect_next_bits_r_cfiUpdate_pc <= io_redirect_bits_cfiUpdate_pc; + redirect_next_bits_r_cfiUpdate_pd_isRVC <= io_redirect_bits_cfiUpdate_pd_isRVC; + redirect_next_bits_r_cfiUpdate_pd_isCall <= io_redirect_bits_cfiUpdate_pd_isCall; + redirect_next_bits_r_cfiUpdate_pd_isRet <= io_redirect_bits_cfiUpdate_pd_isRet; + redirect_next_bits_r_cfiUpdate_ssp <= io_redirect_bits_cfiUpdate_ssp; + redirect_next_bits_r_cfiUpdate_sctr <= io_redirect_bits_cfiUpdate_sctr; + redirect_next_bits_r_cfiUpdate_TOSW_flag <= io_redirect_bits_cfiUpdate_TOSW_flag; + redirect_next_bits_r_cfiUpdate_TOSW_value <= io_redirect_bits_cfiUpdate_TOSW_value; + redirect_next_bits_r_cfiUpdate_TOSR_flag <= io_redirect_bits_cfiUpdate_TOSR_flag; + redirect_next_bits_r_cfiUpdate_TOSR_value <= io_redirect_bits_cfiUpdate_TOSR_value; + redirect_next_bits_r_cfiUpdate_NOS_flag <= io_redirect_bits_cfiUpdate_NOS_flag; + redirect_next_bits_r_cfiUpdate_NOS_value <= io_redirect_bits_cfiUpdate_NOS_value; + end + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) + redirect_next_valid_last_r <= 1'h0; + else if (io_redirect_valid | redirect_next_valid_last_r) + redirect_next_valid_last_r <= io_redirect_valid; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:21]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [4:0] i = 5'h0; i < 5'h16; i += 5'h1) begin + _RANDOM[i] = `RANDOM; + end + s1_pc_dup_0 = {_RANDOM[5'h0], _RANDOM[5'h1][8:0]}; + s1_pc_dup_1 = {_RANDOM[5'h1][31:9], _RANDOM[5'h2][17:0]}; + s1_pc_dup_2 = {_RANDOM[5'h2][31:18], _RANDOM[5'h3][26:0]}; + s1_pc_dup_3 = {_RANDOM[5'h3][31:27], _RANDOM[5'h4], _RANDOM[5'h5][3:0]}; + s2_pc_dup_0 = {_RANDOM[5'h5][31:4], _RANDOM[5'h6][12:0]}; + s2_pc_dup_1 = {_RANDOM[5'h6][31:13], _RANDOM[5'h7][21:0]}; + s2_pc_dup_2 = {_RANDOM[5'h7][31:22], _RANDOM[5'h8][30:0]}; + s2_pc_dup_3 = {_RANDOM[5'h8][31], _RANDOM[5'h9], _RANDOM[5'hA][7:0]}; + s3_pc_dup_0 = {_RANDOM[5'hA][31:8], _RANDOM[5'hB][16:0]}; + s3_pc_dup_1 = {_RANDOM[5'hB][31:17], _RANDOM[5'hC][25:0]}; + s3_pc_dup_2 = {_RANDOM[5'hC][31:26], _RANDOM[5'hD], _RANDOM[5'hE][2:0]}; + s3_pc_dup_3 = {_RANDOM[5'hE][31:3], _RANDOM[5'hF][11:0]}; + REG = _RANDOM[5'hF][12]; + REG_1 = _RANDOM[5'hF][13]; + s3_top = {_RANDOM[5'hF][31:14], _RANDOM[5'h10][22:0]}; + s3_spec_new_addr = {_RANDOM[5'h10][31:23], _RANDOM[5'h11]}; + s3_pushed_in_s2 = _RANDOM[5'h12][0]; + s3_popped_in_s2 = _RANDOM[5'h12][1]; + s3_meta_ssp = _RANDOM[5'h12][5:2]; + s3_meta_sctr = _RANDOM[5'h12][8:6]; + s3_meta_TOSW_flag = _RANDOM[5'h12][9]; + s3_meta_TOSW_value = _RANDOM[5'h12][14:10]; + s3_meta_TOSR_flag = _RANDOM[5'h12][15]; + s3_meta_TOSR_value = _RANDOM[5'h12][20:16]; + s3_meta_NOS_flag = _RANDOM[5'h12][21]; + s3_meta_NOS_value = _RANDOM[5'h12][26:22]; + redirect_next_valid_last_r = _RANDOM[5'h12][27]; + redirect_next_bits_r_level = _RANDOM[5'h13][17]; + redirect_next_bits_r_cfiUpdate_pc = {_RANDOM[5'h13][31:19], _RANDOM[5'h14][27:0]}; + redirect_next_bits_r_cfiUpdate_pd_isRVC = _RANDOM[5'h14][29]; + redirect_next_bits_r_cfiUpdate_pd_isCall = _RANDOM[5'h15][0]; + redirect_next_bits_r_cfiUpdate_pd_isRet = _RANDOM[5'h15][1]; + redirect_next_bits_r_cfiUpdate_ssp = _RANDOM[5'h15][5:2]; + redirect_next_bits_r_cfiUpdate_sctr = _RANDOM[5'h15][7:6]; + redirect_next_bits_r_cfiUpdate_TOSW_flag = _RANDOM[5'h15][8]; + redirect_next_bits_r_cfiUpdate_TOSW_value = _RANDOM[5'h15][13:9]; + redirect_next_bits_r_cfiUpdate_TOSR_flag = _RANDOM[5'h15][14]; + redirect_next_bits_r_cfiUpdate_TOSR_value = _RANDOM[5'h15][19:15]; + redirect_next_bits_r_cfiUpdate_NOS_flag = _RANDOM[5'h15][20]; + redirect_next_bits_r_cfiUpdate_NOS_value = _RANDOM[5'h15][25:21]; + `endif // RANDOMIZE_REG_INIT + if (reset) + redirect_next_valid_last_r = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + DelayN_2 reset_vector_delay ( + .clock (clock), + .io_in (io_reset_vector), + .io_out (_reset_vector_delay_io_out) + ); + RASStack RASStack ( + .clock (clock), + .reset (reset), + .io_spec_push_valid (s2_spec_push), + .io_spec_pop_valid (s2_spec_pop), + .io_spec_push_addr (_s2_spec_new_addr_T_1), + .io_s2_fire (io_s2_fire_2), + .io_s3_fire (io_s3_fire_2), + .io_s3_cancel + (io_s3_fire_2 & (s3_pushed_in_s2 != s3_push | s3_popped_in_s2 != s3_pop)), + .io_s3_meta_ssp (s3_meta_ssp), + .io_s3_meta_sctr (s3_meta_sctr), + .io_s3_meta_TOSW_flag (s3_meta_TOSW_flag), + .io_s3_meta_TOSW_value (s3_meta_TOSW_value), + .io_s3_meta_TOSR_flag (s3_meta_TOSR_flag), + .io_s3_meta_TOSR_value (s3_meta_TOSR_value), + .io_s3_meta_NOS_flag (s3_meta_NOS_flag), + .io_s3_meta_NOS_value (s3_meta_NOS_value), + .io_s3_missed_pop (s3_pop & ~s3_popped_in_s2), + .io_s3_missed_push (s3_push & ~s3_pushed_in_s2), + .io_s3_pushAddr (s3_spec_new_addr), + .io_spec_pop_addr (_RASStack_io_spec_pop_addr), + .io_commit_push_valid + (io_update_valid & io_update_bits_ftb_entry_tailSlot_valid + & io_update_bits_ftb_entry_isCall & io_update_bits_jmp_taken + & io_update_bits_cfi_idx_valid & _GEN_1), + .io_commit_pop_valid + (io_update_valid & io_update_bits_ftb_entry_tailSlot_valid + & io_update_bits_ftb_entry_isRet & io_update_bits_jmp_taken + & io_update_bits_cfi_idx_valid & _GEN_1), + .io_commit_meta_TOSW_flag (io_update_bits_meta[17]), + .io_commit_meta_TOSW_value (io_update_bits_meta[16:12]), + .io_commit_meta_ssp (io_update_bits_meta[24:21]), + .io_redirect_valid (redirect_next_valid_last_r), + .io_redirect_isCall + (redirect_next_valid_last_r & ~redirect_next_bits_r_level + & redirect_next_bits_r_cfiUpdate_pd_isCall), + .io_redirect_isRet + (redirect_next_valid_last_r & ~redirect_next_bits_r_level + & redirect_next_bits_r_cfiUpdate_pd_isRet), + .io_redirect_meta_ssp (redirect_next_bits_r_cfiUpdate_ssp), + .io_redirect_meta_sctr ({1'h0, redirect_next_bits_r_cfiUpdate_sctr}), + .io_redirect_meta_TOSW_flag (redirect_next_bits_r_cfiUpdate_TOSW_flag), + .io_redirect_meta_TOSW_value (redirect_next_bits_r_cfiUpdate_TOSW_value), + .io_redirect_meta_TOSR_flag (redirect_next_bits_r_cfiUpdate_TOSR_flag), + .io_redirect_meta_TOSR_value (redirect_next_bits_r_cfiUpdate_TOSR_value), + .io_redirect_meta_NOS_flag (redirect_next_bits_r_cfiUpdate_NOS_flag), + .io_redirect_meta_NOS_value (redirect_next_bits_r_cfiUpdate_NOS_value), + .io_redirect_callAddr + (41'(redirect_next_bits_r_cfiUpdate_pc + + {38'h0, redirect_next_bits_r_cfiUpdate_pd_isRVC ? 3'h2 : 3'h4})), + .io_ssp (_RASStack_io_ssp), + .io_sctr (_RASStack_io_sctr), + .io_TOSR_flag (_RASStack_io_TOSR_flag), + .io_TOSR_value (_RASStack_io_TOSR_value), + .io_TOSW_flag (_RASStack_io_TOSW_flag), + .io_TOSW_value (_RASStack_io_TOSW_value), + .io_NOS_flag (_RASStack_io_NOS_flag), + .io_NOS_value (_RASStack_io_NOS_value) + ); + assign io_out_s2_pc_0 = s2_pc_dup_0; + assign io_out_s2_pc_1 = s2_pc_dup_1; + assign io_out_s2_pc_2 = s2_pc_dup_2; + assign io_out_s2_pc_3 = s2_pc_dup_3; + assign io_out_s2_full_pred_0_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0; + assign io_out_s2_full_pred_0_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1; + assign io_out_s2_full_pred_0_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0; + assign io_out_s2_full_pred_0_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1; + assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0; + assign io_out_s2_full_pred_0_targets_1 = + io_in_bits_resp_in_0_s2_full_pred_2_is_jalr + ? (_GEN + ? _RASStack_io_spec_pop_addr + : io_in_bits_resp_in_0_s2_full_pred_0_jalr_target) + : io_in_bits_resp_in_0_s2_full_pred_0_targets_1; + assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0; + assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1; + assign io_out_s2_full_pred_0_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr; + assign io_out_s2_full_pred_0_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing; + assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit; + assign io_out_s2_full_pred_1_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0; + assign io_out_s2_full_pred_1_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1; + assign io_out_s2_full_pred_1_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0; + assign io_out_s2_full_pred_1_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1; + assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0; + assign io_out_s2_full_pred_1_targets_1 = + io_in_bits_resp_in_0_s2_full_pred_2_is_jalr + ? (_GEN + ? _RASStack_io_spec_pop_addr + : io_in_bits_resp_in_0_s2_full_pred_1_jalr_target) + : io_in_bits_resp_in_0_s2_full_pred_1_targets_1; + assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0; + assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1; + assign io_out_s2_full_pred_1_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr; + assign io_out_s2_full_pred_1_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing; + assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit; + assign io_out_s2_full_pred_2_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; + assign io_out_s2_full_pred_2_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; + assign io_out_s2_full_pred_2_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0; + assign io_out_s2_full_pred_2_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1; + assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0; + assign io_out_s2_full_pred_2_targets_1 = + io_in_bits_resp_in_0_s2_full_pred_2_is_jalr + ? (_GEN + ? _RASStack_io_spec_pop_addr + : io_in_bits_resp_in_0_s2_full_pred_2_jalr_target) + : io_in_bits_resp_in_0_s2_full_pred_2_targets_1; + assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0; + assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1; + assign io_out_s2_full_pred_2_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr; + assign io_out_s2_full_pred_2_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing; + assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit; + assign io_out_s2_full_pred_3_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0; + assign io_out_s2_full_pred_3_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1; + assign io_out_s2_full_pred_3_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0; + assign io_out_s2_full_pred_3_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1; + assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0; + assign io_out_s2_full_pred_3_targets_1 = + io_in_bits_resp_in_0_s2_full_pred_2_is_jalr + ? (_GEN + ? _RASStack_io_spec_pop_addr + : io_in_bits_resp_in_0_s2_full_pred_3_jalr_target) + : io_in_bits_resp_in_0_s2_full_pred_3_targets_1; + assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0; + assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1; + assign io_out_s2_full_pred_3_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr; + assign io_out_s2_full_pred_3_fallThroughErr = + io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr; + assign io_out_s2_full_pred_3_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing; + assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit; + assign io_out_s3_pc_0 = s3_pc_dup_0; + assign io_out_s3_pc_1 = s3_pc_dup_1; + assign io_out_s3_pc_2 = s3_pc_dup_2; + assign io_out_s3_pc_3 = s3_pc_dup_3; + assign io_out_s3_full_pred_0_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0; + assign io_out_s3_full_pred_0_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1; + assign io_out_s3_full_pred_0_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0; + assign io_out_s3_full_pred_0_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1; + assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0; + assign io_out_s3_full_pred_0_targets_1 = + io_in_bits_resp_in_0_s3_full_pred_2_is_jalr + ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_0_jalr_target) + : io_in_bits_resp_in_0_s3_full_pred_0_targets_1; + assign io_out_s3_full_pred_0_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr; + assign io_out_s3_full_pred_0_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr; + assign io_out_s3_full_pred_0_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing; + assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit; + assign io_out_s3_full_pred_1_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0; + assign io_out_s3_full_pred_1_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1; + assign io_out_s3_full_pred_1_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0; + assign io_out_s3_full_pred_1_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1; + assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0; + assign io_out_s3_full_pred_1_targets_1 = + io_in_bits_resp_in_0_s3_full_pred_2_is_jalr + ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_1_jalr_target) + : io_in_bits_resp_in_0_s3_full_pred_1_targets_1; + assign io_out_s3_full_pred_1_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr; + assign io_out_s3_full_pred_1_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr; + assign io_out_s3_full_pred_1_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing; + assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit; + assign io_out_s3_full_pred_2_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; + assign io_out_s3_full_pred_2_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; + assign io_out_s3_full_pred_2_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0; + assign io_out_s3_full_pred_2_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1; + assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0; + assign io_out_s3_full_pred_2_targets_1 = + io_in_bits_resp_in_0_s3_full_pred_2_is_jalr + ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_2_jalr_target) + : io_in_bits_resp_in_0_s3_full_pred_2_targets_1; + assign io_out_s3_full_pred_2_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr; + assign io_out_s3_full_pred_2_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr; + assign io_out_s3_full_pred_2_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing; + assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit; + assign io_out_s3_full_pred_3_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0; + assign io_out_s3_full_pred_3_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1; + assign io_out_s3_full_pred_3_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0; + assign io_out_s3_full_pred_3_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1; + assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0; + assign io_out_s3_full_pred_3_targets_1 = + io_in_bits_resp_in_0_s3_full_pred_2_is_jalr + ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_3_jalr_target) + : io_in_bits_resp_in_0_s3_full_pred_3_targets_1; + assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0; + assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1; + assign io_out_s3_full_pred_3_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr; + assign io_out_s3_full_pred_3_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr; + assign io_out_s3_full_pred_3_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing; + assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit; + assign io_out_last_stage_meta = + {198'h0, + s3_meta_ssp, + s3_meta_sctr, + s3_meta_TOSW_flag, + s3_meta_TOSW_value, + s3_meta_TOSR_flag, + s3_meta_TOSR_value, + s3_meta_NOS_flag, + s3_meta_NOS_value}; + assign io_out_last_stage_spec_info_ssp = s3_meta_ssp; + assign io_out_last_stage_spec_info_sctr = s3_meta_sctr[1:0]; + assign io_out_last_stage_spec_info_TOSW_flag = s3_meta_TOSW_flag; + assign io_out_last_stage_spec_info_TOSW_value = s3_meta_TOSW_value; + assign io_out_last_stage_spec_info_TOSR_flag = s3_meta_TOSR_flag; + assign io_out_last_stage_spec_info_TOSR_value = s3_meta_TOSR_value; + assign io_out_last_stage_spec_info_NOS_flag = s3_meta_NOS_flag; + assign io_out_last_stage_spec_info_NOS_value = s3_meta_NOS_value; + assign io_out_last_stage_spec_info_topAddr = s3_top; + assign io_out_last_stage_ftb_entry_valid = + io_in_bits_resp_in_0_last_stage_ftb_entry_valid; + assign io_out_last_stage_ftb_entry_brSlots_0_offset = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset; + assign io_out_last_stage_ftb_entry_brSlots_0_lower = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower; + assign io_out_last_stage_ftb_entry_brSlots_0_tarStat = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat; + assign io_out_last_stage_ftb_entry_brSlots_0_sharing = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing; + assign io_out_last_stage_ftb_entry_brSlots_0_valid = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid; + assign io_out_last_stage_ftb_entry_tailSlot_offset = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset; + assign io_out_last_stage_ftb_entry_tailSlot_lower = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower; + assign io_out_last_stage_ftb_entry_tailSlot_tarStat = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat; + assign io_out_last_stage_ftb_entry_tailSlot_sharing = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing; + assign io_out_last_stage_ftb_entry_tailSlot_valid = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid; + assign io_out_last_stage_ftb_entry_pftAddr = + io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr; + assign io_out_last_stage_ftb_entry_carry = + io_in_bits_resp_in_0_last_stage_ftb_entry_carry; + assign io_out_last_stage_ftb_entry_isCall = + io_in_bits_resp_in_0_last_stage_ftb_entry_isCall; + assign io_out_last_stage_ftb_entry_isRet = + io_in_bits_resp_in_0_last_stage_ftb_entry_isRet; + assign io_out_last_stage_ftb_entry_isJalr = + io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr; + assign io_out_last_stage_ftb_entry_last_may_be_rvi_call = + io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call; + assign io_out_last_stage_ftb_entry_always_taken_0 = + io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0; + assign io_out_last_stage_ftb_entry_always_taken_1 = + io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1; +endmodule + diff --git a/rtl/BPUTop/RASStack.sv b/rtl/BPUTop/RASStack.sv new file mode 100644 index 0000000..f31ba96 --- /dev/null +++ b/rtl/BPUTop/RASStack.sv @@ -0,0 +1,1934 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module RASStack( + input clock, + input reset, + input io_spec_push_valid, + input io_spec_pop_valid, + input [40:0] io_spec_push_addr, + input io_s2_fire, + input io_s3_fire, + input io_s3_cancel, + input [3:0] io_s3_meta_ssp, + input [2:0] io_s3_meta_sctr, + input io_s3_meta_TOSW_flag, + input [4:0] io_s3_meta_TOSW_value, + input io_s3_meta_TOSR_flag, + input [4:0] io_s3_meta_TOSR_value, + input io_s3_meta_NOS_flag, + input [4:0] io_s3_meta_NOS_value, + input io_s3_missed_pop, + input io_s3_missed_push, + input [40:0] io_s3_pushAddr, + output [40:0] io_spec_pop_addr, + input io_commit_push_valid, + input io_commit_pop_valid, + input io_commit_meta_TOSW_flag, + input [4:0] io_commit_meta_TOSW_value, + input [3:0] io_commit_meta_ssp, + input io_redirect_valid, + input io_redirect_isCall, + input io_redirect_isRet, + input [3:0] io_redirect_meta_ssp, + input [2:0] io_redirect_meta_sctr, + input io_redirect_meta_TOSW_flag, + input [4:0] io_redirect_meta_TOSW_value, + input io_redirect_meta_TOSR_flag, + input [4:0] io_redirect_meta_TOSR_value, + input io_redirect_meta_NOS_flag, + input [4:0] io_redirect_meta_NOS_value, + input [40:0] io_redirect_callAddr, + output [3:0] io_ssp, + output [2:0] io_sctr, + output io_TOSR_flag, + output [4:0] io_TOSR_value, + output io_TOSW_flag, + output [4:0] io_TOSW_value, + output io_NOS_flag, + output [4:0] io_NOS_value +); + + reg [40:0] commit_stack_0_retAddr; + reg [7:0] commit_stack_0_ctr; + reg [40:0] commit_stack_1_retAddr; + reg [7:0] commit_stack_1_ctr; + reg [40:0] commit_stack_2_retAddr; + reg [7:0] commit_stack_2_ctr; + reg [40:0] commit_stack_3_retAddr; + reg [7:0] commit_stack_3_ctr; + reg [40:0] commit_stack_4_retAddr; + reg [7:0] commit_stack_4_ctr; + reg [40:0] commit_stack_5_retAddr; + reg [7:0] commit_stack_5_ctr; + reg [40:0] commit_stack_6_retAddr; + reg [7:0] commit_stack_6_ctr; + reg [40:0] commit_stack_7_retAddr; + reg [7:0] commit_stack_7_ctr; + reg [40:0] commit_stack_8_retAddr; + reg [7:0] commit_stack_8_ctr; + reg [40:0] commit_stack_9_retAddr; + reg [7:0] commit_stack_9_ctr; + reg [40:0] commit_stack_10_retAddr; + reg [7:0] commit_stack_10_ctr; + reg [40:0] commit_stack_11_retAddr; + reg [7:0] commit_stack_11_ctr; + reg [40:0] commit_stack_12_retAddr; + reg [7:0] commit_stack_12_ctr; + reg [40:0] commit_stack_13_retAddr; + reg [7:0] commit_stack_13_ctr; + reg [40:0] commit_stack_14_retAddr; + reg [7:0] commit_stack_14_ctr; + reg [40:0] commit_stack_15_retAddr; + reg [7:0] commit_stack_15_ctr; + reg [40:0] spec_queue_0_retAddr; + reg [7:0] spec_queue_0_ctr; + reg [40:0] spec_queue_1_retAddr; + reg [7:0] spec_queue_1_ctr; + reg [40:0] spec_queue_2_retAddr; + reg [7:0] spec_queue_2_ctr; + reg [40:0] spec_queue_3_retAddr; + reg [7:0] spec_queue_3_ctr; + reg [40:0] spec_queue_4_retAddr; + reg [7:0] spec_queue_4_ctr; + reg [40:0] spec_queue_5_retAddr; + reg [7:0] spec_queue_5_ctr; + reg [40:0] spec_queue_6_retAddr; + reg [7:0] spec_queue_6_ctr; + reg [40:0] spec_queue_7_retAddr; + reg [7:0] spec_queue_7_ctr; + reg [40:0] spec_queue_8_retAddr; + reg [7:0] spec_queue_8_ctr; + reg [40:0] spec_queue_9_retAddr; + reg [7:0] spec_queue_9_ctr; + reg [40:0] spec_queue_10_retAddr; + reg [7:0] spec_queue_10_ctr; + reg [40:0] spec_queue_11_retAddr; + reg [7:0] spec_queue_11_ctr; + reg [40:0] spec_queue_12_retAddr; + reg [7:0] spec_queue_12_ctr; + reg [40:0] spec_queue_13_retAddr; + reg [7:0] spec_queue_13_ctr; + reg [40:0] spec_queue_14_retAddr; + reg [7:0] spec_queue_14_ctr; + reg [40:0] spec_queue_15_retAddr; + reg [7:0] spec_queue_15_ctr; + reg [40:0] spec_queue_16_retAddr; + reg [7:0] spec_queue_16_ctr; + reg [40:0] spec_queue_17_retAddr; + reg [7:0] spec_queue_17_ctr; + reg [40:0] spec_queue_18_retAddr; + reg [7:0] spec_queue_18_ctr; + reg [40:0] spec_queue_19_retAddr; + reg [7:0] spec_queue_19_ctr; + reg [40:0] spec_queue_20_retAddr; + reg [7:0] spec_queue_20_ctr; + reg [40:0] spec_queue_21_retAddr; + reg [7:0] spec_queue_21_ctr; + reg [40:0] spec_queue_22_retAddr; + reg [7:0] spec_queue_22_ctr; + reg [40:0] spec_queue_23_retAddr; + reg [7:0] spec_queue_23_ctr; + reg [40:0] spec_queue_24_retAddr; + reg [7:0] spec_queue_24_ctr; + reg [40:0] spec_queue_25_retAddr; + reg [7:0] spec_queue_25_ctr; + reg [40:0] spec_queue_26_retAddr; + reg [7:0] spec_queue_26_ctr; + reg [40:0] spec_queue_27_retAddr; + reg [7:0] spec_queue_27_ctr; + reg [40:0] spec_queue_28_retAddr; + reg [7:0] spec_queue_28_ctr; + reg [40:0] spec_queue_29_retAddr; + reg [7:0] spec_queue_29_ctr; + reg [40:0] spec_queue_30_retAddr; + reg [7:0] spec_queue_30_ctr; + reg [40:0] spec_queue_31_retAddr; + reg [7:0] spec_queue_31_ctr; + reg spec_nos_0_flag; + reg [4:0] spec_nos_0_value; + reg spec_nos_1_flag; + reg [4:0] spec_nos_1_value; + reg spec_nos_2_flag; + reg [4:0] spec_nos_2_value; + reg spec_nos_3_flag; + reg [4:0] spec_nos_3_value; + reg spec_nos_4_flag; + reg [4:0] spec_nos_4_value; + reg spec_nos_5_flag; + reg [4:0] spec_nos_5_value; + reg spec_nos_6_flag; + reg [4:0] spec_nos_6_value; + reg spec_nos_7_flag; + reg [4:0] spec_nos_7_value; + reg spec_nos_8_flag; + reg [4:0] spec_nos_8_value; + reg spec_nos_9_flag; + reg [4:0] spec_nos_9_value; + reg spec_nos_10_flag; + reg [4:0] spec_nos_10_value; + reg spec_nos_11_flag; + reg [4:0] spec_nos_11_value; + reg spec_nos_12_flag; + reg [4:0] spec_nos_12_value; + reg spec_nos_13_flag; + reg [4:0] spec_nos_13_value; + reg spec_nos_14_flag; + reg [4:0] spec_nos_14_value; + reg spec_nos_15_flag; + reg [4:0] spec_nos_15_value; + reg spec_nos_16_flag; + reg [4:0] spec_nos_16_value; + reg spec_nos_17_flag; + reg [4:0] spec_nos_17_value; + reg spec_nos_18_flag; + reg [4:0] spec_nos_18_value; + reg spec_nos_19_flag; + reg [4:0] spec_nos_19_value; + reg spec_nos_20_flag; + reg [4:0] spec_nos_20_value; + reg spec_nos_21_flag; + reg [4:0] spec_nos_21_value; + reg spec_nos_22_flag; + reg [4:0] spec_nos_22_value; + reg spec_nos_23_flag; + reg [4:0] spec_nos_23_value; + reg spec_nos_24_flag; + reg [4:0] spec_nos_24_value; + reg spec_nos_25_flag; + reg [4:0] spec_nos_25_value; + reg spec_nos_26_flag; + reg [4:0] spec_nos_26_value; + reg spec_nos_27_flag; + reg [4:0] spec_nos_27_value; + reg spec_nos_28_flag; + reg [4:0] spec_nos_28_value; + reg spec_nos_29_flag; + reg [4:0] spec_nos_29_value; + reg spec_nos_30_flag; + reg [4:0] spec_nos_30_value; + reg spec_nos_31_flag; + reg [4:0] spec_nos_31_value; + reg [3:0] nsp; + reg [3:0] ssp; + reg [2:0] sctr; + reg TOSR_flag; + reg [4:0] TOSR_value; + reg TOSW_flag; + reg [4:0] TOSW_value; + reg BOS_flag; + reg [4:0] BOS_value; + reg spec_overflowed; + reg [40:0] writeBypassEntry_retAddr; + reg [7:0] writeBypassEntry_ctr; + reg writeBypassNos_flag; + reg [4:0] writeBypassNos_value; + reg writeBypassValid; + wire _realPush_T_4 = io_redirect_valid & io_redirect_isCall; + wire _GEN = TOSR_value >= BOS_value; + wire topEntry_inflightValid = + (TOSR_flag ^ BOS_flag ^ _GEN) & (TOSR_flag ^ TOSW_flag ^ TOSR_value < TOSW_value); + wire [31:0][40:0] _GEN_0 = + {{spec_queue_31_retAddr}, + {spec_queue_30_retAddr}, + {spec_queue_29_retAddr}, + {spec_queue_28_retAddr}, + {spec_queue_27_retAddr}, + {spec_queue_26_retAddr}, + {spec_queue_25_retAddr}, + {spec_queue_24_retAddr}, + {spec_queue_23_retAddr}, + {spec_queue_22_retAddr}, + {spec_queue_21_retAddr}, + {spec_queue_20_retAddr}, + {spec_queue_19_retAddr}, + {spec_queue_18_retAddr}, + {spec_queue_17_retAddr}, + {spec_queue_16_retAddr}, + {spec_queue_15_retAddr}, + {spec_queue_14_retAddr}, + {spec_queue_13_retAddr}, + {spec_queue_12_retAddr}, + {spec_queue_11_retAddr}, + {spec_queue_10_retAddr}, + {spec_queue_9_retAddr}, + {spec_queue_8_retAddr}, + {spec_queue_7_retAddr}, + {spec_queue_6_retAddr}, + {spec_queue_5_retAddr}, + {spec_queue_4_retAddr}, + {spec_queue_3_retAddr}, + {spec_queue_2_retAddr}, + {spec_queue_1_retAddr}, + {spec_queue_0_retAddr}}; + wire [40:0] _GEN_1 = _GEN_0[TOSR_value]; + wire [31:0][7:0] _GEN_2 = + {{spec_queue_31_ctr}, + {spec_queue_30_ctr}, + {spec_queue_29_ctr}, + {spec_queue_28_ctr}, + {spec_queue_27_ctr}, + {spec_queue_26_ctr}, + {spec_queue_25_ctr}, + {spec_queue_24_ctr}, + {spec_queue_23_ctr}, + {spec_queue_22_ctr}, + {spec_queue_21_ctr}, + {spec_queue_20_ctr}, + {spec_queue_19_ctr}, + {spec_queue_18_ctr}, + {spec_queue_17_ctr}, + {spec_queue_16_ctr}, + {spec_queue_15_ctr}, + {spec_queue_14_ctr}, + {spec_queue_13_ctr}, + {spec_queue_12_ctr}, + {spec_queue_11_ctr}, + {spec_queue_10_ctr}, + {spec_queue_9_ctr}, + {spec_queue_8_ctr}, + {spec_queue_7_ctr}, + {spec_queue_6_ctr}, + {spec_queue_5_ctr}, + {spec_queue_4_ctr}, + {spec_queue_3_ctr}, + {spec_queue_2_ctr}, + {spec_queue_1_ctr}, + {spec_queue_0_ctr}}; + wire [15:0][40:0] _GEN_3 = + {{commit_stack_15_retAddr}, + {commit_stack_14_retAddr}, + {commit_stack_13_retAddr}, + {commit_stack_12_retAddr}, + {commit_stack_11_retAddr}, + {commit_stack_10_retAddr}, + {commit_stack_9_retAddr}, + {commit_stack_8_retAddr}, + {commit_stack_7_retAddr}, + {commit_stack_6_retAddr}, + {commit_stack_5_retAddr}, + {commit_stack_4_retAddr}, + {commit_stack_3_retAddr}, + {commit_stack_2_retAddr}, + {commit_stack_1_retAddr}, + {commit_stack_0_retAddr}}; + wire [40:0] _GEN_4 = _GEN_3[ssp]; + wire [15:0][7:0] _GEN_5 = + {{commit_stack_15_ctr}, + {commit_stack_14_ctr}, + {commit_stack_13_ctr}, + {commit_stack_12_ctr}, + {commit_stack_11_ctr}, + {commit_stack_10_ctr}, + {commit_stack_9_ctr}, + {commit_stack_8_ctr}, + {commit_stack_7_ctr}, + {commit_stack_6_ctr}, + {commit_stack_5_ctr}, + {commit_stack_4_ctr}, + {commit_stack_3_ctr}, + {commit_stack_2_ctr}, + {commit_stack_1_ctr}, + {commit_stack_0_ctr}}; + wire [31:0] _GEN_6 = + {{spec_nos_31_flag}, + {spec_nos_30_flag}, + {spec_nos_29_flag}, + {spec_nos_28_flag}, + {spec_nos_27_flag}, + {spec_nos_26_flag}, + {spec_nos_25_flag}, + {spec_nos_24_flag}, + {spec_nos_23_flag}, + {spec_nos_22_flag}, + {spec_nos_21_flag}, + {spec_nos_20_flag}, + {spec_nos_19_flag}, + {spec_nos_18_flag}, + {spec_nos_17_flag}, + {spec_nos_16_flag}, + {spec_nos_15_flag}, + {spec_nos_14_flag}, + {spec_nos_13_flag}, + {spec_nos_12_flag}, + {spec_nos_11_flag}, + {spec_nos_10_flag}, + {spec_nos_9_flag}, + {spec_nos_8_flag}, + {spec_nos_7_flag}, + {spec_nos_6_flag}, + {spec_nos_5_flag}, + {spec_nos_4_flag}, + {spec_nos_3_flag}, + {spec_nos_2_flag}, + {spec_nos_1_flag}, + {spec_nos_0_flag}}; + wire [31:0][4:0] _GEN_7 = + {{spec_nos_31_value}, + {spec_nos_30_value}, + {spec_nos_29_value}, + {spec_nos_28_value}, + {spec_nos_27_value}, + {spec_nos_26_value}, + {spec_nos_25_value}, + {spec_nos_24_value}, + {spec_nos_23_value}, + {spec_nos_22_value}, + {spec_nos_21_value}, + {spec_nos_20_value}, + {spec_nos_19_value}, + {spec_nos_18_value}, + {spec_nos_17_value}, + {spec_nos_16_value}, + {spec_nos_15_value}, + {spec_nos_14_value}, + {spec_nos_13_value}, + {spec_nos_12_value}, + {spec_nos_11_value}, + {spec_nos_10_value}, + {spec_nos_9_value}, + {spec_nos_8_value}, + {spec_nos_7_value}, + {spec_nos_6_value}, + {spec_nos_5_value}, + {spec_nos_4_value}, + {spec_nos_3_value}, + {spec_nos_2_value}, + {spec_nos_1_value}, + {spec_nos_0_value}}; + wire [4:0] _GEN_8 = _GEN_7[TOSR_value]; + wire topNos_flag = + writeBypassValid ? writeBypassNos_flag : _GEN_6[TOSR_value]; + wire [4:0] topNos_value = writeBypassValid ? writeBypassNos_value : _GEN_8; + wire differentFlag_15 = io_redirect_meta_TOSR_flag ^ BOS_flag; + wire compare_15 = io_redirect_meta_TOSR_value < BOS_value; + wire differentFlag_16 = + io_redirect_meta_TOSR_flag ^ io_redirect_meta_TOSW_flag; + wire compare_16 = + io_redirect_meta_TOSR_value < io_redirect_meta_TOSW_value; + wire redirectTopEntry_inflightValid = + (differentFlag_15 ^ ~compare_15) & (differentFlag_16 ^ compare_16); + wire [40:0] writeEntry_retAddr = + _realPush_T_4 ? io_redirect_callAddr : io_spec_push_addr; + wire _writeEntry_ctr_T_1 = + (redirectTopEntry_inflightValid + ? _GEN_0[io_redirect_meta_TOSR_value] + : _GEN_3[io_redirect_meta_ssp]) == io_redirect_callAddr; + wire [2:0] _sctr_T_12 = 3'(io_redirect_meta_sctr + 3'h1); + wire _writeEntry_ctr_T_7 = + (writeBypassValid + ? writeBypassEntry_retAddr + : topEntry_inflightValid ? _GEN_1 : _GEN_4) == io_spec_push_addr; + wire [2:0] _sctr_T = 3'(sctr + 3'h1); + reg [40:0] timingTop_retAddr; + reg [40:0] realWriteEntry_next_retAddr; + reg [7:0] realWriteEntry_next_ctr; + wire _GEN_9 = io_redirect_isCall | ~io_s3_missed_push; + wire [40:0] realWriteEntry_retAddr = + _GEN_9 ? realWriteEntry_next_retAddr : io_s3_pushAddr; + reg [4:0] realWriteAddr_next_value; + reg realNos_next_flag; + reg [4:0] realNos_next_value; + reg realPush_r; + reg realPush_REG; + wire realPush = + io_s3_fire & (~io_s3_cancel & realPush_r | io_s3_missed_push) | realPush_REG; + wire _GEN_10 = _writeEntry_ctr_T_1 & io_redirect_meta_sctr != 3'h7; + wire _GEN_11 = + io_redirect_isRet & (differentFlag_15 ^ ~compare_15) + & (differentFlag_16 ^ compare_16); + wire [3:0] _sctr_T_16 = 4'(io_redirect_meta_ssp - 4'h1); + wire [3:0] _sctr_T_8 = 4'(io_s3_meta_ssp - 4'h1); + wire _GEN_12 = _writeEntry_ctr_T_7 & sctr != 3'h7; + wire [3:0] _sctr_T_4 = 4'(ssp - 4'h1); + wire writeBypassValidWire = + _realPush_T_4 | ~io_redirect_valid + & (io_s2_fire ? io_spec_push_valid : ~io_s3_fire & writeBypassValid); + wire differentFlag_10 = io_s3_meta_TOSR_flag ^ BOS_flag; + wire compare_10 = io_s3_meta_TOSR_value < BOS_value; + wire differentFlag_11 = io_s3_meta_TOSR_flag ^ io_s3_meta_TOSW_flag; + wire compare_11 = io_s3_meta_TOSR_value < io_s3_meta_TOSW_value; + wire s3TopEntry_inflightValid = + (differentFlag_10 ^ ~compare_10) & (differentFlag_11 ^ compare_11); + wire _GEN_13 = io_redirect_meta_NOS_value >= BOS_value; + wire _GEN_14 = io_redirect_meta_NOS_flag ^ BOS_flag ^ _GEN_13; + wire _GEN_15 = topNos_value >= BOS_value; + wire _GEN_16 = topNos_flag ^ BOS_flag ^ _GEN_15; + wire _GEN_17 = io_s3_meta_NOS_value >= BOS_value; + wire _GEN_18 = io_s3_meta_NOS_flag ^ BOS_flag ^ _GEN_17; + wire _s3_missPushEntry_ctr_T = + (s3TopEntry_inflightValid + ? _GEN_0[io_s3_meta_TOSR_value] + : _GEN_3[io_s3_meta_ssp]) == io_s3_pushAddr; + wire [2:0] _sctr_T_10 = 3'(io_s3_meta_sctr + 3'h1); + wire [7:0] s3_missPushEntry_ctr = + {5'h0, + _s3_missPushEntry_ctr_T + & (s3TopEntry_inflightValid + ? _GEN_2[io_s3_meta_TOSR_value] + : _GEN_5[io_s3_meta_ssp]) < 8'h7 + ? _sctr_T_10 + : 3'h0}; + wire [4:0] realWriteAddr_value = + _GEN_9 ? realWriteAddr_next_value : io_s3_meta_TOSW_value; + wire realNos_flag = _GEN_9 ? realNos_next_flag : io_s3_meta_TOSR_flag; + wire [4:0] realNos_value = _GEN_9 ? realNos_next_value : io_s3_meta_TOSR_value; + wire [5:0] _GEN_19 = {TOSW_flag, TOSW_value}; + wire [5:0] _GEN_20 = {BOS_flag, BOS_value}; + wire _GEN_21 = + io_spec_push_valid & 6'(_GEN_19 + 6'h1) == {BOS_flag, BOS_value}; + wire [5:0] _GEN_22 = {io_s3_meta_TOSW_flag, io_s3_meta_TOSW_value}; + wire _GEN_23 = 6'(_GEN_22 + 6'h1) == {BOS_flag, BOS_value}; + wire [7:0] _GEN_24 = _GEN_5[nsp]; + wire [7:0] _commit_stack_ctr_T = 8'(_GEN_24 - 8'h1); + wire _GEN_25 = io_commit_meta_ssp == 4'h0; + wire _GEN_26 = io_commit_pop_valid & (|_GEN_24) & _GEN_25; + wire _GEN_27 = io_commit_meta_ssp == 4'h1; + wire _GEN_28 = io_commit_pop_valid & (|_GEN_24) & _GEN_27; + wire _GEN_29 = io_commit_meta_ssp == 4'h2; + wire _GEN_30 = io_commit_pop_valid & (|_GEN_24) & _GEN_29; + wire _GEN_31 = io_commit_meta_ssp == 4'h3; + wire _GEN_32 = io_commit_pop_valid & (|_GEN_24) & _GEN_31; + wire _GEN_33 = io_commit_meta_ssp == 4'h4; + wire _GEN_34 = io_commit_pop_valid & (|_GEN_24) & _GEN_33; + wire _GEN_35 = io_commit_meta_ssp == 4'h5; + wire _GEN_36 = io_commit_pop_valid & (|_GEN_24) & _GEN_35; + wire _GEN_37 = io_commit_meta_ssp == 4'h6; + wire _GEN_38 = io_commit_pop_valid & (|_GEN_24) & _GEN_37; + wire _GEN_39 = io_commit_meta_ssp == 4'h7; + wire _GEN_40 = io_commit_pop_valid & (|_GEN_24) & _GEN_39; + wire _GEN_41 = io_commit_meta_ssp == 4'h8; + wire _GEN_42 = io_commit_pop_valid & (|_GEN_24) & _GEN_41; + wire _GEN_43 = io_commit_meta_ssp == 4'h9; + wire _GEN_44 = io_commit_pop_valid & (|_GEN_24) & _GEN_43; + wire _GEN_45 = io_commit_meta_ssp == 4'hA; + wire _GEN_46 = io_commit_pop_valid & (|_GEN_24) & _GEN_45; + wire _GEN_47 = io_commit_meta_ssp == 4'hB; + wire _GEN_48 = io_commit_pop_valid & (|_GEN_24) & _GEN_47; + wire _GEN_49 = io_commit_meta_ssp == 4'hC; + wire _GEN_50 = io_commit_pop_valid & (|_GEN_24) & _GEN_49; + wire _GEN_51 = io_commit_meta_ssp == 4'hD; + wire _GEN_52 = io_commit_pop_valid & (|_GEN_24) & _GEN_51; + wire _GEN_53 = io_commit_meta_ssp == 4'hE; + wire _GEN_54 = io_commit_pop_valid & (|_GEN_24) & _GEN_53; + wire _GEN_55 = io_commit_pop_valid & (|_GEN_24) & (&io_commit_meta_ssp); + wire _GEN_56 = + _GEN_24 < 8'h7 & _GEN_3[nsp] == _GEN_0[io_commit_meta_TOSW_value]; + wire [3:0] _nsp_T_2 = 4'(io_commit_meta_ssp + 4'h1); + wire _GEN_57 = _nsp_T_2 == 4'h0; + wire _GEN_58 = _nsp_T_2 == 4'h1; + wire _GEN_59 = _nsp_T_2 == 4'h2; + wire _GEN_60 = _nsp_T_2 == 4'h3; + wire _GEN_61 = _nsp_T_2 == 4'h4; + wire _GEN_62 = _nsp_T_2 == 4'h5; + wire _GEN_63 = _nsp_T_2 == 4'h6; + wire _GEN_64 = _nsp_T_2 == 4'h7; + wire _GEN_65 = _nsp_T_2 == 4'h8; + wire _GEN_66 = _nsp_T_2 == 4'h9; + wire _GEN_67 = _nsp_T_2 == 4'hA; + wire _GEN_68 = _nsp_T_2 == 4'hB; + wire _GEN_69 = _nsp_T_2 == 4'hC; + wire _GEN_70 = _nsp_T_2 == 4'hD; + wire _GEN_71 = _nsp_T_2 == 4'hE; + wire [5:0] _GEN_72 = {io_commit_meta_TOSW_flag, io_commit_meta_TOSW_value}; + wire [5:0] _new_ptr_T_11 = 6'(_GEN_72 + 6'h1); + wire _GEN_73 = + io_commit_push_valid + & (~spec_overflowed | _new_ptr_T_11[5] ^ BOS_flag ^ _new_ptr_T_11[4:0] > BOS_value); + wire [5:0] _GEN_74 = {io_redirect_meta_TOSW_flag, io_redirect_meta_TOSW_value}; + wire _GEN_75 = + io_redirect_valid & io_redirect_isCall & 6'(_GEN_74 + 6'h1) == {BOS_flag, BOS_value}; + wire [7:0] _commit_stack_ctr_T_2 = 8'(_GEN_24 + 8'h1); + wire [5:0] _GEN_76 = 6'(_GEN_74 + 6'h1); + wire inflightValid_8 = + _GEN_14 + & (io_redirect_meta_NOS_flag ^ io_redirect_meta_TOSW_flag + ^ io_redirect_meta_NOS_value < io_redirect_meta_TOSW_value); + wire _GEN_77 = + io_s3_missed_pop & (differentFlag_10 ^ ~compare_10) & (differentFlag_11 ^ compare_11); + wire inflightValid_6 = + _GEN_18 + & (io_s3_meta_NOS_flag ^ io_s3_meta_TOSW_flag + ^ io_s3_meta_NOS_value < io_s3_meta_TOSW_value); + wire [5:0] _GEN_78 = 6'(_GEN_22 + 6'h1); + wire _GEN_79 = _s3_missPushEntry_ctr_T & io_s3_meta_sctr != 3'h7; + wire inflightValid_4 = + _GEN_16 & (topNos_flag ^ TOSW_flag ^ topNos_value < TOSW_value); + wire [5:0] _GEN_80 = 6'(_GEN_19 + 6'h1); + wire [5:0] _BOS_new_ptr_T_16 = 6'(_GEN_20 + 6'h1); + wire [5:0] _BOS_new_ptr_T_11 = 6'(_GEN_72 + 6'h1); + wire [5:0] _BOS_new_ptr_T_6 = 6'(_GEN_20 + 6'h1); + wire [5:0] _BOS_new_ptr_T_1 = 6'(_GEN_20 + 6'h1); + always @(posedge clock or posedge reset) begin + if (reset) begin + commit_stack_0_retAddr <= 41'h0; + commit_stack_0_ctr <= 8'h0; + commit_stack_1_retAddr <= 41'h0; + commit_stack_1_ctr <= 8'h0; + commit_stack_2_retAddr <= 41'h0; + commit_stack_2_ctr <= 8'h0; + commit_stack_3_retAddr <= 41'h0; + commit_stack_3_ctr <= 8'h0; + commit_stack_4_retAddr <= 41'h0; + commit_stack_4_ctr <= 8'h0; + commit_stack_5_retAddr <= 41'h0; + commit_stack_5_ctr <= 8'h0; + commit_stack_6_retAddr <= 41'h0; + commit_stack_6_ctr <= 8'h0; + commit_stack_7_retAddr <= 41'h0; + commit_stack_7_ctr <= 8'h0; + commit_stack_8_retAddr <= 41'h0; + commit_stack_8_ctr <= 8'h0; + commit_stack_9_retAddr <= 41'h0; + commit_stack_9_ctr <= 8'h0; + commit_stack_10_retAddr <= 41'h0; + commit_stack_10_ctr <= 8'h0; + commit_stack_11_retAddr <= 41'h0; + commit_stack_11_ctr <= 8'h0; + commit_stack_12_retAddr <= 41'h0; + commit_stack_12_ctr <= 8'h0; + commit_stack_13_retAddr <= 41'h0; + commit_stack_13_ctr <= 8'h0; + commit_stack_14_retAddr <= 41'h0; + commit_stack_14_ctr <= 8'h0; + commit_stack_15_retAddr <= 41'h0; + commit_stack_15_ctr <= 8'h0; + spec_queue_0_retAddr <= 41'h0; + spec_queue_0_ctr <= 8'h0; + spec_queue_1_retAddr <= 41'h0; + spec_queue_1_ctr <= 8'h0; + spec_queue_2_retAddr <= 41'h0; + spec_queue_2_ctr <= 8'h0; + spec_queue_3_retAddr <= 41'h0; + spec_queue_3_ctr <= 8'h0; + spec_queue_4_retAddr <= 41'h0; + spec_queue_4_ctr <= 8'h0; + spec_queue_5_retAddr <= 41'h0; + spec_queue_5_ctr <= 8'h0; + spec_queue_6_retAddr <= 41'h0; + spec_queue_6_ctr <= 8'h0; + spec_queue_7_retAddr <= 41'h0; + spec_queue_7_ctr <= 8'h0; + spec_queue_8_retAddr <= 41'h0; + spec_queue_8_ctr <= 8'h0; + spec_queue_9_retAddr <= 41'h0; + spec_queue_9_ctr <= 8'h0; + spec_queue_10_retAddr <= 41'h0; + spec_queue_10_ctr <= 8'h0; + spec_queue_11_retAddr <= 41'h0; + spec_queue_11_ctr <= 8'h0; + spec_queue_12_retAddr <= 41'h0; + spec_queue_12_ctr <= 8'h0; + spec_queue_13_retAddr <= 41'h0; + spec_queue_13_ctr <= 8'h0; + spec_queue_14_retAddr <= 41'h0; + spec_queue_14_ctr <= 8'h0; + spec_queue_15_retAddr <= 41'h0; + spec_queue_15_ctr <= 8'h0; + spec_queue_16_retAddr <= 41'h0; + spec_queue_16_ctr <= 8'h0; + spec_queue_17_retAddr <= 41'h0; + spec_queue_17_ctr <= 8'h0; + spec_queue_18_retAddr <= 41'h0; + spec_queue_18_ctr <= 8'h0; + spec_queue_19_retAddr <= 41'h0; + spec_queue_19_ctr <= 8'h0; + spec_queue_20_retAddr <= 41'h0; + spec_queue_20_ctr <= 8'h0; + spec_queue_21_retAddr <= 41'h0; + spec_queue_21_ctr <= 8'h0; + spec_queue_22_retAddr <= 41'h0; + spec_queue_22_ctr <= 8'h0; + spec_queue_23_retAddr <= 41'h0; + spec_queue_23_ctr <= 8'h0; + spec_queue_24_retAddr <= 41'h0; + spec_queue_24_ctr <= 8'h0; + spec_queue_25_retAddr <= 41'h0; + spec_queue_25_ctr <= 8'h0; + spec_queue_26_retAddr <= 41'h0; + spec_queue_26_ctr <= 8'h0; + spec_queue_27_retAddr <= 41'h0; + spec_queue_27_ctr <= 8'h0; + spec_queue_28_retAddr <= 41'h0; + spec_queue_28_ctr <= 8'h0; + spec_queue_29_retAddr <= 41'h0; + spec_queue_29_ctr <= 8'h0; + spec_queue_30_retAddr <= 41'h0; + spec_queue_30_ctr <= 8'h0; + spec_queue_31_retAddr <= 41'h0; + spec_queue_31_ctr <= 8'h0; + spec_nos_0_flag <= 1'h0; + spec_nos_0_value <= 5'h0; + spec_nos_1_flag <= 1'h0; + spec_nos_1_value <= 5'h0; + spec_nos_2_flag <= 1'h0; + spec_nos_2_value <= 5'h0; + spec_nos_3_flag <= 1'h0; + spec_nos_3_value <= 5'h0; + spec_nos_4_flag <= 1'h0; + spec_nos_4_value <= 5'h0; + spec_nos_5_flag <= 1'h0; + spec_nos_5_value <= 5'h0; + spec_nos_6_flag <= 1'h0; + spec_nos_6_value <= 5'h0; + spec_nos_7_flag <= 1'h0; + spec_nos_7_value <= 5'h0; + spec_nos_8_flag <= 1'h0; + spec_nos_8_value <= 5'h0; + spec_nos_9_flag <= 1'h0; + spec_nos_9_value <= 5'h0; + spec_nos_10_flag <= 1'h0; + spec_nos_10_value <= 5'h0; + spec_nos_11_flag <= 1'h0; + spec_nos_11_value <= 5'h0; + spec_nos_12_flag <= 1'h0; + spec_nos_12_value <= 5'h0; + spec_nos_13_flag <= 1'h0; + spec_nos_13_value <= 5'h0; + spec_nos_14_flag <= 1'h0; + spec_nos_14_value <= 5'h0; + spec_nos_15_flag <= 1'h0; + spec_nos_15_value <= 5'h0; + spec_nos_16_flag <= 1'h0; + spec_nos_16_value <= 5'h0; + spec_nos_17_flag <= 1'h0; + spec_nos_17_value <= 5'h0; + spec_nos_18_flag <= 1'h0; + spec_nos_18_value <= 5'h0; + spec_nos_19_flag <= 1'h0; + spec_nos_19_value <= 5'h0; + spec_nos_20_flag <= 1'h0; + spec_nos_20_value <= 5'h0; + spec_nos_21_flag <= 1'h0; + spec_nos_21_value <= 5'h0; + spec_nos_22_flag <= 1'h0; + spec_nos_22_value <= 5'h0; + spec_nos_23_flag <= 1'h0; + spec_nos_23_value <= 5'h0; + spec_nos_24_flag <= 1'h0; + spec_nos_24_value <= 5'h0; + spec_nos_25_flag <= 1'h0; + spec_nos_25_value <= 5'h0; + spec_nos_26_flag <= 1'h0; + spec_nos_26_value <= 5'h0; + spec_nos_27_flag <= 1'h0; + spec_nos_27_value <= 5'h0; + spec_nos_28_flag <= 1'h0; + spec_nos_28_value <= 5'h0; + spec_nos_29_flag <= 1'h0; + spec_nos_29_value <= 5'h0; + spec_nos_30_flag <= 1'h0; + spec_nos_30_value <= 5'h0; + spec_nos_31_flag <= 1'h0; + spec_nos_31_value <= 5'h0; + nsp <= 4'h0; + ssp <= 4'h0; + sctr <= 3'h0; + TOSR_flag <= 1'h1; + TOSR_value <= 5'h1F; + TOSW_flag <= 1'h0; + TOSW_value <= 5'h0; + BOS_flag <= 1'h0; + BOS_value <= 5'h0; + spec_overflowed <= 1'h0; + writeBypassValid <= 1'h0; + timingTop_retAddr <= 41'h0; + end + else begin + if (~io_commit_push_valid | _GEN_56 | ~_GEN_57) begin + end + else + commit_stack_0_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (io_commit_push_valid) begin + if (_GEN_56) begin + if (_GEN_25) + commit_stack_0_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_26) + commit_stack_0_ctr <= _commit_stack_ctr_T; + if (_GEN_27) + commit_stack_1_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_28) + commit_stack_1_ctr <= _commit_stack_ctr_T; + if (_GEN_29) + commit_stack_2_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_30) + commit_stack_2_ctr <= _commit_stack_ctr_T; + if (_GEN_31) + commit_stack_3_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_32) + commit_stack_3_ctr <= _commit_stack_ctr_T; + if (_GEN_33) + commit_stack_4_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_34) + commit_stack_4_ctr <= _commit_stack_ctr_T; + if (_GEN_35) + commit_stack_5_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_36) + commit_stack_5_ctr <= _commit_stack_ctr_T; + if (_GEN_37) + commit_stack_6_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_38) + commit_stack_6_ctr <= _commit_stack_ctr_T; + if (_GEN_39) + commit_stack_7_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_40) + commit_stack_7_ctr <= _commit_stack_ctr_T; + if (_GEN_41) + commit_stack_8_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_42) + commit_stack_8_ctr <= _commit_stack_ctr_T; + if (_GEN_43) + commit_stack_9_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_44) + commit_stack_9_ctr <= _commit_stack_ctr_T; + if (_GEN_45) + commit_stack_10_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_46) + commit_stack_10_ctr <= _commit_stack_ctr_T; + if (_GEN_47) + commit_stack_11_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_48) + commit_stack_11_ctr <= _commit_stack_ctr_T; + if (_GEN_49) + commit_stack_12_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_50) + commit_stack_12_ctr <= _commit_stack_ctr_T; + if (_GEN_51) + commit_stack_13_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_52) + commit_stack_13_ctr <= _commit_stack_ctr_T; + if (_GEN_53) + commit_stack_14_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_54) + commit_stack_14_ctr <= _commit_stack_ctr_T; + if (&io_commit_meta_ssp) + commit_stack_15_ctr <= _commit_stack_ctr_T_2; + else if (_GEN_55) + commit_stack_15_ctr <= _commit_stack_ctr_T; + nsp <= io_commit_meta_ssp; + end + else begin + if (_GEN_57) + commit_stack_0_ctr <= 8'h0; + else if (_GEN_26) + commit_stack_0_ctr <= _commit_stack_ctr_T; + if (_GEN_58) + commit_stack_1_ctr <= 8'h0; + else if (_GEN_28) + commit_stack_1_ctr <= _commit_stack_ctr_T; + if (_GEN_59) + commit_stack_2_ctr <= 8'h0; + else if (_GEN_30) + commit_stack_2_ctr <= _commit_stack_ctr_T; + if (_GEN_60) + commit_stack_3_ctr <= 8'h0; + else if (_GEN_32) + commit_stack_3_ctr <= _commit_stack_ctr_T; + if (_GEN_61) + commit_stack_4_ctr <= 8'h0; + else if (_GEN_34) + commit_stack_4_ctr <= _commit_stack_ctr_T; + if (_GEN_62) + commit_stack_5_ctr <= 8'h0; + else if (_GEN_36) + commit_stack_5_ctr <= _commit_stack_ctr_T; + if (_GEN_63) + commit_stack_6_ctr <= 8'h0; + else if (_GEN_38) + commit_stack_6_ctr <= _commit_stack_ctr_T; + if (_GEN_64) + commit_stack_7_ctr <= 8'h0; + else if (_GEN_40) + commit_stack_7_ctr <= _commit_stack_ctr_T; + if (_GEN_65) + commit_stack_8_ctr <= 8'h0; + else if (_GEN_42) + commit_stack_8_ctr <= _commit_stack_ctr_T; + if (_GEN_66) + commit_stack_9_ctr <= 8'h0; + else if (_GEN_44) + commit_stack_9_ctr <= _commit_stack_ctr_T; + if (_GEN_67) + commit_stack_10_ctr <= 8'h0; + else if (_GEN_46) + commit_stack_10_ctr <= _commit_stack_ctr_T; + if (_GEN_68) + commit_stack_11_ctr <= 8'h0; + else if (_GEN_48) + commit_stack_11_ctr <= _commit_stack_ctr_T; + if (_GEN_69) + commit_stack_12_ctr <= 8'h0; + else if (_GEN_50) + commit_stack_12_ctr <= _commit_stack_ctr_T; + if (_GEN_70) + commit_stack_13_ctr <= 8'h0; + else if (_GEN_52) + commit_stack_13_ctr <= _commit_stack_ctr_T; + if (_GEN_71) + commit_stack_14_ctr <= 8'h0; + else if (_GEN_54) + commit_stack_14_ctr <= _commit_stack_ctr_T; + if (&_nsp_T_2) + commit_stack_15_ctr <= 8'h0; + else if (_GEN_55) + commit_stack_15_ctr <= _commit_stack_ctr_T; + nsp <= _nsp_T_2; + end + end + else begin + if (_GEN_26) + commit_stack_0_ctr <= _commit_stack_ctr_T; + if (_GEN_28) + commit_stack_1_ctr <= _commit_stack_ctr_T; + if (_GEN_30) + commit_stack_2_ctr <= _commit_stack_ctr_T; + if (_GEN_32) + commit_stack_3_ctr <= _commit_stack_ctr_T; + if (_GEN_34) + commit_stack_4_ctr <= _commit_stack_ctr_T; + if (_GEN_36) + commit_stack_5_ctr <= _commit_stack_ctr_T; + if (_GEN_38) + commit_stack_6_ctr <= _commit_stack_ctr_T; + if (_GEN_40) + commit_stack_7_ctr <= _commit_stack_ctr_T; + if (_GEN_42) + commit_stack_8_ctr <= _commit_stack_ctr_T; + if (_GEN_44) + commit_stack_9_ctr <= _commit_stack_ctr_T; + if (_GEN_46) + commit_stack_10_ctr <= _commit_stack_ctr_T; + if (_GEN_48) + commit_stack_11_ctr <= _commit_stack_ctr_T; + if (_GEN_50) + commit_stack_12_ctr <= _commit_stack_ctr_T; + if (_GEN_52) + commit_stack_13_ctr <= _commit_stack_ctr_T; + if (_GEN_54) + commit_stack_14_ctr <= _commit_stack_ctr_T; + if (_GEN_55) + commit_stack_15_ctr <= _commit_stack_ctr_T; + if (io_commit_pop_valid) begin + if (|_GEN_24) + nsp <= io_commit_meta_ssp; + else + nsp <= 4'(io_commit_meta_ssp - 4'h1); + end + end + if (~io_commit_push_valid | _GEN_56 | ~_GEN_58) begin + end + else + commit_stack_1_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~_GEN_59) begin + end + else + commit_stack_2_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~_GEN_60) begin + end + else + commit_stack_3_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~_GEN_61) begin + end + else + commit_stack_4_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~_GEN_62) begin + end + else + commit_stack_5_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~_GEN_63) begin + end + else + commit_stack_6_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~_GEN_64) begin + end + else + commit_stack_7_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~_GEN_65) begin + end + else + commit_stack_8_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~_GEN_66) begin + end + else + commit_stack_9_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~_GEN_67) begin + end + else + commit_stack_10_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~_GEN_68) begin + end + else + commit_stack_11_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~_GEN_69) begin + end + else + commit_stack_12_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~_GEN_70) begin + end + else + commit_stack_13_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~_GEN_71) begin + end + else + commit_stack_14_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (~io_commit_push_valid | _GEN_56 | ~(&_nsp_T_2)) begin + end + else + commit_stack_15_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; + if (realPush & realWriteAddr_value == 5'h0) begin + spec_queue_0_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_0_ctr <= realWriteEntry_next_ctr; + else + spec_queue_0_ctr <= s3_missPushEntry_ctr; + spec_nos_0_flag <= realNos_flag; + spec_nos_0_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h1) begin + spec_queue_1_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_1_ctr <= realWriteEntry_next_ctr; + else + spec_queue_1_ctr <= s3_missPushEntry_ctr; + spec_nos_1_flag <= realNos_flag; + spec_nos_1_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h2) begin + spec_queue_2_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_2_ctr <= realWriteEntry_next_ctr; + else + spec_queue_2_ctr <= s3_missPushEntry_ctr; + spec_nos_2_flag <= realNos_flag; + spec_nos_2_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h3) begin + spec_queue_3_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_3_ctr <= realWriteEntry_next_ctr; + else + spec_queue_3_ctr <= s3_missPushEntry_ctr; + spec_nos_3_flag <= realNos_flag; + spec_nos_3_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h4) begin + spec_queue_4_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_4_ctr <= realWriteEntry_next_ctr; + else + spec_queue_4_ctr <= s3_missPushEntry_ctr; + spec_nos_4_flag <= realNos_flag; + spec_nos_4_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h5) begin + spec_queue_5_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_5_ctr <= realWriteEntry_next_ctr; + else + spec_queue_5_ctr <= s3_missPushEntry_ctr; + spec_nos_5_flag <= realNos_flag; + spec_nos_5_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h6) begin + spec_queue_6_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_6_ctr <= realWriteEntry_next_ctr; + else + spec_queue_6_ctr <= s3_missPushEntry_ctr; + spec_nos_6_flag <= realNos_flag; + spec_nos_6_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h7) begin + spec_queue_7_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_7_ctr <= realWriteEntry_next_ctr; + else + spec_queue_7_ctr <= s3_missPushEntry_ctr; + spec_nos_7_flag <= realNos_flag; + spec_nos_7_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h8) begin + spec_queue_8_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_8_ctr <= realWriteEntry_next_ctr; + else + spec_queue_8_ctr <= s3_missPushEntry_ctr; + spec_nos_8_flag <= realNos_flag; + spec_nos_8_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h9) begin + spec_queue_9_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_9_ctr <= realWriteEntry_next_ctr; + else + spec_queue_9_ctr <= s3_missPushEntry_ctr; + spec_nos_9_flag <= realNos_flag; + spec_nos_9_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'hA) begin + spec_queue_10_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_10_ctr <= realWriteEntry_next_ctr; + else + spec_queue_10_ctr <= s3_missPushEntry_ctr; + spec_nos_10_flag <= realNos_flag; + spec_nos_10_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'hB) begin + spec_queue_11_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_11_ctr <= realWriteEntry_next_ctr; + else + spec_queue_11_ctr <= s3_missPushEntry_ctr; + spec_nos_11_flag <= realNos_flag; + spec_nos_11_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'hC) begin + spec_queue_12_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_12_ctr <= realWriteEntry_next_ctr; + else + spec_queue_12_ctr <= s3_missPushEntry_ctr; + spec_nos_12_flag <= realNos_flag; + spec_nos_12_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'hD) begin + spec_queue_13_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_13_ctr <= realWriteEntry_next_ctr; + else + spec_queue_13_ctr <= s3_missPushEntry_ctr; + spec_nos_13_flag <= realNos_flag; + spec_nos_13_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'hE) begin + spec_queue_14_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_14_ctr <= realWriteEntry_next_ctr; + else + spec_queue_14_ctr <= s3_missPushEntry_ctr; + spec_nos_14_flag <= realNos_flag; + spec_nos_14_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'hF) begin + spec_queue_15_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_15_ctr <= realWriteEntry_next_ctr; + else + spec_queue_15_ctr <= s3_missPushEntry_ctr; + spec_nos_15_flag <= realNos_flag; + spec_nos_15_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h10) begin + spec_queue_16_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_16_ctr <= realWriteEntry_next_ctr; + else + spec_queue_16_ctr <= s3_missPushEntry_ctr; + spec_nos_16_flag <= realNos_flag; + spec_nos_16_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h11) begin + spec_queue_17_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_17_ctr <= realWriteEntry_next_ctr; + else + spec_queue_17_ctr <= s3_missPushEntry_ctr; + spec_nos_17_flag <= realNos_flag; + spec_nos_17_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h12) begin + spec_queue_18_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_18_ctr <= realWriteEntry_next_ctr; + else + spec_queue_18_ctr <= s3_missPushEntry_ctr; + spec_nos_18_flag <= realNos_flag; + spec_nos_18_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h13) begin + spec_queue_19_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_19_ctr <= realWriteEntry_next_ctr; + else + spec_queue_19_ctr <= s3_missPushEntry_ctr; + spec_nos_19_flag <= realNos_flag; + spec_nos_19_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h14) begin + spec_queue_20_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_20_ctr <= realWriteEntry_next_ctr; + else + spec_queue_20_ctr <= s3_missPushEntry_ctr; + spec_nos_20_flag <= realNos_flag; + spec_nos_20_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h15) begin + spec_queue_21_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_21_ctr <= realWriteEntry_next_ctr; + else + spec_queue_21_ctr <= s3_missPushEntry_ctr; + spec_nos_21_flag <= realNos_flag; + spec_nos_21_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h16) begin + spec_queue_22_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_22_ctr <= realWriteEntry_next_ctr; + else + spec_queue_22_ctr <= s3_missPushEntry_ctr; + spec_nos_22_flag <= realNos_flag; + spec_nos_22_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h17) begin + spec_queue_23_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_23_ctr <= realWriteEntry_next_ctr; + else + spec_queue_23_ctr <= s3_missPushEntry_ctr; + spec_nos_23_flag <= realNos_flag; + spec_nos_23_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h18) begin + spec_queue_24_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_24_ctr <= realWriteEntry_next_ctr; + else + spec_queue_24_ctr <= s3_missPushEntry_ctr; + spec_nos_24_flag <= realNos_flag; + spec_nos_24_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h19) begin + spec_queue_25_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_25_ctr <= realWriteEntry_next_ctr; + else + spec_queue_25_ctr <= s3_missPushEntry_ctr; + spec_nos_25_flag <= realNos_flag; + spec_nos_25_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h1A) begin + spec_queue_26_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_26_ctr <= realWriteEntry_next_ctr; + else + spec_queue_26_ctr <= s3_missPushEntry_ctr; + spec_nos_26_flag <= realNos_flag; + spec_nos_26_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h1B) begin + spec_queue_27_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_27_ctr <= realWriteEntry_next_ctr; + else + spec_queue_27_ctr <= s3_missPushEntry_ctr; + spec_nos_27_flag <= realNos_flag; + spec_nos_27_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h1C) begin + spec_queue_28_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_28_ctr <= realWriteEntry_next_ctr; + else + spec_queue_28_ctr <= s3_missPushEntry_ctr; + spec_nos_28_flag <= realNos_flag; + spec_nos_28_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h1D) begin + spec_queue_29_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_29_ctr <= realWriteEntry_next_ctr; + else + spec_queue_29_ctr <= s3_missPushEntry_ctr; + spec_nos_29_flag <= realNos_flag; + spec_nos_29_value <= realNos_value; + end + if (realPush & realWriteAddr_value == 5'h1E) begin + spec_queue_30_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_30_ctr <= realWriteEntry_next_ctr; + else + spec_queue_30_ctr <= s3_missPushEntry_ctr; + spec_nos_30_flag <= realNos_flag; + spec_nos_30_value <= realNos_value; + end + if (realPush & (&realWriteAddr_value)) begin + spec_queue_31_retAddr <= realWriteEntry_retAddr; + if (_GEN_9) + spec_queue_31_ctr <= realWriteEntry_next_ctr; + else + spec_queue_31_ctr <= s3_missPushEntry_ctr; + spec_nos_31_flag <= realNos_flag; + spec_nos_31_value <= realNos_value; + end + if (io_redirect_valid) begin + ssp <= + ~io_redirect_isRet | (|io_redirect_meta_sctr) + ? (~io_redirect_isCall | _GEN_10 + ? io_redirect_meta_ssp + : 4'(io_redirect_meta_ssp + 4'h1)) + : inflightValid_8 ? 4'(io_redirect_meta_ssp - 4'h1) : _sctr_T_16; + sctr <= + io_redirect_isRet + ? ((|io_redirect_meta_sctr) + ? 3'(io_redirect_meta_sctr - 3'h1) + : inflightValid_8 + ? _GEN_2[io_redirect_meta_NOS_value][2:0] + : _GEN_5[_sctr_T_16][2:0]) + : io_redirect_isCall ? (_GEN_10 ? _sctr_T_12 : 3'h0) : io_redirect_meta_sctr; + TOSR_flag <= + _GEN_11 + ? io_redirect_meta_NOS_flag + : io_redirect_isCall + ? io_redirect_meta_TOSW_flag + : io_redirect_meta_TOSR_flag; + TOSR_value <= + _GEN_11 + ? io_redirect_meta_NOS_value + : io_redirect_isCall + ? io_redirect_meta_TOSW_value + : io_redirect_meta_TOSR_value; + TOSW_flag <= io_redirect_isCall ? _GEN_76[5] : io_redirect_meta_TOSW_flag; + TOSW_value <= io_redirect_isCall ? _GEN_76[4:0] : io_redirect_meta_TOSW_value; + end + else if (io_s3_cancel) begin + ssp <= + ~io_s3_missed_push | _GEN_79 + ? (~io_s3_missed_pop | (|io_s3_meta_sctr) + ? io_s3_meta_ssp + : inflightValid_6 ? 4'(io_s3_meta_ssp - 4'h1) : _sctr_T_8) + : 4'(io_s3_meta_ssp + 4'h1); + sctr <= + io_s3_missed_push + ? (_GEN_79 ? _sctr_T_10 : 3'h0) + : io_s3_missed_pop + ? ((|io_s3_meta_sctr) + ? 3'(io_s3_meta_sctr - 3'h1) + : inflightValid_6 + ? _GEN_2[io_s3_meta_NOS_value][2:0] + : _GEN_5[_sctr_T_8][2:0]) + : io_s3_meta_sctr; + TOSR_flag <= + io_s3_missed_push + ? io_s3_meta_TOSW_flag + : _GEN_77 ? io_s3_meta_NOS_flag : io_s3_meta_TOSR_flag; + TOSR_value <= + io_s3_missed_push + ? io_s3_meta_TOSW_value + : _GEN_77 ? io_s3_meta_NOS_value : io_s3_meta_TOSR_value; + TOSW_flag <= io_s3_missed_push ? _GEN_78[5] : io_s3_meta_TOSW_flag; + TOSW_value <= io_s3_missed_push ? _GEN_78[4:0] : io_s3_meta_TOSW_value; + end + else begin + if (~io_spec_pop_valid | (|sctr)) begin + if (~io_spec_push_valid | _GEN_12) begin + end + else + ssp <= 4'(ssp + 4'h1); + end + else if (inflightValid_4) + ssp <= 4'(ssp - 4'h1); + else + ssp <= _sctr_T_4; + if (io_spec_pop_valid) begin + if (|sctr) + sctr <= 3'(sctr - 3'h1); + else + sctr <= inflightValid_4 ? _GEN_2[topNos_value][2:0] : _GEN_5[_sctr_T_4][2:0]; + end + else if (io_spec_push_valid) begin + if (_GEN_12) + sctr <= _sctr_T; + else + sctr <= 3'h0; + end + if (io_spec_pop_valid & (TOSR_flag ^ BOS_flag ^ _GEN) + & (TOSR_flag ^ TOSW_flag ^ TOSR_value < TOSW_value)) begin + TOSR_flag <= topNos_flag; + if (writeBypassValid) + TOSR_value <= writeBypassNos_value; + else + TOSR_value <= _GEN_8; + end + else if (io_spec_push_valid) begin + TOSR_flag <= TOSW_flag; + TOSR_value <= TOSW_value; + end + if (io_spec_push_valid) begin + TOSW_flag <= _GEN_80[5]; + TOSW_value <= _GEN_80[4:0]; + end + end + if (_GEN_75) begin + BOS_flag <= _BOS_new_ptr_T_16[5]; + BOS_value <= _BOS_new_ptr_T_16[4:0]; + end + else if (_GEN_73) begin + BOS_flag <= _BOS_new_ptr_T_11[5]; + BOS_value <= _BOS_new_ptr_T_11[4:0]; + end + else if (io_s3_cancel & io_s3_missed_push & _GEN_23) begin + BOS_flag <= _BOS_new_ptr_T_6[5]; + BOS_value <= _BOS_new_ptr_T_6[4:0]; + end + else if (_GEN_21) begin + BOS_flag <= _BOS_new_ptr_T_1[5]; + BOS_value <= _BOS_new_ptr_T_1[4:0]; + end + spec_overflowed <= + _GEN_75 | ~_GEN_73 + & (io_s3_cancel & io_s3_missed_push + ? _GEN_23 | _GEN_21 | spec_overflowed + : _GEN_21 | spec_overflowed); + writeBypassValid <= writeBypassValidWire; + timingTop_retAddr <= + writeBypassValidWire + ? (_realPush_T_4 | io_spec_push_valid + ? writeEntry_retAddr + : writeBypassEntry_retAddr) + : io_redirect_valid & io_redirect_isRet + ? ((io_redirect_meta_NOS_flag ^ BOS_flag ^ _GEN_13) + & (io_redirect_meta_NOS_flag ^ io_redirect_meta_TOSW_flag + ^ io_redirect_meta_NOS_value < io_redirect_meta_TOSW_value) + ? _GEN_0[io_redirect_meta_NOS_value] + : _GEN_3[(|io_redirect_meta_sctr) + ? io_redirect_meta_ssp + : _GEN_14 + & (io_redirect_meta_NOS_flag ^ TOSW_flag + ^ io_redirect_meta_NOS_value < TOSW_value) + ? 4'(io_redirect_meta_ssp - 4'h1) + : 4'(io_redirect_meta_ssp - 4'h1)]) + : io_redirect_valid + ? ((differentFlag_15 ^ ~compare_15) & (differentFlag_16 ^ compare_16) + ? _GEN_0[io_redirect_meta_TOSR_value] + : _GEN_3[io_redirect_meta_ssp]) + : io_spec_pop_valid + ? ((topNos_flag ^ BOS_flag ^ _GEN_15) + & (topNos_flag ^ TOSW_flag ^ topNos_value < TOSW_value) + ? _GEN_0[topNos_value] + : _GEN_3[(|sctr) + ? ssp + : _GEN_16 + & (topNos_flag ^ TOSW_flag + ^ topNos_value < TOSW_value) + ? 4'(ssp - 4'h1) + : 4'(ssp - 4'h1)]) + : realPush + ? realWriteEntry_retAddr + : io_s3_cancel + ? (io_s3_missed_push + ? io_s3_pushAddr + : io_s3_missed_pop + ? ((io_s3_meta_NOS_flag ^ BOS_flag ^ _GEN_17) + & (io_s3_meta_NOS_flag ^ io_s3_meta_TOSW_flag + ^ io_s3_meta_NOS_value < io_s3_meta_TOSW_value) + ? _GEN_0[io_s3_meta_NOS_value] + : _GEN_3[(|io_s3_meta_sctr) + ? io_s3_meta_ssp + : _GEN_18 + & (io_s3_meta_NOS_flag + ^ io_s3_meta_TOSW_flag + ^ io_s3_meta_NOS_value < io_s3_meta_TOSW_value) + ? 4'(io_s3_meta_ssp - 4'h1) + : 4'(io_s3_meta_ssp - 4'h1)]) + : (differentFlag_10 ^ ~compare_10) + & (differentFlag_11 ^ compare_11) + ? _GEN_0[io_s3_meta_TOSR_value] + : _GEN_3[io_s3_meta_ssp]) + : (TOSR_flag ^ BOS_flag ^ _GEN) + & (TOSR_flag ^ TOSW_flag ^ TOSR_value < TOSW_value) + ? _GEN_1 + : _GEN_4; + end + end // always @(posedge, posedge) + wire [7:0] writeEntry_ctr = + {5'h0, + _realPush_T_4 + ? (_writeEntry_ctr_T_1 + & (redirectTopEntry_inflightValid + ? _GEN_2[io_redirect_meta_TOSR_value] + : _GEN_5[io_redirect_meta_ssp]) < 8'h7 + ? _sctr_T_12 + : 3'h0) + : _writeEntry_ctr_T_7 + & (writeBypassValid + ? writeBypassEntry_ctr + : topEntry_inflightValid ? _GEN_2[TOSR_value] : _GEN_5[ssp]) < 8'h7 + ? _sctr_T + : 3'h0}; + always @(posedge clock) begin + if (io_spec_push_valid | _realPush_T_4) begin + writeBypassEntry_retAddr <= writeEntry_retAddr; + writeBypassEntry_ctr <= writeEntry_ctr; + writeBypassNos_flag <= _realPush_T_4 ? io_redirect_meta_NOS_flag : TOSR_flag; + writeBypassNos_value <= _realPush_T_4 ? io_redirect_meta_NOS_value : TOSR_value; + end + if (io_s2_fire | io_redirect_isCall) begin + realWriteEntry_next_retAddr <= writeEntry_retAddr; + realWriteEntry_next_ctr <= writeEntry_ctr; + end + if (io_s2_fire | _realPush_T_4) + realWriteAddr_next_value <= + _realPush_T_4 ? io_redirect_meta_TOSW_value : TOSW_value; + if (io_s2_fire | _realPush_T_4) begin + realNos_next_flag <= _realPush_T_4 ? io_redirect_meta_TOSR_flag : TOSR_flag; + realNos_next_value <= _realPush_T_4 ? io_redirect_meta_TOSR_value : TOSR_value; + end + if (io_s2_fire) + realPush_r <= io_spec_push_valid; + realPush_REG <= _realPush_T_4; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:85]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [6:0] i = 7'h0; i < 7'h56; i += 7'h1) begin + _RANDOM[i] = `RANDOM; + end + commit_stack_0_retAddr = {_RANDOM[7'h0], _RANDOM[7'h1][8:0]}; + commit_stack_0_ctr = _RANDOM[7'h1][16:9]; + commit_stack_1_retAddr = {_RANDOM[7'h1][31:17], _RANDOM[7'h2][25:0]}; + commit_stack_1_ctr = {_RANDOM[7'h2][31:26], _RANDOM[7'h3][1:0]}; + commit_stack_2_retAddr = {_RANDOM[7'h3][31:2], _RANDOM[7'h4][10:0]}; + commit_stack_2_ctr = _RANDOM[7'h4][18:11]; + commit_stack_3_retAddr = {_RANDOM[7'h4][31:19], _RANDOM[7'h5][27:0]}; + commit_stack_3_ctr = {_RANDOM[7'h5][31:28], _RANDOM[7'h6][3:0]}; + commit_stack_4_retAddr = {_RANDOM[7'h6][31:4], _RANDOM[7'h7][12:0]}; + commit_stack_4_ctr = _RANDOM[7'h7][20:13]; + commit_stack_5_retAddr = {_RANDOM[7'h7][31:21], _RANDOM[7'h8][29:0]}; + commit_stack_5_ctr = {_RANDOM[7'h8][31:30], _RANDOM[7'h9][5:0]}; + commit_stack_6_retAddr = {_RANDOM[7'h9][31:6], _RANDOM[7'hA][14:0]}; + commit_stack_6_ctr = _RANDOM[7'hA][22:15]; + commit_stack_7_retAddr = {_RANDOM[7'hA][31:23], _RANDOM[7'hB]}; + commit_stack_7_ctr = _RANDOM[7'hC][7:0]; + commit_stack_8_retAddr = {_RANDOM[7'hC][31:8], _RANDOM[7'hD][16:0]}; + commit_stack_8_ctr = _RANDOM[7'hD][24:17]; + commit_stack_9_retAddr = + {_RANDOM[7'hD][31:25], _RANDOM[7'hE], _RANDOM[7'hF][1:0]}; + commit_stack_9_ctr = _RANDOM[7'hF][9:2]; + commit_stack_10_retAddr = {_RANDOM[7'hF][31:10], _RANDOM[7'h10][18:0]}; + commit_stack_10_ctr = _RANDOM[7'h10][26:19]; + commit_stack_11_retAddr = + {_RANDOM[7'h10][31:27], _RANDOM[7'h11], _RANDOM[7'h12][3:0]}; + commit_stack_11_ctr = _RANDOM[7'h12][11:4]; + commit_stack_12_retAddr = {_RANDOM[7'h12][31:12], _RANDOM[7'h13][20:0]}; + commit_stack_12_ctr = _RANDOM[7'h13][28:21]; + commit_stack_13_retAddr = + {_RANDOM[7'h13][31:29], _RANDOM[7'h14], _RANDOM[7'h15][5:0]}; + commit_stack_13_ctr = _RANDOM[7'h15][13:6]; + commit_stack_14_retAddr = {_RANDOM[7'h15][31:14], _RANDOM[7'h16][22:0]}; + commit_stack_14_ctr = _RANDOM[7'h16][30:23]; + commit_stack_15_retAddr = + {_RANDOM[7'h16][31], _RANDOM[7'h17], _RANDOM[7'h18][7:0]}; + commit_stack_15_ctr = _RANDOM[7'h18][15:8]; + spec_queue_0_retAddr = {_RANDOM[7'h18][31:16], _RANDOM[7'h19][24:0]}; + spec_queue_0_ctr = {_RANDOM[7'h19][31:25], _RANDOM[7'h1A][0]}; + spec_queue_1_retAddr = {_RANDOM[7'h1A][31:1], _RANDOM[7'h1B][9:0]}; + spec_queue_1_ctr = _RANDOM[7'h1B][17:10]; + spec_queue_2_retAddr = {_RANDOM[7'h1B][31:18], _RANDOM[7'h1C][26:0]}; + spec_queue_2_ctr = {_RANDOM[7'h1C][31:27], _RANDOM[7'h1D][2:0]}; + spec_queue_3_retAddr = {_RANDOM[7'h1D][31:3], _RANDOM[7'h1E][11:0]}; + spec_queue_3_ctr = _RANDOM[7'h1E][19:12]; + spec_queue_4_retAddr = {_RANDOM[7'h1E][31:20], _RANDOM[7'h1F][28:0]}; + spec_queue_4_ctr = {_RANDOM[7'h1F][31:29], _RANDOM[7'h20][4:0]}; + spec_queue_5_retAddr = {_RANDOM[7'h20][31:5], _RANDOM[7'h21][13:0]}; + spec_queue_5_ctr = _RANDOM[7'h21][21:14]; + spec_queue_6_retAddr = {_RANDOM[7'h21][31:22], _RANDOM[7'h22][30:0]}; + spec_queue_6_ctr = {_RANDOM[7'h22][31], _RANDOM[7'h23][6:0]}; + spec_queue_7_retAddr = {_RANDOM[7'h23][31:7], _RANDOM[7'h24][15:0]}; + spec_queue_7_ctr = _RANDOM[7'h24][23:16]; + spec_queue_8_retAddr = {_RANDOM[7'h24][31:24], _RANDOM[7'h25], _RANDOM[7'h26][0]}; + spec_queue_8_ctr = _RANDOM[7'h26][8:1]; + spec_queue_9_retAddr = {_RANDOM[7'h26][31:9], _RANDOM[7'h27][17:0]}; + spec_queue_9_ctr = _RANDOM[7'h27][25:18]; + spec_queue_10_retAddr = + {_RANDOM[7'h27][31:26], _RANDOM[7'h28], _RANDOM[7'h29][2:0]}; + spec_queue_10_ctr = _RANDOM[7'h29][10:3]; + spec_queue_11_retAddr = {_RANDOM[7'h29][31:11], _RANDOM[7'h2A][19:0]}; + spec_queue_11_ctr = _RANDOM[7'h2A][27:20]; + spec_queue_12_retAddr = + {_RANDOM[7'h2A][31:28], _RANDOM[7'h2B], _RANDOM[7'h2C][4:0]}; + spec_queue_12_ctr = _RANDOM[7'h2C][12:5]; + spec_queue_13_retAddr = {_RANDOM[7'h2C][31:13], _RANDOM[7'h2D][21:0]}; + spec_queue_13_ctr = _RANDOM[7'h2D][29:22]; + spec_queue_14_retAddr = + {_RANDOM[7'h2D][31:30], _RANDOM[7'h2E], _RANDOM[7'h2F][6:0]}; + spec_queue_14_ctr = _RANDOM[7'h2F][14:7]; + spec_queue_15_retAddr = {_RANDOM[7'h2F][31:15], _RANDOM[7'h30][23:0]}; + spec_queue_15_ctr = _RANDOM[7'h30][31:24]; + spec_queue_16_retAddr = {_RANDOM[7'h31], _RANDOM[7'h32][8:0]}; + spec_queue_16_ctr = _RANDOM[7'h32][16:9]; + spec_queue_17_retAddr = {_RANDOM[7'h32][31:17], _RANDOM[7'h33][25:0]}; + spec_queue_17_ctr = {_RANDOM[7'h33][31:26], _RANDOM[7'h34][1:0]}; + spec_queue_18_retAddr = {_RANDOM[7'h34][31:2], _RANDOM[7'h35][10:0]}; + spec_queue_18_ctr = _RANDOM[7'h35][18:11]; + spec_queue_19_retAddr = {_RANDOM[7'h35][31:19], _RANDOM[7'h36][27:0]}; + spec_queue_19_ctr = {_RANDOM[7'h36][31:28], _RANDOM[7'h37][3:0]}; + spec_queue_20_retAddr = {_RANDOM[7'h37][31:4], _RANDOM[7'h38][12:0]}; + spec_queue_20_ctr = _RANDOM[7'h38][20:13]; + spec_queue_21_retAddr = {_RANDOM[7'h38][31:21], _RANDOM[7'h39][29:0]}; + spec_queue_21_ctr = {_RANDOM[7'h39][31:30], _RANDOM[7'h3A][5:0]}; + spec_queue_22_retAddr = {_RANDOM[7'h3A][31:6], _RANDOM[7'h3B][14:0]}; + spec_queue_22_ctr = _RANDOM[7'h3B][22:15]; + spec_queue_23_retAddr = {_RANDOM[7'h3B][31:23], _RANDOM[7'h3C]}; + spec_queue_23_ctr = _RANDOM[7'h3D][7:0]; + spec_queue_24_retAddr = {_RANDOM[7'h3D][31:8], _RANDOM[7'h3E][16:0]}; + spec_queue_24_ctr = _RANDOM[7'h3E][24:17]; + spec_queue_25_retAddr = + {_RANDOM[7'h3E][31:25], _RANDOM[7'h3F], _RANDOM[7'h40][1:0]}; + spec_queue_25_ctr = _RANDOM[7'h40][9:2]; + spec_queue_26_retAddr = {_RANDOM[7'h40][31:10], _RANDOM[7'h41][18:0]}; + spec_queue_26_ctr = _RANDOM[7'h41][26:19]; + spec_queue_27_retAddr = + {_RANDOM[7'h41][31:27], _RANDOM[7'h42], _RANDOM[7'h43][3:0]}; + spec_queue_27_ctr = _RANDOM[7'h43][11:4]; + spec_queue_28_retAddr = {_RANDOM[7'h43][31:12], _RANDOM[7'h44][20:0]}; + spec_queue_28_ctr = _RANDOM[7'h44][28:21]; + spec_queue_29_retAddr = + {_RANDOM[7'h44][31:29], _RANDOM[7'h45], _RANDOM[7'h46][5:0]}; + spec_queue_29_ctr = _RANDOM[7'h46][13:6]; + spec_queue_30_retAddr = {_RANDOM[7'h46][31:14], _RANDOM[7'h47][22:0]}; + spec_queue_30_ctr = _RANDOM[7'h47][30:23]; + spec_queue_31_retAddr = {_RANDOM[7'h47][31], _RANDOM[7'h48], _RANDOM[7'h49][7:0]}; + spec_queue_31_ctr = _RANDOM[7'h49][15:8]; + spec_nos_0_flag = _RANDOM[7'h49][16]; + spec_nos_0_value = _RANDOM[7'h49][21:17]; + spec_nos_1_flag = _RANDOM[7'h49][22]; + spec_nos_1_value = _RANDOM[7'h49][27:23]; + spec_nos_2_flag = _RANDOM[7'h49][28]; + spec_nos_2_value = {_RANDOM[7'h49][31:29], _RANDOM[7'h4A][1:0]}; + spec_nos_3_flag = _RANDOM[7'h4A][2]; + spec_nos_3_value = _RANDOM[7'h4A][7:3]; + spec_nos_4_flag = _RANDOM[7'h4A][8]; + spec_nos_4_value = _RANDOM[7'h4A][13:9]; + spec_nos_5_flag = _RANDOM[7'h4A][14]; + spec_nos_5_value = _RANDOM[7'h4A][19:15]; + spec_nos_6_flag = _RANDOM[7'h4A][20]; + spec_nos_6_value = _RANDOM[7'h4A][25:21]; + spec_nos_7_flag = _RANDOM[7'h4A][26]; + spec_nos_7_value = _RANDOM[7'h4A][31:27]; + spec_nos_8_flag = _RANDOM[7'h4B][0]; + spec_nos_8_value = _RANDOM[7'h4B][5:1]; + spec_nos_9_flag = _RANDOM[7'h4B][6]; + spec_nos_9_value = _RANDOM[7'h4B][11:7]; + spec_nos_10_flag = _RANDOM[7'h4B][12]; + spec_nos_10_value = _RANDOM[7'h4B][17:13]; + spec_nos_11_flag = _RANDOM[7'h4B][18]; + spec_nos_11_value = _RANDOM[7'h4B][23:19]; + spec_nos_12_flag = _RANDOM[7'h4B][24]; + spec_nos_12_value = _RANDOM[7'h4B][29:25]; + spec_nos_13_flag = _RANDOM[7'h4B][30]; + spec_nos_13_value = {_RANDOM[7'h4B][31], _RANDOM[7'h4C][3:0]}; + spec_nos_14_flag = _RANDOM[7'h4C][4]; + spec_nos_14_value = _RANDOM[7'h4C][9:5]; + spec_nos_15_flag = _RANDOM[7'h4C][10]; + spec_nos_15_value = _RANDOM[7'h4C][15:11]; + spec_nos_16_flag = _RANDOM[7'h4C][16]; + spec_nos_16_value = _RANDOM[7'h4C][21:17]; + spec_nos_17_flag = _RANDOM[7'h4C][22]; + spec_nos_17_value = _RANDOM[7'h4C][27:23]; + spec_nos_18_flag = _RANDOM[7'h4C][28]; + spec_nos_18_value = {_RANDOM[7'h4C][31:29], _RANDOM[7'h4D][1:0]}; + spec_nos_19_flag = _RANDOM[7'h4D][2]; + spec_nos_19_value = _RANDOM[7'h4D][7:3]; + spec_nos_20_flag = _RANDOM[7'h4D][8]; + spec_nos_20_value = _RANDOM[7'h4D][13:9]; + spec_nos_21_flag = _RANDOM[7'h4D][14]; + spec_nos_21_value = _RANDOM[7'h4D][19:15]; + spec_nos_22_flag = _RANDOM[7'h4D][20]; + spec_nos_22_value = _RANDOM[7'h4D][25:21]; + spec_nos_23_flag = _RANDOM[7'h4D][26]; + spec_nos_23_value = _RANDOM[7'h4D][31:27]; + spec_nos_24_flag = _RANDOM[7'h4E][0]; + spec_nos_24_value = _RANDOM[7'h4E][5:1]; + spec_nos_25_flag = _RANDOM[7'h4E][6]; + spec_nos_25_value = _RANDOM[7'h4E][11:7]; + spec_nos_26_flag = _RANDOM[7'h4E][12]; + spec_nos_26_value = _RANDOM[7'h4E][17:13]; + spec_nos_27_flag = _RANDOM[7'h4E][18]; + spec_nos_27_value = _RANDOM[7'h4E][23:19]; + spec_nos_28_flag = _RANDOM[7'h4E][24]; + spec_nos_28_value = _RANDOM[7'h4E][29:25]; + spec_nos_29_flag = _RANDOM[7'h4E][30]; + spec_nos_29_value = {_RANDOM[7'h4E][31], _RANDOM[7'h4F][3:0]}; + spec_nos_30_flag = _RANDOM[7'h4F][4]; + spec_nos_30_value = _RANDOM[7'h4F][9:5]; + spec_nos_31_flag = _RANDOM[7'h4F][10]; + spec_nos_31_value = _RANDOM[7'h4F][15:11]; + nsp = _RANDOM[7'h4F][19:16]; + ssp = _RANDOM[7'h4F][23:20]; + sctr = _RANDOM[7'h4F][26:24]; + TOSR_flag = _RANDOM[7'h4F][27]; + TOSR_value = {_RANDOM[7'h4F][31:28], _RANDOM[7'h50][0]}; + TOSW_flag = _RANDOM[7'h50][1]; + TOSW_value = _RANDOM[7'h50][6:2]; + BOS_flag = _RANDOM[7'h50][7]; + BOS_value = _RANDOM[7'h50][12:8]; + spec_overflowed = _RANDOM[7'h50][13]; + writeBypassEntry_retAddr = {_RANDOM[7'h50][31:14], _RANDOM[7'h51][22:0]}; + writeBypassEntry_ctr = _RANDOM[7'h51][30:23]; + writeBypassNos_flag = _RANDOM[7'h51][31]; + writeBypassNos_value = _RANDOM[7'h52][4:0]; + writeBypassValid = _RANDOM[7'h52][5]; + timingTop_retAddr = {_RANDOM[7'h52][31:6], _RANDOM[7'h53][14:0]}; + realWriteEntry_next_retAddr = + {_RANDOM[7'h53][31:29], _RANDOM[7'h54], _RANDOM[7'h55][5:0]}; + realWriteEntry_next_ctr = _RANDOM[7'h55][13:6]; + realWriteAddr_next_value = _RANDOM[7'h55][19:15]; + realNos_next_flag = _RANDOM[7'h55][20]; + realNos_next_value = _RANDOM[7'h55][25:21]; + realPush_r = _RANDOM[7'h55][26]; + realPush_REG = _RANDOM[7'h55][27]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + commit_stack_0_retAddr = 41'h0; + commit_stack_0_ctr = 8'h0; + commit_stack_1_retAddr = 41'h0; + commit_stack_1_ctr = 8'h0; + commit_stack_2_retAddr = 41'h0; + commit_stack_2_ctr = 8'h0; + commit_stack_3_retAddr = 41'h0; + commit_stack_3_ctr = 8'h0; + commit_stack_4_retAddr = 41'h0; + commit_stack_4_ctr = 8'h0; + commit_stack_5_retAddr = 41'h0; + commit_stack_5_ctr = 8'h0; + commit_stack_6_retAddr = 41'h0; + commit_stack_6_ctr = 8'h0; + commit_stack_7_retAddr = 41'h0; + commit_stack_7_ctr = 8'h0; + commit_stack_8_retAddr = 41'h0; + commit_stack_8_ctr = 8'h0; + commit_stack_9_retAddr = 41'h0; + commit_stack_9_ctr = 8'h0; + commit_stack_10_retAddr = 41'h0; + commit_stack_10_ctr = 8'h0; + commit_stack_11_retAddr = 41'h0; + commit_stack_11_ctr = 8'h0; + commit_stack_12_retAddr = 41'h0; + commit_stack_12_ctr = 8'h0; + commit_stack_13_retAddr = 41'h0; + commit_stack_13_ctr = 8'h0; + commit_stack_14_retAddr = 41'h0; + commit_stack_14_ctr = 8'h0; + commit_stack_15_retAddr = 41'h0; + commit_stack_15_ctr = 8'h0; + spec_queue_0_retAddr = 41'h0; + spec_queue_0_ctr = 8'h0; + spec_queue_1_retAddr = 41'h0; + spec_queue_1_ctr = 8'h0; + spec_queue_2_retAddr = 41'h0; + spec_queue_2_ctr = 8'h0; + spec_queue_3_retAddr = 41'h0; + spec_queue_3_ctr = 8'h0; + spec_queue_4_retAddr = 41'h0; + spec_queue_4_ctr = 8'h0; + spec_queue_5_retAddr = 41'h0; + spec_queue_5_ctr = 8'h0; + spec_queue_6_retAddr = 41'h0; + spec_queue_6_ctr = 8'h0; + spec_queue_7_retAddr = 41'h0; + spec_queue_7_ctr = 8'h0; + spec_queue_8_retAddr = 41'h0; + spec_queue_8_ctr = 8'h0; + spec_queue_9_retAddr = 41'h0; + spec_queue_9_ctr = 8'h0; + spec_queue_10_retAddr = 41'h0; + spec_queue_10_ctr = 8'h0; + spec_queue_11_retAddr = 41'h0; + spec_queue_11_ctr = 8'h0; + spec_queue_12_retAddr = 41'h0; + spec_queue_12_ctr = 8'h0; + spec_queue_13_retAddr = 41'h0; + spec_queue_13_ctr = 8'h0; + spec_queue_14_retAddr = 41'h0; + spec_queue_14_ctr = 8'h0; + spec_queue_15_retAddr = 41'h0; + spec_queue_15_ctr = 8'h0; + spec_queue_16_retAddr = 41'h0; + spec_queue_16_ctr = 8'h0; + spec_queue_17_retAddr = 41'h0; + spec_queue_17_ctr = 8'h0; + spec_queue_18_retAddr = 41'h0; + spec_queue_18_ctr = 8'h0; + spec_queue_19_retAddr = 41'h0; + spec_queue_19_ctr = 8'h0; + spec_queue_20_retAddr = 41'h0; + spec_queue_20_ctr = 8'h0; + spec_queue_21_retAddr = 41'h0; + spec_queue_21_ctr = 8'h0; + spec_queue_22_retAddr = 41'h0; + spec_queue_22_ctr = 8'h0; + spec_queue_23_retAddr = 41'h0; + spec_queue_23_ctr = 8'h0; + spec_queue_24_retAddr = 41'h0; + spec_queue_24_ctr = 8'h0; + spec_queue_25_retAddr = 41'h0; + spec_queue_25_ctr = 8'h0; + spec_queue_26_retAddr = 41'h0; + spec_queue_26_ctr = 8'h0; + spec_queue_27_retAddr = 41'h0; + spec_queue_27_ctr = 8'h0; + spec_queue_28_retAddr = 41'h0; + spec_queue_28_ctr = 8'h0; + spec_queue_29_retAddr = 41'h0; + spec_queue_29_ctr = 8'h0; + spec_queue_30_retAddr = 41'h0; + spec_queue_30_ctr = 8'h0; + spec_queue_31_retAddr = 41'h0; + spec_queue_31_ctr = 8'h0; + spec_nos_0_flag = 1'h0; + spec_nos_0_value = 5'h0; + spec_nos_1_flag = 1'h0; + spec_nos_1_value = 5'h0; + spec_nos_2_flag = 1'h0; + spec_nos_2_value = 5'h0; + spec_nos_3_flag = 1'h0; + spec_nos_3_value = 5'h0; + spec_nos_4_flag = 1'h0; + spec_nos_4_value = 5'h0; + spec_nos_5_flag = 1'h0; + spec_nos_5_value = 5'h0; + spec_nos_6_flag = 1'h0; + spec_nos_6_value = 5'h0; + spec_nos_7_flag = 1'h0; + spec_nos_7_value = 5'h0; + spec_nos_8_flag = 1'h0; + spec_nos_8_value = 5'h0; + spec_nos_9_flag = 1'h0; + spec_nos_9_value = 5'h0; + spec_nos_10_flag = 1'h0; + spec_nos_10_value = 5'h0; + spec_nos_11_flag = 1'h0; + spec_nos_11_value = 5'h0; + spec_nos_12_flag = 1'h0; + spec_nos_12_value = 5'h0; + spec_nos_13_flag = 1'h0; + spec_nos_13_value = 5'h0; + spec_nos_14_flag = 1'h0; + spec_nos_14_value = 5'h0; + spec_nos_15_flag = 1'h0; + spec_nos_15_value = 5'h0; + spec_nos_16_flag = 1'h0; + spec_nos_16_value = 5'h0; + spec_nos_17_flag = 1'h0; + spec_nos_17_value = 5'h0; + spec_nos_18_flag = 1'h0; + spec_nos_18_value = 5'h0; + spec_nos_19_flag = 1'h0; + spec_nos_19_value = 5'h0; + spec_nos_20_flag = 1'h0; + spec_nos_20_value = 5'h0; + spec_nos_21_flag = 1'h0; + spec_nos_21_value = 5'h0; + spec_nos_22_flag = 1'h0; + spec_nos_22_value = 5'h0; + spec_nos_23_flag = 1'h0; + spec_nos_23_value = 5'h0; + spec_nos_24_flag = 1'h0; + spec_nos_24_value = 5'h0; + spec_nos_25_flag = 1'h0; + spec_nos_25_value = 5'h0; + spec_nos_26_flag = 1'h0; + spec_nos_26_value = 5'h0; + spec_nos_27_flag = 1'h0; + spec_nos_27_value = 5'h0; + spec_nos_28_flag = 1'h0; + spec_nos_28_value = 5'h0; + spec_nos_29_flag = 1'h0; + spec_nos_29_value = 5'h0; + spec_nos_30_flag = 1'h0; + spec_nos_30_value = 5'h0; + spec_nos_31_flag = 1'h0; + spec_nos_31_value = 5'h0; + nsp = 4'h0; + ssp = 4'h0; + sctr = 3'h0; + TOSR_flag = 1'h1; + TOSR_value = 5'h1F; + TOSW_flag = 1'h0; + TOSW_value = 5'h0; + BOS_flag = 1'h0; + BOS_value = 5'h0; + spec_overflowed = 1'h0; + writeBypassValid = 1'h0; + timingTop_retAddr = 41'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_spec_pop_addr = timingTop_retAddr; + assign io_ssp = ssp; + assign io_sctr = sctr; + assign io_TOSR_flag = TOSR_flag; + assign io_TOSR_value = TOSR_value; + assign io_TOSW_flag = TOSW_flag; + assign io_TOSW_value = TOSW_value; + assign io_NOS_flag = topNos_flag; + assign io_NOS_value = topNos_value; +endmodule + diff --git a/rtl/BPUTop/SCTable.sv b/rtl/BPUTop/SCTable.sv new file mode 100644 index 0000000..b02a717 --- /dev/null +++ b/rtl/BPUTop/SCTable.sv @@ -0,0 +1,244 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SCTable( + input clock, + input reset, + input io_req_valid, + input [40:0] io_req_bits_pc, + output [5:0] io_resp_ctrs_0_0, + output [5:0] io_resp_ctrs_0_1, + output [5:0] io_resp_ctrs_1_0, + output [5:0] io_resp_ctrs_1_1, + input [40:0] io_update_pc, + input io_update_mask_0, + input io_update_mask_1, + input [5:0] io_update_oldCtrs_0, + input [5:0] io_update_oldCtrs_1, + input io_update_tagePreds_0, + input io_update_tagePreds_1, + input io_update_takens_0, + input io_update_takens_1 +); + + wire _wrbypasses_1_io_hit; + wire _wrbypasses_1_io_hit_data_0_valid; + wire [5:0] _wrbypasses_1_io_hit_data_0_bits; + wire _wrbypasses_1_io_hit_data_1_valid; + wire [5:0] _wrbypasses_1_io_hit_data_1_bits; + wire _wrbypasses_0_io_hit; + wire _wrbypasses_0_io_hit_data_0_valid; + wire [5:0] _wrbypasses_0_io_hit_data_0_bits; + wire _wrbypasses_0_io_hit_data_1_valid; + wire [5:0] _wrbypasses_0_io_hit_data_1_bits; + wire [5:0] _table_io_r_resp_data_0; + wire [5:0] _table_io_r_resp_data_1; + wire [5:0] _table_io_r_resp_data_2; + wire [5:0] _table_io_r_resp_data_3; + reg [40:0] s1_pc; + wire updateWayMask_0 = + io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & ~io_update_tagePreds_1; + wire updateWayMask_1 = + io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & io_update_tagePreds_1; + wire updateWayMask_2 = + io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & ~io_update_tagePreds_1; + wire updateWayMask_3 = + io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & io_update_tagePreds_1; + wire ctrPos = + ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; + wire [5:0] oldCtr = + (~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit) + & (ctrPos + ? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_1_valid + : ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos + ? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0) + : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0)) + : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0) + | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); + wire taken = + ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; + wire [5:0] update_wdata_0 = + oldCtr == 6'h1F & taken + ? 6'h1F + : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); + wire ctrPos_1 = + io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; + wire [5:0] oldCtr_1 = + (io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit) + & (ctrPos_1 + ? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_1_valid + : io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos_1 + ? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits) + : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits)) + : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0) + | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); + wire taken_1 = + io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; + wire [5:0] update_wdata_1 = + oldCtr_1 == 6'h1F & taken_1 + ? 6'h1F + : oldCtr_1 == 6'h20 & ~taken_1 + ? 6'h20 + : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); + wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0; + wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0; + wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0; + wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1; + always @(posedge clock) begin + if (io_req_valid) + s1_pc <= io_req_bits_pc; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; + end + s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]}; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_35 table_0 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid), + .io_r_req_bits_setIdx (io_req_bits_pc[8:1]), + .io_r_resp_data_0 (_table_io_r_resp_data_0), + .io_r_resp_data_1 (_table_io_r_resp_data_1), + .io_r_resp_data_2 (_table_io_r_resp_data_2), + .io_r_resp_data_3 (_table_io_r_resp_data_3), + .io_w_req_valid (io_update_mask_0 | io_update_mask_1), + .io_w_req_bits_setIdx (io_update_pc[8:1]), + .io_w_req_bits_data_0 (update_wdata_0), + .io_w_req_bits_data_1 (update_wdata_0), + .io_w_req_bits_data_2 (update_wdata_1), + .io_w_req_bits_data_3 (update_wdata_1), + .io_w_req_bits_waymask + ({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0}) + ); + WrBypass_33 wrbypasses_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0), + .io_write_idx (io_update_pc[8:1]), + .io_write_data_0 (_GEN | _GEN_0), + .io_write_data_1 (_GEN | _GEN_0), + .io_write_way_mask_0 + (~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2), + .io_write_way_mask_1 + (~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3), + .io_hit (_wrbypasses_0_io_hit), + .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits) + ); + WrBypass_33 wrbypasses_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1), + .io_write_idx (io_update_pc[8:1]), + .io_write_data_0 (_GEN_1 | _GEN_2), + .io_write_data_1 (_GEN_1 | _GEN_2), + .io_write_way_mask_0 + (io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2), + .io_write_way_mask_1 + (io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3), + .io_hit (_wrbypasses_1_io_hit), + .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits) + ); + assign io_resp_ctrs_0_0 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0) + | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); + assign io_resp_ctrs_0_1 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1) + | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); + assign io_resp_ctrs_1_0 = + (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); + assign io_resp_ctrs_1_1 = + (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); +endmodule + diff --git a/rtl/BPUTop/SCTable_1.sv b/rtl/BPUTop/SCTable_1.sv new file mode 100644 index 0000000..00fbfb4 --- /dev/null +++ b/rtl/BPUTop/SCTable_1.sv @@ -0,0 +1,250 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SCTable_1( + input clock, + input reset, + input io_req_valid, + input [40:0] io_req_bits_pc, + input [3:0] io_req_bits_folded_hist_hist_12_folded_hist, + output [5:0] io_resp_ctrs_0_0, + output [5:0] io_resp_ctrs_0_1, + output [5:0] io_resp_ctrs_1_0, + output [5:0] io_resp_ctrs_1_1, + input [40:0] io_update_pc, + input [3:0] io_update_folded_hist_hist_12_folded_hist, + input io_update_mask_0, + input io_update_mask_1, + input [5:0] io_update_oldCtrs_0, + input [5:0] io_update_oldCtrs_1, + input io_update_tagePreds_0, + input io_update_tagePreds_1, + input io_update_takens_0, + input io_update_takens_1 +); + + wire _wrbypasses_1_io_hit; + wire _wrbypasses_1_io_hit_data_0_valid; + wire [5:0] _wrbypasses_1_io_hit_data_0_bits; + wire _wrbypasses_1_io_hit_data_1_valid; + wire [5:0] _wrbypasses_1_io_hit_data_1_bits; + wire _wrbypasses_0_io_hit; + wire _wrbypasses_0_io_hit_data_0_valid; + wire [5:0] _wrbypasses_0_io_hit_data_0_bits; + wire _wrbypasses_0_io_hit_data_1_valid; + wire [5:0] _wrbypasses_0_io_hit_data_1_bits; + wire [5:0] _table_io_r_resp_data_0; + wire [5:0] _table_io_r_resp_data_1; + wire [5:0] _table_io_r_resp_data_2; + wire [5:0] _table_io_r_resp_data_3; + reg [40:0] s1_pc; + wire updateWayMask_0 = + io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & ~io_update_tagePreds_1; + wire updateWayMask_1 = + io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & io_update_tagePreds_1; + wire updateWayMask_2 = + io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & ~io_update_tagePreds_1; + wire updateWayMask_3 = + io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & io_update_tagePreds_1; + wire [7:0] update_idx = + {io_update_pc[8:5], io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist}; + wire ctrPos = + ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; + wire [5:0] oldCtr = + (~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit) + & (ctrPos + ? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_1_valid + : ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos + ? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0) + : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0)) + : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0) + | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); + wire taken = + ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; + wire [5:0] update_wdata_0 = + oldCtr == 6'h1F & taken + ? 6'h1F + : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); + wire ctrPos_1 = + io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; + wire [5:0] oldCtr_1 = + (io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit) + & (ctrPos_1 + ? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_1_valid + : io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos_1 + ? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits) + : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits)) + : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0) + | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); + wire taken_1 = + io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; + wire [5:0] update_wdata_1 = + oldCtr_1 == 6'h1F & taken_1 + ? 6'h1F + : oldCtr_1 == 6'h20 & ~taken_1 + ? 6'h20 + : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); + wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0; + wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0; + wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0; + wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1; + always @(posedge clock) begin + if (io_req_valid) + s1_pc <= io_req_bits_pc; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; + end + s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]}; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_35 table_0 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid), + .io_r_req_bits_setIdx + ({io_req_bits_pc[8:5], + io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist}), + .io_r_resp_data_0 (_table_io_r_resp_data_0), + .io_r_resp_data_1 (_table_io_r_resp_data_1), + .io_r_resp_data_2 (_table_io_r_resp_data_2), + .io_r_resp_data_3 (_table_io_r_resp_data_3), + .io_w_req_valid (io_update_mask_0 | io_update_mask_1), + .io_w_req_bits_setIdx (update_idx), + .io_w_req_bits_data_0 (update_wdata_0), + .io_w_req_bits_data_1 (update_wdata_0), + .io_w_req_bits_data_2 (update_wdata_1), + .io_w_req_bits_data_3 (update_wdata_1), + .io_w_req_bits_waymask + ({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0}) + ); + WrBypass_33 wrbypasses_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0), + .io_write_idx (update_idx), + .io_write_data_0 (_GEN | _GEN_0), + .io_write_data_1 (_GEN | _GEN_0), + .io_write_way_mask_0 + (~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2), + .io_write_way_mask_1 + (~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3), + .io_hit (_wrbypasses_0_io_hit), + .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits) + ); + WrBypass_33 wrbypasses_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1), + .io_write_idx (update_idx), + .io_write_data_0 (_GEN_1 | _GEN_2), + .io_write_data_1 (_GEN_1 | _GEN_2), + .io_write_way_mask_0 + (io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2), + .io_write_way_mask_1 + (io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3), + .io_hit (_wrbypasses_1_io_hit), + .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits) + ); + assign io_resp_ctrs_0_0 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0) + | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); + assign io_resp_ctrs_0_1 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1) + | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); + assign io_resp_ctrs_1_0 = + (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); + assign io_resp_ctrs_1_1 = + (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); +endmodule + diff --git a/rtl/BPUTop/SCTable_2.sv b/rtl/BPUTop/SCTable_2.sv new file mode 100644 index 0000000..48c47ae --- /dev/null +++ b/rtl/BPUTop/SCTable_2.sv @@ -0,0 +1,248 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SCTable_2( + input clock, + input reset, + input io_req_valid, + input [40:0] io_req_bits_pc, + input [7:0] io_req_bits_folded_hist_hist_11_folded_hist, + output [5:0] io_resp_ctrs_0_0, + output [5:0] io_resp_ctrs_0_1, + output [5:0] io_resp_ctrs_1_0, + output [5:0] io_resp_ctrs_1_1, + input [40:0] io_update_pc, + input [7:0] io_update_folded_hist_hist_11_folded_hist, + input io_update_mask_0, + input io_update_mask_1, + input [5:0] io_update_oldCtrs_0, + input [5:0] io_update_oldCtrs_1, + input io_update_tagePreds_0, + input io_update_tagePreds_1, + input io_update_takens_0, + input io_update_takens_1 +); + + wire _wrbypasses_1_io_hit; + wire _wrbypasses_1_io_hit_data_0_valid; + wire [5:0] _wrbypasses_1_io_hit_data_0_bits; + wire _wrbypasses_1_io_hit_data_1_valid; + wire [5:0] _wrbypasses_1_io_hit_data_1_bits; + wire _wrbypasses_0_io_hit; + wire _wrbypasses_0_io_hit_data_0_valid; + wire [5:0] _wrbypasses_0_io_hit_data_0_bits; + wire _wrbypasses_0_io_hit_data_1_valid; + wire [5:0] _wrbypasses_0_io_hit_data_1_bits; + wire [5:0] _table_io_r_resp_data_0; + wire [5:0] _table_io_r_resp_data_1; + wire [5:0] _table_io_r_resp_data_2; + wire [5:0] _table_io_r_resp_data_3; + reg [40:0] s1_pc; + wire updateWayMask_0 = + io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & ~io_update_tagePreds_1; + wire updateWayMask_1 = + io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & io_update_tagePreds_1; + wire updateWayMask_2 = + io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & ~io_update_tagePreds_1; + wire updateWayMask_3 = + io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & io_update_tagePreds_1; + wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_11_folded_hist; + wire ctrPos = + ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; + wire [5:0] oldCtr = + (~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit) + & (ctrPos + ? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_1_valid + : ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos + ? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0) + : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0)) + : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0) + | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); + wire taken = + ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; + wire [5:0] update_wdata_0 = + oldCtr == 6'h1F & taken + ? 6'h1F + : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); + wire ctrPos_1 = + io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; + wire [5:0] oldCtr_1 = + (io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit) + & (ctrPos_1 + ? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_1_valid + : io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos_1 + ? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits) + : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits)) + : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0) + | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); + wire taken_1 = + io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; + wire [5:0] update_wdata_1 = + oldCtr_1 == 6'h1F & taken_1 + ? 6'h1F + : oldCtr_1 == 6'h20 & ~taken_1 + ? 6'h20 + : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); + wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0; + wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0; + wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0; + wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1; + always @(posedge clock) begin + if (io_req_valid) + s1_pc <= io_req_bits_pc; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; + end + s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]}; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_35 table_0 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid), + .io_r_req_bits_setIdx + (io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_11_folded_hist), + .io_r_resp_data_0 (_table_io_r_resp_data_0), + .io_r_resp_data_1 (_table_io_r_resp_data_1), + .io_r_resp_data_2 (_table_io_r_resp_data_2), + .io_r_resp_data_3 (_table_io_r_resp_data_3), + .io_w_req_valid (io_update_mask_0 | io_update_mask_1), + .io_w_req_bits_setIdx (update_idx), + .io_w_req_bits_data_0 (update_wdata_0), + .io_w_req_bits_data_1 (update_wdata_0), + .io_w_req_bits_data_2 (update_wdata_1), + .io_w_req_bits_data_3 (update_wdata_1), + .io_w_req_bits_waymask + ({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0}) + ); + WrBypass_33 wrbypasses_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0), + .io_write_idx (update_idx), + .io_write_data_0 (_GEN | _GEN_0), + .io_write_data_1 (_GEN | _GEN_0), + .io_write_way_mask_0 + (~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2), + .io_write_way_mask_1 + (~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3), + .io_hit (_wrbypasses_0_io_hit), + .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits) + ); + WrBypass_33 wrbypasses_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1), + .io_write_idx (update_idx), + .io_write_data_0 (_GEN_1 | _GEN_2), + .io_write_data_1 (_GEN_1 | _GEN_2), + .io_write_way_mask_0 + (io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2), + .io_write_way_mask_1 + (io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3), + .io_hit (_wrbypasses_1_io_hit), + .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits) + ); + assign io_resp_ctrs_0_0 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0) + | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); + assign io_resp_ctrs_0_1 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1) + | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); + assign io_resp_ctrs_1_0 = + (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); + assign io_resp_ctrs_1_1 = + (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); +endmodule + diff --git a/rtl/BPUTop/SCTable_3.sv b/rtl/BPUTop/SCTable_3.sv new file mode 100644 index 0000000..362b220 --- /dev/null +++ b/rtl/BPUTop/SCTable_3.sv @@ -0,0 +1,248 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SCTable_3( + input clock, + input reset, + input io_req_valid, + input [40:0] io_req_bits_pc, + input [7:0] io_req_bits_folded_hist_hist_2_folded_hist, + output [5:0] io_resp_ctrs_0_0, + output [5:0] io_resp_ctrs_0_1, + output [5:0] io_resp_ctrs_1_0, + output [5:0] io_resp_ctrs_1_1, + input [40:0] io_update_pc, + input [7:0] io_update_folded_hist_hist_2_folded_hist, + input io_update_mask_0, + input io_update_mask_1, + input [5:0] io_update_oldCtrs_0, + input [5:0] io_update_oldCtrs_1, + input io_update_tagePreds_0, + input io_update_tagePreds_1, + input io_update_takens_0, + input io_update_takens_1 +); + + wire _wrbypasses_1_io_hit; + wire _wrbypasses_1_io_hit_data_0_valid; + wire [5:0] _wrbypasses_1_io_hit_data_0_bits; + wire _wrbypasses_1_io_hit_data_1_valid; + wire [5:0] _wrbypasses_1_io_hit_data_1_bits; + wire _wrbypasses_0_io_hit; + wire _wrbypasses_0_io_hit_data_0_valid; + wire [5:0] _wrbypasses_0_io_hit_data_0_bits; + wire _wrbypasses_0_io_hit_data_1_valid; + wire [5:0] _wrbypasses_0_io_hit_data_1_bits; + wire [5:0] _table_io_r_resp_data_0; + wire [5:0] _table_io_r_resp_data_1; + wire [5:0] _table_io_r_resp_data_2; + wire [5:0] _table_io_r_resp_data_3; + reg [40:0] s1_pc; + wire updateWayMask_0 = + io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & ~io_update_tagePreds_1; + wire updateWayMask_1 = + io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1 + & io_update_pc[1] & io_update_tagePreds_1; + wire updateWayMask_2 = + io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & ~io_update_tagePreds_1; + wire updateWayMask_3 = + io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1 + & ~(io_update_pc[1]) & io_update_tagePreds_1; + wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_2_folded_hist; + wire ctrPos = + ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1; + wire [5:0] oldCtr = + (~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit) + & (ctrPos + ? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_1_valid + : ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1] + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos + ? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0) + : (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0)) + : (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0) + | (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0); + wire taken = + ~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1; + wire [5:0] update_wdata_0 = + oldCtr == 6'h1F & taken + ? 6'h1F + : oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1); + wire ctrPos_1 = + io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1; + wire [5:0] oldCtr_1 = + (io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit) + & (ctrPos_1 + ? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_1_valid + : io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _wrbypasses_1_io_hit_data_0_valid) + ? (ctrPos_1 + ? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits) + : (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0) + | (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits)) + : (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0) + | (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1); + wire taken_1 = + io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1; + wire [5:0] update_wdata_1 = + oldCtr_1 == 6'h1F & taken_1 + ? 6'h1F + : oldCtr_1 == 6'h20 & ~taken_1 + ? 6'h20 + : taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1); + wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0; + wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0; + wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0; + wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1; + always @(posedge clock) begin + if (io_req_valid) + s1_pc <= io_req_bits_pc; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; + end + s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]}; + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + SRAMTemplate_35 table_0 ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid), + .io_r_req_bits_setIdx + (io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_2_folded_hist), + .io_r_resp_data_0 (_table_io_r_resp_data_0), + .io_r_resp_data_1 (_table_io_r_resp_data_1), + .io_r_resp_data_2 (_table_io_r_resp_data_2), + .io_r_resp_data_3 (_table_io_r_resp_data_3), + .io_w_req_valid (io_update_mask_0 | io_update_mask_1), + .io_w_req_bits_setIdx (update_idx), + .io_w_req_bits_data_0 (update_wdata_0), + .io_w_req_bits_data_1 (update_wdata_0), + .io_w_req_bits_data_2 (update_wdata_1), + .io_w_req_bits_data_3 (update_wdata_1), + .io_w_req_bits_waymask + ({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0}) + ); + WrBypass_33 wrbypasses_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0), + .io_write_idx (update_idx), + .io_write_data_0 (_GEN | _GEN_0), + .io_write_data_1 (_GEN | _GEN_0), + .io_write_way_mask_0 + (~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2), + .io_write_way_mask_1 + (~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3), + .io_hit (_wrbypasses_0_io_hit), + .io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits) + ); + WrBypass_33 wrbypasses_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1), + .io_write_idx (update_idx), + .io_write_data_0 (_GEN_1 | _GEN_2), + .io_write_data_1 (_GEN_1 | _GEN_2), + .io_write_way_mask_0 + (io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2), + .io_write_way_mask_1 + (io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3), + .io_hit (_wrbypasses_1_io_hit), + .io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits) + ); + assign io_resp_ctrs_0_0 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0) + | (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0); + assign io_resp_ctrs_0_1 = + (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1) + | (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0); + assign io_resp_ctrs_1_0 = + (s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2); + assign io_resp_ctrs_1_1 = + (s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0) + | (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3); +endmodule + diff --git a/rtl/BPUTop/SRAMTemplate_13.sv b/rtl/BPUTop/SRAMTemplate_13.sv new file mode 100644 index 0000000..4de5bbc --- /dev/null +++ b/rtl/BPUTop/SRAMTemplate_13.sv @@ -0,0 +1,443 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_13( + input clock, + input reset, + output io_r_req_ready, + input io_r_req_valid, + input [8:0] io_r_req_bits_setIdx, + output io_r_resp_data_0_entry_valid, + output [3:0] io_r_resp_data_0_entry_brSlots_0_offset, + output [11:0] io_r_resp_data_0_entry_brSlots_0_lower, + output [1:0] io_r_resp_data_0_entry_brSlots_0_tarStat, + output io_r_resp_data_0_entry_brSlots_0_sharing, + output io_r_resp_data_0_entry_brSlots_0_valid, + output [3:0] io_r_resp_data_0_entry_tailSlot_offset, + output [19:0] io_r_resp_data_0_entry_tailSlot_lower, + output [1:0] io_r_resp_data_0_entry_tailSlot_tarStat, + output io_r_resp_data_0_entry_tailSlot_sharing, + output io_r_resp_data_0_entry_tailSlot_valid, + output [3:0] io_r_resp_data_0_entry_pftAddr, + output io_r_resp_data_0_entry_carry, + output io_r_resp_data_0_entry_isCall, + output io_r_resp_data_0_entry_isRet, + output io_r_resp_data_0_entry_isJalr, + output io_r_resp_data_0_entry_last_may_be_rvi_call, + output io_r_resp_data_0_entry_always_taken_0, + output io_r_resp_data_0_entry_always_taken_1, + output [19:0] io_r_resp_data_0_tag, + output io_r_resp_data_1_entry_valid, + output [3:0] io_r_resp_data_1_entry_brSlots_0_offset, + output [11:0] io_r_resp_data_1_entry_brSlots_0_lower, + output [1:0] io_r_resp_data_1_entry_brSlots_0_tarStat, + output io_r_resp_data_1_entry_brSlots_0_sharing, + output io_r_resp_data_1_entry_brSlots_0_valid, + output [3:0] io_r_resp_data_1_entry_tailSlot_offset, + output [19:0] io_r_resp_data_1_entry_tailSlot_lower, + output [1:0] io_r_resp_data_1_entry_tailSlot_tarStat, + output io_r_resp_data_1_entry_tailSlot_sharing, + output io_r_resp_data_1_entry_tailSlot_valid, + output [3:0] io_r_resp_data_1_entry_pftAddr, + output io_r_resp_data_1_entry_carry, + output io_r_resp_data_1_entry_isCall, + output io_r_resp_data_1_entry_isRet, + output io_r_resp_data_1_entry_isJalr, + output io_r_resp_data_1_entry_last_may_be_rvi_call, + output io_r_resp_data_1_entry_always_taken_0, + output io_r_resp_data_1_entry_always_taken_1, + output [19:0] io_r_resp_data_1_tag, + output io_r_resp_data_2_entry_valid, + output [3:0] io_r_resp_data_2_entry_brSlots_0_offset, + output [11:0] io_r_resp_data_2_entry_brSlots_0_lower, + output [1:0] io_r_resp_data_2_entry_brSlots_0_tarStat, + output io_r_resp_data_2_entry_brSlots_0_sharing, + output io_r_resp_data_2_entry_brSlots_0_valid, + output [3:0] io_r_resp_data_2_entry_tailSlot_offset, + output [19:0] io_r_resp_data_2_entry_tailSlot_lower, + output [1:0] io_r_resp_data_2_entry_tailSlot_tarStat, + output io_r_resp_data_2_entry_tailSlot_sharing, + output io_r_resp_data_2_entry_tailSlot_valid, + output [3:0] io_r_resp_data_2_entry_pftAddr, + output io_r_resp_data_2_entry_carry, + output io_r_resp_data_2_entry_isCall, + output io_r_resp_data_2_entry_isRet, + output io_r_resp_data_2_entry_isJalr, + output io_r_resp_data_2_entry_last_may_be_rvi_call, + output io_r_resp_data_2_entry_always_taken_0, + output io_r_resp_data_2_entry_always_taken_1, + output [19:0] io_r_resp_data_2_tag, + output io_r_resp_data_3_entry_valid, + output [3:0] io_r_resp_data_3_entry_brSlots_0_offset, + output [11:0] io_r_resp_data_3_entry_brSlots_0_lower, + output [1:0] io_r_resp_data_3_entry_brSlots_0_tarStat, + output io_r_resp_data_3_entry_brSlots_0_sharing, + output io_r_resp_data_3_entry_brSlots_0_valid, + output [3:0] io_r_resp_data_3_entry_tailSlot_offset, + output [19:0] io_r_resp_data_3_entry_tailSlot_lower, + output [1:0] io_r_resp_data_3_entry_tailSlot_tarStat, + output io_r_resp_data_3_entry_tailSlot_sharing, + output io_r_resp_data_3_entry_tailSlot_valid, + output [3:0] io_r_resp_data_3_entry_pftAddr, + output io_r_resp_data_3_entry_carry, + output io_r_resp_data_3_entry_isCall, + output io_r_resp_data_3_entry_isRet, + output io_r_resp_data_3_entry_isJalr, + output io_r_resp_data_3_entry_last_may_be_rvi_call, + output io_r_resp_data_3_entry_always_taken_0, + output io_r_resp_data_3_entry_always_taken_1, + output [19:0] io_r_resp_data_3_tag, + input io_w_req_valid, + input [8:0] io_w_req_bits_setIdx, + input io_w_req_bits_data_0_entry_valid, + input [3:0] io_w_req_bits_data_0_entry_brSlots_0_offset, + input [11:0] io_w_req_bits_data_0_entry_brSlots_0_lower, + input [1:0] io_w_req_bits_data_0_entry_brSlots_0_tarStat, + input io_w_req_bits_data_0_entry_brSlots_0_sharing, + input io_w_req_bits_data_0_entry_brSlots_0_valid, + input [3:0] io_w_req_bits_data_0_entry_tailSlot_offset, + input [19:0] io_w_req_bits_data_0_entry_tailSlot_lower, + input [1:0] io_w_req_bits_data_0_entry_tailSlot_tarStat, + input io_w_req_bits_data_0_entry_tailSlot_sharing, + input io_w_req_bits_data_0_entry_tailSlot_valid, + input [3:0] io_w_req_bits_data_0_entry_pftAddr, + input io_w_req_bits_data_0_entry_carry, + input io_w_req_bits_data_0_entry_isCall, + input io_w_req_bits_data_0_entry_isRet, + input io_w_req_bits_data_0_entry_isJalr, + input io_w_req_bits_data_0_entry_last_may_be_rvi_call, + input io_w_req_bits_data_0_entry_always_taken_0, + input io_w_req_bits_data_0_entry_always_taken_1, + input [19:0] io_w_req_bits_data_0_tag, + input io_w_req_bits_data_1_entry_valid, + input [3:0] io_w_req_bits_data_1_entry_brSlots_0_offset, + input [11:0] io_w_req_bits_data_1_entry_brSlots_0_lower, + input [1:0] io_w_req_bits_data_1_entry_brSlots_0_tarStat, + input io_w_req_bits_data_1_entry_brSlots_0_sharing, + input io_w_req_bits_data_1_entry_brSlots_0_valid, + input [3:0] io_w_req_bits_data_1_entry_tailSlot_offset, + input [19:0] io_w_req_bits_data_1_entry_tailSlot_lower, + input [1:0] io_w_req_bits_data_1_entry_tailSlot_tarStat, + input io_w_req_bits_data_1_entry_tailSlot_sharing, + input io_w_req_bits_data_1_entry_tailSlot_valid, + input [3:0] io_w_req_bits_data_1_entry_pftAddr, + input io_w_req_bits_data_1_entry_carry, + input io_w_req_bits_data_1_entry_isCall, + input io_w_req_bits_data_1_entry_isRet, + input io_w_req_bits_data_1_entry_isJalr, + input io_w_req_bits_data_1_entry_last_may_be_rvi_call, + input io_w_req_bits_data_1_entry_always_taken_0, + input io_w_req_bits_data_1_entry_always_taken_1, + input [19:0] io_w_req_bits_data_1_tag, + input io_w_req_bits_data_2_entry_valid, + input [3:0] io_w_req_bits_data_2_entry_brSlots_0_offset, + input [11:0] io_w_req_bits_data_2_entry_brSlots_0_lower, + input [1:0] io_w_req_bits_data_2_entry_brSlots_0_tarStat, + input io_w_req_bits_data_2_entry_brSlots_0_sharing, + input io_w_req_bits_data_2_entry_brSlots_0_valid, + input [3:0] io_w_req_bits_data_2_entry_tailSlot_offset, + input [19:0] io_w_req_bits_data_2_entry_tailSlot_lower, + input [1:0] io_w_req_bits_data_2_entry_tailSlot_tarStat, + input io_w_req_bits_data_2_entry_tailSlot_sharing, + input io_w_req_bits_data_2_entry_tailSlot_valid, + input [3:0] io_w_req_bits_data_2_entry_pftAddr, + input io_w_req_bits_data_2_entry_carry, + input io_w_req_bits_data_2_entry_isCall, + input io_w_req_bits_data_2_entry_isRet, + input io_w_req_bits_data_2_entry_isJalr, + input io_w_req_bits_data_2_entry_last_may_be_rvi_call, + input io_w_req_bits_data_2_entry_always_taken_0, + input io_w_req_bits_data_2_entry_always_taken_1, + input [19:0] io_w_req_bits_data_2_tag, + input io_w_req_bits_data_3_entry_valid, + input [3:0] io_w_req_bits_data_3_entry_brSlots_0_offset, + input [11:0] io_w_req_bits_data_3_entry_brSlots_0_lower, + input [1:0] io_w_req_bits_data_3_entry_brSlots_0_tarStat, + input io_w_req_bits_data_3_entry_brSlots_0_sharing, + input io_w_req_bits_data_3_entry_brSlots_0_valid, + input [3:0] io_w_req_bits_data_3_entry_tailSlot_offset, + input [19:0] io_w_req_bits_data_3_entry_tailSlot_lower, + input [1:0] io_w_req_bits_data_3_entry_tailSlot_tarStat, + input io_w_req_bits_data_3_entry_tailSlot_sharing, + input io_w_req_bits_data_3_entry_tailSlot_valid, + input [3:0] io_w_req_bits_data_3_entry_pftAddr, + input io_w_req_bits_data_3_entry_carry, + input io_w_req_bits_data_3_entry_isCall, + input io_w_req_bits_data_3_entry_isRet, + input io_w_req_bits_data_3_entry_isJalr, + input io_w_req_bits_data_3_entry_last_may_be_rvi_call, + input io_w_req_bits_data_3_entry_always_taken_0, + input io_w_req_bits_data_3_entry_always_taken_1, + input [19:0] io_w_req_bits_data_3_tag, + input [3:0] io_w_req_bits_waymask +); + + wire [8:0] setIdx; + wire realRen; + wire wen; + wire [319:0] _array_RW0_rdata; + reg _resetState; + reg [8:0] _resetSet; + assign wen = io_w_req_valid | _resetState; + assign realRen = io_r_req_valid & ~wen; + assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx; + always @(posedge clock or posedge reset) begin + if (reset) begin + _resetState <= 1'h1; + _resetSet <= 9'h0; + end + else begin + _resetState <= ~(_resetState & (&_resetSet)) & _resetState; + if (_resetState) + _resetSet <= 9'(_resetSet + 9'h1); + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + _resetState = _RANDOM[/*Zero width*/ 1'b0][0]; + _resetSet = _RANDOM[/*Zero width*/ 1'b0][9:1]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + _resetState = 1'h1; + _resetSet = 9'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_3 array ( + .RW0_addr (wen ? setIdx : io_r_req_bits_setIdx), + .RW0_en (realRen | wen), + .RW0_clk (clock), + .RW0_wmode (wen), + .RW0_wdata + ({~_resetState & io_w_req_bits_data_3_entry_valid, + _resetState ? 4'h0 : io_w_req_bits_data_3_entry_brSlots_0_offset, + _resetState ? 12'h0 : io_w_req_bits_data_3_entry_brSlots_0_lower, + _resetState ? 2'h0 : io_w_req_bits_data_3_entry_brSlots_0_tarStat, + ~_resetState & io_w_req_bits_data_3_entry_brSlots_0_sharing, + ~_resetState & io_w_req_bits_data_3_entry_brSlots_0_valid, + _resetState ? 4'h0 : io_w_req_bits_data_3_entry_tailSlot_offset, + _resetState ? 20'h0 : io_w_req_bits_data_3_entry_tailSlot_lower, + _resetState ? 2'h0 : io_w_req_bits_data_3_entry_tailSlot_tarStat, + ~_resetState & io_w_req_bits_data_3_entry_tailSlot_sharing, + ~_resetState & io_w_req_bits_data_3_entry_tailSlot_valid, + _resetState ? 4'h0 : io_w_req_bits_data_3_entry_pftAddr, + ~_resetState & io_w_req_bits_data_3_entry_carry, + ~_resetState & io_w_req_bits_data_3_entry_isCall, + ~_resetState & io_w_req_bits_data_3_entry_isRet, + ~_resetState & io_w_req_bits_data_3_entry_isJalr, + ~_resetState & io_w_req_bits_data_3_entry_last_may_be_rvi_call, + ~_resetState & io_w_req_bits_data_3_entry_always_taken_1, + ~_resetState & io_w_req_bits_data_3_entry_always_taken_0, + _resetState ? 20'h0 : io_w_req_bits_data_3_tag, + ~_resetState & io_w_req_bits_data_2_entry_valid, + _resetState ? 4'h0 : io_w_req_bits_data_2_entry_brSlots_0_offset, + _resetState ? 12'h0 : io_w_req_bits_data_2_entry_brSlots_0_lower, + _resetState ? 2'h0 : io_w_req_bits_data_2_entry_brSlots_0_tarStat, + ~_resetState & io_w_req_bits_data_2_entry_brSlots_0_sharing, + ~_resetState & io_w_req_bits_data_2_entry_brSlots_0_valid, + _resetState ? 4'h0 : io_w_req_bits_data_2_entry_tailSlot_offset, + _resetState ? 20'h0 : io_w_req_bits_data_2_entry_tailSlot_lower, + _resetState ? 2'h0 : io_w_req_bits_data_2_entry_tailSlot_tarStat, + ~_resetState & io_w_req_bits_data_2_entry_tailSlot_sharing, + ~_resetState & io_w_req_bits_data_2_entry_tailSlot_valid, + _resetState ? 4'h0 : io_w_req_bits_data_2_entry_pftAddr, + ~_resetState & io_w_req_bits_data_2_entry_carry, + ~_resetState & io_w_req_bits_data_2_entry_isCall, + ~_resetState & io_w_req_bits_data_2_entry_isRet, + ~_resetState & io_w_req_bits_data_2_entry_isJalr, + ~_resetState & io_w_req_bits_data_2_entry_last_may_be_rvi_call, + ~_resetState & io_w_req_bits_data_2_entry_always_taken_1, + ~_resetState & io_w_req_bits_data_2_entry_always_taken_0, + _resetState ? 20'h0 : io_w_req_bits_data_2_tag, + ~_resetState & io_w_req_bits_data_1_entry_valid, + _resetState ? 4'h0 : io_w_req_bits_data_1_entry_brSlots_0_offset, + _resetState ? 12'h0 : io_w_req_bits_data_1_entry_brSlots_0_lower, + _resetState ? 2'h0 : io_w_req_bits_data_1_entry_brSlots_0_tarStat, + ~_resetState & io_w_req_bits_data_1_entry_brSlots_0_sharing, + ~_resetState & io_w_req_bits_data_1_entry_brSlots_0_valid, + _resetState ? 4'h0 : io_w_req_bits_data_1_entry_tailSlot_offset, + _resetState ? 20'h0 : io_w_req_bits_data_1_entry_tailSlot_lower, + _resetState ? 2'h0 : io_w_req_bits_data_1_entry_tailSlot_tarStat, + ~_resetState & io_w_req_bits_data_1_entry_tailSlot_sharing, + ~_resetState & io_w_req_bits_data_1_entry_tailSlot_valid, + _resetState ? 4'h0 : io_w_req_bits_data_1_entry_pftAddr, + ~_resetState & io_w_req_bits_data_1_entry_carry, + ~_resetState & io_w_req_bits_data_1_entry_isCall, + ~_resetState & io_w_req_bits_data_1_entry_isRet, + ~_resetState & io_w_req_bits_data_1_entry_isJalr, + ~_resetState & io_w_req_bits_data_1_entry_last_may_be_rvi_call, + ~_resetState & io_w_req_bits_data_1_entry_always_taken_1, + ~_resetState & io_w_req_bits_data_1_entry_always_taken_0, + _resetState ? 20'h0 : io_w_req_bits_data_1_tag, + ~_resetState & io_w_req_bits_data_0_entry_valid, + _resetState ? 4'h0 : io_w_req_bits_data_0_entry_brSlots_0_offset, + _resetState ? 12'h0 : io_w_req_bits_data_0_entry_brSlots_0_lower, + _resetState ? 2'h0 : io_w_req_bits_data_0_entry_brSlots_0_tarStat, + ~_resetState & io_w_req_bits_data_0_entry_brSlots_0_sharing, + ~_resetState & io_w_req_bits_data_0_entry_brSlots_0_valid, + _resetState ? 4'h0 : io_w_req_bits_data_0_entry_tailSlot_offset, + _resetState ? 20'h0 : io_w_req_bits_data_0_entry_tailSlot_lower, + _resetState ? 2'h0 : io_w_req_bits_data_0_entry_tailSlot_tarStat, + ~_resetState & io_w_req_bits_data_0_entry_tailSlot_sharing, + ~_resetState & io_w_req_bits_data_0_entry_tailSlot_valid, + _resetState ? 4'h0 : io_w_req_bits_data_0_entry_pftAddr, + ~_resetState & io_w_req_bits_data_0_entry_carry, + ~_resetState & io_w_req_bits_data_0_entry_isCall, + ~_resetState & io_w_req_bits_data_0_entry_isRet, + ~_resetState & io_w_req_bits_data_0_entry_isJalr, + ~_resetState & io_w_req_bits_data_0_entry_last_may_be_rvi_call, + ~_resetState & io_w_req_bits_data_0_entry_always_taken_1, + ~_resetState & io_w_req_bits_data_0_entry_always_taken_0, + _resetState ? 20'h0 : io_w_req_bits_data_0_tag}), + .RW0_rdata (_array_RW0_rdata), + .RW0_wmask (_resetState ? 4'hF : io_w_req_bits_waymask) + ); + assign io_r_req_ready = ~_resetState & ~wen; + assign io_r_resp_data_0_entry_valid = _array_RW0_rdata[79]; + assign io_r_resp_data_0_entry_brSlots_0_offset = _array_RW0_rdata[78:75]; + assign io_r_resp_data_0_entry_brSlots_0_lower = _array_RW0_rdata[74:63]; + assign io_r_resp_data_0_entry_brSlots_0_tarStat = _array_RW0_rdata[62:61]; + assign io_r_resp_data_0_entry_brSlots_0_sharing = _array_RW0_rdata[60]; + assign io_r_resp_data_0_entry_brSlots_0_valid = _array_RW0_rdata[59]; + assign io_r_resp_data_0_entry_tailSlot_offset = _array_RW0_rdata[58:55]; + assign io_r_resp_data_0_entry_tailSlot_lower = _array_RW0_rdata[54:35]; + assign io_r_resp_data_0_entry_tailSlot_tarStat = _array_RW0_rdata[34:33]; + assign io_r_resp_data_0_entry_tailSlot_sharing = _array_RW0_rdata[32]; + assign io_r_resp_data_0_entry_tailSlot_valid = _array_RW0_rdata[31]; + assign io_r_resp_data_0_entry_pftAddr = _array_RW0_rdata[30:27]; + assign io_r_resp_data_0_entry_carry = _array_RW0_rdata[26]; + assign io_r_resp_data_0_entry_isCall = _array_RW0_rdata[25]; + assign io_r_resp_data_0_entry_isRet = _array_RW0_rdata[24]; + assign io_r_resp_data_0_entry_isJalr = _array_RW0_rdata[23]; + assign io_r_resp_data_0_entry_last_may_be_rvi_call = _array_RW0_rdata[22]; + assign io_r_resp_data_0_entry_always_taken_0 = _array_RW0_rdata[20]; + assign io_r_resp_data_0_entry_always_taken_1 = _array_RW0_rdata[21]; + assign io_r_resp_data_0_tag = _array_RW0_rdata[19:0]; + assign io_r_resp_data_1_entry_valid = _array_RW0_rdata[159]; + assign io_r_resp_data_1_entry_brSlots_0_offset = _array_RW0_rdata[158:155]; + assign io_r_resp_data_1_entry_brSlots_0_lower = _array_RW0_rdata[154:143]; + assign io_r_resp_data_1_entry_brSlots_0_tarStat = _array_RW0_rdata[142:141]; + assign io_r_resp_data_1_entry_brSlots_0_sharing = _array_RW0_rdata[140]; + assign io_r_resp_data_1_entry_brSlots_0_valid = _array_RW0_rdata[139]; + assign io_r_resp_data_1_entry_tailSlot_offset = _array_RW0_rdata[138:135]; + assign io_r_resp_data_1_entry_tailSlot_lower = _array_RW0_rdata[134:115]; + assign io_r_resp_data_1_entry_tailSlot_tarStat = _array_RW0_rdata[114:113]; + assign io_r_resp_data_1_entry_tailSlot_sharing = _array_RW0_rdata[112]; + assign io_r_resp_data_1_entry_tailSlot_valid = _array_RW0_rdata[111]; + assign io_r_resp_data_1_entry_pftAddr = _array_RW0_rdata[110:107]; + assign io_r_resp_data_1_entry_carry = _array_RW0_rdata[106]; + assign io_r_resp_data_1_entry_isCall = _array_RW0_rdata[105]; + assign io_r_resp_data_1_entry_isRet = _array_RW0_rdata[104]; + assign io_r_resp_data_1_entry_isJalr = _array_RW0_rdata[103]; + assign io_r_resp_data_1_entry_last_may_be_rvi_call = _array_RW0_rdata[102]; + assign io_r_resp_data_1_entry_always_taken_0 = _array_RW0_rdata[100]; + assign io_r_resp_data_1_entry_always_taken_1 = _array_RW0_rdata[101]; + assign io_r_resp_data_1_tag = _array_RW0_rdata[99:80]; + assign io_r_resp_data_2_entry_valid = _array_RW0_rdata[239]; + assign io_r_resp_data_2_entry_brSlots_0_offset = _array_RW0_rdata[238:235]; + assign io_r_resp_data_2_entry_brSlots_0_lower = _array_RW0_rdata[234:223]; + assign io_r_resp_data_2_entry_brSlots_0_tarStat = _array_RW0_rdata[222:221]; + assign io_r_resp_data_2_entry_brSlots_0_sharing = _array_RW0_rdata[220]; + assign io_r_resp_data_2_entry_brSlots_0_valid = _array_RW0_rdata[219]; + assign io_r_resp_data_2_entry_tailSlot_offset = _array_RW0_rdata[218:215]; + assign io_r_resp_data_2_entry_tailSlot_lower = _array_RW0_rdata[214:195]; + assign io_r_resp_data_2_entry_tailSlot_tarStat = _array_RW0_rdata[194:193]; + assign io_r_resp_data_2_entry_tailSlot_sharing = _array_RW0_rdata[192]; + assign io_r_resp_data_2_entry_tailSlot_valid = _array_RW0_rdata[191]; + assign io_r_resp_data_2_entry_pftAddr = _array_RW0_rdata[190:187]; + assign io_r_resp_data_2_entry_carry = _array_RW0_rdata[186]; + assign io_r_resp_data_2_entry_isCall = _array_RW0_rdata[185]; + assign io_r_resp_data_2_entry_isRet = _array_RW0_rdata[184]; + assign io_r_resp_data_2_entry_isJalr = _array_RW0_rdata[183]; + assign io_r_resp_data_2_entry_last_may_be_rvi_call = _array_RW0_rdata[182]; + assign io_r_resp_data_2_entry_always_taken_0 = _array_RW0_rdata[180]; + assign io_r_resp_data_2_entry_always_taken_1 = _array_RW0_rdata[181]; + assign io_r_resp_data_2_tag = _array_RW0_rdata[179:160]; + assign io_r_resp_data_3_entry_valid = _array_RW0_rdata[319]; + assign io_r_resp_data_3_entry_brSlots_0_offset = _array_RW0_rdata[318:315]; + assign io_r_resp_data_3_entry_brSlots_0_lower = _array_RW0_rdata[314:303]; + assign io_r_resp_data_3_entry_brSlots_0_tarStat = _array_RW0_rdata[302:301]; + assign io_r_resp_data_3_entry_brSlots_0_sharing = _array_RW0_rdata[300]; + assign io_r_resp_data_3_entry_brSlots_0_valid = _array_RW0_rdata[299]; + assign io_r_resp_data_3_entry_tailSlot_offset = _array_RW0_rdata[298:295]; + assign io_r_resp_data_3_entry_tailSlot_lower = _array_RW0_rdata[294:275]; + assign io_r_resp_data_3_entry_tailSlot_tarStat = _array_RW0_rdata[274:273]; + assign io_r_resp_data_3_entry_tailSlot_sharing = _array_RW0_rdata[272]; + assign io_r_resp_data_3_entry_tailSlot_valid = _array_RW0_rdata[271]; + assign io_r_resp_data_3_entry_pftAddr = _array_RW0_rdata[270:267]; + assign io_r_resp_data_3_entry_carry = _array_RW0_rdata[266]; + assign io_r_resp_data_3_entry_isCall = _array_RW0_rdata[265]; + assign io_r_resp_data_3_entry_isRet = _array_RW0_rdata[264]; + assign io_r_resp_data_3_entry_isJalr = _array_RW0_rdata[263]; + assign io_r_resp_data_3_entry_last_may_be_rvi_call = _array_RW0_rdata[262]; + assign io_r_resp_data_3_entry_always_taken_0 = _array_RW0_rdata[260]; + assign io_r_resp_data_3_entry_always_taken_1 = _array_RW0_rdata[261]; + assign io_r_resp_data_3_tag = _array_RW0_rdata[259:240]; +endmodule + diff --git a/rtl/BPUTop/SRAMTemplate_14.sv b/rtl/BPUTop/SRAMTemplate_14.sv new file mode 100644 index 0000000..532c6c8 --- /dev/null +++ b/rtl/BPUTop/SRAMTemplate_14.sv @@ -0,0 +1,248 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_14( + input clock, + input reset, + output io_r_req_ready, + input io_r_req_valid, + input [7:0] io_r_req_bits_setIdx, + output io_r_resp_data_0, + output io_r_resp_data_1, + output io_r_resp_data_2, + output io_r_resp_data_3, + output io_r_resp_data_4, + output io_r_resp_data_5, + output io_r_resp_data_6, + output io_r_resp_data_7, + output io_r_resp_data_8, + output io_r_resp_data_9, + output io_r_resp_data_10, + output io_r_resp_data_11, + output io_r_resp_data_12, + output io_r_resp_data_13, + output io_r_resp_data_14, + output io_r_resp_data_15, + input io_w_req_valid, + input [7:0] io_w_req_bits_setIdx, + input io_w_req_bits_data_0, + input io_w_req_bits_data_1, + input io_w_req_bits_data_2, + input io_w_req_bits_data_3, + input io_w_req_bits_data_4, + input io_w_req_bits_data_5, + input io_w_req_bits_data_6, + input io_w_req_bits_data_7, + input io_w_req_bits_data_8, + input io_w_req_bits_data_9, + input io_w_req_bits_data_10, + input io_w_req_bits_data_11, + input io_w_req_bits_data_12, + input io_w_req_bits_data_13, + input io_w_req_bits_data_14, + input io_w_req_bits_data_15, + input [15:0] io_w_req_bits_waymask, + input extra_reset +); + + wire [7:0] setIdx; + wire realRen; + wire wen; + wire [15:0] _array_RW0_rdata; + reg _resetState; + reg [7:0] _resetSet; + assign wen = io_w_req_valid | _resetState; + assign realRen = io_r_req_valid & ~wen; + assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx; + reg rdata_last_r; + reg rdata_hold_data_0; + reg rdata_hold_data_1; + reg rdata_hold_data_2; + reg rdata_hold_data_3; + reg rdata_hold_data_4; + reg rdata_hold_data_5; + reg rdata_hold_data_6; + reg rdata_hold_data_7; + reg rdata_hold_data_8; + reg rdata_hold_data_9; + reg rdata_hold_data_10; + reg rdata_hold_data_11; + reg rdata_hold_data_12; + reg rdata_hold_data_13; + reg rdata_hold_data_14; + reg rdata_hold_data_15; + always @(posedge clock or posedge reset) begin + if (reset) begin + _resetState <= 1'h1; + _resetSet <= 8'h0; + rdata_last_r <= 1'h0; + end + else begin + _resetState <= extra_reset | ~(_resetState & (&_resetSet)) & _resetState; + if (_resetState) + _resetSet <= 8'(_resetSet + 8'h1); + if (realRen | rdata_last_r) + rdata_last_r <= realRen; + end + end // always @(posedge, posedge) + always @(posedge clock) begin + if (rdata_last_r) begin + rdata_hold_data_0 <= _array_RW0_rdata[0]; + rdata_hold_data_1 <= _array_RW0_rdata[1]; + rdata_hold_data_2 <= _array_RW0_rdata[2]; + rdata_hold_data_3 <= _array_RW0_rdata[3]; + rdata_hold_data_4 <= _array_RW0_rdata[4]; + rdata_hold_data_5 <= _array_RW0_rdata[5]; + rdata_hold_data_6 <= _array_RW0_rdata[6]; + rdata_hold_data_7 <= _array_RW0_rdata[7]; + rdata_hold_data_8 <= _array_RW0_rdata[8]; + rdata_hold_data_9 <= _array_RW0_rdata[9]; + rdata_hold_data_10 <= _array_RW0_rdata[10]; + rdata_hold_data_11 <= _array_RW0_rdata[11]; + rdata_hold_data_12 <= _array_RW0_rdata[12]; + rdata_hold_data_13 <= _array_RW0_rdata[13]; + rdata_hold_data_14 <= _array_RW0_rdata[14]; + rdata_hold_data_15 <= _array_RW0_rdata[15]; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:33]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [5:0] i = 6'h0; i < 6'h22; i += 6'h1) begin + _RANDOM[i] = `RANDOM; + end + _resetState = _RANDOM[6'h0][0]; + _resetSet = _RANDOM[6'h0][8:1]; + rdata_last_r = _RANDOM[6'h21][10]; + rdata_hold_data_0 = _RANDOM[6'h21][11]; + rdata_hold_data_1 = _RANDOM[6'h21][12]; + rdata_hold_data_2 = _RANDOM[6'h21][13]; + rdata_hold_data_3 = _RANDOM[6'h21][14]; + rdata_hold_data_4 = _RANDOM[6'h21][15]; + rdata_hold_data_5 = _RANDOM[6'h21][16]; + rdata_hold_data_6 = _RANDOM[6'h21][17]; + rdata_hold_data_7 = _RANDOM[6'h21][18]; + rdata_hold_data_8 = _RANDOM[6'h21][19]; + rdata_hold_data_9 = _RANDOM[6'h21][20]; + rdata_hold_data_10 = _RANDOM[6'h21][21]; + rdata_hold_data_11 = _RANDOM[6'h21][22]; + rdata_hold_data_12 = _RANDOM[6'h21][23]; + rdata_hold_data_13 = _RANDOM[6'h21][24]; + rdata_hold_data_14 = _RANDOM[6'h21][25]; + rdata_hold_data_15 = _RANDOM[6'h21][26]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + _resetState = 1'h1; + _resetSet = 8'h0; + rdata_last_r = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_4 array ( + .RW0_addr (wen ? setIdx : io_r_req_bits_setIdx), + .RW0_en (realRen | wen), + .RW0_clk (clock), + .RW0_wmode (wen), + .RW0_wdata + ({~_resetState & io_w_req_bits_data_15, + ~_resetState & io_w_req_bits_data_14, + ~_resetState & io_w_req_bits_data_13, + ~_resetState & io_w_req_bits_data_12, + ~_resetState & io_w_req_bits_data_11, + ~_resetState & io_w_req_bits_data_10, + ~_resetState & io_w_req_bits_data_9, + ~_resetState & io_w_req_bits_data_8, + ~_resetState & io_w_req_bits_data_7, + ~_resetState & io_w_req_bits_data_6, + ~_resetState & io_w_req_bits_data_5, + ~_resetState & io_w_req_bits_data_4, + ~_resetState & io_w_req_bits_data_3, + ~_resetState & io_w_req_bits_data_2, + ~_resetState & io_w_req_bits_data_1, + ~_resetState & io_w_req_bits_data_0}), + .RW0_rdata (_array_RW0_rdata), + .RW0_wmask (_resetState ? 16'hFFFF : io_w_req_bits_waymask) + ); + assign io_r_req_ready = ~_resetState & ~wen; + assign io_r_resp_data_0 = rdata_last_r ? _array_RW0_rdata[0] : rdata_hold_data_0; + assign io_r_resp_data_1 = rdata_last_r ? _array_RW0_rdata[1] : rdata_hold_data_1; + assign io_r_resp_data_2 = rdata_last_r ? _array_RW0_rdata[2] : rdata_hold_data_2; + assign io_r_resp_data_3 = rdata_last_r ? _array_RW0_rdata[3] : rdata_hold_data_3; + assign io_r_resp_data_4 = rdata_last_r ? _array_RW0_rdata[4] : rdata_hold_data_4; + assign io_r_resp_data_5 = rdata_last_r ? _array_RW0_rdata[5] : rdata_hold_data_5; + assign io_r_resp_data_6 = rdata_last_r ? _array_RW0_rdata[6] : rdata_hold_data_6; + assign io_r_resp_data_7 = rdata_last_r ? _array_RW0_rdata[7] : rdata_hold_data_7; + assign io_r_resp_data_8 = rdata_last_r ? _array_RW0_rdata[8] : rdata_hold_data_8; + assign io_r_resp_data_9 = rdata_last_r ? _array_RW0_rdata[9] : rdata_hold_data_9; + assign io_r_resp_data_10 = rdata_last_r ? _array_RW0_rdata[10] : rdata_hold_data_10; + assign io_r_resp_data_11 = rdata_last_r ? _array_RW0_rdata[11] : rdata_hold_data_11; + assign io_r_resp_data_12 = rdata_last_r ? _array_RW0_rdata[12] : rdata_hold_data_12; + assign io_r_resp_data_13 = rdata_last_r ? _array_RW0_rdata[13] : rdata_hold_data_13; + assign io_r_resp_data_14 = rdata_last_r ? _array_RW0_rdata[14] : rdata_hold_data_14; + assign io_r_resp_data_15 = rdata_last_r ? _array_RW0_rdata[15] : rdata_hold_data_15; +endmodule + diff --git a/rtl/BPUTop/SRAMTemplate_15.sv b/rtl/BPUTop/SRAMTemplate_15.sv new file mode 100644 index 0000000..f57e511 --- /dev/null +++ b/rtl/BPUTop/SRAMTemplate_15.sv @@ -0,0 +1,165 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_15( + input clock, + input reset, + output io_r_req_ready, + input io_r_req_valid, + input [8:0] io_r_req_bits_setIdx, + output io_r_resp_data_0_valid, + output [7:0] io_r_resp_data_0_tag, + output [2:0] io_r_resp_data_0_ctr, + output io_r_resp_data_1_valid, + output [7:0] io_r_resp_data_1_tag, + output [2:0] io_r_resp_data_1_ctr, + input io_w_req_valid, + input [8:0] io_w_req_bits_setIdx, + input [7:0] io_w_req_bits_data_0_tag, + input [2:0] io_w_req_bits_data_0_ctr, + input [7:0] io_w_req_bits_data_1_tag, + input [2:0] io_w_req_bits_data_1_ctr, + input [1:0] io_w_req_bits_waymask +); + + wire [8:0] setIdx; + wire realRen; + wire wen; + wire [23:0] _array_RW0_rdata; + reg _resetState; + reg [8:0] _resetSet; + assign wen = io_w_req_valid | _resetState; + assign realRen = io_r_req_valid & ~wen; + assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx; + reg rdata_last_r; + reg [11:0] rdata_hold_data_0; + reg [11:0] rdata_hold_data_1; + wire [11:0] _rdata_T_0 = rdata_last_r ? _array_RW0_rdata[11:0] : rdata_hold_data_0; + wire [11:0] _rdata_T_1 = rdata_last_r ? _array_RW0_rdata[23:12] : rdata_hold_data_1; + always @(posedge clock or posedge reset) begin + if (reset) begin + _resetState <= 1'h1; + _resetSet <= 9'h0; + rdata_last_r <= 1'h0; + end + else begin + _resetState <= ~(_resetState & (&_resetSet)) & _resetState; + if (_resetState) + _resetSet <= 9'(_resetSet + 9'h1); + if (realRen | rdata_last_r) + rdata_last_r <= realRen; + end + end // always @(posedge, posedge) + always @(posedge clock) begin + if (rdata_last_r) begin + rdata_hold_data_0 <= _array_RW0_rdata[11:0]; + rdata_hold_data_1 <= _array_RW0_rdata[23:12]; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:5]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin + _RANDOM[i] = `RANDOM; + end + _resetState = _RANDOM[3'h0][0]; + _resetSet = _RANDOM[3'h0][9:1]; + rdata_last_r = _RANDOM[3'h4][31]; + rdata_hold_data_0 = _RANDOM[3'h5][11:0]; + rdata_hold_data_1 = _RANDOM[3'h5][23:12]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + _resetState = 1'h1; + _resetSet = 9'h0; + rdata_last_r = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_5 array ( + .RW0_addr (wen ? setIdx : io_r_req_bits_setIdx), + .RW0_en (realRen | wen), + .RW0_clk (clock), + .RW0_wmode (wen), + .RW0_wdata + ({~_resetState, + _resetState ? 8'h0 : io_w_req_bits_data_1_tag, + _resetState ? 3'h0 : io_w_req_bits_data_1_ctr, + ~_resetState, + _resetState ? 8'h0 : io_w_req_bits_data_0_tag, + _resetState ? 3'h0 : io_w_req_bits_data_0_ctr}), + .RW0_rdata (_array_RW0_rdata), + .RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask) + ); + assign io_r_req_ready = ~_resetState & ~wen; + assign io_r_resp_data_0_valid = _rdata_T_0[11]; + assign io_r_resp_data_0_tag = _rdata_T_0[10:3]; + assign io_r_resp_data_0_ctr = _rdata_T_0[2:0]; + assign io_r_resp_data_1_valid = _rdata_T_1[11]; + assign io_r_resp_data_1_tag = _rdata_T_1[10:3]; + assign io_r_resp_data_1_ctr = _rdata_T_1[2:0]; +endmodule + diff --git a/rtl/BPUTop/SRAMTemplate_34.sv b/rtl/BPUTop/SRAMTemplate_34.sv new file mode 100644 index 0000000..8542d46 --- /dev/null +++ b/rtl/BPUTop/SRAMTemplate_34.sv @@ -0,0 +1,229 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_34( + input clock, + input reset, + input io_r_req_valid, + input [8:0] io_r_req_bits_setIdx, + output [1:0] io_r_resp_data_0, + output [1:0] io_r_resp_data_1, + output [1:0] io_r_resp_data_2, + output [1:0] io_r_resp_data_3, + output [1:0] io_r_resp_data_4, + output [1:0] io_r_resp_data_5, + output [1:0] io_r_resp_data_6, + output [1:0] io_r_resp_data_7, + input io_w_req_valid, + input [8:0] io_w_req_bits_setIdx, + input [1:0] io_w_req_bits_data_0, + input [1:0] io_w_req_bits_data_1, + input [1:0] io_w_req_bits_data_2, + input [1:0] io_w_req_bits_data_3, + input [1:0] io_w_req_bits_data_4, + input [1:0] io_w_req_bits_data_5, + input [1:0] io_w_req_bits_data_6, + input [1:0] io_w_req_bits_data_7, + input [7:0] io_w_req_bits_waymask +); + + wire [15:0] _array_R0_data; + reg [1:0] bypass_wdata_r_0; + reg [1:0] bypass_wdata_r_1; + reg [1:0] bypass_wdata_r_2; + reg [1:0] bypass_wdata_r_3; + reg [1:0] bypass_wdata_r_4; + reg [1:0] bypass_wdata_r_5; + reg [1:0] bypass_wdata_r_6; + reg [1:0] bypass_wdata_r_7; + wire bypass_mask_need_check = io_r_req_valid & io_w_req_valid; + reg bypass_mask_need_check_reg_last_r; + reg [8:0] bypass_mask_waddr_reg; + reg [8:0] bypass_mask_raddr_reg; + reg [7:0] bypass_mask_wmask_reg; + wire [7:0] bypass_mask = + {8{bypass_mask_need_check_reg_last_r + & bypass_mask_waddr_reg == bypass_mask_raddr_reg}} & bypass_mask_wmask_reg; + wire [1:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_r_0 : _array_R0_data[1:0]; + wire [1:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_r_1 : _array_R0_data[3:2]; + wire [1:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_r_2 : _array_R0_data[5:4]; + wire [1:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_r_3 : _array_R0_data[7:6]; + wire [1:0] mem_rdata_4 = bypass_mask[4] ? bypass_wdata_r_4 : _array_R0_data[9:8]; + wire [1:0] mem_rdata_5 = bypass_mask[5] ? bypass_wdata_r_5 : _array_R0_data[11:10]; + wire [1:0] mem_rdata_6 = bypass_mask[6] ? bypass_wdata_r_6 : _array_R0_data[13:12]; + wire [1:0] mem_rdata_7 = bypass_mask[7] ? bypass_wdata_r_7 : _array_R0_data[15:14]; + reg rdata_last_r; + reg [1:0] rdata_hold_data_0; + reg [1:0] rdata_hold_data_1; + reg [1:0] rdata_hold_data_2; + reg [1:0] rdata_hold_data_3; + reg [1:0] rdata_hold_data_4; + reg [1:0] rdata_hold_data_5; + reg [1:0] rdata_hold_data_6; + reg [1:0] rdata_hold_data_7; + always @(posedge clock) begin + if (io_w_req_valid & io_r_req_valid) begin + bypass_wdata_r_0 <= io_w_req_bits_data_0; + bypass_wdata_r_1 <= io_w_req_bits_data_1; + bypass_wdata_r_2 <= io_w_req_bits_data_2; + bypass_wdata_r_3 <= io_w_req_bits_data_3; + bypass_wdata_r_4 <= io_w_req_bits_data_4; + bypass_wdata_r_5 <= io_w_req_bits_data_5; + bypass_wdata_r_6 <= io_w_req_bits_data_6; + bypass_wdata_r_7 <= io_w_req_bits_data_7; + end + if (bypass_mask_need_check) begin + bypass_mask_waddr_reg <= io_w_req_bits_setIdx; + bypass_mask_raddr_reg <= io_r_req_bits_setIdx; + bypass_mask_wmask_reg <= io_w_req_bits_waymask; + end + if (rdata_last_r) begin + rdata_hold_data_0 <= mem_rdata_0; + rdata_hold_data_1 <= mem_rdata_1; + rdata_hold_data_2 <= mem_rdata_2; + rdata_hold_data_3 <= mem_rdata_3; + rdata_hold_data_4 <= mem_rdata_4; + rdata_hold_data_5 <= mem_rdata_5; + rdata_hold_data_6 <= mem_rdata_6; + rdata_hold_data_7 <= mem_rdata_7; + end + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) begin + bypass_mask_need_check_reg_last_r <= 1'h0; + rdata_last_r <= 1'h0; + end + else begin + if (bypass_mask_need_check | bypass_mask_need_check_reg_last_r) + bypass_mask_need_check_reg_last_r <= bypass_mask_need_check; + if (io_r_req_valid | rdata_last_r) + rdata_last_r <= io_r_req_valid; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; + end + bypass_wdata_r_0 = _RANDOM[1'h0][1:0]; + bypass_wdata_r_1 = _RANDOM[1'h0][3:2]; + bypass_wdata_r_2 = _RANDOM[1'h0][5:4]; + bypass_wdata_r_3 = _RANDOM[1'h0][7:6]; + bypass_wdata_r_4 = _RANDOM[1'h0][9:8]; + bypass_wdata_r_5 = _RANDOM[1'h0][11:10]; + bypass_wdata_r_6 = _RANDOM[1'h0][13:12]; + bypass_wdata_r_7 = _RANDOM[1'h0][15:14]; + bypass_mask_need_check_reg_last_r = _RANDOM[1'h0][16]; + bypass_mask_waddr_reg = _RANDOM[1'h0][25:17]; + bypass_mask_raddr_reg = {_RANDOM[1'h0][31:26], _RANDOM[1'h1][2:0]}; + bypass_mask_wmask_reg = _RANDOM[1'h1][10:3]; + rdata_last_r = _RANDOM[1'h1][11]; + rdata_hold_data_0 = _RANDOM[1'h1][13:12]; + rdata_hold_data_1 = _RANDOM[1'h1][15:14]; + rdata_hold_data_2 = _RANDOM[1'h1][17:16]; + rdata_hold_data_3 = _RANDOM[1'h1][19:18]; + rdata_hold_data_4 = _RANDOM[1'h1][21:20]; + rdata_hold_data_5 = _RANDOM[1'h1][23:22]; + rdata_hold_data_6 = _RANDOM[1'h1][25:24]; + rdata_hold_data_7 = _RANDOM[1'h1][27:26]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + bypass_mask_need_check_reg_last_r = 1'h0; + rdata_last_r = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_6 array ( + .R0_addr (io_r_req_bits_setIdx), + .R0_en (io_r_req_valid), + .R0_clk (clock), + .R0_data (_array_R0_data), + .W0_addr (io_w_req_bits_setIdx), + .W0_en (io_w_req_valid), + .W0_clk (clock), + .W0_data + ({io_w_req_bits_data_7, + io_w_req_bits_data_6, + io_w_req_bits_data_5, + io_w_req_bits_data_4, + io_w_req_bits_data_3, + io_w_req_bits_data_2, + io_w_req_bits_data_1, + io_w_req_bits_data_0}), + .W0_mask (io_w_req_bits_waymask) + ); + assign io_r_resp_data_0 = rdata_last_r ? mem_rdata_0 : rdata_hold_data_0; + assign io_r_resp_data_1 = rdata_last_r ? mem_rdata_1 : rdata_hold_data_1; + assign io_r_resp_data_2 = rdata_last_r ? mem_rdata_2 : rdata_hold_data_2; + assign io_r_resp_data_3 = rdata_last_r ? mem_rdata_3 : rdata_hold_data_3; + assign io_r_resp_data_4 = rdata_last_r ? mem_rdata_4 : rdata_hold_data_4; + assign io_r_resp_data_5 = rdata_last_r ? mem_rdata_5 : rdata_hold_data_5; + assign io_r_resp_data_6 = rdata_last_r ? mem_rdata_6 : rdata_hold_data_6; + assign io_r_resp_data_7 = rdata_last_r ? mem_rdata_7 : rdata_hold_data_7; +endmodule + diff --git a/rtl/BPUTop/SRAMTemplate_35.sv b/rtl/BPUTop/SRAMTemplate_35.sv new file mode 100644 index 0000000..3c57c92 --- /dev/null +++ b/rtl/BPUTop/SRAMTemplate_35.sv @@ -0,0 +1,196 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_35( + input clock, + input reset, + input io_r_req_valid, + input [7:0] io_r_req_bits_setIdx, + output [5:0] io_r_resp_data_0, + output [5:0] io_r_resp_data_1, + output [5:0] io_r_resp_data_2, + output [5:0] io_r_resp_data_3, + input io_w_req_valid, + input [7:0] io_w_req_bits_setIdx, + input [5:0] io_w_req_bits_data_0, + input [5:0] io_w_req_bits_data_1, + input [5:0] io_w_req_bits_data_2, + input [5:0] io_w_req_bits_data_3, + input [3:0] io_w_req_bits_waymask +); + + wire [23:0] _array_R0_data; + reg _resetState; + reg [7:0] _resetSet; + reg [5:0] bypass_wdata_r_0; + reg [5:0] bypass_wdata_r_1; + reg [5:0] bypass_wdata_r_2; + reg [5:0] bypass_wdata_r_3; + wire bypass_mask_need_check = io_r_req_valid & io_w_req_valid; + reg bypass_mask_need_check_reg_last_r; + reg [7:0] bypass_mask_waddr_reg; + reg [7:0] bypass_mask_raddr_reg; + reg [3:0] bypass_mask_wmask_reg; + wire [3:0] bypass_mask = + {4{bypass_mask_need_check_reg_last_r + & bypass_mask_waddr_reg == bypass_mask_raddr_reg}} & bypass_mask_wmask_reg; + wire [5:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_r_0 : _array_R0_data[5:0]; + wire [5:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_r_1 : _array_R0_data[11:6]; + wire [5:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_r_2 : _array_R0_data[17:12]; + wire [5:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_r_3 : _array_R0_data[23:18]; + reg rdata_last_r; + reg [5:0] rdata_hold_data_0; + reg [5:0] rdata_hold_data_1; + reg [5:0] rdata_hold_data_2; + reg [5:0] rdata_hold_data_3; + always @(posedge clock or posedge reset) begin + if (reset) begin + _resetState <= 1'h1; + _resetSet <= 8'h0; + bypass_mask_need_check_reg_last_r <= 1'h0; + rdata_last_r <= 1'h0; + end + else begin + _resetState <= ~(_resetState & (&_resetSet)) & _resetState; + if (_resetState) + _resetSet <= 8'(_resetSet + 8'h1); + if (bypass_mask_need_check | bypass_mask_need_check_reg_last_r) + bypass_mask_need_check_reg_last_r <= bypass_mask_need_check; + if (io_r_req_valid | rdata_last_r) + rdata_last_r <= io_r_req_valid; + end + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_w_req_valid & io_r_req_valid) begin + bypass_wdata_r_0 <= io_w_req_bits_data_0; + bypass_wdata_r_1 <= io_w_req_bits_data_1; + bypass_wdata_r_2 <= io_w_req_bits_data_2; + bypass_wdata_r_3 <= io_w_req_bits_data_3; + end + if (bypass_mask_need_check) begin + bypass_mask_waddr_reg <= io_w_req_bits_setIdx; + bypass_mask_raddr_reg <= io_r_req_bits_setIdx; + bypass_mask_wmask_reg <= io_w_req_bits_waymask; + end + if (rdata_last_r) begin + rdata_hold_data_0 <= mem_rdata_0; + rdata_hold_data_1 <= mem_rdata_1; + rdata_hold_data_2 <= mem_rdata_2; + rdata_hold_data_3 <= mem_rdata_3; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; + end + _resetState = _RANDOM[2'h0][0]; + _resetSet = _RANDOM[2'h0][8:1]; + bypass_wdata_r_0 = _RANDOM[2'h0][14:9]; + bypass_wdata_r_1 = _RANDOM[2'h0][20:15]; + bypass_wdata_r_2 = _RANDOM[2'h0][26:21]; + bypass_wdata_r_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][0]}; + bypass_mask_need_check_reg_last_r = _RANDOM[2'h1][1]; + bypass_mask_waddr_reg = _RANDOM[2'h1][9:2]; + bypass_mask_raddr_reg = _RANDOM[2'h1][17:10]; + bypass_mask_wmask_reg = _RANDOM[2'h1][21:18]; + rdata_last_r = _RANDOM[2'h1][22]; + rdata_hold_data_0 = _RANDOM[2'h1][28:23]; + rdata_hold_data_1 = {_RANDOM[2'h1][31:29], _RANDOM[2'h2][2:0]}; + rdata_hold_data_2 = _RANDOM[2'h2][8:3]; + rdata_hold_data_3 = _RANDOM[2'h2][14:9]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + _resetState = 1'h1; + _resetSet = 8'h0; + bypass_mask_need_check_reg_last_r = 1'h0; + rdata_last_r = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_7 array ( + .R0_addr (io_r_req_bits_setIdx), + .R0_en (io_r_req_valid), + .R0_clk (clock), + .R0_data (_array_R0_data), + .W0_addr (_resetState ? _resetSet : io_w_req_bits_setIdx), + .W0_en (io_w_req_valid | _resetState), + .W0_clk (clock), + .W0_data + ({_resetState ? 6'h0 : io_w_req_bits_data_3, + _resetState ? 6'h0 : io_w_req_bits_data_2, + _resetState ? 6'h0 : io_w_req_bits_data_1, + _resetState ? 6'h0 : io_w_req_bits_data_0}), + .W0_mask (_resetState ? 4'hF : io_w_req_bits_waymask) + ); + assign io_r_resp_data_0 = rdata_last_r ? mem_rdata_0 : rdata_hold_data_0; + assign io_r_resp_data_1 = rdata_last_r ? mem_rdata_1 : rdata_hold_data_1; + assign io_r_resp_data_2 = rdata_last_r ? mem_rdata_2 : rdata_hold_data_2; + assign io_r_resp_data_3 = rdata_last_r ? mem_rdata_3 : rdata_hold_data_3; +endmodule + diff --git a/rtl/BPUTop/SRAMTemplate_39.sv b/rtl/BPUTop/SRAMTemplate_39.sv new file mode 100644 index 0000000..3fd702a --- /dev/null +++ b/rtl/BPUTop/SRAMTemplate_39.sv @@ -0,0 +1,149 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_39( + input clock, + input reset, + input io_r_req_valid, + input [6:0] io_r_req_bits_setIdx, + output io_r_resp_data_0_valid, + output [8:0] io_r_resp_data_0_tag, + output [1:0] io_r_resp_data_0_ctr, + output [40:0] io_r_resp_data_0_target, + input io_w_req_valid, + input [6:0] io_w_req_bits_setIdx, + input [8:0] io_w_req_bits_data_0_tag, + input [1:0] io_w_req_bits_data_0_ctr, + input [40:0] io_w_req_bits_data_0_target +); + + wire [6:0] setIdx; + wire realRen; + wire wen; + wire [52:0] _array_0_RW0_rdata; + reg _resetState; + reg [6:0] _resetSet; + assign wen = io_w_req_valid | _resetState; + assign realRen = io_r_req_valid & ~wen; + assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx; + reg rdata_last_r; + reg [52:0] rdata_hold_data_0; + wire [52:0] _rdata_T_0 = rdata_last_r ? _array_0_RW0_rdata : rdata_hold_data_0; + always @(posedge clock or posedge reset) begin + if (reset) begin + _resetState <= 1'h1; + _resetSet <= 7'h0; + rdata_last_r <= 1'h0; + end + else begin + _resetState <= ~(_resetState & (&_resetSet)) & _resetState; + if (_resetState) + _resetSet <= 7'(_resetSet + 7'h1); + if (realRen | rdata_last_r) + rdata_last_r <= realRen; + end + end // always @(posedge, posedge) + always @(posedge clock) begin + if (rdata_last_r) + rdata_hold_data_0 <= _array_0_RW0_rdata; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:4]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h5; i += 3'h1) begin + _RANDOM[i] = `RANDOM; + end + _resetState = _RANDOM[3'h0][0]; + _resetSet = _RANDOM[3'h0][7:1]; + rdata_last_r = _RANDOM[3'h2][24]; + rdata_hold_data_0 = {_RANDOM[3'h2][31:25], _RANDOM[3'h3], _RANDOM[3'h4][13:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + _resetState = 1'h1; + _resetSet = 7'h0; + rdata_last_r = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_0_0 array_0 ( + .RW0_addr (wen ? setIdx : io_r_req_bits_setIdx), + .RW0_en (realRen | wen), + .RW0_clk (clock), + .RW0_wmode (wen), + .RW0_wdata + ({~_resetState, + _resetState ? 9'h0 : io_w_req_bits_data_0_tag, + _resetState ? 2'h0 : io_w_req_bits_data_0_ctr, + _resetState ? 41'h0 : io_w_req_bits_data_0_target}), + .RW0_rdata (_array_0_RW0_rdata) + ); + assign io_r_resp_data_0_valid = _rdata_T_0[52]; + assign io_r_resp_data_0_tag = _rdata_T_0[51:43]; + assign io_r_resp_data_0_ctr = _rdata_T_0[42:41]; + assign io_r_resp_data_0_target = _rdata_T_0[40:0]; +endmodule + diff --git a/rtl/BPUTop/SRAMTemplate_43.sv b/rtl/BPUTop/SRAMTemplate_43.sv new file mode 100644 index 0000000..a908ac0 --- /dev/null +++ b/rtl/BPUTop/SRAMTemplate_43.sv @@ -0,0 +1,171 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module SRAMTemplate_43( + input clock, + input reset, + input io_r_req_valid, + input [6:0] io_r_req_bits_setIdx, + output io_r_resp_data_0_valid, + output [8:0] io_r_resp_data_0_tag, + output [1:0] io_r_resp_data_0_ctr, + output [40:0] io_r_resp_data_0_target, + output io_r_resp_data_1_valid, + output [8:0] io_r_resp_data_1_tag, + output [1:0] io_r_resp_data_1_ctr, + output [40:0] io_r_resp_data_1_target, + input io_w_req_valid, + input [6:0] io_w_req_bits_setIdx, + input [8:0] io_w_req_bits_data_0_tag, + input [1:0] io_w_req_bits_data_0_ctr, + input [40:0] io_w_req_bits_data_0_target, + input [8:0] io_w_req_bits_data_1_tag, + input [1:0] io_w_req_bits_data_1_ctr, + input [40:0] io_w_req_bits_data_1_target, + input [1:0] io_w_req_bits_waymask +); + + wire [6:0] setIdx; + wire realRen; + wire wen; + wire [105:0] _array_RW0_rdata; + reg _resetState; + reg [6:0] _resetSet; + assign wen = io_w_req_valid | _resetState; + assign realRen = io_r_req_valid & ~wen; + assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx; + reg rdata_last_r; + reg [52:0] rdata_hold_data_0; + reg [52:0] rdata_hold_data_1; + wire [52:0] _rdata_T_0 = rdata_last_r ? _array_RW0_rdata[52:0] : rdata_hold_data_0; + wire [52:0] _rdata_T_1 = rdata_last_r ? _array_RW0_rdata[105:53] : rdata_hold_data_1; + always @(posedge clock or posedge reset) begin + if (reset) begin + _resetState <= 1'h1; + _resetSet <= 7'h0; + rdata_last_r <= 1'h0; + end + else begin + _resetState <= ~(_resetState & (&_resetSet)) & _resetState; + if (_resetState) + _resetSet <= 7'(_resetSet + 7'h1); + if (realRen | rdata_last_r) + rdata_last_r <= realRen; + end + end // always @(posedge, posedge) + always @(posedge clock) begin + if (rdata_last_r) begin + rdata_hold_data_0 <= _array_RW0_rdata[52:0]; + rdata_hold_data_1 <= _array_RW0_rdata[105:53]; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:8]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [3:0] i = 4'h0; i < 4'h9; i += 4'h1) begin + _RANDOM[i] = `RANDOM; + end + _resetState = _RANDOM[4'h0][0]; + _resetSet = _RANDOM[4'h0][7:1]; + rdata_last_r = _RANDOM[4'h4][25]; + rdata_hold_data_0 = {_RANDOM[4'h4][31:26], _RANDOM[4'h5], _RANDOM[4'h6][14:0]}; + rdata_hold_data_1 = {_RANDOM[4'h6][31:15], _RANDOM[4'h7], _RANDOM[4'h8][3:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + _resetState = 1'h1; + _resetSet = 7'h0; + rdata_last_r = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + array_8 array ( + .RW0_addr (wen ? setIdx : io_r_req_bits_setIdx), + .RW0_en (realRen | wen), + .RW0_clk (clock), + .RW0_wmode (wen), + .RW0_wdata + ({~_resetState, + _resetState ? 9'h0 : io_w_req_bits_data_1_tag, + _resetState ? 2'h0 : io_w_req_bits_data_1_ctr, + _resetState ? 41'h0 : io_w_req_bits_data_1_target, + ~_resetState, + _resetState ? 9'h0 : io_w_req_bits_data_0_tag, + _resetState ? 2'h0 : io_w_req_bits_data_0_ctr, + _resetState ? 41'h0 : io_w_req_bits_data_0_target}), + .RW0_rdata (_array_RW0_rdata), + .RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask) + ); + assign io_r_resp_data_0_valid = _rdata_T_0[52]; + assign io_r_resp_data_0_tag = _rdata_T_0[51:43]; + assign io_r_resp_data_0_ctr = _rdata_T_0[42:41]; + assign io_r_resp_data_0_target = _rdata_T_0[40:0]; + assign io_r_resp_data_1_valid = _rdata_T_1[52]; + assign io_r_resp_data_1_tag = _rdata_T_1[51:43]; + assign io_r_resp_data_1_ctr = _rdata_T_1[42:41]; + assign io_r_resp_data_1_target = _rdata_T_1[40:0]; +endmodule + diff --git a/rtl/BPUTop/TageBTable.sv b/rtl/BPUTop/TageBTable.sv new file mode 100644 index 0000000..4ecd095 --- /dev/null +++ b/rtl/BPUTop/TageBTable.sv @@ -0,0 +1,188 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module TageBTable( + input clock, + input reset, + output io_req_ready, + input io_req_valid, + input [40:0] io_req_bits, + output [1:0] io_s1_cnt_0, + output [1:0] io_s1_cnt_1, + input io_update_mask_0, + input io_update_mask_1, + input [40:0] io_update_pc, + input [1:0] io_update_cnt_0, + input [1:0] io_update_cnt_1, + input io_update_takens_0, + input io_update_takens_1 +); + + wire [1:0] newCtrs_1; + wire [1:0] newCtrs_0; + wire _wrbypass_io_hit; + wire _wrbypass_io_hit_data_0_valid; + wire [1:0] _wrbypass_io_hit_data_0_bits; + wire _wrbypass_io_hit_data_1_valid; + wire [1:0] _wrbypass_io_hit_data_1_bits; + wire [1:0] _bt_io_r_resp_data_0; + wire [1:0] _bt_io_r_resp_data_1; + reg doing_reset; + reg [10:0] resetRow; + reg [10:0] s1_idx; + wire _wrbypass_io_wen_T = io_update_mask_0 | io_update_mask_1; + wire [1:0] oldCtrs_0 = + _wrbypass_io_hit + & (io_update_pc[1] ? _wrbypass_io_hit_data_1_valid : _wrbypass_io_hit_data_0_valid) + ? (io_update_pc[1] ? _wrbypass_io_hit_data_1_bits : _wrbypass_io_hit_data_0_bits) + : io_update_pc[1] ? io_update_cnt_1 : io_update_cnt_0; + wire [1:0] oldCtrs_1 = + _wrbypass_io_hit + & (io_update_pc[1] ? _wrbypass_io_hit_data_0_valid : _wrbypass_io_hit_data_1_valid) + ? (io_update_pc[1] ? _wrbypass_io_hit_data_0_bits : _wrbypass_io_hit_data_1_bits) + : io_update_pc[1] ? io_update_cnt_0 : io_update_cnt_1; + wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; + assign newCtrs_0 = + (&oldCtrs_0) & _GEN + ? 2'h3 + : oldCtrs_0 == 2'h0 & ~_GEN + ? 2'h0 + : _GEN ? 2'(oldCtrs_0 + 2'h1) : 2'(oldCtrs_0 - 2'h1); + wire _GEN_0 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; + assign newCtrs_1 = + (&oldCtrs_1) & _GEN_0 + ? 2'h3 + : oldCtrs_1 == 2'h0 & ~_GEN_0 + ? 2'h0 + : _GEN_0 ? 2'(oldCtrs_1 + 2'h1) : 2'(oldCtrs_1 - 2'h1); + always @(posedge clock or posedge reset) begin + if (reset) begin + doing_reset <= 1'h1; + resetRow <= 11'h0; + end + else begin + doing_reset <= resetRow != 11'h7FF & doing_reset; + resetRow <= 11'(resetRow + {10'h0, doing_reset}); + end + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_req_valid) + s1_idx <= io_req_bits[11:1]; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; + resetRow = _RANDOM[/*Zero width*/ 1'b0][11:1]; + s1_idx = _RANDOM[/*Zero width*/ 1'b0][22:12]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + doing_reset = 1'h1; + resetRow = 11'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FoldedSRAMTemplate_20 bt ( + .clock (clock), + .reset (reset), + .io_r_req_valid (io_req_valid), + .io_r_req_bits_setIdx (io_req_bits[11:1]), + .io_r_resp_data_0 (_bt_io_r_resp_data_0), + .io_r_resp_data_1 (_bt_io_r_resp_data_1), + .io_w_req_valid (_wrbypass_io_wen_T | doing_reset), + .io_w_req_bits_setIdx (doing_reset ? resetRow : io_update_pc[11:1]), + .io_w_req_bits_data_0 (doing_reset ? 2'h2 : newCtrs_0), + .io_w_req_bits_data_1 (doing_reset ? 2'h2 : newCtrs_1), + .io_w_req_bits_waymask + (doing_reset + ? 2'h3 + : {io_update_mask_0 & io_update_pc[1] | io_update_mask_1 & ~(io_update_pc[1]), + io_update_mask_0 & ~(io_update_pc[1]) | io_update_mask_1 & io_update_pc[1]}) + ); + WrBypass_32 wrbypass ( + .clock (clock), + .reset (reset), + .io_wen (_wrbypass_io_wen_T), + .io_write_idx (io_update_pc[11:1]), + .io_write_data_0 (io_update_pc[1] ? newCtrs_1 : newCtrs_0), + .io_write_data_1 (io_update_pc[1] ? newCtrs_0 : newCtrs_1), + .io_write_way_mask_0 (io_update_mask_0), + .io_write_way_mask_1 (io_update_mask_1), + .io_hit (_wrbypass_io_hit), + .io_hit_data_0_valid (_wrbypass_io_hit_data_0_valid), + .io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits), + .io_hit_data_1_valid (_wrbypass_io_hit_data_1_valid), + .io_hit_data_1_bits (_wrbypass_io_hit_data_1_bits) + ); + assign io_req_ready = ~doing_reset; + assign io_s1_cnt_0 = + (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_0) | (s1_idx[0] ? _bt_io_r_resp_data_1 : 2'h0); + assign io_s1_cnt_1 = + (s1_idx[0] ? _bt_io_r_resp_data_0 : 2'h0) | (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_1); +endmodule + diff --git a/rtl/BPUTop/TageTable.sv b/rtl/BPUTop/TageTable.sv new file mode 100644 index 0000000..f97c7a7 --- /dev/null +++ b/rtl/BPUTop/TageTable.sv @@ -0,0 +1,752 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module TageTable( + input clock, + input reset, + output io_req_ready, + input io_req_valid, + input [40:0] io_req_bits_pc, + input [7:0] io_req_bits_folded_hist_hist_14_folded_hist, + input [6:0] io_req_bits_folded_hist_hist_7_folded_hist, + output io_resps_0_valid, + output [2:0] io_resps_0_bits_ctr, + output io_resps_0_bits_u, + output io_resps_0_bits_unconf, + output io_resps_1_valid, + output [2:0] io_resps_1_bits_ctr, + output io_resps_1_bits_u, + output io_resps_1_bits_unconf, + input [40:0] io_update_pc, + input [7:0] io_update_folded_hist_hist_14_folded_hist, + input [6:0] io_update_folded_hist_hist_7_folded_hist, + input io_update_mask_0, + input io_update_mask_1, + input io_update_takens_0, + input io_update_takens_1, + input io_update_alloc_0, + input io_update_alloc_1, + input [2:0] io_update_oldCtrs_0, + input [2:0] io_update_oldCtrs_1, + input io_update_uMask_0, + input io_update_uMask_1, + input io_update_us_0, + input io_update_us_1, + input io_update_reset_u_0, + input io_update_reset_u_1 +); + + wire per_bank_not_silent_update_3_1; + wire per_bank_not_silent_update_3_0; + wire per_bank_not_silent_update_2_1; + wire per_bank_not_silent_update_2_0; + wire per_bank_not_silent_update_1_1; + wire per_bank_not_silent_update_1_0; + wire per_bank_not_silent_update_0_1; + wire per_bank_not_silent_update_0_0; + reg powerOnResetState; + wire _resp_invalid_by_write_T_6; + wire _bank_wrbypasses_3_1_io_hit; + wire _bank_wrbypasses_3_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; + wire _bank_wrbypasses_3_0_io_hit; + wire _bank_wrbypasses_3_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; + wire _bank_wrbypasses_2_1_io_hit; + wire _bank_wrbypasses_2_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; + wire _bank_wrbypasses_2_0_io_hit; + wire _bank_wrbypasses_2_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; + wire _bank_wrbypasses_1_1_io_hit; + wire _bank_wrbypasses_1_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; + wire _bank_wrbypasses_1_0_io_hit; + wire _bank_wrbypasses_1_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; + wire _bank_wrbypasses_0_1_io_hit; + wire _bank_wrbypasses_0_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; + wire _bank_wrbypasses_0_0_io_hit; + wire _bank_wrbypasses_0_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; + wire _table_banks_3_io_r_req_ready; + wire _table_banks_3_io_r_resp_data_0_valid; + wire [7:0] _table_banks_3_io_r_resp_data_0_tag; + wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; + wire _table_banks_3_io_r_resp_data_1_valid; + wire [7:0] _table_banks_3_io_r_resp_data_1_tag; + wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; + wire _table_banks_2_io_r_req_ready; + wire _table_banks_2_io_r_resp_data_0_valid; + wire [7:0] _table_banks_2_io_r_resp_data_0_tag; + wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; + wire _table_banks_2_io_r_resp_data_1_valid; + wire [7:0] _table_banks_2_io_r_resp_data_1_tag; + wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; + wire _table_banks_1_io_r_req_ready; + wire _table_banks_1_io_r_resp_data_0_valid; + wire [7:0] _table_banks_1_io_r_resp_data_0_tag; + wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; + wire _table_banks_1_io_r_resp_data_1_valid; + wire [7:0] _table_banks_1_io_r_resp_data_1_tag; + wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; + wire _table_banks_0_io_r_req_ready; + wire _table_banks_0_io_r_resp_data_0_valid; + wire [7:0] _table_banks_0_io_r_resp_data_0_tag; + wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; + wire _table_banks_0_io_r_resp_data_1_valid; + wire [7:0] _table_banks_0_io_r_resp_data_1_tag; + wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; + wire _us_io_r_req_ready; + wire _us_io_r_resp_data_0; + wire _us_io_r_resp_data_1; + wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1; + wire [7:0] _GEN = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist; + wire s0_bank_req_1h_0 = _GEN[1:0] == 2'h0; + wire s0_bank_req_1h_1 = _GEN[1:0] == 2'h1; + wire s0_bank_req_1h_2 = _GEN[1:0] == 2'h2; + wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; + wire [8:0] _table_banks_3_io_r_req_bits_setIdx_T = {io_req_bits_pc[11:9], _GEN[7:2]}; + reg [39:0] s1_unhashed_idx; + reg [7:0] s1_tag; + reg s1_bank_req_1h_0; + reg s1_bank_req_1h_1; + reg s1_bank_req_1h_2; + reg s1_bank_req_1h_3; + reg s1_bank_has_write_on_this_req_0; + reg s1_bank_has_write_on_this_req_1; + reg s1_bank_has_write_on_this_req_2; + reg s1_bank_has_write_on_this_req_3; + wire [2:0] _resp_selected_T_6 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); + wire [2:0] _resp_selected_T_27 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); + wire _unconf_selected_T_6 = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); + wire _unconf_selected_T_13 = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); + wire _hit_selected_T_6 = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag + & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag + & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag + & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag + & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6; + wire _hit_selected_T_13 = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag + & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag + & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag + & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag + & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6; + assign _resp_invalid_by_write_T_6 = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2 + | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; + wire [7:0] _GEN_0 = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist; + wire [7:0] update_tag = _GEN_0 ^ {io_update_folded_hist_hist_7_folded_hist, 1'h0}; + wire update_req_bank_1h_0 = _GEN_0[1:0] == 2'h0; + wire update_req_bank_1h_1 = _GEN_0[1:0] == 2'h1; + wire update_req_bank_1h_2 = _GEN_0[1:0] == 2'h2; + wire [8:0] update_idx_in_bank = {io_update_pc[11:9], _GEN_0[7:2]}; + wire [1:0] per_bank_update_way_mask_0 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_0_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_0_0}; + wire [1:0] per_bank_update_way_mask_1 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_1_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_1_0}; + wire [1:0] per_bank_update_way_mask_2 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_2_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_2_0}; + wire [1:0] per_bank_update_way_mask_3 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_3_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_3_0}; + wire _s1_bank_has_write_on_this_req_WIRE_0 = + (|per_bank_update_way_mask_0) & update_req_bank_1h_0; + wire _s1_bank_has_write_on_this_req_WIRE_1 = + (|per_bank_update_way_mask_1) & update_req_bank_1h_1; + wire _s1_bank_has_write_on_this_req_WIRE_2 = + (|per_bank_update_way_mask_2) & update_req_bank_1h_2; + wire _s1_bank_has_write_on_this_req_WIRE_3 = + (|per_bank_update_way_mask_3) & (&(_GEN_0[1:0])); + wire [2:0] _wrbypass_io_T_6 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid = + (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit_data_0_valid); + wire _GEN_1 = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; + wire [2:0] _GEN_2 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; + wire _GEN_3 = (|_GEN_2) | _GEN_1; + wire _GEN_4 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; + wire [2:0] per_bank_update_wdata_0_0_ctr = + _GEN_4 + ? (_GEN_1 ? 3'h4 : 3'h3) + : wrbypass_data_valid + ? ((&_wrbypass_io_T_6) & _GEN_1 + ? 3'h7 + : _wrbypass_io_T_6 == 3'h0 & ~_GEN_1 + ? 3'h0 + : _GEN_1 ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1)) + : (&_GEN_2) & _GEN_1 + ? 3'h7 + : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_0_0 = + (wrbypass_data_valid + ? ~((&_wrbypass_io_T_6) & _GEN_1 | _wrbypass_io_T_6 == 3'h0 & ~_GEN_1) + : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; + wire [2:0] _wrbypass_io_T_28 = + (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); + wire wrbypass_data_valid_1 = + (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit_data_0_valid); + wire _GEN_5 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; + wire [2:0] _GEN_6 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; + wire _GEN_7 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; + wire [2:0] per_bank_update_wdata_0_1_ctr = + _GEN_7 + ? (_GEN_5 ? 3'h4 : 3'h3) + : wrbypass_data_valid_1 + ? ((&_wrbypass_io_T_28) & _GEN_5 + ? 3'h7 + : _wrbypass_io_T_28 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1)) + : (&_GEN_6) & _GEN_5 + ? 3'h7 + : _GEN_6 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); + assign per_bank_not_silent_update_0_1 = + (wrbypass_data_valid_1 + ? ~((&_wrbypass_io_T_28) & _GEN_5 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_5) + : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; + wire [2:0] _wrbypass_io_T_50 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid_2 = + (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_1_0_ctr = + _GEN_4 + ? (_GEN_1 ? 3'h4 : 3'h3) + : wrbypass_data_valid_2 + ? ((&_wrbypass_io_T_50) & _GEN_1 + ? 3'h7 + : _wrbypass_io_T_50 == 3'h0 & ~_GEN_1 + ? 3'h0 + : _GEN_1 ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1)) + : (&_GEN_2) & _GEN_1 + ? 3'h7 + : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_1_0 = + (wrbypass_data_valid_2 + ? ~((&_wrbypass_io_T_50) & _GEN_1 | _wrbypass_io_T_50 == 3'h0 & ~_GEN_1) + : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; + wire [2:0] _wrbypass_io_T_72 = + (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); + wire wrbypass_data_valid_3 = + (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_1_1_ctr = + _GEN_7 + ? (_GEN_5 ? 3'h4 : 3'h3) + : wrbypass_data_valid_3 + ? ((&_wrbypass_io_T_72) & _GEN_5 + ? 3'h7 + : _wrbypass_io_T_72 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1)) + : (&_GEN_6) & _GEN_5 + ? 3'h7 + : _GEN_6 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); + assign per_bank_not_silent_update_1_1 = + (wrbypass_data_valid_3 + ? ~((&_wrbypass_io_T_72) & _GEN_5 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_5) + : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; + wire [2:0] _wrbypass_io_T_94 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid_4 = + (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_2_0_ctr = + _GEN_4 + ? (_GEN_1 ? 3'h4 : 3'h3) + : wrbypass_data_valid_4 + ? ((&_wrbypass_io_T_94) & _GEN_1 + ? 3'h7 + : _wrbypass_io_T_94 == 3'h0 & ~_GEN_1 + ? 3'h0 + : _GEN_1 ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1)) + : (&_GEN_2) & _GEN_1 + ? 3'h7 + : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_2_0 = + (wrbypass_data_valid_4 + ? ~((&_wrbypass_io_T_94) & _GEN_1 | _wrbypass_io_T_94 == 3'h0 & ~_GEN_1) + : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; + wire [2:0] _wrbypass_io_T_116 = + (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); + wire wrbypass_data_valid_5 = + (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_2_1_ctr = + _GEN_7 + ? (_GEN_5 ? 3'h4 : 3'h3) + : wrbypass_data_valid_5 + ? ((&_wrbypass_io_T_116) & _GEN_5 + ? 3'h7 + : _wrbypass_io_T_116 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 + ? 3'(_wrbypass_io_T_116 + 3'h1) + : 3'(_wrbypass_io_T_116 - 3'h1)) + : (&_GEN_6) & _GEN_5 + ? 3'h7 + : _GEN_6 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); + assign per_bank_not_silent_update_2_1 = + (wrbypass_data_valid_5 + ? ~((&_wrbypass_io_T_116) & _GEN_5 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_5) + : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; + wire [2:0] _wrbypass_io_T_138 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid_6 = + (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_3_0_ctr = + _GEN_4 + ? (_GEN_1 ? 3'h4 : 3'h3) + : wrbypass_data_valid_6 + ? ((&_wrbypass_io_T_138) & _GEN_1 + ? 3'h7 + : _wrbypass_io_T_138 == 3'h0 & ~_GEN_1 + ? 3'h0 + : _GEN_1 + ? 3'(_wrbypass_io_T_138 + 3'h1) + : 3'(_wrbypass_io_T_138 - 3'h1)) + : (&_GEN_2) & _GEN_1 + ? 3'h7 + : _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_3_0 = + (wrbypass_data_valid_6 + ? ~((&_wrbypass_io_T_138) & _GEN_1 | _wrbypass_io_T_138 == 3'h0 & ~_GEN_1) + : ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4; + wire [2:0] _wrbypass_io_T_160 = + (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); + wire wrbypass_data_valid_7 = + (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_3_1_ctr = + _GEN_7 + ? (_GEN_5 ? 3'h4 : 3'h3) + : wrbypass_data_valid_7 + ? ((&_wrbypass_io_T_160) & _GEN_5 + ? 3'h7 + : _wrbypass_io_T_160 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 + ? 3'(_wrbypass_io_T_160 + 3'h1) + : 3'(_wrbypass_io_T_160 - 3'h1)) + : (&_GEN_6) & _GEN_5 + ? 3'h7 + : _GEN_6 == 3'h0 & ~_GEN_5 + ? 3'h0 + : _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1); + assign per_bank_not_silent_update_3_1 = + (wrbypass_data_valid_7 + ? ~((&_wrbypass_io_T_160) & _GEN_5 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_5) + : ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7; + always @(posedge clock) begin + if (_s1_bank_req_1h_T) begin + s1_unhashed_idx <= io_req_bits_pc[40:1]; + s1_tag <= _GEN ^ {io_req_bits_folded_hist_hist_7_folded_hist, 1'h0}; + s1_bank_req_1h_0 <= s0_bank_req_1h_0; + s1_bank_req_1h_1 <= s0_bank_req_1h_1; + s1_bank_req_1h_2 <= s0_bank_req_1h_2; + s1_bank_req_1h_3 <= &(_GEN[1:0]); + end + if (io_req_valid) begin + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; + s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; + s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; + end + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) + powerOnResetState <= 1'h1; + else + powerOnResetState <= + ~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready + & _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready + & _table_banks_3_io_r_req_ready) & powerOnResetState; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; + end + s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]}; + s1_tag = _RANDOM[2'h1][26:19]; + s1_bank_req_1h_0 = _RANDOM[2'h3][4]; + s1_bank_req_1h_1 = _RANDOM[2'h3][5]; + s1_bank_req_1h_2 = _RANDOM[2'h3][6]; + s1_bank_req_1h_3 = _RANDOM[2'h3][7]; + s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8]; + s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9]; + s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10]; + s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11]; + powerOnResetState = _RANDOM[2'h3][12]; + `endif // RANDOMIZE_REG_INIT + if (reset) + powerOnResetState = 1'h1; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FoldedSRAMTemplate us ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_us_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T), + .io_r_req_bits_setIdx ({io_req_bits_pc[11:9], _GEN}), + .io_r_resp_data_0 (_us_io_r_resp_data_0), + .io_r_resp_data_1 (_us_io_r_resp_data_1), + .io_w_req_valid + (_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)), + .io_w_req_bits_setIdx ({io_update_pc[11:9], _GEN_0}), + .io_w_req_bits_data_0 + (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), + .io_w_req_bits_data_1 + (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), + .io_w_req_bits_waymask + ({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1, + ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), + .extra_reset + ((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1) + ); + FoldedSRAMTemplate_1 table_banks_0 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_0_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), + .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), + .io_w_req_bits_setIdx (update_idx_in_bank), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_0) + ); + FoldedSRAMTemplate_1 table_banks_1 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_1_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), + .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), + .io_w_req_bits_setIdx (update_idx_in_bank), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_1) + ); + FoldedSRAMTemplate_1 table_banks_2 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_2_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), + .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), + .io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), + .io_w_req_bits_setIdx (update_idx_in_bank), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_2) + ); + FoldedSRAMTemplate_1 table_banks_3 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_3_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & (&(_GEN[1:0]))), + .io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T), + .io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), + .io_w_req_bits_setIdx (update_idx_in_bank), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_3) + ); + WrBypass bank_wrbypasses_0_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_0), + .io_write_idx (update_idx_in_bank), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_0_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_0_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_0), + .io_write_idx (update_idx_in_bank), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), + .io_hit (_bank_wrbypasses_0_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_1), + .io_write_idx (update_idx_in_bank), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_1_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_1), + .io_write_idx (update_idx_in_bank), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), + .io_hit (_bank_wrbypasses_1_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_2), + .io_write_idx (update_idx_in_bank), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_2_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_2), + .io_write_idx (update_idx_in_bank), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), + .io_hit (_bank_wrbypasses_2_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & (&(_GEN_0[1:0]))), + .io_write_idx (update_idx_in_bank), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_3_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & (&(_GEN_0[1:0]))), + .io_write_idx (update_idx_in_bank), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), + .io_hit (_bank_wrbypasses_3_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits) + ); + assign io_req_ready = ~powerOnResetState; + assign io_resps_0_valid = + ~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13; + assign io_resps_0_bits_ctr = + (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6) + | (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0); + assign io_resps_0_bits_u = + ~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0] + & _us_io_r_resp_data_1; + assign io_resps_0_bits_unconf = + ~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0] + & _unconf_selected_T_13; + assign io_resps_1_valid = + s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13; + assign io_resps_1_bits_ctr = + (s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0) + | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27); + assign io_resps_1_bits_u = + s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0]) + & _us_io_r_resp_data_1; + assign io_resps_1_bits_unconf = + s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0]) + & _unconf_selected_T_13; +endmodule + diff --git a/rtl/BPUTop/TageTable_1.sv b/rtl/BPUTop/TageTable_1.sv new file mode 100644 index 0000000..fe15fb3 --- /dev/null +++ b/rtl/BPUTop/TageTable_1.sv @@ -0,0 +1,754 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module TageTable_1( + input clock, + input reset, + output io_req_ready, + input io_req_valid, + input [40:0] io_req_bits_pc, + input [6:0] io_req_bits_folded_hist_hist_15_folded_hist, + input [7:0] io_req_bits_folded_hist_hist_4_folded_hist, + input [10:0] io_req_bits_folded_hist_hist_1_folded_hist, + output io_resps_0_valid, + output [2:0] io_resps_0_bits_ctr, + output io_resps_0_bits_u, + output io_resps_0_bits_unconf, + output io_resps_1_valid, + output [2:0] io_resps_1_bits_ctr, + output io_resps_1_bits_u, + output io_resps_1_bits_unconf, + input [40:0] io_update_pc, + input [6:0] io_update_folded_hist_hist_15_folded_hist, + input [7:0] io_update_folded_hist_hist_4_folded_hist, + input [10:0] io_update_folded_hist_hist_1_folded_hist, + input io_update_mask_0, + input io_update_mask_1, + input io_update_takens_0, + input io_update_takens_1, + input io_update_alloc_0, + input io_update_alloc_1, + input [2:0] io_update_oldCtrs_0, + input [2:0] io_update_oldCtrs_1, + input io_update_uMask_0, + input io_update_uMask_1, + input io_update_us_0, + input io_update_us_1, + input io_update_reset_u_0, + input io_update_reset_u_1 +); + + wire per_bank_not_silent_update_3_1; + wire per_bank_not_silent_update_3_0; + wire per_bank_not_silent_update_2_1; + wire per_bank_not_silent_update_2_0; + wire per_bank_not_silent_update_1_1; + wire per_bank_not_silent_update_1_0; + wire per_bank_not_silent_update_0_1; + wire per_bank_not_silent_update_0_0; + reg powerOnResetState; + wire _resp_invalid_by_write_T_6; + wire _bank_wrbypasses_3_1_io_hit; + wire _bank_wrbypasses_3_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; + wire _bank_wrbypasses_3_0_io_hit; + wire _bank_wrbypasses_3_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; + wire _bank_wrbypasses_2_1_io_hit; + wire _bank_wrbypasses_2_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; + wire _bank_wrbypasses_2_0_io_hit; + wire _bank_wrbypasses_2_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; + wire _bank_wrbypasses_1_1_io_hit; + wire _bank_wrbypasses_1_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; + wire _bank_wrbypasses_1_0_io_hit; + wire _bank_wrbypasses_1_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; + wire _bank_wrbypasses_0_1_io_hit; + wire _bank_wrbypasses_0_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; + wire _bank_wrbypasses_0_0_io_hit; + wire _bank_wrbypasses_0_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; + wire _table_banks_3_io_r_req_ready; + wire _table_banks_3_io_r_resp_data_0_valid; + wire [7:0] _table_banks_3_io_r_resp_data_0_tag; + wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; + wire _table_banks_3_io_r_resp_data_1_valid; + wire [7:0] _table_banks_3_io_r_resp_data_1_tag; + wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; + wire _table_banks_2_io_r_req_ready; + wire _table_banks_2_io_r_resp_data_0_valid; + wire [7:0] _table_banks_2_io_r_resp_data_0_tag; + wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; + wire _table_banks_2_io_r_resp_data_1_valid; + wire [7:0] _table_banks_2_io_r_resp_data_1_tag; + wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; + wire _table_banks_1_io_r_req_ready; + wire _table_banks_1_io_r_resp_data_0_valid; + wire [7:0] _table_banks_1_io_r_resp_data_0_tag; + wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; + wire _table_banks_1_io_r_resp_data_1_valid; + wire [7:0] _table_banks_1_io_r_resp_data_1_tag; + wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; + wire _table_banks_0_io_r_req_ready; + wire _table_banks_0_io_r_resp_data_0_valid; + wire [7:0] _table_banks_0_io_r_resp_data_0_tag; + wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; + wire _table_banks_0_io_r_resp_data_1_valid; + wire [7:0] _table_banks_0_io_r_resp_data_1_tag; + wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; + wire _us_io_r_req_ready; + wire _us_io_r_resp_data_0; + wire _us_io_r_resp_data_1; + wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1; + wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_1_folded_hist; + wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; + wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; + wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; + wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; + reg [39:0] s1_unhashed_idx; + reg [7:0] s1_tag; + reg s1_bank_req_1h_0; + reg s1_bank_req_1h_1; + reg s1_bank_req_1h_2; + reg s1_bank_req_1h_3; + reg s1_bank_has_write_on_this_req_0; + reg s1_bank_has_write_on_this_req_1; + reg s1_bank_has_write_on_this_req_2; + reg s1_bank_has_write_on_this_req_3; + wire [2:0] _resp_selected_T_6 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); + wire [2:0] _resp_selected_T_27 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); + wire _unconf_selected_T_6 = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); + wire _unconf_selected_T_13 = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); + wire _hit_selected_T_6 = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag + & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag + & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag + & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag + & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6; + wire _hit_selected_T_13 = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag + & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag + & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag + & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag + & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6; + assign _resp_invalid_by_write_T_6 = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2 + | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; + wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_1_folded_hist; + wire [7:0] update_tag = + io_update_pc[8:1] ^ io_update_folded_hist_hist_4_folded_hist + ^ {io_update_folded_hist_hist_15_folded_hist, 1'h0}; + wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; + wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; + wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; + wire [1:0] per_bank_update_way_mask_0 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_0_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_0_0}; + wire [1:0] per_bank_update_way_mask_1 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_1_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_1_0}; + wire [1:0] per_bank_update_way_mask_2 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_2_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_2_0}; + wire [1:0] per_bank_update_way_mask_3 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_3_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_3_0}; + wire _s1_bank_has_write_on_this_req_WIRE_0 = + (|per_bank_update_way_mask_0) & update_req_bank_1h_0; + wire _s1_bank_has_write_on_this_req_WIRE_1 = + (|per_bank_update_way_mask_1) & update_req_bank_1h_1; + wire _s1_bank_has_write_on_this_req_WIRE_2 = + (|per_bank_update_way_mask_2) & update_req_bank_1h_2; + wire _s1_bank_has_write_on_this_req_WIRE_3 = + (|per_bank_update_way_mask_3) & (&(update_idx[1:0])); + wire [2:0] _wrbypass_io_T_6 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid = + (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit_data_0_valid); + wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; + wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; + wire _GEN_1 = (|_GEN_0) | _GEN; + wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; + wire [2:0] per_bank_update_wdata_0_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid + ? ((&_wrbypass_io_T_6) & _GEN + ? 3'h7 + : _wrbypass_io_T_6 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_0_0 = + (wrbypass_data_valid + ? ~((&_wrbypass_io_T_6) & _GEN | _wrbypass_io_T_6 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; + wire [2:0] _wrbypass_io_T_28 = + (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); + wire wrbypass_data_valid_1 = + (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit_data_0_valid); + wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; + wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; + wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; + wire [2:0] per_bank_update_wdata_0_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_1 + ? ((&_wrbypass_io_T_28) & _GEN_3 + ? 3'h7 + : _wrbypass_io_T_28 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); + assign per_bank_not_silent_update_0_1 = + (wrbypass_data_valid_1 + ? ~((&_wrbypass_io_T_28) & _GEN_3 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; + wire [2:0] _wrbypass_io_T_50 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid_2 = + (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_1_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_2 + ? ((&_wrbypass_io_T_50) & _GEN + ? 3'h7 + : _wrbypass_io_T_50 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_1_0 = + (wrbypass_data_valid_2 + ? ~((&_wrbypass_io_T_50) & _GEN | _wrbypass_io_T_50 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; + wire [2:0] _wrbypass_io_T_72 = + (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); + wire wrbypass_data_valid_3 = + (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_1_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_3 + ? ((&_wrbypass_io_T_72) & _GEN_3 + ? 3'h7 + : _wrbypass_io_T_72 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); + assign per_bank_not_silent_update_1_1 = + (wrbypass_data_valid_3 + ? ~((&_wrbypass_io_T_72) & _GEN_3 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; + wire [2:0] _wrbypass_io_T_94 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid_4 = + (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_2_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_4 + ? ((&_wrbypass_io_T_94) & _GEN + ? 3'h7 + : _wrbypass_io_T_94 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_2_0 = + (wrbypass_data_valid_4 + ? ~((&_wrbypass_io_T_94) & _GEN | _wrbypass_io_T_94 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; + wire [2:0] _wrbypass_io_T_116 = + (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); + wire wrbypass_data_valid_5 = + (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_2_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_5 + ? ((&_wrbypass_io_T_116) & _GEN_3 + ? 3'h7 + : _wrbypass_io_T_116 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_T_116 + 3'h1) + : 3'(_wrbypass_io_T_116 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); + assign per_bank_not_silent_update_2_1 = + (wrbypass_data_valid_5 + ? ~((&_wrbypass_io_T_116) & _GEN_3 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; + wire [2:0] _wrbypass_io_T_138 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid_6 = + (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_3_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_6 + ? ((&_wrbypass_io_T_138) & _GEN + ? 3'h7 + : _wrbypass_io_T_138 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_3_0 = + (wrbypass_data_valid_6 + ? ~((&_wrbypass_io_T_138) & _GEN | _wrbypass_io_T_138 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; + wire [2:0] _wrbypass_io_T_160 = + (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); + wire wrbypass_data_valid_7 = + (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_3_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_7 + ? ((&_wrbypass_io_T_160) & _GEN_3 + ? 3'h7 + : _wrbypass_io_T_160 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_T_160 + 3'h1) + : 3'(_wrbypass_io_T_160 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); + assign per_bank_not_silent_update_3_1 = + (wrbypass_data_valid_7 + ? ~((&_wrbypass_io_T_160) & _GEN_3 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; + always @(posedge clock) begin + if (_s1_bank_req_1h_T) begin + s1_unhashed_idx <= io_req_bits_pc[40:1]; + s1_tag <= + io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_4_folded_hist + ^ {io_req_bits_folded_hist_hist_15_folded_hist, 1'h0}; + s1_bank_req_1h_0 <= s0_bank_req_1h_0; + s1_bank_req_1h_1 <= s0_bank_req_1h_1; + s1_bank_req_1h_2 <= s0_bank_req_1h_2; + s1_bank_req_1h_3 <= &(s0_idx[1:0]); + end + if (io_req_valid) begin + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; + s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; + s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; + end + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) + powerOnResetState <= 1'h1; + else + powerOnResetState <= + ~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready + & _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready + & _table_banks_3_io_r_req_ready) & powerOnResetState; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; + end + s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]}; + s1_tag = _RANDOM[2'h1][26:19]; + s1_bank_req_1h_0 = _RANDOM[2'h3][4]; + s1_bank_req_1h_1 = _RANDOM[2'h3][5]; + s1_bank_req_1h_2 = _RANDOM[2'h3][6]; + s1_bank_req_1h_3 = _RANDOM[2'h3][7]; + s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8]; + s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9]; + s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10]; + s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11]; + powerOnResetState = _RANDOM[2'h3][12]; + `endif // RANDOMIZE_REG_INIT + if (reset) + powerOnResetState = 1'h1; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FoldedSRAMTemplate us ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_us_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T), + .io_r_req_bits_setIdx (s0_idx), + .io_r_resp_data_0 (_us_io_r_resp_data_0), + .io_r_resp_data_1 (_us_io_r_resp_data_1), + .io_w_req_valid + (_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)), + .io_w_req_bits_setIdx (update_idx), + .io_w_req_bits_data_0 + (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), + .io_w_req_bits_data_1 + (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), + .io_w_req_bits_waymask + ({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1, + ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), + .extra_reset + ((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1) + ); + FoldedSRAMTemplate_1 table_banks_0 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_0_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), + .io_r_req_bits_setIdx (s0_idx[10:2]), + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), + .io_w_req_bits_setIdx (update_idx[10:2]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_0) + ); + FoldedSRAMTemplate_1 table_banks_1 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_1_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), + .io_r_req_bits_setIdx (s0_idx[10:2]), + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), + .io_w_req_bits_setIdx (update_idx[10:2]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_1) + ); + FoldedSRAMTemplate_1 table_banks_2 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_2_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), + .io_r_req_bits_setIdx (s0_idx[10:2]), + .io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), + .io_w_req_bits_setIdx (update_idx[10:2]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_2) + ); + FoldedSRAMTemplate_1 table_banks_3 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_3_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), + .io_r_req_bits_setIdx (s0_idx[10:2]), + .io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), + .io_w_req_bits_setIdx (update_idx[10:2]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_3) + ); + WrBypass bank_wrbypasses_0_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_0), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_0_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_0_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_0), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), + .io_hit (_bank_wrbypasses_0_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_1), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_1_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_1), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), + .io_hit (_bank_wrbypasses_1_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_2), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_2_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_2), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), + .io_hit (_bank_wrbypasses_2_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & (&(update_idx[1:0]))), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_3_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & (&(update_idx[1:0]))), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), + .io_hit (_bank_wrbypasses_3_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits) + ); + assign io_req_ready = ~powerOnResetState; + assign io_resps_0_valid = + ~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13; + assign io_resps_0_bits_ctr = + (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6) + | (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0); + assign io_resps_0_bits_u = + ~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0] + & _us_io_r_resp_data_1; + assign io_resps_0_bits_unconf = + ~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0] + & _unconf_selected_T_13; + assign io_resps_1_valid = + s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13; + assign io_resps_1_bits_ctr = + (s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0) + | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27); + assign io_resps_1_bits_u = + s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0]) + & _us_io_r_resp_data_1; + assign io_resps_1_bits_unconf = + s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0]) + & _unconf_selected_T_13; +endmodule + diff --git a/rtl/BPUTop/TageTable_2.sv b/rtl/BPUTop/TageTable_2.sv new file mode 100644 index 0000000..1a7e46b --- /dev/null +++ b/rtl/BPUTop/TageTable_2.sv @@ -0,0 +1,754 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module TageTable_2( + input clock, + input reset, + output io_req_ready, + input io_req_valid, + input [40:0] io_req_bits_pc, + input [10:0] io_req_bits_folded_hist_hist_17_folded_hist, + input [6:0] io_req_bits_folded_hist_hist_9_folded_hist, + input [7:0] io_req_bits_folded_hist_hist_3_folded_hist, + output io_resps_0_valid, + output [2:0] io_resps_0_bits_ctr, + output io_resps_0_bits_u, + output io_resps_0_bits_unconf, + output io_resps_1_valid, + output [2:0] io_resps_1_bits_ctr, + output io_resps_1_bits_u, + output io_resps_1_bits_unconf, + input [40:0] io_update_pc, + input [10:0] io_update_folded_hist_hist_17_folded_hist, + input [6:0] io_update_folded_hist_hist_9_folded_hist, + input [7:0] io_update_folded_hist_hist_3_folded_hist, + input io_update_mask_0, + input io_update_mask_1, + input io_update_takens_0, + input io_update_takens_1, + input io_update_alloc_0, + input io_update_alloc_1, + input [2:0] io_update_oldCtrs_0, + input [2:0] io_update_oldCtrs_1, + input io_update_uMask_0, + input io_update_uMask_1, + input io_update_us_0, + input io_update_us_1, + input io_update_reset_u_0, + input io_update_reset_u_1 +); + + wire per_bank_not_silent_update_3_1; + wire per_bank_not_silent_update_3_0; + wire per_bank_not_silent_update_2_1; + wire per_bank_not_silent_update_2_0; + wire per_bank_not_silent_update_1_1; + wire per_bank_not_silent_update_1_0; + wire per_bank_not_silent_update_0_1; + wire per_bank_not_silent_update_0_0; + reg powerOnResetState; + wire _resp_invalid_by_write_T_6; + wire _bank_wrbypasses_3_1_io_hit; + wire _bank_wrbypasses_3_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; + wire _bank_wrbypasses_3_0_io_hit; + wire _bank_wrbypasses_3_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; + wire _bank_wrbypasses_2_1_io_hit; + wire _bank_wrbypasses_2_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; + wire _bank_wrbypasses_2_0_io_hit; + wire _bank_wrbypasses_2_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; + wire _bank_wrbypasses_1_1_io_hit; + wire _bank_wrbypasses_1_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; + wire _bank_wrbypasses_1_0_io_hit; + wire _bank_wrbypasses_1_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; + wire _bank_wrbypasses_0_1_io_hit; + wire _bank_wrbypasses_0_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; + wire _bank_wrbypasses_0_0_io_hit; + wire _bank_wrbypasses_0_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; + wire _table_banks_3_io_r_req_ready; + wire _table_banks_3_io_r_resp_data_0_valid; + wire [7:0] _table_banks_3_io_r_resp_data_0_tag; + wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; + wire _table_banks_3_io_r_resp_data_1_valid; + wire [7:0] _table_banks_3_io_r_resp_data_1_tag; + wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; + wire _table_banks_2_io_r_req_ready; + wire _table_banks_2_io_r_resp_data_0_valid; + wire [7:0] _table_banks_2_io_r_resp_data_0_tag; + wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; + wire _table_banks_2_io_r_resp_data_1_valid; + wire [7:0] _table_banks_2_io_r_resp_data_1_tag; + wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; + wire _table_banks_1_io_r_req_ready; + wire _table_banks_1_io_r_resp_data_0_valid; + wire [7:0] _table_banks_1_io_r_resp_data_0_tag; + wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; + wire _table_banks_1_io_r_resp_data_1_valid; + wire [7:0] _table_banks_1_io_r_resp_data_1_tag; + wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; + wire _table_banks_0_io_r_req_ready; + wire _table_banks_0_io_r_resp_data_0_valid; + wire [7:0] _table_banks_0_io_r_resp_data_0_tag; + wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; + wire _table_banks_0_io_r_resp_data_1_valid; + wire [7:0] _table_banks_0_io_r_resp_data_1_tag; + wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; + wire _us_io_r_req_ready; + wire _us_io_r_resp_data_0; + wire _us_io_r_resp_data_1; + wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1; + wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_17_folded_hist; + wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; + wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; + wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; + wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; + reg [39:0] s1_unhashed_idx; + reg [7:0] s1_tag; + reg s1_bank_req_1h_0; + reg s1_bank_req_1h_1; + reg s1_bank_req_1h_2; + reg s1_bank_req_1h_3; + reg s1_bank_has_write_on_this_req_0; + reg s1_bank_has_write_on_this_req_1; + reg s1_bank_has_write_on_this_req_2; + reg s1_bank_has_write_on_this_req_3; + wire [2:0] _resp_selected_T_6 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); + wire [2:0] _resp_selected_T_27 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); + wire _unconf_selected_T_6 = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); + wire _unconf_selected_T_13 = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); + wire _hit_selected_T_6 = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag + & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag + & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag + & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag + & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6; + wire _hit_selected_T_13 = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag + & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag + & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag + & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag + & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6; + assign _resp_invalid_by_write_T_6 = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2 + | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; + wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_17_folded_hist; + wire [7:0] update_tag = + io_update_pc[8:1] ^ io_update_folded_hist_hist_3_folded_hist + ^ {io_update_folded_hist_hist_9_folded_hist, 1'h0}; + wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; + wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; + wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; + wire [1:0] per_bank_update_way_mask_0 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_0_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_0_0}; + wire [1:0] per_bank_update_way_mask_1 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_1_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_1_0}; + wire [1:0] per_bank_update_way_mask_2 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_2_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_2_0}; + wire [1:0] per_bank_update_way_mask_3 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_3_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_3_0}; + wire _s1_bank_has_write_on_this_req_WIRE_0 = + (|per_bank_update_way_mask_0) & update_req_bank_1h_0; + wire _s1_bank_has_write_on_this_req_WIRE_1 = + (|per_bank_update_way_mask_1) & update_req_bank_1h_1; + wire _s1_bank_has_write_on_this_req_WIRE_2 = + (|per_bank_update_way_mask_2) & update_req_bank_1h_2; + wire _s1_bank_has_write_on_this_req_WIRE_3 = + (|per_bank_update_way_mask_3) & (&(update_idx[1:0])); + wire [2:0] _wrbypass_io_T_6 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid = + (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit_data_0_valid); + wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; + wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; + wire _GEN_1 = (|_GEN_0) | _GEN; + wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; + wire [2:0] per_bank_update_wdata_0_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid + ? ((&_wrbypass_io_T_6) & _GEN + ? 3'h7 + : _wrbypass_io_T_6 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_0_0 = + (wrbypass_data_valid + ? ~((&_wrbypass_io_T_6) & _GEN | _wrbypass_io_T_6 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; + wire [2:0] _wrbypass_io_T_28 = + (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); + wire wrbypass_data_valid_1 = + (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit_data_0_valid); + wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; + wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; + wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; + wire [2:0] per_bank_update_wdata_0_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_1 + ? ((&_wrbypass_io_T_28) & _GEN_3 + ? 3'h7 + : _wrbypass_io_T_28 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); + assign per_bank_not_silent_update_0_1 = + (wrbypass_data_valid_1 + ? ~((&_wrbypass_io_T_28) & _GEN_3 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; + wire [2:0] _wrbypass_io_T_50 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid_2 = + (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_1_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_2 + ? ((&_wrbypass_io_T_50) & _GEN + ? 3'h7 + : _wrbypass_io_T_50 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_1_0 = + (wrbypass_data_valid_2 + ? ~((&_wrbypass_io_T_50) & _GEN | _wrbypass_io_T_50 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; + wire [2:0] _wrbypass_io_T_72 = + (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); + wire wrbypass_data_valid_3 = + (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_1_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_3 + ? ((&_wrbypass_io_T_72) & _GEN_3 + ? 3'h7 + : _wrbypass_io_T_72 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); + assign per_bank_not_silent_update_1_1 = + (wrbypass_data_valid_3 + ? ~((&_wrbypass_io_T_72) & _GEN_3 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; + wire [2:0] _wrbypass_io_T_94 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid_4 = + (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_2_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_4 + ? ((&_wrbypass_io_T_94) & _GEN + ? 3'h7 + : _wrbypass_io_T_94 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_2_0 = + (wrbypass_data_valid_4 + ? ~((&_wrbypass_io_T_94) & _GEN | _wrbypass_io_T_94 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; + wire [2:0] _wrbypass_io_T_116 = + (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); + wire wrbypass_data_valid_5 = + (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_2_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_5 + ? ((&_wrbypass_io_T_116) & _GEN_3 + ? 3'h7 + : _wrbypass_io_T_116 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_T_116 + 3'h1) + : 3'(_wrbypass_io_T_116 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); + assign per_bank_not_silent_update_2_1 = + (wrbypass_data_valid_5 + ? ~((&_wrbypass_io_T_116) & _GEN_3 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; + wire [2:0] _wrbypass_io_T_138 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid_6 = + (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_3_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_6 + ? ((&_wrbypass_io_T_138) & _GEN + ? 3'h7 + : _wrbypass_io_T_138 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_3_0 = + (wrbypass_data_valid_6 + ? ~((&_wrbypass_io_T_138) & _GEN | _wrbypass_io_T_138 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; + wire [2:0] _wrbypass_io_T_160 = + (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); + wire wrbypass_data_valid_7 = + (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_3_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_7 + ? ((&_wrbypass_io_T_160) & _GEN_3 + ? 3'h7 + : _wrbypass_io_T_160 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_T_160 + 3'h1) + : 3'(_wrbypass_io_T_160 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); + assign per_bank_not_silent_update_3_1 = + (wrbypass_data_valid_7 + ? ~((&_wrbypass_io_T_160) & _GEN_3 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; + always @(posedge clock) begin + if (_s1_bank_req_1h_T) begin + s1_unhashed_idx <= io_req_bits_pc[40:1]; + s1_tag <= + io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_3_folded_hist + ^ {io_req_bits_folded_hist_hist_9_folded_hist, 1'h0}; + s1_bank_req_1h_0 <= s0_bank_req_1h_0; + s1_bank_req_1h_1 <= s0_bank_req_1h_1; + s1_bank_req_1h_2 <= s0_bank_req_1h_2; + s1_bank_req_1h_3 <= &(s0_idx[1:0]); + end + if (io_req_valid) begin + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; + s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; + s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; + end + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) + powerOnResetState <= 1'h1; + else + powerOnResetState <= + ~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready + & _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready + & _table_banks_3_io_r_req_ready) & powerOnResetState; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; + end + s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]}; + s1_tag = _RANDOM[2'h1][26:19]; + s1_bank_req_1h_0 = _RANDOM[2'h3][4]; + s1_bank_req_1h_1 = _RANDOM[2'h3][5]; + s1_bank_req_1h_2 = _RANDOM[2'h3][6]; + s1_bank_req_1h_3 = _RANDOM[2'h3][7]; + s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8]; + s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9]; + s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10]; + s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11]; + powerOnResetState = _RANDOM[2'h3][12]; + `endif // RANDOMIZE_REG_INIT + if (reset) + powerOnResetState = 1'h1; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FoldedSRAMTemplate us ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_us_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T), + .io_r_req_bits_setIdx (s0_idx), + .io_r_resp_data_0 (_us_io_r_resp_data_0), + .io_r_resp_data_1 (_us_io_r_resp_data_1), + .io_w_req_valid + (_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)), + .io_w_req_bits_setIdx (update_idx), + .io_w_req_bits_data_0 + (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), + .io_w_req_bits_data_1 + (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), + .io_w_req_bits_waymask + ({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1, + ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), + .extra_reset + ((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1) + ); + FoldedSRAMTemplate_1 table_banks_0 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_0_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), + .io_r_req_bits_setIdx (s0_idx[10:2]), + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), + .io_w_req_bits_setIdx (update_idx[10:2]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_0) + ); + FoldedSRAMTemplate_1 table_banks_1 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_1_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), + .io_r_req_bits_setIdx (s0_idx[10:2]), + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), + .io_w_req_bits_setIdx (update_idx[10:2]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_1) + ); + FoldedSRAMTemplate_1 table_banks_2 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_2_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), + .io_r_req_bits_setIdx (s0_idx[10:2]), + .io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), + .io_w_req_bits_setIdx (update_idx[10:2]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_2) + ); + FoldedSRAMTemplate_1 table_banks_3 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_3_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), + .io_r_req_bits_setIdx (s0_idx[10:2]), + .io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), + .io_w_req_bits_setIdx (update_idx[10:2]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_3) + ); + WrBypass bank_wrbypasses_0_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_0), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_0_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_0_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_0), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), + .io_hit (_bank_wrbypasses_0_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_1), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_1_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_1), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), + .io_hit (_bank_wrbypasses_1_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_2), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_2_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_2), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), + .io_hit (_bank_wrbypasses_2_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & (&(update_idx[1:0]))), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_3_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & (&(update_idx[1:0]))), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), + .io_hit (_bank_wrbypasses_3_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits) + ); + assign io_req_ready = ~powerOnResetState; + assign io_resps_0_valid = + ~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13; + assign io_resps_0_bits_ctr = + (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6) + | (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0); + assign io_resps_0_bits_u = + ~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0] + & _us_io_r_resp_data_1; + assign io_resps_0_bits_unconf = + ~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0] + & _unconf_selected_T_13; + assign io_resps_1_valid = + s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13; + assign io_resps_1_bits_ctr = + (s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0) + | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27); + assign io_resps_1_bits_u = + s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0]) + & _us_io_r_resp_data_1; + assign io_resps_1_bits_unconf = + s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0]) + & _unconf_selected_T_13; +endmodule + diff --git a/rtl/BPUTop/TageTable_3.sv b/rtl/BPUTop/TageTable_3.sv new file mode 100644 index 0000000..8ec61db --- /dev/null +++ b/rtl/BPUTop/TageTable_3.sv @@ -0,0 +1,754 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module TageTable_3( + input clock, + input reset, + output io_req_ready, + input io_req_valid, + input [40:0] io_req_bits_pc, + input [10:0] io_req_bits_folded_hist_hist_16_folded_hist, + input [7:0] io_req_bits_folded_hist_hist_8_folded_hist, + input [6:0] io_req_bits_folded_hist_hist_5_folded_hist, + output io_resps_0_valid, + output [2:0] io_resps_0_bits_ctr, + output io_resps_0_bits_u, + output io_resps_0_bits_unconf, + output io_resps_1_valid, + output [2:0] io_resps_1_bits_ctr, + output io_resps_1_bits_u, + output io_resps_1_bits_unconf, + input [40:0] io_update_pc, + input [10:0] io_update_folded_hist_hist_16_folded_hist, + input [7:0] io_update_folded_hist_hist_8_folded_hist, + input [6:0] io_update_folded_hist_hist_5_folded_hist, + input io_update_mask_0, + input io_update_mask_1, + input io_update_takens_0, + input io_update_takens_1, + input io_update_alloc_0, + input io_update_alloc_1, + input [2:0] io_update_oldCtrs_0, + input [2:0] io_update_oldCtrs_1, + input io_update_uMask_0, + input io_update_uMask_1, + input io_update_us_0, + input io_update_us_1, + input io_update_reset_u_0, + input io_update_reset_u_1 +); + + wire per_bank_not_silent_update_3_1; + wire per_bank_not_silent_update_3_0; + wire per_bank_not_silent_update_2_1; + wire per_bank_not_silent_update_2_0; + wire per_bank_not_silent_update_1_1; + wire per_bank_not_silent_update_1_0; + wire per_bank_not_silent_update_0_1; + wire per_bank_not_silent_update_0_0; + reg powerOnResetState; + wire _resp_invalid_by_write_T_6; + wire _bank_wrbypasses_3_1_io_hit; + wire _bank_wrbypasses_3_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits; + wire _bank_wrbypasses_3_0_io_hit; + wire _bank_wrbypasses_3_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits; + wire _bank_wrbypasses_2_1_io_hit; + wire _bank_wrbypasses_2_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits; + wire _bank_wrbypasses_2_0_io_hit; + wire _bank_wrbypasses_2_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits; + wire _bank_wrbypasses_1_1_io_hit; + wire _bank_wrbypasses_1_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits; + wire _bank_wrbypasses_1_0_io_hit; + wire _bank_wrbypasses_1_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits; + wire _bank_wrbypasses_0_1_io_hit; + wire _bank_wrbypasses_0_1_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits; + wire _bank_wrbypasses_0_0_io_hit; + wire _bank_wrbypasses_0_0_io_hit_data_0_valid; + wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits; + wire _table_banks_3_io_r_req_ready; + wire _table_banks_3_io_r_resp_data_0_valid; + wire [7:0] _table_banks_3_io_r_resp_data_0_tag; + wire [2:0] _table_banks_3_io_r_resp_data_0_ctr; + wire _table_banks_3_io_r_resp_data_1_valid; + wire [7:0] _table_banks_3_io_r_resp_data_1_tag; + wire [2:0] _table_banks_3_io_r_resp_data_1_ctr; + wire _table_banks_2_io_r_req_ready; + wire _table_banks_2_io_r_resp_data_0_valid; + wire [7:0] _table_banks_2_io_r_resp_data_0_tag; + wire [2:0] _table_banks_2_io_r_resp_data_0_ctr; + wire _table_banks_2_io_r_resp_data_1_valid; + wire [7:0] _table_banks_2_io_r_resp_data_1_tag; + wire [2:0] _table_banks_2_io_r_resp_data_1_ctr; + wire _table_banks_1_io_r_req_ready; + wire _table_banks_1_io_r_resp_data_0_valid; + wire [7:0] _table_banks_1_io_r_resp_data_0_tag; + wire [2:0] _table_banks_1_io_r_resp_data_0_ctr; + wire _table_banks_1_io_r_resp_data_1_valid; + wire [7:0] _table_banks_1_io_r_resp_data_1_tag; + wire [2:0] _table_banks_1_io_r_resp_data_1_ctr; + wire _table_banks_0_io_r_req_ready; + wire _table_banks_0_io_r_resp_data_0_valid; + wire [7:0] _table_banks_0_io_r_resp_data_0_tag; + wire [2:0] _table_banks_0_io_r_resp_data_0_ctr; + wire _table_banks_0_io_r_resp_data_1_valid; + wire [7:0] _table_banks_0_io_r_resp_data_1_tag; + wire [2:0] _table_banks_0_io_r_resp_data_1_ctr; + wire _us_io_r_req_ready; + wire _us_io_r_resp_data_0; + wire _us_io_r_resp_data_1; + wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1; + wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_16_folded_hist; + wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0; + wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1; + wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2; + wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid; + reg [39:0] s1_unhashed_idx; + reg [7:0] s1_tag; + reg s1_bank_req_1h_0; + reg s1_bank_req_1h_1; + reg s1_bank_req_1h_2; + reg s1_bank_req_1h_3; + reg s1_bank_has_write_on_this_req_0; + reg s1_bank_has_write_on_this_req_1; + reg s1_bank_has_write_on_this_req_2; + reg s1_bank_has_write_on_this_req_3; + wire [2:0] _resp_selected_T_6 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0); + wire [2:0] _resp_selected_T_27 = + (s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0) + | (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0); + wire _unconf_selected_T_6 = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_0_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_0_ctr == 3'h3); + wire _unconf_selected_T_13 = + s1_bank_req_1h_0 + & (_table_banks_0_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1 + & (_table_banks_1_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2 + & (_table_banks_2_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3 + & (_table_banks_3_io_r_resp_data_1_ctr == 3'h4 + | _table_banks_3_io_r_resp_data_1_ctr == 3'h3); + wire _hit_selected_T_6 = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag + & _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag + & _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag + & _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag + & _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6; + wire _hit_selected_T_13 = + s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag + & _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag + & _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag + & _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6 + | s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag + & _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6; + assign _resp_invalid_by_write_T_6 = + s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1 + & s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2 + | s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3; + wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_16_folded_hist; + wire [7:0] update_tag = + io_update_pc[8:1] ^ io_update_folded_hist_hist_8_folded_hist + ^ {io_update_folded_hist_hist_5_folded_hist, 1'h0}; + wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0; + wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1; + wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2; + wire [1:0] per_bank_update_way_mask_0 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_0_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_0_0}; + wire [1:0] per_bank_update_way_mask_1 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_1_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_1_0}; + wire [1:0] per_bank_update_way_mask_2 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_2_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_2_0}; + wire [1:0] per_bank_update_way_mask_3 = + {(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1) + & per_bank_not_silent_update_3_1, + (~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1) + & per_bank_not_silent_update_3_0}; + wire _s1_bank_has_write_on_this_req_WIRE_0 = + (|per_bank_update_way_mask_0) & update_req_bank_1h_0; + wire _s1_bank_has_write_on_this_req_WIRE_1 = + (|per_bank_update_way_mask_1) & update_req_bank_1h_1; + wire _s1_bank_has_write_on_this_req_WIRE_2 = + (|per_bank_update_way_mask_2) & update_req_bank_1h_2; + wire _s1_bank_has_write_on_this_req_WIRE_3 = + (|per_bank_update_way_mask_3) & (&(update_idx[1:0])); + wire [2:0] _wrbypass_io_T_6 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid = + (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_0_1_io_hit_data_0_valid); + wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0; + wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0; + wire _GEN_1 = (|_GEN_0) | _GEN; + wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0; + wire [2:0] per_bank_update_wdata_0_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid + ? ((&_wrbypass_io_T_6) & _GEN + ? 3'h7 + : _wrbypass_io_T_6 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_0_0 = + (wrbypass_data_valid + ? ~((&_wrbypass_io_T_6) & _GEN | _wrbypass_io_T_6 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; + wire [2:0] _wrbypass_io_T_28 = + (io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits); + wire wrbypass_data_valid_1 = + (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_0_1_io_hit_data_0_valid); + wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1; + wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1; + wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1; + wire [2:0] per_bank_update_wdata_0_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_1 + ? ((&_wrbypass_io_T_28) & _GEN_3 + ? 3'h7 + : _wrbypass_io_T_28 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); + assign per_bank_not_silent_update_0_1 = + (wrbypass_data_valid_1 + ? ~((&_wrbypass_io_T_28) & _GEN_3 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; + wire [2:0] _wrbypass_io_T_50 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid_2 = + (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_1_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_1_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_2 + ? ((&_wrbypass_io_T_50) & _GEN + ? 3'h7 + : _wrbypass_io_T_50 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_1_0 = + (wrbypass_data_valid_2 + ? ~((&_wrbypass_io_T_50) & _GEN | _wrbypass_io_T_50 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; + wire [2:0] _wrbypass_io_T_72 = + (io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits); + wire wrbypass_data_valid_3 = + (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_1_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_1_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_3 + ? ((&_wrbypass_io_T_72) & _GEN_3 + ? 3'h7 + : _wrbypass_io_T_72 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); + assign per_bank_not_silent_update_1_1 = + (wrbypass_data_valid_3 + ? ~((&_wrbypass_io_T_72) & _GEN_3 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; + wire [2:0] _wrbypass_io_T_94 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid_4 = + (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_2_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_2_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_4 + ? ((&_wrbypass_io_T_94) & _GEN + ? 3'h7 + : _wrbypass_io_T_94 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_2_0 = + (wrbypass_data_valid_4 + ? ~((&_wrbypass_io_T_94) & _GEN | _wrbypass_io_T_94 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; + wire [2:0] _wrbypass_io_T_116 = + (io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits); + wire wrbypass_data_valid_5 = + (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_2_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_2_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_5 + ? ((&_wrbypass_io_T_116) & _GEN_3 + ? 3'h7 + : _wrbypass_io_T_116 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_T_116 + 3'h1) + : 3'(_wrbypass_io_T_116 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); + assign per_bank_not_silent_update_2_1 = + (wrbypass_data_valid_5 + ? ~((&_wrbypass_io_T_116) & _GEN_3 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; + wire [2:0] _wrbypass_io_T_138 = + (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits) + | (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0); + wire wrbypass_data_valid_6 = + (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit) + & (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1] + & _bank_wrbypasses_3_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_3_0_ctr = + _GEN_2 + ? (_GEN ? 3'h4 : 3'h3) + : wrbypass_data_valid_6 + ? ((&_wrbypass_io_T_138) & _GEN + ? 3'h7 + : _wrbypass_io_T_138 == 3'h0 & ~_GEN + ? 3'h0 + : _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1)) + : (&_GEN_0) & _GEN + ? 3'h7 + : _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0; + assign per_bank_not_silent_update_3_0 = + (wrbypass_data_valid_6 + ? ~((&_wrbypass_io_T_138) & _GEN | _wrbypass_io_T_138 == 3'h0 & ~_GEN) + : ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2; + wire [2:0] _wrbypass_io_T_160 = + (io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0) + | (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits); + wire wrbypass_data_valid_7 = + (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit) + & (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1]) + & _bank_wrbypasses_3_1_io_hit_data_0_valid); + wire [2:0] per_bank_update_wdata_3_1_ctr = + _GEN_5 + ? (_GEN_3 ? 3'h4 : 3'h3) + : wrbypass_data_valid_7 + ? ((&_wrbypass_io_T_160) & _GEN_3 + ? 3'h7 + : _wrbypass_io_T_160 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 + ? 3'(_wrbypass_io_T_160 + 3'h1) + : 3'(_wrbypass_io_T_160 - 3'h1)) + : (&_GEN_4) & _GEN_3 + ? 3'h7 + : _GEN_4 == 3'h0 & ~_GEN_3 + ? 3'h0 + : _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1); + assign per_bank_not_silent_update_3_1 = + (wrbypass_data_valid_7 + ? ~((&_wrbypass_io_T_160) & _GEN_3 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_3) + : ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5; + always @(posedge clock) begin + if (_s1_bank_req_1h_T) begin + s1_unhashed_idx <= io_req_bits_pc[40:1]; + s1_tag <= + io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_8_folded_hist + ^ {io_req_bits_folded_hist_hist_5_folded_hist, 1'h0}; + s1_bank_req_1h_0 <= s0_bank_req_1h_0; + s1_bank_req_1h_1 <= s0_bank_req_1h_1; + s1_bank_req_1h_2 <= s0_bank_req_1h_2; + s1_bank_req_1h_3 <= &(s0_idx[1:0]); + end + if (io_req_valid) begin + s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0; + s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1; + s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2; + s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3; + end + end // always @(posedge) + always @(posedge clock or posedge reset) begin + if (reset) + powerOnResetState <= 1'h1; + else + powerOnResetState <= + ~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready + & _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready + & _table_banks_3_io_r_req_ready) & powerOnResetState; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; + end + s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]}; + s1_tag = _RANDOM[2'h1][26:19]; + s1_bank_req_1h_0 = _RANDOM[2'h3][4]; + s1_bank_req_1h_1 = _RANDOM[2'h3][5]; + s1_bank_req_1h_2 = _RANDOM[2'h3][6]; + s1_bank_req_1h_3 = _RANDOM[2'h3][7]; + s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8]; + s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9]; + s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10]; + s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11]; + powerOnResetState = _RANDOM[2'h3][12]; + `endif // RANDOMIZE_REG_INIT + if (reset) + powerOnResetState = 1'h1; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FoldedSRAMTemplate us ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_us_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T), + .io_r_req_bits_setIdx (s0_idx), + .io_r_resp_data_0 (_us_io_r_resp_data_0), + .io_r_resp_data_1 (_us_io_r_resp_data_1), + .io_w_req_valid + (_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)), + .io_w_req_bits_setIdx (update_idx), + .io_w_req_bits_data_0 + (~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1), + .io_w_req_bits_data_1 + (io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1), + .io_w_req_bits_waymask + ({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1, + ~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}), + .extra_reset + ((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1) + ); + FoldedSRAMTemplate_1 table_banks_0 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_0_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0), + .io_r_req_bits_setIdx (s0_idx[10:2]), + .io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0), + .io_w_req_bits_setIdx (update_idx[10:2]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_0) + ); + FoldedSRAMTemplate_1 table_banks_1 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_1_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1), + .io_r_req_bits_setIdx (s0_idx[10:2]), + .io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1), + .io_w_req_bits_setIdx (update_idx[10:2]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_1) + ); + FoldedSRAMTemplate_1 table_banks_2 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_2_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2), + .io_r_req_bits_setIdx (s0_idx[10:2]), + .io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2), + .io_w_req_bits_setIdx (update_idx[10:2]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_2) + ); + FoldedSRAMTemplate_1 table_banks_3 ( + .clock (clock), + .reset (reset), + .io_r_req_ready (_table_banks_3_io_r_req_ready), + .io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))), + .io_r_req_bits_setIdx (s0_idx[10:2]), + .io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid), + .io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag), + .io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr), + .io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid), + .io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag), + .io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr), + .io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3), + .io_w_req_bits_setIdx (update_idx[10:2]), + .io_w_req_bits_data_0_tag (update_tag), + .io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr), + .io_w_req_bits_data_1_tag (update_tag), + .io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr), + .io_w_req_bits_waymask (per_bank_update_way_mask_3) + ); + WrBypass bank_wrbypasses_0_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_0), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_0_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_0_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_0), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)), + .io_hit (_bank_wrbypasses_0_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_1), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_1_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_1_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_1), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)), + .io_hit (_bank_wrbypasses_1_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & update_req_bank_1h_2), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_2_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_2_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & update_req_bank_1h_2), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)), + .io_hit (_bank_wrbypasses_2_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_0 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_0 & (&(update_idx[1:0]))), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr) + | (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)), + .io_hit (_bank_wrbypasses_3_0_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits) + ); + WrBypass bank_wrbypasses_3_1 ( + .clock (clock), + .reset (reset), + .io_wen (io_update_mask_1 & (&(update_idx[1:0]))), + .io_write_idx (update_idx[10:2]), + .io_write_data_0 + ((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0) + | (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)), + .io_hit (_bank_wrbypasses_3_1_io_hit), + .io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid), + .io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits) + ); + assign io_req_ready = ~powerOnResetState; + assign io_resps_0_valid = + ~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13; + assign io_resps_0_bits_ctr = + (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6) + | (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0); + assign io_resps_0_bits_u = + ~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0] + & _us_io_r_resp_data_1; + assign io_resps_0_bits_unconf = + ~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0] + & _unconf_selected_T_13; + assign io_resps_1_valid = + s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13; + assign io_resps_1_bits_ctr = + (s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0) + | (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27); + assign io_resps_1_bits_u = + s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0]) + & _us_io_r_resp_data_1; + assign io_resps_1_bits_unconf = + s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0]) + & _unconf_selected_T_13; +endmodule + diff --git a/rtl/BPUTop/Tage_SC.sv b/rtl/BPUTop/Tage_SC.sv new file mode 100644 index 0000000..b8a4750 --- /dev/null +++ b/rtl/BPUTop/Tage_SC.sv @@ -0,0 +1,5910 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module Tage_SC( + input clock, + input reset, + input [35:0] io_reset_vector, + input [40:0] io_in_bits_s0_pc_0, + input [40:0] io_in_bits_s0_pc_1, + input [40:0] io_in_bits_s0_pc_3, + input [10:0] io_in_bits_folded_hist_1_hist_17_folded_hist, + input [10:0] io_in_bits_folded_hist_1_hist_16_folded_hist, + input [6:0] io_in_bits_folded_hist_1_hist_15_folded_hist, + input [7:0] io_in_bits_folded_hist_1_hist_14_folded_hist, + input [6:0] io_in_bits_folded_hist_1_hist_9_folded_hist, + input [7:0] io_in_bits_folded_hist_1_hist_8_folded_hist, + input [6:0] io_in_bits_folded_hist_1_hist_7_folded_hist, + input [6:0] io_in_bits_folded_hist_1_hist_5_folded_hist, + input [7:0] io_in_bits_folded_hist_1_hist_4_folded_hist, + input [7:0] io_in_bits_folded_hist_1_hist_3_folded_hist, + input [10:0] io_in_bits_folded_hist_1_hist_1_folded_hist, + input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, + input [7:0] io_in_bits_folded_hist_3_hist_11_folded_hist, + input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, + output io_out_s2_full_pred_0_br_taken_mask_0, + output io_out_s2_full_pred_0_br_taken_mask_1, + output io_out_s2_full_pred_1_br_taken_mask_0, + output io_out_s2_full_pred_1_br_taken_mask_1, + output io_out_s2_full_pred_2_br_taken_mask_0, + output io_out_s2_full_pred_2_br_taken_mask_1, + output io_out_s2_full_pred_3_br_taken_mask_0, + output io_out_s2_full_pred_3_br_taken_mask_1, + output io_out_s3_full_pred_0_br_taken_mask_0, + output io_out_s3_full_pred_0_br_taken_mask_1, + output io_out_s3_full_pred_1_br_taken_mask_0, + output io_out_s3_full_pred_1_br_taken_mask_1, + output io_out_s3_full_pred_2_br_taken_mask_0, + output io_out_s3_full_pred_2_br_taken_mask_1, + output io_out_s3_full_pred_3_br_taken_mask_0, + output io_out_s3_full_pred_3_br_taken_mask_1, + output [222:0] io_out_last_stage_meta, + input io_ctrl_tage_enable, + input io_ctrl_sc_enable, + input io_s0_fire_0, + input io_s0_fire_1, + input io_s0_fire_3, + input io_s1_fire_0, + input io_s1_fire_1, + input io_s1_fire_2, + input io_s1_fire_3, + input io_s2_fire_0, + input io_s2_fire_1, + input io_s2_fire_2, + input io_s2_fire_3, + output io_s1_ready, + input io_update_valid, + input [40:0] io_update_bits_pc, + input [10:0] io_update_bits_spec_info_folded_hist_hist_17_folded_hist, + input [10:0] io_update_bits_spec_info_folded_hist_hist_16_folded_hist, + input [6:0] io_update_bits_spec_info_folded_hist_hist_15_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, + input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_11_folded_hist, + input [6:0] io_update_bits_spec_info_folded_hist_hist_9_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_8_folded_hist, + input [6:0] io_update_bits_spec_info_folded_hist_hist_7_folded_hist, + input [6:0] io_update_bits_spec_info_folded_hist_hist_5_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, + input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, + input [10:0] io_update_bits_spec_info_folded_hist_hist_1_folded_hist, + input io_update_bits_ftb_entry_brSlots_0_valid, + input io_update_bits_ftb_entry_tailSlot_sharing, + input io_update_bits_ftb_entry_tailSlot_valid, + input io_update_bits_ftb_entry_always_taken_0, + input io_update_bits_ftb_entry_always_taken_1, + input io_update_bits_br_taken_mask_0, + input io_update_bits_br_taken_mask_1, + input io_update_bits_mispred_mask_0, + input io_update_bits_mispred_mask_1, + input [222:0] io_update_bits_meta, + output [5:0] io_perf_0_value, + output [5:0] io_perf_1_value, + output [5:0] io_perf_2_value +); + + reg [5:0] r_3_3; + reg [5:0] r_3_2; + reg [5:0] r_3_1; + reg [5:0] r_3_0; + reg resp_meta_scMeta_scPreds_1_r; + reg resp_meta_scMeta_scUsed_1_r; + reg resp_meta_scMeta_tageTakens_1_r; + reg [5:0] r_2_3; + reg [5:0] r_2_2; + reg [5:0] r_2_1; + reg [5:0] r_2_0; + reg resp_meta_scMeta_scPreds_0_r; + reg resp_meta_scMeta_scUsed_0_r; + reg resp_meta_scMeta_tageTakens_0_r; + reg [1:0] resp_meta_basecnts_1_r; + reg resp_meta_takens_1_r; + reg resp_meta_altDiffers_1_r; + reg resp_meta_altUsed_1_r; + reg [3:0] resp_meta_allocates_1_r; + reg resp_meta_providerResps_1_r_unconf; + reg resp_meta_providerResps_1_r_u; + reg [2:0] resp_meta_providerResps_1_r_ctr; + reg [1:0] resp_meta_providers_1_bits_r; + reg resp_meta_providers_1_valid_r; + reg [1:0] resp_meta_basecnts_0_r; + reg resp_meta_takens_0_r; + reg resp_meta_altDiffers_0_r; + reg resp_meta_altUsed_0_r; + reg [3:0] resp_meta_allocates_0_r; + reg resp_meta_providerResps_0_r_unconf; + reg resp_meta_providerResps_0_r_u; + reg [2:0] resp_meta_providerResps_0_r_ctr; + reg [1:0] resp_meta_providers_0_bits_r; + reg resp_meta_providers_0_valid_r; + wire [5:0] _scTables_3_io_resp_ctrs_0_0; + wire [5:0] _scTables_3_io_resp_ctrs_0_1; + wire [5:0] _scTables_3_io_resp_ctrs_1_0; + wire [5:0] _scTables_3_io_resp_ctrs_1_1; + wire [5:0] _scTables_2_io_resp_ctrs_0_0; + wire [5:0] _scTables_2_io_resp_ctrs_0_1; + wire [5:0] _scTables_2_io_resp_ctrs_1_0; + wire [5:0] _scTables_2_io_resp_ctrs_1_1; + wire [5:0] _scTables_1_io_resp_ctrs_0_0; + wire [5:0] _scTables_1_io_resp_ctrs_0_1; + wire [5:0] _scTables_1_io_resp_ctrs_1_0; + wire [5:0] _scTables_1_io_resp_ctrs_1_1; + wire [5:0] _scTables_0_io_resp_ctrs_0_0; + wire [5:0] _scTables_0_io_resp_ctrs_0_1; + wire [5:0] _scTables_0_io_resp_ctrs_1_0; + wire [5:0] _scTables_0_io_resp_ctrs_1_1; + wire _bt_io_req_ready; + wire [1:0] _bt_io_s1_cnt_0; + wire [1:0] _bt_io_s1_cnt_1; + wire _tables_3_io_req_ready; + wire _tables_3_io_resps_0_valid; + wire [2:0] _tables_3_io_resps_0_bits_ctr; + wire _tables_3_io_resps_0_bits_u; + wire _tables_3_io_resps_0_bits_unconf; + wire _tables_3_io_resps_1_valid; + wire [2:0] _tables_3_io_resps_1_bits_ctr; + wire _tables_3_io_resps_1_bits_u; + wire _tables_3_io_resps_1_bits_unconf; + wire _tables_2_io_req_ready; + wire _tables_2_io_resps_0_valid; + wire [2:0] _tables_2_io_resps_0_bits_ctr; + wire _tables_2_io_resps_0_bits_u; + wire _tables_2_io_resps_0_bits_unconf; + wire _tables_2_io_resps_1_valid; + wire [2:0] _tables_2_io_resps_1_bits_ctr; + wire _tables_2_io_resps_1_bits_u; + wire _tables_2_io_resps_1_bits_unconf; + wire _tables_1_io_req_ready; + wire _tables_1_io_resps_0_valid; + wire [2:0] _tables_1_io_resps_0_bits_ctr; + wire _tables_1_io_resps_0_bits_u; + wire _tables_1_io_resps_0_bits_unconf; + wire _tables_1_io_resps_1_valid; + wire [2:0] _tables_1_io_resps_1_bits_ctr; + wire _tables_1_io_resps_1_bits_u; + wire _tables_1_io_resps_1_bits_unconf; + wire _tables_0_io_req_ready; + wire _tables_0_io_resps_0_valid; + wire [2:0] _tables_0_io_resps_0_bits_ctr; + wire _tables_0_io_resps_0_bits_u; + wire _tables_0_io_resps_0_bits_unconf; + wire _tables_0_io_resps_1_valid; + wire [2:0] _tables_0_io_resps_1_bits_ctr; + wire _tables_0_io_resps_1_bits_u; + wire _tables_0_io_resps_1_bits_unconf; + wire [35:0] _reset_vector_delay_io_out; + reg [40:0] s1_pc_dup_0; + reg REG; + reg REG_1; + reg [6:0] bankTickCtrDistanceToTops_0; + reg [6:0] bankTickCtrDistanceToTops_1; + reg [6:0] bankTickCtrs_0; + reg [6:0] bankTickCtrs_1; + reg [3:0] useAltOnNaCtrs_0_0; + reg [3:0] useAltOnNaCtrs_0_1; + reg [3:0] useAltOnNaCtrs_0_2; + reg [3:0] useAltOnNaCtrs_0_3; + reg [3:0] useAltOnNaCtrs_0_4; + reg [3:0] useAltOnNaCtrs_0_5; + reg [3:0] useAltOnNaCtrs_0_6; + reg [3:0] useAltOnNaCtrs_0_7; + reg [3:0] useAltOnNaCtrs_0_8; + reg [3:0] useAltOnNaCtrs_0_9; + reg [3:0] useAltOnNaCtrs_0_10; + reg [3:0] useAltOnNaCtrs_0_11; + reg [3:0] useAltOnNaCtrs_0_12; + reg [3:0] useAltOnNaCtrs_0_13; + reg [3:0] useAltOnNaCtrs_0_14; + reg [3:0] useAltOnNaCtrs_0_15; + reg [3:0] useAltOnNaCtrs_0_16; + reg [3:0] useAltOnNaCtrs_0_17; + reg [3:0] useAltOnNaCtrs_0_18; + reg [3:0] useAltOnNaCtrs_0_19; + reg [3:0] useAltOnNaCtrs_0_20; + reg [3:0] useAltOnNaCtrs_0_21; + reg [3:0] useAltOnNaCtrs_0_22; + reg [3:0] useAltOnNaCtrs_0_23; + reg [3:0] useAltOnNaCtrs_0_24; + reg [3:0] useAltOnNaCtrs_0_25; + reg [3:0] useAltOnNaCtrs_0_26; + reg [3:0] useAltOnNaCtrs_0_27; + reg [3:0] useAltOnNaCtrs_0_28; + reg [3:0] useAltOnNaCtrs_0_29; + reg [3:0] useAltOnNaCtrs_0_30; + reg [3:0] useAltOnNaCtrs_0_31; + reg [3:0] useAltOnNaCtrs_0_32; + reg [3:0] useAltOnNaCtrs_0_33; + reg [3:0] useAltOnNaCtrs_0_34; + reg [3:0] useAltOnNaCtrs_0_35; + reg [3:0] useAltOnNaCtrs_0_36; + reg [3:0] useAltOnNaCtrs_0_37; + reg [3:0] useAltOnNaCtrs_0_38; + reg [3:0] useAltOnNaCtrs_0_39; + reg [3:0] useAltOnNaCtrs_0_40; + reg [3:0] useAltOnNaCtrs_0_41; + reg [3:0] useAltOnNaCtrs_0_42; + reg [3:0] useAltOnNaCtrs_0_43; + reg [3:0] useAltOnNaCtrs_0_44; + reg [3:0] useAltOnNaCtrs_0_45; + reg [3:0] useAltOnNaCtrs_0_46; + reg [3:0] useAltOnNaCtrs_0_47; + reg [3:0] useAltOnNaCtrs_0_48; + reg [3:0] useAltOnNaCtrs_0_49; + reg [3:0] useAltOnNaCtrs_0_50; + reg [3:0] useAltOnNaCtrs_0_51; + reg [3:0] useAltOnNaCtrs_0_52; + reg [3:0] useAltOnNaCtrs_0_53; + reg [3:0] useAltOnNaCtrs_0_54; + reg [3:0] useAltOnNaCtrs_0_55; + reg [3:0] useAltOnNaCtrs_0_56; + reg [3:0] useAltOnNaCtrs_0_57; + reg [3:0] useAltOnNaCtrs_0_58; + reg [3:0] useAltOnNaCtrs_0_59; + reg [3:0] useAltOnNaCtrs_0_60; + reg [3:0] useAltOnNaCtrs_0_61; + reg [3:0] useAltOnNaCtrs_0_62; + reg [3:0] useAltOnNaCtrs_0_63; + reg [3:0] useAltOnNaCtrs_0_64; + reg [3:0] useAltOnNaCtrs_0_65; + reg [3:0] useAltOnNaCtrs_0_66; + reg [3:0] useAltOnNaCtrs_0_67; + reg [3:0] useAltOnNaCtrs_0_68; + reg [3:0] useAltOnNaCtrs_0_69; + reg [3:0] useAltOnNaCtrs_0_70; + reg [3:0] useAltOnNaCtrs_0_71; + reg [3:0] useAltOnNaCtrs_0_72; + reg [3:0] useAltOnNaCtrs_0_73; + reg [3:0] useAltOnNaCtrs_0_74; + reg [3:0] useAltOnNaCtrs_0_75; + reg [3:0] useAltOnNaCtrs_0_76; + reg [3:0] useAltOnNaCtrs_0_77; + reg [3:0] useAltOnNaCtrs_0_78; + reg [3:0] useAltOnNaCtrs_0_79; + reg [3:0] useAltOnNaCtrs_0_80; + reg [3:0] useAltOnNaCtrs_0_81; + reg [3:0] useAltOnNaCtrs_0_82; + reg [3:0] useAltOnNaCtrs_0_83; + reg [3:0] useAltOnNaCtrs_0_84; + reg [3:0] useAltOnNaCtrs_0_85; + reg [3:0] useAltOnNaCtrs_0_86; + reg [3:0] useAltOnNaCtrs_0_87; + reg [3:0] useAltOnNaCtrs_0_88; + reg [3:0] useAltOnNaCtrs_0_89; + reg [3:0] useAltOnNaCtrs_0_90; + reg [3:0] useAltOnNaCtrs_0_91; + reg [3:0] useAltOnNaCtrs_0_92; + reg [3:0] useAltOnNaCtrs_0_93; + reg [3:0] useAltOnNaCtrs_0_94; + reg [3:0] useAltOnNaCtrs_0_95; + reg [3:0] useAltOnNaCtrs_0_96; + reg [3:0] useAltOnNaCtrs_0_97; + reg [3:0] useAltOnNaCtrs_0_98; + reg [3:0] useAltOnNaCtrs_0_99; + reg [3:0] useAltOnNaCtrs_0_100; + reg [3:0] useAltOnNaCtrs_0_101; + reg [3:0] useAltOnNaCtrs_0_102; + reg [3:0] useAltOnNaCtrs_0_103; + reg [3:0] useAltOnNaCtrs_0_104; + reg [3:0] useAltOnNaCtrs_0_105; + reg [3:0] useAltOnNaCtrs_0_106; + reg [3:0] useAltOnNaCtrs_0_107; + reg [3:0] useAltOnNaCtrs_0_108; + reg [3:0] useAltOnNaCtrs_0_109; + reg [3:0] useAltOnNaCtrs_0_110; + reg [3:0] useAltOnNaCtrs_0_111; + reg [3:0] useAltOnNaCtrs_0_112; + reg [3:0] useAltOnNaCtrs_0_113; + reg [3:0] useAltOnNaCtrs_0_114; + reg [3:0] useAltOnNaCtrs_0_115; + reg [3:0] useAltOnNaCtrs_0_116; + reg [3:0] useAltOnNaCtrs_0_117; + reg [3:0] useAltOnNaCtrs_0_118; + reg [3:0] useAltOnNaCtrs_0_119; + reg [3:0] useAltOnNaCtrs_0_120; + reg [3:0] useAltOnNaCtrs_0_121; + reg [3:0] useAltOnNaCtrs_0_122; + reg [3:0] useAltOnNaCtrs_0_123; + reg [3:0] useAltOnNaCtrs_0_124; + reg [3:0] useAltOnNaCtrs_0_125; + reg [3:0] useAltOnNaCtrs_0_126; + reg [3:0] useAltOnNaCtrs_0_127; + reg [3:0] useAltOnNaCtrs_1_0; + reg [3:0] useAltOnNaCtrs_1_1; + reg [3:0] useAltOnNaCtrs_1_2; + reg [3:0] useAltOnNaCtrs_1_3; + reg [3:0] useAltOnNaCtrs_1_4; + reg [3:0] useAltOnNaCtrs_1_5; + reg [3:0] useAltOnNaCtrs_1_6; + reg [3:0] useAltOnNaCtrs_1_7; + reg [3:0] useAltOnNaCtrs_1_8; + reg [3:0] useAltOnNaCtrs_1_9; + reg [3:0] useAltOnNaCtrs_1_10; + reg [3:0] useAltOnNaCtrs_1_11; + reg [3:0] useAltOnNaCtrs_1_12; + reg [3:0] useAltOnNaCtrs_1_13; + reg [3:0] useAltOnNaCtrs_1_14; + reg [3:0] useAltOnNaCtrs_1_15; + reg [3:0] useAltOnNaCtrs_1_16; + reg [3:0] useAltOnNaCtrs_1_17; + reg [3:0] useAltOnNaCtrs_1_18; + reg [3:0] useAltOnNaCtrs_1_19; + reg [3:0] useAltOnNaCtrs_1_20; + reg [3:0] useAltOnNaCtrs_1_21; + reg [3:0] useAltOnNaCtrs_1_22; + reg [3:0] useAltOnNaCtrs_1_23; + reg [3:0] useAltOnNaCtrs_1_24; + reg [3:0] useAltOnNaCtrs_1_25; + reg [3:0] useAltOnNaCtrs_1_26; + reg [3:0] useAltOnNaCtrs_1_27; + reg [3:0] useAltOnNaCtrs_1_28; + reg [3:0] useAltOnNaCtrs_1_29; + reg [3:0] useAltOnNaCtrs_1_30; + reg [3:0] useAltOnNaCtrs_1_31; + reg [3:0] useAltOnNaCtrs_1_32; + reg [3:0] useAltOnNaCtrs_1_33; + reg [3:0] useAltOnNaCtrs_1_34; + reg [3:0] useAltOnNaCtrs_1_35; + reg [3:0] useAltOnNaCtrs_1_36; + reg [3:0] useAltOnNaCtrs_1_37; + reg [3:0] useAltOnNaCtrs_1_38; + reg [3:0] useAltOnNaCtrs_1_39; + reg [3:0] useAltOnNaCtrs_1_40; + reg [3:0] useAltOnNaCtrs_1_41; + reg [3:0] useAltOnNaCtrs_1_42; + reg [3:0] useAltOnNaCtrs_1_43; + reg [3:0] useAltOnNaCtrs_1_44; + reg [3:0] useAltOnNaCtrs_1_45; + reg [3:0] useAltOnNaCtrs_1_46; + reg [3:0] useAltOnNaCtrs_1_47; + reg [3:0] useAltOnNaCtrs_1_48; + reg [3:0] useAltOnNaCtrs_1_49; + reg [3:0] useAltOnNaCtrs_1_50; + reg [3:0] useAltOnNaCtrs_1_51; + reg [3:0] useAltOnNaCtrs_1_52; + reg [3:0] useAltOnNaCtrs_1_53; + reg [3:0] useAltOnNaCtrs_1_54; + reg [3:0] useAltOnNaCtrs_1_55; + reg [3:0] useAltOnNaCtrs_1_56; + reg [3:0] useAltOnNaCtrs_1_57; + reg [3:0] useAltOnNaCtrs_1_58; + reg [3:0] useAltOnNaCtrs_1_59; + reg [3:0] useAltOnNaCtrs_1_60; + reg [3:0] useAltOnNaCtrs_1_61; + reg [3:0] useAltOnNaCtrs_1_62; + reg [3:0] useAltOnNaCtrs_1_63; + reg [3:0] useAltOnNaCtrs_1_64; + reg [3:0] useAltOnNaCtrs_1_65; + reg [3:0] useAltOnNaCtrs_1_66; + reg [3:0] useAltOnNaCtrs_1_67; + reg [3:0] useAltOnNaCtrs_1_68; + reg [3:0] useAltOnNaCtrs_1_69; + reg [3:0] useAltOnNaCtrs_1_70; + reg [3:0] useAltOnNaCtrs_1_71; + reg [3:0] useAltOnNaCtrs_1_72; + reg [3:0] useAltOnNaCtrs_1_73; + reg [3:0] useAltOnNaCtrs_1_74; + reg [3:0] useAltOnNaCtrs_1_75; + reg [3:0] useAltOnNaCtrs_1_76; + reg [3:0] useAltOnNaCtrs_1_77; + reg [3:0] useAltOnNaCtrs_1_78; + reg [3:0] useAltOnNaCtrs_1_79; + reg [3:0] useAltOnNaCtrs_1_80; + reg [3:0] useAltOnNaCtrs_1_81; + reg [3:0] useAltOnNaCtrs_1_82; + reg [3:0] useAltOnNaCtrs_1_83; + reg [3:0] useAltOnNaCtrs_1_84; + reg [3:0] useAltOnNaCtrs_1_85; + reg [3:0] useAltOnNaCtrs_1_86; + reg [3:0] useAltOnNaCtrs_1_87; + reg [3:0] useAltOnNaCtrs_1_88; + reg [3:0] useAltOnNaCtrs_1_89; + reg [3:0] useAltOnNaCtrs_1_90; + reg [3:0] useAltOnNaCtrs_1_91; + reg [3:0] useAltOnNaCtrs_1_92; + reg [3:0] useAltOnNaCtrs_1_93; + reg [3:0] useAltOnNaCtrs_1_94; + reg [3:0] useAltOnNaCtrs_1_95; + reg [3:0] useAltOnNaCtrs_1_96; + reg [3:0] useAltOnNaCtrs_1_97; + reg [3:0] useAltOnNaCtrs_1_98; + reg [3:0] useAltOnNaCtrs_1_99; + reg [3:0] useAltOnNaCtrs_1_100; + reg [3:0] useAltOnNaCtrs_1_101; + reg [3:0] useAltOnNaCtrs_1_102; + reg [3:0] useAltOnNaCtrs_1_103; + reg [3:0] useAltOnNaCtrs_1_104; + reg [3:0] useAltOnNaCtrs_1_105; + reg [3:0] useAltOnNaCtrs_1_106; + reg [3:0] useAltOnNaCtrs_1_107; + reg [3:0] useAltOnNaCtrs_1_108; + reg [3:0] useAltOnNaCtrs_1_109; + reg [3:0] useAltOnNaCtrs_1_110; + reg [3:0] useAltOnNaCtrs_1_111; + reg [3:0] useAltOnNaCtrs_1_112; + reg [3:0] useAltOnNaCtrs_1_113; + reg [3:0] useAltOnNaCtrs_1_114; + reg [3:0] useAltOnNaCtrs_1_115; + reg [3:0] useAltOnNaCtrs_1_116; + reg [3:0] useAltOnNaCtrs_1_117; + reg [3:0] useAltOnNaCtrs_1_118; + reg [3:0] useAltOnNaCtrs_1_119; + reg [3:0] useAltOnNaCtrs_1_120; + reg [3:0] useAltOnNaCtrs_1_121; + reg [3:0] useAltOnNaCtrs_1_122; + reg [3:0] useAltOnNaCtrs_1_123; + reg [3:0] useAltOnNaCtrs_1_124; + reg [3:0] useAltOnNaCtrs_1_125; + reg [3:0] useAltOnNaCtrs_1_126; + reg [3:0] useAltOnNaCtrs_1_127; + reg s2_provideds_0; + reg s2_provideds_1; + reg [1:0] s2_providers_0; + reg [1:0] s2_providers_1; + reg [2:0] s2_providerResps_0_ctr; + reg s2_providerResps_0_u; + reg s2_providerResps_0_unconf; + reg [2:0] s2_providerResps_1_ctr; + reg s2_providerResps_1_u; + reg s2_providerResps_1_unconf; + reg s2_altUsed_0; + reg s2_altUsed_1; + reg s2_tageTakens_dup_0_0; + reg s2_tageTakens_dup_0_1; + reg s2_tageTakens_dup_1_0; + reg s2_tageTakens_dup_1_1; + reg s2_tageTakens_dup_2_0; + reg s2_tageTakens_dup_2_1; + reg s2_tageTakens_dup_3_0; + reg s2_tageTakens_dup_3_1; + reg s2_finalAltPreds_0; + reg s2_finalAltPreds_1; + reg [1:0] s2_basecnts_0; + reg [1:0] s2_basecnts_1; + wire updateValids_0 = + io_update_bits_ftb_entry_brSlots_0_valid & io_update_valid + & ~io_update_bits_ftb_entry_always_taken_0; + wire updateValids_1 = + io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_tailSlot_sharing + & io_update_valid & ~io_update_bits_ftb_entry_always_taken_1 + & ~io_update_bits_br_taken_mask_0; + reg [3:0] allocatableSlots; + reg tage_enable_dup_REG; + wire updateTaken = updateValids_0 & io_update_bits_br_taken_mask_0; + wire updateProviderCorrect = io_update_bits_meta[76] == updateTaken; + wire needToAllocate = + updateValids_0 & io_update_bits_mispred_mask_0 + & ~(io_update_bits_meta[70] & updateProviderCorrect & io_update_bits_meta[84]); + reg [63:0] allocLFSR_lfsr; + wire [3:0] _longerHistoryTableMask_T_1 = 4'h1 << io_update_bits_meta[83:82]; + wire [2:0] _GEN = _longerHistoryTableMask_T_1[2:0] | _longerHistoryTableMask_T_1[3:1]; + wire [3:0] longerHistoryTableMask = + ~({&(io_update_bits_meta[83:82]), + _GEN[2], + _GEN[1] | (&(io_update_bits_meta[83:82])), + _GEN[0] | io_update_bits_meta[83:82] == 2'h2 | (&(io_update_bits_meta[83:82]))} + & {4{io_update_bits_meta[84]}}); + wire _firstEntry_T = io_update_bits_meta[56] & longerHistoryTableMask[0]; + wire _firstEntry_T_1 = io_update_bits_meta[57] & longerHistoryTableMask[1]; + wire _firstEntry_T_2 = io_update_bits_meta[58] & longerHistoryTableMask[2]; + reg [3:0] allocatableSlots_1; + reg tage_enable_dup_REG_1; + wire updateTaken_1 = updateValids_1 & io_update_bits_br_taken_mask_1; + wire updateProviderCorrect_1 = io_update_bits_meta[81] == updateTaken_1; + wire needToAllocate_1 = + updateValids_1 & io_update_bits_mispred_mask_1 + & ~(io_update_bits_meta[71] & updateProviderCorrect_1 & io_update_bits_meta[87]); + reg [63:0] allocLFSR_lfsr_1; + wire [3:0] _longerHistoryTableMask_T_11 = 4'h1 << io_update_bits_meta[86:85]; + wire [2:0] _GEN_0 = + _longerHistoryTableMask_T_11[2:0] | _longerHistoryTableMask_T_11[3:1]; + wire [3:0] longerHistoryTableMask_1 = + ~({&(io_update_bits_meta[86:85]), + _GEN_0[2], + _GEN_0[1] | (&(io_update_bits_meta[86:85])), + _GEN_0[0] | io_update_bits_meta[86:85] == 2'h2 | (&(io_update_bits_meta[86:85]))} + & {4{io_update_bits_meta[87]}}); + wire _firstEntry_T_6 = io_update_bits_meta[60] & longerHistoryTableMask_1[0]; + wire _firstEntry_T_7 = io_update_bits_meta[61] & longerHistoryTableMask_1[1]; + wire _firstEntry_T_8 = io_update_bits_meta[62] & longerHistoryTableMask_1[2]; + reg tables_0_io_update_reset_u_0_REG; + reg tables_0_io_update_mask_0_REG; + reg tables_0_io_update_takens_0_r; + reg tables_0_io_update_alloc_0_r; + reg [2:0] tables_0_io_update_oldCtrs_0_r; + reg tables_0_io_update_uMask_0_r; + reg tables_0_io_update_us_0_r; + reg tables_1_io_update_reset_u_0_REG; + reg tables_1_io_update_mask_0_REG; + reg tables_1_io_update_takens_0_r; + reg tables_1_io_update_alloc_0_r; + reg [2:0] tables_1_io_update_oldCtrs_0_r; + reg tables_1_io_update_uMask_0_r; + reg tables_1_io_update_us_0_r; + reg tables_2_io_update_reset_u_0_REG; + reg tables_2_io_update_mask_0_REG; + reg tables_2_io_update_takens_0_r; + reg tables_2_io_update_alloc_0_r; + reg [2:0] tables_2_io_update_oldCtrs_0_r; + reg tables_2_io_update_uMask_0_r; + reg tables_2_io_update_us_0_r; + reg tables_3_io_update_reset_u_0_REG; + reg tables_3_io_update_mask_0_REG; + reg tables_3_io_update_takens_0_r; + reg tables_3_io_update_alloc_0_r; + reg [2:0] tables_3_io_update_oldCtrs_0_r; + reg tables_3_io_update_uMask_0_r; + reg tables_3_io_update_us_0_r; + reg tables_0_io_update_reset_u_1_REG; + reg tables_0_io_update_mask_1_REG; + reg tables_0_io_update_takens_1_r; + reg tables_0_io_update_alloc_1_r; + reg [2:0] tables_0_io_update_oldCtrs_1_r; + reg tables_0_io_update_uMask_1_r; + reg tables_0_io_update_us_1_r; + reg [40:0] tables_0_io_update_pc_r_1; + reg [7:0] tables_0_io_update_folded_hist_r_1_hist_14_folded_hist; + reg [6:0] tables_0_io_update_folded_hist_r_1_hist_7_folded_hist; + reg tables_1_io_update_reset_u_1_REG; + reg tables_1_io_update_mask_1_REG; + reg tables_1_io_update_takens_1_r; + reg tables_1_io_update_alloc_1_r; + reg [2:0] tables_1_io_update_oldCtrs_1_r; + reg tables_1_io_update_uMask_1_r; + reg tables_1_io_update_us_1_r; + reg [40:0] tables_1_io_update_pc_r_1; + reg [6:0] tables_1_io_update_folded_hist_r_1_hist_15_folded_hist; + reg [7:0] tables_1_io_update_folded_hist_r_1_hist_4_folded_hist; + reg [10:0] tables_1_io_update_folded_hist_r_1_hist_1_folded_hist; + reg tables_2_io_update_reset_u_1_REG; + reg tables_2_io_update_mask_1_REG; + reg tables_2_io_update_takens_1_r; + reg tables_2_io_update_alloc_1_r; + reg [2:0] tables_2_io_update_oldCtrs_1_r; + reg tables_2_io_update_uMask_1_r; + reg tables_2_io_update_us_1_r; + reg [40:0] tables_2_io_update_pc_r_1; + reg [10:0] tables_2_io_update_folded_hist_r_1_hist_17_folded_hist; + reg [6:0] tables_2_io_update_folded_hist_r_1_hist_9_folded_hist; + reg [7:0] tables_2_io_update_folded_hist_r_1_hist_3_folded_hist; + reg tables_3_io_update_reset_u_1_REG; + reg tables_3_io_update_mask_1_REG; + reg tables_3_io_update_takens_1_r; + reg tables_3_io_update_alloc_1_r; + reg [2:0] tables_3_io_update_oldCtrs_1_r; + reg tables_3_io_update_uMask_1_r; + reg tables_3_io_update_us_1_r; + reg [40:0] tables_3_io_update_pc_r_1; + reg [10:0] tables_3_io_update_folded_hist_r_1_hist_16_folded_hist; + reg [7:0] tables_3_io_update_folded_hist_r_1_hist_8_folded_hist; + reg [6:0] tables_3_io_update_folded_hist_r_1_hist_5_folded_hist; + reg REG_2_0; + reg REG_2_1; + reg [1:0] r_0; + reg [1:0] r_1; + reg [40:0] bt_io_update_pc_r; + reg r_1_0; + reg r_1_1; + reg [4:0] scThresholds_0_ctr; + reg [7:0] scThresholds_0_thres; + reg [4:0] scThresholds_1_ctr; + reg [7:0] scThresholds_1_thres; + reg [8:0] s2_scTableSums_0; + reg [8:0] s2_scTableSums_1; + reg [2:0] s2_tagePrvdCtrCentered_r; + reg [5:0] s2_scResps_r_0_ctrs_0_0; + reg [5:0] s2_scResps_r_0_ctrs_0_1; + reg [5:0] s2_scResps_r_1_ctrs_0_0; + reg [5:0] s2_scResps_r_1_ctrs_0_1; + reg [5:0] s2_scResps_r_2_ctrs_0_0; + reg [5:0] s2_scResps_r_2_ctrs_0_1; + reg [5:0] s2_scResps_r_3_ctrs_0_0; + reg [5:0] s2_scResps_r_3_ctrs_0_1; + reg s3_pred_dup_0; + reg s3_pred_dup_1; + reg s3_pred_dup_2; + reg s3_pred_dup_3; + reg sc_enable_dup_REG; + wire _GEN_1 = updateValids_0 & io_update_bits_meta[50]; + wire [7:0] _sum_T_8 = + 8'({io_update_bits_meta[5], io_update_bits_meta[5:0], 1'h1} + + {io_update_bits_meta[11], io_update_bits_meta[11:6], 1'h1}); + wire [7:0] _sum_T_9 = + 8'({io_update_bits_meta[17], io_update_bits_meta[17:12], 1'h1} + + {io_update_bits_meta[23], io_update_bits_meta[23:18], 1'h1}); + wire [8:0] _sum_T_10 = 9'({_sum_T_8[7], _sum_T_8} + {_sum_T_9[7], _sum_T_9}); + wire [2:0] _sumAboveThreshold_T = io_update_bits_meta[76:74] ^ 3'h4; + wire [9:0] sum = + 10'({_sum_T_10[8], _sum_T_10} + + {{3{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8}); + wire _update_on_mispred_0_T = + io_update_bits_meta[48] != io_update_bits_br_taken_mask_0; + reg [8:0] s2_scTableSums_1_0; + reg [8:0] s2_scTableSums_1_1; + reg [2:0] s2_tagePrvdCtrCentered_r_1; + reg [5:0] s2_scResps_r_1_0_ctrs_1_0; + reg [5:0] s2_scResps_r_1_0_ctrs_1_1; + reg [5:0] s2_scResps_r_1_1_ctrs_1_0; + reg [5:0] s2_scResps_r_1_1_ctrs_1_1; + reg [5:0] s2_scResps_r_1_2_ctrs_1_0; + reg [5:0] s2_scResps_r_1_2_ctrs_1_1; + reg [5:0] s2_scResps_r_1_3_ctrs_1_0; + reg [5:0] s2_scResps_r_1_3_ctrs_1_1; + reg s3_pred_dup_0_1; + reg s3_pred_dup_1_1; + reg s3_pred_dup_2_1; + reg s3_pred_dup_3_1; + reg sc_enable_dup_REG_1; + wire _GEN_2 = updateValids_1 & io_update_bits_meta[51]; + wire [7:0] _sum_T_22 = + 8'({io_update_bits_meta[29], io_update_bits_meta[29:24], 1'h1} + + {io_update_bits_meta[35], io_update_bits_meta[35:30], 1'h1}); + wire [7:0] _sum_T_23 = + 8'({io_update_bits_meta[41], io_update_bits_meta[41:36], 1'h1} + + {io_update_bits_meta[47], io_update_bits_meta[47:42], 1'h1}); + wire [8:0] _sum_T_24 = 9'({_sum_T_22[7], _sum_T_22} + {_sum_T_23[7], _sum_T_23}); + wire [2:0] _sumAboveThreshold_T_19 = io_update_bits_meta[81:79] ^ 3'h4; + wire [9:0] sum_1 = + 10'({_sum_T_24[8], _sum_T_24} + + {{3{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8}); + wire _update_on_mispred_1_T = + io_update_bits_meta[49] != io_update_bits_br_taken_mask_1; + reg scTables_0_io_update_mask_0_REG; + reg scTables_0_io_update_tagePreds_0_r; + reg scTables_0_io_update_takens_0_r; + reg [5:0] scTables_0_io_update_oldCtrs_0_r; + reg scTables_1_io_update_mask_0_REG; + reg scTables_1_io_update_tagePreds_0_r; + reg scTables_1_io_update_takens_0_r; + reg [5:0] scTables_1_io_update_oldCtrs_0_r; + reg scTables_2_io_update_mask_0_REG; + reg scTables_2_io_update_tagePreds_0_r; + reg scTables_2_io_update_takens_0_r; + reg [5:0] scTables_2_io_update_oldCtrs_0_r; + reg scTables_3_io_update_mask_0_REG; + reg scTables_3_io_update_tagePreds_0_r; + reg scTables_3_io_update_takens_0_r; + reg [5:0] scTables_3_io_update_oldCtrs_0_r; + reg scTables_0_io_update_mask_1_REG; + reg scTables_0_io_update_tagePreds_1_r; + reg scTables_0_io_update_takens_1_r; + reg [5:0] scTables_0_io_update_oldCtrs_1_r; + reg [40:0] scTables_0_io_update_pc_r_1; + reg scTables_1_io_update_mask_1_REG; + reg scTables_1_io_update_tagePreds_1_r; + reg scTables_1_io_update_takens_1_r; + reg [5:0] scTables_1_io_update_oldCtrs_1_r; + reg [40:0] scTables_1_io_update_pc_r_1; + reg [3:0] scTables_1_io_update_folded_hist_r_1_hist_12_folded_hist; + reg scTables_2_io_update_mask_1_REG; + reg scTables_2_io_update_tagePreds_1_r; + reg scTables_2_io_update_takens_1_r; + reg [5:0] scTables_2_io_update_oldCtrs_1_r; + reg [40:0] scTables_2_io_update_pc_r_1; + reg [7:0] scTables_2_io_update_folded_hist_r_1_hist_11_folded_hist; + reg scTables_3_io_update_mask_1_REG; + reg scTables_3_io_update_tagePreds_1_r; + reg scTables_3_io_update_takens_1_r; + reg [5:0] scTables_3_io_update_oldCtrs_1_r; + reg [40:0] scTables_3_io_update_pc_r_1; + reg [7:0] scTables_3_io_update_folded_hist_r_1_hist_2_folded_hist; + reg [1:0] io_perf_0_value_REG; + reg [1:0] io_perf_0_value_REG_1; + reg [1:0] io_perf_1_value_REG; + reg [1:0] io_perf_1_value_REG_1; + reg [1:0] io_perf_2_value_REG; + reg [1:0] io_perf_2_value_REG_1; + wire [7:0] _s1_scTableSums_T_8 = + 8'({_scTables_0_io_resp_ctrs_0_0[5], _scTables_0_io_resp_ctrs_0_0, 1'h1} + + {_scTables_1_io_resp_ctrs_0_0[5], _scTables_1_io_resp_ctrs_0_0, 1'h1}); + wire [7:0] _s1_scTableSums_T_9 = + 8'({_scTables_2_io_resp_ctrs_0_0[5], _scTables_2_io_resp_ctrs_0_0, 1'h1} + + {_scTables_3_io_resp_ctrs_0_0[5], _scTables_3_io_resp_ctrs_0_0, 1'h1}); + wire [7:0] _s1_scTableSums_T_19 = + 8'({_scTables_0_io_resp_ctrs_0_1[5], _scTables_0_io_resp_ctrs_0_1, 1'h1} + + {_scTables_1_io_resp_ctrs_0_1[5], _scTables_1_io_resp_ctrs_0_1, 1'h1}); + wire [7:0] _s1_scTableSums_T_20 = + 8'({_scTables_2_io_resp_ctrs_0_1[5], _scTables_2_io_resp_ctrs_0_1, 1'h1} + + {_scTables_3_io_resp_ctrs_0_1[5], _scTables_3_io_resp_ctrs_0_1, 1'h1}); + wire [7:0] _s1_scTableSums_T_30 = + 8'({_scTables_0_io_resp_ctrs_1_0[5], _scTables_0_io_resp_ctrs_1_0, 1'h1} + + {_scTables_1_io_resp_ctrs_1_0[5], _scTables_1_io_resp_ctrs_1_0, 1'h1}); + wire [7:0] _s1_scTableSums_T_31 = + 8'({_scTables_2_io_resp_ctrs_1_0[5], _scTables_2_io_resp_ctrs_1_0, 1'h1} + + {_scTables_3_io_resp_ctrs_1_0[5], _scTables_3_io_resp_ctrs_1_0, 1'h1}); + wire [7:0] _s1_scTableSums_T_41 = + 8'({_scTables_0_io_resp_ctrs_1_1[5], _scTables_0_io_resp_ctrs_1_1, 1'h1} + + {_scTables_1_io_resp_ctrs_1_1[5], _scTables_1_io_resp_ctrs_1_1, 1'h1}); + wire [7:0] _s1_scTableSums_T_42 = + 8'({_scTables_2_io_resp_ctrs_1_1[5], _scTables_2_io_resp_ctrs_1_1, 1'h1} + + {_scTables_3_io_resp_ctrs_1_1[5], _scTables_3_io_resp_ctrs_1_1, 1'h1}); + wire useAltCtr = + s1_pc_dup_0[7:1] == 7'h0 & useAltOnNaCtrs_0_0[3] | s1_pc_dup_0[7:1] == 7'h1 + & useAltOnNaCtrs_0_1[3] | s1_pc_dup_0[7:1] == 7'h2 & useAltOnNaCtrs_0_2[3] + | s1_pc_dup_0[7:1] == 7'h3 & useAltOnNaCtrs_0_3[3] | s1_pc_dup_0[7:1] == 7'h4 + & useAltOnNaCtrs_0_4[3] | s1_pc_dup_0[7:1] == 7'h5 & useAltOnNaCtrs_0_5[3] + | s1_pc_dup_0[7:1] == 7'h6 & useAltOnNaCtrs_0_6[3] | s1_pc_dup_0[7:1] == 7'h7 + & useAltOnNaCtrs_0_7[3] | s1_pc_dup_0[7:1] == 7'h8 & useAltOnNaCtrs_0_8[3] + | s1_pc_dup_0[7:1] == 7'h9 & useAltOnNaCtrs_0_9[3] | s1_pc_dup_0[7:1] == 7'hA + & useAltOnNaCtrs_0_10[3] | s1_pc_dup_0[7:1] == 7'hB & useAltOnNaCtrs_0_11[3] + | s1_pc_dup_0[7:1] == 7'hC & useAltOnNaCtrs_0_12[3] | s1_pc_dup_0[7:1] == 7'hD + & useAltOnNaCtrs_0_13[3] | s1_pc_dup_0[7:1] == 7'hE & useAltOnNaCtrs_0_14[3] + | s1_pc_dup_0[7:1] == 7'hF & useAltOnNaCtrs_0_15[3] | s1_pc_dup_0[7:1] == 7'h10 + & useAltOnNaCtrs_0_16[3] | s1_pc_dup_0[7:1] == 7'h11 & useAltOnNaCtrs_0_17[3] + | s1_pc_dup_0[7:1] == 7'h12 & useAltOnNaCtrs_0_18[3] | s1_pc_dup_0[7:1] == 7'h13 + & useAltOnNaCtrs_0_19[3] | s1_pc_dup_0[7:1] == 7'h14 & useAltOnNaCtrs_0_20[3] + | s1_pc_dup_0[7:1] == 7'h15 & useAltOnNaCtrs_0_21[3] | s1_pc_dup_0[7:1] == 7'h16 + & useAltOnNaCtrs_0_22[3] | s1_pc_dup_0[7:1] == 7'h17 & useAltOnNaCtrs_0_23[3] + | s1_pc_dup_0[7:1] == 7'h18 & useAltOnNaCtrs_0_24[3] | s1_pc_dup_0[7:1] == 7'h19 + & useAltOnNaCtrs_0_25[3] | s1_pc_dup_0[7:1] == 7'h1A & useAltOnNaCtrs_0_26[3] + | s1_pc_dup_0[7:1] == 7'h1B & useAltOnNaCtrs_0_27[3] | s1_pc_dup_0[7:1] == 7'h1C + & useAltOnNaCtrs_0_28[3] | s1_pc_dup_0[7:1] == 7'h1D & useAltOnNaCtrs_0_29[3] + | s1_pc_dup_0[7:1] == 7'h1E & useAltOnNaCtrs_0_30[3] | s1_pc_dup_0[7:1] == 7'h1F + & useAltOnNaCtrs_0_31[3] | s1_pc_dup_0[7:1] == 7'h20 & useAltOnNaCtrs_0_32[3] + | s1_pc_dup_0[7:1] == 7'h21 & useAltOnNaCtrs_0_33[3] | s1_pc_dup_0[7:1] == 7'h22 + & useAltOnNaCtrs_0_34[3] | s1_pc_dup_0[7:1] == 7'h23 & useAltOnNaCtrs_0_35[3] + | s1_pc_dup_0[7:1] == 7'h24 & useAltOnNaCtrs_0_36[3] | s1_pc_dup_0[7:1] == 7'h25 + & useAltOnNaCtrs_0_37[3] | s1_pc_dup_0[7:1] == 7'h26 & useAltOnNaCtrs_0_38[3] + | s1_pc_dup_0[7:1] == 7'h27 & useAltOnNaCtrs_0_39[3] | s1_pc_dup_0[7:1] == 7'h28 + & useAltOnNaCtrs_0_40[3] | s1_pc_dup_0[7:1] == 7'h29 & useAltOnNaCtrs_0_41[3] + | s1_pc_dup_0[7:1] == 7'h2A & useAltOnNaCtrs_0_42[3] | s1_pc_dup_0[7:1] == 7'h2B + & useAltOnNaCtrs_0_43[3] | s1_pc_dup_0[7:1] == 7'h2C & useAltOnNaCtrs_0_44[3] + | s1_pc_dup_0[7:1] == 7'h2D & useAltOnNaCtrs_0_45[3] | s1_pc_dup_0[7:1] == 7'h2E + & useAltOnNaCtrs_0_46[3] | s1_pc_dup_0[7:1] == 7'h2F & useAltOnNaCtrs_0_47[3] + | s1_pc_dup_0[7:1] == 7'h30 & useAltOnNaCtrs_0_48[3] | s1_pc_dup_0[7:1] == 7'h31 + & useAltOnNaCtrs_0_49[3] | s1_pc_dup_0[7:1] == 7'h32 & useAltOnNaCtrs_0_50[3] + | s1_pc_dup_0[7:1] == 7'h33 & useAltOnNaCtrs_0_51[3] | s1_pc_dup_0[7:1] == 7'h34 + & useAltOnNaCtrs_0_52[3] | s1_pc_dup_0[7:1] == 7'h35 & useAltOnNaCtrs_0_53[3] + | s1_pc_dup_0[7:1] == 7'h36 & useAltOnNaCtrs_0_54[3] | s1_pc_dup_0[7:1] == 7'h37 + & useAltOnNaCtrs_0_55[3] | s1_pc_dup_0[7:1] == 7'h38 & useAltOnNaCtrs_0_56[3] + | s1_pc_dup_0[7:1] == 7'h39 & useAltOnNaCtrs_0_57[3] | s1_pc_dup_0[7:1] == 7'h3A + & useAltOnNaCtrs_0_58[3] | s1_pc_dup_0[7:1] == 7'h3B & useAltOnNaCtrs_0_59[3] + | s1_pc_dup_0[7:1] == 7'h3C & useAltOnNaCtrs_0_60[3] | s1_pc_dup_0[7:1] == 7'h3D + & useAltOnNaCtrs_0_61[3] | s1_pc_dup_0[7:1] == 7'h3E & useAltOnNaCtrs_0_62[3] + | s1_pc_dup_0[7:1] == 7'h3F & useAltOnNaCtrs_0_63[3] | s1_pc_dup_0[7:1] == 7'h40 + & useAltOnNaCtrs_0_64[3] | s1_pc_dup_0[7:1] == 7'h41 & useAltOnNaCtrs_0_65[3] + | s1_pc_dup_0[7:1] == 7'h42 & useAltOnNaCtrs_0_66[3] | s1_pc_dup_0[7:1] == 7'h43 + & useAltOnNaCtrs_0_67[3] | s1_pc_dup_0[7:1] == 7'h44 & useAltOnNaCtrs_0_68[3] + | s1_pc_dup_0[7:1] == 7'h45 & useAltOnNaCtrs_0_69[3] | s1_pc_dup_0[7:1] == 7'h46 + & useAltOnNaCtrs_0_70[3] | s1_pc_dup_0[7:1] == 7'h47 & useAltOnNaCtrs_0_71[3] + | s1_pc_dup_0[7:1] == 7'h48 & useAltOnNaCtrs_0_72[3] | s1_pc_dup_0[7:1] == 7'h49 + & useAltOnNaCtrs_0_73[3] | s1_pc_dup_0[7:1] == 7'h4A & useAltOnNaCtrs_0_74[3] + | s1_pc_dup_0[7:1] == 7'h4B & useAltOnNaCtrs_0_75[3] | s1_pc_dup_0[7:1] == 7'h4C + & useAltOnNaCtrs_0_76[3] | s1_pc_dup_0[7:1] == 7'h4D & useAltOnNaCtrs_0_77[3] + | s1_pc_dup_0[7:1] == 7'h4E & useAltOnNaCtrs_0_78[3] | s1_pc_dup_0[7:1] == 7'h4F + & useAltOnNaCtrs_0_79[3] | s1_pc_dup_0[7:1] == 7'h50 & useAltOnNaCtrs_0_80[3] + | s1_pc_dup_0[7:1] == 7'h51 & useAltOnNaCtrs_0_81[3] | s1_pc_dup_0[7:1] == 7'h52 + & useAltOnNaCtrs_0_82[3] | s1_pc_dup_0[7:1] == 7'h53 & useAltOnNaCtrs_0_83[3] + | s1_pc_dup_0[7:1] == 7'h54 & useAltOnNaCtrs_0_84[3] | s1_pc_dup_0[7:1] == 7'h55 + & useAltOnNaCtrs_0_85[3] | s1_pc_dup_0[7:1] == 7'h56 & useAltOnNaCtrs_0_86[3] + | s1_pc_dup_0[7:1] == 7'h57 & useAltOnNaCtrs_0_87[3] | s1_pc_dup_0[7:1] == 7'h58 + & useAltOnNaCtrs_0_88[3] | s1_pc_dup_0[7:1] == 7'h59 & useAltOnNaCtrs_0_89[3] + | s1_pc_dup_0[7:1] == 7'h5A & useAltOnNaCtrs_0_90[3] | s1_pc_dup_0[7:1] == 7'h5B + & useAltOnNaCtrs_0_91[3] | s1_pc_dup_0[7:1] == 7'h5C & useAltOnNaCtrs_0_92[3] + | s1_pc_dup_0[7:1] == 7'h5D & useAltOnNaCtrs_0_93[3] | s1_pc_dup_0[7:1] == 7'h5E + & useAltOnNaCtrs_0_94[3] | s1_pc_dup_0[7:1] == 7'h5F & useAltOnNaCtrs_0_95[3] + | s1_pc_dup_0[7:1] == 7'h60 & useAltOnNaCtrs_0_96[3] | s1_pc_dup_0[7:1] == 7'h61 + & useAltOnNaCtrs_0_97[3] | s1_pc_dup_0[7:1] == 7'h62 & useAltOnNaCtrs_0_98[3] + | s1_pc_dup_0[7:1] == 7'h63 & useAltOnNaCtrs_0_99[3] | s1_pc_dup_0[7:1] == 7'h64 + & useAltOnNaCtrs_0_100[3] | s1_pc_dup_0[7:1] == 7'h65 & useAltOnNaCtrs_0_101[3] + | s1_pc_dup_0[7:1] == 7'h66 & useAltOnNaCtrs_0_102[3] | s1_pc_dup_0[7:1] == 7'h67 + & useAltOnNaCtrs_0_103[3] | s1_pc_dup_0[7:1] == 7'h68 & useAltOnNaCtrs_0_104[3] + | s1_pc_dup_0[7:1] == 7'h69 & useAltOnNaCtrs_0_105[3] | s1_pc_dup_0[7:1] == 7'h6A + & useAltOnNaCtrs_0_106[3] | s1_pc_dup_0[7:1] == 7'h6B & useAltOnNaCtrs_0_107[3] + | s1_pc_dup_0[7:1] == 7'h6C & useAltOnNaCtrs_0_108[3] | s1_pc_dup_0[7:1] == 7'h6D + & useAltOnNaCtrs_0_109[3] | s1_pc_dup_0[7:1] == 7'h6E & useAltOnNaCtrs_0_110[3] + | s1_pc_dup_0[7:1] == 7'h6F & useAltOnNaCtrs_0_111[3] | s1_pc_dup_0[7:1] == 7'h70 + & useAltOnNaCtrs_0_112[3] | s1_pc_dup_0[7:1] == 7'h71 & useAltOnNaCtrs_0_113[3] + | s1_pc_dup_0[7:1] == 7'h72 & useAltOnNaCtrs_0_114[3] | s1_pc_dup_0[7:1] == 7'h73 + & useAltOnNaCtrs_0_115[3] | s1_pc_dup_0[7:1] == 7'h74 & useAltOnNaCtrs_0_116[3] + | s1_pc_dup_0[7:1] == 7'h75 & useAltOnNaCtrs_0_117[3] | s1_pc_dup_0[7:1] == 7'h76 + & useAltOnNaCtrs_0_118[3] | s1_pc_dup_0[7:1] == 7'h77 & useAltOnNaCtrs_0_119[3] + | s1_pc_dup_0[7:1] == 7'h78 & useAltOnNaCtrs_0_120[3] | s1_pc_dup_0[7:1] == 7'h79 + & useAltOnNaCtrs_0_121[3] | s1_pc_dup_0[7:1] == 7'h7A & useAltOnNaCtrs_0_122[3] + | s1_pc_dup_0[7:1] == 7'h7B & useAltOnNaCtrs_0_123[3] | s1_pc_dup_0[7:1] == 7'h7C + & useAltOnNaCtrs_0_124[3] | s1_pc_dup_0[7:1] == 7'h7D & useAltOnNaCtrs_0_125[3] + | s1_pc_dup_0[7:1] == 7'h7E & useAltOnNaCtrs_0_126[3] | (&(s1_pc_dup_0[7:1])) + & useAltOnNaCtrs_0_127[3]; + wire _providerInfo_T = _tables_3_io_resps_0_valid | _tables_2_io_resps_0_valid; + wire [2:0] providerInfo_resp_ctr = + _providerInfo_T + ? (_tables_3_io_resps_0_valid + ? _tables_3_io_resps_0_bits_ctr + : _tables_2_io_resps_0_bits_ctr) + : _tables_1_io_resps_0_valid + ? _tables_1_io_resps_0_bits_ctr + : _tables_0_io_resps_0_bits_ctr; + wire provided = + _tables_0_io_resps_0_valid | _tables_1_io_resps_0_valid | _tables_2_io_resps_0_valid + | _tables_3_io_resps_0_valid; + wire s1_altUsed_0 = + ~provided + | (_providerInfo_T + ? (_tables_3_io_resps_0_valid + ? _tables_3_io_resps_0_bits_unconf & useAltCtr + : _tables_2_io_resps_0_bits_unconf & useAltCtr) + : _tables_1_io_resps_0_valid + ? _tables_1_io_resps_0_bits_unconf & useAltCtr + : _tables_0_io_resps_0_bits_unconf & useAltCtr); + wire s1_tageTakens_0 = + s1_altUsed_0 ? _bt_io_s1_cnt_0[1] : providerInfo_resp_ctr[2]; + wire baseupdate_0 = updateValids_0 & io_update_bits_meta[70]; + wire _GEN_3 = io_update_bits_meta[83:82] == 2'h0; + wire _GEN_4 = updateValids_0 & io_update_bits_meta[84]; + wire _GEN_5 = io_update_bits_meta[83:82] == 2'h1; + wire _GEN_6 = io_update_bits_meta[83:82] == 2'h2; + wire [1:0] maskedEntry = + io_update_bits_meta[56] & longerHistoryTableMask[0] & allocLFSR_lfsr[0] + ? 2'h0 + : io_update_bits_meta[57] & longerHistoryTableMask[1] & allocLFSR_lfsr[1] + ? 2'h1 + : {1'h1, + ~(io_update_bits_meta[58] & longerHistoryTableMask[2] & allocLFSR_lfsr[2])}; + wire [3:0] _allocate_T = + (io_update_bits_meta[59:56] & longerHistoryTableMask) >> maskedEntry; + wire [1:0] allocate = + _allocate_T[0] + ? maskedEntry + : _firstEntry_T ? 2'h0 : _firstEntry_T_1 ? 2'h1 : {1'h1, ~_firstEntry_T_2}; + wire _GEN_7 = allocate == 2'h0; + wire _GEN_8 = needToAllocate & (|(io_update_bits_meta[59:56])) & _GEN_7; + wire updateMask_0_0 = _GEN_8 | _GEN_4 & _GEN_3; + wire _GEN_9 = allocate == 2'h1; + wire _GEN_10 = needToAllocate & (|(io_update_bits_meta[59:56])) & _GEN_9; + wire updateMask_0_1 = _GEN_10 | _GEN_4 & _GEN_5; + wire _GEN_11 = allocate == 2'h2; + wire _GEN_12 = needToAllocate & (|(io_update_bits_meta[59:56])) & _GEN_11; + wire updateMask_0_2 = _GEN_12 | _GEN_4 & _GEN_6; + wire _GEN_13 = needToAllocate & (|(io_update_bits_meta[59:56])) & (&allocate); + wire updateMask_0_3 = _GEN_13 | _GEN_4 & (&(io_update_bits_meta[83:82])); + wire _GEN_14 = needToAllocate & (|(io_update_bits_meta[59:56])); + wire updateResetU_0 = needToAllocate & (&bankTickCtrs_0); + wire useAltCtr_1 = + s1_pc_dup_0[7:1] == 7'h0 & useAltOnNaCtrs_1_0[3] | s1_pc_dup_0[7:1] == 7'h1 + & useAltOnNaCtrs_1_1[3] | s1_pc_dup_0[7:1] == 7'h2 & useAltOnNaCtrs_1_2[3] + | s1_pc_dup_0[7:1] == 7'h3 & useAltOnNaCtrs_1_3[3] | s1_pc_dup_0[7:1] == 7'h4 + & useAltOnNaCtrs_1_4[3] | s1_pc_dup_0[7:1] == 7'h5 & useAltOnNaCtrs_1_5[3] + | s1_pc_dup_0[7:1] == 7'h6 & useAltOnNaCtrs_1_6[3] | s1_pc_dup_0[7:1] == 7'h7 + & useAltOnNaCtrs_1_7[3] | s1_pc_dup_0[7:1] == 7'h8 & useAltOnNaCtrs_1_8[3] + | s1_pc_dup_0[7:1] == 7'h9 & useAltOnNaCtrs_1_9[3] | s1_pc_dup_0[7:1] == 7'hA + & useAltOnNaCtrs_1_10[3] | s1_pc_dup_0[7:1] == 7'hB & useAltOnNaCtrs_1_11[3] + | s1_pc_dup_0[7:1] == 7'hC & useAltOnNaCtrs_1_12[3] | s1_pc_dup_0[7:1] == 7'hD + & useAltOnNaCtrs_1_13[3] | s1_pc_dup_0[7:1] == 7'hE & useAltOnNaCtrs_1_14[3] + | s1_pc_dup_0[7:1] == 7'hF & useAltOnNaCtrs_1_15[3] | s1_pc_dup_0[7:1] == 7'h10 + & useAltOnNaCtrs_1_16[3] | s1_pc_dup_0[7:1] == 7'h11 & useAltOnNaCtrs_1_17[3] + | s1_pc_dup_0[7:1] == 7'h12 & useAltOnNaCtrs_1_18[3] | s1_pc_dup_0[7:1] == 7'h13 + & useAltOnNaCtrs_1_19[3] | s1_pc_dup_0[7:1] == 7'h14 & useAltOnNaCtrs_1_20[3] + | s1_pc_dup_0[7:1] == 7'h15 & useAltOnNaCtrs_1_21[3] | s1_pc_dup_0[7:1] == 7'h16 + & useAltOnNaCtrs_1_22[3] | s1_pc_dup_0[7:1] == 7'h17 & useAltOnNaCtrs_1_23[3] + | s1_pc_dup_0[7:1] == 7'h18 & useAltOnNaCtrs_1_24[3] | s1_pc_dup_0[7:1] == 7'h19 + & useAltOnNaCtrs_1_25[3] | s1_pc_dup_0[7:1] == 7'h1A & useAltOnNaCtrs_1_26[3] + | s1_pc_dup_0[7:1] == 7'h1B & useAltOnNaCtrs_1_27[3] | s1_pc_dup_0[7:1] == 7'h1C + & useAltOnNaCtrs_1_28[3] | s1_pc_dup_0[7:1] == 7'h1D & useAltOnNaCtrs_1_29[3] + | s1_pc_dup_0[7:1] == 7'h1E & useAltOnNaCtrs_1_30[3] | s1_pc_dup_0[7:1] == 7'h1F + & useAltOnNaCtrs_1_31[3] | s1_pc_dup_0[7:1] == 7'h20 & useAltOnNaCtrs_1_32[3] + | s1_pc_dup_0[7:1] == 7'h21 & useAltOnNaCtrs_1_33[3] | s1_pc_dup_0[7:1] == 7'h22 + & useAltOnNaCtrs_1_34[3] | s1_pc_dup_0[7:1] == 7'h23 & useAltOnNaCtrs_1_35[3] + | s1_pc_dup_0[7:1] == 7'h24 & useAltOnNaCtrs_1_36[3] | s1_pc_dup_0[7:1] == 7'h25 + & useAltOnNaCtrs_1_37[3] | s1_pc_dup_0[7:1] == 7'h26 & useAltOnNaCtrs_1_38[3] + | s1_pc_dup_0[7:1] == 7'h27 & useAltOnNaCtrs_1_39[3] | s1_pc_dup_0[7:1] == 7'h28 + & useAltOnNaCtrs_1_40[3] | s1_pc_dup_0[7:1] == 7'h29 & useAltOnNaCtrs_1_41[3] + | s1_pc_dup_0[7:1] == 7'h2A & useAltOnNaCtrs_1_42[3] | s1_pc_dup_0[7:1] == 7'h2B + & useAltOnNaCtrs_1_43[3] | s1_pc_dup_0[7:1] == 7'h2C & useAltOnNaCtrs_1_44[3] + | s1_pc_dup_0[7:1] == 7'h2D & useAltOnNaCtrs_1_45[3] | s1_pc_dup_0[7:1] == 7'h2E + & useAltOnNaCtrs_1_46[3] | s1_pc_dup_0[7:1] == 7'h2F & useAltOnNaCtrs_1_47[3] + | s1_pc_dup_0[7:1] == 7'h30 & useAltOnNaCtrs_1_48[3] | s1_pc_dup_0[7:1] == 7'h31 + & useAltOnNaCtrs_1_49[3] | s1_pc_dup_0[7:1] == 7'h32 & useAltOnNaCtrs_1_50[3] + | s1_pc_dup_0[7:1] == 7'h33 & useAltOnNaCtrs_1_51[3] | s1_pc_dup_0[7:1] == 7'h34 + & useAltOnNaCtrs_1_52[3] | s1_pc_dup_0[7:1] == 7'h35 & useAltOnNaCtrs_1_53[3] + | s1_pc_dup_0[7:1] == 7'h36 & useAltOnNaCtrs_1_54[3] | s1_pc_dup_0[7:1] == 7'h37 + & useAltOnNaCtrs_1_55[3] | s1_pc_dup_0[7:1] == 7'h38 & useAltOnNaCtrs_1_56[3] + | s1_pc_dup_0[7:1] == 7'h39 & useAltOnNaCtrs_1_57[3] | s1_pc_dup_0[7:1] == 7'h3A + & useAltOnNaCtrs_1_58[3] | s1_pc_dup_0[7:1] == 7'h3B & useAltOnNaCtrs_1_59[3] + | s1_pc_dup_0[7:1] == 7'h3C & useAltOnNaCtrs_1_60[3] | s1_pc_dup_0[7:1] == 7'h3D + & useAltOnNaCtrs_1_61[3] | s1_pc_dup_0[7:1] == 7'h3E & useAltOnNaCtrs_1_62[3] + | s1_pc_dup_0[7:1] == 7'h3F & useAltOnNaCtrs_1_63[3] | s1_pc_dup_0[7:1] == 7'h40 + & useAltOnNaCtrs_1_64[3] | s1_pc_dup_0[7:1] == 7'h41 & useAltOnNaCtrs_1_65[3] + | s1_pc_dup_0[7:1] == 7'h42 & useAltOnNaCtrs_1_66[3] | s1_pc_dup_0[7:1] == 7'h43 + & useAltOnNaCtrs_1_67[3] | s1_pc_dup_0[7:1] == 7'h44 & useAltOnNaCtrs_1_68[3] + | s1_pc_dup_0[7:1] == 7'h45 & useAltOnNaCtrs_1_69[3] | s1_pc_dup_0[7:1] == 7'h46 + & useAltOnNaCtrs_1_70[3] | s1_pc_dup_0[7:1] == 7'h47 & useAltOnNaCtrs_1_71[3] + | s1_pc_dup_0[7:1] == 7'h48 & useAltOnNaCtrs_1_72[3] | s1_pc_dup_0[7:1] == 7'h49 + & useAltOnNaCtrs_1_73[3] | s1_pc_dup_0[7:1] == 7'h4A & useAltOnNaCtrs_1_74[3] + | s1_pc_dup_0[7:1] == 7'h4B & useAltOnNaCtrs_1_75[3] | s1_pc_dup_0[7:1] == 7'h4C + & useAltOnNaCtrs_1_76[3] | s1_pc_dup_0[7:1] == 7'h4D & useAltOnNaCtrs_1_77[3] + | s1_pc_dup_0[7:1] == 7'h4E & useAltOnNaCtrs_1_78[3] | s1_pc_dup_0[7:1] == 7'h4F + & useAltOnNaCtrs_1_79[3] | s1_pc_dup_0[7:1] == 7'h50 & useAltOnNaCtrs_1_80[3] + | s1_pc_dup_0[7:1] == 7'h51 & useAltOnNaCtrs_1_81[3] | s1_pc_dup_0[7:1] == 7'h52 + & useAltOnNaCtrs_1_82[3] | s1_pc_dup_0[7:1] == 7'h53 & useAltOnNaCtrs_1_83[3] + | s1_pc_dup_0[7:1] == 7'h54 & useAltOnNaCtrs_1_84[3] | s1_pc_dup_0[7:1] == 7'h55 + & useAltOnNaCtrs_1_85[3] | s1_pc_dup_0[7:1] == 7'h56 & useAltOnNaCtrs_1_86[3] + | s1_pc_dup_0[7:1] == 7'h57 & useAltOnNaCtrs_1_87[3] | s1_pc_dup_0[7:1] == 7'h58 + & useAltOnNaCtrs_1_88[3] | s1_pc_dup_0[7:1] == 7'h59 & useAltOnNaCtrs_1_89[3] + | s1_pc_dup_0[7:1] == 7'h5A & useAltOnNaCtrs_1_90[3] | s1_pc_dup_0[7:1] == 7'h5B + & useAltOnNaCtrs_1_91[3] | s1_pc_dup_0[7:1] == 7'h5C & useAltOnNaCtrs_1_92[3] + | s1_pc_dup_0[7:1] == 7'h5D & useAltOnNaCtrs_1_93[3] | s1_pc_dup_0[7:1] == 7'h5E + & useAltOnNaCtrs_1_94[3] | s1_pc_dup_0[7:1] == 7'h5F & useAltOnNaCtrs_1_95[3] + | s1_pc_dup_0[7:1] == 7'h60 & useAltOnNaCtrs_1_96[3] | s1_pc_dup_0[7:1] == 7'h61 + & useAltOnNaCtrs_1_97[3] | s1_pc_dup_0[7:1] == 7'h62 & useAltOnNaCtrs_1_98[3] + | s1_pc_dup_0[7:1] == 7'h63 & useAltOnNaCtrs_1_99[3] | s1_pc_dup_0[7:1] == 7'h64 + & useAltOnNaCtrs_1_100[3] | s1_pc_dup_0[7:1] == 7'h65 & useAltOnNaCtrs_1_101[3] + | s1_pc_dup_0[7:1] == 7'h66 & useAltOnNaCtrs_1_102[3] | s1_pc_dup_0[7:1] == 7'h67 + & useAltOnNaCtrs_1_103[3] | s1_pc_dup_0[7:1] == 7'h68 & useAltOnNaCtrs_1_104[3] + | s1_pc_dup_0[7:1] == 7'h69 & useAltOnNaCtrs_1_105[3] | s1_pc_dup_0[7:1] == 7'h6A + & useAltOnNaCtrs_1_106[3] | s1_pc_dup_0[7:1] == 7'h6B & useAltOnNaCtrs_1_107[3] + | s1_pc_dup_0[7:1] == 7'h6C & useAltOnNaCtrs_1_108[3] | s1_pc_dup_0[7:1] == 7'h6D + & useAltOnNaCtrs_1_109[3] | s1_pc_dup_0[7:1] == 7'h6E & useAltOnNaCtrs_1_110[3] + | s1_pc_dup_0[7:1] == 7'h6F & useAltOnNaCtrs_1_111[3] | s1_pc_dup_0[7:1] == 7'h70 + & useAltOnNaCtrs_1_112[3] | s1_pc_dup_0[7:1] == 7'h71 & useAltOnNaCtrs_1_113[3] + | s1_pc_dup_0[7:1] == 7'h72 & useAltOnNaCtrs_1_114[3] | s1_pc_dup_0[7:1] == 7'h73 + & useAltOnNaCtrs_1_115[3] | s1_pc_dup_0[7:1] == 7'h74 & useAltOnNaCtrs_1_116[3] + | s1_pc_dup_0[7:1] == 7'h75 & useAltOnNaCtrs_1_117[3] | s1_pc_dup_0[7:1] == 7'h76 + & useAltOnNaCtrs_1_118[3] | s1_pc_dup_0[7:1] == 7'h77 & useAltOnNaCtrs_1_119[3] + | s1_pc_dup_0[7:1] == 7'h78 & useAltOnNaCtrs_1_120[3] | s1_pc_dup_0[7:1] == 7'h79 + & useAltOnNaCtrs_1_121[3] | s1_pc_dup_0[7:1] == 7'h7A & useAltOnNaCtrs_1_122[3] + | s1_pc_dup_0[7:1] == 7'h7B & useAltOnNaCtrs_1_123[3] | s1_pc_dup_0[7:1] == 7'h7C + & useAltOnNaCtrs_1_124[3] | s1_pc_dup_0[7:1] == 7'h7D & useAltOnNaCtrs_1_125[3] + | s1_pc_dup_0[7:1] == 7'h7E & useAltOnNaCtrs_1_126[3] | (&(s1_pc_dup_0[7:1])) + & useAltOnNaCtrs_1_127[3]; + wire _providerInfo_T_5 = _tables_3_io_resps_1_valid | _tables_2_io_resps_1_valid; + wire [2:0] s1_providerResps_1_ctr = + _providerInfo_T_5 + ? (_tables_3_io_resps_1_valid + ? _tables_3_io_resps_1_bits_ctr + : _tables_2_io_resps_1_bits_ctr) + : _tables_1_io_resps_1_valid + ? _tables_1_io_resps_1_bits_ctr + : _tables_0_io_resps_1_bits_ctr; + wire provided_1 = + _tables_0_io_resps_1_valid | _tables_1_io_resps_1_valid | _tables_2_io_resps_1_valid + | _tables_3_io_resps_1_valid; + wire s1_altUsed_1 = + ~provided_1 + | (_providerInfo_T_5 + ? (_tables_3_io_resps_1_valid + ? _tables_3_io_resps_1_bits_unconf & useAltCtr_1 + : _tables_2_io_resps_1_bits_unconf & useAltCtr_1) + : _tables_1_io_resps_1_valid + ? _tables_1_io_resps_1_bits_unconf & useAltCtr_1 + : _tables_0_io_resps_1_bits_unconf & useAltCtr_1); + wire s1_tageTakens_1 = + s1_altUsed_1 ? _bt_io_s1_cnt_1[1] : s1_providerResps_1_ctr[2]; + wire baseupdate_1 = updateValids_1 & io_update_bits_meta[71]; + wire _GEN_15 = io_update_bits_meta[86:85] == 2'h0; + wire _GEN_16 = updateValids_1 & io_update_bits_meta[87]; + wire _GEN_17 = io_update_bits_meta[86:85] == 2'h1; + wire _GEN_18 = io_update_bits_meta[86:85] == 2'h2; + wire [1:0] maskedEntry_1 = + io_update_bits_meta[60] & longerHistoryTableMask_1[0] & allocLFSR_lfsr_1[0] + ? 2'h0 + : io_update_bits_meta[61] & longerHistoryTableMask_1[1] & allocLFSR_lfsr_1[1] + ? 2'h1 + : {1'h1, + ~(io_update_bits_meta[62] & longerHistoryTableMask_1[2] + & allocLFSR_lfsr_1[2])}; + wire [3:0] _allocate_T_2 = + (io_update_bits_meta[63:60] & longerHistoryTableMask_1) >> maskedEntry_1; + wire [1:0] allocate_1 = + _allocate_T_2[0] + ? maskedEntry_1 + : _firstEntry_T_6 ? 2'h0 : _firstEntry_T_7 ? 2'h1 : {1'h1, ~_firstEntry_T_8}; + wire _GEN_19 = allocate_1 == 2'h0; + wire _GEN_20 = needToAllocate_1 & (|(io_update_bits_meta[63:60])) & _GEN_19; + wire updateMask_1_0 = _GEN_20 | _GEN_16 & _GEN_15; + wire _GEN_21 = allocate_1 == 2'h1; + wire _GEN_22 = needToAllocate_1 & (|(io_update_bits_meta[63:60])) & _GEN_21; + wire updateMask_1_1 = _GEN_22 | _GEN_16 & _GEN_17; + wire _GEN_23 = allocate_1 == 2'h2; + wire _GEN_24 = needToAllocate_1 & (|(io_update_bits_meta[63:60])) & _GEN_23; + wire updateMask_1_2 = _GEN_24 | _GEN_16 & _GEN_18; + wire _GEN_25 = + needToAllocate_1 & (|(io_update_bits_meta[63:60])) & (&allocate_1); + wire updateMask_1_3 = _GEN_25 | _GEN_16 & (&(io_update_bits_meta[86:85])); + wire _GEN_26 = needToAllocate_1 & (|(io_update_bits_meta[63:60])); + wire updateResetU_1 = needToAllocate_1 & (&bankTickCtrs_1); + wire [2:0] _s2_tagePrvdCtrCentered_T = s2_tagePrvdCtrCentered_r ^ 3'h4; + wire [9:0] _GEN_27 = + {{3{_s2_tagePrvdCtrCentered_T[2]}}, _s2_tagePrvdCtrCentered_T, 4'h8}; + wire [9:0] s2_totalSums_0 = 10'({s2_scTableSums_0[8], s2_scTableSums_0} + _GEN_27); + wire [9:0] s2_totalSums_1 = 10'({s2_scTableSums_1[8], s2_scTableSums_1} + _GEN_27); + wire [8:0] _GEN_28 = {1'h0, scThresholds_0_thres}; + wire [8:0] _GEN_29 = + {{2{_s2_tagePrvdCtrCentered_T[2]}}, _s2_tagePrvdCtrCentered_T, 4'h8}; + wire _GEN_30 = + s2_tageTakens_dup_3_0 + ? $signed(s2_totalSums_1) > -10'sh1 + : $signed(s2_totalSums_0) > -10'sh1; + wire s2_pred = + s2_provideds_0 + & (s2_tageTakens_dup_3_0 + ? $signed(s2_scTableSums_1) > $signed(9'(_GEN_28 - _GEN_29)) + & ~(s2_totalSums_1[9]) + | $signed(s2_scTableSums_1) < $signed(9'(9'(9'h0 - _GEN_28) - _GEN_29)) + & s2_totalSums_1[9] + : $signed(s2_scTableSums_0) > $signed(9'(_GEN_28 - _GEN_29)) + & ~(s2_totalSums_0[9]) + | $signed(s2_scTableSums_0) < $signed(9'(9'(9'h0 - _GEN_28) - _GEN_29)) + & s2_totalSums_0[9]) + ? _GEN_30 + : s2_tageTakens_dup_3_0; + wire [12:0] _GEN_31 = {1'h0, 12'({1'h0, scThresholds_0_thres, 3'h0} + 12'h15)}; + wire [12:0] _GEN_32 = {{6{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8}; + wire [12:0] _GEN_33 = {{3{sum[9]}}, sum}; + wire [10:0] sumAboveThreshold_totalSum = + 11'({sum[9], sum} + {{4{_sumAboveThreshold_T[2]}}, _sumAboveThreshold_T, 4'h8}); + wire _GEN_34 = + _update_on_mispred_0_T + | ~($signed(_GEN_33) > $signed(13'(_GEN_31 - _GEN_32)) + & ~(sumAboveThreshold_totalSum[10]) + | $signed(_GEN_33) < $signed(13'(13'(13'h0 - _GEN_31) - _GEN_32)) + & sumAboveThreshold_totalSum[10]); + wire scUpdateMask_0_3 = _GEN_1 & _GEN_34; + wire _GEN_35 = _GEN_1 & _GEN_34; + wire [2:0] _s2_tagePrvdCtrCentered_T_2 = s2_tagePrvdCtrCentered_r_1 ^ 3'h4; + wire [9:0] _GEN_36 = + {{3{_s2_tagePrvdCtrCentered_T_2[2]}}, _s2_tagePrvdCtrCentered_T_2, 4'h8}; + wire [9:0] s2_totalSums_0_1 = + 10'({s2_scTableSums_1_0[8], s2_scTableSums_1_0} + _GEN_36); + wire [9:0] s2_totalSums_1_1 = + 10'({s2_scTableSums_1_1[8], s2_scTableSums_1_1} + _GEN_36); + wire [8:0] _GEN_37 = {1'h0, scThresholds_1_thres}; + wire [8:0] _GEN_38 = + {{2{_s2_tagePrvdCtrCentered_T_2[2]}}, _s2_tagePrvdCtrCentered_T_2, 4'h8}; + wire _GEN_39 = + s2_tageTakens_dup_3_1 + ? $signed(s2_totalSums_1_1) > -10'sh1 + : $signed(s2_totalSums_0_1) > -10'sh1; + wire s2_pred_1 = + s2_provideds_1 + & (s2_tageTakens_dup_3_1 + ? $signed(s2_scTableSums_1_1) > $signed(9'(_GEN_37 - _GEN_38)) + & ~(s2_totalSums_1_1[9]) + | $signed(s2_scTableSums_1_1) < $signed(9'(9'(9'h0 - _GEN_37) - _GEN_38)) + & s2_totalSums_1_1[9] + : $signed(s2_scTableSums_1_0) > $signed(9'(_GEN_37 - _GEN_38)) + & ~(s2_totalSums_0_1[9]) + | $signed(s2_scTableSums_1_0) < $signed(9'(9'(9'h0 - _GEN_37) - _GEN_38)) + & s2_totalSums_0_1[9]) + ? _GEN_39 + : s2_tageTakens_dup_3_1; + wire [12:0] _GEN_40 = {1'h0, 12'({1'h0, scThresholds_1_thres, 3'h0} + 12'h15)}; + wire [12:0] _GEN_41 = {{6{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8}; + wire [12:0] _GEN_42 = {{3{sum_1[9]}}, sum_1}; + wire [10:0] sumAboveThreshold_totalSum_1 = + 11'({sum_1[9], sum_1} + + {{4{_sumAboveThreshold_T_19[2]}}, _sumAboveThreshold_T_19, 4'h8}); + wire _GEN_43 = + _update_on_mispred_1_T + | ~($signed(_GEN_42) > $signed(13'(_GEN_40 - _GEN_41)) + & ~(sumAboveThreshold_totalSum_1[10]) + | $signed(_GEN_42) < $signed(13'(13'(13'h0 - _GEN_40) - _GEN_41)) + & sumAboveThreshold_totalSum_1[10]); + wire scUpdateMask_1_3 = _GEN_2 & _GEN_43; + wire _GEN_44 = _GEN_2 & _GEN_43; + wire [1:0] providerInfo_tableIdx = + _providerInfo_T + ? {1'h1, _tables_3_io_resps_0_valid} + : {1'h0, _tables_1_io_resps_0_valid}; + wire [3:0] _allocatableSlots_T_14 = 4'h1 << providerInfo_tableIdx; + wire [2:0] _GEN_45 = _allocatableSlots_T_14[2:0] | _allocatableSlots_T_14[3:1]; + wire [1:0] s1_providers_1 = + _providerInfo_T_5 + ? {1'h1, _tables_3_io_resps_1_valid} + : {1'h0, _tables_1_io_resps_1_valid}; + wire [3:0] _allocatableSlots_T_39 = 4'h1 << s1_providers_1; + wire [2:0] _GEN_46 = _allocatableSlots_T_39[2:0] | _allocatableSlots_T_39[3:1]; + always @(posedge clock) begin + if (REG_1) + s1_pc_dup_0 <= {5'h0, _reset_vector_delay_io_out}; + else if (io_s0_fire_0) + s1_pc_dup_0 <= io_in_bits_s0_pc_0; + REG <= reset; + REG_1 <= REG & ~reset; + if (io_s1_fire_1) begin + s2_provideds_0 <= provided; + s2_provideds_1 <= provided_1; + s2_providers_0 <= providerInfo_tableIdx; + s2_providers_1 <= s1_providers_1; + s2_providerResps_0_ctr <= providerInfo_resp_ctr; + s2_providerResps_0_u <= + _providerInfo_T + ? (_tables_3_io_resps_0_valid + ? _tables_3_io_resps_0_bits_u + : _tables_2_io_resps_0_bits_u) + : _tables_1_io_resps_0_valid + ? _tables_1_io_resps_0_bits_u + : _tables_0_io_resps_0_bits_u; + s2_providerResps_0_unconf <= + _providerInfo_T + ? (_tables_3_io_resps_0_valid + ? _tables_3_io_resps_0_bits_unconf + : _tables_2_io_resps_0_bits_unconf) + : _tables_1_io_resps_0_valid + ? _tables_1_io_resps_0_bits_unconf + : _tables_0_io_resps_0_bits_unconf; + s2_providerResps_1_ctr <= s1_providerResps_1_ctr; + s2_providerResps_1_u <= + _providerInfo_T_5 + ? (_tables_3_io_resps_1_valid + ? _tables_3_io_resps_1_bits_u + : _tables_2_io_resps_1_bits_u) + : _tables_1_io_resps_1_valid + ? _tables_1_io_resps_1_bits_u + : _tables_0_io_resps_1_bits_u; + s2_providerResps_1_unconf <= + _providerInfo_T_5 + ? (_tables_3_io_resps_1_valid + ? _tables_3_io_resps_1_bits_unconf + : _tables_2_io_resps_1_bits_unconf) + : _tables_1_io_resps_1_valid + ? _tables_1_io_resps_1_bits_unconf + : _tables_0_io_resps_1_bits_unconf; + s2_altUsed_0 <= s1_altUsed_0; + s2_altUsed_1 <= s1_altUsed_1; + s2_tageTakens_dup_1_0 <= s1_tageTakens_0; + s2_tageTakens_dup_1_1 <= s1_tageTakens_1; + s2_finalAltPreds_0 <= _bt_io_s1_cnt_0[1]; + s2_finalAltPreds_1 <= _bt_io_s1_cnt_1[1]; + s2_basecnts_0 <= _bt_io_s1_cnt_0; + s2_basecnts_1 <= _bt_io_s1_cnt_1; + allocatableSlots <= + {~_tables_3_io_resps_0_valid & ~_tables_3_io_resps_0_bits_u, + ~_tables_2_io_resps_0_valid & ~_tables_2_io_resps_0_bits_u, + ~_tables_1_io_resps_0_valid & ~_tables_1_io_resps_0_bits_u, + ~_tables_0_io_resps_0_valid & ~_tables_0_io_resps_0_bits_u} + & ~({&providerInfo_tableIdx, + _GEN_45[2], + _GEN_45[1] | (&providerInfo_tableIdx), + _GEN_45[0] | providerInfo_tableIdx == 2'h2 | (&providerInfo_tableIdx)} + & {4{provided}}); + allocatableSlots_1 <= + {~_tables_3_io_resps_1_valid & ~_tables_3_io_resps_1_bits_u, + ~_tables_2_io_resps_1_valid & ~_tables_2_io_resps_1_bits_u, + ~_tables_1_io_resps_1_valid & ~_tables_1_io_resps_1_bits_u, + ~_tables_0_io_resps_1_valid & ~_tables_0_io_resps_1_bits_u} + & ~({&s1_providers_1, + _GEN_46[2], + _GEN_46[1] | (&s1_providers_1), + _GEN_46[0] | s1_providers_1 == 2'h2 | (&s1_providers_1)} & {4{provided_1}}); + end + if (io_s1_fire_0) begin + s2_tageTakens_dup_0_0 <= s1_tageTakens_0; + s2_tageTakens_dup_0_1 <= s1_tageTakens_1; + end + if (io_s1_fire_2) begin + s2_tageTakens_dup_2_0 <= s1_tageTakens_0; + s2_tageTakens_dup_2_1 <= s1_tageTakens_1; + end + if (io_s1_fire_3) begin + s2_tageTakens_dup_3_0 <= s1_tageTakens_0; + s2_tageTakens_dup_3_1 <= s1_tageTakens_1; + s2_scTableSums_0 <= + 9'({_s1_scTableSums_T_8[7], _s1_scTableSums_T_8} + + {_s1_scTableSums_T_9[7], _s1_scTableSums_T_9}); + s2_scTableSums_1 <= + 9'({_s1_scTableSums_T_19[7], _s1_scTableSums_T_19} + + {_s1_scTableSums_T_20[7], _s1_scTableSums_T_20}); + s2_tagePrvdCtrCentered_r <= providerInfo_resp_ctr; + s2_scResps_r_0_ctrs_0_0 <= _scTables_0_io_resp_ctrs_0_0; + s2_scResps_r_0_ctrs_0_1 <= _scTables_0_io_resp_ctrs_0_1; + s2_scResps_r_1_ctrs_0_0 <= _scTables_1_io_resp_ctrs_0_0; + s2_scResps_r_1_ctrs_0_1 <= _scTables_1_io_resp_ctrs_0_1; + s2_scResps_r_2_ctrs_0_0 <= _scTables_2_io_resp_ctrs_0_0; + s2_scResps_r_2_ctrs_0_1 <= _scTables_2_io_resp_ctrs_0_1; + s2_scResps_r_3_ctrs_0_0 <= _scTables_3_io_resp_ctrs_0_0; + s2_scResps_r_3_ctrs_0_1 <= _scTables_3_io_resp_ctrs_0_1; + s2_scTableSums_1_0 <= + 9'({_s1_scTableSums_T_30[7], _s1_scTableSums_T_30} + + {_s1_scTableSums_T_31[7], _s1_scTableSums_T_31}); + s2_scTableSums_1_1 <= + 9'({_s1_scTableSums_T_41[7], _s1_scTableSums_T_41} + + {_s1_scTableSums_T_42[7], _s1_scTableSums_T_42}); + s2_tagePrvdCtrCentered_r_1 <= s1_providerResps_1_ctr; + s2_scResps_r_1_0_ctrs_1_0 <= _scTables_0_io_resp_ctrs_1_0; + s2_scResps_r_1_0_ctrs_1_1 <= _scTables_0_io_resp_ctrs_1_1; + s2_scResps_r_1_1_ctrs_1_0 <= _scTables_1_io_resp_ctrs_1_0; + s2_scResps_r_1_1_ctrs_1_1 <= _scTables_1_io_resp_ctrs_1_1; + s2_scResps_r_1_2_ctrs_1_0 <= _scTables_2_io_resp_ctrs_1_0; + s2_scResps_r_1_2_ctrs_1_1 <= _scTables_2_io_resp_ctrs_1_1; + s2_scResps_r_1_3_ctrs_1_0 <= _scTables_3_io_resp_ctrs_1_0; + s2_scResps_r_1_3_ctrs_1_1 <= _scTables_3_io_resp_ctrs_1_1; + end + if (io_s2_fire_1) begin + resp_meta_providers_0_valid_r <= s2_provideds_0; + resp_meta_providers_0_bits_r <= s2_providers_0; + resp_meta_providerResps_0_r_ctr <= s2_providerResps_0_ctr; + resp_meta_providerResps_0_r_u <= s2_providerResps_0_u; + resp_meta_providerResps_0_r_unconf <= s2_providerResps_0_unconf; + resp_meta_allocates_0_r <= allocatableSlots; + resp_meta_altUsed_0_r <= s2_altUsed_0; + resp_meta_altDiffers_0_r <= s2_finalAltPreds_0 != s2_providerResps_0_ctr[2]; + resp_meta_takens_0_r <= s2_tageTakens_dup_0_0; + resp_meta_basecnts_0_r <= s2_basecnts_0; + resp_meta_providers_1_valid_r <= s2_provideds_1; + resp_meta_providers_1_bits_r <= s2_providers_1; + resp_meta_providerResps_1_r_ctr <= s2_providerResps_1_ctr; + resp_meta_providerResps_1_r_u <= s2_providerResps_1_u; + resp_meta_providerResps_1_r_unconf <= s2_providerResps_1_unconf; + resp_meta_allocates_1_r <= allocatableSlots_1; + resp_meta_altUsed_1_r <= s2_altUsed_1; + resp_meta_altDiffers_1_r <= s2_finalAltPreds_1 != s2_providerResps_1_ctr[2]; + resp_meta_takens_1_r <= s2_tageTakens_dup_0_1; + resp_meta_basecnts_1_r <= s2_basecnts_1; + s3_pred_dup_1 <= s2_pred; + s3_pred_dup_1_1 <= s2_pred_1; + end + tage_enable_dup_REG <= io_ctrl_tage_enable; + tage_enable_dup_REG_1 <= io_ctrl_tage_enable; + tables_0_io_update_reset_u_0_REG <= updateResetU_0; + tables_0_io_update_mask_0_REG <= updateMask_0_0; + if (updateMask_0_0 | updateMask_1_0) begin + tables_0_io_update_takens_0_r <= updateTaken; + tables_0_io_update_alloc_0_r <= _GEN_14 & _GEN_7; + tables_0_io_update_oldCtrs_0_r <= io_update_bits_meta[76:74]; + tables_0_io_update_uMask_0_r <= + _GEN_8 | updateValids_0 & io_update_bits_meta[84] & _GEN_3 + & io_update_bits_meta[68]; + tables_0_io_update_us_0_r <= ~_GEN_8 & updateProviderCorrect; + tables_0_io_update_takens_1_r <= updateTaken_1; + tables_0_io_update_alloc_1_r <= _GEN_26 & _GEN_19; + tables_0_io_update_oldCtrs_1_r <= io_update_bits_meta[81:79]; + tables_0_io_update_uMask_1_r <= + _GEN_20 | updateValids_1 & io_update_bits_meta[87] & _GEN_15 + & io_update_bits_meta[69]; + tables_0_io_update_us_1_r <= ~_GEN_20 & updateProviderCorrect_1; + tables_0_io_update_pc_r_1 <= io_update_bits_pc; + tables_0_io_update_folded_hist_r_1_hist_14_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_14_folded_hist; + tables_0_io_update_folded_hist_r_1_hist_7_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_7_folded_hist; + end + tables_1_io_update_reset_u_0_REG <= updateResetU_0; + tables_1_io_update_mask_0_REG <= updateMask_0_1; + if (updateMask_0_1 | updateMask_1_1) begin + tables_1_io_update_takens_0_r <= updateTaken; + tables_1_io_update_alloc_0_r <= _GEN_14 & _GEN_9; + tables_1_io_update_oldCtrs_0_r <= io_update_bits_meta[76:74]; + tables_1_io_update_uMask_0_r <= + _GEN_10 | updateValids_0 & io_update_bits_meta[84] & _GEN_5 + & io_update_bits_meta[68]; + tables_1_io_update_us_0_r <= ~_GEN_10 & updateProviderCorrect; + tables_1_io_update_takens_1_r <= updateTaken_1; + tables_1_io_update_alloc_1_r <= _GEN_26 & _GEN_21; + tables_1_io_update_oldCtrs_1_r <= io_update_bits_meta[81:79]; + tables_1_io_update_uMask_1_r <= + _GEN_22 | updateValids_1 & io_update_bits_meta[87] & _GEN_17 + & io_update_bits_meta[69]; + tables_1_io_update_us_1_r <= ~_GEN_22 & updateProviderCorrect_1; + tables_1_io_update_pc_r_1 <= io_update_bits_pc; + tables_1_io_update_folded_hist_r_1_hist_15_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_15_folded_hist; + tables_1_io_update_folded_hist_r_1_hist_4_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_4_folded_hist; + tables_1_io_update_folded_hist_r_1_hist_1_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_1_folded_hist; + end + tables_2_io_update_reset_u_0_REG <= updateResetU_0; + tables_2_io_update_mask_0_REG <= updateMask_0_2; + if (updateMask_0_2 | updateMask_1_2) begin + tables_2_io_update_takens_0_r <= updateTaken; + tables_2_io_update_alloc_0_r <= _GEN_14 & _GEN_11; + tables_2_io_update_oldCtrs_0_r <= io_update_bits_meta[76:74]; + tables_2_io_update_uMask_0_r <= + _GEN_12 | updateValids_0 & io_update_bits_meta[84] & _GEN_6 + & io_update_bits_meta[68]; + tables_2_io_update_us_0_r <= ~_GEN_12 & updateProviderCorrect; + tables_2_io_update_takens_1_r <= updateTaken_1; + tables_2_io_update_alloc_1_r <= _GEN_26 & _GEN_23; + tables_2_io_update_oldCtrs_1_r <= io_update_bits_meta[81:79]; + tables_2_io_update_uMask_1_r <= + _GEN_24 | updateValids_1 & io_update_bits_meta[87] & _GEN_18 + & io_update_bits_meta[69]; + tables_2_io_update_us_1_r <= ~_GEN_24 & updateProviderCorrect_1; + tables_2_io_update_pc_r_1 <= io_update_bits_pc; + tables_2_io_update_folded_hist_r_1_hist_17_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_17_folded_hist; + tables_2_io_update_folded_hist_r_1_hist_9_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_9_folded_hist; + tables_2_io_update_folded_hist_r_1_hist_3_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_3_folded_hist; + end + tables_3_io_update_reset_u_0_REG <= updateResetU_0; + tables_3_io_update_mask_0_REG <= updateMask_0_3; + if (updateMask_0_3 | updateMask_1_3) begin + tables_3_io_update_takens_0_r <= updateTaken; + tables_3_io_update_alloc_0_r <= _GEN_14 & (&allocate); + tables_3_io_update_oldCtrs_0_r <= io_update_bits_meta[76:74]; + tables_3_io_update_uMask_0_r <= + _GEN_13 | updateValids_0 & io_update_bits_meta[84] + & (&(io_update_bits_meta[83:82])) & io_update_bits_meta[68]; + tables_3_io_update_us_0_r <= ~_GEN_13 & updateProviderCorrect; + tables_3_io_update_takens_1_r <= updateTaken_1; + tables_3_io_update_alloc_1_r <= _GEN_26 & (&allocate_1); + tables_3_io_update_oldCtrs_1_r <= io_update_bits_meta[81:79]; + tables_3_io_update_uMask_1_r <= + _GEN_25 | updateValids_1 & io_update_bits_meta[87] + & (&(io_update_bits_meta[86:85])) & io_update_bits_meta[69]; + tables_3_io_update_us_1_r <= ~_GEN_25 & updateProviderCorrect_1; + tables_3_io_update_pc_r_1 <= io_update_bits_pc; + tables_3_io_update_folded_hist_r_1_hist_16_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_16_folded_hist; + tables_3_io_update_folded_hist_r_1_hist_8_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_8_folded_hist; + tables_3_io_update_folded_hist_r_1_hist_5_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_5_folded_hist; + end + tables_0_io_update_reset_u_1_REG <= updateResetU_1; + tables_0_io_update_mask_1_REG <= updateMask_1_0; + tables_1_io_update_reset_u_1_REG <= updateResetU_1; + tables_1_io_update_mask_1_REG <= updateMask_1_1; + tables_2_io_update_reset_u_1_REG <= updateResetU_1; + tables_2_io_update_mask_1_REG <= updateMask_1_2; + tables_3_io_update_reset_u_1_REG <= updateResetU_1; + tables_3_io_update_mask_1_REG <= updateMask_1_3; + REG_2_0 <= baseupdate_0; + REG_2_1 <= baseupdate_1; + if (baseupdate_0 | baseupdate_1) begin + r_0 <= io_update_bits_meta[65:64]; + r_1 <= io_update_bits_meta[67:66]; + bt_io_update_pc_r <= io_update_bits_pc; + r_1_0 <= updateTaken; + r_1_1 <= updateTaken_1; + end + if (io_s2_fire_3) begin + resp_meta_scMeta_tageTakens_0_r <= s2_tageTakens_dup_3_0; + resp_meta_scMeta_scUsed_0_r <= s2_provideds_0; + resp_meta_scMeta_scPreds_0_r <= _GEN_30; + r_2_0 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_0_ctrs_0_1 : s2_scResps_r_0_ctrs_0_0; + r_2_1 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_1_ctrs_0_1 : s2_scResps_r_1_ctrs_0_0; + r_2_2 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_2_ctrs_0_1 : s2_scResps_r_2_ctrs_0_0; + r_2_3 <= s2_tageTakens_dup_3_0 ? s2_scResps_r_3_ctrs_0_1 : s2_scResps_r_3_ctrs_0_0; + s3_pred_dup_3 <= s2_pred; + resp_meta_scMeta_tageTakens_1_r <= s2_tageTakens_dup_3_1; + resp_meta_scMeta_scUsed_1_r <= s2_provideds_1; + resp_meta_scMeta_scPreds_1_r <= _GEN_39; + r_3_0 <= + s2_tageTakens_dup_3_1 ? s2_scResps_r_1_0_ctrs_1_1 : s2_scResps_r_1_0_ctrs_1_0; + r_3_1 <= + s2_tageTakens_dup_3_1 ? s2_scResps_r_1_1_ctrs_1_1 : s2_scResps_r_1_1_ctrs_1_0; + r_3_2 <= + s2_tageTakens_dup_3_1 ? s2_scResps_r_1_2_ctrs_1_1 : s2_scResps_r_1_2_ctrs_1_0; + r_3_3 <= + s2_tageTakens_dup_3_1 ? s2_scResps_r_1_3_ctrs_1_1 : s2_scResps_r_1_3_ctrs_1_0; + s3_pred_dup_3_1 <= s2_pred_1; + end + if (io_s2_fire_0) begin + s3_pred_dup_0 <= s2_pred; + s3_pred_dup_0_1 <= s2_pred_1; + end + if (io_s2_fire_2) begin + s3_pred_dup_2 <= s2_pred; + s3_pred_dup_2_1 <= s2_pred_1; + end + sc_enable_dup_REG <= io_ctrl_sc_enable; + sc_enable_dup_REG_1 <= io_ctrl_sc_enable; + scTables_0_io_update_mask_0_REG <= scUpdateMask_0_3; + if (scUpdateMask_0_3 | scUpdateMask_1_3) begin + scTables_0_io_update_tagePreds_0_r <= io_update_bits_meta[52]; + scTables_0_io_update_takens_0_r <= io_update_bits_br_taken_mask_0; + scTables_0_io_update_oldCtrs_0_r <= io_update_bits_meta[5:0]; + scTables_0_io_update_tagePreds_1_r <= io_update_bits_meta[53]; + scTables_0_io_update_takens_1_r <= io_update_bits_br_taken_mask_1; + scTables_0_io_update_oldCtrs_1_r <= io_update_bits_meta[29:24]; + scTables_0_io_update_pc_r_1 <= io_update_bits_pc; + end + scTables_1_io_update_mask_0_REG <= scUpdateMask_0_3; + if (scUpdateMask_0_3 | scUpdateMask_1_3) begin + scTables_1_io_update_tagePreds_0_r <= io_update_bits_meta[52]; + scTables_1_io_update_takens_0_r <= io_update_bits_br_taken_mask_0; + scTables_1_io_update_oldCtrs_0_r <= io_update_bits_meta[11:6]; + scTables_1_io_update_tagePreds_1_r <= io_update_bits_meta[53]; + scTables_1_io_update_takens_1_r <= io_update_bits_br_taken_mask_1; + scTables_1_io_update_oldCtrs_1_r <= io_update_bits_meta[35:30]; + scTables_1_io_update_pc_r_1 <= io_update_bits_pc; + scTables_1_io_update_folded_hist_r_1_hist_12_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_12_folded_hist; + end + scTables_2_io_update_mask_0_REG <= scUpdateMask_0_3; + if (scUpdateMask_0_3 | scUpdateMask_1_3) begin + scTables_2_io_update_tagePreds_0_r <= io_update_bits_meta[52]; + scTables_2_io_update_takens_0_r <= io_update_bits_br_taken_mask_0; + scTables_2_io_update_oldCtrs_0_r <= io_update_bits_meta[17:12]; + scTables_2_io_update_tagePreds_1_r <= io_update_bits_meta[53]; + scTables_2_io_update_takens_1_r <= io_update_bits_br_taken_mask_1; + scTables_2_io_update_oldCtrs_1_r <= io_update_bits_meta[41:36]; + scTables_2_io_update_pc_r_1 <= io_update_bits_pc; + scTables_2_io_update_folded_hist_r_1_hist_11_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_11_folded_hist; + end + scTables_3_io_update_mask_0_REG <= scUpdateMask_0_3; + if (scUpdateMask_0_3 | scUpdateMask_1_3) begin + scTables_3_io_update_tagePreds_0_r <= io_update_bits_meta[52]; + scTables_3_io_update_takens_0_r <= io_update_bits_br_taken_mask_0; + scTables_3_io_update_oldCtrs_0_r <= io_update_bits_meta[23:18]; + scTables_3_io_update_tagePreds_1_r <= io_update_bits_meta[53]; + scTables_3_io_update_takens_1_r <= io_update_bits_br_taken_mask_1; + scTables_3_io_update_oldCtrs_1_r <= io_update_bits_meta[47:42]; + scTables_3_io_update_pc_r_1 <= io_update_bits_pc; + scTables_3_io_update_folded_hist_r_1_hist_2_folded_hist <= + io_update_bits_spec_info_folded_hist_hist_2_folded_hist; + end + scTables_0_io_update_mask_1_REG <= scUpdateMask_1_3; + scTables_1_io_update_mask_1_REG <= scUpdateMask_1_3; + scTables_2_io_update_mask_1_REG <= scUpdateMask_1_3; + scTables_3_io_update_mask_1_REG <= scUpdateMask_1_3; + io_perf_0_value_REG <= + 2'({1'h0, io_update_bits_meta[84]} + {1'h0, io_update_bits_meta[87]}); + io_perf_0_value_REG_1 <= io_perf_0_value_REG; + io_perf_1_value_REG <= + 2'({1'h0, _GEN_35 & _update_on_mispred_0_T} + + {1'h0, _GEN_44 & _update_on_mispred_1_T}); + io_perf_1_value_REG_1 <= io_perf_1_value_REG; + io_perf_2_value_REG <= + 2'({1'h0, _GEN_35 & io_update_bits_meta[48] == io_update_bits_br_taken_mask_0} + + {1'h0, _GEN_44 & io_update_bits_meta[49] == io_update_bits_br_taken_mask_1}); + io_perf_2_value_REG_1 <= io_perf_2_value_REG; + end // always @(posedge) + wire [3:0] _allocFailureMask_T = ~(io_update_bits_meta[59:56]); + wire [1:0] _GEN_47 = {1'h0, _allocFailureMask_T[0] & longerHistoryTableMask[0]}; + wire [1:0] _GEN_48 = {1'h0, _allocFailureMask_T[1] & longerHistoryTableMask[1]}; + wire [1:0] _GEN_49 = {1'h0, _allocFailureMask_T[2] & longerHistoryTableMask[2]}; + wire [1:0] _GEN_50 = {1'h0, _allocFailureMask_T[3] & longerHistoryTableMask[3]}; + wire [1:0] _GEN_51 = {1'h0, _firstEntry_T}; + wire [1:0] _GEN_52 = {1'h0, _firstEntry_T_1}; + wire [1:0] _GEN_53 = {1'h0, _firstEntry_T_2}; + wire [1:0] _GEN_54 = {1'h0, io_update_bits_meta[59] & longerHistoryTableMask[3]}; + wire tickInc = + 3'({1'h0, 2'(_GEN_47 + _GEN_48)} + + {1'h0, + 2'(_GEN_49 + + _GEN_50)}) > 3'({1'h0, 2'(_GEN_51 + _GEN_52)} + + {1'h0, 2'(_GEN_53 + _GEN_54)}); + wire [6:0] _GEN_55 = + {4'h0, + 3'(3'({1'h0, 2'(_GEN_47 + _GEN_48)} + {1'h0, 2'(_GEN_49 + _GEN_50)}) + - (3'({1'h0, 2'(_GEN_51 + _GEN_52)} + {1'h0, 2'(_GEN_53 + _GEN_54)})))}; + wire tickDec = + 3'({1'h0, 2'(_GEN_51 + _GEN_52)} + + {1'h0, + 2'(_GEN_53 + + _GEN_54)}) > 3'({1'h0, 2'(_GEN_47 + _GEN_48)} + + {1'h0, 2'(_GEN_49 + _GEN_50)}); + wire [6:0] _GEN_56 = + {4'h0, + 3'(3'({1'h0, 2'(_GEN_51 + _GEN_52)} + {1'h0, 2'(_GEN_53 + _GEN_54)}) + - (3'({1'h0, 2'(_GEN_47 + _GEN_48)} + {1'h0, 2'(_GEN_49 + _GEN_50)})))}; + wire [3:0] _allocFailureMask_T_1 = ~(io_update_bits_meta[63:60]); + wire [1:0] _GEN_57 = {1'h0, _allocFailureMask_T_1[0] & longerHistoryTableMask_1[0]}; + wire [1:0] _GEN_58 = {1'h0, _allocFailureMask_T_1[1] & longerHistoryTableMask_1[1]}; + wire [1:0] _GEN_59 = {1'h0, _allocFailureMask_T_1[2] & longerHistoryTableMask_1[2]}; + wire [1:0] _GEN_60 = {1'h0, _allocFailureMask_T_1[3] & longerHistoryTableMask_1[3]}; + wire [1:0] _GEN_61 = {1'h0, _firstEntry_T_6}; + wire [1:0] _GEN_62 = {1'h0, _firstEntry_T_7}; + wire [1:0] _GEN_63 = {1'h0, _firstEntry_T_8}; + wire [1:0] _GEN_64 = {1'h0, io_update_bits_meta[63] & longerHistoryTableMask_1[3]}; + wire tickInc_1 = + 3'({1'h0, 2'(_GEN_57 + _GEN_58)} + + {1'h0, + 2'(_GEN_59 + + _GEN_60)}) > 3'({1'h0, 2'(_GEN_61 + _GEN_62)} + + {1'h0, 2'(_GEN_63 + _GEN_64)}); + wire [6:0] _GEN_65 = + {4'h0, + 3'(3'({1'h0, 2'(_GEN_57 + _GEN_58)} + {1'h0, 2'(_GEN_59 + _GEN_60)}) + - (3'({1'h0, 2'(_GEN_61 + _GEN_62)} + {1'h0, 2'(_GEN_63 + _GEN_64)})))}; + wire tickDec_1 = + 3'({1'h0, 2'(_GEN_61 + _GEN_62)} + + {1'h0, + 2'(_GEN_63 + + _GEN_64)}) > 3'({1'h0, 2'(_GEN_57 + _GEN_58)} + + {1'h0, 2'(_GEN_59 + _GEN_60)}); + wire [6:0] _GEN_66 = + {4'h0, + 3'(3'({1'h0, 2'(_GEN_61 + _GEN_62)} + {1'h0, 2'(_GEN_63 + _GEN_64)}) + - (3'({1'h0, 2'(_GEN_57 + _GEN_58)} + {1'h0, 2'(_GEN_59 + _GEN_60)})))}; + wire _newThres_newCtr_T = (&scThresholds_0_ctr) & _update_on_mispred_0_T; + wire _newThres_newCtr_T_2 = scThresholds_0_ctr == 5'h0 & ~_update_on_mispred_0_T; + wire [4:0] _newThres_newCtr_T_3 = 5'(scThresholds_0_ctr + 5'h1); + wire [4:0] _newThres_newCtr_T_5 = 5'(scThresholds_0_ctr - 5'h1); + wire _GEN_67 = io_update_bits_meta[48] == io_update_bits_br_taken_mask_0; + wire [4:0] newThres_newCtr = + _newThres_newCtr_T + ? 5'h1F + : _newThres_newCtr_T_2 + ? 5'h0 + : _GEN_67 ? _newThres_newCtr_T_5 : _newThres_newCtr_T_3; + wire _newThres_res_ctr_T_4 = newThres_newCtr == 5'h0; + wire _newThres_newCtr_T_9 = (&scThresholds_1_ctr) & _update_on_mispred_1_T; + wire _newThres_newCtr_T_11 = + scThresholds_1_ctr == 5'h0 & ~_update_on_mispred_1_T; + wire [4:0] _newThres_newCtr_T_12 = 5'(scThresholds_1_ctr + 5'h1); + wire [4:0] _newThres_newCtr_T_14 = 5'(scThresholds_1_ctr - 5'h1); + wire _GEN_68 = io_update_bits_meta[49] == io_update_bits_br_taken_mask_1; + wire [4:0] newThres_newCtr_1 = + _newThres_newCtr_T_9 + ? 5'h1F + : _newThres_newCtr_T_11 + ? 5'h0 + : _GEN_68 ? _newThres_newCtr_T_14 : _newThres_newCtr_T_12; + wire _newThres_res_ctr_T_11 = newThres_newCtr_1 == 5'h0; + wire [3:0] updateUseAltCtr = + (io_update_bits_pc[7:1] == 7'h0 ? useAltOnNaCtrs_0_0 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1 ? useAltOnNaCtrs_0_1 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2 ? useAltOnNaCtrs_0_2 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3 ? useAltOnNaCtrs_0_3 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4 ? useAltOnNaCtrs_0_4 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5 ? useAltOnNaCtrs_0_5 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6 ? useAltOnNaCtrs_0_6 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7 ? useAltOnNaCtrs_0_7 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h8 ? useAltOnNaCtrs_0_8 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h9 ? useAltOnNaCtrs_0_9 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hA ? useAltOnNaCtrs_0_10 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hB ? useAltOnNaCtrs_0_11 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hC ? useAltOnNaCtrs_0_12 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hD ? useAltOnNaCtrs_0_13 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hE ? useAltOnNaCtrs_0_14 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hF ? useAltOnNaCtrs_0_15 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h10 ? useAltOnNaCtrs_0_16 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h11 ? useAltOnNaCtrs_0_17 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h12 ? useAltOnNaCtrs_0_18 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h13 ? useAltOnNaCtrs_0_19 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h14 ? useAltOnNaCtrs_0_20 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h15 ? useAltOnNaCtrs_0_21 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h16 ? useAltOnNaCtrs_0_22 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h17 ? useAltOnNaCtrs_0_23 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h18 ? useAltOnNaCtrs_0_24 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h19 ? useAltOnNaCtrs_0_25 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1A ? useAltOnNaCtrs_0_26 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1B ? useAltOnNaCtrs_0_27 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1C ? useAltOnNaCtrs_0_28 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1D ? useAltOnNaCtrs_0_29 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1E ? useAltOnNaCtrs_0_30 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1F ? useAltOnNaCtrs_0_31 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h20 ? useAltOnNaCtrs_0_32 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h21 ? useAltOnNaCtrs_0_33 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h22 ? useAltOnNaCtrs_0_34 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h23 ? useAltOnNaCtrs_0_35 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h24 ? useAltOnNaCtrs_0_36 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h25 ? useAltOnNaCtrs_0_37 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h26 ? useAltOnNaCtrs_0_38 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h27 ? useAltOnNaCtrs_0_39 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h28 ? useAltOnNaCtrs_0_40 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h29 ? useAltOnNaCtrs_0_41 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2A ? useAltOnNaCtrs_0_42 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2B ? useAltOnNaCtrs_0_43 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2C ? useAltOnNaCtrs_0_44 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2D ? useAltOnNaCtrs_0_45 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2E ? useAltOnNaCtrs_0_46 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2F ? useAltOnNaCtrs_0_47 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h30 ? useAltOnNaCtrs_0_48 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h31 ? useAltOnNaCtrs_0_49 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h32 ? useAltOnNaCtrs_0_50 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h33 ? useAltOnNaCtrs_0_51 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h34 ? useAltOnNaCtrs_0_52 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h35 ? useAltOnNaCtrs_0_53 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h36 ? useAltOnNaCtrs_0_54 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h37 ? useAltOnNaCtrs_0_55 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h38 ? useAltOnNaCtrs_0_56 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h39 ? useAltOnNaCtrs_0_57 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3A ? useAltOnNaCtrs_0_58 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3B ? useAltOnNaCtrs_0_59 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3C ? useAltOnNaCtrs_0_60 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3D ? useAltOnNaCtrs_0_61 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3E ? useAltOnNaCtrs_0_62 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3F ? useAltOnNaCtrs_0_63 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h40 ? useAltOnNaCtrs_0_64 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h41 ? useAltOnNaCtrs_0_65 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h42 ? useAltOnNaCtrs_0_66 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h43 ? useAltOnNaCtrs_0_67 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h44 ? useAltOnNaCtrs_0_68 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h45 ? useAltOnNaCtrs_0_69 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h46 ? useAltOnNaCtrs_0_70 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h47 ? useAltOnNaCtrs_0_71 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h48 ? useAltOnNaCtrs_0_72 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h49 ? useAltOnNaCtrs_0_73 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4A ? useAltOnNaCtrs_0_74 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4B ? useAltOnNaCtrs_0_75 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4C ? useAltOnNaCtrs_0_76 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4D ? useAltOnNaCtrs_0_77 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4E ? useAltOnNaCtrs_0_78 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4F ? useAltOnNaCtrs_0_79 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h50 ? useAltOnNaCtrs_0_80 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h51 ? useAltOnNaCtrs_0_81 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h52 ? useAltOnNaCtrs_0_82 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h53 ? useAltOnNaCtrs_0_83 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h54 ? useAltOnNaCtrs_0_84 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h55 ? useAltOnNaCtrs_0_85 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h56 ? useAltOnNaCtrs_0_86 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h57 ? useAltOnNaCtrs_0_87 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h58 ? useAltOnNaCtrs_0_88 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h59 ? useAltOnNaCtrs_0_89 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5A ? useAltOnNaCtrs_0_90 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5B ? useAltOnNaCtrs_0_91 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5C ? useAltOnNaCtrs_0_92 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5D ? useAltOnNaCtrs_0_93 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5E ? useAltOnNaCtrs_0_94 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5F ? useAltOnNaCtrs_0_95 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h60 ? useAltOnNaCtrs_0_96 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h61 ? useAltOnNaCtrs_0_97 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h62 ? useAltOnNaCtrs_0_98 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h63 ? useAltOnNaCtrs_0_99 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h64 ? useAltOnNaCtrs_0_100 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h65 ? useAltOnNaCtrs_0_101 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h66 ? useAltOnNaCtrs_0_102 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h67 ? useAltOnNaCtrs_0_103 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h68 ? useAltOnNaCtrs_0_104 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h69 ? useAltOnNaCtrs_0_105 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6A ? useAltOnNaCtrs_0_106 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6B ? useAltOnNaCtrs_0_107 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6C ? useAltOnNaCtrs_0_108 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6D ? useAltOnNaCtrs_0_109 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6E ? useAltOnNaCtrs_0_110 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6F ? useAltOnNaCtrs_0_111 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h70 ? useAltOnNaCtrs_0_112 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h71 ? useAltOnNaCtrs_0_113 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h72 ? useAltOnNaCtrs_0_114 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h73 ? useAltOnNaCtrs_0_115 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h74 ? useAltOnNaCtrs_0_116 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h75 ? useAltOnNaCtrs_0_117 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h76 ? useAltOnNaCtrs_0_118 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h77 ? useAltOnNaCtrs_0_119 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h78 ? useAltOnNaCtrs_0_120 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h79 ? useAltOnNaCtrs_0_121 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7A ? useAltOnNaCtrs_0_122 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7B ? useAltOnNaCtrs_0_123 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7C ? useAltOnNaCtrs_0_124 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7D ? useAltOnNaCtrs_0_125 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7E ? useAltOnNaCtrs_0_126 : 4'h0) + | ((&(io_update_bits_pc[7:1])) ? useAltOnNaCtrs_0_127 : 4'h0); + wire updateAltCorrect = io_update_bits_meta[65] == updateTaken; + wire _GEN_69 = + io_update_bits_meta[84] + & (io_update_bits_meta[76:74] == 3'h4 | io_update_bits_meta[76:74] == 3'h3) + & io_update_bits_meta[68]; + wire _newCtr_T = (&updateUseAltCtr) & updateAltCorrect; + wire _newCtr_T_2 = updateUseAltCtr == 4'h0 & ~updateAltCorrect; + wire [3:0] _newCtr_T_3 = 4'(updateUseAltCtr + 4'h1); + wire [3:0] _newCtr_T_5 = 4'(updateUseAltCtr - 4'h1); + wire [3:0] updateUseAltCtr_1 = + (io_update_bits_pc[7:1] == 7'h0 ? useAltOnNaCtrs_1_0 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1 ? useAltOnNaCtrs_1_1 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2 ? useAltOnNaCtrs_1_2 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3 ? useAltOnNaCtrs_1_3 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4 ? useAltOnNaCtrs_1_4 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5 ? useAltOnNaCtrs_1_5 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6 ? useAltOnNaCtrs_1_6 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7 ? useAltOnNaCtrs_1_7 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h8 ? useAltOnNaCtrs_1_8 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h9 ? useAltOnNaCtrs_1_9 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hA ? useAltOnNaCtrs_1_10 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hB ? useAltOnNaCtrs_1_11 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hC ? useAltOnNaCtrs_1_12 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hD ? useAltOnNaCtrs_1_13 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hE ? useAltOnNaCtrs_1_14 : 4'h0) + | (io_update_bits_pc[7:1] == 7'hF ? useAltOnNaCtrs_1_15 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h10 ? useAltOnNaCtrs_1_16 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h11 ? useAltOnNaCtrs_1_17 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h12 ? useAltOnNaCtrs_1_18 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h13 ? useAltOnNaCtrs_1_19 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h14 ? useAltOnNaCtrs_1_20 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h15 ? useAltOnNaCtrs_1_21 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h16 ? useAltOnNaCtrs_1_22 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h17 ? useAltOnNaCtrs_1_23 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h18 ? useAltOnNaCtrs_1_24 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h19 ? useAltOnNaCtrs_1_25 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1A ? useAltOnNaCtrs_1_26 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1B ? useAltOnNaCtrs_1_27 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1C ? useAltOnNaCtrs_1_28 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1D ? useAltOnNaCtrs_1_29 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1E ? useAltOnNaCtrs_1_30 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h1F ? useAltOnNaCtrs_1_31 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h20 ? useAltOnNaCtrs_1_32 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h21 ? useAltOnNaCtrs_1_33 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h22 ? useAltOnNaCtrs_1_34 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h23 ? useAltOnNaCtrs_1_35 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h24 ? useAltOnNaCtrs_1_36 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h25 ? useAltOnNaCtrs_1_37 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h26 ? useAltOnNaCtrs_1_38 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h27 ? useAltOnNaCtrs_1_39 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h28 ? useAltOnNaCtrs_1_40 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h29 ? useAltOnNaCtrs_1_41 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2A ? useAltOnNaCtrs_1_42 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2B ? useAltOnNaCtrs_1_43 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2C ? useAltOnNaCtrs_1_44 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2D ? useAltOnNaCtrs_1_45 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2E ? useAltOnNaCtrs_1_46 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h2F ? useAltOnNaCtrs_1_47 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h30 ? useAltOnNaCtrs_1_48 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h31 ? useAltOnNaCtrs_1_49 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h32 ? useAltOnNaCtrs_1_50 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h33 ? useAltOnNaCtrs_1_51 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h34 ? useAltOnNaCtrs_1_52 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h35 ? useAltOnNaCtrs_1_53 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h36 ? useAltOnNaCtrs_1_54 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h37 ? useAltOnNaCtrs_1_55 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h38 ? useAltOnNaCtrs_1_56 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h39 ? useAltOnNaCtrs_1_57 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3A ? useAltOnNaCtrs_1_58 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3B ? useAltOnNaCtrs_1_59 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3C ? useAltOnNaCtrs_1_60 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3D ? useAltOnNaCtrs_1_61 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3E ? useAltOnNaCtrs_1_62 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h3F ? useAltOnNaCtrs_1_63 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h40 ? useAltOnNaCtrs_1_64 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h41 ? useAltOnNaCtrs_1_65 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h42 ? useAltOnNaCtrs_1_66 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h43 ? useAltOnNaCtrs_1_67 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h44 ? useAltOnNaCtrs_1_68 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h45 ? useAltOnNaCtrs_1_69 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h46 ? useAltOnNaCtrs_1_70 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h47 ? useAltOnNaCtrs_1_71 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h48 ? useAltOnNaCtrs_1_72 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h49 ? useAltOnNaCtrs_1_73 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4A ? useAltOnNaCtrs_1_74 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4B ? useAltOnNaCtrs_1_75 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4C ? useAltOnNaCtrs_1_76 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4D ? useAltOnNaCtrs_1_77 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4E ? useAltOnNaCtrs_1_78 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h4F ? useAltOnNaCtrs_1_79 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h50 ? useAltOnNaCtrs_1_80 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h51 ? useAltOnNaCtrs_1_81 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h52 ? useAltOnNaCtrs_1_82 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h53 ? useAltOnNaCtrs_1_83 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h54 ? useAltOnNaCtrs_1_84 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h55 ? useAltOnNaCtrs_1_85 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h56 ? useAltOnNaCtrs_1_86 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h57 ? useAltOnNaCtrs_1_87 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h58 ? useAltOnNaCtrs_1_88 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h59 ? useAltOnNaCtrs_1_89 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5A ? useAltOnNaCtrs_1_90 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5B ? useAltOnNaCtrs_1_91 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5C ? useAltOnNaCtrs_1_92 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5D ? useAltOnNaCtrs_1_93 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5E ? useAltOnNaCtrs_1_94 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h5F ? useAltOnNaCtrs_1_95 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h60 ? useAltOnNaCtrs_1_96 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h61 ? useAltOnNaCtrs_1_97 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h62 ? useAltOnNaCtrs_1_98 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h63 ? useAltOnNaCtrs_1_99 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h64 ? useAltOnNaCtrs_1_100 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h65 ? useAltOnNaCtrs_1_101 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h66 ? useAltOnNaCtrs_1_102 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h67 ? useAltOnNaCtrs_1_103 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h68 ? useAltOnNaCtrs_1_104 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h69 ? useAltOnNaCtrs_1_105 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6A ? useAltOnNaCtrs_1_106 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6B ? useAltOnNaCtrs_1_107 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6C ? useAltOnNaCtrs_1_108 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6D ? useAltOnNaCtrs_1_109 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6E ? useAltOnNaCtrs_1_110 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h6F ? useAltOnNaCtrs_1_111 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h70 ? useAltOnNaCtrs_1_112 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h71 ? useAltOnNaCtrs_1_113 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h72 ? useAltOnNaCtrs_1_114 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h73 ? useAltOnNaCtrs_1_115 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h74 ? useAltOnNaCtrs_1_116 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h75 ? useAltOnNaCtrs_1_117 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h76 ? useAltOnNaCtrs_1_118 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h77 ? useAltOnNaCtrs_1_119 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h78 ? useAltOnNaCtrs_1_120 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h79 ? useAltOnNaCtrs_1_121 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7A ? useAltOnNaCtrs_1_122 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7B ? useAltOnNaCtrs_1_123 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7C ? useAltOnNaCtrs_1_124 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7D ? useAltOnNaCtrs_1_125 : 4'h0) + | (io_update_bits_pc[7:1] == 7'h7E ? useAltOnNaCtrs_1_126 : 4'h0) + | ((&(io_update_bits_pc[7:1])) ? useAltOnNaCtrs_1_127 : 4'h0); + wire updateAltCorrect_1 = io_update_bits_meta[67] == updateTaken_1; + wire _GEN_70 = + io_update_bits_meta[87] + & (io_update_bits_meta[81:79] == 3'h4 | io_update_bits_meta[81:79] == 3'h3) + & io_update_bits_meta[69]; + wire _newCtr_T_9 = (&updateUseAltCtr_1) & updateAltCorrect_1; + wire _newCtr_T_11 = updateUseAltCtr_1 == 4'h0 & ~updateAltCorrect_1; + wire [3:0] _newCtr_T_12 = 4'(updateUseAltCtr_1 + 4'h1); + wire [3:0] _newCtr_T_14 = 4'(updateUseAltCtr_1 - 4'h1); + wire [9:0] _sumAbs_T_4 = $signed(sum) < 10'sh0 ? 10'(10'h0 - sum) : sum; + wire [9:0] _sumAbs_T_9 = $signed(sum_1) < 10'sh0 ? 10'(10'h0 - sum_1) : sum_1; + always @(posedge clock or posedge reset) begin + if (reset) begin + bankTickCtrDistanceToTops_0 <= 7'h7F; + bankTickCtrDistanceToTops_1 <= 7'h7F; + bankTickCtrs_0 <= 7'h0; + bankTickCtrs_1 <= 7'h0; + useAltOnNaCtrs_0_0 <= 4'h8; + useAltOnNaCtrs_0_1 <= 4'h8; + useAltOnNaCtrs_0_2 <= 4'h8; + useAltOnNaCtrs_0_3 <= 4'h8; + useAltOnNaCtrs_0_4 <= 4'h8; + useAltOnNaCtrs_0_5 <= 4'h8; + useAltOnNaCtrs_0_6 <= 4'h8; + useAltOnNaCtrs_0_7 <= 4'h8; + useAltOnNaCtrs_0_8 <= 4'h8; + useAltOnNaCtrs_0_9 <= 4'h8; + useAltOnNaCtrs_0_10 <= 4'h8; + useAltOnNaCtrs_0_11 <= 4'h8; + useAltOnNaCtrs_0_12 <= 4'h8; + useAltOnNaCtrs_0_13 <= 4'h8; + useAltOnNaCtrs_0_14 <= 4'h8; + useAltOnNaCtrs_0_15 <= 4'h8; + useAltOnNaCtrs_0_16 <= 4'h8; + useAltOnNaCtrs_0_17 <= 4'h8; + useAltOnNaCtrs_0_18 <= 4'h8; + useAltOnNaCtrs_0_19 <= 4'h8; + useAltOnNaCtrs_0_20 <= 4'h8; + useAltOnNaCtrs_0_21 <= 4'h8; + useAltOnNaCtrs_0_22 <= 4'h8; + useAltOnNaCtrs_0_23 <= 4'h8; + useAltOnNaCtrs_0_24 <= 4'h8; + useAltOnNaCtrs_0_25 <= 4'h8; + useAltOnNaCtrs_0_26 <= 4'h8; + useAltOnNaCtrs_0_27 <= 4'h8; + useAltOnNaCtrs_0_28 <= 4'h8; + useAltOnNaCtrs_0_29 <= 4'h8; + useAltOnNaCtrs_0_30 <= 4'h8; + useAltOnNaCtrs_0_31 <= 4'h8; + useAltOnNaCtrs_0_32 <= 4'h8; + useAltOnNaCtrs_0_33 <= 4'h8; + useAltOnNaCtrs_0_34 <= 4'h8; + useAltOnNaCtrs_0_35 <= 4'h8; + useAltOnNaCtrs_0_36 <= 4'h8; + useAltOnNaCtrs_0_37 <= 4'h8; + useAltOnNaCtrs_0_38 <= 4'h8; + useAltOnNaCtrs_0_39 <= 4'h8; + useAltOnNaCtrs_0_40 <= 4'h8; + useAltOnNaCtrs_0_41 <= 4'h8; + useAltOnNaCtrs_0_42 <= 4'h8; + useAltOnNaCtrs_0_43 <= 4'h8; + useAltOnNaCtrs_0_44 <= 4'h8; + useAltOnNaCtrs_0_45 <= 4'h8; + useAltOnNaCtrs_0_46 <= 4'h8; + useAltOnNaCtrs_0_47 <= 4'h8; + useAltOnNaCtrs_0_48 <= 4'h8; + useAltOnNaCtrs_0_49 <= 4'h8; + useAltOnNaCtrs_0_50 <= 4'h8; + useAltOnNaCtrs_0_51 <= 4'h8; + useAltOnNaCtrs_0_52 <= 4'h8; + useAltOnNaCtrs_0_53 <= 4'h8; + useAltOnNaCtrs_0_54 <= 4'h8; + useAltOnNaCtrs_0_55 <= 4'h8; + useAltOnNaCtrs_0_56 <= 4'h8; + useAltOnNaCtrs_0_57 <= 4'h8; + useAltOnNaCtrs_0_58 <= 4'h8; + useAltOnNaCtrs_0_59 <= 4'h8; + useAltOnNaCtrs_0_60 <= 4'h8; + useAltOnNaCtrs_0_61 <= 4'h8; + useAltOnNaCtrs_0_62 <= 4'h8; + useAltOnNaCtrs_0_63 <= 4'h8; + useAltOnNaCtrs_0_64 <= 4'h8; + useAltOnNaCtrs_0_65 <= 4'h8; + useAltOnNaCtrs_0_66 <= 4'h8; + useAltOnNaCtrs_0_67 <= 4'h8; + useAltOnNaCtrs_0_68 <= 4'h8; + useAltOnNaCtrs_0_69 <= 4'h8; + useAltOnNaCtrs_0_70 <= 4'h8; + useAltOnNaCtrs_0_71 <= 4'h8; + useAltOnNaCtrs_0_72 <= 4'h8; + useAltOnNaCtrs_0_73 <= 4'h8; + useAltOnNaCtrs_0_74 <= 4'h8; + useAltOnNaCtrs_0_75 <= 4'h8; + useAltOnNaCtrs_0_76 <= 4'h8; + useAltOnNaCtrs_0_77 <= 4'h8; + useAltOnNaCtrs_0_78 <= 4'h8; + useAltOnNaCtrs_0_79 <= 4'h8; + useAltOnNaCtrs_0_80 <= 4'h8; + useAltOnNaCtrs_0_81 <= 4'h8; + useAltOnNaCtrs_0_82 <= 4'h8; + useAltOnNaCtrs_0_83 <= 4'h8; + useAltOnNaCtrs_0_84 <= 4'h8; + useAltOnNaCtrs_0_85 <= 4'h8; + useAltOnNaCtrs_0_86 <= 4'h8; + useAltOnNaCtrs_0_87 <= 4'h8; + useAltOnNaCtrs_0_88 <= 4'h8; + useAltOnNaCtrs_0_89 <= 4'h8; + useAltOnNaCtrs_0_90 <= 4'h8; + useAltOnNaCtrs_0_91 <= 4'h8; + useAltOnNaCtrs_0_92 <= 4'h8; + useAltOnNaCtrs_0_93 <= 4'h8; + useAltOnNaCtrs_0_94 <= 4'h8; + useAltOnNaCtrs_0_95 <= 4'h8; + useAltOnNaCtrs_0_96 <= 4'h8; + useAltOnNaCtrs_0_97 <= 4'h8; + useAltOnNaCtrs_0_98 <= 4'h8; + useAltOnNaCtrs_0_99 <= 4'h8; + useAltOnNaCtrs_0_100 <= 4'h8; + useAltOnNaCtrs_0_101 <= 4'h8; + useAltOnNaCtrs_0_102 <= 4'h8; + useAltOnNaCtrs_0_103 <= 4'h8; + useAltOnNaCtrs_0_104 <= 4'h8; + useAltOnNaCtrs_0_105 <= 4'h8; + useAltOnNaCtrs_0_106 <= 4'h8; + useAltOnNaCtrs_0_107 <= 4'h8; + useAltOnNaCtrs_0_108 <= 4'h8; + useAltOnNaCtrs_0_109 <= 4'h8; + useAltOnNaCtrs_0_110 <= 4'h8; + useAltOnNaCtrs_0_111 <= 4'h8; + useAltOnNaCtrs_0_112 <= 4'h8; + useAltOnNaCtrs_0_113 <= 4'h8; + useAltOnNaCtrs_0_114 <= 4'h8; + useAltOnNaCtrs_0_115 <= 4'h8; + useAltOnNaCtrs_0_116 <= 4'h8; + useAltOnNaCtrs_0_117 <= 4'h8; + useAltOnNaCtrs_0_118 <= 4'h8; + useAltOnNaCtrs_0_119 <= 4'h8; + useAltOnNaCtrs_0_120 <= 4'h8; + useAltOnNaCtrs_0_121 <= 4'h8; + useAltOnNaCtrs_0_122 <= 4'h8; + useAltOnNaCtrs_0_123 <= 4'h8; + useAltOnNaCtrs_0_124 <= 4'h8; + useAltOnNaCtrs_0_125 <= 4'h8; + useAltOnNaCtrs_0_126 <= 4'h8; + useAltOnNaCtrs_0_127 <= 4'h8; + useAltOnNaCtrs_1_0 <= 4'h8; + useAltOnNaCtrs_1_1 <= 4'h8; + useAltOnNaCtrs_1_2 <= 4'h8; + useAltOnNaCtrs_1_3 <= 4'h8; + useAltOnNaCtrs_1_4 <= 4'h8; + useAltOnNaCtrs_1_5 <= 4'h8; + useAltOnNaCtrs_1_6 <= 4'h8; + useAltOnNaCtrs_1_7 <= 4'h8; + useAltOnNaCtrs_1_8 <= 4'h8; + useAltOnNaCtrs_1_9 <= 4'h8; + useAltOnNaCtrs_1_10 <= 4'h8; + useAltOnNaCtrs_1_11 <= 4'h8; + useAltOnNaCtrs_1_12 <= 4'h8; + useAltOnNaCtrs_1_13 <= 4'h8; + useAltOnNaCtrs_1_14 <= 4'h8; + useAltOnNaCtrs_1_15 <= 4'h8; + useAltOnNaCtrs_1_16 <= 4'h8; + useAltOnNaCtrs_1_17 <= 4'h8; + useAltOnNaCtrs_1_18 <= 4'h8; + useAltOnNaCtrs_1_19 <= 4'h8; + useAltOnNaCtrs_1_20 <= 4'h8; + useAltOnNaCtrs_1_21 <= 4'h8; + useAltOnNaCtrs_1_22 <= 4'h8; + useAltOnNaCtrs_1_23 <= 4'h8; + useAltOnNaCtrs_1_24 <= 4'h8; + useAltOnNaCtrs_1_25 <= 4'h8; + useAltOnNaCtrs_1_26 <= 4'h8; + useAltOnNaCtrs_1_27 <= 4'h8; + useAltOnNaCtrs_1_28 <= 4'h8; + useAltOnNaCtrs_1_29 <= 4'h8; + useAltOnNaCtrs_1_30 <= 4'h8; + useAltOnNaCtrs_1_31 <= 4'h8; + useAltOnNaCtrs_1_32 <= 4'h8; + useAltOnNaCtrs_1_33 <= 4'h8; + useAltOnNaCtrs_1_34 <= 4'h8; + useAltOnNaCtrs_1_35 <= 4'h8; + useAltOnNaCtrs_1_36 <= 4'h8; + useAltOnNaCtrs_1_37 <= 4'h8; + useAltOnNaCtrs_1_38 <= 4'h8; + useAltOnNaCtrs_1_39 <= 4'h8; + useAltOnNaCtrs_1_40 <= 4'h8; + useAltOnNaCtrs_1_41 <= 4'h8; + useAltOnNaCtrs_1_42 <= 4'h8; + useAltOnNaCtrs_1_43 <= 4'h8; + useAltOnNaCtrs_1_44 <= 4'h8; + useAltOnNaCtrs_1_45 <= 4'h8; + useAltOnNaCtrs_1_46 <= 4'h8; + useAltOnNaCtrs_1_47 <= 4'h8; + useAltOnNaCtrs_1_48 <= 4'h8; + useAltOnNaCtrs_1_49 <= 4'h8; + useAltOnNaCtrs_1_50 <= 4'h8; + useAltOnNaCtrs_1_51 <= 4'h8; + useAltOnNaCtrs_1_52 <= 4'h8; + useAltOnNaCtrs_1_53 <= 4'h8; + useAltOnNaCtrs_1_54 <= 4'h8; + useAltOnNaCtrs_1_55 <= 4'h8; + useAltOnNaCtrs_1_56 <= 4'h8; + useAltOnNaCtrs_1_57 <= 4'h8; + useAltOnNaCtrs_1_58 <= 4'h8; + useAltOnNaCtrs_1_59 <= 4'h8; + useAltOnNaCtrs_1_60 <= 4'h8; + useAltOnNaCtrs_1_61 <= 4'h8; + useAltOnNaCtrs_1_62 <= 4'h8; + useAltOnNaCtrs_1_63 <= 4'h8; + useAltOnNaCtrs_1_64 <= 4'h8; + useAltOnNaCtrs_1_65 <= 4'h8; + useAltOnNaCtrs_1_66 <= 4'h8; + useAltOnNaCtrs_1_67 <= 4'h8; + useAltOnNaCtrs_1_68 <= 4'h8; + useAltOnNaCtrs_1_69 <= 4'h8; + useAltOnNaCtrs_1_70 <= 4'h8; + useAltOnNaCtrs_1_71 <= 4'h8; + useAltOnNaCtrs_1_72 <= 4'h8; + useAltOnNaCtrs_1_73 <= 4'h8; + useAltOnNaCtrs_1_74 <= 4'h8; + useAltOnNaCtrs_1_75 <= 4'h8; + useAltOnNaCtrs_1_76 <= 4'h8; + useAltOnNaCtrs_1_77 <= 4'h8; + useAltOnNaCtrs_1_78 <= 4'h8; + useAltOnNaCtrs_1_79 <= 4'h8; + useAltOnNaCtrs_1_80 <= 4'h8; + useAltOnNaCtrs_1_81 <= 4'h8; + useAltOnNaCtrs_1_82 <= 4'h8; + useAltOnNaCtrs_1_83 <= 4'h8; + useAltOnNaCtrs_1_84 <= 4'h8; + useAltOnNaCtrs_1_85 <= 4'h8; + useAltOnNaCtrs_1_86 <= 4'h8; + useAltOnNaCtrs_1_87 <= 4'h8; + useAltOnNaCtrs_1_88 <= 4'h8; + useAltOnNaCtrs_1_89 <= 4'h8; + useAltOnNaCtrs_1_90 <= 4'h8; + useAltOnNaCtrs_1_91 <= 4'h8; + useAltOnNaCtrs_1_92 <= 4'h8; + useAltOnNaCtrs_1_93 <= 4'h8; + useAltOnNaCtrs_1_94 <= 4'h8; + useAltOnNaCtrs_1_95 <= 4'h8; + useAltOnNaCtrs_1_96 <= 4'h8; + useAltOnNaCtrs_1_97 <= 4'h8; + useAltOnNaCtrs_1_98 <= 4'h8; + useAltOnNaCtrs_1_99 <= 4'h8; + useAltOnNaCtrs_1_100 <= 4'h8; + useAltOnNaCtrs_1_101 <= 4'h8; + useAltOnNaCtrs_1_102 <= 4'h8; + useAltOnNaCtrs_1_103 <= 4'h8; + useAltOnNaCtrs_1_104 <= 4'h8; + useAltOnNaCtrs_1_105 <= 4'h8; + useAltOnNaCtrs_1_106 <= 4'h8; + useAltOnNaCtrs_1_107 <= 4'h8; + useAltOnNaCtrs_1_108 <= 4'h8; + useAltOnNaCtrs_1_109 <= 4'h8; + useAltOnNaCtrs_1_110 <= 4'h8; + useAltOnNaCtrs_1_111 <= 4'h8; + useAltOnNaCtrs_1_112 <= 4'h8; + useAltOnNaCtrs_1_113 <= 4'h8; + useAltOnNaCtrs_1_114 <= 4'h8; + useAltOnNaCtrs_1_115 <= 4'h8; + useAltOnNaCtrs_1_116 <= 4'h8; + useAltOnNaCtrs_1_117 <= 4'h8; + useAltOnNaCtrs_1_118 <= 4'h8; + useAltOnNaCtrs_1_119 <= 4'h8; + useAltOnNaCtrs_1_120 <= 4'h8; + useAltOnNaCtrs_1_121 <= 4'h8; + useAltOnNaCtrs_1_122 <= 4'h8; + useAltOnNaCtrs_1_123 <= 4'h8; + useAltOnNaCtrs_1_124 <= 4'h8; + useAltOnNaCtrs_1_125 <= 4'h8; + useAltOnNaCtrs_1_126 <= 4'h8; + useAltOnNaCtrs_1_127 <= 4'h8; + allocLFSR_lfsr <= 64'h1234567887654321; + allocLFSR_lfsr_1 <= 64'h1234567887654321; + scThresholds_0_ctr <= 5'h10; + scThresholds_0_thres <= 8'h6; + scThresholds_1_ctr <= 5'h10; + scThresholds_1_thres <= 8'h6; + end + else begin + if (needToAllocate) begin + if (&bankTickCtrs_0) begin + bankTickCtrDistanceToTops_0 <= 7'h7F; + bankTickCtrs_0 <= 7'h0; + end + else if (tickInc) begin + if (_GEN_55 >= bankTickCtrDistanceToTops_0 & tickInc) begin + bankTickCtrDistanceToTops_0 <= 7'h0; + bankTickCtrs_0 <= 7'h7F; + end + else begin + bankTickCtrDistanceToTops_0 <= 7'(bankTickCtrDistanceToTops_0 - _GEN_55); + bankTickCtrs_0 <= 7'(bankTickCtrs_0 + _GEN_55); + end + end + else if (tickDec) begin + if (_GEN_56 >= bankTickCtrs_0 & tickDec) begin + bankTickCtrDistanceToTops_0 <= 7'h7F; + bankTickCtrs_0 <= 7'h0; + end + else begin + bankTickCtrDistanceToTops_0 <= 7'(bankTickCtrDistanceToTops_0 + _GEN_56); + bankTickCtrs_0 <= 7'(bankTickCtrs_0 - _GEN_56); + end + end + end + if (needToAllocate_1) begin + if (&bankTickCtrs_1) begin + bankTickCtrDistanceToTops_1 <= 7'h7F; + bankTickCtrs_1 <= 7'h0; + end + else if (tickInc_1) begin + if (_GEN_65 >= bankTickCtrDistanceToTops_1 & tickInc_1) begin + bankTickCtrDistanceToTops_1 <= 7'h0; + bankTickCtrs_1 <= 7'h7F; + end + else begin + bankTickCtrDistanceToTops_1 <= 7'(bankTickCtrDistanceToTops_1 - _GEN_65); + bankTickCtrs_1 <= 7'(bankTickCtrs_1 + _GEN_65); + end + end + else if (tickDec_1) begin + if (_GEN_66 >= bankTickCtrs_1 & tickDec_1) begin + bankTickCtrDistanceToTops_1 <= 7'h7F; + bankTickCtrs_1 <= 7'h0; + end + else begin + bankTickCtrDistanceToTops_1 <= 7'(bankTickCtrDistanceToTops_1 + _GEN_66); + bankTickCtrs_1 <= 7'(bankTickCtrs_1 - _GEN_66); + end + end + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h0) begin + if (_newCtr_T) + useAltOnNaCtrs_0_0 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_0 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_0 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_0 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1) begin + if (_newCtr_T) + useAltOnNaCtrs_0_1 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_1 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_1 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_1 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2) begin + if (_newCtr_T) + useAltOnNaCtrs_0_2 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_2 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_2 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_2 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3) begin + if (_newCtr_T) + useAltOnNaCtrs_0_3 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_3 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_3 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_3 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4) begin + if (_newCtr_T) + useAltOnNaCtrs_0_4 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_4 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_4 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_4 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5) begin + if (_newCtr_T) + useAltOnNaCtrs_0_5 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_5 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_5 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_5 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6) begin + if (_newCtr_T) + useAltOnNaCtrs_0_6 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_6 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_6 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_6 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h7) begin + if (_newCtr_T) + useAltOnNaCtrs_0_7 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_7 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_7 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_7 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h8) begin + if (_newCtr_T) + useAltOnNaCtrs_0_8 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_8 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_8 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_8 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h9) begin + if (_newCtr_T) + useAltOnNaCtrs_0_9 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_9 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_9 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_9 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'hA) begin + if (_newCtr_T) + useAltOnNaCtrs_0_10 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_10 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_10 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_10 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'hB) begin + if (_newCtr_T) + useAltOnNaCtrs_0_11 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_11 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_11 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_11 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'hC) begin + if (_newCtr_T) + useAltOnNaCtrs_0_12 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_12 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_12 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_12 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'hD) begin + if (_newCtr_T) + useAltOnNaCtrs_0_13 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_13 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_13 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_13 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'hE) begin + if (_newCtr_T) + useAltOnNaCtrs_0_14 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_14 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_14 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_14 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'hF) begin + if (_newCtr_T) + useAltOnNaCtrs_0_15 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_15 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_15 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_15 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h10) begin + if (_newCtr_T) + useAltOnNaCtrs_0_16 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_16 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_16 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_16 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h11) begin + if (_newCtr_T) + useAltOnNaCtrs_0_17 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_17 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_17 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_17 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h12) begin + if (_newCtr_T) + useAltOnNaCtrs_0_18 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_18 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_18 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_18 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h13) begin + if (_newCtr_T) + useAltOnNaCtrs_0_19 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_19 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_19 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_19 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h14) begin + if (_newCtr_T) + useAltOnNaCtrs_0_20 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_20 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_20 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_20 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h15) begin + if (_newCtr_T) + useAltOnNaCtrs_0_21 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_21 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_21 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_21 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h16) begin + if (_newCtr_T) + useAltOnNaCtrs_0_22 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_22 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_22 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_22 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h17) begin + if (_newCtr_T) + useAltOnNaCtrs_0_23 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_23 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_23 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_23 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h18) begin + if (_newCtr_T) + useAltOnNaCtrs_0_24 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_24 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_24 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_24 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h19) begin + if (_newCtr_T) + useAltOnNaCtrs_0_25 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_25 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_25 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_25 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1A) begin + if (_newCtr_T) + useAltOnNaCtrs_0_26 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_26 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_26 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_26 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1B) begin + if (_newCtr_T) + useAltOnNaCtrs_0_27 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_27 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_27 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_27 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1C) begin + if (_newCtr_T) + useAltOnNaCtrs_0_28 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_28 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_28 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_28 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1D) begin + if (_newCtr_T) + useAltOnNaCtrs_0_29 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_29 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_29 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_29 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1E) begin + if (_newCtr_T) + useAltOnNaCtrs_0_30 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_30 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_30 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_30 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h1F) begin + if (_newCtr_T) + useAltOnNaCtrs_0_31 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_31 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_31 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_31 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h20) begin + if (_newCtr_T) + useAltOnNaCtrs_0_32 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_32 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_32 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_32 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h21) begin + if (_newCtr_T) + useAltOnNaCtrs_0_33 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_33 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_33 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_33 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h22) begin + if (_newCtr_T) + useAltOnNaCtrs_0_34 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_34 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_34 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_34 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h23) begin + if (_newCtr_T) + useAltOnNaCtrs_0_35 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_35 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_35 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_35 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h24) begin + if (_newCtr_T) + useAltOnNaCtrs_0_36 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_36 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_36 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_36 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h25) begin + if (_newCtr_T) + useAltOnNaCtrs_0_37 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_37 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_37 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_37 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h26) begin + if (_newCtr_T) + useAltOnNaCtrs_0_38 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_38 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_38 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_38 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h27) begin + if (_newCtr_T) + useAltOnNaCtrs_0_39 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_39 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_39 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_39 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h28) begin + if (_newCtr_T) + useAltOnNaCtrs_0_40 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_40 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_40 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_40 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h29) begin + if (_newCtr_T) + useAltOnNaCtrs_0_41 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_41 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_41 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_41 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2A) begin + if (_newCtr_T) + useAltOnNaCtrs_0_42 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_42 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_42 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_42 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2B) begin + if (_newCtr_T) + useAltOnNaCtrs_0_43 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_43 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_43 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_43 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2C) begin + if (_newCtr_T) + useAltOnNaCtrs_0_44 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_44 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_44 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_44 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2D) begin + if (_newCtr_T) + useAltOnNaCtrs_0_45 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_45 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_45 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_45 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2E) begin + if (_newCtr_T) + useAltOnNaCtrs_0_46 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_46 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_46 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_46 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h2F) begin + if (_newCtr_T) + useAltOnNaCtrs_0_47 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_47 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_47 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_47 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h30) begin + if (_newCtr_T) + useAltOnNaCtrs_0_48 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_48 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_48 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_48 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h31) begin + if (_newCtr_T) + useAltOnNaCtrs_0_49 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_49 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_49 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_49 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h32) begin + if (_newCtr_T) + useAltOnNaCtrs_0_50 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_50 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_50 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_50 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h33) begin + if (_newCtr_T) + useAltOnNaCtrs_0_51 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_51 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_51 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_51 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h34) begin + if (_newCtr_T) + useAltOnNaCtrs_0_52 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_52 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_52 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_52 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h35) begin + if (_newCtr_T) + useAltOnNaCtrs_0_53 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_53 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_53 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_53 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h36) begin + if (_newCtr_T) + useAltOnNaCtrs_0_54 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_54 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_54 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_54 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h37) begin + if (_newCtr_T) + useAltOnNaCtrs_0_55 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_55 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_55 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_55 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h38) begin + if (_newCtr_T) + useAltOnNaCtrs_0_56 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_56 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_56 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_56 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h39) begin + if (_newCtr_T) + useAltOnNaCtrs_0_57 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_57 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_57 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_57 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3A) begin + if (_newCtr_T) + useAltOnNaCtrs_0_58 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_58 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_58 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_58 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3B) begin + if (_newCtr_T) + useAltOnNaCtrs_0_59 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_59 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_59 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_59 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3C) begin + if (_newCtr_T) + useAltOnNaCtrs_0_60 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_60 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_60 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_60 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3D) begin + if (_newCtr_T) + useAltOnNaCtrs_0_61 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_61 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_61 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_61 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3E) begin + if (_newCtr_T) + useAltOnNaCtrs_0_62 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_62 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_62 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_62 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h3F) begin + if (_newCtr_T) + useAltOnNaCtrs_0_63 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_63 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_63 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_63 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h40) begin + if (_newCtr_T) + useAltOnNaCtrs_0_64 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_64 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_64 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_64 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h41) begin + if (_newCtr_T) + useAltOnNaCtrs_0_65 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_65 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_65 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_65 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h42) begin + if (_newCtr_T) + useAltOnNaCtrs_0_66 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_66 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_66 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_66 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h43) begin + if (_newCtr_T) + useAltOnNaCtrs_0_67 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_67 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_67 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_67 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h44) begin + if (_newCtr_T) + useAltOnNaCtrs_0_68 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_68 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_68 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_68 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h45) begin + if (_newCtr_T) + useAltOnNaCtrs_0_69 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_69 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_69 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_69 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h46) begin + if (_newCtr_T) + useAltOnNaCtrs_0_70 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_70 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_70 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_70 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h47) begin + if (_newCtr_T) + useAltOnNaCtrs_0_71 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_71 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_71 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_71 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h48) begin + if (_newCtr_T) + useAltOnNaCtrs_0_72 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_72 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_72 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_72 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h49) begin + if (_newCtr_T) + useAltOnNaCtrs_0_73 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_73 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_73 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_73 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4A) begin + if (_newCtr_T) + useAltOnNaCtrs_0_74 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_74 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_74 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_74 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4B) begin + if (_newCtr_T) + useAltOnNaCtrs_0_75 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_75 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_75 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_75 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4C) begin + if (_newCtr_T) + useAltOnNaCtrs_0_76 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_76 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_76 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_76 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4D) begin + if (_newCtr_T) + useAltOnNaCtrs_0_77 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_77 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_77 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_77 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4E) begin + if (_newCtr_T) + useAltOnNaCtrs_0_78 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_78 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_78 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_78 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h4F) begin + if (_newCtr_T) + useAltOnNaCtrs_0_79 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_79 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_79 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_79 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h50) begin + if (_newCtr_T) + useAltOnNaCtrs_0_80 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_80 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_80 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_80 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h51) begin + if (_newCtr_T) + useAltOnNaCtrs_0_81 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_81 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_81 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_81 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h52) begin + if (_newCtr_T) + useAltOnNaCtrs_0_82 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_82 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_82 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_82 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h53) begin + if (_newCtr_T) + useAltOnNaCtrs_0_83 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_83 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_83 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_83 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h54) begin + if (_newCtr_T) + useAltOnNaCtrs_0_84 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_84 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_84 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_84 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h55) begin + if (_newCtr_T) + useAltOnNaCtrs_0_85 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_85 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_85 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_85 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h56) begin + if (_newCtr_T) + useAltOnNaCtrs_0_86 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_86 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_86 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_86 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h57) begin + if (_newCtr_T) + useAltOnNaCtrs_0_87 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_87 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_87 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_87 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h58) begin + if (_newCtr_T) + useAltOnNaCtrs_0_88 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_88 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_88 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_88 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h59) begin + if (_newCtr_T) + useAltOnNaCtrs_0_89 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_89 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_89 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_89 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5A) begin + if (_newCtr_T) + useAltOnNaCtrs_0_90 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_90 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_90 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_90 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5B) begin + if (_newCtr_T) + useAltOnNaCtrs_0_91 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_91 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_91 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_91 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5C) begin + if (_newCtr_T) + useAltOnNaCtrs_0_92 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_92 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_92 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_92 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5D) begin + if (_newCtr_T) + useAltOnNaCtrs_0_93 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_93 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_93 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_93 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5E) begin + if (_newCtr_T) + useAltOnNaCtrs_0_94 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_94 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_94 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_94 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h5F) begin + if (_newCtr_T) + useAltOnNaCtrs_0_95 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_95 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_95 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_95 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h60) begin + if (_newCtr_T) + useAltOnNaCtrs_0_96 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_96 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_96 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_96 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h61) begin + if (_newCtr_T) + useAltOnNaCtrs_0_97 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_97 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_97 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_97 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h62) begin + if (_newCtr_T) + useAltOnNaCtrs_0_98 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_98 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_98 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_98 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h63) begin + if (_newCtr_T) + useAltOnNaCtrs_0_99 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_99 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_99 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_99 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h64) begin + if (_newCtr_T) + useAltOnNaCtrs_0_100 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_100 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_100 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_100 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h65) begin + if (_newCtr_T) + useAltOnNaCtrs_0_101 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_101 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_101 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_101 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h66) begin + if (_newCtr_T) + useAltOnNaCtrs_0_102 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_102 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_102 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_102 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h67) begin + if (_newCtr_T) + useAltOnNaCtrs_0_103 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_103 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_103 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_103 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h68) begin + if (_newCtr_T) + useAltOnNaCtrs_0_104 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_104 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_104 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_104 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h69) begin + if (_newCtr_T) + useAltOnNaCtrs_0_105 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_105 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_105 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_105 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6A) begin + if (_newCtr_T) + useAltOnNaCtrs_0_106 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_106 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_106 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_106 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6B) begin + if (_newCtr_T) + useAltOnNaCtrs_0_107 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_107 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_107 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_107 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6C) begin + if (_newCtr_T) + useAltOnNaCtrs_0_108 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_108 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_108 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_108 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6D) begin + if (_newCtr_T) + useAltOnNaCtrs_0_109 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_109 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_109 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_109 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6E) begin + if (_newCtr_T) + useAltOnNaCtrs_0_110 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_110 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_110 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_110 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h6F) begin + if (_newCtr_T) + useAltOnNaCtrs_0_111 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_111 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_111 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_111 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h70) begin + if (_newCtr_T) + useAltOnNaCtrs_0_112 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_112 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_112 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_112 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h71) begin + if (_newCtr_T) + useAltOnNaCtrs_0_113 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_113 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_113 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_113 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h72) begin + if (_newCtr_T) + useAltOnNaCtrs_0_114 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_114 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_114 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_114 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h73) begin + if (_newCtr_T) + useAltOnNaCtrs_0_115 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_115 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_115 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_115 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h74) begin + if (_newCtr_T) + useAltOnNaCtrs_0_116 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_116 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_116 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_116 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h75) begin + if (_newCtr_T) + useAltOnNaCtrs_0_117 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_117 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_117 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_117 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h76) begin + if (_newCtr_T) + useAltOnNaCtrs_0_118 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_118 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_118 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_118 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h77) begin + if (_newCtr_T) + useAltOnNaCtrs_0_119 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_119 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_119 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_119 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h78) begin + if (_newCtr_T) + useAltOnNaCtrs_0_120 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_120 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_120 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_120 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h79) begin + if (_newCtr_T) + useAltOnNaCtrs_0_121 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_121 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_121 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_121 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h7A) begin + if (_newCtr_T) + useAltOnNaCtrs_0_122 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_122 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_122 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_122 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h7B) begin + if (_newCtr_T) + useAltOnNaCtrs_0_123 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_123 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_123 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_123 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h7C) begin + if (_newCtr_T) + useAltOnNaCtrs_0_124 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_124 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_124 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_124 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h7D) begin + if (_newCtr_T) + useAltOnNaCtrs_0_125 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_125 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_125 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_125 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & io_update_bits_pc[7:1] == 7'h7E) begin + if (_newCtr_T) + useAltOnNaCtrs_0_126 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_126 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_126 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_126 <= _newCtr_T_5; + end + if (updateValids_0 & _GEN_69 & (&(io_update_bits_pc[7:1]))) begin + if (_newCtr_T) + useAltOnNaCtrs_0_127 <= 4'hF; + else if (_newCtr_T_2) + useAltOnNaCtrs_0_127 <= 4'h0; + else if (updateAltCorrect) + useAltOnNaCtrs_0_127 <= _newCtr_T_3; + else + useAltOnNaCtrs_0_127 <= _newCtr_T_5; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h0) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_0 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_0 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_0 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_0 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_1 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_1 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_1 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_1 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_2 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_2 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_2 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_2 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_3 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_3 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_3 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_3 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_4 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_4 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_4 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_4 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_5 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_5 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_5 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_5 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_6 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_6 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_6 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_6 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h7) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_7 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_7 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_7 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_7 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h8) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_8 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_8 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_8 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_8 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h9) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_9 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_9 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_9 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_9 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'hA) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_10 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_10 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_10 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_10 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'hB) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_11 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_11 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_11 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_11 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'hC) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_12 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_12 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_12 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_12 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'hD) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_13 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_13 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_13 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_13 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'hE) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_14 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_14 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_14 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_14 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'hF) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_15 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_15 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_15 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_15 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h10) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_16 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_16 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_16 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_16 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h11) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_17 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_17 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_17 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_17 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h12) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_18 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_18 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_18 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_18 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h13) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_19 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_19 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_19 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_19 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h14) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_20 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_20 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_20 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_20 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h15) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_21 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_21 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_21 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_21 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h16) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_22 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_22 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_22 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_22 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h17) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_23 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_23 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_23 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_23 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h18) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_24 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_24 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_24 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_24 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h19) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_25 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_25 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_25 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_25 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1A) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_26 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_26 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_26 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_26 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1B) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_27 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_27 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_27 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_27 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1C) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_28 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_28 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_28 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_28 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1D) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_29 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_29 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_29 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_29 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1E) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_30 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_30 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_30 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_30 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h1F) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_31 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_31 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_31 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_31 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h20) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_32 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_32 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_32 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_32 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h21) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_33 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_33 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_33 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_33 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h22) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_34 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_34 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_34 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_34 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h23) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_35 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_35 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_35 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_35 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h24) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_36 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_36 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_36 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_36 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h25) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_37 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_37 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_37 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_37 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h26) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_38 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_38 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_38 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_38 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h27) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_39 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_39 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_39 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_39 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h28) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_40 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_40 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_40 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_40 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h29) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_41 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_41 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_41 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_41 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2A) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_42 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_42 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_42 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_42 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2B) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_43 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_43 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_43 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_43 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2C) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_44 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_44 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_44 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_44 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2D) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_45 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_45 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_45 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_45 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2E) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_46 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_46 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_46 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_46 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h2F) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_47 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_47 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_47 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_47 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h30) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_48 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_48 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_48 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_48 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h31) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_49 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_49 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_49 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_49 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h32) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_50 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_50 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_50 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_50 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h33) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_51 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_51 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_51 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_51 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h34) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_52 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_52 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_52 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_52 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h35) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_53 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_53 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_53 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_53 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h36) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_54 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_54 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_54 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_54 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h37) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_55 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_55 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_55 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_55 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h38) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_56 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_56 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_56 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_56 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h39) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_57 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_57 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_57 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_57 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3A) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_58 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_58 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_58 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_58 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3B) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_59 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_59 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_59 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_59 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3C) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_60 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_60 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_60 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_60 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3D) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_61 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_61 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_61 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_61 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3E) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_62 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_62 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_62 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_62 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h3F) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_63 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_63 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_63 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_63 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h40) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_64 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_64 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_64 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_64 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h41) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_65 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_65 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_65 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_65 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h42) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_66 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_66 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_66 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_66 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h43) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_67 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_67 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_67 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_67 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h44) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_68 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_68 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_68 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_68 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h45) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_69 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_69 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_69 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_69 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h46) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_70 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_70 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_70 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_70 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h47) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_71 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_71 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_71 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_71 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h48) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_72 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_72 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_72 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_72 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h49) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_73 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_73 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_73 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_73 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4A) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_74 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_74 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_74 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_74 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4B) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_75 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_75 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_75 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_75 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4C) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_76 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_76 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_76 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_76 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4D) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_77 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_77 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_77 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_77 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4E) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_78 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_78 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_78 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_78 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h4F) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_79 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_79 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_79 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_79 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h50) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_80 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_80 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_80 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_80 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h51) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_81 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_81 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_81 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_81 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h52) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_82 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_82 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_82 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_82 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h53) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_83 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_83 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_83 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_83 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h54) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_84 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_84 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_84 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_84 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h55) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_85 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_85 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_85 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_85 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h56) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_86 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_86 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_86 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_86 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h57) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_87 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_87 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_87 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_87 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h58) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_88 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_88 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_88 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_88 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h59) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_89 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_89 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_89 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_89 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5A) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_90 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_90 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_90 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_90 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5B) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_91 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_91 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_91 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_91 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5C) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_92 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_92 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_92 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_92 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5D) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_93 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_93 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_93 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_93 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5E) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_94 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_94 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_94 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_94 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h5F) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_95 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_95 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_95 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_95 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h60) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_96 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_96 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_96 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_96 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h61) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_97 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_97 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_97 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_97 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h62) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_98 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_98 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_98 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_98 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h63) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_99 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_99 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_99 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_99 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h64) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_100 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_100 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_100 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_100 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h65) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_101 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_101 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_101 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_101 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h66) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_102 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_102 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_102 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_102 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h67) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_103 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_103 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_103 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_103 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h68) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_104 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_104 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_104 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_104 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h69) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_105 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_105 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_105 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_105 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6A) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_106 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_106 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_106 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_106 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6B) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_107 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_107 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_107 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_107 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6C) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_108 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_108 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_108 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_108 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6D) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_109 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_109 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_109 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_109 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6E) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_110 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_110 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_110 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_110 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h6F) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_111 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_111 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_111 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_111 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h70) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_112 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_112 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_112 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_112 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h71) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_113 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_113 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_113 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_113 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h72) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_114 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_114 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_114 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_114 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h73) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_115 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_115 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_115 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_115 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h74) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_116 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_116 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_116 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_116 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h75) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_117 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_117 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_117 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_117 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h76) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_118 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_118 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_118 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_118 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h77) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_119 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_119 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_119 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_119 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h78) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_120 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_120 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_120 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_120 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h79) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_121 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_121 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_121 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_121 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h7A) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_122 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_122 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_122 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_122 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h7B) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_123 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_123 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_123 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_123 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h7C) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_124 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_124 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_124 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_124 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h7D) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_125 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_125 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_125 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_125 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & io_update_bits_pc[7:1] == 7'h7E) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_126 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_126 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_126 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_126 <= _newCtr_T_14; + end + if (updateValids_1 & _GEN_70 & (&(io_update_bits_pc[7:1]))) begin + if (_newCtr_T_9) + useAltOnNaCtrs_1_127 <= 4'hF; + else if (_newCtr_T_11) + useAltOnNaCtrs_1_127 <= 4'h0; + else if (updateAltCorrect_1) + useAltOnNaCtrs_1_127 <= _newCtr_T_12; + else + useAltOnNaCtrs_1_127 <= _newCtr_T_14; + end + if (allocLFSR_lfsr == 64'h0) + allocLFSR_lfsr <= 64'h1; + else + allocLFSR_lfsr <= + {allocLFSR_lfsr[0] ^ allocLFSR_lfsr[1] ^ allocLFSR_lfsr[3] ^ allocLFSR_lfsr[4], + allocLFSR_lfsr[63:1]}; + if (allocLFSR_lfsr_1 == 64'h0) + allocLFSR_lfsr_1 <= 64'h1; + else + allocLFSR_lfsr_1 <= + {allocLFSR_lfsr_1[0] ^ allocLFSR_lfsr_1[1] ^ allocLFSR_lfsr_1[3] + ^ allocLFSR_lfsr_1[4], + allocLFSR_lfsr_1[63:1]}; + if (_GEN_1 & io_update_bits_meta[48] != io_update_bits_meta[52] + & _sumAbs_T_4 >= {2'h0, 8'(scThresholds_0_thres - 8'h4)} + & _sumAbs_T_4 <= {2'h0, 8'(scThresholds_0_thres - 8'h2)}) begin + if ((&newThres_newCtr) | _newThres_res_ctr_T_4) + scThresholds_0_ctr <= 5'h10; + else if (_newThres_newCtr_T) + scThresholds_0_ctr <= 5'h1F; + else if (_newThres_newCtr_T_2) + scThresholds_0_ctr <= 5'h0; + else if (_GEN_67) + scThresholds_0_ctr <= _newThres_newCtr_T_5; + else + scThresholds_0_ctr <= _newThres_newCtr_T_3; + if ((&newThres_newCtr) & scThresholds_0_thres < 8'h20) + scThresholds_0_thres <= 8'(scThresholds_0_thres + 8'h2); + else if (_newThres_res_ctr_T_4 & scThresholds_0_thres > 8'h5) + scThresholds_0_thres <= 8'(scThresholds_0_thres - 8'h2); + end + if (_GEN_2 & io_update_bits_meta[49] != io_update_bits_meta[53] + & _sumAbs_T_9 >= {2'h0, 8'(scThresholds_1_thres - 8'h4)} + & _sumAbs_T_9 <= {2'h0, 8'(scThresholds_1_thres - 8'h2)}) begin + if ((&newThres_newCtr_1) | _newThres_res_ctr_T_11) + scThresholds_1_ctr <= 5'h10; + else if (_newThres_newCtr_T_9) + scThresholds_1_ctr <= 5'h1F; + else if (_newThres_newCtr_T_11) + scThresholds_1_ctr <= 5'h0; + else if (_GEN_68) + scThresholds_1_ctr <= _newThres_newCtr_T_14; + else + scThresholds_1_ctr <= _newThres_newCtr_T_12; + if ((&newThres_newCtr_1) & scThresholds_1_thres < 8'h20) + scThresholds_1_thres <= 8'(scThresholds_1_thres + 8'h2); + else if (_newThres_res_ctr_T_11 & scThresholds_1_thres > 8'h5) + scThresholds_1_thres <= 8'(scThresholds_1_thres - 8'h2); + end + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:233]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [7:0] i = 8'h0; i < 8'hEA; i += 8'h1) begin + _RANDOM[i] = `RANDOM; + end + s1_pc_dup_0 = {_RANDOM[8'h0], _RANDOM[8'h1][8:0]}; + REG = _RANDOM[8'hF][12]; + REG_1 = _RANDOM[8'hF][13]; + bankTickCtrDistanceToTops_0 = _RANDOM[8'hF][20:14]; + bankTickCtrDistanceToTops_1 = _RANDOM[8'hF][27:21]; + bankTickCtrs_0 = {_RANDOM[8'hF][31:28], _RANDOM[8'h10][2:0]}; + bankTickCtrs_1 = _RANDOM[8'h10][9:3]; + useAltOnNaCtrs_0_0 = _RANDOM[8'h10][13:10]; + useAltOnNaCtrs_0_1 = _RANDOM[8'h10][17:14]; + useAltOnNaCtrs_0_2 = _RANDOM[8'h10][21:18]; + useAltOnNaCtrs_0_3 = _RANDOM[8'h10][25:22]; + useAltOnNaCtrs_0_4 = _RANDOM[8'h10][29:26]; + useAltOnNaCtrs_0_5 = {_RANDOM[8'h10][31:30], _RANDOM[8'h11][1:0]}; + useAltOnNaCtrs_0_6 = _RANDOM[8'h11][5:2]; + useAltOnNaCtrs_0_7 = _RANDOM[8'h11][9:6]; + useAltOnNaCtrs_0_8 = _RANDOM[8'h11][13:10]; + useAltOnNaCtrs_0_9 = _RANDOM[8'h11][17:14]; + useAltOnNaCtrs_0_10 = _RANDOM[8'h11][21:18]; + useAltOnNaCtrs_0_11 = _RANDOM[8'h11][25:22]; + useAltOnNaCtrs_0_12 = _RANDOM[8'h11][29:26]; + useAltOnNaCtrs_0_13 = {_RANDOM[8'h11][31:30], _RANDOM[8'h12][1:0]}; + useAltOnNaCtrs_0_14 = _RANDOM[8'h12][5:2]; + useAltOnNaCtrs_0_15 = _RANDOM[8'h12][9:6]; + useAltOnNaCtrs_0_16 = _RANDOM[8'h12][13:10]; + useAltOnNaCtrs_0_17 = _RANDOM[8'h12][17:14]; + useAltOnNaCtrs_0_18 = _RANDOM[8'h12][21:18]; + useAltOnNaCtrs_0_19 = _RANDOM[8'h12][25:22]; + useAltOnNaCtrs_0_20 = _RANDOM[8'h12][29:26]; + useAltOnNaCtrs_0_21 = {_RANDOM[8'h12][31:30], _RANDOM[8'h13][1:0]}; + useAltOnNaCtrs_0_22 = _RANDOM[8'h13][5:2]; + useAltOnNaCtrs_0_23 = _RANDOM[8'h13][9:6]; + useAltOnNaCtrs_0_24 = _RANDOM[8'h13][13:10]; + useAltOnNaCtrs_0_25 = _RANDOM[8'h13][17:14]; + useAltOnNaCtrs_0_26 = _RANDOM[8'h13][21:18]; + useAltOnNaCtrs_0_27 = _RANDOM[8'h13][25:22]; + useAltOnNaCtrs_0_28 = _RANDOM[8'h13][29:26]; + useAltOnNaCtrs_0_29 = {_RANDOM[8'h13][31:30], _RANDOM[8'h14][1:0]}; + useAltOnNaCtrs_0_30 = _RANDOM[8'h14][5:2]; + useAltOnNaCtrs_0_31 = _RANDOM[8'h14][9:6]; + useAltOnNaCtrs_0_32 = _RANDOM[8'h14][13:10]; + useAltOnNaCtrs_0_33 = _RANDOM[8'h14][17:14]; + useAltOnNaCtrs_0_34 = _RANDOM[8'h14][21:18]; + useAltOnNaCtrs_0_35 = _RANDOM[8'h14][25:22]; + useAltOnNaCtrs_0_36 = _RANDOM[8'h14][29:26]; + useAltOnNaCtrs_0_37 = {_RANDOM[8'h14][31:30], _RANDOM[8'h15][1:0]}; + useAltOnNaCtrs_0_38 = _RANDOM[8'h15][5:2]; + useAltOnNaCtrs_0_39 = _RANDOM[8'h15][9:6]; + useAltOnNaCtrs_0_40 = _RANDOM[8'h15][13:10]; + useAltOnNaCtrs_0_41 = _RANDOM[8'h15][17:14]; + useAltOnNaCtrs_0_42 = _RANDOM[8'h15][21:18]; + useAltOnNaCtrs_0_43 = _RANDOM[8'h15][25:22]; + useAltOnNaCtrs_0_44 = _RANDOM[8'h15][29:26]; + useAltOnNaCtrs_0_45 = {_RANDOM[8'h15][31:30], _RANDOM[8'h16][1:0]}; + useAltOnNaCtrs_0_46 = _RANDOM[8'h16][5:2]; + useAltOnNaCtrs_0_47 = _RANDOM[8'h16][9:6]; + useAltOnNaCtrs_0_48 = _RANDOM[8'h16][13:10]; + useAltOnNaCtrs_0_49 = _RANDOM[8'h16][17:14]; + useAltOnNaCtrs_0_50 = _RANDOM[8'h16][21:18]; + useAltOnNaCtrs_0_51 = _RANDOM[8'h16][25:22]; + useAltOnNaCtrs_0_52 = _RANDOM[8'h16][29:26]; + useAltOnNaCtrs_0_53 = {_RANDOM[8'h16][31:30], _RANDOM[8'h17][1:0]}; + useAltOnNaCtrs_0_54 = _RANDOM[8'h17][5:2]; + useAltOnNaCtrs_0_55 = _RANDOM[8'h17][9:6]; + useAltOnNaCtrs_0_56 = _RANDOM[8'h17][13:10]; + useAltOnNaCtrs_0_57 = _RANDOM[8'h17][17:14]; + useAltOnNaCtrs_0_58 = _RANDOM[8'h17][21:18]; + useAltOnNaCtrs_0_59 = _RANDOM[8'h17][25:22]; + useAltOnNaCtrs_0_60 = _RANDOM[8'h17][29:26]; + useAltOnNaCtrs_0_61 = {_RANDOM[8'h17][31:30], _RANDOM[8'h18][1:0]}; + useAltOnNaCtrs_0_62 = _RANDOM[8'h18][5:2]; + useAltOnNaCtrs_0_63 = _RANDOM[8'h18][9:6]; + useAltOnNaCtrs_0_64 = _RANDOM[8'h18][13:10]; + useAltOnNaCtrs_0_65 = _RANDOM[8'h18][17:14]; + useAltOnNaCtrs_0_66 = _RANDOM[8'h18][21:18]; + useAltOnNaCtrs_0_67 = _RANDOM[8'h18][25:22]; + useAltOnNaCtrs_0_68 = _RANDOM[8'h18][29:26]; + useAltOnNaCtrs_0_69 = {_RANDOM[8'h18][31:30], _RANDOM[8'h19][1:0]}; + useAltOnNaCtrs_0_70 = _RANDOM[8'h19][5:2]; + useAltOnNaCtrs_0_71 = _RANDOM[8'h19][9:6]; + useAltOnNaCtrs_0_72 = _RANDOM[8'h19][13:10]; + useAltOnNaCtrs_0_73 = _RANDOM[8'h19][17:14]; + useAltOnNaCtrs_0_74 = _RANDOM[8'h19][21:18]; + useAltOnNaCtrs_0_75 = _RANDOM[8'h19][25:22]; + useAltOnNaCtrs_0_76 = _RANDOM[8'h19][29:26]; + useAltOnNaCtrs_0_77 = {_RANDOM[8'h19][31:30], _RANDOM[8'h1A][1:0]}; + useAltOnNaCtrs_0_78 = _RANDOM[8'h1A][5:2]; + useAltOnNaCtrs_0_79 = _RANDOM[8'h1A][9:6]; + useAltOnNaCtrs_0_80 = _RANDOM[8'h1A][13:10]; + useAltOnNaCtrs_0_81 = _RANDOM[8'h1A][17:14]; + useAltOnNaCtrs_0_82 = _RANDOM[8'h1A][21:18]; + useAltOnNaCtrs_0_83 = _RANDOM[8'h1A][25:22]; + useAltOnNaCtrs_0_84 = _RANDOM[8'h1A][29:26]; + useAltOnNaCtrs_0_85 = {_RANDOM[8'h1A][31:30], _RANDOM[8'h1B][1:0]}; + useAltOnNaCtrs_0_86 = _RANDOM[8'h1B][5:2]; + useAltOnNaCtrs_0_87 = _RANDOM[8'h1B][9:6]; + useAltOnNaCtrs_0_88 = _RANDOM[8'h1B][13:10]; + useAltOnNaCtrs_0_89 = _RANDOM[8'h1B][17:14]; + useAltOnNaCtrs_0_90 = _RANDOM[8'h1B][21:18]; + useAltOnNaCtrs_0_91 = _RANDOM[8'h1B][25:22]; + useAltOnNaCtrs_0_92 = _RANDOM[8'h1B][29:26]; + useAltOnNaCtrs_0_93 = {_RANDOM[8'h1B][31:30], _RANDOM[8'h1C][1:0]}; + useAltOnNaCtrs_0_94 = _RANDOM[8'h1C][5:2]; + useAltOnNaCtrs_0_95 = _RANDOM[8'h1C][9:6]; + useAltOnNaCtrs_0_96 = _RANDOM[8'h1C][13:10]; + useAltOnNaCtrs_0_97 = _RANDOM[8'h1C][17:14]; + useAltOnNaCtrs_0_98 = _RANDOM[8'h1C][21:18]; + useAltOnNaCtrs_0_99 = _RANDOM[8'h1C][25:22]; + useAltOnNaCtrs_0_100 = _RANDOM[8'h1C][29:26]; + useAltOnNaCtrs_0_101 = {_RANDOM[8'h1C][31:30], _RANDOM[8'h1D][1:0]}; + useAltOnNaCtrs_0_102 = _RANDOM[8'h1D][5:2]; + useAltOnNaCtrs_0_103 = _RANDOM[8'h1D][9:6]; + useAltOnNaCtrs_0_104 = _RANDOM[8'h1D][13:10]; + useAltOnNaCtrs_0_105 = _RANDOM[8'h1D][17:14]; + useAltOnNaCtrs_0_106 = _RANDOM[8'h1D][21:18]; + useAltOnNaCtrs_0_107 = _RANDOM[8'h1D][25:22]; + useAltOnNaCtrs_0_108 = _RANDOM[8'h1D][29:26]; + useAltOnNaCtrs_0_109 = {_RANDOM[8'h1D][31:30], _RANDOM[8'h1E][1:0]}; + useAltOnNaCtrs_0_110 = _RANDOM[8'h1E][5:2]; + useAltOnNaCtrs_0_111 = _RANDOM[8'h1E][9:6]; + useAltOnNaCtrs_0_112 = _RANDOM[8'h1E][13:10]; + useAltOnNaCtrs_0_113 = _RANDOM[8'h1E][17:14]; + useAltOnNaCtrs_0_114 = _RANDOM[8'h1E][21:18]; + useAltOnNaCtrs_0_115 = _RANDOM[8'h1E][25:22]; + useAltOnNaCtrs_0_116 = _RANDOM[8'h1E][29:26]; + useAltOnNaCtrs_0_117 = {_RANDOM[8'h1E][31:30], _RANDOM[8'h1F][1:0]}; + useAltOnNaCtrs_0_118 = _RANDOM[8'h1F][5:2]; + useAltOnNaCtrs_0_119 = _RANDOM[8'h1F][9:6]; + useAltOnNaCtrs_0_120 = _RANDOM[8'h1F][13:10]; + useAltOnNaCtrs_0_121 = _RANDOM[8'h1F][17:14]; + useAltOnNaCtrs_0_122 = _RANDOM[8'h1F][21:18]; + useAltOnNaCtrs_0_123 = _RANDOM[8'h1F][25:22]; + useAltOnNaCtrs_0_124 = _RANDOM[8'h1F][29:26]; + useAltOnNaCtrs_0_125 = {_RANDOM[8'h1F][31:30], _RANDOM[8'h20][1:0]}; + useAltOnNaCtrs_0_126 = _RANDOM[8'h20][5:2]; + useAltOnNaCtrs_0_127 = _RANDOM[8'h20][9:6]; + useAltOnNaCtrs_1_0 = _RANDOM[8'h20][13:10]; + useAltOnNaCtrs_1_1 = _RANDOM[8'h20][17:14]; + useAltOnNaCtrs_1_2 = _RANDOM[8'h20][21:18]; + useAltOnNaCtrs_1_3 = _RANDOM[8'h20][25:22]; + useAltOnNaCtrs_1_4 = _RANDOM[8'h20][29:26]; + useAltOnNaCtrs_1_5 = {_RANDOM[8'h20][31:30], _RANDOM[8'h21][1:0]}; + useAltOnNaCtrs_1_6 = _RANDOM[8'h21][5:2]; + useAltOnNaCtrs_1_7 = _RANDOM[8'h21][9:6]; + useAltOnNaCtrs_1_8 = _RANDOM[8'h21][13:10]; + useAltOnNaCtrs_1_9 = _RANDOM[8'h21][17:14]; + useAltOnNaCtrs_1_10 = _RANDOM[8'h21][21:18]; + useAltOnNaCtrs_1_11 = _RANDOM[8'h21][25:22]; + useAltOnNaCtrs_1_12 = _RANDOM[8'h21][29:26]; + useAltOnNaCtrs_1_13 = {_RANDOM[8'h21][31:30], _RANDOM[8'h22][1:0]}; + useAltOnNaCtrs_1_14 = _RANDOM[8'h22][5:2]; + useAltOnNaCtrs_1_15 = _RANDOM[8'h22][9:6]; + useAltOnNaCtrs_1_16 = _RANDOM[8'h22][13:10]; + useAltOnNaCtrs_1_17 = _RANDOM[8'h22][17:14]; + useAltOnNaCtrs_1_18 = _RANDOM[8'h22][21:18]; + useAltOnNaCtrs_1_19 = _RANDOM[8'h22][25:22]; + useAltOnNaCtrs_1_20 = _RANDOM[8'h22][29:26]; + useAltOnNaCtrs_1_21 = {_RANDOM[8'h22][31:30], _RANDOM[8'h23][1:0]}; + useAltOnNaCtrs_1_22 = _RANDOM[8'h23][5:2]; + useAltOnNaCtrs_1_23 = _RANDOM[8'h23][9:6]; + useAltOnNaCtrs_1_24 = _RANDOM[8'h23][13:10]; + useAltOnNaCtrs_1_25 = _RANDOM[8'h23][17:14]; + useAltOnNaCtrs_1_26 = _RANDOM[8'h23][21:18]; + useAltOnNaCtrs_1_27 = _RANDOM[8'h23][25:22]; + useAltOnNaCtrs_1_28 = _RANDOM[8'h23][29:26]; + useAltOnNaCtrs_1_29 = {_RANDOM[8'h23][31:30], _RANDOM[8'h24][1:0]}; + useAltOnNaCtrs_1_30 = _RANDOM[8'h24][5:2]; + useAltOnNaCtrs_1_31 = _RANDOM[8'h24][9:6]; + useAltOnNaCtrs_1_32 = _RANDOM[8'h24][13:10]; + useAltOnNaCtrs_1_33 = _RANDOM[8'h24][17:14]; + useAltOnNaCtrs_1_34 = _RANDOM[8'h24][21:18]; + useAltOnNaCtrs_1_35 = _RANDOM[8'h24][25:22]; + useAltOnNaCtrs_1_36 = _RANDOM[8'h24][29:26]; + useAltOnNaCtrs_1_37 = {_RANDOM[8'h24][31:30], _RANDOM[8'h25][1:0]}; + useAltOnNaCtrs_1_38 = _RANDOM[8'h25][5:2]; + useAltOnNaCtrs_1_39 = _RANDOM[8'h25][9:6]; + useAltOnNaCtrs_1_40 = _RANDOM[8'h25][13:10]; + useAltOnNaCtrs_1_41 = _RANDOM[8'h25][17:14]; + useAltOnNaCtrs_1_42 = _RANDOM[8'h25][21:18]; + useAltOnNaCtrs_1_43 = _RANDOM[8'h25][25:22]; + useAltOnNaCtrs_1_44 = _RANDOM[8'h25][29:26]; + useAltOnNaCtrs_1_45 = {_RANDOM[8'h25][31:30], _RANDOM[8'h26][1:0]}; + useAltOnNaCtrs_1_46 = _RANDOM[8'h26][5:2]; + useAltOnNaCtrs_1_47 = _RANDOM[8'h26][9:6]; + useAltOnNaCtrs_1_48 = _RANDOM[8'h26][13:10]; + useAltOnNaCtrs_1_49 = _RANDOM[8'h26][17:14]; + useAltOnNaCtrs_1_50 = _RANDOM[8'h26][21:18]; + useAltOnNaCtrs_1_51 = _RANDOM[8'h26][25:22]; + useAltOnNaCtrs_1_52 = _RANDOM[8'h26][29:26]; + useAltOnNaCtrs_1_53 = {_RANDOM[8'h26][31:30], _RANDOM[8'h27][1:0]}; + useAltOnNaCtrs_1_54 = _RANDOM[8'h27][5:2]; + useAltOnNaCtrs_1_55 = _RANDOM[8'h27][9:6]; + useAltOnNaCtrs_1_56 = _RANDOM[8'h27][13:10]; + useAltOnNaCtrs_1_57 = _RANDOM[8'h27][17:14]; + useAltOnNaCtrs_1_58 = _RANDOM[8'h27][21:18]; + useAltOnNaCtrs_1_59 = _RANDOM[8'h27][25:22]; + useAltOnNaCtrs_1_60 = _RANDOM[8'h27][29:26]; + useAltOnNaCtrs_1_61 = {_RANDOM[8'h27][31:30], _RANDOM[8'h28][1:0]}; + useAltOnNaCtrs_1_62 = _RANDOM[8'h28][5:2]; + useAltOnNaCtrs_1_63 = _RANDOM[8'h28][9:6]; + useAltOnNaCtrs_1_64 = _RANDOM[8'h28][13:10]; + useAltOnNaCtrs_1_65 = _RANDOM[8'h28][17:14]; + useAltOnNaCtrs_1_66 = _RANDOM[8'h28][21:18]; + useAltOnNaCtrs_1_67 = _RANDOM[8'h28][25:22]; + useAltOnNaCtrs_1_68 = _RANDOM[8'h28][29:26]; + useAltOnNaCtrs_1_69 = {_RANDOM[8'h28][31:30], _RANDOM[8'h29][1:0]}; + useAltOnNaCtrs_1_70 = _RANDOM[8'h29][5:2]; + useAltOnNaCtrs_1_71 = _RANDOM[8'h29][9:6]; + useAltOnNaCtrs_1_72 = _RANDOM[8'h29][13:10]; + useAltOnNaCtrs_1_73 = _RANDOM[8'h29][17:14]; + useAltOnNaCtrs_1_74 = _RANDOM[8'h29][21:18]; + useAltOnNaCtrs_1_75 = _RANDOM[8'h29][25:22]; + useAltOnNaCtrs_1_76 = _RANDOM[8'h29][29:26]; + useAltOnNaCtrs_1_77 = {_RANDOM[8'h29][31:30], _RANDOM[8'h2A][1:0]}; + useAltOnNaCtrs_1_78 = _RANDOM[8'h2A][5:2]; + useAltOnNaCtrs_1_79 = _RANDOM[8'h2A][9:6]; + useAltOnNaCtrs_1_80 = _RANDOM[8'h2A][13:10]; + useAltOnNaCtrs_1_81 = _RANDOM[8'h2A][17:14]; + useAltOnNaCtrs_1_82 = _RANDOM[8'h2A][21:18]; + useAltOnNaCtrs_1_83 = _RANDOM[8'h2A][25:22]; + useAltOnNaCtrs_1_84 = _RANDOM[8'h2A][29:26]; + useAltOnNaCtrs_1_85 = {_RANDOM[8'h2A][31:30], _RANDOM[8'h2B][1:0]}; + useAltOnNaCtrs_1_86 = _RANDOM[8'h2B][5:2]; + useAltOnNaCtrs_1_87 = _RANDOM[8'h2B][9:6]; + useAltOnNaCtrs_1_88 = _RANDOM[8'h2B][13:10]; + useAltOnNaCtrs_1_89 = _RANDOM[8'h2B][17:14]; + useAltOnNaCtrs_1_90 = _RANDOM[8'h2B][21:18]; + useAltOnNaCtrs_1_91 = _RANDOM[8'h2B][25:22]; + useAltOnNaCtrs_1_92 = _RANDOM[8'h2B][29:26]; + useAltOnNaCtrs_1_93 = {_RANDOM[8'h2B][31:30], _RANDOM[8'h2C][1:0]}; + useAltOnNaCtrs_1_94 = _RANDOM[8'h2C][5:2]; + useAltOnNaCtrs_1_95 = _RANDOM[8'h2C][9:6]; + useAltOnNaCtrs_1_96 = _RANDOM[8'h2C][13:10]; + useAltOnNaCtrs_1_97 = _RANDOM[8'h2C][17:14]; + useAltOnNaCtrs_1_98 = _RANDOM[8'h2C][21:18]; + useAltOnNaCtrs_1_99 = _RANDOM[8'h2C][25:22]; + useAltOnNaCtrs_1_100 = _RANDOM[8'h2C][29:26]; + useAltOnNaCtrs_1_101 = {_RANDOM[8'h2C][31:30], _RANDOM[8'h2D][1:0]}; + useAltOnNaCtrs_1_102 = _RANDOM[8'h2D][5:2]; + useAltOnNaCtrs_1_103 = _RANDOM[8'h2D][9:6]; + useAltOnNaCtrs_1_104 = _RANDOM[8'h2D][13:10]; + useAltOnNaCtrs_1_105 = _RANDOM[8'h2D][17:14]; + useAltOnNaCtrs_1_106 = _RANDOM[8'h2D][21:18]; + useAltOnNaCtrs_1_107 = _RANDOM[8'h2D][25:22]; + useAltOnNaCtrs_1_108 = _RANDOM[8'h2D][29:26]; + useAltOnNaCtrs_1_109 = {_RANDOM[8'h2D][31:30], _RANDOM[8'h2E][1:0]}; + useAltOnNaCtrs_1_110 = _RANDOM[8'h2E][5:2]; + useAltOnNaCtrs_1_111 = _RANDOM[8'h2E][9:6]; + useAltOnNaCtrs_1_112 = _RANDOM[8'h2E][13:10]; + useAltOnNaCtrs_1_113 = _RANDOM[8'h2E][17:14]; + useAltOnNaCtrs_1_114 = _RANDOM[8'h2E][21:18]; + useAltOnNaCtrs_1_115 = _RANDOM[8'h2E][25:22]; + useAltOnNaCtrs_1_116 = _RANDOM[8'h2E][29:26]; + useAltOnNaCtrs_1_117 = {_RANDOM[8'h2E][31:30], _RANDOM[8'h2F][1:0]}; + useAltOnNaCtrs_1_118 = _RANDOM[8'h2F][5:2]; + useAltOnNaCtrs_1_119 = _RANDOM[8'h2F][9:6]; + useAltOnNaCtrs_1_120 = _RANDOM[8'h2F][13:10]; + useAltOnNaCtrs_1_121 = _RANDOM[8'h2F][17:14]; + useAltOnNaCtrs_1_122 = _RANDOM[8'h2F][21:18]; + useAltOnNaCtrs_1_123 = _RANDOM[8'h2F][25:22]; + useAltOnNaCtrs_1_124 = _RANDOM[8'h2F][29:26]; + useAltOnNaCtrs_1_125 = {_RANDOM[8'h2F][31:30], _RANDOM[8'h30][1:0]}; + useAltOnNaCtrs_1_126 = _RANDOM[8'h30][5:2]; + useAltOnNaCtrs_1_127 = _RANDOM[8'h30][9:6]; + s2_provideds_0 = _RANDOM[8'h32][28]; + s2_provideds_1 = _RANDOM[8'h32][29]; + s2_providers_0 = _RANDOM[8'h32][31:30]; + s2_providers_1 = _RANDOM[8'h33][1:0]; + s2_providerResps_0_ctr = _RANDOM[8'h33][4:2]; + s2_providerResps_0_u = _RANDOM[8'h33][5]; + s2_providerResps_0_unconf = _RANDOM[8'h33][6]; + s2_providerResps_1_ctr = _RANDOM[8'h33][9:7]; + s2_providerResps_1_u = _RANDOM[8'h33][10]; + s2_providerResps_1_unconf = _RANDOM[8'h33][11]; + s2_altUsed_0 = _RANDOM[8'h33][12]; + s2_altUsed_1 = _RANDOM[8'h33][13]; + s2_tageTakens_dup_0_0 = _RANDOM[8'h33][14]; + s2_tageTakens_dup_0_1 = _RANDOM[8'h33][15]; + s2_tageTakens_dup_1_0 = _RANDOM[8'h33][16]; + s2_tageTakens_dup_1_1 = _RANDOM[8'h33][17]; + s2_tageTakens_dup_2_0 = _RANDOM[8'h33][18]; + s2_tageTakens_dup_2_1 = _RANDOM[8'h33][19]; + s2_tageTakens_dup_3_0 = _RANDOM[8'h33][20]; + s2_tageTakens_dup_3_1 = _RANDOM[8'h33][21]; + s2_finalAltPreds_0 = _RANDOM[8'h33][22]; + s2_finalAltPreds_1 = _RANDOM[8'h33][23]; + s2_basecnts_0 = _RANDOM[8'h33][25:24]; + s2_basecnts_1 = _RANDOM[8'h33][27:26]; + resp_meta_providers_0_valid_r = _RANDOM[8'h33][30]; + resp_meta_providers_0_bits_r = {_RANDOM[8'h33][31], _RANDOM[8'h34][0]}; + resp_meta_providerResps_0_r_ctr = _RANDOM[8'h34][3:1]; + resp_meta_providerResps_0_r_u = _RANDOM[8'h34][4]; + resp_meta_providerResps_0_r_unconf = _RANDOM[8'h34][5]; + allocatableSlots = _RANDOM[8'h34][9:6]; + resp_meta_allocates_0_r = _RANDOM[8'h34][13:10]; + resp_meta_altUsed_0_r = _RANDOM[8'h34][14]; + resp_meta_altDiffers_0_r = _RANDOM[8'h34][15]; + resp_meta_takens_0_r = _RANDOM[8'h34][16]; + resp_meta_basecnts_0_r = _RANDOM[8'h34][18:17]; + tage_enable_dup_REG = _RANDOM[8'h34][19]; + allocLFSR_lfsr = {_RANDOM[8'h34][31:20], _RANDOM[8'h35], _RANDOM[8'h36][19:0]}; + resp_meta_providers_1_valid_r = _RANDOM[8'h36][20]; + resp_meta_providers_1_bits_r = _RANDOM[8'h36][22:21]; + resp_meta_providerResps_1_r_ctr = _RANDOM[8'h36][25:23]; + resp_meta_providerResps_1_r_u = _RANDOM[8'h36][26]; + resp_meta_providerResps_1_r_unconf = _RANDOM[8'h36][27]; + allocatableSlots_1 = _RANDOM[8'h36][31:28]; + resp_meta_allocates_1_r = _RANDOM[8'h37][3:0]; + resp_meta_altUsed_1_r = _RANDOM[8'h37][4]; + resp_meta_altDiffers_1_r = _RANDOM[8'h37][5]; + resp_meta_takens_1_r = _RANDOM[8'h37][6]; + resp_meta_basecnts_1_r = _RANDOM[8'h37][8:7]; + tage_enable_dup_REG_1 = _RANDOM[8'h37][9]; + allocLFSR_lfsr_1 = {_RANDOM[8'h37][31:10], _RANDOM[8'h38], _RANDOM[8'h39][9:0]}; + tables_0_io_update_reset_u_0_REG = _RANDOM[8'h39][10]; + tables_0_io_update_mask_0_REG = _RANDOM[8'h39][11]; + tables_0_io_update_takens_0_r = _RANDOM[8'h39][12]; + tables_0_io_update_alloc_0_r = _RANDOM[8'h39][13]; + tables_0_io_update_oldCtrs_0_r = _RANDOM[8'h39][16:14]; + tables_0_io_update_uMask_0_r = _RANDOM[8'h39][17]; + tables_0_io_update_us_0_r = _RANDOM[8'h39][18]; + tables_1_io_update_reset_u_0_REG = _RANDOM[8'h47][16]; + tables_1_io_update_mask_0_REG = _RANDOM[8'h47][17]; + tables_1_io_update_takens_0_r = _RANDOM[8'h47][18]; + tables_1_io_update_alloc_0_r = _RANDOM[8'h47][19]; + tables_1_io_update_oldCtrs_0_r = _RANDOM[8'h47][22:20]; + tables_1_io_update_uMask_0_r = _RANDOM[8'h47][23]; + tables_1_io_update_us_0_r = _RANDOM[8'h47][24]; + tables_2_io_update_reset_u_0_REG = _RANDOM[8'h55][22]; + tables_2_io_update_mask_0_REG = _RANDOM[8'h55][23]; + tables_2_io_update_takens_0_r = _RANDOM[8'h55][24]; + tables_2_io_update_alloc_0_r = _RANDOM[8'h55][25]; + tables_2_io_update_oldCtrs_0_r = _RANDOM[8'h55][28:26]; + tables_2_io_update_uMask_0_r = _RANDOM[8'h55][29]; + tables_2_io_update_us_0_r = _RANDOM[8'h55][30]; + tables_3_io_update_reset_u_0_REG = _RANDOM[8'h63][28]; + tables_3_io_update_mask_0_REG = _RANDOM[8'h63][29]; + tables_3_io_update_takens_0_r = _RANDOM[8'h63][30]; + tables_3_io_update_alloc_0_r = _RANDOM[8'h63][31]; + tables_3_io_update_oldCtrs_0_r = _RANDOM[8'h64][2:0]; + tables_3_io_update_uMask_0_r = _RANDOM[8'h64][3]; + tables_3_io_update_us_0_r = _RANDOM[8'h64][4]; + tables_0_io_update_reset_u_1_REG = _RANDOM[8'h72][2]; + tables_0_io_update_mask_1_REG = _RANDOM[8'h72][3]; + tables_0_io_update_takens_1_r = _RANDOM[8'h72][4]; + tables_0_io_update_alloc_1_r = _RANDOM[8'h72][5]; + tables_0_io_update_oldCtrs_1_r = _RANDOM[8'h72][8:6]; + tables_0_io_update_uMask_1_r = _RANDOM[8'h72][9]; + tables_0_io_update_us_1_r = _RANDOM[8'h72][10]; + tables_0_io_update_pc_r_1 = {_RANDOM[8'h72][31:11], _RANDOM[8'h73][19:0]}; + tables_0_io_update_folded_hist_r_1_hist_14_folded_hist = _RANDOM[8'h74][24:17]; + tables_0_io_update_folded_hist_r_1_hist_7_folded_hist = _RANDOM[8'h76][12:6]; + tables_1_io_update_reset_u_1_REG = _RANDOM[8'h80][8]; + tables_1_io_update_mask_1_REG = _RANDOM[8'h80][9]; + tables_1_io_update_takens_1_r = _RANDOM[8'h80][10]; + tables_1_io_update_alloc_1_r = _RANDOM[8'h80][11]; + tables_1_io_update_oldCtrs_1_r = _RANDOM[8'h80][14:12]; + tables_1_io_update_uMask_1_r = _RANDOM[8'h80][15]; + tables_1_io_update_us_1_r = _RANDOM[8'h80][16]; + tables_1_io_update_pc_r_1 = {_RANDOM[8'h80][31:17], _RANDOM[8'h81][25:0]}; + tables_1_io_update_folded_hist_r_1_hist_15_folded_hist = _RANDOM[8'h82][22:16]; + tables_1_io_update_folded_hist_r_1_hist_4_folded_hist = _RANDOM[8'h85][10:3]; + tables_1_io_update_folded_hist_r_1_hist_1_folded_hist = + {_RANDOM[8'h85][31:27], _RANDOM[8'h86][5:0]}; + tables_2_io_update_reset_u_1_REG = _RANDOM[8'h8E][14]; + tables_2_io_update_mask_1_REG = _RANDOM[8'h8E][15]; + tables_2_io_update_takens_1_r = _RANDOM[8'h8E][16]; + tables_2_io_update_alloc_1_r = _RANDOM[8'h8E][17]; + tables_2_io_update_oldCtrs_1_r = _RANDOM[8'h8E][20:18]; + tables_2_io_update_uMask_1_r = _RANDOM[8'h8E][21]; + tables_2_io_update_us_1_r = _RANDOM[8'h8E][22]; + tables_2_io_update_pc_r_1 = {_RANDOM[8'h8E][31:23], _RANDOM[8'h8F]}; + tables_2_io_update_folded_hist_r_1_hist_17_folded_hist = _RANDOM[8'h90][10:0]; + tables_2_io_update_folded_hist_r_1_hist_9_folded_hist = _RANDOM[8'h92][9:3]; + tables_2_io_update_folded_hist_r_1_hist_3_folded_hist = _RANDOM[8'h93][24:17]; + tables_3_io_update_reset_u_1_REG = _RANDOM[8'h9C][20]; + tables_3_io_update_mask_1_REG = _RANDOM[8'h9C][21]; + tables_3_io_update_takens_1_r = _RANDOM[8'h9C][22]; + tables_3_io_update_alloc_1_r = _RANDOM[8'h9C][23]; + tables_3_io_update_oldCtrs_1_r = _RANDOM[8'h9C][26:24]; + tables_3_io_update_uMask_1_r = _RANDOM[8'h9C][27]; + tables_3_io_update_us_1_r = _RANDOM[8'h9C][28]; + tables_3_io_update_pc_r_1 = + {_RANDOM[8'h9C][31:29], _RANDOM[8'h9D], _RANDOM[8'h9E][5:0]}; + tables_3_io_update_folded_hist_r_1_hist_16_folded_hist = _RANDOM[8'h9E][27:17]; + tables_3_io_update_folded_hist_r_1_hist_8_folded_hist = _RANDOM[8'hA0][23:16]; + tables_3_io_update_folded_hist_r_1_hist_5_folded_hist = _RANDOM[8'hA1][14:8]; + REG_2_0 = _RANDOM[8'hAA][26]; + REG_2_1 = _RANDOM[8'hAA][27]; + r_0 = _RANDOM[8'hAA][29:28]; + r_1 = _RANDOM[8'hAA][31:30]; + bt_io_update_pc_r = {_RANDOM[8'hAB], _RANDOM[8'hAC][8:0]}; + r_1_0 = _RANDOM[8'hAC][9]; + r_1_1 = _RANDOM[8'hAC][10]; + scThresholds_0_ctr = _RANDOM[8'hAD][31:27]; + scThresholds_0_thres = _RANDOM[8'hAE][7:0]; + scThresholds_1_ctr = _RANDOM[8'hAE][12:8]; + scThresholds_1_thres = _RANDOM[8'hAE][20:13]; + s2_scTableSums_0 = _RANDOM[8'hAE][29:21]; + s2_scTableSums_1 = {_RANDOM[8'hAE][31:30], _RANDOM[8'hAF][6:0]}; + s2_tagePrvdCtrCentered_r = _RANDOM[8'hAF][9:7]; + s2_scResps_r_0_ctrs_0_0 = _RANDOM[8'hAF][15:10]; + s2_scResps_r_0_ctrs_0_1 = _RANDOM[8'hAF][21:16]; + s2_scResps_r_1_ctrs_0_0 = _RANDOM[8'hB0][7:2]; + s2_scResps_r_1_ctrs_0_1 = _RANDOM[8'hB0][13:8]; + s2_scResps_r_2_ctrs_0_0 = _RANDOM[8'hB0][31:26]; + s2_scResps_r_2_ctrs_0_1 = _RANDOM[8'hB1][5:0]; + s2_scResps_r_3_ctrs_0_0 = _RANDOM[8'hB1][23:18]; + s2_scResps_r_3_ctrs_0_1 = _RANDOM[8'hB1][29:24]; + resp_meta_scMeta_tageTakens_0_r = _RANDOM[8'hB2][12]; + resp_meta_scMeta_scUsed_0_r = _RANDOM[8'hB2][13]; + resp_meta_scMeta_scPreds_0_r = _RANDOM[8'hB2][14]; + r_2_0 = _RANDOM[8'hB2][20:15]; + r_2_1 = _RANDOM[8'hB2][26:21]; + r_2_2 = {_RANDOM[8'hB2][31:27], _RANDOM[8'hB3][0]}; + r_2_3 = _RANDOM[8'hB3][6:1]; + s3_pred_dup_0 = _RANDOM[8'hB3][7]; + s3_pred_dup_1 = _RANDOM[8'hB3][8]; + s3_pred_dup_2 = _RANDOM[8'hB3][9]; + s3_pred_dup_3 = _RANDOM[8'hB3][10]; + sc_enable_dup_REG = _RANDOM[8'hB3][11]; + s2_scTableSums_1_0 = _RANDOM[8'hB3][20:12]; + s2_scTableSums_1_1 = _RANDOM[8'hB3][29:21]; + s2_tagePrvdCtrCentered_r_1 = {_RANDOM[8'hB3][31:30], _RANDOM[8'hB4][0]}; + s2_scResps_r_1_0_ctrs_1_0 = _RANDOM[8'hB4][18:13]; + s2_scResps_r_1_0_ctrs_1_1 = _RANDOM[8'hB4][24:19]; + s2_scResps_r_1_1_ctrs_1_0 = _RANDOM[8'hB5][10:5]; + s2_scResps_r_1_1_ctrs_1_1 = _RANDOM[8'hB5][16:11]; + s2_scResps_r_1_2_ctrs_1_0 = {_RANDOM[8'hB5][31:29], _RANDOM[8'hB6][2:0]}; + s2_scResps_r_1_2_ctrs_1_1 = _RANDOM[8'hB6][8:3]; + s2_scResps_r_1_3_ctrs_1_0 = _RANDOM[8'hB6][26:21]; + s2_scResps_r_1_3_ctrs_1_1 = {_RANDOM[8'hB6][31:27], _RANDOM[8'hB7][0]}; + resp_meta_scMeta_tageTakens_1_r = _RANDOM[8'hB7][3]; + resp_meta_scMeta_scUsed_1_r = _RANDOM[8'hB7][4]; + resp_meta_scMeta_scPreds_1_r = _RANDOM[8'hB7][5]; + r_3_0 = _RANDOM[8'hB7][11:6]; + r_3_1 = _RANDOM[8'hB7][17:12]; + r_3_2 = _RANDOM[8'hB7][23:18]; + r_3_3 = _RANDOM[8'hB7][29:24]; + s3_pred_dup_0_1 = _RANDOM[8'hB7][30]; + s3_pred_dup_1_1 = _RANDOM[8'hB7][31]; + s3_pred_dup_2_1 = _RANDOM[8'hB8][0]; + s3_pred_dup_3_1 = _RANDOM[8'hB8][1]; + sc_enable_dup_REG_1 = _RANDOM[8'hB8][2]; + scTables_0_io_update_mask_0_REG = _RANDOM[8'hB8][3]; + scTables_0_io_update_tagePreds_0_r = _RANDOM[8'hB8][4]; + scTables_0_io_update_takens_0_r = _RANDOM[8'hB8][5]; + scTables_0_io_update_oldCtrs_0_r = _RANDOM[8'hB8][11:6]; + scTables_1_io_update_mask_0_REG = _RANDOM[8'hBE][9]; + scTables_1_io_update_tagePreds_0_r = _RANDOM[8'hBE][10]; + scTables_1_io_update_takens_0_r = _RANDOM[8'hBE][11]; + scTables_1_io_update_oldCtrs_0_r = _RANDOM[8'hBE][17:12]; + scTables_2_io_update_mask_0_REG = _RANDOM[8'hC4][15]; + scTables_2_io_update_tagePreds_0_r = _RANDOM[8'hC4][16]; + scTables_2_io_update_takens_0_r = _RANDOM[8'hC4][17]; + scTables_2_io_update_oldCtrs_0_r = _RANDOM[8'hC4][23:18]; + scTables_3_io_update_mask_0_REG = _RANDOM[8'hCA][21]; + scTables_3_io_update_tagePreds_0_r = _RANDOM[8'hCA][22]; + scTables_3_io_update_takens_0_r = _RANDOM[8'hCA][23]; + scTables_3_io_update_oldCtrs_0_r = _RANDOM[8'hCA][29:24]; + scTables_0_io_update_mask_1_REG = _RANDOM[8'hD0][27]; + scTables_0_io_update_tagePreds_1_r = _RANDOM[8'hD0][28]; + scTables_0_io_update_takens_1_r = _RANDOM[8'hD0][29]; + scTables_0_io_update_oldCtrs_1_r = {_RANDOM[8'hD0][31:30], _RANDOM[8'hD1][3:0]}; + scTables_0_io_update_pc_r_1 = {_RANDOM[8'hD1][31:4], _RANDOM[8'hD2][12:0]}; + scTables_1_io_update_mask_1_REG = _RANDOM[8'hD7][1]; + scTables_1_io_update_tagePreds_1_r = _RANDOM[8'hD7][2]; + scTables_1_io_update_takens_1_r = _RANDOM[8'hD7][3]; + scTables_1_io_update_oldCtrs_1_r = _RANDOM[8'hD7][9:4]; + scTables_1_io_update_pc_r_1 = {_RANDOM[8'hD7][31:10], _RANDOM[8'hD8][18:0]}; + scTables_1_io_update_folded_hist_r_1_hist_12_folded_hist = _RANDOM[8'hDA][4:1]; + scTables_2_io_update_mask_1_REG = _RANDOM[8'hDD][7]; + scTables_2_io_update_tagePreds_1_r = _RANDOM[8'hDD][8]; + scTables_2_io_update_takens_1_r = _RANDOM[8'hDD][9]; + scTables_2_io_update_oldCtrs_1_r = _RANDOM[8'hDD][15:10]; + scTables_2_io_update_pc_r_1 = {_RANDOM[8'hDD][31:16], _RANDOM[8'hDE][24:0]}; + scTables_2_io_update_folded_hist_r_1_hist_11_folded_hist = _RANDOM[8'hE0][18:11]; + scTables_3_io_update_mask_1_REG = _RANDOM[8'hE3][13]; + scTables_3_io_update_tagePreds_1_r = _RANDOM[8'hE3][14]; + scTables_3_io_update_takens_1_r = _RANDOM[8'hE3][15]; + scTables_3_io_update_oldCtrs_1_r = _RANDOM[8'hE3][21:16]; + scTables_3_io_update_pc_r_1 = {_RANDOM[8'hE3][31:22], _RANDOM[8'hE4][30:0]}; + scTables_3_io_update_folded_hist_r_1_hist_2_folded_hist = _RANDOM[8'hE8][31:24]; + io_perf_0_value_REG = _RANDOM[8'hE9][20:19]; + io_perf_0_value_REG_1 = _RANDOM[8'hE9][22:21]; + io_perf_1_value_REG = _RANDOM[8'hE9][24:23]; + io_perf_1_value_REG_1 = _RANDOM[8'hE9][26:25]; + io_perf_2_value_REG = _RANDOM[8'hE9][28:27]; + io_perf_2_value_REG_1 = _RANDOM[8'hE9][30:29]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + bankTickCtrDistanceToTops_0 = 7'h7F; + bankTickCtrDistanceToTops_1 = 7'h7F; + bankTickCtrs_0 = 7'h0; + bankTickCtrs_1 = 7'h0; + useAltOnNaCtrs_0_0 = 4'h8; + useAltOnNaCtrs_0_1 = 4'h8; + useAltOnNaCtrs_0_2 = 4'h8; + useAltOnNaCtrs_0_3 = 4'h8; + useAltOnNaCtrs_0_4 = 4'h8; + useAltOnNaCtrs_0_5 = 4'h8; + useAltOnNaCtrs_0_6 = 4'h8; + useAltOnNaCtrs_0_7 = 4'h8; + useAltOnNaCtrs_0_8 = 4'h8; + useAltOnNaCtrs_0_9 = 4'h8; + useAltOnNaCtrs_0_10 = 4'h8; + useAltOnNaCtrs_0_11 = 4'h8; + useAltOnNaCtrs_0_12 = 4'h8; + useAltOnNaCtrs_0_13 = 4'h8; + useAltOnNaCtrs_0_14 = 4'h8; + useAltOnNaCtrs_0_15 = 4'h8; + useAltOnNaCtrs_0_16 = 4'h8; + useAltOnNaCtrs_0_17 = 4'h8; + useAltOnNaCtrs_0_18 = 4'h8; + useAltOnNaCtrs_0_19 = 4'h8; + useAltOnNaCtrs_0_20 = 4'h8; + useAltOnNaCtrs_0_21 = 4'h8; + useAltOnNaCtrs_0_22 = 4'h8; + useAltOnNaCtrs_0_23 = 4'h8; + useAltOnNaCtrs_0_24 = 4'h8; + useAltOnNaCtrs_0_25 = 4'h8; + useAltOnNaCtrs_0_26 = 4'h8; + useAltOnNaCtrs_0_27 = 4'h8; + useAltOnNaCtrs_0_28 = 4'h8; + useAltOnNaCtrs_0_29 = 4'h8; + useAltOnNaCtrs_0_30 = 4'h8; + useAltOnNaCtrs_0_31 = 4'h8; + useAltOnNaCtrs_0_32 = 4'h8; + useAltOnNaCtrs_0_33 = 4'h8; + useAltOnNaCtrs_0_34 = 4'h8; + useAltOnNaCtrs_0_35 = 4'h8; + useAltOnNaCtrs_0_36 = 4'h8; + useAltOnNaCtrs_0_37 = 4'h8; + useAltOnNaCtrs_0_38 = 4'h8; + useAltOnNaCtrs_0_39 = 4'h8; + useAltOnNaCtrs_0_40 = 4'h8; + useAltOnNaCtrs_0_41 = 4'h8; + useAltOnNaCtrs_0_42 = 4'h8; + useAltOnNaCtrs_0_43 = 4'h8; + useAltOnNaCtrs_0_44 = 4'h8; + useAltOnNaCtrs_0_45 = 4'h8; + useAltOnNaCtrs_0_46 = 4'h8; + useAltOnNaCtrs_0_47 = 4'h8; + useAltOnNaCtrs_0_48 = 4'h8; + useAltOnNaCtrs_0_49 = 4'h8; + useAltOnNaCtrs_0_50 = 4'h8; + useAltOnNaCtrs_0_51 = 4'h8; + useAltOnNaCtrs_0_52 = 4'h8; + useAltOnNaCtrs_0_53 = 4'h8; + useAltOnNaCtrs_0_54 = 4'h8; + useAltOnNaCtrs_0_55 = 4'h8; + useAltOnNaCtrs_0_56 = 4'h8; + useAltOnNaCtrs_0_57 = 4'h8; + useAltOnNaCtrs_0_58 = 4'h8; + useAltOnNaCtrs_0_59 = 4'h8; + useAltOnNaCtrs_0_60 = 4'h8; + useAltOnNaCtrs_0_61 = 4'h8; + useAltOnNaCtrs_0_62 = 4'h8; + useAltOnNaCtrs_0_63 = 4'h8; + useAltOnNaCtrs_0_64 = 4'h8; + useAltOnNaCtrs_0_65 = 4'h8; + useAltOnNaCtrs_0_66 = 4'h8; + useAltOnNaCtrs_0_67 = 4'h8; + useAltOnNaCtrs_0_68 = 4'h8; + useAltOnNaCtrs_0_69 = 4'h8; + useAltOnNaCtrs_0_70 = 4'h8; + useAltOnNaCtrs_0_71 = 4'h8; + useAltOnNaCtrs_0_72 = 4'h8; + useAltOnNaCtrs_0_73 = 4'h8; + useAltOnNaCtrs_0_74 = 4'h8; + useAltOnNaCtrs_0_75 = 4'h8; + useAltOnNaCtrs_0_76 = 4'h8; + useAltOnNaCtrs_0_77 = 4'h8; + useAltOnNaCtrs_0_78 = 4'h8; + useAltOnNaCtrs_0_79 = 4'h8; + useAltOnNaCtrs_0_80 = 4'h8; + useAltOnNaCtrs_0_81 = 4'h8; + useAltOnNaCtrs_0_82 = 4'h8; + useAltOnNaCtrs_0_83 = 4'h8; + useAltOnNaCtrs_0_84 = 4'h8; + useAltOnNaCtrs_0_85 = 4'h8; + useAltOnNaCtrs_0_86 = 4'h8; + useAltOnNaCtrs_0_87 = 4'h8; + useAltOnNaCtrs_0_88 = 4'h8; + useAltOnNaCtrs_0_89 = 4'h8; + useAltOnNaCtrs_0_90 = 4'h8; + useAltOnNaCtrs_0_91 = 4'h8; + useAltOnNaCtrs_0_92 = 4'h8; + useAltOnNaCtrs_0_93 = 4'h8; + useAltOnNaCtrs_0_94 = 4'h8; + useAltOnNaCtrs_0_95 = 4'h8; + useAltOnNaCtrs_0_96 = 4'h8; + useAltOnNaCtrs_0_97 = 4'h8; + useAltOnNaCtrs_0_98 = 4'h8; + useAltOnNaCtrs_0_99 = 4'h8; + useAltOnNaCtrs_0_100 = 4'h8; + useAltOnNaCtrs_0_101 = 4'h8; + useAltOnNaCtrs_0_102 = 4'h8; + useAltOnNaCtrs_0_103 = 4'h8; + useAltOnNaCtrs_0_104 = 4'h8; + useAltOnNaCtrs_0_105 = 4'h8; + useAltOnNaCtrs_0_106 = 4'h8; + useAltOnNaCtrs_0_107 = 4'h8; + useAltOnNaCtrs_0_108 = 4'h8; + useAltOnNaCtrs_0_109 = 4'h8; + useAltOnNaCtrs_0_110 = 4'h8; + useAltOnNaCtrs_0_111 = 4'h8; + useAltOnNaCtrs_0_112 = 4'h8; + useAltOnNaCtrs_0_113 = 4'h8; + useAltOnNaCtrs_0_114 = 4'h8; + useAltOnNaCtrs_0_115 = 4'h8; + useAltOnNaCtrs_0_116 = 4'h8; + useAltOnNaCtrs_0_117 = 4'h8; + useAltOnNaCtrs_0_118 = 4'h8; + useAltOnNaCtrs_0_119 = 4'h8; + useAltOnNaCtrs_0_120 = 4'h8; + useAltOnNaCtrs_0_121 = 4'h8; + useAltOnNaCtrs_0_122 = 4'h8; + useAltOnNaCtrs_0_123 = 4'h8; + useAltOnNaCtrs_0_124 = 4'h8; + useAltOnNaCtrs_0_125 = 4'h8; + useAltOnNaCtrs_0_126 = 4'h8; + useAltOnNaCtrs_0_127 = 4'h8; + useAltOnNaCtrs_1_0 = 4'h8; + useAltOnNaCtrs_1_1 = 4'h8; + useAltOnNaCtrs_1_2 = 4'h8; + useAltOnNaCtrs_1_3 = 4'h8; + useAltOnNaCtrs_1_4 = 4'h8; + useAltOnNaCtrs_1_5 = 4'h8; + useAltOnNaCtrs_1_6 = 4'h8; + useAltOnNaCtrs_1_7 = 4'h8; + useAltOnNaCtrs_1_8 = 4'h8; + useAltOnNaCtrs_1_9 = 4'h8; + useAltOnNaCtrs_1_10 = 4'h8; + useAltOnNaCtrs_1_11 = 4'h8; + useAltOnNaCtrs_1_12 = 4'h8; + useAltOnNaCtrs_1_13 = 4'h8; + useAltOnNaCtrs_1_14 = 4'h8; + useAltOnNaCtrs_1_15 = 4'h8; + useAltOnNaCtrs_1_16 = 4'h8; + useAltOnNaCtrs_1_17 = 4'h8; + useAltOnNaCtrs_1_18 = 4'h8; + useAltOnNaCtrs_1_19 = 4'h8; + useAltOnNaCtrs_1_20 = 4'h8; + useAltOnNaCtrs_1_21 = 4'h8; + useAltOnNaCtrs_1_22 = 4'h8; + useAltOnNaCtrs_1_23 = 4'h8; + useAltOnNaCtrs_1_24 = 4'h8; + useAltOnNaCtrs_1_25 = 4'h8; + useAltOnNaCtrs_1_26 = 4'h8; + useAltOnNaCtrs_1_27 = 4'h8; + useAltOnNaCtrs_1_28 = 4'h8; + useAltOnNaCtrs_1_29 = 4'h8; + useAltOnNaCtrs_1_30 = 4'h8; + useAltOnNaCtrs_1_31 = 4'h8; + useAltOnNaCtrs_1_32 = 4'h8; + useAltOnNaCtrs_1_33 = 4'h8; + useAltOnNaCtrs_1_34 = 4'h8; + useAltOnNaCtrs_1_35 = 4'h8; + useAltOnNaCtrs_1_36 = 4'h8; + useAltOnNaCtrs_1_37 = 4'h8; + useAltOnNaCtrs_1_38 = 4'h8; + useAltOnNaCtrs_1_39 = 4'h8; + useAltOnNaCtrs_1_40 = 4'h8; + useAltOnNaCtrs_1_41 = 4'h8; + useAltOnNaCtrs_1_42 = 4'h8; + useAltOnNaCtrs_1_43 = 4'h8; + useAltOnNaCtrs_1_44 = 4'h8; + useAltOnNaCtrs_1_45 = 4'h8; + useAltOnNaCtrs_1_46 = 4'h8; + useAltOnNaCtrs_1_47 = 4'h8; + useAltOnNaCtrs_1_48 = 4'h8; + useAltOnNaCtrs_1_49 = 4'h8; + useAltOnNaCtrs_1_50 = 4'h8; + useAltOnNaCtrs_1_51 = 4'h8; + useAltOnNaCtrs_1_52 = 4'h8; + useAltOnNaCtrs_1_53 = 4'h8; + useAltOnNaCtrs_1_54 = 4'h8; + useAltOnNaCtrs_1_55 = 4'h8; + useAltOnNaCtrs_1_56 = 4'h8; + useAltOnNaCtrs_1_57 = 4'h8; + useAltOnNaCtrs_1_58 = 4'h8; + useAltOnNaCtrs_1_59 = 4'h8; + useAltOnNaCtrs_1_60 = 4'h8; + useAltOnNaCtrs_1_61 = 4'h8; + useAltOnNaCtrs_1_62 = 4'h8; + useAltOnNaCtrs_1_63 = 4'h8; + useAltOnNaCtrs_1_64 = 4'h8; + useAltOnNaCtrs_1_65 = 4'h8; + useAltOnNaCtrs_1_66 = 4'h8; + useAltOnNaCtrs_1_67 = 4'h8; + useAltOnNaCtrs_1_68 = 4'h8; + useAltOnNaCtrs_1_69 = 4'h8; + useAltOnNaCtrs_1_70 = 4'h8; + useAltOnNaCtrs_1_71 = 4'h8; + useAltOnNaCtrs_1_72 = 4'h8; + useAltOnNaCtrs_1_73 = 4'h8; + useAltOnNaCtrs_1_74 = 4'h8; + useAltOnNaCtrs_1_75 = 4'h8; + useAltOnNaCtrs_1_76 = 4'h8; + useAltOnNaCtrs_1_77 = 4'h8; + useAltOnNaCtrs_1_78 = 4'h8; + useAltOnNaCtrs_1_79 = 4'h8; + useAltOnNaCtrs_1_80 = 4'h8; + useAltOnNaCtrs_1_81 = 4'h8; + useAltOnNaCtrs_1_82 = 4'h8; + useAltOnNaCtrs_1_83 = 4'h8; + useAltOnNaCtrs_1_84 = 4'h8; + useAltOnNaCtrs_1_85 = 4'h8; + useAltOnNaCtrs_1_86 = 4'h8; + useAltOnNaCtrs_1_87 = 4'h8; + useAltOnNaCtrs_1_88 = 4'h8; + useAltOnNaCtrs_1_89 = 4'h8; + useAltOnNaCtrs_1_90 = 4'h8; + useAltOnNaCtrs_1_91 = 4'h8; + useAltOnNaCtrs_1_92 = 4'h8; + useAltOnNaCtrs_1_93 = 4'h8; + useAltOnNaCtrs_1_94 = 4'h8; + useAltOnNaCtrs_1_95 = 4'h8; + useAltOnNaCtrs_1_96 = 4'h8; + useAltOnNaCtrs_1_97 = 4'h8; + useAltOnNaCtrs_1_98 = 4'h8; + useAltOnNaCtrs_1_99 = 4'h8; + useAltOnNaCtrs_1_100 = 4'h8; + useAltOnNaCtrs_1_101 = 4'h8; + useAltOnNaCtrs_1_102 = 4'h8; + useAltOnNaCtrs_1_103 = 4'h8; + useAltOnNaCtrs_1_104 = 4'h8; + useAltOnNaCtrs_1_105 = 4'h8; + useAltOnNaCtrs_1_106 = 4'h8; + useAltOnNaCtrs_1_107 = 4'h8; + useAltOnNaCtrs_1_108 = 4'h8; + useAltOnNaCtrs_1_109 = 4'h8; + useAltOnNaCtrs_1_110 = 4'h8; + useAltOnNaCtrs_1_111 = 4'h8; + useAltOnNaCtrs_1_112 = 4'h8; + useAltOnNaCtrs_1_113 = 4'h8; + useAltOnNaCtrs_1_114 = 4'h8; + useAltOnNaCtrs_1_115 = 4'h8; + useAltOnNaCtrs_1_116 = 4'h8; + useAltOnNaCtrs_1_117 = 4'h8; + useAltOnNaCtrs_1_118 = 4'h8; + useAltOnNaCtrs_1_119 = 4'h8; + useAltOnNaCtrs_1_120 = 4'h8; + useAltOnNaCtrs_1_121 = 4'h8; + useAltOnNaCtrs_1_122 = 4'h8; + useAltOnNaCtrs_1_123 = 4'h8; + useAltOnNaCtrs_1_124 = 4'h8; + useAltOnNaCtrs_1_125 = 4'h8; + useAltOnNaCtrs_1_126 = 4'h8; + useAltOnNaCtrs_1_127 = 4'h8; + allocLFSR_lfsr = 64'h1234567887654321; + allocLFSR_lfsr_1 = 64'h1234567887654321; + scThresholds_0_ctr = 5'h10; + scThresholds_0_thres = 8'h6; + scThresholds_1_ctr = 5'h10; + scThresholds_1_thres = 8'h6; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + DelayN_2 reset_vector_delay ( + .clock (clock), + .io_in (io_reset_vector), + .io_out (_reset_vector_delay_io_out) + ); + TageTable tables_0 ( + .clock (clock), + .reset (reset), + .io_req_ready (_tables_0_io_req_ready), + .io_req_valid (io_s0_fire_1), + .io_req_bits_pc (io_in_bits_s0_pc_1), + .io_req_bits_folded_hist_hist_14_folded_hist + (io_in_bits_folded_hist_1_hist_14_folded_hist), + .io_req_bits_folded_hist_hist_7_folded_hist + (io_in_bits_folded_hist_1_hist_7_folded_hist), + .io_resps_0_valid (_tables_0_io_resps_0_valid), + .io_resps_0_bits_ctr (_tables_0_io_resps_0_bits_ctr), + .io_resps_0_bits_u (_tables_0_io_resps_0_bits_u), + .io_resps_0_bits_unconf (_tables_0_io_resps_0_bits_unconf), + .io_resps_1_valid (_tables_0_io_resps_1_valid), + .io_resps_1_bits_ctr (_tables_0_io_resps_1_bits_ctr), + .io_resps_1_bits_u (_tables_0_io_resps_1_bits_u), + .io_resps_1_bits_unconf (_tables_0_io_resps_1_bits_unconf), + .io_update_pc (tables_0_io_update_pc_r_1), + .io_update_folded_hist_hist_14_folded_hist + (tables_0_io_update_folded_hist_r_1_hist_14_folded_hist), + .io_update_folded_hist_hist_7_folded_hist + (tables_0_io_update_folded_hist_r_1_hist_7_folded_hist), + .io_update_mask_0 (tables_0_io_update_mask_0_REG), + .io_update_mask_1 (tables_0_io_update_mask_1_REG), + .io_update_takens_0 (tables_0_io_update_takens_0_r), + .io_update_takens_1 (tables_0_io_update_takens_1_r), + .io_update_alloc_0 (tables_0_io_update_alloc_0_r), + .io_update_alloc_1 (tables_0_io_update_alloc_1_r), + .io_update_oldCtrs_0 (tables_0_io_update_oldCtrs_0_r), + .io_update_oldCtrs_1 (tables_0_io_update_oldCtrs_1_r), + .io_update_uMask_0 (tables_0_io_update_uMask_0_r), + .io_update_uMask_1 (tables_0_io_update_uMask_1_r), + .io_update_us_0 (tables_0_io_update_us_0_r), + .io_update_us_1 (tables_0_io_update_us_1_r), + .io_update_reset_u_0 (tables_0_io_update_reset_u_0_REG), + .io_update_reset_u_1 (tables_0_io_update_reset_u_1_REG) + ); + TageTable_1 tables_1 ( + .clock (clock), + .reset (reset), + .io_req_ready (_tables_1_io_req_ready), + .io_req_valid (io_s0_fire_1), + .io_req_bits_pc (io_in_bits_s0_pc_1), + .io_req_bits_folded_hist_hist_15_folded_hist + (io_in_bits_folded_hist_1_hist_15_folded_hist), + .io_req_bits_folded_hist_hist_4_folded_hist + (io_in_bits_folded_hist_1_hist_4_folded_hist), + .io_req_bits_folded_hist_hist_1_folded_hist + (io_in_bits_folded_hist_1_hist_1_folded_hist), + .io_resps_0_valid (_tables_1_io_resps_0_valid), + .io_resps_0_bits_ctr (_tables_1_io_resps_0_bits_ctr), + .io_resps_0_bits_u (_tables_1_io_resps_0_bits_u), + .io_resps_0_bits_unconf (_tables_1_io_resps_0_bits_unconf), + .io_resps_1_valid (_tables_1_io_resps_1_valid), + .io_resps_1_bits_ctr (_tables_1_io_resps_1_bits_ctr), + .io_resps_1_bits_u (_tables_1_io_resps_1_bits_u), + .io_resps_1_bits_unconf (_tables_1_io_resps_1_bits_unconf), + .io_update_pc (tables_1_io_update_pc_r_1), + .io_update_folded_hist_hist_15_folded_hist + (tables_1_io_update_folded_hist_r_1_hist_15_folded_hist), + .io_update_folded_hist_hist_4_folded_hist + (tables_1_io_update_folded_hist_r_1_hist_4_folded_hist), + .io_update_folded_hist_hist_1_folded_hist + (tables_1_io_update_folded_hist_r_1_hist_1_folded_hist), + .io_update_mask_0 (tables_1_io_update_mask_0_REG), + .io_update_mask_1 (tables_1_io_update_mask_1_REG), + .io_update_takens_0 (tables_1_io_update_takens_0_r), + .io_update_takens_1 (tables_1_io_update_takens_1_r), + .io_update_alloc_0 (tables_1_io_update_alloc_0_r), + .io_update_alloc_1 (tables_1_io_update_alloc_1_r), + .io_update_oldCtrs_0 (tables_1_io_update_oldCtrs_0_r), + .io_update_oldCtrs_1 (tables_1_io_update_oldCtrs_1_r), + .io_update_uMask_0 (tables_1_io_update_uMask_0_r), + .io_update_uMask_1 (tables_1_io_update_uMask_1_r), + .io_update_us_0 (tables_1_io_update_us_0_r), + .io_update_us_1 (tables_1_io_update_us_1_r), + .io_update_reset_u_0 (tables_1_io_update_reset_u_0_REG), + .io_update_reset_u_1 (tables_1_io_update_reset_u_1_REG) + ); + TageTable_2 tables_2 ( + .clock (clock), + .reset (reset), + .io_req_ready (_tables_2_io_req_ready), + .io_req_valid (io_s0_fire_1), + .io_req_bits_pc (io_in_bits_s0_pc_1), + .io_req_bits_folded_hist_hist_17_folded_hist + (io_in_bits_folded_hist_1_hist_17_folded_hist), + .io_req_bits_folded_hist_hist_9_folded_hist + (io_in_bits_folded_hist_1_hist_9_folded_hist), + .io_req_bits_folded_hist_hist_3_folded_hist + (io_in_bits_folded_hist_1_hist_3_folded_hist), + .io_resps_0_valid (_tables_2_io_resps_0_valid), + .io_resps_0_bits_ctr (_tables_2_io_resps_0_bits_ctr), + .io_resps_0_bits_u (_tables_2_io_resps_0_bits_u), + .io_resps_0_bits_unconf (_tables_2_io_resps_0_bits_unconf), + .io_resps_1_valid (_tables_2_io_resps_1_valid), + .io_resps_1_bits_ctr (_tables_2_io_resps_1_bits_ctr), + .io_resps_1_bits_u (_tables_2_io_resps_1_bits_u), + .io_resps_1_bits_unconf (_tables_2_io_resps_1_bits_unconf), + .io_update_pc (tables_2_io_update_pc_r_1), + .io_update_folded_hist_hist_17_folded_hist + (tables_2_io_update_folded_hist_r_1_hist_17_folded_hist), + .io_update_folded_hist_hist_9_folded_hist + (tables_2_io_update_folded_hist_r_1_hist_9_folded_hist), + .io_update_folded_hist_hist_3_folded_hist + (tables_2_io_update_folded_hist_r_1_hist_3_folded_hist), + .io_update_mask_0 (tables_2_io_update_mask_0_REG), + .io_update_mask_1 (tables_2_io_update_mask_1_REG), + .io_update_takens_0 (tables_2_io_update_takens_0_r), + .io_update_takens_1 (tables_2_io_update_takens_1_r), + .io_update_alloc_0 (tables_2_io_update_alloc_0_r), + .io_update_alloc_1 (tables_2_io_update_alloc_1_r), + .io_update_oldCtrs_0 (tables_2_io_update_oldCtrs_0_r), + .io_update_oldCtrs_1 (tables_2_io_update_oldCtrs_1_r), + .io_update_uMask_0 (tables_2_io_update_uMask_0_r), + .io_update_uMask_1 (tables_2_io_update_uMask_1_r), + .io_update_us_0 (tables_2_io_update_us_0_r), + .io_update_us_1 (tables_2_io_update_us_1_r), + .io_update_reset_u_0 (tables_2_io_update_reset_u_0_REG), + .io_update_reset_u_1 (tables_2_io_update_reset_u_1_REG) + ); + TageTable_3 tables_3 ( + .clock (clock), + .reset (reset), + .io_req_ready (_tables_3_io_req_ready), + .io_req_valid (io_s0_fire_1), + .io_req_bits_pc (io_in_bits_s0_pc_1), + .io_req_bits_folded_hist_hist_16_folded_hist + (io_in_bits_folded_hist_1_hist_16_folded_hist), + .io_req_bits_folded_hist_hist_8_folded_hist + (io_in_bits_folded_hist_1_hist_8_folded_hist), + .io_req_bits_folded_hist_hist_5_folded_hist + (io_in_bits_folded_hist_1_hist_5_folded_hist), + .io_resps_0_valid (_tables_3_io_resps_0_valid), + .io_resps_0_bits_ctr (_tables_3_io_resps_0_bits_ctr), + .io_resps_0_bits_u (_tables_3_io_resps_0_bits_u), + .io_resps_0_bits_unconf (_tables_3_io_resps_0_bits_unconf), + .io_resps_1_valid (_tables_3_io_resps_1_valid), + .io_resps_1_bits_ctr (_tables_3_io_resps_1_bits_ctr), + .io_resps_1_bits_u (_tables_3_io_resps_1_bits_u), + .io_resps_1_bits_unconf (_tables_3_io_resps_1_bits_unconf), + .io_update_pc (tables_3_io_update_pc_r_1), + .io_update_folded_hist_hist_16_folded_hist + (tables_3_io_update_folded_hist_r_1_hist_16_folded_hist), + .io_update_folded_hist_hist_8_folded_hist + (tables_3_io_update_folded_hist_r_1_hist_8_folded_hist), + .io_update_folded_hist_hist_5_folded_hist + (tables_3_io_update_folded_hist_r_1_hist_5_folded_hist), + .io_update_mask_0 (tables_3_io_update_mask_0_REG), + .io_update_mask_1 (tables_3_io_update_mask_1_REG), + .io_update_takens_0 (tables_3_io_update_takens_0_r), + .io_update_takens_1 (tables_3_io_update_takens_1_r), + .io_update_alloc_0 (tables_3_io_update_alloc_0_r), + .io_update_alloc_1 (tables_3_io_update_alloc_1_r), + .io_update_oldCtrs_0 (tables_3_io_update_oldCtrs_0_r), + .io_update_oldCtrs_1 (tables_3_io_update_oldCtrs_1_r), + .io_update_uMask_0 (tables_3_io_update_uMask_0_r), + .io_update_uMask_1 (tables_3_io_update_uMask_1_r), + .io_update_us_0 (tables_3_io_update_us_0_r), + .io_update_us_1 (tables_3_io_update_us_1_r), + .io_update_reset_u_0 (tables_3_io_update_reset_u_0_REG), + .io_update_reset_u_1 (tables_3_io_update_reset_u_1_REG) + ); + TageBTable bt ( + .clock (clock), + .reset (reset), + .io_req_ready (_bt_io_req_ready), + .io_req_valid (io_s0_fire_1), + .io_req_bits (io_in_bits_s0_pc_1), + .io_s1_cnt_0 (_bt_io_s1_cnt_0), + .io_s1_cnt_1 (_bt_io_s1_cnt_1), + .io_update_mask_0 (REG_2_0), + .io_update_mask_1 (REG_2_1), + .io_update_pc (bt_io_update_pc_r), + .io_update_cnt_0 (r_0), + .io_update_cnt_1 (r_1), + .io_update_takens_0 (r_1_0), + .io_update_takens_1 (r_1_1) + ); + SCTable scTables_0 ( + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_resp_ctrs_0_0 (_scTables_0_io_resp_ctrs_0_0), + .io_resp_ctrs_0_1 (_scTables_0_io_resp_ctrs_0_1), + .io_resp_ctrs_1_0 (_scTables_0_io_resp_ctrs_1_0), + .io_resp_ctrs_1_1 (_scTables_0_io_resp_ctrs_1_1), + .io_update_pc (scTables_0_io_update_pc_r_1), + .io_update_mask_0 (scTables_0_io_update_mask_0_REG), + .io_update_mask_1 (scTables_0_io_update_mask_1_REG), + .io_update_oldCtrs_0 (scTables_0_io_update_oldCtrs_0_r), + .io_update_oldCtrs_1 (scTables_0_io_update_oldCtrs_1_r), + .io_update_tagePreds_0 (scTables_0_io_update_tagePreds_0_r), + .io_update_tagePreds_1 (scTables_0_io_update_tagePreds_1_r), + .io_update_takens_0 (scTables_0_io_update_takens_0_r), + .io_update_takens_1 (scTables_0_io_update_takens_1_r) + ); + SCTable_1 scTables_1 ( + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_12_folded_hist + (io_in_bits_folded_hist_3_hist_12_folded_hist), + .io_resp_ctrs_0_0 (_scTables_1_io_resp_ctrs_0_0), + .io_resp_ctrs_0_1 (_scTables_1_io_resp_ctrs_0_1), + .io_resp_ctrs_1_0 (_scTables_1_io_resp_ctrs_1_0), + .io_resp_ctrs_1_1 (_scTables_1_io_resp_ctrs_1_1), + .io_update_pc (scTables_1_io_update_pc_r_1), + .io_update_folded_hist_hist_12_folded_hist + (scTables_1_io_update_folded_hist_r_1_hist_12_folded_hist), + .io_update_mask_0 (scTables_1_io_update_mask_0_REG), + .io_update_mask_1 (scTables_1_io_update_mask_1_REG), + .io_update_oldCtrs_0 (scTables_1_io_update_oldCtrs_0_r), + .io_update_oldCtrs_1 (scTables_1_io_update_oldCtrs_1_r), + .io_update_tagePreds_0 (scTables_1_io_update_tagePreds_0_r), + .io_update_tagePreds_1 (scTables_1_io_update_tagePreds_1_r), + .io_update_takens_0 (scTables_1_io_update_takens_0_r), + .io_update_takens_1 (scTables_1_io_update_takens_1_r) + ); + SCTable_2 scTables_2 ( + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_11_folded_hist + (io_in_bits_folded_hist_3_hist_11_folded_hist), + .io_resp_ctrs_0_0 (_scTables_2_io_resp_ctrs_0_0), + .io_resp_ctrs_0_1 (_scTables_2_io_resp_ctrs_0_1), + .io_resp_ctrs_1_0 (_scTables_2_io_resp_ctrs_1_0), + .io_resp_ctrs_1_1 (_scTables_2_io_resp_ctrs_1_1), + .io_update_pc (scTables_2_io_update_pc_r_1), + .io_update_folded_hist_hist_11_folded_hist + (scTables_2_io_update_folded_hist_r_1_hist_11_folded_hist), + .io_update_mask_0 (scTables_2_io_update_mask_0_REG), + .io_update_mask_1 (scTables_2_io_update_mask_1_REG), + .io_update_oldCtrs_0 (scTables_2_io_update_oldCtrs_0_r), + .io_update_oldCtrs_1 (scTables_2_io_update_oldCtrs_1_r), + .io_update_tagePreds_0 (scTables_2_io_update_tagePreds_0_r), + .io_update_tagePreds_1 (scTables_2_io_update_tagePreds_1_r), + .io_update_takens_0 (scTables_2_io_update_takens_0_r), + .io_update_takens_1 (scTables_2_io_update_takens_1_r) + ); + SCTable_3 scTables_3 ( + .clock (clock), + .reset (reset), + .io_req_valid (io_s0_fire_3), + .io_req_bits_pc (io_in_bits_s0_pc_3), + .io_req_bits_folded_hist_hist_2_folded_hist + (io_in_bits_folded_hist_3_hist_2_folded_hist), + .io_resp_ctrs_0_0 (_scTables_3_io_resp_ctrs_0_0), + .io_resp_ctrs_0_1 (_scTables_3_io_resp_ctrs_0_1), + .io_resp_ctrs_1_0 (_scTables_3_io_resp_ctrs_1_0), + .io_resp_ctrs_1_1 (_scTables_3_io_resp_ctrs_1_1), + .io_update_pc (scTables_3_io_update_pc_r_1), + .io_update_folded_hist_hist_2_folded_hist + (scTables_3_io_update_folded_hist_r_1_hist_2_folded_hist), + .io_update_mask_0 (scTables_3_io_update_mask_0_REG), + .io_update_mask_1 (scTables_3_io_update_mask_1_REG), + .io_update_oldCtrs_0 (scTables_3_io_update_oldCtrs_0_r), + .io_update_oldCtrs_1 (scTables_3_io_update_oldCtrs_1_r), + .io_update_tagePreds_0 (scTables_3_io_update_tagePreds_0_r), + .io_update_tagePreds_1 (scTables_3_io_update_tagePreds_1_r), + .io_update_takens_0 (scTables_3_io_update_takens_0_r), + .io_update_takens_1 (scTables_3_io_update_takens_1_r) + ); + assign io_out_s2_full_pred_0_br_taken_mask_0 = + tage_enable_dup_REG & s2_tageTakens_dup_0_0; + assign io_out_s2_full_pred_0_br_taken_mask_1 = + tage_enable_dup_REG_1 & s2_tageTakens_dup_0_1; + assign io_out_s2_full_pred_1_br_taken_mask_0 = + tage_enable_dup_REG & s2_tageTakens_dup_1_0; + assign io_out_s2_full_pred_1_br_taken_mask_1 = + tage_enable_dup_REG_1 & s2_tageTakens_dup_1_1; + assign io_out_s2_full_pred_2_br_taken_mask_0 = + tage_enable_dup_REG & s2_tageTakens_dup_2_0; + assign io_out_s2_full_pred_2_br_taken_mask_1 = + tage_enable_dup_REG_1 & s2_tageTakens_dup_2_1; + assign io_out_s2_full_pred_3_br_taken_mask_0 = + tage_enable_dup_REG & s2_tageTakens_dup_3_0; + assign io_out_s2_full_pred_3_br_taken_mask_1 = + tage_enable_dup_REG_1 & s2_tageTakens_dup_3_1; + assign io_out_s3_full_pred_0_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_0; + assign io_out_s3_full_pred_0_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_0_1; + assign io_out_s3_full_pred_1_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_1; + assign io_out_s3_full_pred_1_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_1_1; + assign io_out_s3_full_pred_2_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_2; + assign io_out_s3_full_pred_2_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_2_1; + assign io_out_s3_full_pred_3_br_taken_mask_0 = sc_enable_dup_REG & s3_pred_dup_3; + assign io_out_s3_full_pred_3_br_taken_mask_1 = sc_enable_dup_REG_1 & s3_pred_dup_3_1; + assign io_out_last_stage_meta = + {135'h0, + resp_meta_providers_1_valid_r, + resp_meta_providers_1_bits_r, + resp_meta_providers_0_valid_r, + resp_meta_providers_0_bits_r, + resp_meta_providerResps_1_r_ctr, + resp_meta_providerResps_1_r_u, + resp_meta_providerResps_1_r_unconf, + resp_meta_providerResps_0_r_ctr, + resp_meta_providerResps_0_r_u, + resp_meta_providerResps_0_r_unconf, + resp_meta_altUsed_1_r, + resp_meta_altUsed_0_r, + resp_meta_altDiffers_1_r, + resp_meta_altDiffers_0_r, + resp_meta_basecnts_1_r, + resp_meta_basecnts_0_r, + resp_meta_allocates_1_r, + resp_meta_allocates_0_r, + resp_meta_takens_1_r, + resp_meta_takens_0_r, + resp_meta_scMeta_tageTakens_1_r, + resp_meta_scMeta_tageTakens_0_r, + resp_meta_scMeta_scUsed_1_r, + resp_meta_scMeta_scUsed_0_r, + resp_meta_scMeta_scPreds_1_r, + resp_meta_scMeta_scPreds_0_r, + r_3_3, + r_3_2, + r_3_1, + r_3_0, + r_2_3, + r_2_2, + r_2_1, + r_2_0}; + assign io_s1_ready = + _tables_0_io_req_ready & _tables_1_io_req_ready & _tables_2_io_req_ready + & _tables_3_io_req_ready & _bt_io_req_ready; + assign io_perf_0_value = {4'h0, io_perf_0_value_REG_1}; + assign io_perf_1_value = {4'h0, io_perf_1_value_REG_1}; + assign io_perf_2_value = {4'h0, io_perf_2_value_REG_1}; +endmodule + diff --git a/rtl/BPUTop/WrBypass.sv b/rtl/BPUTop/WrBypass.sv new file mode 100644 index 0000000..5c3db2c --- /dev/null +++ b/rtl/BPUTop/WrBypass.sv @@ -0,0 +1,281 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module WrBypass( + input clock, + input reset, + input io_wen, + input [8:0] io_write_idx, + input [2:0] io_write_data_0, + output io_hit, + output io_hit_data_0_valid, + output [2:0] io_hit_data_0_bits +); + + wire _idx_tag_cam_io_r_resp_0_0; + wire _idx_tag_cam_io_r_resp_0_1; + wire _idx_tag_cam_io_r_resp_0_2; + wire _idx_tag_cam_io_r_resp_0_3; + wire _idx_tag_cam_io_r_resp_0_4; + wire _idx_tag_cam_io_r_resp_0_5; + wire _idx_tag_cam_io_r_resp_0_6; + wire _idx_tag_cam_io_r_resp_0_7; + reg valids_0_0; + reg valids_1_0; + reg valids_2_0; + reg valids_3_0; + reg valids_4_0; + reg valids_5_0; + reg valids_6_0; + reg valids_7_0; + reg ever_written_0; + reg ever_written_1; + reg ever_written_2; + reg ever_written_3; + reg ever_written_4; + reg ever_written_5; + reg ever_written_6; + reg ever_written_7; + wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; + wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; + wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; + wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; + wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; + wire [2:0] _hit_idx_T_2 = + {hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1}; + wire [2:0] hit_idx = + {|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4}, + |(_hit_idx_T_2[2:1]), + _hit_idx_T_2[2] | _hit_idx_T_2[0]}; + wire hit = + hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6 + | hits_oh_7; + reg [6:0] state_reg; + wire [2:0] enq_idx = + {state_reg[6], + state_reg[6] + ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]} + : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}; + wire [2:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx; + wire _GEN = enq_idx == 3'h0; + wire _GEN_0 = enq_idx == 3'h1; + wire _GEN_1 = enq_idx == 3'h2; + wire _GEN_2 = enq_idx == 3'h3; + wire _GEN_3 = enq_idx == 3'h4; + wire _GEN_4 = enq_idx == 3'h5; + wire _GEN_5 = enq_idx == 3'h6; + always @(posedge clock or posedge reset) begin + if (reset) begin + valids_0_0 <= 1'h0; + valids_1_0 <= 1'h0; + valids_2_0 <= 1'h0; + valids_3_0 <= 1'h0; + valids_4_0 <= 1'h0; + valids_5_0 <= 1'h0; + valids_6_0 <= 1'h0; + valids_7_0 <= 1'h0; + ever_written_0 <= 1'h0; + ever_written_1 <= 1'h0; + ever_written_2 <= 1'h0; + ever_written_3 <= 1'h0; + ever_written_4 <= 1'h0; + ever_written_5 <= 1'h0; + ever_written_6 <= 1'h0; + ever_written_7 <= 1'h0; + state_reg <= 7'h0; + end + else begin + if (io_wen) begin + if (hit) begin + valids_0_0 <= hit_idx == 3'h0 | valids_0_0; + valids_1_0 <= hit_idx == 3'h1 | valids_1_0; + valids_2_0 <= hit_idx == 3'h2 | valids_2_0; + valids_3_0 <= hit_idx == 3'h3 | valids_3_0; + valids_4_0 <= hit_idx == 3'h4 | valids_4_0; + valids_5_0 <= hit_idx == 3'h5 | valids_5_0; + valids_6_0 <= hit_idx == 3'h6 | valids_6_0; + valids_7_0 <= (&hit_idx) | valids_7_0; + end + else begin + valids_0_0 <= _GEN | ~_GEN & valids_0_0; + valids_1_0 <= _GEN_0 | ~_GEN_0 & valids_1_0; + valids_2_0 <= _GEN_1 | ~_GEN_1 & valids_2_0; + valids_3_0 <= _GEN_2 | ~_GEN_2 & valids_3_0; + valids_4_0 <= _GEN_3 | ~_GEN_3 & valids_4_0; + valids_5_0 <= _GEN_4 | ~_GEN_4 & valids_5_0; + valids_6_0 <= _GEN_5 | ~_GEN_5 & valids_6_0; + valids_7_0 <= (&enq_idx) | ~(&enq_idx) & valids_7_0; + end + state_reg <= + {~(state_reg_touch_way_sized[2]), + state_reg_touch_way_sized[2] + ? {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[4], + state_reg_touch_way_sized[1] + ? state_reg[3] + : ~(state_reg_touch_way_sized[0])} + : state_reg[5:3], + state_reg_touch_way_sized[2] + ? state_reg[2:0] + : {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[1], + state_reg_touch_way_sized[1] + ? state_reg[0] + : ~(state_reg_touch_way_sized[0])}}; + end + ever_written_0 <= io_wen & ~hit & _GEN | ever_written_0; + ever_written_1 <= io_wen & ~hit & _GEN_0 | ever_written_1; + ever_written_2 <= io_wen & ~hit & _GEN_1 | ever_written_2; + ever_written_3 <= io_wen & ~hit & _GEN_2 | ever_written_3; + ever_written_4 <= io_wen & ~hit & _GEN_3 | ever_written_4; + ever_written_5 <= io_wen & ~hit & _GEN_4 | ever_written_5; + ever_written_6 <= io_wen & ~hit & _GEN_5 | ever_written_6; + ever_written_7 <= io_wen & ~hit & (&enq_idx) | ever_written_7; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0]; + valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][1]; + valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][2]; + valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][3]; + valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][4]; + valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][5]; + valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][6]; + valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][7]; + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][8]; + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][9]; + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][10]; + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][11]; + ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][12]; + ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][13]; + ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][14]; + ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][15]; + state_reg = _RANDOM[/*Zero width*/ 1'b0][22:16]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + valids_0_0 = 1'h0; + valids_1_0 = 1'h0; + valids_2_0 = 1'h0; + valids_3_0 = 1'h0; + valids_4_0 = 1'h0; + valids_5_0 = 1'h0; + valids_6_0 = 1'h0; + valids_7_0 = 1'h0; + ever_written_0 = 1'h0; + ever_written_1 = 1'h0; + ever_written_2 = 1'h0; + ever_written_3 = 1'h0; + ever_written_4 = 1'h0; + ever_written_5 = 1'h0; + ever_written_6 = 1'h0; + ever_written_7 = 1'h0; + state_reg = 7'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + CAMTemplate idx_tag_cam ( + .clock (clock), + .io_r_req_0_idx (io_write_idx), + .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), + .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), + .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), + .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), + .io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4), + .io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5), + .io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6), + .io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7), + .io_w_valid (io_wen & ~hit), + .io_w_bits_data_idx (io_write_idx), + .io_w_bits_index (enq_idx) + ); + data_mem_0_8x3 data_mem_0_ext ( + .R0_addr (hit_idx), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (io_hit_data_0_bits), + .W0_addr (hit ? hit_idx : enq_idx), + .W0_en (io_wen), + .W0_clk (clock), + .W0_data (io_write_data_0) + ); + assign io_hit = hit; + assign io_hit_data_0_valid = + hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3 + & valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6 + & valids_6_0 | hits_oh_7 & valids_7_0; +endmodule + diff --git a/rtl/BPUTop/WrBypass_32.sv b/rtl/BPUTop/WrBypass_32.sv new file mode 100644 index 0000000..d802d39 --- /dev/null +++ b/rtl/BPUTop/WrBypass_32.sv @@ -0,0 +1,355 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module WrBypass_32( + input clock, + input reset, + input io_wen, + input [10:0] io_write_idx, + input [1:0] io_write_data_0, + input [1:0] io_write_data_1, + input io_write_way_mask_0, + input io_write_way_mask_1, + output io_hit, + output io_hit_data_0_valid, + output [1:0] io_hit_data_0_bits, + output io_hit_data_1_valid, + output [1:0] io_hit_data_1_bits +); + + wire [3:0] _data_mem_ext_R0_data; + wire [3:0] _data_mem_ext_R1_data; + wire _idx_tag_cam_io_r_resp_0_0; + wire _idx_tag_cam_io_r_resp_0_1; + wire _idx_tag_cam_io_r_resp_0_2; + wire _idx_tag_cam_io_r_resp_0_3; + wire _idx_tag_cam_io_r_resp_0_4; + wire _idx_tag_cam_io_r_resp_0_5; + wire _idx_tag_cam_io_r_resp_0_6; + wire _idx_tag_cam_io_r_resp_0_7; + reg valids_0_0; + reg valids_0_1; + reg valids_1_0; + reg valids_1_1; + reg valids_2_0; + reg valids_2_1; + reg valids_3_0; + reg valids_3_1; + reg valids_4_0; + reg valids_4_1; + reg valids_5_0; + reg valids_5_1; + reg valids_6_0; + reg valids_6_1; + reg valids_7_0; + reg valids_7_1; + reg ever_written_0; + reg ever_written_1; + reg ever_written_2; + reg ever_written_3; + reg ever_written_4; + reg ever_written_5; + reg ever_written_6; + reg ever_written_7; + wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; + wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; + wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; + wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; + wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; + wire [2:0] _hit_idx_T_2 = + {hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1}; + wire [2:0] hit_idx = + {|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4}, + |(_hit_idx_T_2[2:1]), + _hit_idx_T_2[2] | _hit_idx_T_2[0]}; + wire hit = + hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6 + | hits_oh_7; + reg [6:0] state_reg; + wire [2:0] enq_idx = + {state_reg[6], + state_reg[6] + ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]} + : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}; + wire _GEN = hit_idx == 3'h0; + wire _GEN_0 = hit_idx == 3'h1; + wire _GEN_1 = hit_idx == 3'h2; + wire _GEN_2 = hit_idx == 3'h3; + wire _GEN_3 = hit_idx == 3'h4; + wire _GEN_4 = hit_idx == 3'h5; + wire _GEN_5 = hit_idx == 3'h6; + wire [2:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx; + wire _GEN_6 = enq_idx == 3'h0; + wire _GEN_7 = enq_idx == 3'h1; + wire _GEN_8 = enq_idx == 3'h2; + wire _GEN_9 = enq_idx == 3'h3; + wire _GEN_10 = enq_idx == 3'h4; + wire _GEN_11 = enq_idx == 3'h5; + wire _GEN_12 = enq_idx == 3'h6; + always @(posedge clock or posedge reset) begin + if (reset) begin + valids_0_0 <= 1'h0; + valids_0_1 <= 1'h0; + valids_1_0 <= 1'h0; + valids_1_1 <= 1'h0; + valids_2_0 <= 1'h0; + valids_2_1 <= 1'h0; + valids_3_0 <= 1'h0; + valids_3_1 <= 1'h0; + valids_4_0 <= 1'h0; + valids_4_1 <= 1'h0; + valids_5_0 <= 1'h0; + valids_5_1 <= 1'h0; + valids_6_0 <= 1'h0; + valids_6_1 <= 1'h0; + valids_7_0 <= 1'h0; + valids_7_1 <= 1'h0; + ever_written_0 <= 1'h0; + ever_written_1 <= 1'h0; + ever_written_2 <= 1'h0; + ever_written_3 <= 1'h0; + ever_written_4 <= 1'h0; + ever_written_5 <= 1'h0; + ever_written_6 <= 1'h0; + ever_written_7 <= 1'h0; + state_reg <= 7'h0; + end + else begin + if (io_wen) begin + if (hit) begin + valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0; + valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1; + valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0; + valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1; + valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0; + valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1; + valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0; + valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1; + valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0; + valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1; + valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0; + valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1; + valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0; + valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1; + valids_7_0 <= io_write_way_mask_0 & (&hit_idx) | valids_7_0; + valids_7_1 <= io_write_way_mask_1 & (&hit_idx) | valids_7_1; + end + else begin + valids_0_0 <= io_write_way_mask_0 & _GEN_6 | ~_GEN_6 & valids_0_0; + valids_0_1 <= io_write_way_mask_1 & _GEN_6 | ~_GEN_6 & valids_0_1; + valids_1_0 <= io_write_way_mask_0 & _GEN_7 | ~_GEN_7 & valids_1_0; + valids_1_1 <= io_write_way_mask_1 & _GEN_7 | ~_GEN_7 & valids_1_1; + valids_2_0 <= io_write_way_mask_0 & _GEN_8 | ~_GEN_8 & valids_2_0; + valids_2_1 <= io_write_way_mask_1 & _GEN_8 | ~_GEN_8 & valids_2_1; + valids_3_0 <= io_write_way_mask_0 & _GEN_9 | ~_GEN_9 & valids_3_0; + valids_3_1 <= io_write_way_mask_1 & _GEN_9 | ~_GEN_9 & valids_3_1; + valids_4_0 <= io_write_way_mask_0 & _GEN_10 | ~_GEN_10 & valids_4_0; + valids_4_1 <= io_write_way_mask_1 & _GEN_10 | ~_GEN_10 & valids_4_1; + valids_5_0 <= io_write_way_mask_0 & _GEN_11 | ~_GEN_11 & valids_5_0; + valids_5_1 <= io_write_way_mask_1 & _GEN_11 | ~_GEN_11 & valids_5_1; + valids_6_0 <= io_write_way_mask_0 & _GEN_12 | ~_GEN_12 & valids_6_0; + valids_6_1 <= io_write_way_mask_1 & _GEN_12 | ~_GEN_12 & valids_6_1; + valids_7_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_7_0; + valids_7_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_7_1; + end + state_reg <= + {~(state_reg_touch_way_sized[2]), + state_reg_touch_way_sized[2] + ? {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[4], + state_reg_touch_way_sized[1] + ? state_reg[3] + : ~(state_reg_touch_way_sized[0])} + : state_reg[5:3], + state_reg_touch_way_sized[2] + ? state_reg[2:0] + : {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[1], + state_reg_touch_way_sized[1] + ? state_reg[0] + : ~(state_reg_touch_way_sized[0])}}; + end + ever_written_0 <= io_wen & ~hit & (_GEN_6 | io_wen & _GEN_6) | ever_written_0; + ever_written_1 <= io_wen & ~hit & (_GEN_7 | io_wen & _GEN_7) | ever_written_1; + ever_written_2 <= io_wen & ~hit & (_GEN_8 | io_wen & _GEN_8) | ever_written_2; + ever_written_3 <= io_wen & ~hit & (_GEN_9 | io_wen & _GEN_9) | ever_written_3; + ever_written_4 <= io_wen & ~hit & (_GEN_10 | io_wen & _GEN_10) | ever_written_4; + ever_written_5 <= io_wen & ~hit & (_GEN_11 | io_wen & _GEN_11) | ever_written_5; + ever_written_6 <= io_wen & ~hit & (_GEN_12 | io_wen & _GEN_12) | ever_written_6; + ever_written_7 <= + io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_7; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0]; + valids_0_1 = _RANDOM[/*Zero width*/ 1'b0][1]; + valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][2]; + valids_1_1 = _RANDOM[/*Zero width*/ 1'b0][3]; + valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][4]; + valids_2_1 = _RANDOM[/*Zero width*/ 1'b0][5]; + valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][6]; + valids_3_1 = _RANDOM[/*Zero width*/ 1'b0][7]; + valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][8]; + valids_4_1 = _RANDOM[/*Zero width*/ 1'b0][9]; + valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][10]; + valids_5_1 = _RANDOM[/*Zero width*/ 1'b0][11]; + valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][12]; + valids_6_1 = _RANDOM[/*Zero width*/ 1'b0][13]; + valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][14]; + valids_7_1 = _RANDOM[/*Zero width*/ 1'b0][15]; + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][16]; + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][17]; + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][18]; + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][19]; + ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][20]; + ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][21]; + ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][22]; + ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][23]; + state_reg = _RANDOM[/*Zero width*/ 1'b0][30:24]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + valids_0_0 = 1'h0; + valids_0_1 = 1'h0; + valids_1_0 = 1'h0; + valids_1_1 = 1'h0; + valids_2_0 = 1'h0; + valids_2_1 = 1'h0; + valids_3_0 = 1'h0; + valids_3_1 = 1'h0; + valids_4_0 = 1'h0; + valids_4_1 = 1'h0; + valids_5_0 = 1'h0; + valids_5_1 = 1'h0; + valids_6_0 = 1'h0; + valids_6_1 = 1'h0; + valids_7_0 = 1'h0; + valids_7_1 = 1'h0; + ever_written_0 = 1'h0; + ever_written_1 = 1'h0; + ever_written_2 = 1'h0; + ever_written_3 = 1'h0; + ever_written_4 = 1'h0; + ever_written_5 = 1'h0; + ever_written_6 = 1'h0; + ever_written_7 = 1'h0; + state_reg = 7'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + CAMTemplate_32 idx_tag_cam ( + .clock (clock), + .io_r_req_0_idx (io_write_idx), + .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), + .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), + .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), + .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), + .io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4), + .io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5), + .io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6), + .io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7), + .io_w_valid (io_wen & ~hit), + .io_w_bits_data_idx (io_write_idx), + .io_w_bits_index (enq_idx) + ); + data_mem_8x4 data_mem_ext ( + .R0_addr (hit_idx), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_data_mem_ext_R0_data), + .R1_addr (hit_idx), + .R1_en (1'h1), + .R1_clk (clock), + .R1_data (_data_mem_ext_R1_data), + .W0_addr (hit ? hit_idx : enq_idx), + .W0_en (io_wen), + .W0_clk (clock), + .W0_data ({io_write_data_1, io_write_data_0}), + .W0_mask ({io_write_way_mask_1, io_write_way_mask_0}) + ); + assign io_hit = hit; + assign io_hit_data_0_valid = + hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3 + & valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6 + & valids_6_0 | hits_oh_7 & valids_7_0; + assign io_hit_data_0_bits = _data_mem_ext_R1_data[1:0]; + assign io_hit_data_1_valid = + hits_oh_0 & valids_0_1 | hits_oh_1 & valids_1_1 | hits_oh_2 & valids_2_1 | hits_oh_3 + & valids_3_1 | hits_oh_4 & valids_4_1 | hits_oh_5 & valids_5_1 | hits_oh_6 + & valids_6_1 | hits_oh_7 & valids_7_1; + assign io_hit_data_1_bits = _data_mem_ext_R0_data[3:2]; +endmodule + diff --git a/rtl/BPUTop/WrBypass_33.sv b/rtl/BPUTop/WrBypass_33.sv new file mode 100644 index 0000000..21993bf --- /dev/null +++ b/rtl/BPUTop/WrBypass_33.sv @@ -0,0 +1,580 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module WrBypass_33( + input clock, + input reset, + input io_wen, + input [7:0] io_write_idx, + input [5:0] io_write_data_0, + input [5:0] io_write_data_1, + input io_write_way_mask_0, + input io_write_way_mask_1, + output io_hit, + output io_hit_data_0_valid, + output [5:0] io_hit_data_0_bits, + output io_hit_data_1_valid, + output [5:0] io_hit_data_1_bits +); + + wire [11:0] _data_mem_ext_R0_data; + wire [11:0] _data_mem_ext_R1_data; + wire _idx_tag_cam_io_r_resp_0_0; + wire _idx_tag_cam_io_r_resp_0_1; + wire _idx_tag_cam_io_r_resp_0_2; + wire _idx_tag_cam_io_r_resp_0_3; + wire _idx_tag_cam_io_r_resp_0_4; + wire _idx_tag_cam_io_r_resp_0_5; + wire _idx_tag_cam_io_r_resp_0_6; + wire _idx_tag_cam_io_r_resp_0_7; + wire _idx_tag_cam_io_r_resp_0_8; + wire _idx_tag_cam_io_r_resp_0_9; + wire _idx_tag_cam_io_r_resp_0_10; + wire _idx_tag_cam_io_r_resp_0_11; + wire _idx_tag_cam_io_r_resp_0_12; + wire _idx_tag_cam_io_r_resp_0_13; + wire _idx_tag_cam_io_r_resp_0_14; + wire _idx_tag_cam_io_r_resp_0_15; + reg valids_0_0; + reg valids_0_1; + reg valids_1_0; + reg valids_1_1; + reg valids_2_0; + reg valids_2_1; + reg valids_3_0; + reg valids_3_1; + reg valids_4_0; + reg valids_4_1; + reg valids_5_0; + reg valids_5_1; + reg valids_6_0; + reg valids_6_1; + reg valids_7_0; + reg valids_7_1; + reg valids_8_0; + reg valids_8_1; + reg valids_9_0; + reg valids_9_1; + reg valids_10_0; + reg valids_10_1; + reg valids_11_0; + reg valids_11_1; + reg valids_12_0; + reg valids_12_1; + reg valids_13_0; + reg valids_13_1; + reg valids_14_0; + reg valids_14_1; + reg valids_15_0; + reg valids_15_1; + reg ever_written_0; + reg ever_written_1; + reg ever_written_2; + reg ever_written_3; + reg ever_written_4; + reg ever_written_5; + reg ever_written_6; + reg ever_written_7; + reg ever_written_8; + reg ever_written_9; + reg ever_written_10; + reg ever_written_11; + reg ever_written_12; + reg ever_written_13; + reg ever_written_14; + reg ever_written_15; + wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; + wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; + wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; + wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; + wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; + wire hits_oh_8 = _idx_tag_cam_io_r_resp_0_8 & ever_written_8; + wire hits_oh_9 = _idx_tag_cam_io_r_resp_0_9 & ever_written_9; + wire hits_oh_10 = _idx_tag_cam_io_r_resp_0_10 & ever_written_10; + wire hits_oh_11 = _idx_tag_cam_io_r_resp_0_11 & ever_written_11; + wire hits_oh_12 = _idx_tag_cam_io_r_resp_0_12 & ever_written_12; + wire hits_oh_13 = _idx_tag_cam_io_r_resp_0_13 & ever_written_13; + wire hits_oh_14 = _idx_tag_cam_io_r_resp_0_14 & ever_written_14; + wire hits_oh_15 = _idx_tag_cam_io_r_resp_0_15 & ever_written_15; + wire [6:0] _hit_idx_T_2 = + {hits_oh_15, hits_oh_14, hits_oh_13, hits_oh_12, hits_oh_11, hits_oh_10, hits_oh_9} + | {hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4, hits_oh_3, hits_oh_2, hits_oh_1}; + wire [2:0] _hit_idx_T_4 = _hit_idx_T_2[6:4] | _hit_idx_T_2[2:0]; + wire [3:0] hit_idx = + {|{hits_oh_15, + hits_oh_14, + hits_oh_13, + hits_oh_12, + hits_oh_11, + hits_oh_10, + hits_oh_9, + hits_oh_8}, + |(_hit_idx_T_2[6:3]), + |(_hit_idx_T_4[2:1]), + _hit_idx_T_4[2] | _hit_idx_T_4[0]}; + wire hit = + hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6 + | hits_oh_7 | hits_oh_8 | hits_oh_9 | hits_oh_10 | hits_oh_11 | hits_oh_12 + | hits_oh_13 | hits_oh_14 | hits_oh_15; + reg [14:0] state_reg; + wire [3:0] enq_idx = + {state_reg[14], + state_reg[14] + ? {state_reg[13], + state_reg[13] + ? {state_reg[12], state_reg[12] ? state_reg[11] : state_reg[10]} + : {state_reg[9], state_reg[9] ? state_reg[8] : state_reg[7]}} + : {state_reg[6], + state_reg[6] + ? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]} + : {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}}; + wire _GEN = hit_idx == 4'h0; + wire _GEN_0 = hit_idx == 4'h1; + wire _GEN_1 = hit_idx == 4'h2; + wire _GEN_2 = hit_idx == 4'h3; + wire _GEN_3 = hit_idx == 4'h4; + wire _GEN_4 = hit_idx == 4'h5; + wire _GEN_5 = hit_idx == 4'h6; + wire _GEN_6 = hit_idx == 4'h7; + wire _GEN_7 = hit_idx == 4'h8; + wire _GEN_8 = hit_idx == 4'h9; + wire _GEN_9 = hit_idx == 4'hA; + wire _GEN_10 = hit_idx == 4'hB; + wire _GEN_11 = hit_idx == 4'hC; + wire _GEN_12 = hit_idx == 4'hD; + wire _GEN_13 = hit_idx == 4'hE; + wire [3:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx; + wire _GEN_14 = enq_idx == 4'h0; + wire _GEN_15 = enq_idx == 4'h1; + wire _GEN_16 = enq_idx == 4'h2; + wire _GEN_17 = enq_idx == 4'h3; + wire _GEN_18 = enq_idx == 4'h4; + wire _GEN_19 = enq_idx == 4'h5; + wire _GEN_20 = enq_idx == 4'h6; + wire _GEN_21 = enq_idx == 4'h7; + wire _GEN_22 = enq_idx == 4'h8; + wire _GEN_23 = enq_idx == 4'h9; + wire _GEN_24 = enq_idx == 4'hA; + wire _GEN_25 = enq_idx == 4'hB; + wire _GEN_26 = enq_idx == 4'hC; + wire _GEN_27 = enq_idx == 4'hD; + wire _GEN_28 = enq_idx == 4'hE; + always @(posedge clock or posedge reset) begin + if (reset) begin + valids_0_0 <= 1'h0; + valids_0_1 <= 1'h0; + valids_1_0 <= 1'h0; + valids_1_1 <= 1'h0; + valids_2_0 <= 1'h0; + valids_2_1 <= 1'h0; + valids_3_0 <= 1'h0; + valids_3_1 <= 1'h0; + valids_4_0 <= 1'h0; + valids_4_1 <= 1'h0; + valids_5_0 <= 1'h0; + valids_5_1 <= 1'h0; + valids_6_0 <= 1'h0; + valids_6_1 <= 1'h0; + valids_7_0 <= 1'h0; + valids_7_1 <= 1'h0; + valids_8_0 <= 1'h0; + valids_8_1 <= 1'h0; + valids_9_0 <= 1'h0; + valids_9_1 <= 1'h0; + valids_10_0 <= 1'h0; + valids_10_1 <= 1'h0; + valids_11_0 <= 1'h0; + valids_11_1 <= 1'h0; + valids_12_0 <= 1'h0; + valids_12_1 <= 1'h0; + valids_13_0 <= 1'h0; + valids_13_1 <= 1'h0; + valids_14_0 <= 1'h0; + valids_14_1 <= 1'h0; + valids_15_0 <= 1'h0; + valids_15_1 <= 1'h0; + ever_written_0 <= 1'h0; + ever_written_1 <= 1'h0; + ever_written_2 <= 1'h0; + ever_written_3 <= 1'h0; + ever_written_4 <= 1'h0; + ever_written_5 <= 1'h0; + ever_written_6 <= 1'h0; + ever_written_7 <= 1'h0; + ever_written_8 <= 1'h0; + ever_written_9 <= 1'h0; + ever_written_10 <= 1'h0; + ever_written_11 <= 1'h0; + ever_written_12 <= 1'h0; + ever_written_13 <= 1'h0; + ever_written_14 <= 1'h0; + ever_written_15 <= 1'h0; + state_reg <= 15'h0; + end + else begin + if (io_wen) begin + if (hit) begin + valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0; + valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1; + valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0; + valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1; + valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0; + valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1; + valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0; + valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1; + valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0; + valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1; + valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0; + valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1; + valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0; + valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1; + valids_7_0 <= io_write_way_mask_0 & _GEN_6 | valids_7_0; + valids_7_1 <= io_write_way_mask_1 & _GEN_6 | valids_7_1; + valids_8_0 <= io_write_way_mask_0 & _GEN_7 | valids_8_0; + valids_8_1 <= io_write_way_mask_1 & _GEN_7 | valids_8_1; + valids_9_0 <= io_write_way_mask_0 & _GEN_8 | valids_9_0; + valids_9_1 <= io_write_way_mask_1 & _GEN_8 | valids_9_1; + valids_10_0 <= io_write_way_mask_0 & _GEN_9 | valids_10_0; + valids_10_1 <= io_write_way_mask_1 & _GEN_9 | valids_10_1; + valids_11_0 <= io_write_way_mask_0 & _GEN_10 | valids_11_0; + valids_11_1 <= io_write_way_mask_1 & _GEN_10 | valids_11_1; + valids_12_0 <= io_write_way_mask_0 & _GEN_11 | valids_12_0; + valids_12_1 <= io_write_way_mask_1 & _GEN_11 | valids_12_1; + valids_13_0 <= io_write_way_mask_0 & _GEN_12 | valids_13_0; + valids_13_1 <= io_write_way_mask_1 & _GEN_12 | valids_13_1; + valids_14_0 <= io_write_way_mask_0 & _GEN_13 | valids_14_0; + valids_14_1 <= io_write_way_mask_1 & _GEN_13 | valids_14_1; + valids_15_0 <= io_write_way_mask_0 & (&hit_idx) | valids_15_0; + valids_15_1 <= io_write_way_mask_1 & (&hit_idx) | valids_15_1; + end + else begin + valids_0_0 <= io_write_way_mask_0 & _GEN_14 | ~_GEN_14 & valids_0_0; + valids_0_1 <= io_write_way_mask_1 & _GEN_14 | ~_GEN_14 & valids_0_1; + valids_1_0 <= io_write_way_mask_0 & _GEN_15 | ~_GEN_15 & valids_1_0; + valids_1_1 <= io_write_way_mask_1 & _GEN_15 | ~_GEN_15 & valids_1_1; + valids_2_0 <= io_write_way_mask_0 & _GEN_16 | ~_GEN_16 & valids_2_0; + valids_2_1 <= io_write_way_mask_1 & _GEN_16 | ~_GEN_16 & valids_2_1; + valids_3_0 <= io_write_way_mask_0 & _GEN_17 | ~_GEN_17 & valids_3_0; + valids_3_1 <= io_write_way_mask_1 & _GEN_17 | ~_GEN_17 & valids_3_1; + valids_4_0 <= io_write_way_mask_0 & _GEN_18 | ~_GEN_18 & valids_4_0; + valids_4_1 <= io_write_way_mask_1 & _GEN_18 | ~_GEN_18 & valids_4_1; + valids_5_0 <= io_write_way_mask_0 & _GEN_19 | ~_GEN_19 & valids_5_0; + valids_5_1 <= io_write_way_mask_1 & _GEN_19 | ~_GEN_19 & valids_5_1; + valids_6_0 <= io_write_way_mask_0 & _GEN_20 | ~_GEN_20 & valids_6_0; + valids_6_1 <= io_write_way_mask_1 & _GEN_20 | ~_GEN_20 & valids_6_1; + valids_7_0 <= io_write_way_mask_0 & _GEN_21 | ~_GEN_21 & valids_7_0; + valids_7_1 <= io_write_way_mask_1 & _GEN_21 | ~_GEN_21 & valids_7_1; + valids_8_0 <= io_write_way_mask_0 & _GEN_22 | ~_GEN_22 & valids_8_0; + valids_8_1 <= io_write_way_mask_1 & _GEN_22 | ~_GEN_22 & valids_8_1; + valids_9_0 <= io_write_way_mask_0 & _GEN_23 | ~_GEN_23 & valids_9_0; + valids_9_1 <= io_write_way_mask_1 & _GEN_23 | ~_GEN_23 & valids_9_1; + valids_10_0 <= io_write_way_mask_0 & _GEN_24 | ~_GEN_24 & valids_10_0; + valids_10_1 <= io_write_way_mask_1 & _GEN_24 | ~_GEN_24 & valids_10_1; + valids_11_0 <= io_write_way_mask_0 & _GEN_25 | ~_GEN_25 & valids_11_0; + valids_11_1 <= io_write_way_mask_1 & _GEN_25 | ~_GEN_25 & valids_11_1; + valids_12_0 <= io_write_way_mask_0 & _GEN_26 | ~_GEN_26 & valids_12_0; + valids_12_1 <= io_write_way_mask_1 & _GEN_26 | ~_GEN_26 & valids_12_1; + valids_13_0 <= io_write_way_mask_0 & _GEN_27 | ~_GEN_27 & valids_13_0; + valids_13_1 <= io_write_way_mask_1 & _GEN_27 | ~_GEN_27 & valids_13_1; + valids_14_0 <= io_write_way_mask_0 & _GEN_28 | ~_GEN_28 & valids_14_0; + valids_14_1 <= io_write_way_mask_1 & _GEN_28 | ~_GEN_28 & valids_14_1; + valids_15_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_15_0; + valids_15_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_15_1; + end + state_reg <= + {~(state_reg_touch_way_sized[3]), + state_reg_touch_way_sized[3] + ? {~(state_reg_touch_way_sized[2]), + state_reg_touch_way_sized[2] + ? {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[11], + state_reg_touch_way_sized[1] + ? state_reg[10] + : ~(state_reg_touch_way_sized[0])} + : state_reg[12:10], + state_reg_touch_way_sized[2] + ? state_reg[9:7] + : {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[8], + state_reg_touch_way_sized[1] + ? state_reg[7] + : ~(state_reg_touch_way_sized[0])}} + : state_reg[13:7], + state_reg_touch_way_sized[3] + ? state_reg[6:0] + : {~(state_reg_touch_way_sized[2]), + state_reg_touch_way_sized[2] + ? {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[4], + state_reg_touch_way_sized[1] + ? state_reg[3] + : ~(state_reg_touch_way_sized[0])} + : state_reg[5:3], + state_reg_touch_way_sized[2] + ? state_reg[2:0] + : {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] + ? ~(state_reg_touch_way_sized[0]) + : state_reg[1], + state_reg_touch_way_sized[1] + ? state_reg[0] + : ~(state_reg_touch_way_sized[0])}}}; + end + ever_written_0 <= io_wen & ~hit & (_GEN_14 | io_wen & _GEN_14) | ever_written_0; + ever_written_1 <= io_wen & ~hit & (_GEN_15 | io_wen & _GEN_15) | ever_written_1; + ever_written_2 <= io_wen & ~hit & (_GEN_16 | io_wen & _GEN_16) | ever_written_2; + ever_written_3 <= io_wen & ~hit & (_GEN_17 | io_wen & _GEN_17) | ever_written_3; + ever_written_4 <= io_wen & ~hit & (_GEN_18 | io_wen & _GEN_18) | ever_written_4; + ever_written_5 <= io_wen & ~hit & (_GEN_19 | io_wen & _GEN_19) | ever_written_5; + ever_written_6 <= io_wen & ~hit & (_GEN_20 | io_wen & _GEN_20) | ever_written_6; + ever_written_7 <= io_wen & ~hit & (_GEN_21 | io_wen & _GEN_21) | ever_written_7; + ever_written_8 <= io_wen & ~hit & (_GEN_22 | io_wen & _GEN_22) | ever_written_8; + ever_written_9 <= io_wen & ~hit & (_GEN_23 | io_wen & _GEN_23) | ever_written_9; + ever_written_10 <= io_wen & ~hit & (_GEN_24 | io_wen & _GEN_24) | ever_written_10; + ever_written_11 <= io_wen & ~hit & (_GEN_25 | io_wen & _GEN_25) | ever_written_11; + ever_written_12 <= io_wen & ~hit & (_GEN_26 | io_wen & _GEN_26) | ever_written_12; + ever_written_13 <= io_wen & ~hit & (_GEN_27 | io_wen & _GEN_27) | ever_written_13; + ever_written_14 <= io_wen & ~hit & (_GEN_28 | io_wen & _GEN_28) | ever_written_14; + ever_written_15 <= + io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_15; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; + end + valids_0_0 = _RANDOM[1'h0][0]; + valids_0_1 = _RANDOM[1'h0][1]; + valids_1_0 = _RANDOM[1'h0][2]; + valids_1_1 = _RANDOM[1'h0][3]; + valids_2_0 = _RANDOM[1'h0][4]; + valids_2_1 = _RANDOM[1'h0][5]; + valids_3_0 = _RANDOM[1'h0][6]; + valids_3_1 = _RANDOM[1'h0][7]; + valids_4_0 = _RANDOM[1'h0][8]; + valids_4_1 = _RANDOM[1'h0][9]; + valids_5_0 = _RANDOM[1'h0][10]; + valids_5_1 = _RANDOM[1'h0][11]; + valids_6_0 = _RANDOM[1'h0][12]; + valids_6_1 = _RANDOM[1'h0][13]; + valids_7_0 = _RANDOM[1'h0][14]; + valids_7_1 = _RANDOM[1'h0][15]; + valids_8_0 = _RANDOM[1'h0][16]; + valids_8_1 = _RANDOM[1'h0][17]; + valids_9_0 = _RANDOM[1'h0][18]; + valids_9_1 = _RANDOM[1'h0][19]; + valids_10_0 = _RANDOM[1'h0][20]; + valids_10_1 = _RANDOM[1'h0][21]; + valids_11_0 = _RANDOM[1'h0][22]; + valids_11_1 = _RANDOM[1'h0][23]; + valids_12_0 = _RANDOM[1'h0][24]; + valids_12_1 = _RANDOM[1'h0][25]; + valids_13_0 = _RANDOM[1'h0][26]; + valids_13_1 = _RANDOM[1'h0][27]; + valids_14_0 = _RANDOM[1'h0][28]; + valids_14_1 = _RANDOM[1'h0][29]; + valids_15_0 = _RANDOM[1'h0][30]; + valids_15_1 = _RANDOM[1'h0][31]; + ever_written_0 = _RANDOM[1'h1][0]; + ever_written_1 = _RANDOM[1'h1][1]; + ever_written_2 = _RANDOM[1'h1][2]; + ever_written_3 = _RANDOM[1'h1][3]; + ever_written_4 = _RANDOM[1'h1][4]; + ever_written_5 = _RANDOM[1'h1][5]; + ever_written_6 = _RANDOM[1'h1][6]; + ever_written_7 = _RANDOM[1'h1][7]; + ever_written_8 = _RANDOM[1'h1][8]; + ever_written_9 = _RANDOM[1'h1][9]; + ever_written_10 = _RANDOM[1'h1][10]; + ever_written_11 = _RANDOM[1'h1][11]; + ever_written_12 = _RANDOM[1'h1][12]; + ever_written_13 = _RANDOM[1'h1][13]; + ever_written_14 = _RANDOM[1'h1][14]; + ever_written_15 = _RANDOM[1'h1][15]; + state_reg = _RANDOM[1'h1][30:16]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + valids_0_0 = 1'h0; + valids_0_1 = 1'h0; + valids_1_0 = 1'h0; + valids_1_1 = 1'h0; + valids_2_0 = 1'h0; + valids_2_1 = 1'h0; + valids_3_0 = 1'h0; + valids_3_1 = 1'h0; + valids_4_0 = 1'h0; + valids_4_1 = 1'h0; + valids_5_0 = 1'h0; + valids_5_1 = 1'h0; + valids_6_0 = 1'h0; + valids_6_1 = 1'h0; + valids_7_0 = 1'h0; + valids_7_1 = 1'h0; + valids_8_0 = 1'h0; + valids_8_1 = 1'h0; + valids_9_0 = 1'h0; + valids_9_1 = 1'h0; + valids_10_0 = 1'h0; + valids_10_1 = 1'h0; + valids_11_0 = 1'h0; + valids_11_1 = 1'h0; + valids_12_0 = 1'h0; + valids_12_1 = 1'h0; + valids_13_0 = 1'h0; + valids_13_1 = 1'h0; + valids_14_0 = 1'h0; + valids_14_1 = 1'h0; + valids_15_0 = 1'h0; + valids_15_1 = 1'h0; + ever_written_0 = 1'h0; + ever_written_1 = 1'h0; + ever_written_2 = 1'h0; + ever_written_3 = 1'h0; + ever_written_4 = 1'h0; + ever_written_5 = 1'h0; + ever_written_6 = 1'h0; + ever_written_7 = 1'h0; + ever_written_8 = 1'h0; + ever_written_9 = 1'h0; + ever_written_10 = 1'h0; + ever_written_11 = 1'h0; + ever_written_12 = 1'h0; + ever_written_13 = 1'h0; + ever_written_14 = 1'h0; + ever_written_15 = 1'h0; + state_reg = 15'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + CAMTemplate_33 idx_tag_cam ( + .clock (clock), + .io_r_req_0_idx (io_write_idx), + .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), + .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), + .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), + .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), + .io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4), + .io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5), + .io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6), + .io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7), + .io_r_resp_0_8 (_idx_tag_cam_io_r_resp_0_8), + .io_r_resp_0_9 (_idx_tag_cam_io_r_resp_0_9), + .io_r_resp_0_10 (_idx_tag_cam_io_r_resp_0_10), + .io_r_resp_0_11 (_idx_tag_cam_io_r_resp_0_11), + .io_r_resp_0_12 (_idx_tag_cam_io_r_resp_0_12), + .io_r_resp_0_13 (_idx_tag_cam_io_r_resp_0_13), + .io_r_resp_0_14 (_idx_tag_cam_io_r_resp_0_14), + .io_r_resp_0_15 (_idx_tag_cam_io_r_resp_0_15), + .io_w_valid (io_wen & ~hit), + .io_w_bits_data_idx (io_write_idx), + .io_w_bits_index (enq_idx) + ); + data_mem_16x12 data_mem_ext ( + .R0_addr (hit_idx), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_data_mem_ext_R0_data), + .R1_addr (hit_idx), + .R1_en (1'h1), + .R1_clk (clock), + .R1_data (_data_mem_ext_R1_data), + .W0_addr (hit ? hit_idx : enq_idx), + .W0_en (io_wen), + .W0_clk (clock), + .W0_data ({io_write_data_1, io_write_data_0}), + .W0_mask ({io_write_way_mask_1, io_write_way_mask_0}) + ); + assign io_hit = hit; + assign io_hit_data_0_valid = + hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3 + & valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6 + & valids_6_0 | hits_oh_7 & valids_7_0 | hits_oh_8 & valids_8_0 | hits_oh_9 + & valids_9_0 | hits_oh_10 & valids_10_0 | hits_oh_11 & valids_11_0 | hits_oh_12 + & valids_12_0 | hits_oh_13 & valids_13_0 | hits_oh_14 & valids_14_0 | hits_oh_15 + & valids_15_0; + assign io_hit_data_0_bits = _data_mem_ext_R1_data[5:0]; + assign io_hit_data_1_valid = + hits_oh_0 & valids_0_1 | hits_oh_1 & valids_1_1 | hits_oh_2 & valids_2_1 | hits_oh_3 + & valids_3_1 | hits_oh_4 & valids_4_1 | hits_oh_5 & valids_5_1 | hits_oh_6 + & valids_6_1 | hits_oh_7 & valids_7_1 | hits_oh_8 & valids_8_1 | hits_oh_9 + & valids_9_1 | hits_oh_10 & valids_10_1 | hits_oh_11 & valids_11_1 | hits_oh_12 + & valids_12_1 | hits_oh_13 & valids_13_1 | hits_oh_14 & valids_14_1 | hits_oh_15 + & valids_15_1; + assign io_hit_data_1_bits = _data_mem_ext_R0_data[11:6]; +endmodule + diff --git a/rtl/BPUTop/WrBypass_41.sv b/rtl/BPUTop/WrBypass_41.sv new file mode 100644 index 0000000..33c59f3 --- /dev/null +++ b/rtl/BPUTop/WrBypass_41.sv @@ -0,0 +1,157 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module WrBypass_41( + input clock, + input reset, + input io_wen, + input [7:0] io_write_idx, + input [1:0] io_write_data_0, + output io_hit, + output [1:0] io_hit_data_0_bits +); + + wire _idx_tag_cam_io_r_resp_0_0; + wire _idx_tag_cam_io_r_resp_0_1; + wire _idx_tag_cam_io_r_resp_0_2; + wire _idx_tag_cam_io_r_resp_0_3; + reg ever_written_0; + reg ever_written_1; + reg ever_written_2; + reg ever_written_3; + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; + wire [1:0] hit_idx = {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; + wire hit = + _idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; + reg [2:0] state_reg; + wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; + wire [1:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx; + always @(posedge clock or posedge reset) begin + if (reset) begin + ever_written_0 <= 1'h0; + ever_written_1 <= 1'h0; + ever_written_2 <= 1'h0; + ever_written_3 <= 1'h0; + state_reg <= 3'h0; + end + else begin + ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; + ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; + ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; + ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; + if (io_wen) + state_reg <= + {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1], + state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; + state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + ever_written_0 = 1'h0; + ever_written_1 = 1'h0; + ever_written_2 = 1'h0; + ever_written_3 = 1'h0; + state_reg = 3'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + CAMTemplate_41 idx_tag_cam ( + .clock (clock), + .io_r_req_0_idx (io_write_idx), + .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), + .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), + .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), + .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), + .io_w_valid (io_wen & ~hit), + .io_w_bits_data_idx (io_write_idx), + .io_w_bits_index (enq_idx) + ); + data_mem_0_4x2 data_mem_0_ext ( + .R0_addr (hit_idx), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (io_hit_data_0_bits), + .W0_addr (hit ? hit_idx : enq_idx), + .W0_en (io_wen), + .W0_clk (clock), + .W0_data (io_write_data_0) + ); + assign io_hit = hit; +endmodule + diff --git a/rtl/BPUTop/WrBypass_43.sv b/rtl/BPUTop/WrBypass_43.sv new file mode 100644 index 0000000..04893f8 --- /dev/null +++ b/rtl/BPUTop/WrBypass_43.sv @@ -0,0 +1,157 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module WrBypass_43( + input clock, + input reset, + input io_wen, + input [8:0] io_write_idx, + input [1:0] io_write_data_0, + output io_hit, + output [1:0] io_hit_data_0_bits +); + + wire _idx_tag_cam_io_r_resp_0_0; + wire _idx_tag_cam_io_r_resp_0_1; + wire _idx_tag_cam_io_r_resp_0_2; + wire _idx_tag_cam_io_r_resp_0_3; + reg ever_written_0; + reg ever_written_1; + reg ever_written_2; + reg ever_written_3; + wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; + wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; + wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; + wire [1:0] hit_idx = {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; + wire hit = + _idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; + reg [2:0] state_reg; + wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; + wire [1:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx; + always @(posedge clock or posedge reset) begin + if (reset) begin + ever_written_0 <= 1'h0; + ever_written_1 <= 1'h0; + ever_written_2 <= 1'h0; + ever_written_3 <= 1'h0; + state_reg <= 3'h0; + end + else begin + ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; + ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; + ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; + ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; + if (io_wen) + state_reg <= + {~(state_reg_touch_way_sized[1]), + state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1], + state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; + ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; + ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; + ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; + state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + ever_written_0 = 1'h0; + ever_written_1 = 1'h0; + ever_written_2 = 1'h0; + ever_written_3 = 1'h0; + state_reg = 3'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + CAMTemplate_43 idx_tag_cam ( + .clock (clock), + .io_r_req_0_idx (io_write_idx), + .io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0), + .io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1), + .io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2), + .io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3), + .io_w_valid (io_wen & ~hit), + .io_w_bits_data_idx (io_write_idx), + .io_w_bits_index (enq_idx) + ); + data_mem_0_4x2 data_mem_0_ext ( + .R0_addr (hit_idx), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (io_hit_data_0_bits), + .W0_addr (hit ? hit_idx : enq_idx), + .W0_en (io_wen), + .W0_clk (clock), + .W0_data (io_write_data_0) + ); + assign io_hit = hit; +endmodule + diff --git a/rtl/BPUTop/array_0_0.sv b/rtl/BPUTop/array_0_0.sv new file mode 100644 index 0000000..1340652 --- /dev/null +++ b/rtl/BPUTop/array_0_0.sv @@ -0,0 +1,76 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module array_0_0( + input [6:0] RW0_addr, + input RW0_en, + input RW0_clk, + input RW0_wmode, + input [52:0] RW0_wdata, + output [52:0] RW0_rdata +); + + array_0_0_ext array_0_0_ext ( + .RW0_addr (RW0_addr), + .RW0_en (RW0_en), + .RW0_clk (RW0_clk), + .RW0_wmode (RW0_wmode), + .RW0_wdata (RW0_wdata), + .RW0_rdata (RW0_rdata) + ); +endmodule + diff --git a/rtl/BPUTop/array_0_0_ext.v b/rtl/BPUTop/array_0_0_ext.v new file mode 100644 index 0000000..eeb5971 --- /dev/null +++ b/rtl/BPUTop/array_0_0_ext.v @@ -0,0 +1,49 @@ + +module array_0_0_ext( + input RW0_clk, + input [6:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [52:0] RW0_wdata, + output [52:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [6:0] reg_RW0_addr; + reg [52:0] ram [127:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 128; initvar = initvar+1) + ram[initvar] = {2 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for (i=0;i<1;i=i+1) begin + ram[RW0_addr][i*53 +: 53] <= RW0_wdata[i*53 +: 53]; + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [63:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[52:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule \ No newline at end of file diff --git a/rtl/BPUTop/array_3.sv b/rtl/BPUTop/array_3.sv new file mode 100644 index 0000000..8a0675b --- /dev/null +++ b/rtl/BPUTop/array_3.sv @@ -0,0 +1,78 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module array_3( + input [8:0] RW0_addr, + input RW0_en, + input RW0_clk, + input RW0_wmode, + input [319:0] RW0_wdata, + output [319:0] RW0_rdata, + input [3:0] RW0_wmask +); + + array_3_ext array_3_ext ( + .RW0_addr (RW0_addr), + .RW0_en (RW0_en), + .RW0_clk (RW0_clk), + .RW0_wmode (RW0_wmode), + .RW0_wdata (RW0_wdata), + .RW0_rdata (RW0_rdata), + .RW0_wmask (RW0_wmask) + ); +endmodule + diff --git a/rtl/BPUTop/array_3_ext.v b/rtl/BPUTop/array_3_ext.v new file mode 100644 index 0000000..231bc8c --- /dev/null +++ b/rtl/BPUTop/array_3_ext.v @@ -0,0 +1,52 @@ + +module array_3_ext( + input RW0_clk, + input [8:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [3:0] RW0_wmask, + input [319:0] RW0_wdata, + output [319:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [8:0] reg_RW0_addr; + reg [319:0] ram [511:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 512; initvar = initvar+1) + ram[initvar] = {10 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for (i=0;i<4;i=i+1) begin + if (RW0_wmask[i]) begin + ram[RW0_addr][i*80 +: 80] <= RW0_wdata[i*80 +: 80]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [319:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[319:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule \ No newline at end of file diff --git a/rtl/BPUTop/array_4.sv b/rtl/BPUTop/array_4.sv new file mode 100644 index 0000000..401977b --- /dev/null +++ b/rtl/BPUTop/array_4.sv @@ -0,0 +1,78 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module array_4( + input [7:0] RW0_addr, + input RW0_en, + input RW0_clk, + input RW0_wmode, + input [15:0] RW0_wdata, + output [15:0] RW0_rdata, + input [15:0] RW0_wmask +); + + array_4_ext array_4_ext ( + .RW0_addr (RW0_addr), + .RW0_en (RW0_en), + .RW0_clk (RW0_clk), + .RW0_wmode (RW0_wmode), + .RW0_wdata (RW0_wdata), + .RW0_rdata (RW0_rdata), + .RW0_wmask (RW0_wmask) + ); +endmodule + diff --git a/rtl/BPUTop/array_4_ext.v b/rtl/BPUTop/array_4_ext.v new file mode 100644 index 0000000..8539e56 --- /dev/null +++ b/rtl/BPUTop/array_4_ext.v @@ -0,0 +1,48 @@ + +module array_4_ext( + input RW0_clk, + input [7:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [15:0] RW0_wmask, + input [15:0] RW0_wdata, + output [15:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [7:0] reg_RW0_addr; + reg [15:0] ram [255:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 256; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + ram[RW0_addr] <= (RW0_wmask & RW0_wdata) | (~RW0_wmask & ram[RW0_addr]); + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[15:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule \ No newline at end of file diff --git a/rtl/BPUTop/array_5.sv b/rtl/BPUTop/array_5.sv new file mode 100644 index 0000000..b6b6c75 --- /dev/null +++ b/rtl/BPUTop/array_5.sv @@ -0,0 +1,78 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module array_5( + input [8:0] RW0_addr, + input RW0_en, + input RW0_clk, + input RW0_wmode, + input [23:0] RW0_wdata, + output [23:0] RW0_rdata, + input [1:0] RW0_wmask +); + + array_5_ext array_5_ext ( + .RW0_addr (RW0_addr), + .RW0_en (RW0_en), + .RW0_clk (RW0_clk), + .RW0_wmode (RW0_wmode), + .RW0_wdata (RW0_wdata), + .RW0_rdata (RW0_rdata), + .RW0_wmask (RW0_wmask) + ); +endmodule + diff --git a/rtl/BPUTop/array_5_ext.v b/rtl/BPUTop/array_5_ext.v new file mode 100644 index 0000000..3fec18b --- /dev/null +++ b/rtl/BPUTop/array_5_ext.v @@ -0,0 +1,52 @@ + +module array_5_ext( + input RW0_clk, + input [8:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [1:0] RW0_wmask, + input [23:0] RW0_wdata, + output [23:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [8:0] reg_RW0_addr; + reg [23:0] ram [511:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 512; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for (i=0;i<2;i=i+1) begin + if (RW0_wmask[i]) begin + ram[RW0_addr][i*12 +: 12] <= RW0_wdata[i*12 +: 12]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[23:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule \ No newline at end of file diff --git a/rtl/BPUTop/array_6.sv b/rtl/BPUTop/array_6.sv new file mode 100644 index 0000000..3ccacb6 --- /dev/null +++ b/rtl/BPUTop/array_6.sv @@ -0,0 +1,82 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module array_6( + input [8:0] R0_addr, + input R0_en, + input R0_clk, + output [15:0] R0_data, + input [8:0] W0_addr, + input W0_en, + input W0_clk, + input [15:0] W0_data, + input [7:0] W0_mask +); + + array_6_ext array_6_ext ( + .R0_addr (R0_addr), + .R0_en (R0_en), + .R0_clk (R0_clk), + .R0_data (R0_data), + .W0_addr (W0_addr), + .W0_en (W0_en), + .W0_clk (W0_clk), + .W0_data (W0_data), + .W0_mask (W0_mask) + ); +endmodule + diff --git a/rtl/BPUTop/array_6_ext.v b/rtl/BPUTop/array_6_ext.v new file mode 100644 index 0000000..a321fa2 --- /dev/null +++ b/rtl/BPUTop/array_6_ext.v @@ -0,0 +1,57 @@ + +module array_6_ext( + input W0_clk, + input [8:0] W0_addr, + input W0_en, + input [15:0] W0_data, + input [7:0] W0_mask, + input R0_clk, + input [8:0] R0_addr, + input R0_en, + output [15:0] R0_data +); + + reg reg_R0_ren; + reg [8:0] reg_R0_addr; + reg [15:0] ram [511:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 512; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_R0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge R0_clk) + reg_R0_ren <= R0_en; + always @(posedge R0_clk) + if (R0_en) reg_R0_addr <= R0_addr; + always @(posedge W0_clk) + if (W0_en) begin + if (W0_mask[0]) ram[W0_addr][1:0] <= W0_data[1:0]; + if (W0_mask[1]) ram[W0_addr][3:2] <= W0_data[3:2]; + if (W0_mask[2]) ram[W0_addr][5:4] <= W0_data[5:4]; + if (W0_mask[3]) ram[W0_addr][7:6] <= W0_data[7:6]; + if (W0_mask[4]) ram[W0_addr][9:8] <= W0_data[9:8]; + if (W0_mask[5]) ram[W0_addr][11:10] <= W0_data[11:10]; + if (W0_mask[6]) ram[W0_addr][13:12] <= W0_data[13:12]; + if (W0_mask[7]) ram[W0_addr][15:14] <= W0_data[15:14]; + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] R0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + R0_random = {$random}; + reg_R0_ren = R0_random[0]; + end + `endif + always @(posedge R0_clk) R0_random <= {$random}; + assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[15:0]; + `else + assign R0_data = ram[reg_R0_addr]; + `endif + +endmodule \ No newline at end of file diff --git a/rtl/BPUTop/array_7.sv b/rtl/BPUTop/array_7.sv new file mode 100644 index 0000000..34da88d --- /dev/null +++ b/rtl/BPUTop/array_7.sv @@ -0,0 +1,82 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module array_7( + input [7:0] R0_addr, + input R0_en, + input R0_clk, + output [23:0] R0_data, + input [7:0] W0_addr, + input W0_en, + input W0_clk, + input [23:0] W0_data, + input [3:0] W0_mask +); + + array_7_ext array_7_ext ( + .R0_addr (R0_addr), + .R0_en (R0_en), + .R0_clk (R0_clk), + .R0_data (R0_data), + .W0_addr (W0_addr), + .W0_en (W0_en), + .W0_clk (W0_clk), + .W0_data (W0_data), + .W0_mask (W0_mask) + ); +endmodule + diff --git a/rtl/BPUTop/array_7_ext.v b/rtl/BPUTop/array_7_ext.v new file mode 100644 index 0000000..8943483 --- /dev/null +++ b/rtl/BPUTop/array_7_ext.v @@ -0,0 +1,53 @@ + +module array_7_ext( + input W0_clk, + input [7:0] W0_addr, + input W0_en, + input [23:0] W0_data, + input [3:0] W0_mask, + input R0_clk, + input [7:0] R0_addr, + input R0_en, + output [23:0] R0_data +); + + reg reg_R0_ren; + reg [7:0] reg_R0_addr; + reg [23:0] ram [255:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 256; initvar = initvar+1) + ram[initvar] = {1 {$random}}; + reg_R0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge R0_clk) + reg_R0_ren <= R0_en; + always @(posedge R0_clk) + if (R0_en) reg_R0_addr <= R0_addr; + always @(posedge W0_clk) + if (W0_en) begin + if (W0_mask[0]) ram[W0_addr][5:0] <= W0_data[5:0]; + if (W0_mask[1]) ram[W0_addr][11:6] <= W0_data[11:6]; + if (W0_mask[2]) ram[W0_addr][17:12] <= W0_data[17:12]; + if (W0_mask[3]) ram[W0_addr][23:18] <= W0_data[23:18]; + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] R0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + R0_random = {$random}; + reg_R0_ren = R0_random[0]; + end + `endif + always @(posedge R0_clk) R0_random <= {$random}; + assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[23:0]; + `else + assign R0_data = ram[reg_R0_addr]; + `endif + +endmodule \ No newline at end of file diff --git a/rtl/BPUTop/array_8.sv b/rtl/BPUTop/array_8.sv new file mode 100644 index 0000000..a829c0a --- /dev/null +++ b/rtl/BPUTop/array_8.sv @@ -0,0 +1,78 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module array_8( + input [6:0] RW0_addr, + input RW0_en, + input RW0_clk, + input RW0_wmode, + input [105:0] RW0_wdata, + output [105:0] RW0_rdata, + input [1:0] RW0_wmask +); + + array_8_ext array_8_ext ( + .RW0_addr (RW0_addr), + .RW0_en (RW0_en), + .RW0_clk (RW0_clk), + .RW0_wmode (RW0_wmode), + .RW0_wdata (RW0_wdata), + .RW0_rdata (RW0_rdata), + .RW0_wmask (RW0_wmask) + ); +endmodule + diff --git a/rtl/BPUTop/array_8_ext.v b/rtl/BPUTop/array_8_ext.v new file mode 100644 index 0000000..05773d4 --- /dev/null +++ b/rtl/BPUTop/array_8_ext.v @@ -0,0 +1,52 @@ + +module array_8_ext( + input RW0_clk, + input [6:0] RW0_addr, + input RW0_en, + input RW0_wmode, + input [1:0] RW0_wmask, + input [105:0] RW0_wdata, + output [105:0] RW0_rdata +); + + reg reg_RW0_ren; + reg [6:0] reg_RW0_addr; + reg [105:0] ram [127:0]; + `ifdef RANDOMIZE_MEM_INIT + integer initvar; + initial begin + #`RANDOMIZE_DELAY begin end + for (initvar = 0; initvar < 128; initvar = initvar+1) + ram[initvar] = {4 {$random}}; + reg_RW0_addr = {1 {$random}}; + end + `endif + integer i; + always @(posedge RW0_clk) + reg_RW0_ren <= RW0_en && !RW0_wmode; + always @(posedge RW0_clk) + if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr; + always @(posedge RW0_clk) + if (RW0_en && RW0_wmode) begin + for (i=0;i<2;i=i+1) begin + if (RW0_wmask[i]) begin + ram[RW0_addr][i*53 +: 53] <= RW0_wdata[i*53 +: 53]; + end + end + end + `ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [127:0] RW0_random; + `ifdef RANDOMIZE_MEM_INIT + initial begin + #`RANDOMIZE_DELAY begin end + RW0_random = {$random, $random, $random, $random}; + reg_RW0_ren = RW0_random[0]; + end + `endif + always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random}; + assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[105:0]; + `else + assign RW0_rdata = ram[reg_RW0_addr]; + `endif + +endmodule \ No newline at end of file diff --git a/rtl/BPUTop/data_16x16.sv b/rtl/BPUTop/data_16x16.sv new file mode 100644 index 0000000..05d16d2 --- /dev/null +++ b/rtl/BPUTop/data_16x16.sv @@ -0,0 +1,95 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +// VCS coverage exclude_file +module data_16x16( + input [3:0] R0_addr, + input R0_en, + input R0_clk, + output [15:0] R0_data, + input [3:0] W0_addr, + input W0_en, + input W0_clk, + input [15:0] W0_data, + input [3:0] W1_addr, + input W1_en, + input W1_clk, + input [15:0] W1_data +); + + reg [15:0] Memory[0:15]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + if (W1_en & 1'h1) + Memory[W1_addr] <= W1_data; + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ + reg [31:0] _RANDOM_MEM; + initial begin + `INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_MEM_INIT + for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin + _RANDOM_MEM = `RANDOM; + Memory[i[3:0]] = _RANDOM_MEM[15:0]; + end + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 16'bx; +endmodule + diff --git a/rtl/BPUTop/data_32x16.sv b/rtl/BPUTop/data_32x16.sv new file mode 100644 index 0000000..642d3e4 --- /dev/null +++ b/rtl/BPUTop/data_32x16.sv @@ -0,0 +1,95 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +// VCS coverage exclude_file +module data_32x16( + input [4:0] R0_addr, + input R0_en, + input R0_clk, + output [15:0] R0_data, + input [4:0] W0_addr, + input W0_en, + input W0_clk, + input [15:0] W0_data, + input [4:0] W1_addr, + input W1_en, + input W1_clk, + input [15:0] W1_data +); + + reg [15:0] Memory[0:31]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + if (W1_en & 1'h1) + Memory[W1_addr] <= W1_data; + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ + reg [31:0] _RANDOM_MEM; + initial begin + `INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_MEM_INIT + for (logic [5:0] i = 6'h0; i < 6'h20; i += 6'h1) begin + _RANDOM_MEM = `RANDOM; + Memory[i[4:0]] = _RANDOM_MEM[15:0]; + end + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 16'bx; +endmodule + diff --git a/rtl/BPUTop/data_mem_0_4x2.sv b/rtl/BPUTop/data_mem_0_4x2.sv new file mode 100644 index 0000000..c2b083b --- /dev/null +++ b/rtl/BPUTop/data_mem_0_4x2.sv @@ -0,0 +1,89 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +// VCS coverage exclude_file +module data_mem_0_4x2( + input [1:0] R0_addr, + input R0_en, + input R0_clk, + output [1:0] R0_data, + input [1:0] W0_addr, + input W0_en, + input W0_clk, + input [1:0] W0_data +); + + reg [1:0] Memory[0:3]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ + reg [31:0] _RANDOM_MEM; + initial begin + `INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_MEM_INIT + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM_MEM = `RANDOM; + Memory[i[1:0]] = _RANDOM_MEM[1:0]; + end + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 2'bx; +endmodule + diff --git a/rtl/BPUTop/data_mem_0_8x3.sv b/rtl/BPUTop/data_mem_0_8x3.sv new file mode 100644 index 0000000..791bbd2 --- /dev/null +++ b/rtl/BPUTop/data_mem_0_8x3.sv @@ -0,0 +1,89 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +// VCS coverage exclude_file +module data_mem_0_8x3( + input [2:0] R0_addr, + input R0_en, + input R0_clk, + output [2:0] R0_data, + input [2:0] W0_addr, + input W0_en, + input W0_clk, + input [2:0] W0_data +); + + reg [2:0] Memory[0:7]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ + reg [31:0] _RANDOM_MEM; + initial begin + `INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_MEM_INIT + for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin + _RANDOM_MEM = `RANDOM; + Memory[i[2:0]] = _RANDOM_MEM[2:0]; + end + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 3'bx; +endmodule + diff --git a/rtl/BPUTop/data_mem_16x12.sv b/rtl/BPUTop/data_mem_16x12.sv new file mode 100644 index 0000000..f6ef378 --- /dev/null +++ b/rtl/BPUTop/data_mem_16x12.sv @@ -0,0 +1,97 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +// VCS coverage exclude_file +module data_mem_16x12( + input [3:0] R0_addr, + input R0_en, + input R0_clk, + output [11:0] R0_data, + input [3:0] R1_addr, + input R1_en, + input R1_clk, + output [11:0] R1_data, + input [3:0] W0_addr, + input W0_en, + input W0_clk, + input [11:0] W0_data, + input [1:0] W0_mask +); + + reg [11:0] Memory[0:15]; + always @(posedge W0_clk) begin + if (W0_en & W0_mask[0]) + Memory[W0_addr][32'h0 +: 6] <= W0_data[5:0]; + if (W0_en & W0_mask[1]) + Memory[W0_addr][32'h6 +: 6] <= W0_data[11:6]; + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ + reg [31:0] _RANDOM_MEM; + initial begin + `INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_MEM_INIT + for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin + _RANDOM_MEM = `RANDOM; + Memory[i[3:0]] = _RANDOM_MEM[11:0]; + end + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 12'bx; + assign R1_data = R1_en ? Memory[R1_addr] : 12'bx; +endmodule + diff --git a/rtl/BPUTop/data_mem_8x4.sv b/rtl/BPUTop/data_mem_8x4.sv new file mode 100644 index 0000000..016d609 --- /dev/null +++ b/rtl/BPUTop/data_mem_8x4.sv @@ -0,0 +1,97 @@ +// Generated by CIRCT firtool-1.62.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +// VCS coverage exclude_file +module data_mem_8x4( + input [2:0] R0_addr, + input R0_en, + input R0_clk, + output [3:0] R0_data, + input [2:0] R1_addr, + input R1_en, + input R1_clk, + output [3:0] R1_data, + input [2:0] W0_addr, + input W0_en, + input W0_clk, + input [3:0] W0_data, + input [1:0] W0_mask +); + + reg [3:0] Memory[0:7]; + always @(posedge W0_clk) begin + if (W0_en & W0_mask[0]) + Memory[W0_addr][32'h0 +: 2] <= W0_data[1:0]; + if (W0_en & W0_mask[1]) + Memory[W0_addr][32'h2 +: 2] <= W0_data[3:2]; + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ + reg [31:0] _RANDOM_MEM; + initial begin + `INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_MEM_INIT + for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin + _RANDOM_MEM = `RANDOM; + Memory[i[2:0]] = _RANDOM_MEM[3:0]; + end + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 4'bx; + assign R1_data = R1_en ? Memory[R1_addr] : 4'bx; +endmodule +